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chastell/art-decomp | kiss/train11_nov.vhd | 1 | 3,530 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train11_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train11_nov;
architecture behaviour of train11_nov is
constant st0: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1000";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st3: std_logic_vector(3 downto 0) := "1001";
constant st4: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "1010";
constant st6: std_logic_vector(3 downto 0) := "0100";
constant st7: std_logic_vector(3 downto 0) := "0110";
constant st8: std_logic_vector(3 downto 0) := "0101";
constant st9: std_logic_vector(3 downto 0) := "0011";
constant st10: std_logic_vector(3 downto 0) := "0111";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st2; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st5; output <= "1";
end if;
when st2 =>
if std_match(input, "01") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "11") then next_state <= st9; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st4; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st5 =>
if std_match(input, "11") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "10") then next_state <= st8; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st9 =>
if std_match(input, "11") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st10; output <= "1";
end if;
when st10 =>
if std_match(input, "10") then next_state <= st10; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 8de624c333b416fce605a507ac21f365 | 0.572521 | 3.232601 | false | false | false | false |
es17m014/vhdl-counter | src/old/vhdl/mux7seg.vhd | 1 | 2,059 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : mux7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Multiplexer 4 inputs, 4 selector and one output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux7seg is
port (
sw_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end mux7seg;
architecture rtl of mux7seg is
component mux44to1 is
port (
digits_i : in std_logic_vector(15 downto 0);
sel_i : in std_logic_vector(1 downto 0);
digit_o : out std_logic_vector(3 downto 0)
);
end component;
component hex7seg is
port(
digit_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0)
);
end component;
signal digits_i : std_logic_vector(15 downto 0);
signal sel_i : std_logic_vector(1 downto 0);
signal digit_i : std_logic_vector(3 downto 0);
begin
digits_i <= X"1234";
ss_sel_o <= not sw_i;
sel_i(1) <= sw_i(2) or sw_i(3);
sel_i(0) <= sw_i(1) or sw_i(3);
dp_o <= '1';
comp1: mux44to1
port map(
digits_i => digits_i,
sel_i => sel_i,
digit_o => digit_i
);
comp2: hex7seg
port map(
digit_i => digit_i,
ss_o => ss_o
);
end rtl; | mit | aafbb76e611520445828db566eda3e25 | 0.44439 | 3.907021 | false | false | false | false |
chastell/art-decomp | kiss/s420_nov.vhd | 1 | 17,549 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_nov is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_nov;
architecture behaviour of s420_nov is
constant s1111111111111111: std_logic_vector(4 downto 0) := "11111";
constant s0000000000000000: std_logic_vector(4 downto 0) := "00000";
constant s0001000000000000: std_logic_vector(4 downto 0) := "00011";
constant s0010000000000000: std_logic_vector(4 downto 0) := "00010";
constant s0011000000000000: std_logic_vector(4 downto 0) := "00101";
constant s0100000000000000: std_logic_vector(4 downto 0) := "00100";
constant s0101000000000000: std_logic_vector(4 downto 0) := "00111";
constant s0110000000000000: std_logic_vector(4 downto 0) := "00110";
constant s0111000000000000: std_logic_vector(4 downto 0) := "01001";
constant s1000000000000000: std_logic_vector(4 downto 0) := "01000";
constant s1001000000000000: std_logic_vector(4 downto 0) := "01011";
constant s1010000000000000: std_logic_vector(4 downto 0) := "01010";
constant s1011000000000000: std_logic_vector(4 downto 0) := "01101";
constant s1100000000000000: std_logic_vector(4 downto 0) := "01100";
constant s1101000000000000: std_logic_vector(4 downto 0) := "01111";
constant s1110000000000000: std_logic_vector(4 downto 0) := "01110";
constant s1111000000000000: std_logic_vector(4 downto 0) := "10111";
constant s0000000100000000: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 28e3063c07f7bcebc24a5f4792e818c4 | 0.564192 | 4.094494 | false | false | false | false |
ibm2030/IBM2030 | ibm2030-cpu.vhd | 1 | 29,455 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: cpu.vhd
-- Creation Date: 22:15:23 2010-06-30
-- Description:
-- Top level of the CPU proper, combining all the various modules
-- including Processor, Storage, Multiplexor and (eventually) Selector(s)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity cpu is
Port (
WX_IND : OUT std_logic_vector(0 to 12);
W_IND_P : OUT std_logic;
X_IND_P : OUT std_logic;
IND_SALS : OUT SALS_Bus;
IND_EX,IND_CY_MATCH,IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P: OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M : OUT STD_LOGIC_VECTOR(0 to 8);
IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG : OUT STD_LOGIC;
IND_LOC_STG : OUT STD_LOGIC;
IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG : OUT STD_LOGIC;
IND_CHK_B_REG : OUT STD_LOGIC;
IND_CHK_STOR_ADDR : OUT STD_LOGIC;
IND_CHK_CTRL_REG : OUT STD_LOGIC;
IND_CHK_ROS_SALS : OUT STD_LOGIC;
IND_CHK_ROS_ADDR : OUT STD_LOGIC;
IND_CHK_STOR_DATA : OUT STD_LOGIC;
IND_CHK_ALU : OUT STD_LOGIC;
IND_SYST : OUT STD_LOGIC;
IND_MAN : OUT STD_LOGIC;
IND_WAIT : OUT STD_LOGIC;
IND_TEST : OUT STD_LOGIC;
IND_LOAD : OUT STD_LOGIC;
SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_LAMP_TEST,SW_DSPLY,SW_STORE,SW_SYS_RST : IN STD_LOGIC;
SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : IN STD_LOGIC;
SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : IN STD_LOGIC;
SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
SW_INTRP_TIMER, SW_CONS_INTRP : IN STD_LOGIC;
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
E_SW : E_SW_BUS_Type;
-- External MPX connections
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
-- Storage (RAM) interface
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- PCH_CONN_ENTRY : IN PCH_CONN;
RDR_1_CONN_EXIT : OUT RDR_CONN;
n1050_CONTROL : OUT CONN_1050;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
DEBUG : INOUT DEBUG_BUS;
USE_MAN_DECODER_PWR : OUT STD_LOGIC;
Clock1ms : IN STD_LOGIC;
N60_CY_TIMER_PULSE : IN STD_LOGIC;
M_CONV_OSC : OUT STD_LOGIC;
SwSlow : in std_logic;
clk : in std_logic);
end cpu;
architecture FMD of cpu is
-- Outputs from UDC1 (5-01 through 5-05)
signal sSALS : SALS_Bus;
signal CTRL : CTRL_REG;
signal T1,T2,T3,T4 : std_logic;
signal SEL_T1, SEL_T3, SEL_T4 : std_logic;
signal P1,P2,P3,P4 : std_logic;
signal A_BUS1, B_BUS : std_logic_vector(0 to 8);
signal CLOCK_START : std_logic;
signal CLOCK_ON : std_logic;
signal STORE_S_REG_RST : std_logic; -- 03DC2
signal CTRL_REG_RST : std_logic; -- 01CB2
signal TO_KEY_SW : std_logic;
signal METERING_OUT : std_logic;
signal GT_1050_TAGS : std_logic;
signal GT_1050_BUS : std_logic;
signal SET_IND_ROSAR : STD_LOGIC;
signal GT_LOCAL_STORAGE : STD_LOGIC;
signal GT_T_REG_TO_MN : STD_LOGIC;
signal GT_CK_TO_MN : STD_LOGIC;
signal N_STACK_MEM_SELECT : STD_LOGIC;
signal WX_CHK : STD_LOGIC;
-- Outputs from UDC2 (5-06 through 5-09C)
signal Z_BUS,R : std_logic_vector(0 to 8);
signal MN : std_logic_vector(0 to 15);
signal CLOCK_OFF : std_logic;
signal A_REG_PC : std_logic;
signal MN_PC : std_logic;
signal Z0_BUS_0 : std_logic;
signal Z_0 : std_logic;
signal N_CTRL_N : std_logic;
signal ALU_CHK_LCH : std_logic;
signal SELECT_CPU_BUMP : std_logic;
signal sMPX_BUS_O : std_logic_vector(0 to 8);
signal P_1050_SEL_OUT : STD_LOGIC;
signal P_1050_SEL_IN : STD_LOGIC;
signal n1050_REQ_IN : STD_LOGIC;
signal n1050_CE_MODE : STD_LOGIC;
signal MPX_OPN_LT_GATE : STD_LOGIC;
signal ADDR_OUT : STD_LOGIC;
-- Outputs from UDC3 (5-10A through 5-14D)
signal A_BUS3 : STD_LOGIC_VECTOR(0 to 8);
signal SEL_WR_CALL : STD_LOGIC := '0';
signal SX1_SHARE_CYCLE : STD_LOGIC := '0';
signal SX2_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_AUX_WR_CALL : STD_LOGIC := '0';
signal SEL_AUX_RD_CALL : STD_LOGIC := '0';
signal SEL_CONV_OSC : STD_LOGIC;
signal SEL_BASIC_CLOCK_OFF : STD_LOGIC;
signal SEL_SHARE_HOLD : STD_LOGIC := '0';
signal SEL_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_CHNL_DATA_XFER : STD_LOGIC := '0';
signal SEL_ROS_REQ : STD_LOGIC := '0';
signal SEL_READ_CALL : STD_LOGIC := '0';
signal SEL_RD_WR_CTRL : STD_LOGIC := '0';
signal SEL_RD_CALL_TO_STP : STD_LOGIC := '0';
signal SEL_CC_ROS_REQ : STD_LOGIC := '0';
signal MAN_DSPLY_GUV_HUV : STD_LOGIC := '0';
signal HSMPX_TRAP : STD_LOGIC := '0';
signal n1050_SEL_O : STD_LOGIC;
signal n1050_INSTALLED : STD_LOGIC;
signal n1050_OP_IN : STD_LOGIC;
-- Inputs to UDC3
signal SEL_DATA_READY : STD_LOGIC;
signal SEL_CHNL_CPU_CLOCK_STOP : STD_LOGIC;
signal RST_SEL_CHNL_DIAG_LCHS : STD_LOGIC;
signal LOAD_REQ_LCH : STD_LOGIC;
signal USE_GR_OR_HR : STD_LOGIC;
signal SX_CHAIN_PULSE_1 : STD_LOGIC;
signal CHK_RST_SW : STD_LOGIC;
signal S : std_logic_vector(0 to 7);
signal sM_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : std_logic;
signal MACH_RST_2A,MACH_RST_2B,MACH_RST_3, MACH_RST_6 : std_logic;
signal CARRY_0 : STD_LOGIC;
signal COMPLEMENT,NTRUE : STD_LOGIC;
signal FT0,FT1,FT2,FT3,FT5,FT6,FT7 : STD_LOGIC;
signal M_ASSM_BUS1, N_ASSM_BUS1 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS2, N_ASSM_BUS2 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS3, N_ASSM_BUS3 : STD_LOGIC_VECTOR(0 to 8);
signal N1050_INTRV_REQ : STD_LOGIC := '0';
signal TT6_POS_ATTN : STD_LOGIC := '0';
-- signal FT2_MPX_OPNL : STD_LOGIC := '0';
signal MPX_METERING_IN,METER_IN_SX1,METER_IN_SX2 : STD_LOGIC;
signal KEY_SW : STD_LOGIC;
signal GT_SWS_TO_WX_PWR : STD_LOGIC;
signal GT_MAN_SET_MN : STD_LOGIC;
signal EXT_TRAP_MASK_ON : STD_LOGIC;
signal MANUAL_STORE,MAN_STOR_OR_DSPLY : STD_LOGIC;
signal RECYCLE_RST : STD_LOGIC;
signal T_REQUEST : STD_LOGIC := '0';
signal MACH_RST_SET_LCH : STD_LOGIC;
signal RST_LOAD : STD_LOGIC;
signal CARRY_0_LCHD,CARRY_1_LCHD : STD_LOGIC;
signal ALU_CHK : STD_LOGIC;
signal CTRL_N,N_CTRL_LM : STD_LOGIC;
signal SX1_RD_CYCLE,SX2_RD_CYCLE : STD_LOGIC;
signal SX1_WR_CYCLE,SX2_WR_CYCLE : STD_LOGIC;
signal GT_DETECTORS_TO_HR : STD_LOGIC;
signal CPU_RD_PWR : STD_LOGIC;
signal XH,XL,XXH : STD_LOGIC;
signal SET_FW : STD_LOGIC;
signal keyboard_data : STD_LOGIC_VECTOR(7 downto 0);
signal keyboard_error : STD_LOGIC;
signal USE_MANUAL_DECODER : STD_LOGIC;
signal sUSE_MAN_DECODER_PWR : STD_LOGIC;
signal LOCAL_STORAGE_CP, MAIN_STORAGE_CP : STD_LOGIC;
signal STACK_RD_WR_CONTROL : STD_LOGIC;
signal H_REG_5_PWR : STD_LOGIC;
signal FORCE_M_REG_123 : STD_LOGIC;
signal N_SEL_SHARE_HOLD : STD_LOGIC;
signal GK,HK : STD_LOGIC_VECTOR(0 to 3);
signal PROT_LOC_CPU_OR_MPX : STD_LOGIC;
signal PROT_LOC_SEL_CHNL : STD_LOGIC;
signal EARLY_M_REG_0 : STD_LOGIC;
signal ODD : STD_LOGIC; -- 06B to 04A
signal SUPPR_A_REG_CHK : STD_LOGIC;
signal STATUS_IN_LCHD : STD_LOGIC;
signal M_REG_0 : STD_LOGIC;
signal SYS_RST_PRIORITY_LCH : STD_LOGIC;
signal STORE_R : STD_LOGIC;
signal SAL_PC : STD_LOGIC;
signal R_REG_PC : STD_LOGIC;
signal N2ND_ERROR_STOP : STD_LOGIC;
signal MEM_WRAP : STD_LOGIC;
signal MACH_RST_PROT : STD_LOGIC;
signal MACH_RST_MPX : STD_LOGIC;
signal GM_WM_DETECTED : STD_LOGIC;
signal FIRST_MACH_CHK_REQ : STD_LOGIC;
signal FIRST_MACH_CHK : STD_LOGIC;
signal DECIMAL : STD_LOGIC;
signal INTRODUCE_ALU_CHK : STD_LOGIC;
signal SERV_IN_LCHD, ADDR_IN_LCHD, OPNL_IN_LCHD : STD_LOGIC;
signal MPX_SHARE_REQ, MPX_INTERRUPT : STD_LOGIC;
signal CS_DECODE_X001 : STD_LOGIC;
signal SX1_INTERRUPT, SX2_INTERRUPT : STD_LOGIC;
signal SX_1_GATE, SX_2_GATE : STD_LOGIC;
signal SX_1_R_W_CTRL, SX_2_R_W_CTRL : STD_LOGIC;
signal SX_2_BUMP_SW_GT : STD_LOGIC;
-- signal FT3_MPX_SHARE_REQ : STD_LOGIC;
signal CONNECT : STD_LOGIC;
signal P_8F_DETECTED : STD_LOGIC;
signal BASIC_CS0 : STD_LOGIC;
signal USE_R : STD_LOGIC;
signal ANY_MACH_CHK : STD_LOGIC;
signal USE_MAIN_MEMORY, USE_LOCAL_MAIN_MEMORY : STD_LOGIC;
signal ALLOW_PROTECT : STD_LOGIC;
signal USE_BASIC_CA_DECO, USE_ALT_CA_DECODER : STD_LOGIC;
signal ALLOW_PC_SALS : STD_LOGIC;
signal SUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal N1401_MODE : STD_LOGIC;
signal MEM_PROTECT_REQUEST : STD_LOGIC;
signal MANUAL_DISPLAY : STD_LOGIC;
signal MAIN_STORAGE : STD_LOGIC;
signal MACH_RST_SET_LCH_DLY : STD_LOGIC;
signal MACH_RST_SW : STD_LOGIC;
signal MACH_CHK_RST : STD_LOGIC;
signal MACH_CHK_PULSE : STD_LOGIC;
signal GT_D_REG_TO_A_BUS : STD_LOGIC;
signal GT_CA_TO_W_REG : STD_LOGIC;
signal DATA_READY : STD_LOGIC;
signal CTRL_REG_CHK : STD_LOGIC;
signal CPU_WRITE_IN_R_REG : STD_LOGIC;
signal CPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal ANY_PRIORITY_LCH : STD_LOGIC;
signal ALLOW_WRITE_DLYD : STD_LOGIC;
signal ALLOW_WRITE : STD_LOGIC;
signal STORE_HR : STD_LOGIC;
signal STORE_GR : STD_LOGIC;
signal SEL_R_W_CTRL : STD_LOGIC;
signal SEL_CHNL_CHK : STD_LOGIC;
signal HR_REG_0_7, GR_REG_0_7 : STD_LOGIC_VECTOR(0 to 7);
signal STORE_BITS : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal HR_REG_P_BIT : STD_LOGIC;
signal GR_REG_P_BIT : STD_LOGIC;
signal GT_DETECTORS_TO_GR : STD_LOGIC;
signal EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : STD_LOGIC;
signal CHANNEL_RD_CALL : STD_LOGIC;
signal MPX_ROS_LCH : STD_LOGIC;
signal CK_SAL_P_BIT_TO_MPX : STD_LOGIC;
signal STG_MEM_SEL : STD_LOGIC;
signal GATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal CLOCK_START_LCH : STD_LOGIC;
signal LOAD_IND : STD_LOGIC;
signal CLOCK_OUT : STD_LOGIC;
signal READ_ECHO_1, READ_ECHO_2, WRITE_ECHO_1, WRITE_ECHO_2 : STD_LOGIC;
signal DIAGNOSTIC_SW : STD_LOGIC;
signal A_BUS, sFI : STD_LOGIC_VECTOR(0 to 8);
begin
firstBit: entity udc1 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
WX_IND => WX_IND,
X_IND_P => X_IND_P,
W_IND_P => W_IND_P,
A_BUS => A_BUS1,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
MPX_BUS => sFI,
S => S,
R => R,
MN => MN,
M_ASSM_BUS => M_ASSM_BUS1,
N_ASSM_BUS => N_ASSM_BUS1,
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_PWR_OFF => SW_POWER_OFF,
SW_LAMP_TEST => SW_LAMP_TEST,
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,SW_B => SW_B,SW_C => SW_C,SW_D => SW_D,
SW_F => SW_F,SW_G => SW_G,SW_H => SW_H,SW_J => SW_J,
SW_AP => SW_AP,SW_BP => SW_BP,SW_CP => SW_CP,SW_DP => SW_DP,
SW_FP => SW_FP,SW_GP => SW_GP,SW_HP => SW_HP,SW_JP => SW_JP,
TO_KEY_SW => TO_KEY_SW,
E_SW => E_SW, -- Main E switch bus
IND_SYST => IND_SYST,
IND_MAN => IND_MAN,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_LOAD => IND_LOAD,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
CARRY_0 => CARRY_0,
CARRY_0_LCHD => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
COMPLEMENT => COMPLEMENT,
NTRUE => NTRUE,
MPX_METERING_IN => MPX_METERING_IN,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
METER_IN_SX1 => METER_IN_SX1,
METER_IN_SX2 => METER_IN_SX2,
KEY_SW => KEY_SW,
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE,
N1050_INTRV_REQ => N1050_INTRV_REQ,
GT_1050_TAGS => GT_1050_TAGS,
GT_1050_BUS => GT_1050_BUS,
TT6_POS_ATTN => TT6_POS_ATTN,
FT2_MPX_OPNL => FT2,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
FT0 => FT0,
FT1 => FT1,
FT2 => FT2,
FT3 => FT3,
FT5 => FT5,
FT6 => FT6,
FT7 => FT7,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
ALU_CHK => ALU_CHK,
CTRL_N => CTRL_N,
N_CTRL_N => N_CTRL_N,
N_CTRL_LM => N_CTRL_LM,
STORE_S_REG_RST => STORE_S_REG_RST,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
LOCAL_STORAGE_CP => LOCAL_STORAGE_CP,
SET_IND_ROSAR => SET_IND_ROSAR,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_TO_MN_REG => GT_T_REG_TO_MN,
GT_CK_TO_MN_REG => GT_CK_TO_MN,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
PROT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
WX_CHK => WX_CHK,
EARLY_M_REG_0 => EARLY_M_REG_0,
ODD => ODD,
XH => XH,
XL => XL,
XXH => XXH,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
M_REG_0 => M_REG_0,
SYS_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
STORE_R => STORE_R,
SAL_PC => SAL_PC,
R_REG_PC => R_REG_PC,
RST_LOAD => RST_LOAD,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
MACH_RST_PROT => MACH_RST_PROT,
MACH_RST_MPX => MACH_RST_MPX,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
GM_WM_DETECTED => GM_WM_DETECTED,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MPX_SHARE_REQ => MPX_SHARE_REQ,
MPX_INTERRUPT => MPX_INTERRUPT,
CS_DECODE_X001 => CS_DECODE_X001,
CLOCK_OFF => CLOCK_OFF,
CONNECT => CONNECT,
P_8F_DETECTED => P_8F_DETECTED,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALU_CHK_LCH => ALU_CHK_LCH,
ALLOW_PROTECT => ALLOW_PROTECT,
ALLOW_PC_SALS => ALLOW_PC_SALS,
USE_R => USE_R,
USE_BASIC_CA_DECODER => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SEL => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STORAGE => MAIN_STORAGE,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WRITE_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
GT_MAN_SET_MN => GT_MAN_SET_MN,
MPX_ROS_LCH => MPX_ROS_LCH,
CTRL_REG_RST => CTRL_REG_RST,
CK_SAL_P_BIT_TO_MPX => CK_SAL_P_BIT_TO_MPX,
CHANNEL_RD_CALL => CHANNEL_RD_CALL,
GTD_CA_BITS => GATED_CA_BITS,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_MAIN_MEMORY => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
SELECT_CPU_BUMP => SELECT_CPU_BUMP,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
CPU_RD_PWR => CPU_RD_PWR,
LOAD_IND => LOAD_IND,
SET_FW => SET_FW,
MACH_RST_SW => MACH_RST_SW,
LOAD_REQ_LCH => LOAD_REQ_LCH,
USE_GR_OR_HR => USE_GR_OR_HR,
SX_CHAIN_PULSE_1 => SX_CHAIN_PULSE_1,
CHK_RST_SW => CHK_RST_SW,
DIAGNOSTIC_SW => DIAGNOSTIC_SW,
MAN_DSPLY_GUV_HUV => MAN_DSPLY_GUV_HUV,
HSMPX_TRAP => HSMPX_TRAP,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SX_1_R_W_CTRL => SX_1_R_W_CTRL,
SX_2_R_W_CTRL => SX_2_R_W_CTRL,
SX_2_BUMP_SW_GT => SX_2_BUMP_SW_GT,
SEL_WR_CALL => SEL_WR_CALL,
SEL_AUX_WR_CALL => SEL_AUX_WR_CALL,
SEL_AUX_RD_CALL => SEL_AUX_RD_CALL,
SEL_T1 => SEL_T1,
SEL_T4 => SEL_T4,
SEL_CONV_OSC => SEL_CONV_OSC,
SEL_BASIC_CLOCK_OFF => SEL_BASIC_CLOCK_OFF,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_CHNL_DATA_XFER => SEL_CHNL_DATA_XFER,
SEL_ROS_REQ => SEL_ROS_REQ,
SEL_READ_CALL => SEL_READ_CALL,
SEL_RD_WR_CTRL => SEL_RD_WR_CTRL,
SEL_RD_CALL_TO_STP => SEL_RD_CALL_TO_STP,
SEL_CHNL_CPU_CLOCK_STOP => SEL_CHNL_CPU_CLOCK_STOP,
RST_SEL_CHNL_DIAG_LCHS => RST_SEL_CHNL_DIAG_LCHS,
SEL_CC_ROS_REQ => SEL_CC_ROS_REQ,
SX1_INTERRUPT => SX1_INTERRUPT,
SX2_INTERRUPT => SX2_INTERRUPT,
SX_1_GATE => SX_1_GATE,
SX_2_GATE => SX_2_GATE,
CLOCK_ON => CLOCK_ON,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_START => CLOCK_START,
CLOCK_START_LCH => CLOCK_START_LCH,
-- UDC1 Debug stuff
DEBUG => DEBUG,
-- End of Debug stuff
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P4 => P4,
CLK => CLK
);
IND_SALS <= sSALS when SW_LAMP_TEST='0' else
( SALS_PN => '1',
SALS_CN => "111111",
SALS_PS => '1',
SALS_PA => '1',
SALS_CH => "1111",
SALS_CL => "1111",
SALS_CM => "111",
SALS_CU => "11",
SALS_CA => "1111",
SALS_CB => "11",
SALS_CK => "1111",
SALS_PK => '1',
SALS_PC => '1',
SALS_CD => "1111",
SALS_CF => "111",
SALS_CG => "11",
SALS_CV => "11",
SALS_CC => "111",
SALS_CS => "1111",
SALS_AA => '1',
SALS_SA => '1',
SALS_AK => '1');
USE_MAN_DECODER_PWR <= sUSE_MAN_DECODER_PWR;
secondBit: entity udc2 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
A_BUS1 => A_BUS,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
E_BUS => E_SW,
M_ASSM_BUS => M_ASSM_BUS2,
N_ASSM_BUS => N_ASSM_BUS2,
S => S,
R => R,
MN => MN,
Sw_Slow => SwSlow,
CLOCK_START => CLOCK_START,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
CLOCK_IN => clk,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_ON => CLOCK_ON,
LAMP_TEST => SW_LAMP_TEST,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
DIAG_SW => DIAGNOSTIC_SW,
CHK_SW_PROC_SW => SW_CHK_SW_PROCESS,
ROS_SCAN => SW_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
CARRY_0_LATCHED => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
ALU_CHK => ALU_CHK,
NTRUE => NTRUE,
COMPLEMENT => COMPLEMENT,
P_CTRL_N => CTRL_N,
N_CTRL_LM => N_CTRL_LM,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
CPU_RD_PWR => CPU_RD_PWR,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHANNEL_RD_CALL,
XH => XH,
XL => XL,
XXH => XXH,
MAN_STOR_PWR => MANUAL_STORE,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW.S_SEL,
CTRL_REG_RST => CTRL_REG_RST,
CLOCK_OFF => CLOCK_OFF,
A_REG_PC => A_REG_PC,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
P_CONNECT => CONNECT,
N_CTRL_N => N_CTRL_N,
ALU_CHK_LCH => ALU_CHK_LCH,
MN_PC => MN_PC,
SET_IND_ROSAR => SET_IND_ROSAR,
N_STACK_MEMORY_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN, -- from 05B
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STORAGE_CP,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
SEL_CPU_BUMP => SELECT_CPU_BUMP,
PROTECT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROT_LOC_SEL_CHNL,
WX_CHK => WX_CHK,
EARLY_M0 => EARLY_M_REG_0,
ODD => ODD,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
STORE_R => STORE_R,
SALS_PC => SAL_PC,
R_REG_PC => R_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
USE_R => USE_R,
USE_MAIN_MEM => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SELECT => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STG => MAIN_STORAGE,
MACH_RST_SW => MACH_RST_SW,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
LOCAL_STG => LOCAL_STORAGE_CP,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WR_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
ALLOW_WRITE => ALLOW_WRITE,
T_REQUEST => T_REQUEST,
P_8F_DETECTED => P_8F_DETECTED,
CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
GATED_CA_BITS => GATED_CA_BITS,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
CARRY_0 => CARRY_0,
ALLOW_PROTECT => ALLOW_PROTECT,
CS_DECODE_X001 => CS_DECODE_X001,
DECIMAL => DECIMAL,
M_REG_0 => M_REG_0,
MACH_RST_PROT => MACH_RST_PROT,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
MPX_ROS_LCH => MPX_ROS_LCH,
FT7 => FT7,
FT6 => FT6,
FT5 => FT5,
FT2 => FT2,
FT0 => FT0,
FT3 => FT3,
MPX_INTERRUPT => MPX_INTERRUPT,
MPX_METERING_IN => MPX_METERING_IN,
STORE_BITS => STORE_BITS,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MACH_RST_MPX => MACH_RST_MPX,
SET_FW => SET_FW,
MPX_SHARE_REQ => MPX_SHARE_REQ,
LOAD_IND => LOAD_IND,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
-- Signals from UDC3
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD, -- from 12D
GK => GK, -- from 11B
HK => HK, -- from 13B
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SEL_CHNL_CHK => SEL_CHNL_CHK,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
GT_HSMPX_INTO_R_REG => '0',
DR_CORR_P_BIT => '0',
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
ADDR_OUT => ADDR_OUT,
-- Indicators
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
IND_CHK_A_REG => IND_CHK_A_REG,
IND_CHK_B_REG => IND_CHK_B_REG,
IND_CHK_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_CHK_CTRL_REG => IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS => IND_CHK_ROS_SALS,
IND_CHK_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_CHK_STOR_DATA => IND_CHK_STOR_DATA,
IND_CHK_ALU => IND_CHK_ALU,
-- Selector & Mpx channels
MPX_BUS_O => sMPX_BUS_O,
MPX_BUS_I => MPX_BUS_I,
MPX_TAGS_O => MPX_TAGS_O,
MPX_TAGS_I => MPX_TAGS_I,
FI => sFI,
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE,
n1050_SEL_O => n1050_SEL_O,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
n1050_INSTALLED => n1050_INSTALLED,
n1050_REQ_IN => n1050_REQ_IN,
n1050_OP_IN => n1050_OP_IN,
n1050_CE_MODE => n1050_CE_MODE,
StorageIn => StorageIn,
StorageOut => StorageOut,
-- UDC2 Debug stuff
DEBUG => open,
SEL_T1 => SEL_T1,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
SEL_T3 => SEL_T3,
Clk => Clk
);
thirdBit : entity udc3 (FMD) port map (
-- Inputs
E_SW_SEL_BUS => E_SW,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
GTD_CA_BITS => GATED_CA_BITS,
Z_BUS => Z_BUS,
GT_1050_TAGS_OUT => GT_1050_TAGS,
GT_1050_BUS_OUT => GT_1050_BUS,
-- PCH_CONN_ENTRY => PCH_CONN_ENTRY,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
n1050_OP_IN => n1050_OP_IN,
SUPPRESS_OUT => FT0,
CK_SAL_P_BIT => CK_SAL_P_BIT_TO_MPX,
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE,
RECYCLE_RESET => RECYCLE_RST,
-- Outputs
A_BUS => A_BUS3,
M_ASSM_BUS => M_ASSM_BUS3,
N_ASSM_BUS => N_ASSM_BUS3,
T_REQUEST => T_REQUEST,
-- RDR_1_CONN_EXIT => RDR_1_CONN_EXIT,
-- n1050_CONTROL => n1050_CONTROL,
N1050_INTRV_REQ => N1050_INTRV_REQ,
TT6_POS_ATTN => TT6_POS_ATTN,
n1050_SEL_O => n1050_SEL_O,
n1050_INSTALLED => n1050_INSTALLED,
n1050_REQ_IN => n1050_REQ_IN,
n1050_CE_MODE => n1050_CE_MODE,
ADDR_OUT => ADDR_OUT,
SerialInput => SerialInput,
SerialOutput => SerialOutput,
-- Clocks
clk => clk,
Clock1ms => Clock1ms,
Clock60Hz => N60_CY_TIMER_PULSE,
-- UDC3 debug
DEBUG => open,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4
);
M_CONV_OSC <= sM_CONV_OSC;
-- Temporary substitutes for UDC3
SEL_CONV_OSC <= P_CONV_OSC; -- 12A
SEL_BASIC_CLOCK_OFF <= not CLOCK_ON and not CLOCK_START_LCH; -- 12A
-- Combining buses
M_ASSM_BUS2 <= M_ASSM_BUS1 or M_ASSM_BUS3;
N_ASSM_BUS2 <= N_ASSM_BUS1 or N_ASSM_BUS3;
A_BUS <= A_BUS1 and A_BUS3;
end FMD;
| gpl-3.0 | fc4ff29d17f75288555158efc3235a61 | 0.623086 | 2.409998 | false | false | false | false |
chastell/art-decomp | kiss/s1494_nov.vhd | 1 | 31,360 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_nov;
architecture behaviour of s1494_nov is
constant s000000: std_logic_vector(5 downto 0) := "000000";
constant s001110: std_logic_vector(5 downto 0) := "000001";
constant s011000: std_logic_vector(5 downto 0) := "101100";
constant s010100: std_logic_vector(5 downto 0) := "100111";
constant s010011: std_logic_vector(5 downto 0) := "111011";
constant s000100: std_logic_vector(5 downto 0) := "100110";
constant s010111: std_logic_vector(5 downto 0) := "110011";
constant s001100: std_logic_vector(5 downto 0) := "010111";
constant s011011: std_logic_vector(5 downto 0) := "110110";
constant s100110: std_logic_vector(5 downto 0) := "010110";
constant s011101: std_logic_vector(5 downto 0) := "011101";
constant s101110: std_logic_vector(5 downto 0) := "000111";
constant s010101: std_logic_vector(5 downto 0) := "101111";
constant s111110: std_logic_vector(5 downto 0) := "000110";
constant s000011: std_logic_vector(5 downto 0) := "111111";
constant s111011: std_logic_vector(5 downto 0) := "000010";
constant s100111: std_logic_vector(5 downto 0) := "001111";
constant s010000: std_logic_vector(5 downto 0) := "010000";
constant s011010: std_logic_vector(5 downto 0) := "111001";
constant s110010: std_logic_vector(5 downto 0) := "001110";
constant s011100: std_logic_vector(5 downto 0) := "110101";
constant s101010: std_logic_vector(5 downto 0) := "100101";
constant s111010: std_logic_vector(5 downto 0) := "111110";
constant s100000: std_logic_vector(5 downto 0) := "100100";
constant s101000: std_logic_vector(5 downto 0) := "111010";
constant s010010: std_logic_vector(5 downto 0) := "000101";
constant s001010: std_logic_vector(5 downto 0) := "111100";
constant s100100: std_logic_vector(5 downto 0) := "101011";
constant s001011: std_logic_vector(5 downto 0) := "110010";
constant s110100: std_logic_vector(5 downto 0) := "101010";
constant s111000: std_logic_vector(5 downto 0) := "010101";
constant s001000: std_logic_vector(5 downto 0) := "011111";
constant s011110: std_logic_vector(5 downto 0) := "110111";
constant s000010: std_logic_vector(5 downto 0) := "011011";
constant s110011: std_logic_vector(5 downto 0) := "000100";
constant s000111: std_logic_vector(5 downto 0) := "110001";
constant s101011: std_logic_vector(5 downto 0) := "010100";
constant s001111: std_logic_vector(5 downto 0) := "111000";
constant s110000: std_logic_vector(5 downto 0) := "101110";
constant s000110: std_logic_vector(5 downto 0) := "101001";
constant s100010: std_logic_vector(5 downto 0) := "001101";
constant s010001: std_logic_vector(5 downto 0) := "111101";
constant s110110: std_logic_vector(5 downto 0) := "001100";
constant s011111: std_logic_vector(5 downto 0) := "110100";
constant s010110: std_logic_vector(5 downto 0) := "101101";
constant s111100: std_logic_vector(5 downto 0) := "001000";
constant s100011: std_logic_vector(5 downto 0) := "011110";
constant s101100: std_logic_vector(5 downto 0) := "011100";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 925d518fdf60791a15d0d3378ac18562 | 0.625829 | 3.830931 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-07B1.vhd | 1 | 4,491 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B1.vhd
-- Creation Date: 11/01/09
-- Description:
-- SAR (MSAR) and SA (Protection Stack Address) registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.PH;
ENTITY SARSA IS
port
(
-- Inputs
M_ASSM_BUS,N_ASSM_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 05B
MACH_RST_SW : IN STD_LOGIC; -- 03D
MACH_RESET_SET_LCH_DLY : IN STD_LOGIC; -- 04B
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
CPU_RD_PWR : IN STD_LOGIC; -- 04D
SEL_RDWR_CTRL : IN STD_LOGIC; -- 12C
GT_MAN_SET_MN : IN STD_LOGIC; -- 03D
CHNL_RD_CALL : IN STD_LOGIC; -- 04D
XH,XL,XXH : IN STD_LOGIC; -- 08C
MAIN_STORAGE_CP : IN STD_LOGIC; -- 08B
MPX_CP : IN STD_LOGIC; -- 08B
-- Outputs
MN, MN_ST3 : OUT STD_LOGIC_VECTOR(0 to 15);
M_P, N_P , M_ST3_P, N_ST3_P: OUT STD_LOGIC;
SA_REG : OUT STD_LOGIC_VECTOR(0 to 7);
EARLY_M0, M_REG_0 : OUT STD_LOGIC;
MACH_RST_PROTECT : OUT STD_LOGIC;
-- Clocks
T1 : IN STD_LOGIC;
SEL_T1 : IN STD_LOGIC
);
END SARSA;
ARCHITECTURE FMD OF SARSA IS
signal LATCH_MN, LATCH_MN_ST3 : STD_LOGIC;
signal sMACH_RST_PROTECT : STD_LOGIC;
signal STACK_ADDR_REG_SET: STD_LOGIC;
signal SA_REG_IN, SA_REG_IN1, SA_REG_IN2 : STD_LOGIC_VECTOR(0 to 7);
signal sMN : STD_LOGIC_VECTOR(0 to 15);
BEGIN
-- Fig 5-07B
sMACH_RST_PROTECT <= MACH_RST_SW; -- AA3H3
MACH_RST_PROTECT <= sMACH_RST_PROTECT;
LATCH_MN <= MACH_RESET_SET_LCH_DLY or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1D4
LATCH_MN_ST3 <= sMACH_RST_PROTECT or (CPU_RD_PWR and T1) or (GT_MAN_SET_MN and MAN_STOR_OR_DSPLY) or (SEL_T1 and not SEL_RDWR_CTRL); -- AA1E4
REG_M: entity work.PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN,sMN(0 to 7)); -- AA1D2
REG_MP: entity PH port map(M_ASSM_BUS(8),LATCH_MN,M_P); -- AA1D2
REG_N: entity work.PHV8 port map(N_ASSM_BUS(0 to 7),LATCH_MN,sMN(8 to 15) ); -- AA1D3
REG_NP: entity PH port map(N_ASSM_BUS(8),LATCH_MN,N_P); -- AA1D3
REG_MST3: entity work.PHV8 port map(M_ASSM_BUS(0 to 7),LATCH_MN_ST3,MN_ST3(0 to 7)); -- AA1D5
REG_MST3P: entity PH port map(M_ASSM_BUS(8),LATCH_MN_ST3,M_ST3_P); -- AA1D5
REG_NST3: entity work.PHV8 port map(N_ASSM_BUS(0 TO 7),LATCH_MN_ST3,MN_ST3(8 to 15)); -- AA1D6
REG_NST3P: entity PH port map(N_ASSM_BUS(8),LATCH_MN_ST3,N_ST3_P); -- AA1D6
STACK_ADDR_REG_SET <= CHNL_RD_CALL or (CPU_RD_PWR and T1) or GT_MAN_SET_MN or sMACH_RST_PROTECT; -- BE3H7
SA_REG_IN1 <= "111" & M_ASSM_BUS(0 to 4) when MAIN_STORAGE_CP='1' else "00000000"; -- PE3J6
SA_REG_IN2 <= XXH & XL & XH & N_ASSM_BUS(0 to 4) when MPX_CP='1' else "00000000"; -- PE3J6
SA_REG_IN <= SA_REG_IN1 or SA_REG_IN2; -- PE3J6
REG_SA: entity work.PHV8 port map(SA_REG_IN,STACK_ADDR_REG_SET,SA_REG); -- PE3J6
MN <= sMN;
EARLY_M0 <= M_ASSM_BUS(0);
M_REG_0 <= sMN(0);
end FMD;
| gpl-3.0 | c8fc9dc7a0c12efccaef9c280b87c527 | 0.619906 | 2.697297 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-04D.vhd | 1 | 6,446 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-04D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Read/Write Storage Controls
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RWStgCntl IS
port
(
-- Inputs
SALS : IN SALS_Bus;
ANY_PRIORITY_PULSE,ANY_PRIORITY_PULSE_2 : IN STD_LOGIC; -- 03A
SEL_SHARE_HOLD : IN STD_LOGIC; -- 12D
G_REG_0_BIT,G_REG_1_BIT : IN STD_LOGIC; -- 05C
N1401_MODE : IN STD_LOGIC; -- 05A
USE_CPU_DECODER : IN STD_LOGIC; -- 05C
USE_MAN_DECODER : IN STD_LOGIC; -- 03D
E_SW_SEL_AUX_STG : IN STD_LOGIC; -- 04C
MEM_SEL : IN STD_LOGIC; -- 03D
ALLOW_WRITE,ALLOW_WRITE_2 : IN STD_LOGIC; -- 03D
SEL_RD_WR_CTRL : IN STD_LOGIC; -- 12C
MAN_STOR_OR_DISPLAY : IN STD_LOGIC; -- 03D
MACH_RST_1 : IN STD_LOGIC; -- 03D
MANUAL_RD_CALL,MANUAL_WR_CALL : IN STD_LOGIC; -- 03D
HSMPX_READ_CALL : IN STD_LOGIC; -- ?
SEL_RD_CALL_TO_STP : IN STD_LOGIC; -- 12C
SELECT_CPU_BUMP : IN STD_LOGIC; -- 08B
-- Outputs
USE_ALT_CU_DECODE : OUT STD_LOGIC; -- 01B
USE_GR_OR_HR : OUT STD_LOGIC; -- 12D,14D
USE_R : OUT STD_LOGIC; -- 06C,03D
CPU_WRITE_IN_R_REG : OUT STD_LOGIC; -- 07A
CPU_WRITE_PWR : OUT STD_LOGIC; -- 03D,12D,03D,05D
COMPUTE : OUT STD_LOGIC; -- 01C
CPU_READ_PWR : OUT STD_LOGIC; -- 07B,03D,05D
FORCE_M_REG_123 : OUT STD_LOGIC; -- 05B,08B
CU_DECODE_UCW : OUT STD_LOGIC; -- 05B
MAIN_STORAGE_CP : OUT STD_LOGIC; -- 07B,05Bm08B
LOCAL_STORAGE_CP : OUT STD_LOGIC; -- 07A
MAIN_STORAGE : OUT STD_LOGIC; -- 03B,06C,04B,06C,07A,08B
EARLY_LOCAL_STG : OUT STD_LOGIC; -- 05D
GT_LOCAL_STG : OUT STD_LOGIC; -- 08B
CHANNEL_RD_CALL : OUT STD_LOGIC; -- 07B
N_MEM_SELECT : OUT STD_LOGIC; -- 07B
RW_CTRL_STACK : OUT STD_LOGIC; -- 07B
-- Clocks
T1 : IN STD_LOGIC;
SEL_T1 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END RWStgCntl;
ARCHITECTURE FMD OF RWStgCntl IS
signal RD_SEL,WR_SEL : STD_LOGIC;
signal CU01,CM0X0 : STD_LOGIC;
signal CU_DECODE_CPU_LOCAL,MAN_SEL_LOCAL : STD_LOGIC;
signal sCU_DECODE_UCW : STD_LOGIC;
signal sMAIN_STORAGE_CP : STD_LOGIC;
signal sGT_LOCAL_STG : STD_LOGIC;
signal sCHANNEL_RD_CALL : STD_LOGIC;
signal sCPU_READ_PWR : STD_LOGIC;
signal sCPU_WRITE_PWR : STD_LOGIC;
signal sUSE_ALT_CU_DECODE : STD_LOGIC;
signal sUSE_R : STD_LOGIC;
signal sEARLY_LOCAL_STG : STD_LOGIC;
BEGIN
-- Fig 5-04D
sCHANNEL_RD_CALL <= (SEL_T1 and not SEL_RD_WR_CTRL) or HSMPX_READ_CALL; -- AD1L5,BE3E4
CHANNEL_RD_CALL <= sCHANNEL_RD_CALL;
RD_SEL <= MANUAL_RD_CALL or (sCPU_READ_PWR and T1) or sCHANNEL_RD_CALL; -- BE3D3,BE3H5,BE3J5
WR_SEL <= (T1 and sCPU_WRITE_PWR and ALLOW_WRITE_2) or MANUAL_WR_CALL or (SEL_RD_CALL_TO_STP or HSMPX_READ_CALL); -- BE3J5,BE3H5
N_MEM_SELECT <= not (not SELECT_CPU_BUMP and (RD_SEL or WR_SEL)); -- BE3H6
-- ?? Note TD not implemented (yet)
RW_LCH: entity work.FLL port map(RD_SEL,WR_SEL,RW_CTRL_STACK); -- BE3J5
sUSE_ALT_CU_DECODE <= not ANY_PRIORITY_PULSE and not sCPU_READ_PWR; -- AB3D2
USE_ALT_CU_DECODE <= sUSE_ALT_CU_DECODE;
CU01 <= not SALS.SALS_CU(0) and SALS.SALS_CU(1); -- AB3E2
USE_GR_OR_HR <= (sUSE_ALT_CU_DECODE and USE_CPU_DECODER and CU01); -- AB3E2,AB3H6-removed??
sUSE_R <= not CU01 and not SEL_SHARE_HOLD; -- AB3D5,AB3H3
USE_R <= sUSE_R;
CM0X0 <= not SALS.SALS_CM(0) and not SALS.SALS_CM(2); -- AB3D6
CPU_WRITE_IN_R_REG <= sUSE_R and CM0X0; -- AB3F2
sCPU_WRITE_PWR <= CM0X0;
CPU_WRITE_PWR <= sCPU_WRITE_PWR;
sCPU_READ_PWR <= (SALS.SALS_CM(0) and not ANY_PRIORITY_PULSE_2) or (SALS.SALS_CM(1) and SALS.SALS_CM(2) and not ANY_PRIORITY_PULSE_2); -- AB3B6,AB3D2
CPU_READ_PWR <= sCPU_READ_PWR;
COMPUTE <= not sCPU_WRITE_PWR and not sCPU_READ_PWR; -- AB3F2
CU_DECODE_CPU_LOCAL <= ((not G_REG_0_BIT or N1401_MODE) and (N1401_Mode or not G_REG_1_BIT) and SALS.SALS_CU(0) and SALS.SALS_CU(1) and USE_CPU_DECODER) or
(not SALS.SALS_CU(0) and SALS.SALS_CU(1) and USE_CPU_DECODER); -- AA1C2,AA1J4 ?? *not* N1401_MODE ??
FORCE_M_REG_123 <= CU_DECODE_CPU_LOCAL; -- AA1H2
sCU_DECODE_UCW <= SALS.SALS_CU(0) and not SALS.SALS_CU(1) and USE_CPU_DECODER; -- AA1C2
CU_DECODE_UCW <= sCU_DECODE_UCW;
MAN_SEL_LOCAL <= USE_MAN_DECODER and E_SW_SEL_AUX_STG; -- AA1C2
sEARLY_LOCAL_STG <= CU_DECODE_CPU_LOCAL or sCU_DECODE_UCW or MAN_SEL_LOCAL; -- AA1C3
EARLY_LOCAL_STG <= sEARLY_LOCAL_STG;
sMAIN_STORAGE_CP <= not sEARLY_LOCAL_STG; -- AA1J2
MAIN_STORAGE_CP <= sMAIN_STORAGE_CP;
-- SELECT_CPU_BUMP <= sEARLY_LOCAL_STG; -- ? Not sure!
sGT_LOCAL_STG <= ((MEM_SEL and not ALLOW_WRITE) and MAN_STOR_OR_DISPLAY) or (T1 and sCPU_READ_PWR) or (SEL_T1 and not SEL_RD_WR_CTRL) or MACH_RST_1; -- AA1C2,AA1J2-removed??,AA1G4
GT_LOCAL_STG <= sGT_LOCAL_STG;
LS_LCH: entity work.PH port map(not sMAIN_STORAGE_CP,sGT_LOCAL_STG,LOCAL_STORAGE_CP); -- AA1F4
MS_LCH: entity work.PH port map(not sEARLY_LOCAL_STG,sGT_LOCAL_STG,MAIN_STORAGE); -- AA1F4
END FMD;
| gpl-3.0 | 0c32fe9675d3d5a7d05fef20a56a6327 | 0.646758 | 2.673579 | false | false | false | false |
chastell/art-decomp | kiss/s510_jed.vhd | 1 | 13,167 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_jed is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_jed;
architecture behaviour of s510_jed is
constant s000000: std_logic_vector(5 downto 0) := "011011";
constant s010010: std_logic_vector(5 downto 0) := "111010";
constant s010011: std_logic_vector(5 downto 0) := "110010";
constant s000100: std_logic_vector(5 downto 0) := "110011";
constant s000001: std_logic_vector(5 downto 0) := "111011";
constant s100101: std_logic_vector(5 downto 0) := "111100";
constant s100100: std_logic_vector(5 downto 0) := "111110";
constant s000010: std_logic_vector(5 downto 0) := "111101";
constant s000011: std_logic_vector(5 downto 0) := "111111";
constant s011100: std_logic_vector(5 downto 0) := "101000";
constant s011101: std_logic_vector(5 downto 0) := "100000";
constant s000111: std_logic_vector(5 downto 0) := "110110";
constant s000101: std_logic_vector(5 downto 0) := "110111";
constant s010000: std_logic_vector(5 downto 0) := "101110";
constant s010001: std_logic_vector(5 downto 0) := "101010";
constant s001000: std_logic_vector(5 downto 0) := "010110";
constant s001001: std_logic_vector(5 downto 0) := "000110";
constant s010100: std_logic_vector(5 downto 0) := "000010";
constant s010101: std_logic_vector(5 downto 0) := "000000";
constant s001010: std_logic_vector(5 downto 0) := "100110";
constant s001011: std_logic_vector(5 downto 0) := "100010";
constant s011000: std_logic_vector(5 downto 0) := "100011";
constant s011001: std_logic_vector(5 downto 0) := "100001";
constant s011010: std_logic_vector(5 downto 0) := "010000";
constant s011011: std_logic_vector(5 downto 0) := "010001";
constant s001100: std_logic_vector(5 downto 0) := "010101";
constant s001101: std_logic_vector(5 downto 0) := "010100";
constant s011110: std_logic_vector(5 downto 0) := "101100";
constant s011111: std_logic_vector(5 downto 0) := "100100";
constant s100000: std_logic_vector(5 downto 0) := "001010";
constant s100001: std_logic_vector(5 downto 0) := "001000";
constant s100010: std_logic_vector(5 downto 0) := "101101";
constant s100011: std_logic_vector(5 downto 0) := "101111";
constant s001110: std_logic_vector(5 downto 0) := "011100";
constant s001111: std_logic_vector(5 downto 0) := "011101";
constant s100110: std_logic_vector(5 downto 0) := "010111";
constant s100111: std_logic_vector(5 downto 0) := "000111";
constant s101000: std_logic_vector(5 downto 0) := "000011";
constant s101001: std_logic_vector(5 downto 0) := "001011";
constant s101010: std_logic_vector(5 downto 0) := "100101";
constant s101011: std_logic_vector(5 downto 0) := "100111";
constant s101100: std_logic_vector(5 downto 0) := "001100";
constant s101101: std_logic_vector(5 downto 0) := "001101";
constant s101110: std_logic_vector(5 downto 0) := "101001";
constant s010110: std_logic_vector(5 downto 0) := "000100";
constant s010111: std_logic_vector(5 downto 0) := "000101";
constant s000110: std_logic_vector(5 downto 0) := "011010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 19adc779b5260a238dd68af044c15aa4 | 0.536189 | 3.970748 | false | false | false | false |
chastell/art-decomp | kiss/s510_hot.vhd | 1 | 15,224 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_hot is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_hot;
architecture behaviour of s510_hot is
constant s000000: std_logic_vector(46 downto 0) := "10000000000000000000000000000000000000000000000";
constant s010010: std_logic_vector(46 downto 0) := "01000000000000000000000000000000000000000000000";
constant s010011: std_logic_vector(46 downto 0) := "00100000000000000000000000000000000000000000000";
constant s000100: std_logic_vector(46 downto 0) := "00010000000000000000000000000000000000000000000";
constant s000001: std_logic_vector(46 downto 0) := "00001000000000000000000000000000000000000000000";
constant s100101: std_logic_vector(46 downto 0) := "00000100000000000000000000000000000000000000000";
constant s100100: std_logic_vector(46 downto 0) := "00000010000000000000000000000000000000000000000";
constant s000010: std_logic_vector(46 downto 0) := "00000001000000000000000000000000000000000000000";
constant s000011: std_logic_vector(46 downto 0) := "00000000100000000000000000000000000000000000000";
constant s011100: std_logic_vector(46 downto 0) := "00000000010000000000000000000000000000000000000";
constant s011101: std_logic_vector(46 downto 0) := "00000000001000000000000000000000000000000000000";
constant s000111: std_logic_vector(46 downto 0) := "00000000000100000000000000000000000000000000000";
constant s000101: std_logic_vector(46 downto 0) := "00000000000010000000000000000000000000000000000";
constant s010000: std_logic_vector(46 downto 0) := "00000000000001000000000000000000000000000000000";
constant s010001: std_logic_vector(46 downto 0) := "00000000000000100000000000000000000000000000000";
constant s001000: std_logic_vector(46 downto 0) := "00000000000000010000000000000000000000000000000";
constant s001001: std_logic_vector(46 downto 0) := "00000000000000001000000000000000000000000000000";
constant s010100: std_logic_vector(46 downto 0) := "00000000000000000100000000000000000000000000000";
constant s010101: std_logic_vector(46 downto 0) := "00000000000000000010000000000000000000000000000";
constant s001010: std_logic_vector(46 downto 0) := "00000000000000000001000000000000000000000000000";
constant s001011: std_logic_vector(46 downto 0) := "00000000000000000000100000000000000000000000000";
constant s011000: std_logic_vector(46 downto 0) := "00000000000000000000010000000000000000000000000";
constant s011001: std_logic_vector(46 downto 0) := "00000000000000000000001000000000000000000000000";
constant s011010: std_logic_vector(46 downto 0) := "00000000000000000000000100000000000000000000000";
constant s011011: std_logic_vector(46 downto 0) := "00000000000000000000000010000000000000000000000";
constant s001100: std_logic_vector(46 downto 0) := "00000000000000000000000001000000000000000000000";
constant s001101: std_logic_vector(46 downto 0) := "00000000000000000000000000100000000000000000000";
constant s011110: std_logic_vector(46 downto 0) := "00000000000000000000000000010000000000000000000";
constant s011111: std_logic_vector(46 downto 0) := "00000000000000000000000000001000000000000000000";
constant s100000: std_logic_vector(46 downto 0) := "00000000000000000000000000000100000000000000000";
constant s100001: std_logic_vector(46 downto 0) := "00000000000000000000000000000010000000000000000";
constant s100010: std_logic_vector(46 downto 0) := "00000000000000000000000000000001000000000000000";
constant s100011: std_logic_vector(46 downto 0) := "00000000000000000000000000000000100000000000000";
constant s001110: std_logic_vector(46 downto 0) := "00000000000000000000000000000000010000000000000";
constant s001111: std_logic_vector(46 downto 0) := "00000000000000000000000000000000001000000000000";
constant s100110: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000100000000000";
constant s100111: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000010000000000";
constant s101000: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000001000000000";
constant s101001: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000100000000";
constant s101010: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000010000000";
constant s101011: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000001000000";
constant s101100: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000000100000";
constant s101101: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000000010000";
constant s101110: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000000001000";
constant s010110: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000000000100";
constant s010111: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000000000010";
constant s000110: std_logic_vector(46 downto 0) := "00000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(46 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----------------------------------------------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "-----------------------------------------------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | f1f14213f3e8b8cc77ffac25d77b8a3d | 0.593471 | 4.522876 | false | false | false | false |
TheMassController/VHDL_experimenting | project/UART/uart_main.vhd | 1 | 2,431 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- A note about parity:
-- 0: odd parity
-- 1: even parity
-- 2: always 0 parity
-- 3: always 1 parity
-- if parity_bit is false, this parameter is ignored
entity uart_main is
generic (
clk_freq : Natural;
baudrate : Natural;
parity_bit_en : boolean;
parity_bit_type : integer range 0 to 3;
bit_count : integer range 5 to 9;
stop_bits_count : integer range 1 to 2
);
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
uart_rx : in STD_LOGIC;
uart_tx : out STD_LOGIC;
send_start : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(8 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(8 DOWNTO 0);
data_ready : out STD_LOGIC;
data_error : out STD_LOGIC;
parity_error : out STD_LOGIC;
send_ready : out STD_LOGIC
);
end uart_main;
architecture Behavioral of uart_main is
begin
transmitter : entity work.uart_transmit
generic map (
baudrate => baudrate,
clk_freq => clk_freq,
parity_bit_en => parity_bit_en,
parity_bit_type => parity_bit_type,
bit_count => bit_count,
stop_bits => stop_bits_count
)
port map (
rst => rst,
clk => clk,
uart_tx => uart_tx,
data_in => data_in,
data_send_start => send_start,
ready => send_ready
);
receiver : entity work.uart_receiv
generic map (
baudrate => baudrate,
clk_freq => clk_freq,
parity_bit_in => parity_bit_en,
parity_bit_in_type => parity_bit_type,
bit_count_in => bit_count,
stop_bits_in => stop_bits_count
)
port map (
rst => rst,
clk => clk,
uart_rx => uart_rx,
received_data => data_out,
data_ready => data_ready,
parity_error => parity_error,
data_error => data_error
);
end Behavioral;
| mit | 21cabfc4f6d8c2efc3501b8f790fc364 | 0.445496 | 4.176976 | false | false | false | false |
mike7c2/befunge_processor | befunge_stack (David Watson's conflicted copy 2014-12-13).vhd | 1 | 2,596 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_stack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED;
entity befunge_stack is
generic(
stack_depth_pow : integer;
word_size : integer
);
port(
clk : in std_logic;
reset : in std_logic;
stack_0_o : out std_logic_vector(word_size-1 downto 0);
stack_1_o : out std_logic_vector(word_size-1 downto 0);
stack_i : in std_logic_vector(word_size-1 downto 0);
pop1 : in std_logic;
pop2 : in std_logic;
push : in std_logic;
swap : in std_logic;
en : in std_logic
);
end befunge_stack;
architecture pc_v1 of befunge_stack is
type stack_type is array ((2**stack_depth_pow)-1 downto 0) of std_logic_vector(word_size-1 downto 0);
signal stack : stack_type;
signal stack_ptr : Unsigned(stack_depth_pow-1 downto 0);
begin
stack_0 <= stack(stack_ptr);
stack_1 <= stack(stack_ptr-1);
process(reset,clk)
variable ptr_incr : integer range(-2 to 1);
begin
if(reset = '1') then
stack_0_o <= (others => '0');
stack_1_o <= (others => '0');
stack <= (others => (others => '0'));
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( pop1 = "1" ) then
ptr_incr := ptr_incr - 1;
elsif ( pop2 = "1" ) then
ptr_incr := ptr_incr - 2;
elsif ( push = "1" ) then
ptr_incr := ptr_incr + 1;
stack(stack_ptr + ptr_incr) <= stack_i;
elsif (swap = "1" ) then
stack(stack_ptr) <= stack(stack_ptr - 1);
stack(stack_ptr - 1) <= stack(stack_ptr);
end if;
stack_ptr <= std_logic_vector(stack_ptr + ptr_incr);
stack_0_o <= stack(stack_ptr + ptr_incr);
stack_1_o <= stack(stack_ptr + ptr_incr - 1);
end if;
end if;
end if;
end process;
| unlicense | 6ba3d555f05ee1c1c5230bcfb60329dc | 0.468413 | 3.595568 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/gen_counter.vhd | 1 | 1,247 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : gen_counter.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Generischer n -bit counter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
architecture rtl of gen_counter is
signal s_count : std_logic_vector(N-1 downto 0) := (others => '0');
begin
process(clk_i, reset_i)
begin
if reset_i = '1' then
s_count <= (others => '0');
elsif rising_edge(clk_i) then
s_count <= s_count + 1;
end if;
end process;
count_o <= s_count;
end rtl;
| mit | 53710da348346d9be5b71868dd270799 | 0.418605 | 4.723485 | false | false | false | false |
es17m014/vhdl-counter | src/tb/io_ctrl_tb.vhd | 1 | 2,922 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : io_ctrl_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Testbench for the io_ctrl module
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 19.11.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity io_ctrl_tb is
end io_ctrl_tb;
architecture sim of io_ctrl_tb is
component io_ctrl is
port (clk_i : in std_logic;
reset_i : in std_logic;
digits_i : in std_logic_vector(13 downto 0);
sw_i : in std_logic_vector(15 downto 0);
pb_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(7 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
swclean_o : out std_logic_vector(15 downto 0);
pbclean_o : out std_logic_vector(3 downto 0));
end component;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal digits_i : std_logic_vector(13 downto 0);
signal sw_i : std_logic_vector(15 downto 0);
signal pb_i : std_logic_vector(3 downto 0);
signal ss_o : std_logic_vector(7 downto 0);
signal ss_sel_o : std_logic_vector(3 downto 0);
signal swclean_o : std_logic_vector(15 downto 0);
signal pbclean_o : std_logic_vector(3 downto 0);
begin
-- Generate system clock 100 MHz
p_clk : process
begin
clk_i <= '0';
wait for 5 ns;
clk_i <= '1';
wait for 5 ns;
end process;
-- Component under test
p_io_ctrl : io_ctrl
port map (
clk_i => clk_i,
reset_i => reset_i,
digits_i => digits_i,
sw_i => sw_i,
pb_i => pb_i,
ss_o => ss_o,
ss_sel_o => ss_sel_o,
swclean_o => swclean_o,
pbclean_o => pbclean_o);
p_sim : process
begin
reset_i <= '1';
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 5 ns;
reset_i <= '0';
-- test debouncing
sw_i <= "1111111111111111";
pb_i <= "1111";
wait for 5 ns;
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 5 ns;
sw_i <= "1111111111111111";
pb_i <= "1111";
wait for 5 ns;
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 5 ns;
sw_i <= "1111111111111111";
pb_i <= "1111";
wait for 10 ms;
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 10 ms;
end process;
end sim; | mit | 8e71c034b168af4cb406c6f991b36941 | 0.481862 | 3.657071 | false | false | false | false |
chastell/art-decomp | kiss/mc_hot.vhd | 1 | 1,802 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mc_hot is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end mc_hot;
architecture behaviour of mc_hot is
constant HG: std_logic_vector(3 downto 0) := "1000";
constant HY: std_logic_vector(3 downto 0) := "0100";
constant FG: std_logic_vector(3 downto 0) := "0010";
constant FY: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-----";
case current_state is
when HG =>
if std_match(input, "0--") then next_state <= HG; output <= "00010";
elsif std_match(input, "-0-") then next_state <= HG; output <= "00010";
elsif std_match(input, "11-") then next_state <= HY; output <= "10010";
end if;
when HY =>
if std_match(input, "--0") then next_state <= HY; output <= "00110";
elsif std_match(input, "--1") then next_state <= FG; output <= "10110";
end if;
when FG =>
if std_match(input, "10-") then next_state <= FG; output <= "01000";
elsif std_match(input, "0--") then next_state <= FY; output <= "11000";
elsif std_match(input, "-1-") then next_state <= FY; output <= "11000";
end if;
when FY =>
if std_match(input, "--0") then next_state <= FY; output <= "01001";
elsif std_match(input, "--1") then next_state <= HG; output <= "11001";
end if;
when others => next_state <= "----"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 4d27ca7a094df9cdaaa438a29b653663 | 0.585461 | 3.419355 | false | false | false | false |
ibm2030/IBM2030 | Gates2030.vhd | 1 | 13,063 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: gates2030.vhd
-- Creation Date:
-- Description:
-- Definitions of the various types of gate, latches and flipflops used in the 2030.
--
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0
-- Initial release
-- Revision 1.1 2012-04-07
-- Add SingleShot (SS) and XilinxIOVector
-- Revise DelayRisingEdgeX implementation
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Gates_package is
-- component PH is port(D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component PHV4 is port(D : in STD_LOGIC_VECTOR(0 to 3); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 3)); end component;
component PHV5 is port(D : in STD_LOGIC_VECTOR(0 to 4); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 4)); end component;
component PHV8 is port(D : in STD_LOGIC_VECTOR(0 to 7); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 7)); end component;
component PHV9 is port(D : in STD_LOGIC_VECTOR(0 to 8); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 8)); end component;
component PHV13 is port(D : in STD_LOGIC_VECTOR(0 to 12); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 12)); end component;
component PHR is port(D,L,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component PHRV is port(D : in STD_LOGIC_VECTOR; L,R: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end component;
component PHSR is port(D,L,S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component FLE is port(S,R,clock: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
-- component FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component FLV is port(S,R: in STD_LOGIC_VECTOR; clock: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end component;
component FLVL is port(S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end component;
--component FLAO is port( S1,S2,S3,R1,R2: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC;
component AR is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component SS is port( Clk : in STD_LOGIC; Count : in integer; D: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DEGLITCH is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DEGLITCH2 is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component DelayRisingEdge is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end component;
component XilinxIOVector is port( I : in STD_LOGIC_VECTOR; T : in STD_LOGIC; O : out STD_LOGIC_VECTOR; IO : inout STD_LOGIC_VECTOR); end component;
end Gates_package;
-- FL is no longer an edge-triggered SR flip-flop
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity FLE is port(S,R,clock: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of FLE is
begin
process (S,R)
begin
if (R='1') then -- Reset takes priority
Q<='0' after 1ns;
elsif (S='1') then
Q<='1' after 1ns;
end if;
end process;
end slt;
-- FLL is a level-triggered SR flip-flop
--LIBRARY ieee;
--USE ieee.std_logic_1164.all;
--entity FLL is port(S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end;
--
--architecture slt of FLL is
--begin
--process(S,R)
--begin
--if (S='1') then -- Set takes priority
-- Q<='1' after 1ns;
--elsif (R='1') then
-- Q<='0' after 1ns;
--end if;
--end process;
--end slt;
-- Simple PH (polarity hold) latch
--LIBRARY ieee;
--USE ieee.std_logic_1164.all;
--entity PH is port( D,L: in STD_LOGIC; signal Q:out STD_LOGIC); end;
--
--architecture slt of PH is
--begin
--process(L,D)
--begin
--if (L='1') then
-- Q <= D;
--end if;
--end process;
--end slt;
-- Simple PH (polarity hold) latch, 4 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV4 is port(D: in STD_LOGIC_VECTOR(0 to 3); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 3)); end;
architecture slt of PHV4 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 5 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV5 is port(D: in STD_LOGIC_VECTOR(0 to 4); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 4)); end;
architecture slt of PHV5 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 8 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV8 is port(D: in STD_LOGIC_VECTOR(0 to 7); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 7)); end;
architecture slt of PHV8 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 9 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV9 is port(D: in STD_LOGIC_VECTOR(0 to 8); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 8)); end;
architecture slt of PHV9 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- Simple PH (polarity hold) latch, 13 bit STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHV13 is port(D: in STD_LOGIC_VECTOR(0 to 12); L: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR(0 to 12)); end;
architecture slt of PHV13 is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,D)
begin
for i in Q'range loop
if (L='1') then
Q(i) <= D1(i);
end if;
end loop;
end process;
end slt;
-- PH Latch with reset
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHR is port( D: in STD_LOGIC; L,R: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of PHR is
begin
process (L,D,R)
begin
if (R='1') then
Q <= '0';
elsif (L='1') then
Q <= D;
end if;
end process;
end slt;
-- PH Latch with reset, STD_LOGIC_VECTOR version
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHRV is port(D: in STD_LOGIC_VECTOR; L,R: in STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end;
architecture slt of PHRV is
alias D1 : STD_LOGIC_VECTOR(Q'range) is D;
begin
process (L,R,D1)
begin
for i in Q'range loop
if (R='1') then
Q(i) <= '0';
elsif (L='1') then
Q(i)<=D1(i);
end if;
end loop;
end process;
end slt;
--- PH Latch with set & reset
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity PHSR is port(D,L,S,R: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of PHSR is
begin
process (L,D,S,R)
begin
if (R='1') then
Q <= '0';
elsif (S='1') then
Q <= '1';
elsif (L='1') then
Q <= D;
end if;
end process;
end slt;
-- Simple FL (SR) flipflops
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity FLV is port( S,R: in STD_LOGIC_VECTOR; signal clock: STD_LOGIC; signal Q:out STD_LOGIC_VECTOR); end;
architecture slt of FLV is
alias S1 : STD_LOGIC_VECTOR(Q'range) is S;
alias R1 : STD_LOGIC_VECTOR(Q'range) is R;
signal S2,R2 : STD_LOGIC_VECTOR(Q'range) := (others=>'0');
begin
process (S1,R1,clock)
begin
if (rising_edge(clock)) then
for i in Q'range loop
if (R(i)/=R2(i) and R(i)='1') then
Q(i) <= '0';
elsif (S(i)/=S2(i) and S(i)='1') then
Q(i) <= '1';
end if;
R2 <= R1;
S2 <= S1;
end loop;
end if;
end process;
end slt;
--LIBRARY ieee;
--USE ieee.std_logic_1164.all;
--entity FLVL is port( S,R: in STD_LOGIC_VECTOR; signal Q:out STD_LOGIC_VECTOR); end;
--
--architecture slt of FLVL is
--alias S1 : STD_LOGIC_VECTOR(Q'range) is S;
--alias R1 : STD_LOGIC_VECTOR(Q'range) is R;
--begin
--process (S1,R1)
--begin
--for i in Q'range loop
--if (S1(i)='1') then -- Set takes priority
-- Q(i)<='1';
--elsif (R1(i)='1') then
-- Q(i)<='0';
--end if;
--end loop;
--end process;
--end slt;
-- Simple 1 cycle delay from line driver (AR)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity AR is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of AR is
signal Q1 : std_logic;
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
Q <= Q1;
Q1 <= D;
end if;
end process;
end slt;
-- Simple single-shot (SS)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity SS is port( Clk : in STD_LOGIC; Count : in integer; D: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of SS is
signal C : integer;
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
if (C = 0) then
if D='1' then
C <= Count;
Q <= '1';
else
Q <= '0';
end if;
else
if (C = 1) then
Q <= '0';
if D='0' then
C <= 0;
end if;
else
C <= C - 1;
Q <= '1';
end if;
end if;
end if;
end process;
end slt;
-- Simple 1 cycle de-glitch
-- LIBRARY ieee;
-- USE ieee.std_logic_1164.all;
-- entity DEGLITCH is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
-- architecture slt of DEGLITCH is
-- signal DD : std_logic_vector(0 to 1);
-- begin
-- process(D,Clk)
-- begin
-- if (rising_edge(Clk)) then
-- DD <= DD(1) & D;
-- end if;
-- end process;
-- with DD select
-- Q <= '0' when "00"|"01", '1' when others ;
-- end slt;
-- Simple 2 cycle de-glitch
-- LIBRARY ieee;
-- USE ieee.std_logic_1164.all;
-- entity DEGLITCH2 is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
-- architecture slt of DEGLITCH2 is
-- signal DD : std_logic_vector(0 to 2);
-- begin
-- process(D,Clk)
-- begin
-- if (rising_edge(Clk)) then
-- DD <= DD(1 to 2) & D;
-- end if;
-- end process;
-- with DD select
-- Q <= '0' when "000"|"001"|"010"|"011", '1' when others ;
-- end slt;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity DelayRisingEdgeX is port( D,Clk: in STD_LOGIC; signal Q:out STD_LOGIC); end;
architecture slt of DelayRisingEdgeX is
signal Q1 : std_logic_vector(1 to 4) := "0000";
begin
process(D,Clk)
begin
if (rising_edge(Clk)) then
if (D='0') then
Q <= '0';
Q1 <= "0000";
else if (D='1') and (Q1="1111") then
Q <= '1';
Q1 <= "1111";
else
Q <= '0';
Q1 <= Q1(2 to 4) & '1';
end if;
end if;
end if;
end process;
end slt;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity XilinxIOVector is port( I : in STD_LOGIC_VECTOR(0 to 8); T : in STD_LOGIC; O : out STD_LOGIC_VECTOR(0 to 8); IO : inout STD_LOGIC_VECTOR(0 to 8)); end;
architecture slt of XilinxIOVector is
component IOBUF port (I, T: in std_logic; O: out std_logic; IO: inout std_logic); end component;
begin
word_generator: for b in 0 to 8 generate
begin
U1: IOBUF port map (I => I(b), T => T, O => O(b), IO => IO(b));
end generate;
end slt;
package body Gates_package is
-- Variable width AND-OR multiplexor component
function mux(sel : in STD_LOGIC; D : in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias D2:STD_LOGIC_VECTOR(1 to D'LENGTH) is D;
variable Q : STD_LOGIC_VECTOR(1 to D'LENGTH);
begin
if (sel = '1') then
Q := D;
else
Q := (others=>'0');
end if;
return Q;
end function mux;
function EvenParity(v : in STD_LOGIC_VECTOR) return STD_LOGIC is
variable p : STD_LOGIC;
begin
p := '1';
for m in v'range loop
p := p xor v(m);
end loop;
return p;
end;
end Gates_package;
| gpl-3.0 | cb8b074c5c1bf1b4c3c3d042f0e78e06 | 0.639593 | 2.724864 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-10C.vhd | 1 | 17,493 | ---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10C.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console data latches and gating
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY n1050_DATA IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type; -- 04CE1
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03DA3
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02BA3
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02AE6
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05CA2
XLATE_UC : IN STD_LOGIC; -- 09C
WR_LCH : IN STD_LOGIC; -- 09CD2 aka WRITE_LCH
RUN : IN STD_LOGIC; -- 09CE6
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
-- TT4_POS_HOME_STT : IN STD_LOGIC; -- 10DD5
RD_OR_RD_INQ : IN STD_LOGIC; -- 09CC5
W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 08BE3
CLOCK_1 : IN STD_LOGIC; -- 10AA5
PCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
GT_1050_BUS_OUT, GT_1050_TAGS_OUT : IN STD_LOGIC; -- 04CE6
n1050_OP_IN : IN STD_LOGIC; -- 10BC5
SET_SHIFT_LCH : IN STD_LOGIC; -- 09CD6
TA_REG_SET : IN STD_LOGIC; -- 10BB2
RST_ATTACH : IN STD_LOGIC; -- 10BC2
n1050_OPER : IN STD_LOGIC; -- 10DE4
READ_INQ : IN STD_LOGIC; -- 09CE6
RD_SHARE_REQ_LCH : IN STD_LOGIC; -- 09CC6
READ : IN STD_LOGIC; -- 09CE6
WRITE_MODE : IN STD_LOGIC; -- 09CFD2
RESTORE : IN STD_LOGIC; -- 10BD2
OUTPUT_SEL_AND_READY : IN STD_LOGIC; -- 10DD4
SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5
UC_CHARACTER, LC_CHARACTER : IN STD_LOGIC; -- 09CD2
-- Z_BUS_0, Z_BUS_3 : IN STD_LOGIC; -- 06BDX
-- TT3_POS_1050_OPER : IN STD_LOGIC; -- 10DD4
TA_REG_POS_6_ATTN_RST : IN STD_LOGIC; -- 10BE3
PCH_BITS : IN STD_LOGIC_VECTOR(0 to 6);
-- CE controls
CE_GT_TA_OR_TE : IN STD_LOGIC;
CE_DATA_ENTER_GT : IN STD_LOGIC;
CE_TE_DECODE : IN STD_LOGIC;
CE_RUN_MODE : IN STD_LOGIC; -- 10DB3
n1050_CE_MODE : IN STD_LOGIC;
CE_BITS : IN STD_LOGIC_VECTOR(0 to 7); -- 10DA1
-- Outputs
A_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 07CA6
DATA_REG_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 09C
TAGS_OUT : OUT STD_LOGIC_VECTOR(0 to 7); -- 10BB1 11AA2
NPL_BITS : OUT STD_LOGIC_VECTOR(0 to 7);
PTT_BITS : OUT STD_LOGIC_VECTOR(0 to 6); -- Output to printer ("RDR")
TE_LCH : OUT STD_LOGIC;
WR_SHARE_REQ : OUT STD_LOGIC; -- 10BD5
ALLOW_STROBE : OUT STD_LOGIC; -- 09CD4 09CE1
GT_WRITE_REG : OUT STD_LOGIC; -- 10DB4
FORCE_SHIFT_CHAR : OUT STD_LOGIC; -- 10DB4
FORCE_LC_SHIFT : OUT STD_LOGIC; -- 10DB4
SET_LOWER_CASE : OUT STD_LOGIC; -- 09CD4 09CB5
n1050_INTRV_REQ : OUT STD_LOGIC; -- 10BD4 04AA4
READY_SHARE : OUT STD_LOGIC; -- 10BD4 09CB4
TT5_POS_INTRV_REQ : OUT STD_LOGIC; -- 10DC4
-- Buses
TT_BUS: INOUT STD_LOGIC_VECTOR(0 to 7);
GTD_TT3: OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_DATA;
ARCHITECTURE FMD OF n1050_DATA IS
type ConversionAtoE is array(0 to 255) of STD_LOGIC_VECTOR(0 to 7);
signal ASCII_TO_EBCDIC : ConversionAtoE :=
(
character'Pos(cr) => "00010101",
character'Pos(lf) => "00100101",
character'Pos(' ') => "01000000",
character'Pos('.') => "01001011",
character'Pos('<') => "01001100",
character'Pos('(') => "01001101",
character'Pos('+') => "01001110",
character'Pos('&') => "01010000",
character'Pos('$') => "01011011",
character'Pos(')') => "01011101",
character'Pos(';') => "01011110",
character'Pos('-') => "01100000",
character'Pos('/') => "01100001",
character'Pos(',') => "01101011",
character'Pos('%') => "01101100",
character'Pos('>') => "01101110",
character'Pos('?') => "01101111",
character'Pos(':') => "01111010",
character'Pos('#') => "01111011",
character'Pos('@') => "01111100",
character'Pos('0') => "11110000", character'Pos('1') => "11110001", character'Pos('2') => "11110010",
character'Pos('3') => "11110011", character'Pos('4') => "11110100",
character'Pos('5') => "11110101", character'Pos('6') => "11110110", character'Pos('7') => "11110111",
character'Pos('8') => "11111000", character'Pos('9') => "11111001",
character'Pos('A') => "11000001", character'Pos('B') => "11000010", character'Pos('C') => "11000011",
character'Pos('D') => "11000100", character'Pos('E') => "11000101", character'Pos('F') => "11000110",
character'Pos('G') => "11000111", character'Pos('H') => "11001000", character'Pos('I') => "11001001",
character'Pos('J') => "11010001", character'Pos('K') => "11010010", character'Pos('L') => "11010011",
character'Pos('M') => "11010100", character'Pos('N') => "11010101", character'Pos('O') => "11010110",
character'Pos('P') => "11010111", character'Pos('Q') => "11011000", character'Pos('R') => "11011001",
character'Pos('S') => "11100010", character'Pos('T') => "11100011", character'Pos('U') => "11100100",
character'Pos('V') => "11100101", character'Pos('W') => "11100110", character'Pos('X') => "11100111",
character'Pos('Y') => "11101000", character'Pos('Z') => "11101001",
character'Pos('a') => "10000001", character'Pos('b') => "10000010", character'Pos('c') => "10000011",
character'Pos('d') => "10000100", character'Pos('e') => "10000101", character'Pos('f') => "10000110",
character'Pos('g') => "10000111", character'Pos('h') => "10001000", character'Pos('i') => "10001001",
character'Pos('j') => "10010001", character'Pos('k') => "10010010", character'Pos('l') => "10010011",
character'Pos('m') => "10010100", character'Pos('n') => "10010101", character'Pos('o') => "10010110",
character'Pos('p') => "10010111", character'Pos('q') => "10011000", character'Pos('r') => "10011001",
character'Pos('s') => "10100010", character'Pos('t') => "10100011", character'Pos('u') => "10100100",
character'Pos('v') => "10100101", character'Pos('w') => "10100110", character'Pos('x') => "10100111",
character'Pos('y') => "10101000", character'Pos('z') => "10101001",
others => "01101111");
type ConversionEtoA is array(0 to 255) of character;
signal EBCDIC_TO_ASCII : ConversionEtoA :=
(
2#00010101# => cr,
2#00100101# => lf,
2#01000000# => ' ',
2#01001011# => '.',
2#01001100# => '<',
2#01001101# => '(',
2#01001110# => '+',
2#01001111# => '|',
2#01010000# => '&',
2#01011010# => '!',
2#01011011# => '$',
2#01011100# => '*',
2#01011101# => ')',
2#01011110# => ';',
2#01011111# => '~',
2#01100000# => '-',
2#01100001# => '/',
2#01101011# => ',',
2#01101100# => '%',
2#01101101# => '_',
2#01101110# => '>',
2#01101111# => '?',
2#01111010# => ':',
2#01111011# => '#',
2#01111100# => '@',
2#01111101# => ''',
2#01111110# => '=',
2#01111111# => '"',
2#11110000# => '0', 2#11110001# => '1', 2#11110010# => '2', 2#11110011# => '3', 2#11110100# => '4',
2#11110101# => '5', 2#11110110# => '6', 2#11110111# => '7', 2#11111000# => '8', 2#11111001# => '9',
2#11000001# => 'A', 2#11000010# => 'B', 2#11000011# => 'C', 2#11000100# => 'D', 2#11000101# => 'E',
2#11000110# => 'F', 2#11000111# => 'G', 2#11001000# => 'H', 2#11001001# => 'I',
2#11010001# => 'J', 2#11010010# => 'K', 2#11010011# => 'L', 2#11010100# => 'M', 2#11010101# => 'N',
2#11010110# => 'O', 2#11010111# => 'P', 2#11011000# => 'Q', 2#11011001# => 'R',
2#11100010# => 'S', 2#11100011# => 'T', 2#11100100# => 'U', 2#11100101# => 'V', 2#11100110# => 'W',
2#11100111# => 'X', 2#11101000# => 'Y', 2#11101001# => 'Z',
2#10000001# => 'a', 2#10000010# => 'b', 2#10000011# => 'c', 2#10000100# => 'd', 2#10000101# => 'e',
2#10000110# => 'f', 2#10000111# => 'g', 2#10001000# => 'h', 2#10001001# => 'i',
2#10010001# => 'j', 2#10010010# => 'k', 2#10010011# => 'l', 2#10010100# => 'm', 2#10010101# => 'n',
2#10010110# => 'o', 2#10010111# => 'p', 2#10011000# => 'q', 2#10011001# => 'r',
2#10100010# => 's', 2#10100011# => 't', 2#10100100# => 'u', 2#10100101# => 'v', 2#10100110# => 'w',
2#10100111# => 'x', 2#10101000# => 'y', 2#10101001# => 'z',
others => '?');
signal sGT_1050_BUS_OUT, sGT_1050_TAGS_OUT : STD_LOGIC;
signal sSET_LOWER_CASE : STD_LOGIC;
signal sTE_LCH : STD_LOGIC;
signal sSET_LOW_CASE : STD_LOGIC;
signal sDATA_REG : STD_LOGIC_VECTOR(0 to 7);
signal sNPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal GT_1050_BUS_TO_A, GT_1050_TAGS_TO_A : STD_LOGIC;
signal sTAGS_OUT : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_LATCH : STD_LOGIC;
signal DATA_REG_IN : STD_LOGIC_VECTOR(0 to 7);
signal TI_P_BIT : STD_LOGIC;
signal sPTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal sGTD_TT3 : STD_LOGIC;
signal CE_TE_LCH_SET : STD_LOGIC;
signal TE_LCH_SET, TE_LCH_RESET : STD_LOGIC;
signal sGT_WRITE_REG : STD_LOGIC;
signal WR_SHARE_REQ_SET, WR_SHARE_REQ_RESET,sWR_SHARE_REQ : STD_LOGIC;
signal ALLOW_STROBE_SET, ALLOW_STROBE_RESET, sALLOW_STROBE : STD_LOGIC;
signal SHIFT_SET, SHIFT_RESET : STD_LOGIC;
signal sSHIFT : STD_LOGIC := '0';
signal INTRV_REQ_SET, INTRV_REQ_RESET, sINTRV_REQ : STD_LOGIC;
signal n1050_INTRV_REQ_RESET : STD_LOGIC;
signal NOT_OPER_RESET : STD_LOGIC;
signal NOT_OPER : STD_LOGIC := '0';
signal RDY_SHARE_SET, RDY_SHARE_RESET, sRDY_SHARE : STD_LOGIC;
signal CancelCode : STD_LOGIC;
signal NOT_n1050_OPER : STD_LOGIC;
BEGIN
-- Fig 5-10C
GT_1050_BUS_TO_A <= (E_SW_SEL_BUS.TI_SEL and USE_MANUAL_DECODER) or
(USE_ALT_CA_DECODER and not GTD_CA_BITS(0) and GTD_CA_BITS(1) and GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AB3C7 AA=1 CA=0111
GT_1050_TAGS_TO_A <= (E_SW_SEL_BUS.TT_SEL and USE_MANUAL_DECODER) or
(USE_BASIC_CA_DECO and not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3)); -- AA2C6 AA=0 CA=0001
A_REG_BUS <= not(((sNPL_BITS & TI_P_BIT) and (0 to 8=>GT_1050_BUS_TO_A)) or ((TT_BUS & '0') and (0 to 8=>GT_1050_TAGS_TO_A))); -- AC2E2 - Note: Inverted
DATA_REG_PH: PHV8 port map(D=>DATA_REG_IN,L=>DATA_REG_LATCH,Q=>sDATA_REG); -- AC3B2
DATA_REG_BUS <= sDATA_REG;
DATA_REG_LATCH <= (CE_DATA_ENTER_GT and CE_TE_DECODE) or (RD_OR_RD_INQ and W_TIME) or (T3 and sGT_1050_BUS_OUT) or not RUN; -- AC3P5
TAGS_OUT <= DATA_REG_IN; -- ?
sGT_1050_BUS_OUT <= GT_1050_BUS_OUT; -- AC2D6
sGT_1050_TAGS_OUT <= GT_1050_TAGS_OUT; -- AC2M4
DATA_REG_IN <= (Z_BUS(0 to 7) and (0 to 7=>(sGT_1050_BUS_OUT or sGT_1050_TAGS_OUT)))
or (CE_BITS and (0 to 7=>CE_GT_TA_OR_TE))
or (('0' & PCH_BITS) and (0 to 7=>(CLOCK_1 and PCH_1_CLUTCH))); -- AC2B4 AC2H6 AC2M6 AC2M2
sGTD_TT3 <= TT_BUS(3) and n1050_CE_MODE; -- AC2H5 AC2L4
GTD_TT3 <= sGTD_TT3;
TT_BUS(7) <= EVENPARITY(sDATA_REG(1 to 7)) and WR_LCH and RUN and not TT_BUS(0); -- AC2E4 AC2J2
-- CancelCode <= '1' when sDATA_REG(1 to 7)="1100000" else '0'; -- DATA_REG=X1100000
CancelCode <= '1' when sDATA_REG(1 to 7)="0010101" else '0'; -- DATA_REG (ASCII) = 15 = ^U
TT_BUS(0) <= CancelCode and PROCEED_LCH and TT_BUS(4); -- AL2F5 AC2D6
-- The following converts the card code CBA8421 on the DATA_REG bus to EBCDIC
-- C P P P P
-- B 0 0 1 1
-- A 0 1 0 1
-- =====================
-- 0 =40 @=7C -=60 &=50
-- 1 1=F1 /=61 j=91 a=81
-- 2 2=F2 s=A2 k=92 b=82
-- 3 3=F3 t=A3 l=93 c=83
-- 4 4=F4 u=A4 m=94 d=84
-- 5 5=F5 v=A5 n=95 e=85
-- 6 6=F6 w=A6 o=96 f=86
-- 7 7=F7 x=A7 p=97 g=87
-- 8 8=F8 y=A8 q=98 h=88
-- 9 9=F9 z=A9 r=99 i=89
-- A 0=FA CAN
-- B #=7B ,=6B $=5B .=4B
-- C
-- D CR
-- E UC EOB LC
-- F
-- For the purposes of this project, this will convert ASCII on CBA8421 into EBCDIC in MPL
-- sNPL_BITS(0) <= 0; -- AC3J2
-- sNPL_BITS(1) <= 0; -- AC3J2
-- sNPL_BITS(2) <= 0; -- AC3K2
-- sNPL_BITS(3) <= 0; -- AC3H2
-- sNPL_BITS(4) <= 0; -- AC3H2
-- sNPL_BITS(5) <= 0; -- AC3K2
-- sNPL_BITS(6) <= 0; -- AC3J2
-- sNPL_BITS(7) <= 0; -- AC3J2
sNPL_BITS <= ASCII_TO_EBCDIC(Conv_Integer(sDATA_REG));
-- sNPL_BITS <= STD_LOGIC_VECTOR(to_unsigned(Conv_Integer(sDATA_REG),8)); -- * * Temporary debug - no translation
NPL_BITS <= sNPL_BITS;
TI_P_BIT <= EVENPARITY(sNPL_BITS(0 to 7)); -- AC2G4
-- The following converts EBCDIC on the DATA_REG bus to card code CBA8421
-- For the purposes of this project, this will convert EBCDIC in DATA_REG into ASCII in PTT
-- sPTT_BIT_C <= EVEN_PARITY(...); -- C AC3G4
-- sPTT_BIT_B <= 0; -- AC3H2
-- sPTT_BIT_A <= 0; -- AC3K2
-- sPTT_BIT_8 <= 0; -- AC3G2
-- sPTT_BIT_4 <= 0; -- AC3G2
-- sPTT_BIT_2 <= 0; -- AC3G2
-- sPTT_BIT_1 <= 0; -- AC3G2
sPTT_BITS <= STD_LOGIC_VECTOR(to_unsigned(Character'Pos(EBCDIC_TO_ASCII(Conv_Integer(sDATA_REG))),7));
PTT_BITS <= sPTT_BITS;
CE_TE_LCH_SET <= (CE_DATA_ENTER_GT and CE_TE_DECODE) and n1050_OP_IN and CLOCK_1; -- AC2D7 AC2L6 ?? Ignore NOT in AC2M4
TE_LCH_SET <= CE_TE_LCH_SET or (CE_RUN_MODE and CE_TE_DECODE) or (sGT_1050_BUS_OUT and T4); -- AC2J7
sGT_WRITE_REG <= (Z_TIME and sALLOW_STROBE and not sSHIFT); -- AC2C6
GT_WRITE_REG <= sGT_WRITE_REG; -- AC2M4 AC2H6
TE_LCH_RESET <= sSET_LOWER_CASE or sGT_WRITE_REG;
TE_LCH_FL: entity FLL port map(S=>TE_LCH_SET,R=>TE_LCH_RESET,Q=>sTE_LCH); -- AC2B6
TE_LCH <= sTE_LCH;
WR_SHARE_REQ_SET <= not n1050_RST_LCH and W_TIME and WR_LCH and not sTE_LCH;
WR_SHARE_REQ_RESET <= RST_ATTACH or SHARE_REQ_RST;
WR_SHARE_REQ_FL: entity FLL port map(S=>WR_SHARE_REQ_SET,R=>WR_SHARE_REQ_RESET,Q=>sWR_SHARE_REQ); -- AC2K5 AC2D6
WR_SHARE_REQ <= sWR_SHARE_REQ;
ALLOW_STROBE_SET <= RDR_1_CLUTCH and Y_TIME and sTE_LCH;
ALLOW_STROBE_RESET <= sSET_LOWER_CASE or (Y_TIME and not RDR_1_CLUTCH) or X_TIME;
ALLOW_STROBE_FL: entity FLL port map(S=>ALLOW_STROBE_SET,R=>ALLOW_STROBE_RESET,Q=>sALLOW_STROBE); -- AC2B6
ALLOW_STROBE <= sALLOW_STROBE;
SHIFT_SET <= (n1050_CE_MODE and SET_SHIFT_LCH) or (SET_SHIFT_LCH and sTE_LCH and Y_TIME);
SHIFT_RESET <= X_TIME or sSET_LOWER_CASE;
SHIFT_FL: entity FLL port map(S=>SHIFT_SET,R=>SHIFT_RESET,Q=>sSHIFT); -- AC2B6
FORCE_SHIFT_CHAR <= (UC_CHARACTER and Z_TIME and sSHIFT) or (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2C6
FORCE_LC_SHIFT <= (sSHIFT and Z_TIME and LC_CHARACTER); -- AC2D6 ?? not?
sSET_LOWER_CASE <= TA_REG_SET or RST_ATTACH; -- AC2C6 AC2D6
SET_LOWER_CASE <= sSET_LOWER_CASE;
INTRV_REQ_SET <= (not n1050_OPER and READ_INQ and not RD_SHARE_REQ_LCH)
or (not RD_SHARE_REQ_LCH and READ and (not TT_BUS(1) or not TT_BUS(3))) -- AC2G6 AC2H5
or ( WRITE_MODE
and not RESTORE
and not Z_TIME
and not TA_REG_SET
and (not TT_BUS(3) or not OUTPUT_SEL_AND_READY)
and (not CE_DATA_ENTER_GT or not n1050_CE_MODE)); -- AC2E5 AC2K7
INTRV_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH; -- AC2H5 AC2H3
INTRV_REQ_FL: entity FLL port map(S=>INTRV_REQ_SET,R=>INTRV_REQ_RESET,Q=>sINTRV_REQ); -- AC2G6 AC2H3
TT5_POS_INTRV_REQ <= sINTRV_REQ;
n1050_INTRV_REQ_RESET <= n1050_CE_MODE or (Z_BUS(0) and GT_1050_TAGS_OUT) or (GT_1050_TAGS_OUT and Z_BUS(3)) or RST_ATTACH or sRDY_SHARE;
n1050_INTRV_REQ_FL: entity FLL port map(S=>sINTRV_REQ,R=>n1050_INTRV_REQ_RESET,Q=>n1050_INTRV_REQ); -- AC2K3 AC2H4
NOT_OPER_RESET <= RUN or sRDY_SHARE;
NOT_n1050_OPER <= not n1050_OPER;
NOT_OPER_FL: entity FLL port map(S=>NOT_n1050_OPER,R=>NOT_OPER_RESET,Q=>NOT_OPER); -- AC2G5 ?? Set input inverted
RDY_SHARE_SET <= not sINTRV_REQ and TT_BUS(3) and NOT_OPER; -- AC2J7
RDY_SHARE_RESET <= INTRV_REQ_RESET or RUN or TA_REG_POS_6_ATTN_RST;
RDY_SHARE_FL: entity FLL port map(S=>RDY_SHARE_SET,R=>RDY_SHARE_RESET,Q=>sRDY_SHARE); -- AC2F6 AC2E5
READY_SHARE <= sRDY_SHARE;
with DEBUG.Selection select
DEBUG.Probe <=
sDATA_REG(0) when 0,
sDATA_REG(1) when 1,
sDATA_REG(2) when 2,
sDATA_REG(3) when 3,
sDATA_REG(4) when 4,
sDATA_REG(5) when 5,
sDATA_REG(6) when 6,
sDATA_REG(7) when 7,
sNPL_BITS(0) when 8,
sNPL_BITS(1) when 9,
sNPL_BITS(2) when 10,
sNPL_BITS(3) when 11,
sNPL_BITS(4) when 12,
sNPL_BITS(5) when 13,
sNPL_BITS(6) when 14,
sNPL_BITS(7) when 15;
END FMD;
| gpl-3.0 | fb5b7185212f33e503083183c110cbb9 | 0.606986 | 2.595786 | false | false | false | false |
chastell/art-decomp | kiss/dk27_hot.vhd | 1 | 2,442 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_hot;
architecture behaviour of dk27_hot is
constant START: std_logic_vector(6 downto 0) := "1000000";
constant state6: std_logic_vector(6 downto 0) := "0100000";
constant state2: std_logic_vector(6 downto 0) := "0010000";
constant state5: std_logic_vector(6 downto 0) := "0001000";
constant state3: std_logic_vector(6 downto 0) := "0000100";
constant state4: std_logic_vector(6 downto 0) := "0000010";
constant state7: std_logic_vector(6 downto 0) := "0000001";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "-------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | fb2f61cf9f00c1d95e61fcc1bf4ce8b2 | 0.597052 | 3.372928 | false | false | false | false |
chastell/art-decomp | kiss/s1a_rnd.vhd | 1 | 11,806 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1a_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1a_rnd;
architecture behaviour of s1a_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st1: std_logic_vector(4 downto 0) := "00010";
constant st2: std_logic_vector(4 downto 0) := "11011";
constant st5: std_logic_vector(4 downto 0) := "11110";
constant st3: std_logic_vector(4 downto 0) := "11111";
constant st4: std_logic_vector(4 downto 0) := "10001";
constant st6: std_logic_vector(4 downto 0) := "10110";
constant st7: std_logic_vector(4 downto 0) := "01011";
constant st12: std_logic_vector(4 downto 0) := "01111";
constant st13: std_logic_vector(4 downto 0) := "00001";
constant st8: std_logic_vector(4 downto 0) := "10000";
constant st11: std_logic_vector(4 downto 0) := "11010";
constant st15: std_logic_vector(4 downto 0) := "11000";
constant st9: std_logic_vector(4 downto 0) := "01000";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st14: std_logic_vector(4 downto 0) := "01001";
constant st16: std_logic_vector(4 downto 0) := "00110";
constant st17: std_logic_vector(4 downto 0) := "11100";
constant st18: std_logic_vector(4 downto 0) := "00011";
constant st19: std_logic_vector(4 downto 0) := "10111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "000000";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "000000";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "000000";
elsif std_match(input, "----1---") then next_state <= st3; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "000000";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "000000";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "000000";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "000000";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "000000";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "000000";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "000000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000000";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000000";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "000000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "000000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "000000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "000000";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "000000";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "------1-") then next_state <= st7; output <= "000000";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "000000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "000000";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "000000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000000";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "000000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 1a731017a1c8cd8ec2f4b2ac1ce0291a | 0.565136 | 3.298687 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-06A-B.vhd | 1 | 14,629 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-06A-B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- ALU, A & B registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.PH;
use work.FLL;
ENTITY ABALU IS
port
(
-- Inputs
LAMP_TEST : IN STD_LOGIC; -- 04A
SALS : IN SALS_Bus; -- 01C
MANUAL_STORE : IN STD_LOGIC; -- 03D
RECYCLE_RST : IN STD_LOGIC; -- 04A
S_REG_3 : IN STD_LOGIC; -- 07B
SERV_IN_SIG,STAT_IN_SIG,OPNL_IN,ADDR_IN : IN STD_LOGIC; -- 08D
T_REQUEST : IN STD_LOGIC; -- 10B
A_BUS, B_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 8 is P
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
MACH_RST_SET_LCH : IN STD_LOGIC; -- 04B
S_REG_0 : IN STD_LOGIC; -- 07B
CTRL : IN CTRL_REG; -- 01C
DIAG_SW : IN STD_LOGIC; -- 04A
S_REG_RST : IN STD_LOGIC; -- 07B
GT_Z_BUS_TO_S_REG : IN STD_LOGIC; -- 07B
ROS_SCAN : IN STD_LOGIC; -- 03C
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04A
RST_LOAD : IN STD_LOGIC; -- 03C
SYSTEM_RST_PRIORITY_LCH : IN STD_LOGIC; -- 03A
-- Outputs
IND_A,IND_B,IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
A_REG_PC,B_REG_PC : OUT STD_LOGIC; -- 11A,07A,13A
OPNL_IN_LCHD,STATUS_IN_LCHD,Z0_BUS_0,SERV_IN_LCHD,ADDR_IN_LCHD : OUT STD_LOGIC; -- 02A
CARRY_1_LCHD : OUT STD_LOGIC; -- 05A
CARRY_0_LATCHED : OUT STD_LOGIC; -- 01B,02A
CARRY_0 : OUT STD_LOGIC; -- 07B
ALU_CHK : OUT STD_LOGIC; -- 03C,01A,07A
NTRUE,COMPLEMENT : OUT STD_LOGIC; -- 03B
P_CONNECT : OUT STD_LOGIC; -- 02A
P_CTRL_N : OUT STD_LOGIC; -- 02A,03A
N_CTRL_N : OUT STD_LOGIC; -- 04A
N_CTRL_LM : OUT STD_LOGIC; -- 02A
P_Z_BUS,N_Z_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
Z_HI_0,Z_LO_0,Z_0,Z_BUS_LO_DIGIT_PARITY : OUT STD_LOGIC;
MACH_RST_2A,MACH_RST_2B,MACH_RST_2C : OUT STD_LOGIC;
ODD : OUT STD_LOGIC; -- 04A
ALU_CHK_LCH : OUT STD_LOGIC; -- 01B,08D
GT_CARRY_TO_S3 : OUT STD_LOGIC; -- 07B
INTRODUCE_ALU_CHK : OUT STD_LOGIC; -- 04A
DECIMAL : OUT STD_LOGIC; -- 02A
-- Debug
DBG_P_ALU_A_IN, DBG_P_ALU_B_IN, DBG_P_ALU_CARRY, DBG_P_ALU_SUMS : OUT STD_LOGIC_VECTOR(0 to 7);
DBG_N_ALU_A_IN, DBG_N_ALU_B_IN, DBG_N_ALU_CARRY, DBG_N_ALU_SUMS : OUT STD_LOGIC_VECTOR(0 to 7);
DEBUG : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END ABALU;
ARCHITECTURE FMD OF ABALU IS
alias CC : STD_LOGIC_VECTOR(0 to 2) is CTRL.CTRL_CC;
alias CV : STD_LOGIC_VECTOR(0 to 1) is CTRL.CTRL_CV;
alias CROSSED : STD_LOGIC is CTRL.CROSSED;
alias STRAIGHT : STD_LOGIC is CTRL.STRAIGHT;
alias GT_A_LO : STD_LOGIC is CTRL.GT_A_REG_LO;
alias GT_A_HI : STD_LOGIC is CTRL.GT_A_REG_HI;
alias GT_B_REG_LO : STD_LOGIC is CTRL.GT_B_REG_LO;
alias GT_B_REG_HI : STD_LOGIC is CTRL.GT_B_REG_HI;
signal P_CARRY_IN_7,N_CARRY_IN_7 : STD_LOGIC;
signal P_Z_ALU_BUS,N_Z_ALU_BUS : STD_LOGIC_VECTOR(0 to 7);
signal A_REG,B_REG : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal CARRY_S3,INSERT_CARRY,INSERT_0_CARRY : STD_LOGIC;
signal NOT_S3 : STD_LOGIC;
signal HEX,sDECIMAL : STD_LOGIC;
-- signal N_CONNECT : std_logic;
-- signal P_CTRL_LM : STD_LOGIC;
signal P_ALU_A_IN,N_ALU_A_IN : STD_LOGIC_VECTOR(0 to 7);
signal P_ALU_B_IN,N_ALU_B_IN : STD_LOGIC_VECTOR(0 to 7);
signal P_SUMS,N_SUMS,P_CARRY,N_CARRY : STD_LOGIC_VECTOR(0 to 7);
signal HSEL,LSEL : STD_LOGIC_VECTOR(0 to 2);
signal sINTRODUCE_ALU_CHK : STD_LOGIC;
signal sODD,EVEN : STD_LOGIC;
signal DIAG_TEST_BIT : STD_LOGIC;
signal sNTRUE : STD_LOGIC;
signal sP_Z_BUS,sN_Z_BUS : STD_LOGIC_VECTOR(0 to 8);
signal sALU_CHK_LCH : STD_LOGIC;
signal sZ_HI_0, sZ_LO_0, sZ_0 : STD_LOGIC;
signal sMACH_RST_2, sMACH_RST_2A : STD_LOGIC;
signal sGT_CARRY_TO_S3 : STD_LOGIC;
signal SI_LCH_Set,STI_LCH_Set,Z0C1C0_LCH,PC7_LCH_Set,PC7_LCH_Reset,
NC7_LCH_Set,A_LCH_L,B_LCH_L,NS3_LCH_Set,NS3_LCH_Reset,EVEN_LCH_Set,EVEN_LCH_Reset,AC_LCH_Set,AC_LCH_Reset : STD_LOGIC;
signal sCARRY_0_LATCHED, sALU_CHK : STD_LOGIC; -- Debug
BEGIN
-- Fig 5-06A
-- A REGISTER, B REGISTER INDICATORS
IND_A <= "111111111" when LAMP_TEST='1' else A_REG;
IND_B <= "111111111" when LAMP_TEST='1' else B_REG;
A_REG_PC <= EvenParity(A_REG); -- AB2H2
B_REG_PC <= EvenParity(B_REG); -- AB2J2
-- IMMED STAT REG
SI_LCH_Set <= SERV_IN_SIG and not T_REQUEST;
SI_LCH: entity PH port map(SI_LCH_Set,T3,SERV_IN_LCHD); -- AB2D6
STI_LCH_Set <= STAT_IN_SIG and not T_REQUEST;
STI_LCH: entity PH port map(STI_LCH_Set,T3,STATUS_IN_LCHD); -- AB2D6
OI_LCH: entity PH port map(OPNL_IN,T3,OPNL_IN_LCHD); -- AB2D6
AI_LCH: entity PH port map(ADDR_IN,T3,ADDR_IN_LCHD); -- AB2D6
Z0C1C0_LCH <= T4 or RECYCLE_RST;
Z0_LCH: entity PH port map(sZ_0,Z0C1C0_LCH,Z0_BUS_0); -- AB2D6
C1_LCH: entity PH port map(P_CARRY(1),Z0C1C0_LCH,CARRY_1_LCHD); -- AB2D6
C0_LCH: entity PH port map(P_CARRY(0),Z0C1C0_LCH,sCARRY_0_LATCHED); -- AB2D6
CARRY_0_LATCHED <= sCARRY_0_LATCHED;
-- ALU INDICATORS
IND_ALU <= "111111111" when LAMP_TEST='1' else sP_Z_BUS;
-- CARRY IN LATCHES
CARRY_S3 <= '1' when CC="110" else '0'; -- AB2E7
INSERT_CARRY <= '1' when (CC="001") or (CC="101") else '0'; -- AB2E6
INSERT_0_CARRY <= '1' when (CC="000") or (CC="010") or (CC="011") or (CC="100") or (CC="111") else '0'; -- AB2E7
PC7_LCH_Set <= (S_REG_3 and CARRY_S3 and P1) or (P1 and INSERT_CARRY);
PC7_LCH_Reset <= MANUAL_STORE or T1 or RECYCLE_RST;
PC7_LCH: entity FLL port map(PC7_LCH_Set,PC7_LCH_Reset,P_CARRY_IN_7); -- AB2F3,AB2E4
NC7_LCH_Set <= (NOT_S3 and CARRY_S3 and P1) or (P1 and INSERT_0_CARRY) or RECYCLE_RST or MANUAL_STORE;
NC7_LCH: entity FLL port map(NC7_LCH_Set,T1,N_CARRY_IN_7); -- AB2F3,AB2E4
-- ALU CHECK
sALU_CHK <= '1' when (P_Z_ALU_BUS xor N_Z_ALU_BUS)/="11111111" or (P_SUMS(0) = N_SUMS(0)) or (P_SUMS(4) = N_SUMS(4)) or (P_CARRY(0) = N_CARRY(0)) else '0'; -- AB2D3,AB2D4,AB2E4
ALU_CHK <= sALU_CHK;
-- Fig 5-06B
-- A REG and B REG
A_LCH_L <= MAN_STOR_OR_DSPLY or MACH_RST_SET_LCH or T1;
A_LCH: PHV9 port map(not A_BUS,A_LCH_L,A_REG); -- AB1J5,AB1K7
B_LCH_L <= MACH_RST_SET_LCH or T1 or MANUAL_STORE;
B_LCH: PHV9 port map(B_BUS,B_LCH_L,B_REG); -- AB1J5,AB1L5
-- ALU B entry
sNTRUE <= '1' when (CV(0)='1' and S_REG_0='0') or CV="00" else '0'; -- AB2K7
NTRUE <= sNTRUE;
COMPLEMENT <= '1' when (CV(0)='1' and S_REG_0='1') or CV="01" else '0'; -- AB2L7
HEX <= '1' when CV(0)='0' or CV(1)='0' else '0'; -- AB2J7
sDECIMAL <= '1' when CV="11" else '0'; -- AB2H7
DECIMAL <= sDECIMAL;
HSEL <= GT_B_REG_HI & sDECIMAL & sNTRUE;
with HSEL select P_ALU_B_IN(0 to 3) <=
B_REG(0 to 3) + "0110" when "111", -- Spec A1
B_REG(0 to 3) when "101", -- Spec A2
not B_REG(0 to 3) when "100"|"110", -- Spec A3
"0110" when "011", -- Spec A4 ???
"1111" when "000"|"010", -- Spec A5
"0000" when others
;
LSEL <= GT_B_REG_LO & sDECIMAL & sNTRUE;
with LSEL select P_ALU_B_IN(4 to 7) <=
B_REG(4 to 7) + "0110" when "111", -- Spec A1
B_REG(4 to 7) when "101", -- Spec A2
not B_REG(4 to 7) when "100"|"110", -- Spec A3
"0110" when "011", -- Spec A4 ???
"1111" when "000"|"010", -- Spec A5
"0000" when others
;
N_ALU_B_IN <= not P_ALU_B_IN;
-- ALU A entry
P_ALU_A_IN(0 to 3) <=
((0 to 3 => not CROSSED) or A_REG(4 to 7)) and
((0 to 3 => not STRAIGHT) or A_REG(0 to 3)) and
(0 to 3 => GT_A_HI);
P_ALU_A_IN(4 to 7) <=
((4 to 7 => not CROSSED) or A_REG(0 to 3)) and
((4 to 7 => not STRAIGHT) or A_REG(4 to 7)) and
(4 to 7 => GT_A_LO);
N_ALU_A_IN(0 to 3) <=
not(((0 to 3 => GT_A_HI and STRAIGHT) and A_REG(0 to 3)) or
((0 to 3 => GT_A_HI and CROSSED) and A_REG(4 to 7))); -- ?? GT_A_HI is missing in MDM
N_ALU_A_IN(4 to 7) <=
not(((4 to 7 => GT_A_LO and STRAIGHT) and A_REG(4 to 7)) or
((4 to 7 => GT_A_LO and CROSSED) and A_REG(0 to 3)));
-- ALU
P_CONNECT <= '1' when (CC(0)='0' and CC(1)='1') or (CC(1)='1' and CC(2)='1') else '0'; -- AB2D7,AB2F7 CC=01X or CC=X11 i.e. 010 011 111
-- N_CONNECT <= '1' when (CC(0)/='0' or CC(1)/='1') and (CC(1)/='1' or CC(2)/='1') else '0'; -- AB2G7 i.e. 000 001 100 101 110www.typeupsidedown.
P_CTRL_N <= '1' when CC(1)='0' or CC(0)='1' else '0'; -- AB2D7,AB2F7 CC=X0X or 1XX ie. 000 001 100 101 110 111
N_CTRL_N <= '1' when CC(0)/='1' and CC(1)/='0' else '0'; -- AB2G7 CC=1XX nor CC=X0X ==> CC\=1XX and CC\=X0X i.e. 010 or 011
N_CTRL_LM <= '1' when CC/="010" else '0'; -- AB2G7
-- P_CTRL_LM <= '1' when CC="010" else '0'; -- AB2H7
-- CC functions
-- 000 Add, Carry in 0, Ignore Carry out
-- 001 Add, Carry in 1, Ignore Carry out
-- 010 And, Ignore Carry out
-- 011 Or, Ignore Carry out
-- 100 Add, Carry in 0, Set S3 to 1 on Carry out
-- 101 Add, Carry in 1, Set S3 to 1 on Carry out
-- 110 Add, Carry in from S3, Set S3 to 1 on Carry out
-- 111 Xor, Ignore Carry out
-- ALU P
with CC select P_SUMS <= -- AB2J6,AB2H6,AB2G6,AB2F6,AB2J5,AB2H5,AB2G5,AB2F5
P_ALU_A_IN and P_ALU_B_IN when "010",
P_ALU_A_IN or P_ALU_B_IN when "011",
P_ALU_A_IN xor P_ALU_B_IN when "111",
P_ALU_A_IN xor P_ALU_B_IN xor P_CARRY(1 to 7) & P_CARRY_IN_7 when others;
with CC select P_CARRY <=
"00000000" when "010"|"011"|"111",
(P_ALU_A_IN and P_ALU_B_IN) or
(P_ALU_A_IN and P_CARRY(1 to 7) & P_CARRY_IN_7) or
(P_ALU_B_IN and P_CARRY(1 to 7) & P_CARRY_IN_7) when others; -- Ripple carry
CARRY_0 <= P_CARRY(0);
sINTRODUCE_ALU_CHK <= DIAG_SW and sALU_CHK_LCH; -- AE3H5,AB3F6,AB3F7
INTRODUCE_ALU_CHK <= sINTRODUCE_ALU_CHK;
-- ALU N
with CC select N_SUMS <= -- AB2J6,AB2H6,AB2G6,AB2F6,AB2J5,AB2H5,AB2G5,AB2F5
(N_ALU_A_IN or N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "010",
(N_ALU_A_IN and N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "011",
(N_ALU_A_IN xnor N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "111",
(N_ALU_A_IN xor N_ALU_B_IN xor N_CARRY(1 to 7) & N_CARRY_IN_7) or (0 to 7 => sINTRODUCE_ALU_CHK) when others;
with CC select N_CARRY <=
"11111111" and (0 to 7 => not sINTRODUCE_ALU_CHK) when "010"|"011"|"111",
((N_ALU_A_IN and N_ALU_B_IN) or
(N_ALU_A_IN and N_CARRY(1 to 7) & N_CARRY_IN_7) or
(N_ALU_B_IN and N_CARRY(1 to 7) & N_CARRY_IN_7)) and (0 to 7 => not sINTRODUCE_ALU_CHK) when others;
-- Debug
DBG_P_ALU_A_IN <= P_ALU_A_IN;
DBG_P_ALU_B_IN <= P_ALU_B_IN;
DBG_P_ALU_CARRY <= P_CARRY;
DBG_P_ALU_SUMS <= P_SUMS;
DBG_N_ALU_A_IN <= N_ALU_A_IN;
DBG_N_ALU_B_IN <= N_ALU_B_IN;
DBG_N_ALU_CARRY <= N_CARRY;
DBG_N_ALU_SUMS <= N_SUMS;
sGT_CARRY_TO_S3 <= '1' when CC="100" or CC="101" or CC="110" else '0'; -- AB2E6
GT_CARRY_TO_S3 <= sGT_CARRY_TO_S3;
-- Debug
NOT_S3 <= not S_REG_3;
-- NS3_LCH_Set <= (N_CARRY(0) and T4 and sGT_CARRY_TO_S3) or S_REG_RST;
-- NS3_LCH_Reset <= (sGT_CARRY_TO_S3 and T4 and P_CARRY(0)) or (GT_Z_BUS_TO_S_REG and sP_Z_BUS(3));
-- NS3_LCH: FLE port map(NS3_LCH_Set,NS3_LCH_Reset,clk,NOT_S3); -- AB2E3
-- Temp Debug
P_Z_ALU_BUS(0 to 3) <= ((0 => sODD and HEX, 1 to 3 => HEX) and P_SUMS(0 to 3)) or
((0 to 3 => P_CARRY(0) and sDECIMAL) and P_SUMS(0 to 3)) or
((0 to 3 => N_CARRY(0) and sDECIMAL) and (P_SUMS(0 to 3) - "0110"));
N_Z_ALU_BUS(0 to 3) <= ((0 to 3 => HEX) and N_SUMS(0 to 3)) or
((0 to 3 => sDECIMAL and P_CARRY(0)) and N_SUMS(0 to 3)) or
((0 to 3 => sDECIMAL and N_CARRY(0)) and (N_SUMS(0 to 3) + "0110"));
P_Z_ALU_BUS(4 to 7) <= ((4 => sODD and HEX, 5 to 7 => HEX) and P_SUMS(4 to 7)) or
((4 to 7 => P_CARRY(4) and sDECIMAL) and P_SUMS(4 to 7)) or
((4 to 7 => N_CARRY(4) and sDECIMAL) and (P_SUMS(4 to 7) - "0110"));
N_Z_ALU_BUS(4 to 7) <= ((4 to 7 => HEX) and N_SUMS(4 to 7)) or
((4 to 7 => sDECIMAL and P_CARRY(4)) and N_SUMS(4 to 7)) or
((4 to 7 => sDECIMAL and N_CARRY(4)) and (N_SUMS(4 to 7) + "0110"));
sP_Z_BUS <= P_Z_ALU_BUS & EvenParity(P_Z_ALU_BUS & EVEN); -- AB3C4
-- Note N_Z parity is not inverted, so is the same as P_Z
-- This may force a parity error when INTRODUCE_ALU_CHK is active,
-- depending on the value of P_Z. This parity error into R is required
-- for Diag B73 to work
sN_Z_BUS <= N_Z_ALU_BUS & EvenParity(P_Z_ALU_BUS & EVEN);
P_Z_BUS <= sP_Z_BUS;
N_Z_BUS <= sN_Z_BUS;
Z_BUS_LO_DIGIT_PARITY <= EvenParity(P_Z_ALU_BUS(4 to 7)); -- AB3C4
sZ_HI_0 <= '1' when sP_Z_BUS(0 to 3)="0000" else '0'; -- AB2E5
Z_HI_0 <= sZ_HI_0;
sZ_LO_0 <= '1' when sP_Z_BUS(4 to 7)="0000" else '0'; -- AB2E5
Z_LO_0 <= sZ_LO_0;
sZ_0 <= sZ_HI_0 and sZ_LO_0; -- AB2D5
Z_0 <= sZ_0;
sMACH_RST_2 <= sZ_0 and RECYCLE_RST; -- AB3C5
MACH_RST_2A_DELAY: AR port map(D=>sMACH_RST_2,Clk=>Clk,Q=>sMACH_RST_2A);
MACH_RST_2A <= sMACH_RST_2A;
MACH_RST_2B <= sMACH_RST_2A;
MACH_RST_2C <= sMACH_RST_2A;
DIAG_TEST_BIT <= '1' when SALS.SALS_CK="1000" and SALS.SALS_AK='1' else '0'; -- AB3E7
EVEN_LCH_Set <= T2 and DIAG_TEST_BIT and not sALU_CHK_LCH;
EVEN_LCH_Reset <= (T2 and sALU_CHK_LCH) or RST_LOAD or SYSTEM_RST_PRIORITY_LCH or RECYCLE_RST; -- ?? *not* SYSTEM_RST_PRIORITY_LCH ??
EVEN_LCH: entity FLL port map(EVEN_LCH_Set,EVEN_LCH_Reset,EVEN); -- AB3E5,AB3G2
sODD <= not EVEN;
ODD <= sODD;
AC_LCH_Set <= EVEN and DIAG_TEST_BIT and T1;
AC_LCH_Reset <= RECYCLE_RST or RST_LOAD or (ROS_SCAN and GT_SWS_TO_WX_PWR);
AC_LCH: entity FLL port map(AC_LCH_Set,AC_LCH_Reset,sALU_CHK_LCH); -- AG3G7,AB3G2
ALU_CHK_LCH <= sALU_CHK_LCH;
-- Debug
DEBUG <= '1' when NC7_LCH_Set='1' else '0';
END FMD;
| gpl-3.0 | e47988ea4f090d57f4087b4e823b6372 | 0.616447 | 2.330201 | false | false | false | false |
TheMassController/VHDL_experimenting | project/bus/test/bus_tb_pkg.vhd | 1 | 1,215 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library src;
use src.bus_pkg.all;
package bus_tb_pkg is
function bus_tb_mst2slv(
address : natural := 0;
writeData : natural := 0;
writeMask : natural range 0 to 2**bus_write_mask'length - 1 := 0;
readEnable : std_logic := '0';
writeEnable : std_logic := '0'
) return bus_mst2slv_type;
end bus_tb_pkg;
package body bus_tb_pkg is
function bus_tb_mst2slv(
address : natural := 0;
writeData : natural := 0;
writeMask : natural range 0 to 2**bus_write_mask'length - 1 := 0;
readEnable : std_logic := '0';
writeEnable : std_logic := '0'
) return bus_mst2slv_type is
variable retval : bus_mst2slv_type;
begin
retval.address := std_logic_vector(to_unsigned(address, bus_address_type'length));
retval.writeData := std_logic_vector(to_unsigned(writeData, bus_data_type'length));
retval.writeMask := std_logic_vector(to_unsigned(writeMask, bus_write_mask'length));
retval.readEnable := readEnable;
retval.writeEnable := writeEnable;
return retval;
end bus_tb_mst2slv;
end bus_tb_pkg;
| mit | 60ca50dbcc4f56ca348943e9cf72bc6d | 0.626337 | 3.491379 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-05A.vhd | 1 | 4,072 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05A.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- R Reg (MSDR) Indicators and Checks
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RIndsChks IS
port
(
-- Inputs
TEST_LAMP : IN STD_LOGIC; -- 04A
R_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7);
R_REG_BUS_P : IN STD_LOGIC;
G_REG_1 : IN STD_LOGIC;
V_REG_6,V_REG_7 : IN STD_LOGIC;
GM_WM_DETECTED : IN STD_LOGIC; -- 06C
CARRY_1_LCHD : IN STD_LOGIC; -- 06A
S_REG_1 : IN STD_LOGIC; -- 07B
W3_TO_MATCH : IN STD_LOGIC; -- 01B
ROS_SCAN : IN STD_LOGIC; -- 03C
GT_SW_MACH_RST : IN STD_LOGIC; -- 03A
-- Outputs
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
R_REG_PC : OUT STD_LOGIC; -- 07A
R_REG_VALID_DEC_DIGIT : OUT STD_LOGIC; -- 02A
N1BC_OR_R1 : OUT STD_LOGIC; -- 02A
S_REG_1_OR_R_REG_2 : OUT STD_LOGIC; -- 02A
G_REG_1_OR_R_REG_3 : OUT STD_LOGIC; -- 02A
V67_00_OR_GM_WM : OUT STD_LOGIC; -- 02A
N1401_MODE : OUT STD_LOGIC; -- 05B,06C,07A,01B,04D,13C
-- Clocks
T2 : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END RIndsChks;
ARCHITECTURE FMD OF RIndsChks IS
signal V67_EQUALS_00 : STD_LOGIC;
signal N1401_MODE_SET,N1401_MODE_RESET : STD_LOGIC;
signal sN1401_MODE : STD_LOGIC;
BEGIN
-- Fig 5-05A
IND_MSDR <= R_REG_BUS or (0 to 7 => TEST_LAMP);
IND_MSDR_P <= R_REG_BUS_P or TEST_LAMP;
R_REG_PC <= EvenParity(R_REG_BUS & R_REG_BUS_P); -- AA1K6
R_REG_VALID_DEC_DIGIT <= ((not R_REG_BUS(0) or not R_REG_BUS(1)) and (not R_REG_BUS(0) or not R_REG_BUS(2))) and
((not R_REG_BUS(4) or not R_REG_BUS(5)) and (not R_REG_BUS(4) or not R_REG_BUS(6))); -- ?? *and* or *or* as per MDM?
N1401_MODE_SET <= W3_TO_MATCH and not ROS_SCAN; -- AC1C4
N1401_MODE_RESET <= T2 or GT_SW_MACH_RST;
MODE1401: entity work.FLL port map(N1401_MODE_SET,N1401_MODE_RESET,sN1401_MODE); -- AB2B2,AB1B3,AB2C2
N1401_MODE <= sN1401_MODE;
V67_EQUALS_00 <= not V_REG_6 and not V_REG_7; -- AA1H6
-- AB2C2,AB2B2:
N1BC_OR_R1 <= (not sN1401_MODE or R_REG_BUS(1)) and ((CARRY_1_LCHD and not sN1401_MODE) or sN1401_MODE);
S_REG_1_OR_R_REG_2 <= (not sN1401_MODE or R_REG_BUS(2)) and (sN1401_MODE or S_REG_1);
G_REG_1_OR_R_REG_3 <= (not sN1401_MODE or R_REG_BUS(3)) and (sN1401_MODE or (not sN1401_MODE and G_REG_1));
V67_00_OR_GM_WM <= (not sN1401_MODE or GM_WM_DETECTED) and ((not sN1401_MODE and V67_EQUALS_00) or sN1401_MODE);
END FMD;
| gpl-3.0 | 35d3e950c8699f9ec255489449541df7 | 0.611739 | 2.700265 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/XTime.vhd | 2 | 533 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity xtime is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end xtime;
-- Architecture of the Component
architecture a_xtime of xtime is
begin
b_out(7) <= b_in(6);
b_out(6) <= b_in(5);
b_out(5) <= b_in(4);
b_out(4) <= b_in(3) xor b_in(7);
b_out(3) <= b_in(2) xor b_in(7);
b_out(2) <= b_in(1);
b_out(1) <= b_in(0) xor b_in(7);
b_out(0) <= b_in(7);
end a_xtime;
| mit | d19a3924a1998791130e730f15e92133 | 0.585366 | 2.307359 | false | false | false | false |
chastell/art-decomp | kiss/ex5_nov.vhd | 1 | 3,826 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_nov;
architecture behaviour of ex5_nov is
constant s1: std_logic_vector(3 downto 0) := "1110";
constant s2: std_logic_vector(3 downto 0) := "1101";
constant s3: std_logic_vector(3 downto 0) := "1010";
constant s4: std_logic_vector(3 downto 0) := "1001";
constant s5: std_logic_vector(3 downto 0) := "1111";
constant s6: std_logic_vector(3 downto 0) := "1011";
constant s7: std_logic_vector(3 downto 0) := "1100";
constant s8: std_logic_vector(3 downto 0) := "1000";
constant s0: std_logic_vector(3 downto 0) := "0000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s7; output <= "00";
elsif std_match(input, "10") then next_state <= s5; output <= "11";
elsif std_match(input, "11") then next_state <= s4; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s1; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "00";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "11";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s5; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | abb88838abb7ceb46e5f9580fefec294 | 0.564036 | 3.267293 | false | false | false | false |
mike7c2/befunge_processor | befunge_processor.vhd | 1 | 10,180 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--TODO - make PC and address signals use std_logic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED;
entity befunge_processor is
generic
(
word_size : integer := 8;
instruction_size : integer := 16;
stack_size : integer := 2048;
grid_width : integer := 8;
grid_height : integer := 8
);
port
(
clk,reset : in std_logic;
data_in : in std_logic_vector(word_size-1 downto 0);
data_out : out std_logic_vector(word_size-1 downto 0)
);
end befunge_processor;
architecture processor_v1 of befunge_processor is
component befunge_pc is
generic(
grid_width : integer;
grid_height : integer
);
port(
clk : in std_logic;
reset : in std_logic;
address_x : out integer range 0 to grid_width-1;
address_y : out integer range 0 to grid_height-1;
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end component;
constant LEFT_INSTRUCTION : integer range 0 to 255 := 62;
type stack_declaration is array(stack_size-1 downto 0) of std_logic_vector(word_size-1 downto 0);
signal stack : stack_declaration;
type grid_nibble is array (grid_height-1 downto 0) of std_logic_vector(word_size-1 downto 0);
type grid_stuff is array (grid_width-1 downto 0) of grid_nibble;
-- an array "array of array" type
variable grid : grid_stuff :=
(
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size))),
(std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)),std_logic_vector(to_unsigned(LEFT_INSTRUCTION,word_size)))
);
type fde_cycle_states is (idle,fetch,decode,execute);
signal fde_cycle : fde_cycle_states := idle;
type befunge_instruction_set is (move_left,move_right,move_up,move_down);
signal instruction : befunge_instruction_set;
signal grid_data_in : std_logic_vector(word_size-1 downto 0);
signal grid_data_out : std_logic_vector(word_size-1 downto 0);
signal grid_address : integer range 0 to (grid_width*grid_height)-1;
--signal grid_address_y : integer range 0 to grid_height-1;
signal grid_load : std_logic;
signal grid_store : std_logic;
signal dir : std_logic_vector(1 downto 0);
signal pc_address_x : integer range 0 to grid_width-1;
signal pc_address_y : integer range 0 to grid_height-1;
signal pc_skip : std_logic;
signal pc_enable : std_logic;
signal stack_ptr : integer range 0 to stack_size-1;
signal stack_s0 : std_logic_vector(word_size-1 downto 0); --Top of stack
signal stack_s1 : std_logic_vector(word_size-1 downto 0); --Stack -1
begin
data_out <= grid_data_out;
--this will kick up shit if we want to do read/write from the stack any other time
--maybe best to keep a copy of these whenever pushes or pops occur?
stack_s0 <= stack(stack_ptr);
--stack_s1 <= stack(stack_ptr-1);
program_counter : befunge_pc
generic map
(
grid_width => grid_width,
grid_height => grid_height
)
port map
(
clk => clk,
reset => reset,
address_x => pc_address_x,
address_y => pc_address_y,
dir => dir,
skip => pc_skip,
en => pc_enable
);
--TODO : this shit needs casted
grid_address <= to_integer(signed(stack_s0));
--grid_address_y <= stack_s1;
--The grid must handle a write from a store instruction
--the grid must handle a read from the pc address
--the grid must handle a read from a load instruction
grid_process : process(reset,clk, grid_store,instruction)
begin
if(reset = '1') then
fde_cycle <= idle;
else
if rising_edge(clk) then
--set all signals inside this and we're laughing
--fetch execute cycle that we can use to synchronise read/write signals
case fde_cycle is
when idle =>
grid_load <= '0';
when fetch =>
grid_load <= '1';
fde_cycle <= decode;
when decode =>
grid_load <= '0';
fde_cycle <= execute;
when execute =>
grid_load <= '0';
case instruction is
when move_left =>
dir <= "10";
fde_cycle <= fetch;
when move_right =>
dir <= "00";
fde_cycle <= fetch;
when move_up =>
dir <= "01";
fde_cycle <= fetch;
when move_down =>
dir <= "11";
fde_cycle <= fetch;
when others =>
fde_cycle <= idle;
end case;
--fed_cycle <= idle;
end case;
--only write the grid when the grid_store flag is enabled
if (grid_store = '1') then
grid(grid_address_x,grid_address_y) <= grid_data_in;
end if;
if (grid_load = '1') then
grid_data_out <= grid(grid_address);
else
grid_data_out <= grid(pc_address);
end if;
end if;
end if;
end process;
process(reset,clk,instruction,grid_data_out)
begin
if(reset = '1') then
instruction <= move_right;
else
if rising_edge(clk) then
case grid_data_out(7 downto 0) is
when X"3E" => --move right!!
instruction <= move_right;
when X"3C" => --move left!!
instruction <= move_left;
when X"5E" => --move up!!
instruction <= move_up;
when X"76" => --move down!!
instruction <= move_down;
when others =>
instruction <= move_right;
end case;
end if;
end if;
end process;
end processor_v1;
| unlicense | 08f841931b3b4c64ac147682f56e6efc | 0.628978 | 3.489887 | false | false | false | false |
chastell/art-decomp | kiss/s1a_hot.vhd | 1 | 12,157 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1a_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1a_hot;
architecture behaviour of s1a_hot is
constant st0: std_logic_vector(19 downto 0) := "10000000000000000000";
constant st1: std_logic_vector(19 downto 0) := "01000000000000000000";
constant st2: std_logic_vector(19 downto 0) := "00100000000000000000";
constant st5: std_logic_vector(19 downto 0) := "00010000000000000000";
constant st3: std_logic_vector(19 downto 0) := "00001000000000000000";
constant st4: std_logic_vector(19 downto 0) := "00000100000000000000";
constant st6: std_logic_vector(19 downto 0) := "00000010000000000000";
constant st7: std_logic_vector(19 downto 0) := "00000001000000000000";
constant st12: std_logic_vector(19 downto 0) := "00000000100000000000";
constant st13: std_logic_vector(19 downto 0) := "00000000010000000000";
constant st8: std_logic_vector(19 downto 0) := "00000000001000000000";
constant st11: std_logic_vector(19 downto 0) := "00000000000100000000";
constant st15: std_logic_vector(19 downto 0) := "00000000000010000000";
constant st9: std_logic_vector(19 downto 0) := "00000000000001000000";
constant st10: std_logic_vector(19 downto 0) := "00000000000000100000";
constant st14: std_logic_vector(19 downto 0) := "00000000000000010000";
constant st16: std_logic_vector(19 downto 0) := "00000000000000001000";
constant st17: std_logic_vector(19 downto 0) := "00000000000000000100";
constant st18: std_logic_vector(19 downto 0) := "00000000000000000010";
constant st19: std_logic_vector(19 downto 0) := "00000000000000000001";
signal current_state, next_state: std_logic_vector(19 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "000000";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "000000";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "000000";
elsif std_match(input, "----1---") then next_state <= st3; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "000000";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "000000";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "000000";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "000000";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "000000";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "000000";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "000000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000000";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000000";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "000000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "000000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "000000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "000000";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "000000";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "------1-") then next_state <= st7; output <= "000000";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "000000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "000000";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "000000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000000";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "000000";
end if;
when others => next_state <= "--------------------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 508d5138785f72235d918bfa0d213c87 | 0.575224 | 3.390128 | false | false | false | false |
mike7c2/befunge_processor | befunge_stack.vhd | 1 | 2,983 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_stack - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity befunge_stack is
generic(
stack_depth_pow : integer := 4;
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
stack_0_o : out std_logic_vector(word_size-1 downto 0);
stack_1_o : out std_logic_vector(word_size-1 downto 0);
stack_i : in std_logic_vector(word_size-1 downto 0);
pop1 : in std_logic;
pop2 : in std_logic;
push : in std_logic;
swap : in std_logic;
en : in std_logic
);
end befunge_stack;
architecture stack_v1 of befunge_stack is
type stack_type is array ((2**stack_depth_pow)-1 downto 0) of std_logic_vector(word_size-1 downto 0);
signal stack : stack_type;
signal stack_ptr : Signed(stack_depth_pow-1 downto 0);
begin
stack_0_o <= stack(to_integer(Unsigned(stack_ptr)));
stack_1_o <= stack(to_integer(Unsigned(stack_ptr- 1)));
process(reset,clk)
variable ptr_incr : integer range -2 to 1;
begin
if(reset = '1') then
--stack_0_o <= (others => '0');
--stack_1_o <= (others => '0');
stack <= (others => (others => '0'));
stack_ptr <= (others => '0');
else
if rising_edge(clk) then
ptr_incr := 0;
if ( en = '1' ) then
if (pop1 = '1' or pop2 = '1' or push = '1') then
if ( pop1 = '1' ) then
ptr_incr := - 1;
elsif ( pop2 = '1' ) then
ptr_incr := - 2;
elsif ( push = '1' ) then
ptr_incr := 1;
stack(to_integer(Unsigned(stack_ptr + ptr_incr))) <= stack_i;
end if;
elsif (swap = '1' ) then
stack(to_integer(stack_ptr)) <= stack(to_integer(stack_ptr - 1));
stack(to_integer(stack_ptr - 1)) <= stack(to_integer(stack_ptr));
--stack_0_o <= stack(to_integer(stack_ptr + ptr_incr -1));
--stack_1_o <= stack(to_integer(stack_ptr + ptr_incr));
end if;
stack_ptr <= stack_ptr + ptr_incr;
end if;
end if;
end if;
end process;
end stack_v1; | unlicense | 6357fde9236b861444d564e68e6163b9 | 0.445189 | 3.761665 | false | false | false | false |
chastell/art-decomp | kiss/beecount_nov.vhd | 1 | 3,518 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity beecount_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(3 downto 0)
);
end beecount_nov;
architecture behaviour of beecount_nov is
constant st0: std_logic_vector(2 downto 0) := "011";
constant st1: std_logic_vector(2 downto 0) := "111";
constant st2: std_logic_vector(2 downto 0) := "101";
constant st3: std_logic_vector(2 downto 0) := "100";
constant st4: std_logic_vector(2 downto 0) := "010";
constant st5: std_logic_vector(2 downto 0) := "000";
constant st6: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "000") then next_state <= st0; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st1 =>
if std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "0-0") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st2 =>
if std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st3 =>
if std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "0110";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st4 =>
if std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "-00") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st5 =>
if std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st6 =>
if std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "1001";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when others => next_state <= "---"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | ff1875330f060c434b0b2c0fb67cb521 | 0.58556 | 3.309501 | false | false | false | false |
chastell/art-decomp | kiss/dk27_rnd.vhd | 1 | 2,406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_rnd;
architecture behaviour of dk27_rnd is
constant START: std_logic_vector(2 downto 0) := "101";
constant state6: std_logic_vector(2 downto 0) := "010";
constant state2: std_logic_vector(2 downto 0) := "011";
constant state5: std_logic_vector(2 downto 0) := "110";
constant state3: std_logic_vector(2 downto 0) := "111";
constant state4: std_logic_vector(2 downto 0) := "001";
constant state7: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | e3f28485c62f2928784a055b0ff0a6ed | 0.594347 | 3.323204 | false | false | false | false |
thommyj/slotcar | de0/spi_decoder.vhd | 1 | 9,249 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity spi_decoder is
port(
clk : in std_logic;
rst : in std_logic;
spidata_out : out std_logic_vector(7 downto 0);
spidata_in : in std_logic_vector(7 downto 0);
spidata_valid_in : in std_logic;
leds : out std_logic_vector(7 downto 0);
pll_locked : in std_logic;
version : in std_logic_vector(7 downto 0);
extreg_dataout : out std_logic_vector(7 downto 0);
extreg_addressout : out std_logic_vector(7 downto 0);
extreg_read_req : out std_logic;
extreg_enable : out std_logic;
extreg_datain : in std_logic_vector(7 downto 0);
extreg_data_valid : in std_logic;
extreg_addressin : out std_logic_vector(7 downto 0)
);
end entity spi_decoder;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of spi_decoder is
--
-- Define all local signals (like static data) here
--
type state_type is (SPISTATE_IDLE,SPISTATE_WRITE,SPISTATE_READ_WAITFORDONE,SPISTATE_READ_WAITFORDATA,SPISTATE_WRITE2,SPISTATE_WRITE3);
type out_content_type is (SPIOUT_OK, SPIOUT_ERROR, SPIOUT_INTERNAL, SPIOUT_EXTERNAL);
signal state : state_type;
signal out_content : out_content_type;
--received command from peer
signal rec_cmd : std_logic_vector(7 downto 0);
signal rec_data : std_logic_vector(7 downto 0);
--internal registers
signal status_reg : std_logic_vector(7 downto 0);
signal config_reg : std_logic_vector(7 downto 0) := "00000000";
signal led_reg : std_logic_vector(7 downto 0) := "00000000";
--local copies of output
signal int_reg_muxout: std_logic_vector(7 downto 0);
signal ext_reg_out: std_logic_vector(7 downto 0);
signal led_states: std_logic_vector(7 downto 0);
--Protocol
--First byte is the command, MSB sent first
---bit7 = r/w (w=1b1)
---bit6 = internal registers (1b1)/slotcar registers (1b0)
--bit5-0 = address
--Second byte is data, MSB sent first. Peer is assumed to wait "long enough" before reading/writing data
---If command is a read, Peer should send 0xAA (OK) as second command
--Return values
---During write of command, 0xAA is returned if everything is ok. If FPGA is in an error state 0xFF is returned
-- During second byte, if command was a write, 0xAA is returned if command was ok. Otherwise 0xFF if an error was found
--Internal registers
---0x00, version register r
---0x01, status r
---0x02, config r/w,
--bit7:2, reserved
--bit1:0, led output. 2b00 = version, 2b01 = raw spi data from master, 2b10 = SPI state, 2b11 = led register
---0x03, leds r/w
--External registers
---
begin
process(clk,rst)
begin
if (rst = '1') then
state <= SPISTATE_IDLE;
out_content <= SPIOUT_OK;
config_reg <= (others=>'0');
led_reg <= (others=>'0');
extreg_dataout <= (others => '0');
extreg_addressout <= (others => '0');
extreg_enable <= '0';
extreg_read_req <= '0';
elsif rising_edge(clk) then
extreg_enable <= '0'; --external write only needs one cycle
extreg_read_req <= '0';
case state is
---------IDLE--------------
when SPISTATE_IDLE =>
--command received?
if (spidata_valid_in = '1') then
rec_cmd <= spidata_in;
--if MSB is set, command is write
if (spidata_in(7) = '1') then
state <= SPISTATE_WRITE;
out_content <= SPIOUT_OK;
else --otherwise command is read
--internal read if bit 6 is set
if(spidata_in(6) = '1') then
state <= SPISTATE_READ_WAITFORDONE;
out_content <= SPIOUT_INTERNAL;
else --external registers, need an extra clkcycle
state <= SPISTATE_READ_WAITFORDATA;
extreg_read_req <= '1';
out_content <= SPIOUT_ERROR;
--in reality even fewer registers, but we have 6 address bits
--so lets send them. If user exceeds limits register file will
--send error
extreg_addressin <= "00" & spidata_in(5 downto 0);
end if;
end if;
end if;
----------WRITE--------------
when SPISTATE_WRITE =>
--if peer writes data
if (spidata_valid_in = '1') then
state <= SPISTATE_WRITE2;
out_content <= SPIOUT_OK;
end if;
when SPISTATE_WRITE2 =>
--if peer writes data
if (spidata_valid_in = '1') then
rec_data <= spidata_in;
state <= SPISTATE_WRITE3;
out_content <= SPIOUT_OK;
--internal
if(rec_cmd(6) = '1') then
case rec_cmd(5 downto 0) is
when "000010" =>
config_reg <= spidata_in;
when "000011" =>
led_reg <= spidata_in;
when others =>
end case;
--external
else
extreg_dataout <= spidata_in;
extreg_addressout <= "00" & rec_cmd(5 downto 0);
extreg_enable <= '1';
end if;
end if;
----------WRITE--------------
when SPISTATE_WRITE3 =>
--if peer writes data
if (spidata_valid_in = '1') then
state <= SPISTATE_IDLE;
out_content <= SPIOUT_OK;
end if;
----------READ--------------
when SPISTATE_READ_WAITFORDONE =>
--when second byte is received, peer has alread read data
if (spidata_valid_in = '1') then
rec_data <= spidata_in;
state <= SPISTATE_IDLE;
out_content <= SPIOUT_OK;
end if;
when SPISTATE_READ_WAITFORDATA =>
--address to registerfile was put out last cycle,
--data should be available now
if(extreg_data_valid = '1') then
ext_reg_out <= extreg_datain;
state <= SPISTATE_READ_WAITFORDONE;
out_content <= SPIOUT_EXTERNAL;
end if;
end case;
end if; --if reset
end process;
status_reg <= "0000000" & pll_locked;
with out_content select
spidata_out <= x"AA" when SPIOUT_OK,
x"FF" when SPIOUT_ERROR,
int_reg_muxout when SPIOUT_INTERNAL,
ext_reg_out when SPIOUT_EXTERNAL;
with rec_cmd(5 downto 0) select
int_reg_muxout <= version when "000000",
status_reg when "000001",
config_reg when "000010",
led_reg when "000011",
x"FF" when others;
--bit1:0, led output. 2b00 = version, 2b01 = raw spi data from master, 2b10 = SPI state, 2b11 = led register
with config_reg(1 downto 0) select
leds <= version when "00",
spidata_in when "01",
led_states when "10",
led_reg when "11";
with state select
led_states <= x"01" when SPISTATE_IDLE,
x"02" when SPISTATE_WRITE,
x"04" when SPISTATE_READ_WAITFORDONE,
x"08" when SPISTATE_READ_WAITFORDATA,
x"10" when SPISTATE_WRITE2,
x"12" when SPISTATE_WRITE3;
end architecture syn;
-- *** EOF ***
| mit | e05891e02b005d8182e601f1e1d9a8a5 | 0.581036 | 3.644208 | false | false | false | false |
chastell/art-decomp | kiss/styr_jed.vhd | 1 | 18,712 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_jed is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_jed;
architecture behaviour of styr_jed is
constant st0: std_logic_vector(4 downto 0) := "01100";
constant st12: std_logic_vector(4 downto 0) := "00100";
constant st10: std_logic_vector(4 downto 0) := "11100";
constant st1: std_logic_vector(4 downto 0) := "11111";
constant st2: std_logic_vector(4 downto 0) := "00101";
constant st8: std_logic_vector(4 downto 0) := "11101";
constant st3: std_logic_vector(4 downto 0) := "01000";
constant st7: std_logic_vector(4 downto 0) := "01101";
constant st4: std_logic_vector(4 downto 0) := "01011";
constant st5: std_logic_vector(4 downto 0) := "00001";
constant st6: std_logic_vector(4 downto 0) := "01111";
constant st29: std_logic_vector(4 downto 0) := "01110";
constant st9: std_logic_vector(4 downto 0) := "00110";
constant st28: std_logic_vector(4 downto 0) := "11110";
constant st11: std_logic_vector(4 downto 0) := "11000";
constant st13: std_logic_vector(4 downto 0) := "00000";
constant st14: std_logic_vector(4 downto 0) := "10100";
constant st15: std_logic_vector(4 downto 0) := "10001";
constant st16: std_logic_vector(4 downto 0) := "01001";
constant st22: std_logic_vector(4 downto 0) := "10111";
constant st19: std_logic_vector(4 downto 0) := "11001";
constant st17: std_logic_vector(4 downto 0) := "01010";
constant st18: std_logic_vector(4 downto 0) := "11011";
constant st20: std_logic_vector(4 downto 0) := "11010";
constant st21: std_logic_vector(4 downto 0) := "10000";
constant st25: std_logic_vector(4 downto 0) := "10101";
constant st23: std_logic_vector(4 downto 0) := "10110";
constant st24: std_logic_vector(4 downto 0) := "10010";
constant st26: std_logic_vector(4 downto 0) := "00010";
constant st27: std_logic_vector(4 downto 0) := "00111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "----------";
case current_state is
when st0 =>
if std_match(input, "1-0000---") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-10-----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-1-0----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0010---") then next_state <= st10; output <= "1000----10";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "1010100110";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st1 =>
if std_match(input, "------0--") then next_state <= st2; output <= "0110010000";
elsif std_match(input, "------1--") then next_state <= st8; output <= "0110100100";
end if;
when st2 =>
if std_match(input, "1-00000--") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0011---") then next_state <= st2; output <= "010100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st7; output <= "010000--00";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st3 =>
if std_match(input, "1-0000---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st3; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st5; output <= "0110001100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st4 =>
if std_match(input, "---------") then next_state <= st6; output <= "0110010000";
end if;
when st5 =>
if std_match(input, "---------") then next_state <= st1; output <= "0110010100";
end if;
when st6 =>
if std_match(input, "1-00000--") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st6; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st7 =>
if std_match(input, "1-0000---") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st7; output <= "110100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0010------";
elsif std_match(input, "1-010----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st29 =>
if std_match(input, "1-0000---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st29; output <= "110100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st8 =>
if std_match(input, "---------") then next_state <= st9; output <= "0110010000";
end if;
when st9 =>
if std_match(input, "1-00000--") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-001----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-00001--") then next_state <= st28; output <= "010010--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st28 =>
if std_match(input, "1-0000---") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-001----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st10 =>
if std_match(input, "1--0---00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1---0--00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1--0---10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0----1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0---1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st11 =>
if std_match(input, "1--011-0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0--0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--010-0-") then next_state <= st10; output <= "0100----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0---1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st12 =>
if std_match(input, "1--011---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--10----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--000---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0001---") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1--010---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st13 =>
if std_match(input, "1--000---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--01----") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--001---") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st14 =>
if std_match(input, "1--000---") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--01----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--001---") then next_state <= st15; output <= "0010100100";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st15 =>
if std_match(input, "--1------") then next_state <= st16; output <= "0010010000";
elsif std_match(input, "--0------") then next_state <= st22; output <= "0010010000";
end if;
when st16 =>
if std_match(input, "1--000---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--011---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st17 =>
if std_match(input, "1--000---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st18; output <= "0010001100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st18 =>
if std_match(input, "---------") then next_state <= st19; output <= "0010010100";
end if;
when st19 =>
if std_match(input, "---------") then next_state <= st16; output <= "0010010000";
end if;
when st20 =>
if std_match(input, "---------") then next_state <= st21; output <= "0010010000";
end if;
when st21 =>
if std_match(input, "1--000---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st22 =>
if std_match(input, "1-0000---") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st23 =>
if std_match(input, "1-0000---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st24; output <= "0010001100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st24 =>
if std_match(input, "---------") then next_state <= st25; output <= "0010010100";
end if;
when st25 =>
if std_match(input, "---------") then next_state <= st22; output <= "0010010000";
end if;
when st26 =>
if std_match(input, "---------") then next_state <= st27; output <= "0010010000";
end if;
when st27 =>
if std_match(input, "1-0000---") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when others => next_state <= "-----"; output <= "----------";
end case;
end process;
end behaviour;
| agpl-3.0 | 9586cdedb760ca0b9654c23ce2f60970 | 0.553068 | 3.430247 | false | false | false | false |
chastell/art-decomp | kiss/shiftreg_nov.vhd | 1 | 2,558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_nov;
architecture behaviour of shiftreg_nov is
constant st0: std_logic_vector(2 downto 0) := "000";
constant st1: std_logic_vector(2 downto 0) := "100";
constant st2: std_logic_vector(2 downto 0) := "011";
constant st3: std_logic_vector(2 downto 0) := "111";
constant st4: std_logic_vector(2 downto 0) := "010";
constant st5: std_logic_vector(2 downto 0) := "110";
constant st6: std_logic_vector(2 downto 0) := "001";
constant st7: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st0; output <= "1";
elsif std_match(input, "1") then next_state <= st4; output <= "1";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st1; output <= "1";
elsif std_match(input, "1") then next_state <= st5; output <= "1";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st2; output <= "1";
elsif std_match(input, "1") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st3; output <= "1";
elsif std_match(input, "1") then next_state <= st7; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | c76370420ba3d5225c9b78eb9e21c254 | 0.577404 | 3.193508 | false | false | false | false |
chastell/art-decomp | kiss/s27_rnd.vhd | 1 | 3,869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_rnd;
architecture behaviour of s27_rnd is
constant s000: std_logic_vector(2 downto 0) := "101";
constant s001: std_logic_vector(2 downto 0) := "010";
constant s101: std_logic_vector(2 downto 0) := "011";
constant s100: std_logic_vector(2 downto 0) := "110";
constant s010: std_logic_vector(2 downto 0) := "111";
constant s011: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | f72ac5e8c1a98d661d5e09af926ec9b9 | 0.576376 | 3.181743 | false | false | false | false |
chastell/art-decomp | kiss/s420_rnd.vhd | 1 | 17,549 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_rnd;
architecture behaviour of s420_rnd is
constant s1111111111111111: std_logic_vector(4 downto 0) := "11101";
constant s0000000000000000: std_logic_vector(4 downto 0) := "00010";
constant s0001000000000000: std_logic_vector(4 downto 0) := "11011";
constant s0010000000000000: std_logic_vector(4 downto 0) := "11110";
constant s0011000000000000: std_logic_vector(4 downto 0) := "11111";
constant s0100000000000000: std_logic_vector(4 downto 0) := "10001";
constant s0101000000000000: std_logic_vector(4 downto 0) := "10110";
constant s0110000000000000: std_logic_vector(4 downto 0) := "01011";
constant s0111000000000000: std_logic_vector(4 downto 0) := "01111";
constant s1000000000000000: std_logic_vector(4 downto 0) := "00001";
constant s1001000000000000: std_logic_vector(4 downto 0) := "10000";
constant s1010000000000000: std_logic_vector(4 downto 0) := "11010";
constant s1011000000000000: std_logic_vector(4 downto 0) := "11000";
constant s1100000000000000: std_logic_vector(4 downto 0) := "01000";
constant s1101000000000000: std_logic_vector(4 downto 0) := "00100";
constant s1110000000000000: std_logic_vector(4 downto 0) := "01001";
constant s1111000000000000: std_logic_vector(4 downto 0) := "00110";
constant s0000000100000000: std_logic_vector(4 downto 0) := "11100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 3053b94731cadc24208ec1c518d06eec | 0.564192 | 4.094494 | false | false | false | false |
chastell/art-decomp | kiss/ex1_hot.vhd | 1 | 16,661 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_hot is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_hot;
architecture behaviour of ex1_hot is
constant s1: std_logic_vector(19 downto 0) := "10000000000000000000";
constant s2: std_logic_vector(19 downto 0) := "01000000000000000000";
constant s4: std_logic_vector(19 downto 0) := "00100000000000000000";
constant s3: std_logic_vector(19 downto 0) := "00010000000000000000";
constant s5: std_logic_vector(19 downto 0) := "00001000000000000000";
constant s6: std_logic_vector(19 downto 0) := "00000100000000000000";
constant s7: std_logic_vector(19 downto 0) := "00000010000000000000";
constant s8: std_logic_vector(19 downto 0) := "00000001000000000000";
constant s9: std_logic_vector(19 downto 0) := "00000000100000000000";
constant s10: std_logic_vector(19 downto 0) := "00000000010000000000";
constant s11: std_logic_vector(19 downto 0) := "00000000001000000000";
constant s12: std_logic_vector(19 downto 0) := "00000000000100000000";
constant s13: std_logic_vector(19 downto 0) := "00000000000010000000";
constant s14: std_logic_vector(19 downto 0) := "00000000000001000000";
constant s15: std_logic_vector(19 downto 0) := "00000000000000100000";
constant s16: std_logic_vector(19 downto 0) := "00000000000000010000";
constant s17: std_logic_vector(19 downto 0) := "00000000000000001000";
constant s18: std_logic_vector(19 downto 0) := "00000000000000000100";
constant s19: std_logic_vector(19 downto 0) := "00000000000000000010";
constant s20: std_logic_vector(19 downto 0) := "00000000000000000001";
signal current_state, next_state: std_logic_vector(19 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------"; output <= "-------------------";
case current_state is
when s1 =>
if std_match(input, "1011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "11-------") then next_state <= s4; output <= "0000000000000000000";
elsif std_match(input, "1000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "1010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "1001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s2 =>
if std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--1----") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-0--0----") then next_state <= s2; output <= "0111100000000000000";
end if;
when s3 =>
if std_match(input, "-0-------") then next_state <= s7; output <= "0111101010000000000";
end if;
when s4 =>
if std_match(input, "-011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "-000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "-010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "-001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s5 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "----100--") then next_state <= s5; output <= "0001000000000000000";
elsif std_match(input, "----110--") then next_state <= s5; output <= "0001000001000000000";
elsif std_match(input, "----101--") then next_state <= s8; output <= "0000000000000000000";
elsif std_match(input, "----111--") then next_state <= s8; output <= "0000000001000000000";
end if;
when s6 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-1-") then next_state <= s9; output <= "0001101001111000000";
elsif std_match(input, "-0--11-0-") then next_state <= s6; output <= "0001000001000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s10; output <= "0001100001111000000";
elsif std_match(input, "-00-10-1-") then next_state <= s9; output <= "0001101000111000000";
elsif std_match(input, "-0--10-0-") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-01-10-1-") then next_state <= s10; output <= "0001100000111000000";
end if;
when s7 =>
if std_match(input, "-0--0----") then next_state <= s7; output <= "0111101000000000000";
elsif std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-1----") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-01-1----") then next_state <= s12; output <= "0001000000000000000";
end if;
when s8 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000110000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000110000";
end if;
when s9 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s13; output <= "0001100011001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s9; output <= "0001001001001000000";
elsif std_match(input, "-00-11-1-") then next_state <= s14; output <= "0001101011001001000";
elsif std_match(input, "-01-10-1-") then next_state <= s13; output <= "0001100010001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s9; output <= "0001001000001000000";
elsif std_match(input, "-00-10-1-") then next_state <= s14; output <= "0001101010001001000";
end if;
when s10 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s15; output <= "0001100001001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s10; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s15; output <= "0001100000001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s10; output <= "0001000000001000000";
end if;
when s11 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011011000110";
elsif std_match(input, "-00-11-0-") then next_state <= s11; output <= "0001001001000000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011011000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011011000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011011000010";
elsif std_match(input, "-01-11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010011000110";
elsif std_match(input, "-00-10-0-") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010011000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010011000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010011000010";
elsif std_match(input, "-01-10-0-") then next_state <= s12; output <= "0001000000000000000";
end if;
when s12 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001011000110";
elsif std_match(input, "-0--11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001011000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000011000110";
elsif std_match(input, "-0--10-0-") then next_state <= s12; output <= "0001000000000000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000011000010";
end if;
when s13 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s13; output <= "0001000001001000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001001000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s13; output <= "0001000000001000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000001000010";
end if;
when s14 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s14; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s14; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s15 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-0-") then next_state <= s15; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s15; output <= "0001000000001000000";
end if;
when s16 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s16; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s16; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s17 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s18; output <= "0001000000001000001";
end if;
when s18 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s19; output <= "0011100001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s18; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s19; output <= "0011100000000000000";
end if;
when s19 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s19; output <= "0001000001000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s20; output <= "0000000001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s19; output <= "0001000000000000000";
elsif std_match(input, "-0--10-1-") then next_state <= s20; output <= "0000000000000000000";
end if;
when s20 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000100000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000100000";
end if;
when others => next_state <= "--------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | fb0e550c6922022c20996e0f9adfd602 | 0.61719 | 3.703267 | false | false | false | false |
chastell/art-decomp | kiss/ex7_rnd.vhd | 1 | 4,215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_rnd;
architecture behaviour of ex7_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101";
constant s7: std_logic_vector(3 downto 0) := "0010";
constant s0: std_logic_vector(3 downto 0) := "1011";
constant s2: std_logic_vector(3 downto 0) := "1110";
constant s5: std_logic_vector(3 downto 0) := "1111";
constant s3: std_logic_vector(3 downto 0) := "0001";
constant s8: std_logic_vector(3 downto 0) := "0110";
constant s4: std_logic_vector(3 downto 0) := "0000";
constant s6: std_logic_vector(3 downto 0) := "1010";
constant s9: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s7; output <= "11";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "11";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s7; output <= "00";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "00";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s4; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s4; output <= "11";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s6; output <= "11";
elsif std_match(input, "01") then next_state <= s3; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 8e306c011b002dd9f83d3e8e1c59fbb4 | 0.560854 | 3.280156 | false | false | false | false |
LucasMahieu/TP_secu | code/edk_support/user_logic.vhd | 1 | 17,692 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Sep 29 13:35:32 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 14
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
aes_clk : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component aes_core is port (
data_inH : in std_logic_vector( 127 downto 0 );
input_key : in std_logic_vector( 127 downto 0 );
go_cipher, go_key, enc_command : in std_logic;
data_outH : out std_logic_vector( 127 downto 0 );
data_out_ok : out std_logic;
ready_out : out std_logic;
error : out std_logic_vector( 0 downto 0 );
rst, ck : in std_logic;
fault_aes_port : in std_logic_vector( 7 downto 0)
);
end component;
-- AES signals
signal din, key, dout : std_logic_vector( 127 downto 0 );
signal load_key, start_crypt, encdec : std_logic;
signal aes_ready, aes_valid, aes_error : std_logic;
signal aes_rst : std_logic;
signal old_slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- for injection fault
signal fault_sig : std_logic_vector( 7 downto 0 );
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- commands
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- din 0
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- din 1
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- din 2
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- din 3
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- key 0
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- key 1
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- key 2
signal slv_reg8 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- key 3
signal slv_reg9 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- dout 0
signal slv_reg10 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- dout 1
signal slv_reg11 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- dout 2
signal slv_reg12 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- dout 3
signal slv_reg13 : std_logic_vector(0 to C_SLV_DWIDTH-1); -- out state
signal slv_reg_write_sel : std_logic_vector(0 to 13);
signal slv_reg_read_sel : std_logic_vector(0 to 13);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
din <= slv_reg4 & slv_reg3 & slv_reg2 & slv_reg1;
key <= slv_reg8 & slv_reg7 & slv_reg6 & slv_reg5;
encdec <= slv_reg0(2);
aes_rst <= not Bus2IP_Reset;
SLV_PROC : process( aes_clk ) is
begin
if aes_clk'event and aes_clk = '1' then
old_slv_reg0 <= slv_reg0;
end if;
end process SLV_PROC;
KEY_PROC : process( aes_clk ) is
begin
if aes_clk'event and aes_clk = '1' then
if ( old_slv_reg0(1)='0' and slv_reg0(1)='1' ) then
load_key <= '1';
else
load_key <= '0';
end if;
end if;
end process KEY_PROC;
START_PROC : process( aes_clk ) is
begin
if aes_clk'event and aes_clk = '1' then
if ( old_slv_reg0(0)='0' and slv_reg0(0)='1' ) then
start_crypt <= '1';
else
start_crypt <= '0';
end if;
end if;
end process START_PROC;
-- for injection
FAULT_INJECT : process( aes_clk ) is
-- init à 10 pour injecter qu'après le 1er go crypt
variable cycle_count : natural := 7 + ROUND_NUMBER * 6;
begin
if aes_clk'event and aes_clk = '1' then
if ( slv_reg0(3)='1' ) then
cycle_count := cycle_count + 1;
if s_go_crypt = '1' then
cycle_count := 0;
end if;
if cycle_count > 1 + ROUND_NUMBER * 6 and cycle_count < 7 + ROUND_NUMBER * 6 then
fault_sig <= "11111111";
else
fault_sig <= "00000000";
end if;
end if;
end if;
end process FAULT_INJECT;
i_aes : aes_core port map(
data_inH => din,
input_key => key,
go_cipher => start_crypt,
go_key => load_key,
enc_command => encdec,
data_outH => dout,
data_out_ok => aes_valid,
ready_out => aes_ready,
error(0) => aes_error,
rst => aes_rst,
ck => aes_clk,
fault_aes_port => fault_sig
);
OUT_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if ( aes_valid='1' ) then
slv_reg12 <= dout( 127 downto 96 );
slv_reg11 <= dout( 95 downto 64 );
slv_reg10 <= dout( 63 downto 32 );
slv_reg9 <= dout( 31 downto 0 );
end if;
end if;
end process OUT_PROC;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 13);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 13);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
--slv_reg9 <= (others => '0');
--slv_reg10 <= (others => '0');
--slv_reg11 <= (others => '0');
--slv_reg12 <= (others => '0');
--slv_reg13 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "00000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
--when "00000000000001" =>
--for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--if ( Bus2IP_BE(byte_index) = '1' ) then
--slv_reg13(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--end if;
--end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13 ) is
begin
case slv_reg_read_sel is
when "00000000010000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100" => slv_ip2bus_data <= slv_reg11;
when "00000000000010" => slv_ip2bus_data <= slv_reg12;
when "00000000000001" => slv_ip2bus_data <= slv_reg13;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | fd008b4420c562843f0799730253dfed | 0.498643 | 3.728135 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-05B.vhd | 1 | 7,155 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- M & N register (MSAR) assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY MNAssem IS
port
(
-- Inputs
MAIN_STORAGE_CP : IN STD_LOGIC; -- 04D
SX_2_BUMP_SW_GT : IN STD_LOGIC; -- 13C
USE_CPU_DECODER : IN STD_LOGIC; -- 05C
E_SEL_SW_BUS : IN E_SW_BUS_Type; -- 04C
SALS : IN SALS_Bus; -- 01C
MEM_SEL : IN STD_LOGIC; -- 03D
USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
N1401_MODE : IN STD_LOGIC; -- 05A
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03D
SX_2_R_W_CTRL : IN STD_LOGIC; -- 14D
SX_2_SHARE_CYCLE : IN STD_LOGIC; -- 14D
SX_2_GATE : IN STD_LOGIC; -- 13C
SX_1_R_W_CTRL : IN STD_LOGIC; -- 12D
SX_1_SHARE_CYCLE : IN STD_LOGIC; -- 12D
SX_1_GATE : IN STD_LOGIC; -- 13C
XXH : IN STD_LOGIC; -- 08C
CU_DECODE_UCW : IN STD_LOGIC; -- 04D
FORCE_M_REG_123 : IN STD_LOGIC; -- 04D
XH,XL : IN STD_LOGIC; -- 08C
CU_SAL_0_BIT : IN STD_LOGIC; -- 01C
MACH_RST_2A : IN STD_LOGIC; -- 06B
ABCD_SW_BUS : IN STD_LOGIC_VECTOR(0 to 15); -- 04B
AB_SW_P,CD_SW_P : IN STD_LOGIC; -- 04B
I,U,T,V,J,L,GU,GV,HU,HV : IN STD_LOGIC_VECTOR(0 to 7);
I_P,U_P,T_P,V_P,J_P,L_P,GU_P,GV_P,HU_P,HV_P : IN STD_LOGIC;
IJ_SEL, UV_SEL : IN STD_LOGIC; -- 04C
-- Outputs
GT_T_TO_MN_REG : OUT STD_LOGIC; -- 08B
GT_CK_TO_MN_REG : OUT STD_LOGIC; -- 08B
GT_V_TO_N_REG : OUT STD_LOGIC; -- 03B
GT_J_TO_N_REG : OUT STD_LOGIC; -- 03B
M_BUS,N_BUS : OUT STD_LOGIC_VECTOR(0 to 7);
M_BUS_P,N_BUS_P : OUT STD_LOGIC
);
END MNAssem;
ARCHITECTURE FMD OF MNAssem IS
signal GT_ABCD_SWS_TO_MN : STD_LOGIC;
signal GT_I_TO_M_REG,GT_U_TO_M_REG : STD_LOGIC;
signal CK_BUS : STD_LOGIC_VECTOR(0 to 7);
signal CK_BUS_P : STD_LOGIC;
signal GATE_L_REG_TO_M_BUS : STD_LOGIC;
signal GT_GUV_OR_HUV_TO_MN : STD_LOGIC;
signal GT_HUV_TO_MN,GT_GUV_TO_MN : STD_LOGIC;
signal M_BUSP,N_BUSP : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal sGT_T_TO_MN_REG : STD_LOGIC;
signal sGT_CK_TO_MN_REG : STD_LOGIC;
signal sGT_V_TO_N_REG : STD_LOGIC;
signal sGT_J_TO_N_REG : STD_LOGIC;
BEGIN
-- Fig 5-05B
GT_ABCD_SWS_TO_MN <= MEM_SEL and USE_MAN_DECODER_PWR; -- AC1F3
GT_I_TO_M_REG <= IJ_SEL or (MAIN_STORAGE_CP and USE_CPU_DECODER and not SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2)); -- AA1H2,AA1H7,AA1J7 CM=011
GT_U_TO_M_REG <= (MAIN_STORAGE_CP and USE_CPU_DECODER and SALS.SALS_CM(0) and not SALS.SALS_CM(1) and not SALS.SALS_CM(2)) or UV_SEL; -- AA1H7,AA1H2,AA1J7 CM=100
sGT_T_TO_MN_REG <= USE_CPU_DECODER and SALS.SALS_CM(0) and not SALS.SALS_CM(1) and SALS.SALS_CM(2); -- AB3E2,AB3F7-removed?? CM=101
GT_T_TO_MN_REG <= sGT_T_TO_MN_REG;
sGT_CK_TO_MN_REG <= USE_CPU_DECODER and SALS.SALS_CM(0) and SALS.SALS_CM(1) and not SALS.SALS_CM(2); -- AB3E2,AB3F7-removed?? CM=110
GT_CK_TO_MN_REG <= sGT_CK_TO_MN_REG;
CK_BUS(0) <= '1';
CK_BUS(1) <= '0';
CK_BUS(2) <= SALS.SALS_CN(0) or SX_2_BUMP_SW_GT; -- AB1C6
CK_BUS(3) <= SALS.SALS_CK(0);
CK_BUS(4) <= '1';
CK_BUS(5) <= SALS.SALS_CK(1);
CK_BUS(6) <= SALS.SALS_CK(2);
CK_BUS(7) <= SALS.SALS_CK(3);
CK_BUS_P <= (not SALS.SALS_PK or SALS.SALS_CM(0) or not CK_BUS(2)) and (not SALS.SALS_PK or SX_2_BUMP_SW_GT); -- AB1C6
sGT_V_TO_N_REG <= UV_SEL or (SALS.SALS_CM(0) and not SALS.SALS_CM(1) and not SALS.SALS_CM(2) and USE_CPU_DECODER); -- AB3C2 CM=100
GT_V_TO_N_REG <= sGT_V_TO_N_REG;
sGT_J_TO_N_REG <= (not SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2) and USE_CPU_DECODER) or IJ_SEL; -- AB3C2 CM=011
GT_J_TO_N_REG <= sGT_J_TO_N_REG;
GT_GUV_OR_HUV_TO_MN <= USE_CPU_DECODER and SALS.SALS_CM(0) and SALS.SALS_CM(1) and SALS.SALS_CM(2); -- AB3C2 CM=111
GT_HUV_TO_MN <= (USE_MANUAL_DECODER and E_SEL_SW_BUS.E_SEL_SW_HUV_HCD) or (not SX_2_R_W_CTRL and SX_2_SHARE_CYCLE) or (SX_2_GATE and GT_GUV_OR_HUV_TO_MN); -- AE1D5
GT_GUV_TO_MN <= (USE_MANUAL_DECODER and E_SEL_SW_BUS.E_SEL_SW_GUV_GCD) or (not SX_1_R_W_CTRL and SX_1_SHARE_CYCLE) or (GT_GUV_OR_HUV_TO_MN and SX_1_GATE); -- AD1H6
GATE_L_REG_TO_M_BUS <= N1401_MODE and MAIN_STORAGE_CP and sGT_T_TO_MN_REG; -- AB2B3
M_BUSP <= ((0 to 8 => GT_HUV_TO_MN) and HU & HU_P) or -- AB1D2
((0 to 8 => GT_ABCD_SWS_TO_MN) and ABCD_SW_BUS(0 to 7) & AB_SW_P) or -- AB1D2
((0 to 8 => GATE_L_REG_TO_M_BUS) and L & L_P) or -- AB1D2
((0 to 8 => GT_GUV_TO_MN) and GU & GU_P) or -- AB1C2
((0 to 8 => GT_I_TO_M_REG) and I & I_P) or -- AB1C2
((0 to 8 => GT_U_TO_M_REG) and U & U_P) or -- AB1C2
(0 => '0', 1 => (XXH and CU_DECODE_UCW) or (CU_DECODE_UCW and N1401_MODE) or FORCE_M_REG_123, 2 to 8 => '0') or -- AA1B4
(0 to 1 => '0', 2 => (CU_DECODE_UCW and XH and not N1401_MODE) or FORCE_M_REG_123, 3 to 8 => '0') or -- AB1B3,AA1J4
(0 to 2 => '0', 3 => (CU_DECODE_UCW and XL) or (FORCE_M_REG_123 and not N1401_MODE) or (N1401_MODE and CU_SAL_0_BIT and USE_CPU_DECODER), 4 to 8 => '0') or -- AA1B4
(0 to 7 => '0', 8 => (not N1401_MODE and sGT_T_TO_MN_REG) or MACH_RST_2A or sGT_CK_TO_MN_REG); -- AB1G2
M_BUS <= M_BUSP(0 to 7);
M_BUS_P <= M_BUSP(8);
N_BUSP <= ((0 to 8 => GT_ABCD_SWS_TO_MN) and ABCD_SW_BUS(8 to 15) & CD_SW_P) or -- AB1D4
((0 to 8 => sGT_CK_TO_MN_REG) and CK_BUS & CK_BUS_P) or -- AB1D4
(0 to 7 => '0', 8 => MACH_RST_2A) or -- AB1D4
((0 to 8 => sGT_T_TO_MN_REG) and T & T_P) or -- AB1C4
((0 to 8 => sGT_V_TO_N_REG) and V & V_P) or -- AB1C4
((0 to 8 => sGT_J_TO_N_REG) and J & J_P) or -- AB1C4
((0 to 8 => GT_HUV_TO_MN) and HV & HV_P) or -- AB1E4
((0 to 8 => GT_GUV_TO_MN) and GV & GV_P); -- AB1E4
N_BUS <= N_BUSP(0 to 7);
N_BUS_P <= N_BUSP(8);
END FMD;
| gpl-3.0 | 79280382223765cbceb25519c96f13e2 | 0.604612 | 2.335945 | false | false | false | false |
TheMassController/VHDL_experimenting | project/common/static_debouncer.vhd | 1 | 3,606 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity static_debouncer is
generic (
debounce_ticks : natural range 1 to natural'high
);
port (
clk : in STD_LOGIC;
pulse_in : in STD_LOGIC;
pulse_out : out STD_LOGIC
);
end static_debouncer;
architecture behavioral of static_debouncer is
type state_type is (start, wait_for_edge_change, wait_for_debounce);
signal state : state_type := start;
signal read_input : boolean;
signal counter_rst : boolean;
signal counter_run : boolean;
signal counter_done : boolean;
signal output_signal : std_logic;
signal cur_different : boolean;
signal difference_detected : boolean;
signal detector_rst : boolean;
begin
cur_different <= output_signal /= pulse_in;
pulse_out <= output_signal;
difference_detector : process(cur_different, detector_rst)
variable d : boolean;
begin
if detector_rst then
d := false;
elsif cur_different then
d := true;
end if;
difference_detected <= d;
end process;
rising_edge_counter : process(clk, counter_rst, counter_run)
variable cur_count : natural range 0 to natural'high;
variable count_done : boolean;
begin
if counter_rst then
cur_count := 0;
count_done := false;
elsif rising_edge(clk) and counter_run then
cur_count := cur_count + 1;
end if;
if cur_count = (debounce_ticks - 1) then
count_done := true;
end if;
counter_done <= count_done;
end process;
output_control : process(clk, read_input)
variable cur_output : std_logic;
begin
if rising_edge(clk) and read_input then
cur_output := pulse_in;
end if;
output_signal <= cur_output;
end process;
state_selector : process(clk)
begin
if rising_edge(clk) then
case state is
when start =>
state <= wait_for_edge_change;
when wait_for_edge_change =>
if difference_detected then
state <= wait_for_debounce;
else
state <= wait_for_edge_change;
end if;
when wait_for_debounce =>
if counter_done then
state <= wait_for_edge_change;
else
state <= wait_for_debounce;
end if;
end case;
end if;
end process;
state_output : process(state, counter_done, cur_different)
begin
case state is
when start =>
read_input <= true;
counter_rst <= true;
counter_run <= false;
detector_rst <= true;
when wait_for_edge_change =>
read_input <= false;
counter_rst <= true;
counter_run <= false;
detector_rst <= false;
when wait_for_debounce =>
if (counter_done and cur_different) then
read_input <= true;
else
read_input <= false;
end if;
counter_rst <= false;
counter_run <= true;
detector_rst <= true;
end case;
end process;
end behavioral;
| mit | ef8e32a0a7c870270a5e05be8803abe0 | 0.503328 | 4.581957 | false | false | false | false |
chastell/art-decomp | kiss/s386_nov.vhd | 1 | 7,731 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s386_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s386_nov;
architecture behaviour of s386_nov is
constant s000000: std_logic_vector(3 downto 0) := "0000";
constant s001100: std_logic_vector(3 downto 0) := "1000";
constant s001000: std_logic_vector(3 downto 0) := "1111";
constant s000100: std_logic_vector(3 downto 0) := "1001";
constant s010010: std_logic_vector(3 downto 0) := "0111";
constant s000011: std_logic_vector(3 downto 0) := "0011";
constant s010001: std_logic_vector(3 downto 0) := "0110";
constant s010011: std_logic_vector(3 downto 0) := "0101";
constant s110000: std_logic_vector(3 downto 0) := "0100";
constant s100000: std_logic_vector(3 downto 0) := "1011";
constant s000010: std_logic_vector(3 downto 0) := "0010";
constant s010000: std_logic_vector(3 downto 0) := "1010";
constant s000001: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "----11-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----100") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1-101") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0-101") then next_state <= s010000; output <= "0000001";
elsif std_match(input, "----0-0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----011") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----001") then next_state <= s000000; output <= "0000000";
end if;
when s001100 =>
if std_match(input, "-1---00") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---00") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
elsif std_match(input, "-0---10") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---10") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---11") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---11") then next_state <= s000100; output <= "0010000";
end if;
when s001000 =>
if std_match(input, "-----00") then next_state <= s001000; output <= "0000000";
elsif std_match(input, "0----01") then next_state <= s000000; output <= "0101100";
elsif std_match(input, "1----01") then next_state <= s000000; output <= "0101000";
elsif std_match(input, "0----11") then next_state <= s001100; output <= "0101100";
elsif std_match(input, "1----11") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "-----10") then next_state <= s001000; output <= "0000000";
end if;
when s000100 =>
if std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----10") then next_state <= s001100; output <= "0110000";
elsif std_match(input, "-----11") then next_state <= s000100; output <= "0010000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
end if;
when s010010 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000011; output <= "0000000";
end if;
when s000011 =>
if std_match(input, "--01-01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--00-01") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s010001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-1---01") then next_state <= s010011; output <= "0000010";
elsif std_match(input, "-0---01") then next_state <= s010001; output <= "0000010";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s010011 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s110000; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s110000 =>
if std_match(input, "-1---01") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "-0---01") then next_state <= s110000; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s100000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000010; output <= "0000000";
end if;
when s000010 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--10-00") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "--00-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1101") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "--10101") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--00101") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--10001") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--11001") then next_state <= s000010; output <= "0000000";
elsif std_match(input, "--00001") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--01001") then next_state <= s000010; output <= "0000000";
end if;
when s010000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000001; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
end if;
when s000001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0--01") then next_state <= s010000; output <= "0000001";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 5c8a1ce44c7cbc5369009c30bb64f0d0 | 0.591256 | 3.602516 | false | false | false | false |
chastell/art-decomp | kiss/lion_hot.vhd | 1 | 1,844 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_hot;
architecture behaviour of lion_hot is
constant st0: std_logic_vector(3 downto 0) := "1000";
constant st1: std_logic_vector(3 downto 0) := "0100";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st3: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "-0") then next_state <= st0; output <= "0";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "0-") then next_state <= st1; output <= "1";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "1-") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "0-") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 88c703e21e726625acac2501d5981d39 | 0.588395 | 3.252205 | false | false | false | false |
es17m014/vhdl-counter | src/old/vhdl/clkdiv.vhd | 1 | 2,913 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : clkdiv.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is a clock divider see table below
--
-- +---------+--------------+--------------+
-- | q(i) | Frequenz | Periode |
-- +---------+--------------+--------------+
-- | sys_clk | 100.0000 MHz | 10.00000 ns |
-- | 0 | 50.0000 MHz | 20.00000 ns |
-- | 1 | 25.0000 MHz | 40.00000 ns |
-- | 2 | 12.5000 MHz | 80.00000 ns |
-- | 3 | 6.2500 MHz | 160.00000 ns |
-- | 4 | 3.1250 MHz | 320.00000 ns |
-- | 5 | 1.5625 MHz | 640.00000 ns |
-- | 6 | 781.2500 kHz | 1.28000 us |
-- | 7 | 390.6250 kHz | 2.56000 us |
-- | 8 | 195.3125 kHz | 5.12000 us |
-- | 9 | 97.6562 kHz | 10.24000 us |
-- | 10 | 48.8281 kHz | 20.48000 us |
-- | 11 | 24.4140 kHz | 40.96000 us |
-- | 12 | 12.2070 kHz | 81.92000 us |
-- | 13 | 6.1035 kHz | 163.84000 us |
-- | 14 | 3.0518 kHz | 327.68000 us |
-- | 15 | 1.5259 kHz | 655.36000 us |
-- | 16 | 762.9395 Hz | 1.31072 ms |
-- | 17 | 381.4697 Hz | 2.62144 ms |
-- | 18 | 190.7349 Hz | 5.24288 ms |
-- | 19 | 95.3674 Hz | 10.48576 ms |
-- | 20 | 47.6837 Hz | 20.97152 ms |
-- | 21 | 23.8419 Hz | 41.94304 ms |
-- | 22 | 11.9209 Hz | 83.88608 ms |
-- | 23 | 5.9605 Hz | 167.77216 ms |
-- | 24 | 2.9823 Hz | 335.54432 ms |
-- | 25 | 1.4901 Hz | 671.08846 ms |
-- | 26 | 0.7451 Hz | 1.34218 s |
-- +---------+--------------+--------------+
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity clkdiv is
port(
clk_i : in std_logic; -- 100 MHz systemclock to divide
reset_i : in std_logic; -- reset signal
clk190Hz_o : out std_logic -- 190 Hz for X7Seg display
);
end clkdiv;
architecture struc of clkdiv is
signal count : std_logic_vector(26 downto 0) := (others => '0');
begin
process(clk_i, reset_i)
begin
if reset_i = '1' then
count <= (others => '0');
elsif rising_edge(clk_i) then
count <= count + 1;
end if;
end process;
clk190Hz_o <= count(18);
end struc; | mit | 15e02381f3d19609cf27844b49dce9b8 | 0.405767 | 3.355991 | false | false | false | false |
chastell/art-decomp | spec/fixtures/bbara.vhdl | 1 | 8,131 | -- 11 cells of target arch (6/1 + 5/2)
-- G archs: 5/2 5/4
-- H arch: 6/8
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara is
port(
reset: in std_logic;
clock: in std_logic;
fsm_i: in std_logic_vector(0 to 3);
fsm_o: out std_logic_vector(0 to 1)
);
end bbara;
architecture behaviour of bbara is
signal fsm_q, fsm_qp: std_logic_vector(0 to 5);
signal d0_x: std_logic_vector(0 to 3);
signal d0_q: std_logic_vector(0 to 5);
signal d0_qu: std_logic_vector(0 to 3);
signal d0_qv: std_logic_vector(0 to 1);
signal d0_g_i: std_logic_vector(0 to 4);
signal d0_g_o: std_logic_vector(0 to 1);
signal d1_x: std_logic_vector(0 to 2);
signal d1_q: std_logic_vector(0 to 3);
signal d1_qu: std_logic_vector(0 to 0);
signal d1_qv: std_logic_vector(0 to 2);
signal d1_g_i: std_logic_vector(0 to 4);
signal d1_g_o: std_logic_vector(0 to 3);
signal d1_h_i: std_logic_vector(0 to 5);
signal d1_h_o: std_logic_vector(0 to 7);
begin
d0_x <= fsm_i;
d0_q <= fsm_q;
d0_qu <= d0_q(0 to 3);
d0_qv <= d0_q(4 to 5);
d0_g_i <= (d0_x(0) & d0_x(1) & d0_x(3) & d0_qv);
d1_x <= (d0_x(2) & d0_g_o);
d1_q <= d0_qu;
d1_qu <= d1_q(0 to 0);
d1_qv <= d1_q(1 to 3);
d1_g_i <= (d1_x(0) & d1_x(1) & d1_qv);
d1_h_i <= (d1_x(2) & d1_g_o & d1_qu);
fsm_qp <= d1_h_o(0 to 5);
fsm_o <= d1_h_o(6 to 7);
process(reset, clock) begin
if reset = '1' then fsm_q <= "000000";
elsif rising_edge(clock) then fsm_q <= fsm_qp;
end if;
end process;
d0_g: process(d0_g_i) begin
d0_g_o <= (others => '-');
if std_match(d0_g_i, "00000") then d0_g_o <= "11";
elsif std_match(d0_g_i, "00001") then d0_g_o <= "11";
elsif std_match(d0_g_i, "00010") then d0_g_o <= "11";
elsif std_match(d0_g_i, "00011") then d0_g_o <= "01";
elsif std_match(d0_g_i, "00100") then d0_g_o <= "11";
elsif std_match(d0_g_i, "00101") then d0_g_o <= "00";
elsif std_match(d0_g_i, "00110") then d0_g_o <= "00";
elsif std_match(d0_g_i, "00111") then d0_g_o <= "00";
elsif std_match(d0_g_i, "01000") then d0_g_o <= "11";
elsif std_match(d0_g_i, "01001") then d0_g_o <= "11";
elsif std_match(d0_g_i, "01010") then d0_g_o <= "11";
elsif std_match(d0_g_i, "01011") then d0_g_o <= "01";
elsif std_match(d0_g_i, "01100") then d0_g_o <= "10";
elsif std_match(d0_g_i, "01101") then d0_g_o <= "11";
elsif std_match(d0_g_i, "01110") then d0_g_o <= "10";
elsif std_match(d0_g_i, "01111") then d0_g_o <= "11";
elsif std_match(d0_g_i, "10000") then d0_g_o <= "11";
elsif std_match(d0_g_i, "10001") then d0_g_o <= "11";
elsif std_match(d0_g_i, "10010") then d0_g_o <= "11";
elsif std_match(d0_g_i, "10011") then d0_g_o <= "01";
elsif std_match(d0_g_i, "10100") then d0_g_o <= "00";
elsif std_match(d0_g_i, "10101") then d0_g_o <= "10";
elsif std_match(d0_g_i, "10110") then d0_g_o <= "11";
elsif std_match(d0_g_i, "10111") then d0_g_o <= "10";
elsif std_match(d0_g_i, "11000") then d0_g_o <= "11";
elsif std_match(d0_g_i, "11001") then d0_g_o <= "11";
elsif std_match(d0_g_i, "11010") then d0_g_o <= "11";
elsif std_match(d0_g_i, "11011") then d0_g_o <= "01";
elsif std_match(d0_g_i, "11100") then d0_g_o <= "10";
elsif std_match(d0_g_i, "11101") then d0_g_o <= "11";
elsif std_match(d0_g_i, "11110") then d0_g_o <= "10";
elsif std_match(d0_g_i, "11111") then d0_g_o <= "11";
end if;
end process;
d1_g: process(d1_g_i) begin
d1_g_o <= (others => '-');
if std_match(d1_g_i, "00000") then d1_g_o <= "0100";
elsif std_match(d1_g_i, "00001") then d1_g_o <= "0000";
elsif std_match(d1_g_i, "00010") then d1_g_o <= "0001";
elsif std_match(d1_g_i, "00011") then d1_g_o <= "0101";
elsif std_match(d1_g_i, "00100") then d1_g_o <= "0010";
elsif std_match(d1_g_i, "00101") then d1_g_o <= "0011";
elsif std_match(d1_g_i, "01000") then d1_g_o <= "0100";
elsif std_match(d1_g_i, "01001") then d1_g_o <= "0000";
elsif std_match(d1_g_i, "01010") then d1_g_o <= "0001";
elsif std_match(d1_g_i, "01011") then d1_g_o <= "0101";
elsif std_match(d1_g_i, "01100") then d1_g_o <= "0010";
elsif std_match(d1_g_i, "01101") then d1_g_o <= "0011";
elsif std_match(d1_g_i, "10000") then d1_g_o <= "0110";
elsif std_match(d1_g_i, "10001") then d1_g_o <= "0111";
elsif std_match(d1_g_i, "10010") then d1_g_o <= "1000";
elsif std_match(d1_g_i, "10011") then d1_g_o <= "1001";
elsif std_match(d1_g_i, "10100") then d1_g_o <= "1010";
elsif std_match(d1_g_i, "10101") then d1_g_o <= "1011";
elsif std_match(d1_g_i, "11000") then d1_g_o <= "1100";
elsif std_match(d1_g_i, "11001") then d1_g_o <= "1101";
elsif std_match(d1_g_i, "11010") then d1_g_o <= "1110";
elsif std_match(d1_g_i, "11011") then d1_g_o <= "1111";
elsif std_match(d1_g_i, "11100") then d1_g_o <= "1111";
elsif std_match(d1_g_i, "11101") then d1_g_o <= "1111";
end if;
end process;
d1_h: process(d1_h_i) begin
d1_h_o <= (others => '-');
if std_match(d1_h_i, "-00000") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "-00001") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "-00010") then d1_h_o <= "00101100";
elsif std_match(d1_h_i, "-00011") then d1_h_o <= "10101100";
elsif std_match(d1_h_i, "-00101") then d1_h_o <= "11001100";
elsif std_match(d1_h_i, "-00111") then d1_h_o <= "11011100";
elsif std_match(d1_h_i, "-01011") then d1_h_o <= "10111100";
elsif std_match(d1_h_i, "001000") then d1_h_o <= "00000000";
elsif std_match(d1_h_i, "001001") then d1_h_o <= "10000110";
elsif std_match(d1_h_i, "001010") then d1_h_o <= "00111001";
elsif std_match(d1_h_i, "001100") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "001101") then d1_h_o <= "10111100";
elsif std_match(d1_h_i, "001110") then d1_h_o <= "00000000";
elsif std_match(d1_h_i, "001111") then d1_h_o <= "00000000";
elsif std_match(d1_h_i, "010000") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "010001") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "010010") then d1_h_o <= "10111100";
elsif std_match(d1_h_i, "010011") then d1_h_o <= "11001100";
elsif std_match(d1_h_i, "010101") then d1_h_o <= "11011100";
elsif std_match(d1_h_i, "010111") then d1_h_o <= "00000000";
elsif std_match(d1_h_i, "011000") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "011001") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "011010") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "011011") then d1_h_o <= "10101100";
elsif std_match(d1_h_i, "011100") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "011101") then d1_h_o <= "00111000";
elsif std_match(d1_h_i, "011110") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "011111") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "101000") then d1_h_o <= "00000000";
elsif std_match(d1_h_i, "101001") then d1_h_o <= "10000110";
elsif std_match(d1_h_i, "101010") then d1_h_o <= "00111001";
elsif std_match(d1_h_i, "101110") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "101111") then d1_h_o <= "10011100";
elsif std_match(d1_h_i, "110000") then d1_h_o <= "00101100";
elsif std_match(d1_h_i, "110001") then d1_h_o <= "10101100";
elsif std_match(d1_h_i, "110011") then d1_h_o <= "10111100";
elsif std_match(d1_h_i, "110101") then d1_h_o <= "11001100";
elsif std_match(d1_h_i, "110111") then d1_h_o <= "11011100";
elsif std_match(d1_h_i, "111000") then d1_h_o <= "00000000";
elsif std_match(d1_h_i, "111001") then d1_h_o <= "10000110";
elsif std_match(d1_h_i, "111010") then d1_h_o <= "00101100";
elsif std_match(d1_h_i, "111011") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "111100") then d1_h_o <= "10000100";
elsif std_match(d1_h_i, "111101") then d1_h_o <= "00011100";
elsif std_match(d1_h_i, "111110") then d1_h_o <= "00111001";
elsif std_match(d1_h_i, "111111") then d1_h_o <= "00011100";
end if;
end process;
end behaviour;
| agpl-3.0 | f4e122e5e95fc35e2e9fda53869f01d7 | 0.573115 | 2.269961 | false | false | false | false |
chastell/art-decomp | kiss/bbtas_hot.vhd | 1 | 3,051 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbtas_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbtas_hot;
architecture behaviour of bbtas_hot is
constant st0: std_logic_vector(5 downto 0) := "100000";
constant st1: std_logic_vector(5 downto 0) := "010000";
constant st2: std_logic_vector(5 downto 0) := "001000";
constant st3: std_logic_vector(5 downto 0) := "000100";
constant st4: std_logic_vector(5 downto 0) := "000010";
constant st5: std_logic_vector(5 downto 0) := "000001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st1; output <= "00";
elsif std_match(input, "10") then next_state <= st1; output <= "00";
elsif std_match(input, "11") then next_state <= st1; output <= "00";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st2; output <= "00";
elsif std_match(input, "10") then next_state <= st2; output <= "00";
elsif std_match(input, "11") then next_state <= st2; output <= "00";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st1; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "00";
elsif std_match(input, "10") then next_state <= st3; output <= "00";
elsif std_match(input, "11") then next_state <= st3; output <= "00";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st4; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "01";
elsif std_match(input, "10") then next_state <= st3; output <= "10";
elsif std_match(input, "11") then next_state <= st3; output <= "11";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st5; output <= "00";
elsif std_match(input, "01") then next_state <= st4; output <= "00";
elsif std_match(input, "10") then next_state <= st4; output <= "00";
elsif std_match(input, "11") then next_state <= st4; output <= "00";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st5; output <= "00";
elsif std_match(input, "10") then next_state <= st5; output <= "00";
elsif std_match(input, "11") then next_state <= st5; output <= "00";
end if;
when others => next_state <= "------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | e8e15319c9442ae19f9ddd367d01450b | 0.583415 | 3.256137 | false | false | false | false |
chastell/art-decomp | kiss/s386_jed.vhd | 1 | 7,731 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s386_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s386_jed;
architecture behaviour of s386_jed is
constant s000000: std_logic_vector(3 downto 0) := "1010";
constant s001100: std_logic_vector(3 downto 0) := "1011";
constant s010010: std_logic_vector(3 downto 0) := "0011";
constant s010000: std_logic_vector(3 downto 0) := "0111";
constant s001000: std_logic_vector(3 downto 0) := "1001";
constant s000100: std_logic_vector(3 downto 0) := "0001";
constant s000011: std_logic_vector(3 downto 0) := "1100";
constant s010001: std_logic_vector(3 downto 0) := "1111";
constant s010011: std_logic_vector(3 downto 0) := "1101";
constant s110000: std_logic_vector(3 downto 0) := "1000";
constant s100000: std_logic_vector(3 downto 0) := "0010";
constant s000010: std_logic_vector(3 downto 0) := "1110";
constant s000001: std_logic_vector(3 downto 0) := "0110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "----11-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----100") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1-101") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0-101") then next_state <= s010000; output <= "0000001";
elsif std_match(input, "----0-0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----011") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----001") then next_state <= s000000; output <= "0000000";
end if;
when s001100 =>
if std_match(input, "-1---00") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---00") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
elsif std_match(input, "-0---10") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---10") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---11") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---11") then next_state <= s000100; output <= "0010000";
end if;
when s001000 =>
if std_match(input, "-----00") then next_state <= s001000; output <= "0000000";
elsif std_match(input, "0----01") then next_state <= s000000; output <= "0101100";
elsif std_match(input, "1----01") then next_state <= s000000; output <= "0101000";
elsif std_match(input, "0----11") then next_state <= s001100; output <= "0101100";
elsif std_match(input, "1----11") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "-----10") then next_state <= s001000; output <= "0000000";
end if;
when s000100 =>
if std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----10") then next_state <= s001100; output <= "0110000";
elsif std_match(input, "-----11") then next_state <= s000100; output <= "0010000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
end if;
when s010010 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000011; output <= "0000000";
end if;
when s000011 =>
if std_match(input, "--01-01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--00-01") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s010001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-1---01") then next_state <= s010011; output <= "0000010";
elsif std_match(input, "-0---01") then next_state <= s010001; output <= "0000010";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s010011 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s110000; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s110000 =>
if std_match(input, "-1---01") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "-0---01") then next_state <= s110000; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s100000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000010; output <= "0000000";
end if;
when s000010 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--10-00") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "--00-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1101") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "--10101") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--00101") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--10001") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--11001") then next_state <= s000010; output <= "0000000";
elsif std_match(input, "--00001") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--01001") then next_state <= s000010; output <= "0000000";
end if;
when s010000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000001; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
end if;
when s000001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0--01") then next_state <= s010000; output <= "0000001";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 5b036bc938e2b008fbec6601c7272757 | 0.591256 | 3.602516 | false | false | false | false |
chastell/art-decomp | kiss/sand_rnd.vhd | 1 | 20,706 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sand_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(8 downto 0)
);
end sand_rnd;
architecture behaviour of sand_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st5: std_logic_vector(4 downto 0) := "00010";
constant st1: std_logic_vector(4 downto 0) := "11011";
constant st2: std_logic_vector(4 downto 0) := "11110";
constant st4: std_logic_vector(4 downto 0) := "11111";
constant st3: std_logic_vector(4 downto 0) := "10001";
constant st31: std_logic_vector(4 downto 0) := "10110";
constant st25: std_logic_vector(4 downto 0) := "01011";
constant st19: std_logic_vector(4 downto 0) := "01111";
constant st6: std_logic_vector(4 downto 0) := "00001";
constant st29: std_logic_vector(4 downto 0) := "10000";
constant st23: std_logic_vector(4 downto 0) := "11010";
constant st17: std_logic_vector(4 downto 0) := "11000";
constant st13: std_logic_vector(4 downto 0) := "01000";
constant st27: std_logic_vector(4 downto 0) := "00100";
constant st21: std_logic_vector(4 downto 0) := "01001";
constant st15: std_logic_vector(4 downto 0) := "00110";
constant st12: std_logic_vector(4 downto 0) := "11100";
constant st10: std_logic_vector(4 downto 0) := "00011";
constant st7: std_logic_vector(4 downto 0) := "10111";
constant st8: std_logic_vector(4 downto 0) := "10011";
constant st9: std_logic_vector(4 downto 0) := "10010";
constant st11: std_logic_vector(4 downto 0) := "00111";
constant st14: std_logic_vector(4 downto 0) := "01100";
constant st16: std_logic_vector(4 downto 0) := "10101";
constant st18: std_logic_vector(4 downto 0) := "10100";
constant st20: std_logic_vector(4 downto 0) := "00000";
constant st22: std_logic_vector(4 downto 0) := "01101";
constant st24: std_logic_vector(4 downto 0) := "00101";
constant st26: std_logic_vector(4 downto 0) := "11001";
constant st28: std_logic_vector(4 downto 0) := "01010";
constant st30: std_logic_vector(4 downto 0) := "01110";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---------";
case current_state is
when st0 =>
if std_match(input, "---------0-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----0----1-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----1---11-") then next_state <= st5; output <= "011001000";
elsif std_match(input, "----1---01-") then next_state <= st1; output <= "11-001000";
end if;
when st1 =>
if std_match(input, "0000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0100---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0100---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0101---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0101---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0110---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0110---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0111---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0111---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1100---0---") then next_state <= st4; output <= "1010-0100";
elsif std_match(input, "1101---0---") then next_state <= st3; output <= "0000-0110";
elsif std_match(input, "1111--10---") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "1111--00---") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st2 =>
if std_match(input, "-------0-0-") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "-------0-10") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----0-00-11") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "----1-00-11") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "------10-11") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st3 =>
if std_match(input, "------10--1") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-----010--0") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "-----110--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "------00--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st4 =>
if std_match(input, "------10-00") then next_state <= st4; output <= "0000-0000";
elsif std_match(input, "------10-01") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "------00-00") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st4; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st3; output <= "11-0-0000";
elsif std_match(input, "------10-1-") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0---00";
end if;
when st5 =>
if std_match(input, "0000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0000-----1-") then next_state <= st31; output <= "010110100";
elsif std_match(input, "0001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0001-----1-") then next_state <= st25; output <= "010110100";
elsif std_match(input, "0010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0010-----1-") then next_state <= st19; output <= "010110100";
elsif std_match(input, "0011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "0100-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0100-----1-") then next_state <= st29; output <= "010110100";
elsif std_match(input, "0101-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0101-----1-") then next_state <= st23; output <= "010110100";
elsif std_match(input, "0110-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0110-----1-") then next_state <= st17; output <= "010110100";
elsif std_match(input, "0111-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0111-----1-") then next_state <= st13; output <= "010110100";
elsif std_match(input, "1000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1000-----1-") then next_state <= st27; output <= "010110100";
elsif std_match(input, "1001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1001-----1-") then next_state <= st21; output <= "010110100";
elsif std_match(input, "1010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1010-----1-") then next_state <= st15; output <= "010110100";
elsif std_match(input, "1011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "1100-------") then next_state <= st12; output <= "101100100";
elsif std_match(input, "1101-------") then next_state <= st10; output <= "011100110";
elsif std_match(input, "1111-------") then next_state <= st7; output <= "011100000";
end if;
when st6 =>
if std_match(input, "----------0") then next_state <= st5; output <= "000100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "000101000";
elsif std_match(input, "----1-0---1") then next_state <= st7; output <= "011101000";
end if;
when st7 =>
if std_match(input, "-----1---1-") then next_state <= st8; output <= "100000000";
elsif std_match(input, "-----0---1-") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "---------0-") then next_state <= st7; output <= "000100000";
end if;
when st8 =>
if std_match(input, "0000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "00111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0110-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0111-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01110----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "10111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11000----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11010----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1111-------") then next_state <= st8; output <= "000000000";
end if;
when st9 =>
if std_match(input, "----------1") then next_state <= st8; output <= "001001000";
elsif std_match(input, "----------0") then next_state <= st8; output <= "000000000";
end if;
when st10 =>
if std_match(input, "------1--10") then next_state <= st11; output <= "---000010";
elsif std_match(input, "------1--00") then next_state <= st10; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st10; output <= "---101000";
end if;
when st11 =>
if std_match(input, "-----0-----") then next_state <= st11; output <= "---000000";
elsif std_match(input, "-----1-----") then next_state <= st5; output <= "011100000";
end if;
when st12 =>
if std_match(input, "------1--10") then next_state <= st5; output <= "001100000";
elsif std_match(input, "------1--00") then next_state <= st12; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st12; output <= "---101000";
end if;
when st13 =>
if std_match(input, "---------0-") then next_state <= st13; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st14; output <= "001100000";
end if;
when st14 =>
if std_match(input, "---------0-") then next_state <= st14; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st15; output <= "010110000";
end if;
when st15 =>
if std_match(input, "---------0-") then next_state <= st15; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st16; output <= "001100000";
end if;
when st16 =>
if std_match(input, "---------0-") then next_state <= st16; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st17; output <= "010110000";
end if;
when st17 =>
if std_match(input, "---------0-") then next_state <= st17; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st18; output <= "001100000";
end if;
when st18 =>
if std_match(input, "---------0-") then next_state <= st18; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st19; output <= "010110000";
end if;
when st19 =>
if std_match(input, "---------0-") then next_state <= st19; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st20; output <= "001100000";
end if;
when st20 =>
if std_match(input, "---------0-") then next_state <= st20; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st21; output <= "010110000";
end if;
when st21 =>
if std_match(input, "---------0-") then next_state <= st21; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st22; output <= "001100000";
end if;
when st22 =>
if std_match(input, "---------0-") then next_state <= st22; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st23; output <= "010110000";
end if;
when st23 =>
if std_match(input, "---------0-") then next_state <= st23; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st24; output <= "001100000";
end if;
when st24 =>
if std_match(input, "---------0-") then next_state <= st24; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st25; output <= "010110000";
end if;
when st25 =>
if std_match(input, "---------0-") then next_state <= st25; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st26; output <= "001100000";
end if;
when st26 =>
if std_match(input, "---------0-") then next_state <= st26; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st27; output <= "010110000";
end if;
when st27 =>
if std_match(input, "---------0-") then next_state <= st27; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st28; output <= "001100000";
end if;
when st28 =>
if std_match(input, "---------0-") then next_state <= st28; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st29; output <= "010110000";
end if;
when st29 =>
if std_match(input, "---------0-") then next_state <= st29; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st30; output <= "001100000";
end if;
when st30 =>
if std_match(input, "---------0-") then next_state <= st30; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st31; output <= "010110000";
end if;
when st31 =>
if std_match(input, "---------0-") then next_state <= st31; output <= "000110000";
elsif std_match(input, "---------10") then next_state <= st5; output <= "100100000";
elsif std_match(input, "------1--11") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "----0-0--11") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0--11") then next_state <= st7; output <= "011101000";
end if;
when others => next_state <= "-----"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 25419be791ffaddfadc4c7221cf212da | 0.56061 | 3.451575 | false | false | false | false |
chastell/art-decomp | kiss/opus_nov.vhd | 1 | 3,496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_nov;
architecture behaviour of opus_nov is
constant init0: std_logic_vector(3 downto 0) := "0001";
constant init1: std_logic_vector(3 downto 0) := "1000";
constant init2: std_logic_vector(3 downto 0) := "1100";
constant init4: std_logic_vector(3 downto 0) := "0011";
constant IOwait: std_logic_vector(3 downto 0) := "0000";
constant RMACK: std_logic_vector(3 downto 0) := "1101";
constant WMACK: std_logic_vector(3 downto 0) := "0010";
constant read0: std_logic_vector(3 downto 0) := "1010";
constant read1: std_logic_vector(3 downto 0) := "1111";
constant write0: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | e39288671da0b4e56cb36cb8d790b8bd | 0.588673 | 3.492507 | false | false | false | false |
es17m014/vhdl-counter | src/old/vhdl/counter_top.vhd | 1 | 2,972 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : counter_top.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Count, BCD code and display it
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity counter_top is
port (
clk_i : in std_logic;
btn_i : in std_logic_vector(3 downto 3);
aen_i : in std_logic_vector(3 downto 0);
a_to_g_o : out std_logic_vector(6 downto 0);
an_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end counter_top;
architecture rtl of counter_top is
component clkdiv
generic(N : integer := 8);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_o : out std_logic_vector(N-1 downto 0)
);
end component clkdiv;
component counter is
generic(N : integer := 14);
port(
clk_i : in std_logic;
reset_i : in std_logic;
digits_o : out std_logic_vector(N-1 downto 0)
);
end component;
component bin2bcd is
port(
digits_i : in std_logic_vector(13 downto 0);
bcd_o : out std_logic_vector(16 downto 0)
);
end component;
component x7seg is
port (
bcd_i : in std_logic_vector(15 downto 0);
clk_i : in std_logic;
reset_i : in std_logic;
aen_i : in std_logic_vector(3 downto 0);
a_to_g_o : out std_logic_vector(6 downto 0);
an_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end component;
signal digits_i : std_logic_vector(15 downto 0);
signal clk_o : std_logic_vector(20 downto 0);
begin
comp1: clkdiv
generic map(N => 21)
port map(
clk_i => clk_i,
reset_i => reset_i,
clk_o => clk_o
);
comp2: counter
generic map (N => 14)
port map(
clk_i => clk_o(25),
reset_i => reset_i,
digits_o => digits_o
);
comp3: bin2bcd
port map (
digits_i => digits_o
bcd_o => bcd_i
);
comp4: x7seg
port map(
bcd_i => bcd_o,
clk_i => clk_i,
reset_i => btn_i(3),
aen_i => aen_i,
a_to_g_o => a_to_g_o,
an_o => an_o,
dp_o => dp_o
);
end rtl; | mit | 2c473fa41266f07717c493119653748d | 0.440781 | 3.834839 | false | false | false | false |
chastell/art-decomp | kiss/s1488_jed.vhd | 1 | 31,464 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1488_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1488_jed;
architecture behaviour of s1488_jed is
constant s000000: std_logic_vector(5 downto 0) := "000000";
constant s001110: std_logic_vector(5 downto 0) := "100001";
constant s011000: std_logic_vector(5 downto 0) := "101000";
constant s010000: std_logic_vector(5 downto 0) := "101100";
constant s010100: std_logic_vector(5 downto 0) := "100000";
constant s110011: std_logic_vector(5 downto 0) := "000001";
constant s010011: std_logic_vector(5 downto 0) := "110101";
constant s000100: std_logic_vector(5 downto 0) := "001100";
constant s100011: std_logic_vector(5 downto 0) := "010001";
constant s010110: std_logic_vector(5 downto 0) := "111000";
constant s010111: std_logic_vector(5 downto 0) := "011000";
constant s000111: std_logic_vector(5 downto 0) := "010011";
constant s101011: std_logic_vector(5 downto 0) := "100110";
constant s001111: std_logic_vector(5 downto 0) := "110110";
constant s111100: std_logic_vector(5 downto 0) := "001011";
constant s101100: std_logic_vector(5 downto 0) := "000011";
constant s001100: std_logic_vector(5 downto 0) := "001101";
constant s010001: std_logic_vector(5 downto 0) := "010110";
constant s011011: std_logic_vector(5 downto 0) := "011100";
constant s110110: std_logic_vector(5 downto 0) := "101010";
constant s011111: std_logic_vector(5 downto 0) := "100111";
constant s101110: std_logic_vector(5 downto 0) := "000100";
constant s010101: std_logic_vector(5 downto 0) := "101101";
constant s111110: std_logic_vector(5 downto 0) := "100011";
constant s000011: std_logic_vector(5 downto 0) := "110000";
constant s111010: std_logic_vector(5 downto 0) := "110010";
constant s011010: std_logic_vector(5 downto 0) := "010000";
constant s111011: std_logic_vector(5 downto 0) := "110001";
constant s100000: std_logic_vector(5 downto 0) := "100010";
constant s101000: std_logic_vector(5 downto 0) := "110100";
constant s110000: std_logic_vector(5 downto 0) := "111100";
constant s011110: std_logic_vector(5 downto 0) := "100100";
constant s010010: std_logic_vector(5 downto 0) := "101110";
constant s001010: std_logic_vector(5 downto 0) := "100101";
constant s000010: std_logic_vector(5 downto 0) := "000010";
constant s111000: std_logic_vector(5 downto 0) := "000111";
constant s100100: std_logic_vector(5 downto 0) := "000101";
constant s001000: std_logic_vector(5 downto 0) := "101001";
constant s001011: std_logic_vector(5 downto 0) := "011010";
constant s110100: std_logic_vector(5 downto 0) := "001001";
constant s100110: std_logic_vector(5 downto 0) := "001000";
constant s011101: std_logic_vector(5 downto 0) := "110011";
constant s000110: std_logic_vector(5 downto 0) := "010101";
constant s110010: std_logic_vector(5 downto 0) := "001010";
constant s011100: std_logic_vector(5 downto 0) := "010010";
constant s101010: std_logic_vector(5 downto 0) := "010100";
constant s100010: std_logic_vector(5 downto 0) := "000110";
constant s100111: std_logic_vector(5 downto 0) := "001110";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-11----") then next_state <= s000000; output <= "0100011010010010111";
elsif std_match(input, "0-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0100011010010010111";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "--00----") then next_state <= s000000; output <= "0000000010000110000";
elsif std_match(input, "--10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "00------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0010100010001110000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---0---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "0010100010001110000";
end if;
when s011000 =>
if std_match(input, "0-10-010") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000010000000000101";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000010000000000100";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000011000011011101";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "0000000000001111101";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "0000000000001111100";
elsif std_match(input, "0-00-000") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "0000010001001101101";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "0000010001001101100";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "0-----01") then next_state <= s000000; output <= "0000001100111010011";
elsif std_match(input, "0-----11") then next_state <= s000000; output <= "0000001100111010010";
elsif std_match(input, "1-----11") then next_state <= s010100; output <= "0000001100111010010";
elsif std_match(input, "1-----01") then next_state <= s010100; output <= "0000001100111010011";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "0000010001001101101";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "0000010001001101100";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "0000010001001101001";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "0000010001001101000";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000011000011011101";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "0000000000001111101";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "0000000000001111100";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "0000000000001111001";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "0000000000001111000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000010000000000001";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000010000000000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000010000000000100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000010000000000101";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000001010001010000";
end if;
when s010011 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0000001010000110011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0000001010000110111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010000110111";
end if;
when s000100 =>
if std_match(input, "11---01-") then next_state <= s100011; output <= "0000001010001010000";
elsif std_match(input, "01---01-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "01---11-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10----1-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "00----1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0-----0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000001010001010000";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000001000011011001";
end if;
when s110011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s000111; output <= "0000001010001010000";
end if;
when s000111 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000001000011011110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000001000011011010";
end if;
when s101011 =>
if std_match(input, "1-------") then next_state <= s001111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s001111 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0001000000101011011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0001000000101011111";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000101011111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001000000101011011";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0100001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "0000010001001101000";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "0000000000001111000";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000010000000000000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010010010111";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "0000010001001101000";
end if;
when s111100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "1-------") then next_state <= s100011; output <= "0000001110001010000";
end if;
when s101100 =>
if std_match(input, "1-------") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010111 =>
if std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000110010010";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000000110010110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110010010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000110010110";
end if;
when s001100 =>
if std_match(input, "1----0--") then next_state <= s010001; output <= "0000001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010001 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011110111";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "0000001000011110111";
elsif std_match(input, "1----0--") then next_state <= s110110; output <= "0000001000011110011";
end if;
when s110110 =>
if std_match(input, "1-------") then next_state <= s011111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110111111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110111110";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110111010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110111011";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110111010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110111011";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110111110";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110111111";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010101 =>
if std_match(input, "1----1--") then next_state <= s111110; output <= "0000001000001111101";
elsif std_match(input, "1----0--") then next_state <= s111110; output <= "0000001000001111001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000001111101";
end if;
when s111110 =>
if std_match(input, "00--1-0-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "01--1-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "10--1--1") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "10--1--0") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--1-11") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "11--0-11") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-10") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--0-10") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "11--1-01") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--0-0-") then next_state <= s000011; output <= "0000001010001010000";
end if;
when s000011 =>
if std_match(input, "1----0-1") then next_state <= s001110; output <= "0000001010010010011";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "0000001010010110011";
elsif std_match(input, "1----1--") then next_state <= s001110; output <= "0000001010010010111";
elsif std_match(input, "0----0-1") then next_state <= s000000; output <= "0000001010010010011";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000001010010010011";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010010010011";
end if;
when s100000 =>
if std_match(input, "00--1---") then next_state <= s000000; output <= "0000101010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "11--1---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000101010001010000";
elsif std_match(input, "11--0---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000001010001010000";
end if;
when s101000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "1-------") then next_state <= s010010; output <= "0000001010000110011";
end if;
when s010010 =>
if std_match(input, "1---0---") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0---0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000001010001010000";
end if;
when s011110 =>
if std_match(input, "0-00-00-") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0--0-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0--1-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "1-0--1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "0000000000001111000";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "0000000000001111001";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "0000010001001101001";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "0000010001001101000";
elsif std_match(input, "1-10-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000010000000000001";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000010000000000000";
elsif std_match(input, "1-11-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0001001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001010 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000001010100010001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
end if;
when s111000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000001010001010000";
elsif std_match(input, "1---00--") then next_state <= s001000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001000; output <= "0000001010001010000";
end if;
when s001000 =>
if std_match(input, "1----0--") then next_state <= s100100; output <= "0000001000011011001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
end if;
when s100100 =>
if std_match(input, "1-------") then next_state <= s001011; output <= "0001001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001011 =>
if std_match(input, "1----0--") then next_state <= s110100; output <= "0000001000011011010";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000001000011011110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0001001010001010000";
end if;
when s011011 =>
if std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000011010111";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000011010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000011010010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000011010011";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000001000011010010";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000001000011010011";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000001000011010110";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000001000011010111";
end if;
when s100110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011101; output <= "0000001010001010000";
end if;
when s011101 =>
if std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110011000";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011001";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110011101";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110011100";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110011101";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110011100";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110011000";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011001";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "0000001000001111001";
end if;
when s000110 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010001010000";
elsif std_match(input, "1---01--") then next_state <= s011000; output <= "0100001010001010000";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0001001010001010000";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0100001010001010000";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0001001010001010000";
end if;
when s011010 =>
if std_match(input, "1----1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000001010100010001";
elsif std_match(input, "1----01-") then next_state <= s110010; output <= "0000001010100010000";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001010100010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s110010 =>
if std_match(input, "1----00-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011100 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000111010111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000111010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000111010011";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000111010010";
elsif std_match(input, "1----10-") then next_state <= s101010; output <= "0000001000111010110";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000001000111010111";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000001000111010011";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000001000111010010";
end if;
when s101010 =>
if std_match(input, "1-------") then next_state <= s111010; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s100010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011010; output <= "0000001010001010000";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "0000001010010110011";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010101010010010111";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0010101010010010111";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000001000011010010";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 618c7b4269658ead6089487d57fe876f | 0.625795 | 3.832866 | false | false | false | false |
chastell/art-decomp | kiss/ex1_rnd.vhd | 1 | 16,310 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_rnd;
architecture behaviour of ex1_rnd is
constant s1: std_logic_vector(4 downto 0) := "11101";
constant s2: std_logic_vector(4 downto 0) := "00010";
constant s4: std_logic_vector(4 downto 0) := "11011";
constant s3: std_logic_vector(4 downto 0) := "11110";
constant s5: std_logic_vector(4 downto 0) := "11111";
constant s6: std_logic_vector(4 downto 0) := "10001";
constant s7: std_logic_vector(4 downto 0) := "10110";
constant s8: std_logic_vector(4 downto 0) := "01011";
constant s9: std_logic_vector(4 downto 0) := "01111";
constant s10: std_logic_vector(4 downto 0) := "00001";
constant s11: std_logic_vector(4 downto 0) := "10000";
constant s12: std_logic_vector(4 downto 0) := "11010";
constant s13: std_logic_vector(4 downto 0) := "11000";
constant s14: std_logic_vector(4 downto 0) := "01000";
constant s15: std_logic_vector(4 downto 0) := "00100";
constant s16: std_logic_vector(4 downto 0) := "01001";
constant s17: std_logic_vector(4 downto 0) := "00110";
constant s18: std_logic_vector(4 downto 0) := "11100";
constant s19: std_logic_vector(4 downto 0) := "00011";
constant s20: std_logic_vector(4 downto 0) := "10111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s1 =>
if std_match(input, "1011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "11-------") then next_state <= s4; output <= "0000000000000000000";
elsif std_match(input, "1000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "1010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "1001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s2 =>
if std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--1----") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-0--0----") then next_state <= s2; output <= "0111100000000000000";
end if;
when s3 =>
if std_match(input, "-0-------") then next_state <= s7; output <= "0111101010000000000";
end if;
when s4 =>
if std_match(input, "-011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "-000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "-010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "-001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s5 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "----100--") then next_state <= s5; output <= "0001000000000000000";
elsif std_match(input, "----110--") then next_state <= s5; output <= "0001000001000000000";
elsif std_match(input, "----101--") then next_state <= s8; output <= "0000000000000000000";
elsif std_match(input, "----111--") then next_state <= s8; output <= "0000000001000000000";
end if;
when s6 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-1-") then next_state <= s9; output <= "0001101001111000000";
elsif std_match(input, "-0--11-0-") then next_state <= s6; output <= "0001000001000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s10; output <= "0001100001111000000";
elsif std_match(input, "-00-10-1-") then next_state <= s9; output <= "0001101000111000000";
elsif std_match(input, "-0--10-0-") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-01-10-1-") then next_state <= s10; output <= "0001100000111000000";
end if;
when s7 =>
if std_match(input, "-0--0----") then next_state <= s7; output <= "0111101000000000000";
elsif std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-1----") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-01-1----") then next_state <= s12; output <= "0001000000000000000";
end if;
when s8 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000110000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000110000";
end if;
when s9 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s13; output <= "0001100011001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s9; output <= "0001001001001000000";
elsif std_match(input, "-00-11-1-") then next_state <= s14; output <= "0001101011001001000";
elsif std_match(input, "-01-10-1-") then next_state <= s13; output <= "0001100010001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s9; output <= "0001001000001000000";
elsif std_match(input, "-00-10-1-") then next_state <= s14; output <= "0001101010001001000";
end if;
when s10 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s15; output <= "0001100001001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s10; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s15; output <= "0001100000001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s10; output <= "0001000000001000000";
end if;
when s11 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011011000110";
elsif std_match(input, "-00-11-0-") then next_state <= s11; output <= "0001001001000000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011011000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011011000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011011000010";
elsif std_match(input, "-01-11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010011000110";
elsif std_match(input, "-00-10-0-") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010011000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010011000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010011000010";
elsif std_match(input, "-01-10-0-") then next_state <= s12; output <= "0001000000000000000";
end if;
when s12 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001011000110";
elsif std_match(input, "-0--11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001011000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000011000110";
elsif std_match(input, "-0--10-0-") then next_state <= s12; output <= "0001000000000000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000011000010";
end if;
when s13 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s13; output <= "0001000001001000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001001000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s13; output <= "0001000000001000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000001000010";
end if;
when s14 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s14; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s14; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s15 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-0-") then next_state <= s15; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s15; output <= "0001000000001000000";
end if;
when s16 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s16; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s16; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s17 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s18; output <= "0001000000001000001";
end if;
when s18 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s19; output <= "0011100001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s18; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s19; output <= "0011100000000000000";
end if;
when s19 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s19; output <= "0001000001000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s20; output <= "0000000001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s19; output <= "0001000000000000000";
elsif std_match(input, "-0--10-1-") then next_state <= s20; output <= "0000000000000000000";
end if;
when s20 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000100000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000100000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 817231707c40e08d74c189ec12df24cb | 0.610791 | 3.630899 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-09C.vhd | 1 | 9,691 | ---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-09C.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console input and output translation circuitry and
-- Control Character detection
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY n1050_TRANSLATE IS
port
(
-- Inputs
DATA_REG_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 10C
RDR_ON_LCH : IN STD_LOGIC; -- 10BD3
PUNCH_1_CLUTCH_1050 : IN STD_LOGIC; -- 10DD5 aka PCH_1_CLUTCH_1050
HOME_RDR_STT_LCH : IN STD_LOGIC; -- 10BB3
CLOCK_STT_RST : IN STD_LOGIC; -- 10AC2
RST_ATTACH : IN STD_LOGIC; -- 10BC2
W_TIME, X_TIME, Y_TIME, Z_TIME : IN STD_LOGIC; -- 10AXX
n1050_RST : IN STD_LOGIC; -- 10BA3
ALLOW_STROBE : IN STD_LOGIC; -- 10CB6
PROCEED_LCH : IN STD_LOGIC; -- 10BC3
SHARE_REQ_RST : IN STD_LOGIC; -- 10BB6
CE_RUN_MODE : IN STD_LOGIC; -- 10DB2
CE_TI_DECODE : IN STD_LOGIC; -- 10DB2
SET_LOWER_CASE : IN STD_LOGIC; -- 10CC5
n1050_RST_LCH : IN STD_LOGIC; -- 10BA3
READY_SHARE : IN STD_LOGIC; -- 10CE6
-- Outputs
TT2_POS_END : OUT STD_LOGIC; -- 10BD3
XLATE_UC : OUT STD_LOGIC; -- 10C
RD_SHARE_REQ_LCH : OUT STD_LOGIC; -- 10CD4 10BC3 10BD4
READ_SHARE_REQ : OUT STD_LOGIC; -- 10BD3
WRITE_UC : OUT STD_LOGIC; -- 10DD2
SET_SHIFT_LCH : OUT STD_LOGIC; -- 10CC4
PCH_1_HOME : OUT STD_LOGIC; -- 10DC5
RUN : OUT STD_LOGIC; -- 10BB3 10CC3 10BD1 10CE4 10CD2
UNGATED_RUN : OUT STD_LOGIC; -- 10BC4
READ : OUT STD_LOGIC; -- 10CD4
READ_INQ : OUT STD_LOGIC; -- 10CD4
LC_CHARACTER, UC_CHARACTER : OUT STD_LOGIC; -- 10CC5
WRITE_LCH : OUT STD_LOGIC; -- 10BD3 10AC1 10AA2 10BB1 10CA5 10CC3
WRITE_MODE : OUT STD_LOGIC; -- 10CD4
WRITE_STROBE : OUT STD_LOGIC; -- 10DC5
WRITE_LCH_RST : OUT STD_LOGIC; -- 10BA1
RD_OR_RD_INQ : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS
-- Clocks
-- T1,T2,T3,T4 : IN STD_LOGIC;
-- P1,P2,P3,P4 : IN STD_LOGIC
);
END n1050_TRANSLATE;
ARCHITECTURE FMD OF n1050_TRANSLATE IS
signal sLC_CHARACTER, sUC_CHARACTER : STD_LOGIC;
signal DataReg4511, DataReg23not00 : STD_LOGIC;
signal EndCode : STD_LOGIC;
signal DataRegSpecial1, DataRegSpecial2, DataRegSpecial3, DataRegSpecial : STD_LOGIC;
signal XLATE_UC_SET, XLATE_UC_RESET : STD_LOGIC;
signal RD_SHARE_REQ_SET, RD_SHARE_REQ_RESET : STD_LOGIC;
signal PREFIX_SET,PREFIX_RESET,PREFIX : STD_LOGIC;
signal BLOCK_SHIFT_SET,BLOCK_SHIFT : STD_LOGIC;
signal sWRITE_LCH : STD_LOGIC;
signal UPPER_CASE_DECODE, LOWER_CASE_DECODE : STD_LOGIC;
signal sRD_SHARE_REQ_LCH : STD_LOGIC;
signal sREAD, sREAD_INQ, sRD_OR_RD_INQ : STD_LOGIC;
signal DataReg01xxxxxx, DataRegLCA, DataRegLCB, DataRegLCC, DataRegLCD, DataRegLCE : STD_LOGIC;
signal DataRegLC, DataRegUC : STD_LOGIC;
signal PRT_IN_UC_SET, PRT_IN_UC_RESET, PRT_IN_UC : STD_LOGIC;
signal WRITE_SET, WRITE_RESET : STD_LOGIC;
signal sUNGATED_RUN : STD_LOGIC;
BEGIN
-- Fig 5-09C
-- Incoming character handling (keyboard codes AB8421 = 234567)
DataReg4511 <= DATA_REG_BUS(4) and DATA_REG_BUS(5); -- AC3F4 AC3D4 XX11XX
DataReg23not00 <= DATA_REG_BUS(2) or DATA_REG_BUS(3); -- AC3B6 01XXXX 10XXXX 11XXXX
-- EndCode <= DATA_REG_BUS(1) and DataReg4511 and not DATA_REG_BUS(2) and DATA_REG_BUS(6); -- 10x111x = EOB
EndCode <= '1' when DATA_REG_BUS="0000100" else '0'; -- End is 04=Ctrl+D
TT2_POS_END <= (EndCode and sRD_SHARE_REQ_LCH) or READY_SHARE; -- AC3F7 AC3F2 AC3C7 ?? *or* READY_SHARE ??
-- UPPER_CASE_DECODE <= not DATA_REG_BUS(7) and DATA_REG_BUS(6) and DataReg4511 and not DataReg23not00; -- AC3E2 AB8421=001110=Upshift
UPPER_CASE_DECODE <= '0';
-- LOWER_CASE_DECODE <= DATA_REG_BUS(6) and not DATA_REG_BUS(7) and DATA_REG_BUS(2) and DATA_REG_BUS(3) and DataReg4511; -- AC3F7 AB8421=111110=Downshift
LOWER_CASE_DECODE <= '0';
-- The following three lines are probably wrong
DataRegSpecial1 <= DataReg23not00 and DataReg4511 and DATA_REG_BUS(6) and DATA_REG_BUS(7); -- AC3E2 "xx1111" but not "111111"
DataRegSpecial2 <= DataReg4511 and DATA_REG_BUS(7) and not DataReg23not00 and not DATA_REG_BUS(6); -- AC3E2 "101101" = Return
DataRegSpecial3 <= DataReg4511 and not DATA_REG_BUS(6) and not DATA_REG_BUS(7); -- AC3B6 "xx1100"
-- DataRegSpecial <= DataRegSpecial1 or DataRegSpecial2 or DataRegSpecial3;
DataRegSpecial <= '0'; -- Ignore for now
XLATE_UC_SET <= UPPER_CASE_DECODE and X_TIME; -- AC3F2
XLATE_UC_RESET <= SET_LOWER_CASE or (X_TIME and LOWER_CASE_DECODE); -- AC3F2
XLATE_UC_FL: entity FLL port map (S=>XLATE_UC_SET, R=>XLATE_UC_RESET, Q=>XLATE_UC); -- ?????
RD_SHARE_REQ_SET <= not DataRegSpecial and not UPPER_CASE_DECODE and not LOWER_CASE_DECODE and sRD_OR_RD_INQ and Y_TIME;
RD_SHARE_REQ_RESET <= SHARE_REQ_RST or RST_ATTACH or (CE_RUN_MODE and CE_TI_DECODE);
RD_SHARE_REQ_FL: entity FLL port map(S=>RD_SHARE_REQ_SET, R=>RD_SHARE_REQ_RESET, Q=>sRD_SHARE_REQ_LCH); -- AC3F5 AC3C7
RD_SHARE_REQ_LCH <= sRD_SHARE_REQ_LCH;
READ_SHARE_REQ <= sRD_SHARE_REQ_LCH and not Y_TIME; -- AC3E3
sREAD <= HOME_RDR_STT_LCH and RDR_ON_LCH and not sWRITE_LCH; -- AC2G7
READ <= sREAD;
sREAD_INQ <= not sWRITE_LCH and RDR_ON_LCH and PROCEED_LCH; -- AC2G7
READ_INQ <= sREAD_INQ;
sRD_OR_RD_INQ <= sREAD or sREAD_INQ;
RD_OR_RD_INQ <= sRD_OR_RD_INQ;
PCH_1_HOME <= PUNCH_1_CLUTCH_1050 or sREAD or sREAD_INQ; -- AC2G3
-- Outgoing character handling
-- Prefix is 0x100111 i.e. 27 or 67
PREFIX_SET <= not DATA_REG_BUS(0) and DATA_REG_BUS(2) and not DATA_REG_BUS(3)
and not DATA_REG_BUS(4) and DATA_REG_BUS(5) and DATA_REG_BUS(6) and DATA_REG_BUS(7) and Z_TIME; -- AC3B7 AC3F2 AC3D6
PREFIX_FL: entity FLL port map(S=>PREFIX_SET,R=>Y_TIME,Q=>PREFIX); -- AC3F2 AC3G5
-- Block Shift prevents the shift mechanism from being triggered
BLOCK_SHIFT_SET <= PREFIX and X_TIME;
BLOCK_SHIFT_FL: entity FLL port map(S=>BLOCK_SHIFT_SET,R=>W_TIME,Q=>BLOCK_SHIFT); -- AC3F2 AC3C6
DataReg01xxxxxx <= not DATA_REG_BUS(0) and DATA_REG_BUS(1); -- AC3D5 AC3B4
DataRegLCA <= not DATA_REG_BUS(5) and DATA_REG_BUS(7) and DataReg01xxxxxx; -- 01xxx0x1 = 01xx0001 "/" 01xx0011 01xx1001 01xx1011 ".$,#"
DataRegLCB <= not DATA_REG_BUS(4) and not DATA_REG_BUS(6) and DataReg01xxxxxx; -- 01xx0x0x = 01xx0000 "-&" 01xx0001 "/" 01xx0100 01xx0101
DataRegLCC <= DATA_REG_BUS(0) and DATA_REG_BUS(1) and DATA_REG_BUS(2) and DATA_REG_BUS(3); -- AC3F5 1111xxxx = 0-9 = LC
DataRegLCD <= DATA_REG_BUS(2) and DATA_REG_BUS(3) and not DATA_REG_BUS(6) and not DATA_REG_BUS(7)
and DataReg01xxxxxx; -- AC3B7 0111xx00 = 01110000 01110100 01111000 01111100 "@"
DataRegLCE <= DATA_REG_BUS(0) and not DATA_REG_BUS(1); -- AC3E5 10xxxxxx = LC
DataRegLC <= DataRegLCA or DataRegLCB or DataRegLCC or DataRegLCD or DataRegLCE;
DataRegUC <= not DataRegLC and DATA_REG_BUS(1);
sLC_CHARACTER <= DataRegLC and not BLOCK_SHIFT;
LC_CHARACTER <= sLC_CHARACTER;
sUC_CHARACTER <= DataRegUC and not BLOCK_SHIFT;
UC_CHARACTER <= sUC_CHARACTER;
-- PRT_IN_UC remembers whether the printer is already in UC mode
PRT_IN_UC_SET <= sUC_CHARACTER and Z_TIME and ALLOW_STROBE;
PRT_IN_UC_RESET <= (sLC_CHARACTER and Z_TIME and ALLOW_STROBE) or SET_LOWER_CASE; -- AC3F4
PRINT_IN_UC_FL: entity FLL port map(S=>PRT_IN_UC_SET,R=>PRT_IN_UC_RESET,Q=>PRT_IN_UC); -- ?????
WRITE_UC <= PRT_IN_UC;
-- For now the SHIFT function is disabled as it is not required for ASCII output
-- SET_SHIFT_LCH <= not ((PRT_IN_UC and sLC_CHARACTER and sWRITE_LCH) or (sUC_CHARACTER and sWRITE_LCH and not PRT_IN_UC)); -- AC2E5 AC3D4
SET_SHIFT_LCH <= '0';
WRITE_SET <= not RDR_ON_LCH and not PUNCH_1_CLUTCH_1050 and HOME_RDR_STT_LCH; -- AC2G7
WRITE_RESET <= CLOCK_STT_RST or RST_ATTACH;
WRITE_FL : entity FLL port map(S=>WRITE_SET,R=>WRITE_RESET,Q=>sWRITE_LCH); -- AC2J5 AC2H6
WRITE_LCH <= sWRITE_LCH;
WRITE_LCH_RST <= sWRITE_LCH;
WRITE_MODE <= WRITE_SET and not n1050_RST; -- AC2D7
WRITE_STROBE <= Z_TIME and ALLOW_STROBE and sWRITE_LCH; -- AC2K6
-- Stuff common to input and output
sUNGATED_RUN <= sREAD_INQ or sREAD or sWRITE_LCH; -- AC2G3
UNGATED_RUN <= sUNGATED_RUN;
RUN <= sUNGATED_RUN and not n1050_RST_LCH; -- AC2K5 AC2H6
END FMD;
| gpl-3.0 | 20ed73332608d2a4e59a7c5414cecbae | 0.670725 | 2.794406 | false | false | false | false |
thommyj/slotcar | de0/uart_controller.vhd | 1 | 5,623 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity uart_controller is
port(
clk : in std_logic;
rst : in std_logic;
rts_screen : out std_logic;
datarec_screen : in std_logic;
data_from_screen : in std_logic_vector(7 downto 0);
data_to_screen : out std_logic_vector(7 downto 0);
write_address : out std_logic_vector(7 downto 0);
write_data : out std_logic_vector(7 downto 0);
write_en : out std_logic;
read_req : out std_logic;
read_address : out std_logic_vector(7 downto 0);
read_data : in std_logic_vector(7 downto 0);
read_data_valid : in std_logic;
rts_track : out std_logic;
datarec_track : in std_logic;
data_from_track : in std_logic_vector(7 downto 0);
data_to_track : out std_logic_vector(7 downto 0)
);
end entity uart_controller;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of uart_controller is
type uartstate_type is (IDLE, SEND_TO_SCREEN, SEND_TO_TRACK);
signal uartstate : uartstate_type;
signal address : integer;
begin
read_address <= std_logic_vector(to_unsigned(address, read_address'length));
write_address <= std_logic_vector(to_unsigned(address, write_address'length));
--
-- sample uart data
--
process(clk,rst)
begin
if rst = '1' then
uartstate <= IDLE;
rts_screen <= '0';
rts_track <= '0';
address <= 0;
write_en <= '0';
read_req <= '0';
elsif rising_edge(clk) then
rts_screen <= '0';
rts_track <= '0';
write_en <= '0';
read_req <= '0';
case uartstate is
when IDLE =>
if datarec_screen = '1' then
uartstate <= SEND_TO_TRACK;
read_req <= '1';
write_en <= '1';
write_data <= data_from_screen;
--address <= address + 1;
elsif datarec_track = '1' then
uartstate <= SEND_TO_SCREEN;
read_req <= '1';
write_en <= '1';
write_data <= data_from_track;
--address <= address + 1;
end if;
when SEND_TO_TRACK =>
if (read_data_valid = '1') then
uartstate <= IDLE;
rts_track <= '1';
data_to_track <= read_data;
address <= address + 1;
if (address = 23) then
address <= 0;
end if;
end if;
when SEND_TO_SCREEN =>
if (read_data_valid = '1') then
uartstate <= IDLE;
rts_screen <= '1';
data_to_screen <= read_data;
address <= address + 1;
if (address = 23) then
address <= 0;
end if;
end if;
end case;
end if;
end process;
end architecture syn;
-- *** EOF ***
| mit | 66f4f4b8a0afcaf6060dbffc8439e6ae | 0.499911 | 4.128488 | false | false | false | false |
lyn1337/LinuxDSc2 | toolchain/ndstool/source/passme.vhd | 3 | 3,058 | -- standard libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PassMe is
port
(
DSSLOT_CLK : in std_logic;
DSSLOT_ROMCS : in std_logic;
DSSLOT_RESET : in std_logic;
DSSLOT_EEPCS : in std_logic;
DSSLOT_IRQ : out std_logic;
DSSLOT_IO : inout std_logic_vector(7 downto 0);
DSCART_CLK : out std_logic;
DSCART_ROMCS : out std_logic;
DSCART_RESET : out std_logic;
DSCART_EEPCS : out std_logic;
DSCART_IRQ : in std_logic;
DSCART_IO : inout std_logic_vector(7 downto 0);
LED0 : out std_logic
);
end entity;
architecture rtl of passme is
-- removes Xilinx mapping errors
attribute CLOCK_BUFFER : string;
attribute CLOCK_BUFFER of DSSLOT_CLK: signal is "ibuf";
attribute CLOCK_BUFFER of DSCART_CLK: signal is "obuf";
signal is_command : boolean;
signal cmddata_cnt : natural range 0 to 511; -- 8 + 504
signal patched_data : std_logic_vector(7 downto 0);
signal patch_en : boolean;
begin
-- direct passthrough
DSCART_CLK <= DSSLOT_CLK;
DSCART_ROMCS <= DSSLOT_ROMCS;
DSCART_RESET <= DSSLOT_RESET;
DSSLOT_IRQ <= DSCART_IRQ;
DSCART_EEPCS <= DSSLOT_EEPCS;
-- activity LED
LED0 <= not DSSLOT_ROMCS;
-- patch
process (cmddata_cnt)
begin
case (cmddata_cnt - 8) is
--! ALL PATCHES ARE TO BE GENERATED HERE
when others => patched_data <= DSCART_IO;
end case;
end process;
-- dataswitcher
process (DSSLOT_RESET, DSSLOT_ROMCS, DSSLOT_EEPCS, DSSLOT_IO, DSCART_IO, patched_data)
begin
DSSLOT_IO <= (others => 'Z'); -- default is high impedance
DSCART_IO <= (others => 'Z'); -- default is high impedance
if (DSSLOT_RESET='1') then -- if not reset
if (DSSLOT_ROMCS='0') then -- ROM is selected
if (is_command) then -- is command byte
DSCART_IO <= DSSLOT_IO; -- from DS to cartridge
else -- is data byte
if (patch_en) then -- patch enabled
DSSLOT_IO <= patched_data;
else
DSSLOT_IO <= DSCART_IO;
end if;
end if;
elsif (DSSLOT_EEPCS='0') then -- EEPROM is selected
DSCART_IO(7) <= DSSLOT_IO(7); -- pass serial data
DSSLOT_IO(6) <= DSCART_IO(6); -- pass serial data in opposite direction
end if;
end if;
end process;
-- patch_en
process (DSSLOT_RESET, DSSLOT_CLK)
begin
if (DSSLOT_RESET='0') then
patch_en <= true; -- patch header
elsif (rising_edge(DSSLOT_CLK)) then
if (is_command) then
if (DSCART_IO(5) = '1') then -- detect 3C command, assume other command bytes are 00
patch_en <= false; -- do not patch other data
end if;
end if;
end if;
end process;
-- cmddata_cnt, is_command
process (DSSLOT_ROMCS, DSSLOT_CLK)
begin
if (DSSLOT_ROMCS='1') then
cmddata_cnt <= 0; -- new transfer
is_command <= true; -- start with command
elsif (rising_edge(DSSLOT_CLK)) then
if (cmddata_cnt mod 8 = 7) then
is_command <= false; -- next byte is data
end if;
cmddata_cnt <= cmddata_cnt + 1; -- next byte
end if;
end process;
end architecture;
| gpl-2.0 | 04be91505899c6ce842b8ad9c617b314 | 0.646501 | 2.855275 | false | false | false | false |
ibm2030/IBM2030 | vga_controller_640_60.vhd | 1 | 9,420 | ------------------------------------------------------------------------
-- vga_controller_640_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic to generate the synchronization signals,
-- horizontal and vertical pixel counter and video disable signal
-- for the 640x480@60Hz resolution.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web regarding the
-- vga video timings:
-- http://www.epanorama.net/documents/pc/vga_timing.html
-- This module generates the video synch pulses for the monitor to
-- enter 640x480@60Hz resolution state. It also provides horizontal
-- and vertical counters for the currently displayed pixel and a blank
-- signal that is active when the pixel is not inside the visible screen
-- and the color outputs should be reset to 0.
-- timing diagram for the horizontal synch signal (HS)
-- 0 648 744 800 (pixels)
-- -------------------------|______|-----------------
-- timing diagram for the vertical synch signal (VS)
-- 0 482 484 525 (lines)
-- -----------------------------------|______|-------
-- The blank signal is delayed one pixel clock period (40ns) from where
-- the pixel leaves the visible screen, according to the counters, to
-- account for the pixel pipeline delay. This delay happens because
-- it takes time from when the counters indicate current pixel should
-- be displayed to when the color data actually arrives at the monitor
-- pins (memory read delays, synchronization delays).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- rst - global reset signal
-- pixel_clk - input pin, from dcm_25MHz
-- - the clock signal generated by a DCM that has
-- - a frequency of 25MHz.
-- HS - output pin, to monitor
-- - horizontal synch pulse
-- VS - output pin, to monitor
-- - vertical synch pulse
-- hcount - output pin, 11 bits, to clients
-- - horizontal count of the currently displayed
-- - pixel (even if not in visible area)
-- vcount - output pin, 11 bits, to clients
-- - vertical count of the currently active video
-- - line (even if not in visible area)
-- blank - output pin, to clients
-- - active when pixel is not in visible area.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the vga_controller_640_60 entity declaration
-- read above for behavioral description and port definitions.
entity vga_controller_640_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
hcount : out std_logic_vector(10 downto 0);
vcount : out std_logic_vector(10 downto 0);
hchar : out std_logic_vector(10 downto 0);
vchar : out std_logic_vector(10 downto 0);
hpixel : out std_logic_vector(5 downto 0);
vpixel : out std_logic_vector(5 downto 0);
blank : out std_logic
);
end vga_controller_640_60;
architecture Behavioral of vga_controller_640_60 is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- number of horizontal pixels per character
constant HPIX : std_logic_vector(5 downto 0) := "010011"; -- 19
-- number of vertical pixels per character
constant VPIX : std_logic_vector(5 downto 0) := "010011"; -- 19
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01000001101"; -- 525
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01010001000"; -- 648
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01011101000"; -- 744
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "00111100010"; -- 482
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "00111100100"; -- 484
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '0';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
signal hch : std_logic_vector(10 downto 0) := (others => '0');
signal vch : std_logic_vector(10 downto 0) := (others => '0');
signal hpx : std_logic_vector(5 downto 0) := (others => '0');
signal vpx : std_logic_vector(5 downto 0) := (others => '0');
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
-- output horizontal and vertical counters
hcount <= hcounter;
vcount <= vcounter;
hpixel <= hpx;
vpixel <= vpx;
hchar <= hch;
vchar <= vch;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
hch <= (others => '0');
hpx <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
hch <= (others => '0');
hpx <= (others => '0');
else
hcounter <= hcounter + 1;
if(hpx=HPIX) then
hpx <= (others => '0');
hch <= hch + 1;
else
hpx <= hpx + 1;
end if;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
vch <= (others => '0');
vpx <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
vch <= (others => '0');
vpx <= (others => '0');
else
vcounter <= vcounter + 1;
if(vpx=VPIX) then
vpx <= (others => '0');
vch <= vch + 1;
else
vpx <= vpx + 1;
end if;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 96 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 2 video lines
-- = 2*HMAX = 1600 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
end Behavioral; | gpl-3.0 | 96abae13584496af1c336df23cb87881 | 0.545966 | 4.401869 | false | false | false | false |
TheMassController/VHDL_experimenting | project/UART/uart_receiv.vhd | 1 | 17,934 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Handles the incoming data.
-- A note about parity:
-- 0: odd parity
-- 1: even parity
-- 2: always 0 parity
-- 3: always 1 parity
-- if parity_bit is false, this parameter is ignored
entity uart_receiv is
generic (
baudrate : Natural;
clk_freq : Natural;
parity_bit_in : boolean;
parity_bit_in_type : Natural range 0 to 3;
bit_count_in : Natural range 5 to 9;
stop_bits_in : Natural range 1 to 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
uart_rx : in STD_LOGIC;
received_data : out STD_LOGIC_VECTOR(8 DOWNTO 0);
data_ready : out STD_LOGIC; -- Signals that data has been received.
parity_error : out STD_LOGIC; -- Signals that the parity check has failed, is zero if there was none
data_error : out STD_LOGIC -- Signals that data receiving has encoutered errors
);
end uart_receiv;
architecture Behavioral of uart_receiv is
type state_type is (rst_state, wait_start,
start_start, start_bit_one, start_bit_two, start_end,
bit_start, bit_read_one, bit_read_two, bit_end,
parity_start, parity_read_one, parity_read_two, parity_end,
stop_start, stop_bit_one, stop_bit_two, stop_bit_two_final, stop_end);
constant oversampling : Natural := 4;
constant receiveSpeed : integer := integer(clk_freq/(baudrate*oversampling));
signal recv_ticker_rst : STD_LOGIC := '1';
signal recv_ticker_done : STD_LOGIC;
signal state : state_type := rst_state;
signal sub_rst : boolean := false;
signal barrel_data_in : STD_LOGIC := '0';
signal barrel_enable : boolean := false;
signal data_error_b1_in : STD_LOGIC := '0';
signal data_error_b1_en : boolean := false;
signal data_error_b2_in : STD_LOGIC := '0';
signal data_error_b2_en : boolean := false;
signal data_error_ref : STD_LOGIC := '0';
signal parity_test : boolean := false;
signal parity_ref : STD_LOGIC := '0';
signal ready_enable : boolean := false;
function simple_state_transition(if0: state_type; if1 : state_type; var: STD_LOGIC) return state_type is
begin
if var = '1' then
return if1;
else
return if0;
end if;
end simple_state_transition;
begin
receive_ticker : entity work.simple_multishot_timer
generic map (
match_val => receiveSpeed
)
port map (
clk => clk,
rst => recv_ticker_rst,
done => recv_ticker_done
);
data_shifter : process(clk, sub_rst)
variable last_known_enable : boolean := false;
variable last_known_data : STD_LOGIC := '0';
variable barrel_data : STD_LOGIC_VECTOR(bit_count_in-1 DOWNTO 0) := (others => '0');
begin
if sub_rst then
last_known_enable := false;
last_known_data := '0';
barrel_data := (others => '0');
elsif rising_edge(clk) then
if barrel_enable then
last_known_enable := true;
last_known_data := barrel_data_in;
else
if last_known_enable then
last_known_enable := false;
barrel_data := last_known_data & barrel_data(bit_count_in-1 DOWNTO 1);
end if;
end if;
end if;
received_data( 8 DOWNTO bit_count_in) <= (others => '0');
received_data( bit_count_in-1 DOWNTO 0) <= barrel_data;
end process;
data_error_tester : process(clk, sub_rst)
variable last_known_b1in : STD_LOGIC := '0';
variable data_error_out : STD_LOGIC := '0';
begin
if sub_rst then
last_known_b1in := '0';
data_error_out := '0';
elsif rising_edge(clk) then
if data_error_b1_en then
last_known_b1in := data_error_b1_in;
end if;
if data_error_b2_en then
if last_known_b1in /= data_error_b2_in or data_error_ref /= data_error_b2_in then
data_error_out := '1';
end if;
end if;
end if;
data_error <= data_error_out;
end process;
parity_tester : process(clk, sub_rst)
variable last_known_enable : boolean := false;
variable last_known_data : STD_LOGIC := '0';
variable parity_error_out : STD_LOGIC := '0';
variable parity_ref_reg : STD_LOGIC := '0';
variable even : STD_LOGIC := '1';
begin
if sub_rst then
last_known_enable := false;
last_known_data := '0';
parity_error_out := '0';
even := '1';
elsif rising_edge(clk) then
if barrel_enable then
last_known_enable := true;
last_known_data := barrel_data_in;
else
if last_known_enable then
last_known_enable := false;
if last_known_data = '1' then
even := not even;
end if;
end if;
end if;
if parity_test then
case parity_bit_in_type is
when 0 =>
parity_error_out := even xnor parity_ref;
when 1 =>
parity_error_out := even xor parity_ref;
when 2 =>
parity_error_out := parity_ref;
when 3 =>
parity_error_out := not parity_ref;
when others =>
parity_error_out := '1';
end case;
end if;
end if;
parity_error <= parity_error_out;
end process;
ready_lock : process (clk, sub_rst)
variable ready_out : STD_LOGIC := '0';
begin
if sub_rst then
ready_out := '0';
elsif rising_edge(clk) then
if ready_enable then
ready_out := '1';
end if;
end if;
data_ready <= ready_out;
end process;
-- State transitions
process(clk, rst)
-- State transition control variables
variable bits_processed : natural := 0;
variable stop_bits_processed : natural := 0;
begin
if rst = '1' then
state <= rst_state;
elsif rising_edge(clk) then
case state is
-- rst_state, wait_start,
when rst_state =>
bits_processed := 0;
stop_bits_processed := 0;
state <= wait_start;
when wait_start =>
bits_processed := 0;
stop_bits_processed := 0;
state <= simple_state_transition(start_start, wait_start, uart_rx);
-- start_start, start_bit_one, start_bit_two, start_end,
when start_start =>
state <= simple_state_transition(start_start, start_bit_one, recv_ticker_done);
when start_bit_one =>
state <= simple_state_transition(start_bit_one, start_bit_two, recv_ticker_done);
when start_bit_two =>
state <= simple_state_transition(start_bit_two, start_end, recv_ticker_done);
when start_end =>
state <= simple_state_transition(start_end, bit_start, recv_ticker_done);
--bit_start, bit_read_one, bit_read_two, bit_end,
when bit_start =>
state <= simple_state_transition(bit_start, bit_read_one, recv_ticker_done);
when bit_read_one =>
state <= simple_state_transition(bit_read_one, bit_read_two, recv_ticker_done);
when bit_read_two =>
state <= simple_state_transition(bit_read_two, bit_end, recv_ticker_done);
when bit_end =>
if recv_ticker_done = '1' then
bits_processed := bits_processed + 1;
if bits_processed = bit_count_in then
if parity_bit_in then
state <= parity_start;
else
state <= stop_start;
end if;
else
state <= bit_start;
end if;
else
state <= bit_end;
end if;
-- parity_start, parity_read_one, parity_read_two, parity_end,
when parity_start =>
state <= simple_state_transition(parity_start, parity_read_one, recv_ticker_done);
when parity_read_one =>
state <= simple_state_transition(parity_read_one, parity_read_two, recv_ticker_done);
when parity_read_two =>
state <= simple_state_transition(parity_read_two, parity_end, recv_ticker_done);
when parity_end =>
state <= simple_state_transition(parity_end, stop_start, recv_ticker_done);
-- stop_start, stop_read_one, stop_read_two, stop_end);
when stop_start =>
state <= simple_state_transition(stop_start, stop_bit_one, recv_ticker_done);
when stop_bit_one =>
if stop_bits_processed = stop_bits_in - 1 then
state <= simple_state_transition(stop_bit_one, stop_bit_two_final, recv_ticker_done);
else
state <= simple_state_transition(stop_bit_one, stop_bit_two, recv_ticker_done);
end if;
when stop_bit_two =>
if recv_ticker_done = '1' then
stop_bits_processed := stop_bits_processed + 1;
state <= stop_end;
else
state <= stop_bit_two;
end if;
when stop_bit_two_final =>
state <= simple_state_transition(stop_bit_two_final, wait_start, recv_ticker_done);
when stop_end =>
state <= simple_state_transition(stop_end, stop_start, recv_ticker_done);
when others =>
state <= rst_state;
end case;
end if;
end process;
process(state, uart_rx)
begin
case state is
when rst_state =>
-- Signal assignments
recv_ticker_rst <= '1';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= true;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= '0';
data_error_b2_en <= false;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when wait_start =>
-- Signal assignments
recv_ticker_rst <= '1';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= '0';
data_error_b2_en <= false;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when start_start =>
-- Signal assignments
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= true;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= '0';
data_error_b2_en <= false;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when start_end|bit_start|bit_end|parity_start|parity_end|stop_start|stop_end =>
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= '0';
data_error_b2_en <= false;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when start_bit_one|bit_read_one|parity_read_one|stop_bit_one =>
-- Signal assignments
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= uart_rx;
data_error_b1_en <= true;
data_error_b2_in <= '0';
data_error_b2_en <= false;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when start_bit_two =>
-- Signal assignments
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= uart_rx;
data_error_b2_en <= true;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when bit_read_two =>
-- Signal assignments
recv_ticker_rst <= '0';
barrel_enable <= true;
barrel_data_in <= uart_rx;
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= uart_rx;
data_error_b2_en <= true;
data_error_ref <= uart_rx;
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when parity_read_two =>
-- Signal assignments
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= uart_rx;
data_error_b2_en <= true;
data_error_ref <= uart_rx;
if parity_bit_in then
parity_test <= true;
parity_ref <= uart_rx;
else
parity_test <= false;
parity_ref <= '0';
end if;
ready_enable <= false;
when stop_bit_two =>
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= uart_rx;
data_error_b2_en <= true;
data_error_ref <= '1';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
when stop_bit_two_final =>
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= uart_rx;
data_error_b2_en <= true;
data_error_ref <= '1';
parity_test <= false;
parity_ref <= '0';
ready_enable <= true;
when others =>
-- Signal assignments
recv_ticker_rst <= '0';
barrel_enable <= false;
barrel_data_in <= '0';
sub_rst <= false;
data_error_b1_in <= '0';
data_error_b1_en <= false;
data_error_b2_in <= '0';
data_error_b2_en <= true;
data_error_ref <= '0';
parity_test <= false;
parity_ref <= '0';
ready_enable <= false;
end case;
end process;
end Behavioral;
| mit | 0b73cc2ded762df29b5fadc44e807286 | 0.432642 | 4.248756 | false | false | false | false |
chastell/art-decomp | kiss/ex1_nov.vhd | 1 | 16,310 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(18 downto 0)
);
end ex1_nov;
architecture behaviour of ex1_nov is
constant s1: std_logic_vector(4 downto 0) := "01000";
constant s2: std_logic_vector(4 downto 0) := "10011";
constant s3: std_logic_vector(4 downto 0) := "00111";
constant s4: std_logic_vector(4 downto 0) := "00000";
constant s5: std_logic_vector(4 downto 0) := "10000";
constant s6: std_logic_vector(4 downto 0) := "11001";
constant s7: std_logic_vector(4 downto 0) := "01111";
constant s8: std_logic_vector(4 downto 0) := "10001";
constant s9: std_logic_vector(4 downto 0) := "11010";
constant s10: std_logic_vector(4 downto 0) := "11011";
constant s11: std_logic_vector(4 downto 0) := "11100";
constant s12: std_logic_vector(4 downto 0) := "11101";
constant s13: std_logic_vector(4 downto 0) := "11000";
constant s14: std_logic_vector(4 downto 0) := "11110";
constant s15: std_logic_vector(4 downto 0) := "10100";
constant s16: std_logic_vector(4 downto 0) := "11111";
constant s17: std_logic_vector(4 downto 0) := "10101";
constant s18: std_logic_vector(4 downto 0) := "10110";
constant s19: std_logic_vector(4 downto 0) := "10111";
constant s20: std_logic_vector(4 downto 0) := "10010";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s1 =>
if std_match(input, "1011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "11-------") then next_state <= s4; output <= "0000000000000000000";
elsif std_match(input, "1000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "1010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "1001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s2 =>
if std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--1----") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-0--0----") then next_state <= s2; output <= "0111100000000000000";
end if;
when s3 =>
if std_match(input, "-0-------") then next_state <= s7; output <= "0111101010000000000";
end if;
when s4 =>
if std_match(input, "-011-----") then next_state <= s2; output <= "1111100000000000000";
elsif std_match(input, "-000-----") then next_state <= s3; output <= "1000011000000000000";
elsif std_match(input, "-010-----") then next_state <= s1; output <= "1000000000000000000";
elsif std_match(input, "-001-----") then next_state <= s2; output <= "1111100000000000000";
end if;
when s5 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "----100--") then next_state <= s5; output <= "0001000000000000000";
elsif std_match(input, "----110--") then next_state <= s5; output <= "0001000001000000000";
elsif std_match(input, "----101--") then next_state <= s8; output <= "0000000000000000000";
elsif std_match(input, "----111--") then next_state <= s8; output <= "0000000001000000000";
end if;
when s6 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-1-") then next_state <= s9; output <= "0001101001111000000";
elsif std_match(input, "-0--11-0-") then next_state <= s6; output <= "0001000001000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s10; output <= "0001100001111000000";
elsif std_match(input, "-00-10-1-") then next_state <= s9; output <= "0001101000111000000";
elsif std_match(input, "-0--10-0-") then next_state <= s6; output <= "0001000000000000000";
elsif std_match(input, "-01-10-1-") then next_state <= s10; output <= "0001100000111000000";
end if;
when s7 =>
if std_match(input, "-0--0----") then next_state <= s7; output <= "0111101000000000000";
elsif std_match(input, "-1--1----") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-1----") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-01-1----") then next_state <= s12; output <= "0001000000000000000";
end if;
when s8 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000110000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000110000";
end if;
when s9 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-01-11-1-") then next_state <= s13; output <= "0001100011001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s9; output <= "0001001001001000000";
elsif std_match(input, "-00-11-1-") then next_state <= s14; output <= "0001101011001001000";
elsif std_match(input, "-01-10-1-") then next_state <= s13; output <= "0001100010001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s9; output <= "0001001000001000000";
elsif std_match(input, "-00-10-1-") then next_state <= s14; output <= "0001101010001001000";
end if;
when s10 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s15; output <= "0001100001001001000";
elsif std_match(input, "-0--11-0-") then next_state <= s10; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s15; output <= "0001100000001001000";
elsif std_match(input, "-0--10-0-") then next_state <= s10; output <= "0001000000001000000";
end if;
when s11 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011011000110";
elsif std_match(input, "-00-11-0-") then next_state <= s11; output <= "0001001001000000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011011000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011011000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011011000010";
elsif std_match(input, "-01-11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010011000110";
elsif std_match(input, "-00-10-0-") then next_state <= s11; output <= "0001001000000000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010011000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010011000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010011000010";
elsif std_match(input, "-01-10-0-") then next_state <= s12; output <= "0001000000000000000";
end if;
when s12 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001011000110";
elsif std_match(input, "-0--11-0-") then next_state <= s12; output <= "0001000001000000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001011000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000011000110";
elsif std_match(input, "-0--10-0-") then next_state <= s12; output <= "0001000000000000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000011000010";
end if;
when s13 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-11") then next_state <= s15; output <= "0001100001001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s13; output <= "0001000001001000000";
elsif std_match(input, "-0--11-10") then next_state <= s15; output <= "0001100001001000010";
elsif std_match(input, "-0--10-11") then next_state <= s15; output <= "0001100000001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s13; output <= "0001000000001000000";
elsif std_match(input, "-0--10-10") then next_state <= s15; output <= "0001100000001000010";
end if;
when s14 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s14; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s14; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s15 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-0-") then next_state <= s15; output <= "0001000001001000000";
elsif std_match(input, "-0--10-1-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s15; output <= "0001000000001000000";
end if;
when s16 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-00-11-11") then next_state <= s16; output <= "0001101011001000110";
elsif std_match(input, "-0--11-0-") then next_state <= s16; output <= "0001001001001000000";
elsif std_match(input, "-00-11-10") then next_state <= s16; output <= "0001101011001000010";
elsif std_match(input, "-01-11-11") then next_state <= s13; output <= "0001100011001000110";
elsif std_match(input, "-01-11-10") then next_state <= s13; output <= "0001100011001000010";
elsif std_match(input, "-00-10-11") then next_state <= s16; output <= "0001101010001000110";
elsif std_match(input, "-0--10-0-") then next_state <= s16; output <= "0001001000001000000";
elsif std_match(input, "-00-10-10") then next_state <= s16; output <= "0001101010001000010";
elsif std_match(input, "-01-10-11") then next_state <= s13; output <= "0001100010001000110";
elsif std_match(input, "-01-10-10") then next_state <= s13; output <= "0001100010001000010";
end if;
when s17 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s17; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--10-0-") then next_state <= s17; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s18; output <= "0001000000001000001";
end if;
when s18 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s18; output <= "0001000001001000001";
elsif std_match(input, "-0--11-1-") then next_state <= s19; output <= "0011100001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s18; output <= "0001000000001000001";
elsif std_match(input, "-0--10-1-") then next_state <= s19; output <= "0011100000000000000";
end if;
when s19 =>
if std_match(input, "----01---") then next_state <= s1; output <= "0000000001000000000";
elsif std_match(input, "-1--11---") then next_state <= s5; output <= "0101100101000000000";
elsif std_match(input, "-1--10---") then next_state <= s5; output <= "0101100100000000000";
elsif std_match(input, "-0--11-0-") then next_state <= s19; output <= "0001000001000000000";
elsif std_match(input, "-0--11-1-") then next_state <= s20; output <= "0000000001000000000";
elsif std_match(input, "-0--10-0-") then next_state <= s19; output <= "0001000000000000000";
elsif std_match(input, "-0--10-1-") then next_state <= s20; output <= "0000000000000000000";
end if;
when s20 =>
if std_match(input, "-----1---") then next_state <= s1; output <= "0000000001000100000";
elsif std_match(input, "-----0---") then next_state <= s1; output <= "0000000000000100000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 4c0488cad4210142be675240cd4e2e99 | 0.610791 | 3.630899 | false | false | false | false |
mike7c2/befunge_processor | befunge_pkg.vhd | 1 | 1,978 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package befunge_pkg is
constant word_size : integer := 8;
constant instruction_size : integer := 16;
constant stack_size : integer := 2048;
constant grid_width : integer := 8;
constant grid_height : integer := 8;
type grid_nibble is array (grid_height-1 downto 0) of std_logic_vector(word_size-1 downto 0);
type grid_stuff is array (grid_width-1 downto 0) of grid_nibble;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end befunge_pkg;
package body befunge_pkg is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end befunge_pkg;
| unlicense | 0331a9e083873f383888ef7ab6a89bcd | 0.631951 | 3.17496 | false | false | false | false |
chastell/art-decomp | kiss/ex3_nov.vhd | 1 | 4,215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_nov;
architecture behaviour of ex3_nov is
constant s1: std_logic_vector(3 downto 0) := "1111";
constant s3: std_logic_vector(3 downto 0) := "1100";
constant s4: std_logic_vector(3 downto 0) := "0111";
constant s5: std_logic_vector(3 downto 0) := "1101";
constant s6: std_logic_vector(3 downto 0) := "1110";
constant s7: std_logic_vector(3 downto 0) := "1010";
constant s8: std_logic_vector(3 downto 0) := "1001";
constant s9: std_logic_vector(3 downto 0) := "1011";
constant s2: std_logic_vector(3 downto 0) := "1000";
constant s0: std_logic_vector(3 downto 0) := "0000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 46fb28cc37d406a1a1bea78008108dfd | 0.557533 | 3.316286 | false | false | false | false |
chastell/art-decomp | kiss/tav_rnd.vhd | 1 | 4,968 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tav_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end tav_rnd;
architecture behaviour of tav_rnd is
constant st0: std_logic_vector(1 downto 0) := "01";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "00";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "1000") then next_state <= st1; output <= "1000";
elsif std_match(input, "0100") then next_state <= st1; output <= "0100";
elsif std_match(input, "0010") then next_state <= st1; output <= "0010";
elsif std_match(input, "0001") then next_state <= st1; output <= "0001";
elsif std_match(input, "0000") then next_state <= st1; output <= "0000";
elsif std_match(input, "11--") then next_state <= st1; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st1; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st1; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st1; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st1; output <= "0000";
elsif std_match(input, "--11") then next_state <= st1; output <= "0000";
end if;
when st1 =>
if std_match(input, "1000") then next_state <= st2; output <= "1000";
elsif std_match(input, "0100") then next_state <= st2; output <= "0100";
elsif std_match(input, "0010") then next_state <= st2; output <= "0010";
elsif std_match(input, "0001") then next_state <= st2; output <= "0001";
elsif std_match(input, "1100") then next_state <= st2; output <= "1100";
elsif std_match(input, "1010") then next_state <= st2; output <= "1010";
elsif std_match(input, "1001") then next_state <= st2; output <= "1001";
elsif std_match(input, "0110") then next_state <= st2; output <= "0000";
elsif std_match(input, "0000") then next_state <= st2; output <= "0000";
elsif std_match(input, "0011") then next_state <= st2; output <= "0011";
elsif std_match(input, "0101") then next_state <= st2; output <= "0101";
elsif std_match(input, "0111") then next_state <= st2; output <= "0001";
elsif std_match(input, "1011") then next_state <= st2; output <= "1011";
elsif std_match(input, "1101") then next_state <= st2; output <= "1101";
elsif std_match(input, "1110") then next_state <= st2; output <= "1000";
elsif std_match(input, "1111") then next_state <= st2; output <= "1001";
end if;
when st2 =>
if std_match(input, "1000") then next_state <= st3; output <= "1000";
elsif std_match(input, "0100") then next_state <= st3; output <= "0100";
elsif std_match(input, "0010") then next_state <= st3; output <= "0010";
elsif std_match(input, "0001") then next_state <= st3; output <= "0001";
elsif std_match(input, "0000") then next_state <= st3; output <= "0000";
elsif std_match(input, "11--") then next_state <= st3; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st3; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st3; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st3; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st3; output <= "0000";
elsif std_match(input, "--11") then next_state <= st3; output <= "0000";
end if;
when st3 =>
if std_match(input, "1000") then next_state <= st0; output <= "1000";
elsif std_match(input, "0100") then next_state <= st0; output <= "0100";
elsif std_match(input, "0010") then next_state <= st0; output <= "0010";
elsif std_match(input, "0001") then next_state <= st0; output <= "0001";
elsif std_match(input, "0000") then next_state <= st0; output <= "0000";
elsif std_match(input, "11--") then next_state <= st0; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st0; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st0; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st0; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st0; output <= "0000";
elsif std_match(input, "--11") then next_state <= st0; output <= "0000";
end if;
when others => next_state <= "--"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | c7c280502adc7688b901d3b150ddd6e6 | 0.588164 | 3.314209 | false | false | false | false |
chastell/art-decomp | kiss/s832_hot.vhd | 1 | 31,301 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_hot is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_hot;
architecture behaviour of s832_hot is
constant s00000: std_logic_vector(24 downto 0) := "1000000000000000000000000";
constant s10000: std_logic_vector(24 downto 0) := "0100000000000000000000000";
constant s01110: std_logic_vector(24 downto 0) := "0010000000000000000000000";
constant s10001: std_logic_vector(24 downto 0) := "0001000000000000000000000";
constant s01111: std_logic_vector(24 downto 0) := "0000100000000000000000000";
constant s00010: std_logic_vector(24 downto 0) := "0000010000000000000000000";
constant s00001: std_logic_vector(24 downto 0) := "0000001000000000000000000";
constant s00100: std_logic_vector(24 downto 0) := "0000000100000000000000000";
constant s00011: std_logic_vector(24 downto 0) := "0000000010000000000000000";
constant s00101: std_logic_vector(24 downto 0) := "0000000001000000000000000";
constant s00110: std_logic_vector(24 downto 0) := "0000000000100000000000000";
constant s11111: std_logic_vector(24 downto 0) := "0000000000010000000000000";
constant s00111: std_logic_vector(24 downto 0) := "0000000000001000000000000";
constant s10111: std_logic_vector(24 downto 0) := "0000000000000100000000000";
constant s01011: std_logic_vector(24 downto 0) := "0000000000000010000000000";
constant s01000: std_logic_vector(24 downto 0) := "0000000000000001000000000";
constant s01100: std_logic_vector(24 downto 0) := "0000000000000000100000000";
constant s01101: std_logic_vector(24 downto 0) := "0000000000000000010000000";
constant s01001: std_logic_vector(24 downto 0) := "0000000000000000001000000";
constant s01010: std_logic_vector(24 downto 0) := "0000000000000000000100000";
constant s11000: std_logic_vector(24 downto 0) := "0000000000000000000010000";
constant s11011: std_logic_vector(24 downto 0) := "0000000000000000000001000";
constant s11001: std_logic_vector(24 downto 0) := "0000000000000000000000100";
constant s11010: std_logic_vector(24 downto 0) := "0000000000000000000000010";
constant s11100: std_logic_vector(24 downto 0) := "0000000000000000000000001";
signal current_state, next_state: std_logic_vector(24 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------------"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0001000000000010000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0001000000000010000";
elsif std_match(input, "-001------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-011------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000010000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000010001";
end if;
when s10000 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000001000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000000001000000000";
end if;
when s01111 =>
if std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000010000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000010000000010000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000010000000010000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000001000000000100";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000001000001000100";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000001000000000100";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000001000001000100";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000001000000000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000001000000000000";
end if;
when s00100 =>
if std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0-0001-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0--101-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0---11-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s00001 =>
if std_match(input, "------0--------0-1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------0--------000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------101") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------111") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10---------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-10--------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10--------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------110--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-110-------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------110-------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------111--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------1110-----010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1110-----110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----101--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0------11--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----1-----1------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----11---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----10---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1-----0------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----0----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----0----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0-----01---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---110") then next_state <= s01011; output <= "0000000100000000000";
end if;
when s11111 =>
if std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s00111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s01011 =>
if std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
end if;
when s01100 =>
if std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0000000010000100000";
elsif std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0000000010000100000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0000000000000101000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0000000000000101000";
end if;
when s01101 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0101000000000000010";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0101000000000000010";
elsif std_match(input, "-0---------------1") then next_state <= s00000; output <= "0100000000000000010";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0100000000000000010";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0100000000000000010";
elsif std_match(input, "-0-1-------------0") then next_state <= s00000; output <= "0100000000000000010";
end if;
when s01000 =>
if std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "0000000100100000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000100100000001";
end if;
when s01001 =>
if std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "1000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
end if;
when s01010 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s11000 =>
if std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
end if;
when s11001 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "1000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000100000000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11010 =>
if std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11011 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-0--------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----111") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1--0-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-0--1-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
end if;
when s11100 =>
if std_match(input, "----0------------1") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00011 =>
if std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000100000000000";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
end if;
when others => next_state <= "-------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | ab93481242f47dc81c4608424d569b8f | 0.588991 | 4.247083 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/DDR_reg.vhd | 2 | 1,065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end DDR_register;
architecture small of DDR_register is
signal high_data, low_data : std_logic_vector( SIZE-1 downto 0 );
begin
HIGH_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
high_data <= ( others=>'0' );
elsif ( clk'event and clk='1' ) then
high_data <= din_hi;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
LOW_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
low_data <= ( others=>'0' );
elsif ( clk'event and clk='0' ) then
low_data <= din_lo;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
dout_hi <= high_data;
dout_lo <= low_data;
end small;
| mit | 56e2279dc5511ada5266926a9b50eb53 | 0.586854 | 3.246951 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_debouncer.vhd | 1 | 2,250 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_debounce.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_debouncer is end tb_debouncer;
architecture sim of tb_debouncer is
-- Declaration of the component under test
component debouncer
port(clk_i : in std_logic; --input clock
reset_i : in std_logic;
btn_i : in std_logic; --input signal to be debounced
deb_o : out std_logic);
end component debouncer;
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal btn_i : std_logic := '0';
signal deb_o : std_logic;
begin
-- Instantiate the design under test
i_debouncer : debouncer
port map (
clk_i => clk_i,
reset_i => reset_i,
btn_i => btn_i,
deb_o => deb_o);
clk_i <= not clk_i after 5 ns;
-- Generate inputs for simulation
run : process
begin
btn_i <= '0';
wait for 7 ns;
btn_i <= '0';
wait for 4 ns;
btn_i <= '0';
wait for 10 ns;
btn_i <= '1';
wait for 5 ns;
reset_i <= '1';
wait for 5 ns;
reset_i <= '0';
btn_i <= '0';
wait for 6 ns;
btn_i <= '1';
wait for 8 ns;
btn_i <= '1';
wait for 3 ns;
btn_i <= '0';
wait for 7 ns;
btn_i <= '1';
wait for 2 ns;
btn_i <= '1';
wait for 8 ns;
btn_i <= '1';
wait for 500 ns;
btn_i <= '0';
wait;
end process run;
end sim;
| mit | 5ed1935a930823d573bb78cce396a823 | 0.453778 | 3.933566 | false | false | false | false |
chastell/art-decomp | kiss/sse_hot.vhd | 1 | 7,190 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_hot;
architecture behaviour of sse_hot is
constant st11: std_logic_vector(15 downto 0) := "1000000000000000";
constant st10: std_logic_vector(15 downto 0) := "0100000000000000";
constant st4: std_logic_vector(15 downto 0) := "0010000000000000";
constant st12: std_logic_vector(15 downto 0) := "0001000000000000";
constant st7: std_logic_vector(15 downto 0) := "0000100000000000";
constant st6: std_logic_vector(15 downto 0) := "0000010000000000";
constant st1: std_logic_vector(15 downto 0) := "0000001000000000";
constant st0: std_logic_vector(15 downto 0) := "0000000100000000";
constant st8: std_logic_vector(15 downto 0) := "0000000010000000";
constant st9: std_logic_vector(15 downto 0) := "0000000001000000";
constant st3: std_logic_vector(15 downto 0) := "0000000000100000";
constant st2: std_logic_vector(15 downto 0) := "0000000000010000";
constant st5: std_logic_vector(15 downto 0) := "0000000000001000";
constant st13: std_logic_vector(15 downto 0) := "0000000000000100";
constant st14: std_logic_vector(15 downto 0) := "0000000000000010";
constant st15: std_logic_vector(15 downto 0) := "0000000000000001";
signal current_state, next_state: std_logic_vector(15 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------------"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----------------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 3e753d22c8da28e732f6543c567dc738 | 0.570654 | 3.42218 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/X4Time.vhd | 2 | 625 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x4time is port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end x4time;
-- Architecture of the Component
architecture a_x4time of x4time is
begin
b_out(7) <= b_in(4);
b_out(6) <= b_in(3) xor b_in(7);
b_out(5) <= b_in(2) xor b_in(6) xor b_in(7);
b_out(4) <= b_in(1) xor b_in(5) xor b_in(6);
b_out(3) <= b_in(0) xor b_in(5) xor b_in(7);
b_out(2) <= b_in(6) xor b_in(7);
b_out(1) <= b_in(5) xor b_in(6);
b_out(0) <= b_in(5);
end a_x4time;
| mit | 0ececdd97b18642bd70a6890c5199c32 | 0.5744 | 2.248201 | false | false | false | false |
chastell/art-decomp | kiss/s1_nov.vhd | 1 | 11,803 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_nov;
architecture behaviour of s1_nov is
constant st0: std_logic_vector(4 downto 0) := "10110";
constant st1: std_logic_vector(4 downto 0) := "11010";
constant st2: std_logic_vector(4 downto 0) := "10101";
constant st3: std_logic_vector(4 downto 0) := "01010";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00110";
constant st6: std_logic_vector(4 downto 0) := "00011";
constant st7: std_logic_vector(4 downto 0) := "01110";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "11111";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "01001";
constant st12: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10010";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "11110";
constant st17: std_logic_vector(4 downto 0) := "01101";
constant st18: std_logic_vector(4 downto 0) := "00010";
constant st19: std_logic_vector(4 downto 0) := "11101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 52b39625354294ace8b92e5c129d160d | 0.565026 | 3.300615 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-08D.vhd | 1 | 10,393 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08D.vhd
-- Creation Date: 21:39:37 03/22/2010
-- Description:
-- Multiplexor Channel Controls - FA Register - Indicators
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Revise Mpx and 1050 signals
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Gates_package.all;
USE work.Buses_package.all;
USE work.FLL;
entity MpxFA is
Port ( BUS_O_REG : in STD_LOGIC_VECTOR (0 to 8);
DIAG_SW : in STD_LOGIC;
-- External MPX connections:
MPX_BUS_OUT_BITS : out STD_LOGIC_VECTOR (0 to 8);
MPX_BUS_IN_BITS : in STD_LOGIC_VECTOR (0 to 8);
TAGS_OUT : out MPX_TAGS_OUT;
TAGS_IN : in MPX_TAGS_IN;
--
FI : out STD_LOGIC_VECTOR(0 to 8); -- Mpx Bus In to CPU
FAK : in STD_LOGIC;
RECYCLE_RST : in STD_LOGIC;
CK_P_BIT : in STD_LOGIC;
ALU_CHK_LCH : in STD_LOGIC;
CHK_SW_PROC_SW : in STD_LOGIC;
N1050_REQ_IN : in STD_LOGIC;
ROS_SCAN : in STD_LOGIC;
FBK_T2 : in STD_LOGIC;
FT5_BIT_SEL_IN : out STD_LOGIC;
SERV_IN_SIGNAL : out STD_LOGIC;
STATUS_IN_SIGNAL : out STD_LOGIC;
FT3_BIT_MPX_SHARE_REQ : out STD_LOGIC;
MPX_SHARE_REQ : out STD_LOGIC;
T1,T2,T3 : in STD_LOGIC;
ANY_PRIORITY_LCH : in STD_LOGIC;
CK_SALS_PWR : in STD_LOGIC_VECTOR (0 to 3);
SET_BUS_O_CTRL_LCH : in STD_LOGIC;
N1401_MODE : in STD_LOGIC;
N1050_OP_IN : in STD_LOGIC;
N1050_CE_MODE : in STD_LOGIC;
MPX_METERING_IN : out STD_LOGIC;
FT7_MPX_CHNL_IN : in STD_LOGIC;
LOAD_IND : in STD_LOGIC;
SUPPR_CTRL_LCH : in STD_LOGIC;
OP_OUT_SIGNAL : in STD_LOGIC;
OP_OUT_SIG : in STD_LOGIC;
SEL_O_FT6 : out STD_LOGIC;
N1050_SEL_IN : out STD_LOGIC;
n1050_SEL_O : in STD_LOGIC;
P_1050_SEL_IN : out STD_LOGIC;
P_1050_SEL_OUT : out STD_LOGIC;
N1050_INSTALLED : in STD_LOGIC;
SUPPR_O : out STD_LOGIC;
DEBUG : inout DEBUG_BUS;
METERING_OUT : in STD_LOGIC;
CLOCK_OUT : in STD_LOGIC;
CLK : in STD_LOGIC;
-- Mpx Indicators
OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN,
SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT,
SUPPRESS_OUT : out std_logic); -- 08A
end MpxFA;
architecture FMD of MpxFA is
signal sSERV_IN_SIGNAL, sSTATUS_IN_SIGNAL, sADDR_OUT, sSUPPR_O, sOP_OUT : STD_LOGIC;
signal SIS1,SIS2,SIS3 : STD_LOGIC;
signal OP_INLK_SET, OP_INLK : STD_LOGIC;
signal SERV_OUT, CMD_OUT : STD_LOGIC;
signal sTAGS_OUT : MPX_TAGS_OUT;
signal sTAGS_IN : MPX_TAGS_IN;
signal sFT5_BIT_SEL_IN, Reset_SELO : STD_LOGIC;
signal sn1050_SEL_OUT : STD_LOGIC;
signal sn1050_SEL_IN : STD_LOGIC;
signal CMD_STT_Set, RST_CMD_RSTT_ADDR_OUT, CMD_STT : STD_LOGIC;
signal sFT3_BIT_MPX_SHARE_REQ, sSEL_O_FT6, sSUPPR_O_FT0 : STD_LOGIC;
signal FAK_T2 : STD_LOGIC;
signal SetAdrO2, ADDR_OUT_2, SetAdrOut, SetCmdO, RstCmdO, SetSrvO, RstSrvO : STD_LOGIC;
signal SetCUBusyInlk, ResetCUBusyInlk, CUBusy, RST_STT_SEL_OUT : STD_LOGIC;
signal ResetBusOCtrl, BUSOCtrl : STD_LOGIC;
signal SetStartSelO, ResetStartSelO, StartSelO : STD_LOGIC;
signal NO_1050_SEL_O : STD_LOGIC;
signal SetSelReq, ResetSelReq, SetSelOInlk, SelOInlk : STD_LOGIC;
signal SS_RECYCLE_RST : STD_LOGIC;
signal NOT_OPL_IN : STD_LOGIC;
begin
STATUS_IN <= sTAGS_IN.STA_IN;
SERVICE_IN <= sTAGS_IN.SRV_IN;
ADDR_IN <= sTAGS_IN.ADR_IN; -- AA3F3
OPNL_IN <= sTAGS_IN.OPL_IN; -- AA3F2 AA3F5
SIS1 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.SRV_IN) or OP_INLK; -- AA3F2 AA3E2
sSERV_IN_SIGNAL <= SIS1 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit
SERV_IN_SIGNAL <= sSERV_IN_SIGNAL;
SIS3 <= (not SERV_OUT and not CMD_OUT and sTAGS_IN.STA_IN) or (OP_INLK and not sTAGS_OUT.ADR_OUT); -- AA3D7 AA3E2
sSTATUS_IN_SIGNAL <= SIS3 and (not sTAGS_IN.STA_IN or not sTAGS_IN.SRV_IN); -- Wire-AND, not sure about the OR bit
STATUS_IN_SIGNAL <= sSTATUS_IN_SIGNAL;
OP_INLK_SET <= not sTAGS_IN.OPL_IN and T2;
OP_INLK_FL: entity FLL port map (S=>OP_INLK_SET, R=> T1, Q=>OP_INLK); -- AA3E4 ?? R=> NOT T1 ??
sn1050_SEL_IN <= sTAGS_IN.SEL_IN;
n1050_SEL_IN <= sn1050_SEL_IN;
sFT5_BIT_SEL_IN <= (sn1050_SEL_IN and not n1050_INSTALLED) or sn1050_SEL_IN; -- AA3E5 AA3E2
FT5_BIT_SEL_IN <= sFT5_BIT_SEL_IN;
Reset_SELO <= RECYCLE_RST or FBK_T2 or sFT5_BIT_SEL_IN; -- AA3D7 AA3E7
CMD_STT_Set <= CK_P_BIT and FAK_T2; -- ?? FMD has FAK not FAK_T2
RST_CMD_RSTT_ADDR_OUT <= (FAK and T1) or RECYCLE_RST; -- AA3E6 AA3E2
CMD_STT_FL: entity FLL port map (S=>CMD_STT_Set, R=>RST_CMD_RSTT_ADDR_OUT, Q=>CMD_STT); -- AA3D7 AA3E7
sFT3_BIT_MPX_SHARE_REQ <= (ROS_SCAN or not CMD_STT) and (N1050_REQ_IN or sTAGS_IN.REQ_IN or (ALU_CHK_LCH and CHK_SW_PROC_SW) or sTAGS_IN.OPL_IN); -- AA3F2 AA3E5 AA3G4
MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ;
FT3_BIT_MPX_SHARE_REQ <= sFT3_BIT_MPX_SHARE_REQ;
sTAGS_IN.OPL_IN <= TAGS_IN.OPL_IN or (DIAG_SW and BUS_O_REG(7)); -- AA3B4
sTAGS_IN.ADR_IN <= TAGS_IN.ADR_IN or (DIAG_SW and BUS_O_REG(6)); -- AA3B4
sTAGS_IN.STA_IN <= TAGS_IN.STA_IN or (DIAG_SW and BUS_O_REG(4)); -- AA3B4
sTAGS_IN.SRV_IN <= TAGS_IN.SRV_IN or (DIAG_SW and BUS_O_REG(5)); -- AA3B4
sTAGS_IN.SEL_IN <= TAGS_IN.SEL_IN or (DIAG_SW and BUS_O_REG(0)); -- AA3B4
sTAGS_IN.REQ_IN <= TAGS_IN.REQ_IN;
sTAGS_IN.MTR_IN <= TAGS_IN.MTR_IN;
MPX_BUS_OUT_BITS <= BUS_O_REG;
FAK_T2 <= FAK and (T2 and not ANY_PRIORITY_LCH); -- AA3B7 AA3F4 AA3E6
SetAdrO2 <= T3 and sADDR_OUT;
ADDR_OUT_2_FL: entity FLL port map (S=>SetAdrO2, R=>RST_CMD_RSTT_ADDR_OUT, Q=>ADDR_OUT_2); -- AA3E4
SetAdrOut <= FAK_T2 and CK_SALS_PWR(1);
ADDR_OUT_FL: entity FLL port map (S=>SetAdrOut, R=>RST_CMD_RSTT_ADDR_OUT, Q=>sADDR_OUT); -- AA3D7 AA3E7
ADDR_OUT <= sADDR_OUT;
SetCmdO <= FAK_T2 and CK_SALS_PWR(2);
RstCmdO <= not sTAGS_IN.ADR_IN and not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN;
CMD_O: entity FLL port map (S=>SetCmdO, R=>RstCmdO, Q=>CMD_OUT); -- AA3E4 AA3E5
sTAGS_OUT.CMD_OUT <= CMD_OUT;
SetSrvO <= FAK_T2 and CK_SALS_PWR(3);
RstSrvO <= not sTAGS_IN.SRV_IN and not sTAGS_IN.STA_IN;
SRV_O: entity FLL port map (S=>SetSrvO, R=>RstSrvO, Q=>SERV_OUT); -- AA3C7
SetCUBusyInlk <= sTAGS_IN.STA_IN and ADDR_OUT_2 and FBK_T2;
ResetCUBusyInlk <= not sADDR_OUT and T2;
CU_BUSY_INLK: entity FLL port map (S=>SetCUBusyInlk, R=>ResetCUBusyInlk, Q=>CUBusy); -- AA3B5
RST_STT_SEL_OUT <= not OP_OUT_SIG or CUBusy; -- AA3F7
ResetBusOCtrl <= not sADDR_OUT and not CMD_OUT and not SERV_OUT; -- AA3D7
BUS_O_CTRL: entity FLL port map (S=>SET_BUS_O_CTRL_LCH, R=>ResetBusOCtrl, Q=>BUSOCtrl); -- AA3J5
SetStartSelO <= ADDR_OUT_2 and T2 and BUSOCtrl; -- AA3E6
ResetStartSelO <= RST_STT_SEL_OUT or (not N1401_MODE and sTAGS_IN.ADR_IN) or (not ADDR_OUT_2 and Reset_SelO); -- AA3F5 AA3K3
START_SEL_O: entity FLL port map (S=>SetStartSelO, R=>ResetStartSelO, Q=>StartSelO); -- AA3L4 AA3E7
sSEL_O_FT6 <= not CUBusy and (StartSelO or NO_1050_SEL_O or sN1050_SEL_OUT); -- AA3E5
SEL_O_FT6 <= sSEL_O_FT6;
NO_1050_SEL_O <= not N1050_INSTALLED and n1050_SEL_O; -- AA3D2
SetSelReq <= not SelOInlk and T2 and sFT3_BIT_MPX_SHARE_REQ;
ResetSelReq <= SelOInlk or not sFT3_BIT_MPX_SHARE_REQ;
SEL_REQ: entity FLL port map (S=>SetSelReq, R=>ResetSelReq, Q=>sN1050_SEL_OUT); -- AA3F4
-- To Select Out Propagation in 10B
P_1050_SEL_OUT <= sN1050_SEL_OUT;
SetSelOInlk <= (sTAGS_IN.ADR_IN and sTAGS_IN.OPL_IN) or (N1050_OP_IN and not N1050_CE_MODE); -- AA3B7
NOT_OPL_IN <= not sTAGS_IN.OPL_IN;
SEL_O_INLK: entity FLL port map (S=>SetSelOInlk, R=>NOT_OPL_IN, Q=>SelOInlk); -- AA3C7
-- sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) or not LOAD_IND or SUPPR_CTRL_LCH; -- AA3C7 AA3E5
sSUPPR_O <= (FT7_MPX_CHNL_IN and not sTAGS_IN.OPL_IN) and not LOAD_IND and SUPPR_CTRL_LCH; -- AA3C7 AA3E5 ?? AA3C7 shown as 'OR'
SUPPR_O <= sSUPPR_O;
SS_RECYCLE_RST <= RECYCLE_RST; -- AA3G3 Single Shot ??
sOP_OUT <= OP_OUT_SIGNAL and not SS_RECYCLE_RST; -- AA3D6
sTAGS_OUT.ADR_OUT2 <= ADDR_OUT_2;
sTAGS_OUT.ADR_OUT <= sADDR_OUT;
-- sTAGS_OUT.CMD_OUT <= CMD_OUT;
sTAGS_OUT.SRV_OUT <= SERV_OUT;
sTAGS_OUT.SEL_OUT <= sSEL_O_FT6; -- ??
sTAGS_OUT.MTR_OUT <= METERING_OUT;
sTAGS_OUT.CLK_OUT <= CLOCK_OUT;
sTAGS_OUT.SUP_OUT <= sSUPPR_O;
sTAGS_OUT.OPL_OUT <= sOP_OUT;
-- sTAGS_OUT.SEL_OUT <= '0'; -- ??
sTAGS_OUT.STA_OUT <= '0'; -- ??
sTAGS_OUT.HLD_OUT <= '0'; -- ??
TAGS_OUT <= sTAGS_OUT;
FI <= MPX_BUS_IN_BITS;
-- Output tag indicators not really shown
SELECT_OUT <= sSEL_O_FT6;
ADDR_OUT <= sADDR_OUT;
COMMAND_OUT <= CMD_OUT;
SERVICE_OUT <= SERV_OUT;
SUPPRESS_OUT <= sSUPPR_O;
end FMD;
| gpl-3.0 | 3c17e53582863bb9402902be7b6d26fc | 0.625998 | 2.641169 | false | false | false | false |
chastell/art-decomp | kiss/s1494_rnd.vhd | 1 | 31,360 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_rnd;
architecture behaviour of s1494_rnd is
constant s000000: std_logic_vector(5 downto 0) := "111101";
constant s001110: std_logic_vector(5 downto 0) := "000010";
constant s011000: std_logic_vector(5 downto 0) := "011011";
constant s010000: std_logic_vector(5 downto 0) := "111110";
constant s010100: std_logic_vector(5 downto 0) := "111111";
constant s110011: std_logic_vector(5 downto 0) := "010001";
constant s010011: std_logic_vector(5 downto 0) := "010110";
constant s000100: std_logic_vector(5 downto 0) := "001011";
constant s010111: std_logic_vector(5 downto 0) := "001111";
constant s010110: std_logic_vector(5 downto 0) := "011110";
constant s100011: std_logic_vector(5 downto 0) := "101011";
constant s001100: std_logic_vector(5 downto 0) := "100001";
constant s011011: std_logic_vector(5 downto 0) := "110000";
constant s010001: std_logic_vector(5 downto 0) := "101111";
constant s100110: std_logic_vector(5 downto 0) := "011010";
constant s011101: std_logic_vector(5 downto 0) := "111000";
constant s101110: std_logic_vector(5 downto 0) := "110110";
constant s010101: std_logic_vector(5 downto 0) := "001000";
constant s111110: std_logic_vector(5 downto 0) := "000001";
constant s000011: std_logic_vector(5 downto 0) := "100100";
constant s111011: std_logic_vector(5 downto 0) := "001001";
constant s011010: std_logic_vector(5 downto 0) := "101001";
constant s111010: std_logic_vector(5 downto 0) := "100110";
constant s100111: std_logic_vector(5 downto 0) := "111011";
constant s110010: std_logic_vector(5 downto 0) := "011100";
constant s100000: std_logic_vector(5 downto 0) := "100011";
constant s011100: std_logic_vector(5 downto 0) := "100010";
constant s101010: std_logic_vector(5 downto 0) := "011000";
constant s100010: std_logic_vector(5 downto 0) := "000011";
constant s101000: std_logic_vector(5 downto 0) := "110111";
constant s011110: std_logic_vector(5 downto 0) := "010011";
constant s110000: std_logic_vector(5 downto 0) := "110010";
constant s010010: std_logic_vector(5 downto 0) := "000111";
constant s001010: std_logic_vector(5 downto 0) := "001100";
constant s100100: std_logic_vector(5 downto 0) := "110101";
constant s111000: std_logic_vector(5 downto 0) := "010100";
constant s001011: std_logic_vector(5 downto 0) := "000000";
constant s110100: std_logic_vector(5 downto 0) := "100111";
constant s001000: std_logic_vector(5 downto 0) := "011101";
constant s000010: std_logic_vector(5 downto 0) := "101101";
constant s000111: std_logic_vector(5 downto 0) := "100101";
constant s101011: std_logic_vector(5 downto 0) := "100000";
constant s001111: std_logic_vector(5 downto 0) := "111100";
constant s000110: std_logic_vector(5 downto 0) := "000100";
constant s110110: std_logic_vector(5 downto 0) := "110011";
constant s011111: std_logic_vector(5 downto 0) := "010111";
constant s111100: std_logic_vector(5 downto 0) := "111010";
constant s101100: std_logic_vector(5 downto 0) := "111001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 55ad75a291fa0f39797c2c96084a7d53 | 0.625829 | 3.830931 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-08C.vhd | 1 | 6,564 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Multiplexor Channel registers FO & FB
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Revise XH & XL BU latches amd MPX_INTRPT signal
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.PH;
use work.FLVL;
entity MpxFOFB is
Port ( MPX_ROS_LCH : in STD_LOGIC;
S_REG_0 : in STD_LOGIC;
SET_FW : in STD_LOGIC;
S_REG_1 : in STD_LOGIC;
S_REG_2 : in STD_LOGIC;
T3 : in STD_LOGIC;
CK_SALS : in STD_LOGIC_VECTOR (0 to 3);
PK_SALS : in STD_LOGIC;
FBK_T2 : in STD_LOGIC;
MACH_RST_SET_LCH : in STD_LOGIC;
SALS_CS : in STD_LOGIC_VECTOR (0 to 3);
SALS_SA : in STD_LOGIC;
CK_0_PWR : in STD_LOGIC;
R_REG : in STD_LOGIC_VECTOR (0 to 8);
T1,T2 : in STD_LOGIC;
XXH : out STD_LOGIC;
XH : out STD_LOGIC;
XL : out STD_LOGIC;
FT_7_BIT_MPX_CHNL_INTRP : out STD_LOGIC;
FT_2_BIT_MPX_OPN_LCH : out STD_LOGIC;
SUPPR_CTRL_LCH : out STD_LOGIC;
OP_OUT_SIG : out STD_LOGIC;
MPX_OPN_LT_GATE : out STD_LOGIC;
MACH_RST_MPX : out STD_LOGIC;
MPX_INTRPT : out STD_LOGIC;
SX1_MASK : out STD_LOGIC;
EXT_TRAP_MASK_ON : out STD_LOGIC;
SX2_MASK : out STD_LOGIC;
FAK : out STD_LOGIC;
SET_BUS_O_CTRL_LCH : out STD_LOGIC;
MPX_BUS_O_REG : out STD_LOGIC_VECTOR (0 to 8);
clk : in STD_LOGIC);
end MpxFOFB;
architecture FMD of MpxFOFB is
signal sXXH,sXH,sXL,T3SET,X_SET : STD_LOGIC;
signal XXH_IN,XH_IN,XL_IN : STD_LOGIC;
signal XXHBU,XHBU,XLBU : STD_LOGIC;
signal sMACH_RST_MPX : STD_LOGIC;
signal CK11XX, CKX11X,CKX1X1,CK1X1X,CKXX11 : STD_LOGIC;
signal CHNL_L,OPN_L,SUPPR_L,OUT_L : STD_LOGIC;
signal notOP_OUT_SIG,MpxMask : STD_LOGIC;
alias KP is PK_SALS;
signal sFAK,sSET_BUS_O_CTRL : STD_LOGIC;
signal BusO_Set,BusO_Reset : STD_LOGIC_VECTOR (0 to 8);
signal sFT_7_BIT_MPX_CHNL_INTRP,sFT_2_BIT_MPX_OPN_LCH,sSUPPR_CTRL_LCH : STD_LOGIC;
begin
-- XL, XH and XXL bits and backup
XXH_BU: entity PH port map (D=>sXXH, L=>SET_FW, Q=> XXHBU);
XXH_IN <= (XXHBU and MPX_ROS_LCH) or (S_REG_0 and not MPX_ROS_LCH);
X_SET <= T3SET or sMACH_RST_MPX;
XXH_PH: entity PH port map (D=>XXH_IN, L=>X_SET, Q=> sXXH);
XXH <= sXXH;
XH_BU: entity PH port map (D=>sXH, L=>SET_FW, Q=> XHBU);
-- XH_IN <= (XHBU and MPX_ROS_LCH) or (not S_REG_1 and not MPX_ROS_LCH);
XH_IN <= (XHBU and MPX_ROS_LCH) or (S_REG_1 and not MPX_ROS_LCH);
XH_PH: entity PH port map (D=>XH_IN, L=>X_SET, Q=>sXH);
XH <= sXH;
XL_BU: entity PH port map (D=>sXL, L=>SET_FW, Q=> XLBU);
-- XL_IN <= (XLBU and MPX_ROS_LCH) or (not S_REG_2 and not MPX_ROS_LCH);
XL_IN <= (XLBU and MPX_ROS_LCH) or (S_REG_2 and not MPX_ROS_LCH);
XL_PH: entity PH port map (D=>XL_IN, L=>X_SET, Q=>sXL);
XL <= sXL;
-- MPX Flags
T3SET <= (MPX_ROS_LCH and T3) or (FBK_T2 and CK_SALS(0) and CK_SALS(3));
sMACH_RST_MPX <= MACH_RST_SET_LCH;
MACH_RST_MPX <= sMACH_RST_MPX;
CK11XX <= CK_SALS(0) and CK_SALS(1) and FBK_T2;
CHNL_L <= sMACH_RST_MPX or CK11XX;
MPX_CHNL: entity PH port map (D=>KP,L=>CHNL_L,Q=>sFT_7_BIT_MPX_CHNL_INTRP);
FT_7_BIT_MPX_CHNL_INTRP <= sFT_7_BIT_MPX_CHNL_INTRP;
CKX11X <= CK_SALS(1) and CK_SALS(2) and FBK_T2;
OPN_L <= sMACH_RST_MPX or CKX11X;
MPX_OPN: entity PH port map (D=>KP,L=>OPN_L,Q=>sFT_2_BIT_MPX_OPN_LCH);
FT_2_BIT_MPX_OPN_LCH <= sFT_2_BIT_MPX_OPN_LCH;
CK1X1X <= CK_SALS(0) and CK_SALS(2) and FBK_T2;
SUPPR_L <= sMACH_RST_MPX or CK1X1X;
SUPPR_CTRL: entity PH port map (D=>KP,L=>SUPPR_L,Q=>sSUPPR_CTRL_LCH);
SUPPR_CTRL_LCH <= sSUPPR_CTRL_LCH;
CKX1X1 <= CK_SALS(1) and CK_SALS(3) and FBK_T2;
OUT_L <= sMACH_RST_MPX or CKX1X1;
OP_OUT_CTRL: entity PH port map (D=>KP,L=>OUT_L,Q=>notOP_OUT_SIG);
OP_OUT_SIG <= not notOP_OUT_SIG;
MPX_OPN_LT_GATE <= CKX11X;
-- External Interrupt Masks
-- ?? Should the R_REG bits be inverted before use?
CKXX11 <= CK_SALS(2) and CK_SALS(3) and FBK_T2;
MPX_MASK: entity PH port map (D=>R_REG(0),L=>CKXX11,Q=>MPXMask);
MPX_INTRPT <= sFT_7_BIT_MPX_CHNL_INTRP and MPXMask;
SX1MASK: entity PH port map (D=>R_REG(1),L=>CKXX11,Q=>SX1_MASK);
EXT_MASK: entity PH port map (D=>R_REG(7),L=>CKXX11,Q=>EXT_TRAP_MASK_ON);
SX2MASK: entity PH port map (D=>R_REG(2),L=>CKXX11,Q=>SX2_MASK);
-- MPX BUS OUT REGISTER
sFAK <= SALS_CS(0) and SALS_CS(1) and SALS_CS(2) and SALS_CS(3) and not SALS_SA;
FAK <= sFAK;
sSET_BUS_O_CTRL <= sFAK and CK_0_PWR;
SET_BUS_O_CTRL_LCH <= sSET_BUS_O_CTRL;
BusO_Set <= R_REG and (0 to 8=>(sSET_BUS_O_CTRL and T2)); -- ??? "and T2" added to prevent incorrect setting of BUS_O
BusO_Reset <= (0 to 8=>sSET_BUS_O_CTRL and T1);
MPX_BUSO: entity FLVL port map (S=>BusO_Set,R=>BusO_Reset,Q=>MPX_BUS_O_REG);
end FMD;
| gpl-3.0 | f0b31cd4ca555ea981559edfee0a423e | 0.595064 | 2.673727 | false | false | false | false |
chastell/art-decomp | kiss/dk512_jed.vhd | 1 | 4,539 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_jed is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_jed;
architecture behaviour of dk512_jed is
constant state_1: std_logic_vector(3 downto 0) := "1001";
constant state_8: std_logic_vector(3 downto 0) := "0011";
constant state_2: std_logic_vector(3 downto 0) := "1101";
constant state_4: std_logic_vector(3 downto 0) := "0001";
constant state_3: std_logic_vector(3 downto 0) := "0101";
constant state_5: std_logic_vector(3 downto 0) := "0000";
constant state_6: std_logic_vector(3 downto 0) := "0100";
constant state_13: std_logic_vector(3 downto 0) := "0010";
constant state_7: std_logic_vector(3 downto 0) := "1100";
constant state_9: std_logic_vector(3 downto 0) := "0111";
constant state_10: std_logic_vector(3 downto 0) := "1010";
constant state_11: std_logic_vector(3 downto 0) := "0110";
constant state_12: std_logic_vector(3 downto 0) := "1111";
constant state_14: std_logic_vector(3 downto 0) := "1110";
constant state_15: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 8ed6700a043aa3c96d75ee68921eaa53 | 0.582287 | 3.251433 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/DDR_dual.vhd | 2 | 3,075 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_dual is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable_main, enable_dual, select_dual, check_dual : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
error_on_diff_hi, error_on_diff_lo : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
rst, clk : in std_logic );
end DDR_dual;
architecture a_ddr_dual of DDR_dual is
component DDR_enable is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component trigger is port (
switch : in std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
clock, reset : in std_logic;
value : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 ) );
end component;
signal main_hi, main_lo, dual_hi, dual_lo, diff_hi, diff_lo, hi, lo : std_logic_vector( SIZE-1 downto 0 );
begin
main_reg : DDR_enable generic map( SIZE=>SIZE )
port map( din_hi=>din_hi, din_lo=>din_lo,
enable=>enable_main,
dout_hi=>main_hi, dout_lo=>main_lo,
rst=>rst, clk=>clk );
dual_reg : DDR_enable generic map( SIZE=>SIZE )
port map( din_hi=>din_hi, din_lo=>din_lo,
enable=>enable_dual,
dout_hi=>dual_hi, dout_lo=>dual_lo,
rst=>rst, clk=>clk );
diff_hi <= main_hi xor dual_hi; --*
diff_lo <= main_lo xor dual_lo; --*
hi <= main_hi when ( select_dual=C_DISABLE ) else dual_hi;
lo <= main_lo when ( select_dual=C_DISABLE ) else dual_lo;
dout_hi <= ( hi xor diff_hi ) when ( check_dual=C_ENABLE ) else hi;
dout_lo <= ( lo xor diff_lo ) when ( check_dual=C_ENABLE ) else lo;
-- Error triggers, each pair of FFs is checked on the opposite clock edge
-- (e.g., positive FFs are compared on falling clock edge)
P_ERR_HI : process( clk, rst )
begin
if ( rst=RESET_ACTIVE ) then
error_on_diff_hi <= not C_BROKEN;
elsif ( clk='0' and clk'event ) then
if ( check_dual=C_ENABLE ) then
if ( unsigned(diff_hi) /= 0 ) then
error_on_diff_hi <= C_BROKEN;
end if; -- compare
end if; -- check_dual
end if; -- clk, rst
end process P_ERR_HI;
P_ERR_LO : process( clk, rst )
begin
if ( rst=RESET_ACTIVE ) then
error_on_diff_lo <= not C_BROKEN;
elsif ( clk='1' and clk'event ) then
if ( check_dual=C_ENABLE ) then
if ( unsigned(diff_lo) /= 0 ) then
error_on_diff_lo <= C_BROKEN;
end if; -- compare
end if; -- check_dual
end if; -- clk, rst
end process P_ERR_LO;
end a_ddr_dual;
| mit | 59a59917ca5754dcbd65a73eff638138 | 0.557073 | 3.331528 | false | false | false | false |
mike7c2/befunge_processor | befunge_processor_v2.vhd | 1 | 28,974 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_processor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--TODO - make PC and address signals use std_logic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED;
--(dont)--use work.befunge_pkg.all;--not now anyway
entity befunge_processor_v2 is
generic
(
grid_power : integer := 3;
word_size : integer := 8;
instruction_size : integer := 16;
stack_size : integer := 4;
grid_width : integer := 8;
grid_height : integer := 8
);
port
(
--DEBUG
FDE_OUT : OUT std_logic_vector(word_size-1 downto 0);
INSTRUCTION_OUT : OUT std_logic_vector(word_size-1 downto 0);
GRID_ADDRESS_OUT : OUT std_logic_vector((grid_power * 2)-1 downto 0);
--DEBUG
clk,reset : in std_logic;
data_in : in std_logic_vector(word_size-1 downto 0);
data_out : out std_logic_vector(word_size-1 downto 0)
);
end befunge_processor_v2;
architecture processor_v1 of befunge_processor_v2 is
component befunge_pc_v2 is
generic(
grid_power : integer
);
port(
clk : in std_logic;
reset : in std_logic;
pc_address : out std_logic_vector((grid_power * 2)-1 downto 0);
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end component;
component befunge_alu is
generic(
word_size : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
a : in std_logic_vector(word_size-1 downto 0);
b : in std_logic_vector(word_size-1 downto 0);
result : out std_logic_vector(word_size-1 downto 0);
op : in std_logic_vector(2 downto 0);
en : in std_logic;
working : out std_logic
);
end component;
component befunge_stack is
generic(
stack_depth_pow : integer;
word_size : integer
);
port(
clk : in std_logic;
reset : in std_logic;
stack_0_o : out std_logic_vector(word_size-1 downto 0);
stack_1_o : out std_logic_vector(word_size-1 downto 0);
stack_i : in std_logic_vector(word_size-1 downto 0);
pop1 : in std_logic;
pop2 : in std_logic;
push : in std_logic;
swap : in std_logic;
en : in std_logic
);
end component;
constant word_zero : std_logic_vector(word_size -1 downto 0) := (others => '0');
--((grid_height*grid_width)-1 downto 0)
type grid_declaration is array(0 to (2**(grid_power*2))-1) of std_logic_vector(word_size-1 downto 0);
signal grid : grid_declaration :=
(
std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('1'),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),
std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('1'),word_size)),std_logic_vector(to_unsigned(character'pos('+'),word_size)),std_logic_vector(to_unsigned(character'pos(':'),word_size)),std_logic_vector(to_unsigned(character'pos('2'),word_size)),std_logic_vector(to_unsigned(character'pos('-'),word_size)),
std_logic_vector(to_unsigned(character'pos('_'),word_size)),std_logic_vector(to_unsigned(character'pos('^'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),
std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('>'),word_size)),
std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('h'),word_size)),std_logic_vector(to_unsigned(character'pos('e'),word_size)),std_logic_vector(to_unsigned(character'pos('l'),word_size)),std_logic_vector(to_unsigned(character'pos('l'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),
std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('o'),word_size)),std_logic_vector(to_unsigned(character'pos('w'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('o'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('<'),word_size)),
std_logic_vector(to_unsigned(character'pos('>'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('r'),word_size)),std_logic_vector(to_unsigned(character'pos('l'),word_size)),std_logic_vector(to_unsigned(character'pos('d'),word_size)),std_logic_vector(to_unsigned(character'pos('"'),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),
std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('v'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size)),std_logic_vector(to_unsigned(character'pos('<'),word_size)),std_logic_vector(to_unsigned(character'pos(' '),word_size))
);
--(others =>(std_logic_vector(to_unsigned(character'pos('<'),word_size)))); --GO EAST!!!
--grid looks like
-- +----grid_width--------
-- |
-- |
--grid_height
-- |
-- |
--(x,y) is therefore x+(y*grid_width), which makes hardware a little more complex :(
type fde_cycle_states is (idle,fetch,decode,execute,step,nop, alu, alu2, get, get2, put, put2);
signal fde_cycle,fde_previous : fde_cycle_states := idle;
signal grid_data_in,grid_data_out : std_logic_vector(word_size-1 downto 0);
signal grid_address : std_logic_vector((grid_power * 2)-1 downto 0);
signal grid_load : std_logic;
signal grid_store : std_logic;
signal grid_access : std_logic;
signal grid_access_address : std_logic_vector((grid_power * 2)-1 downto 0);
signal dir : std_logic_vector(1 downto 0);
signal pc_address : std_logic_vector((grid_power * 2)-1 downto 0);
signal pc_skip : std_logic;
signal pc_enable : std_logic;
signal stack_0 : std_logic_vector(word_size-1 downto 0);
signal stack_1 : std_logic_vector(word_size-1 downto 0);
signal stack_i : std_logic_vector(word_size-1 downto 0);
signal stack_pop1 : std_logic;
signal stack_pop2 : std_logic;
signal stack_push : std_logic;
signal stack_swap : std_logic;
signal stack_en : std_logic;
signal alu_a : std_logic_vector(word_size-1 downto 0);
signal alu_b : std_logic_vector(word_size-1 downto 0);
signal alu_result : std_logic_vector(word_size-1 downto 0);
signal alu_op : std_logic_vector(2 downto 0);
signal alu_en : std_logic;
signal alu_working : std_logic;
signal string_mode : std_logic;
begin
--DEBUG
GRID_ADDRESS_OUT <= grid_address;
data_out <= grid_data_out;
-- grid_data_in <= data_in;
--DEBUG
alu_inst : befunge_alu
generic map
(
word_size
)
port map
(
clk,
reset,
alu_a,
alu_b,
alu_result,
alu_op,
alu_en,
alu_working
);
stack : befunge_stack
generic map
(
8,
word_size
)
port map
(
clk,
reset,
stack_0,
stack_1,
stack_i,
stack_pop1,
stack_pop2,
stack_push,
stack_swap,
stack_en
);
alu_a <= stack_0;
alu_b <= stack_1;
program_counter : befunge_pc_v2
generic map
(
grid_power
)
port map
(
clk,
reset,
pc_address,
dir,
pc_skip,
pc_enable
);
--Can't do that any more :(
--TODO : this shit needs casted
grid_address <= pc_address when grid_access = '0' else grid_access_address;--to_integer(signed(stack_top));
--grid_address_y <= stack_s1;
--The grid must handle a write from a store instruction
--the grid must handle a read from the pc address
--the grid must handle a read from a load instruction
grid_process : process(reset,clk)
variable push_flag : std_logic := '0';
begin
if(reset = '1') then
fde_cycle <= idle;
stack_pop1 <= '0';
stack_pop2 <= '0';
stack_push <= '0';
stack_swap <= '0';
string_mode <= '0';
pc_skip <= '0';
dir <= "00";
--grid_data_out <= grid(0);
else
if rising_edge(clk) then
--set all signals inside this and we're laughing
--fetch execute cycle that we can use to synchronise read/write signals
case fde_cycle is
when nop =>
FDE_OUT <= X"04";
fde_cycle <= fde_previous;
when idle =>
FDE_OUT <= X"00";
pc_enable <= '0';
pc_skip <= '0';
grid_load <= '0';
push_flag := '0';
stack_push <= '0';
stack_en <= '0';
stack_pop1 <= '0';
stack_pop2 <= '0';
stack_swap <= '0';
alu_en <= '0';
fde_cycle <= fetch;
when fetch =>
FDE_OUT <= X"01";
grid_load <= '1';
fde_cycle <= decode;
when decode =>
FDE_OUT <= X"02";
grid_load <= '0';
fde_cycle <= execute;
when execute =>
fde_cycle <= step; --this must be at the start of the case so it can be overriden
FDE_OUT <= X"03";
grid_load <= '0';
if (string_mode = '0' ) then
--*********************************************Load Literal************************************************************
if ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('0'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(0, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('1'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(1, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('2'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(2, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('3'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(3, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('4'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(4, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('5'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(5, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('6'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(6, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('7'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(7, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('8'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(8, word_size));
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('9'), word_size))) then
stack_i <= std_logic_vector(to_unsigned(9, word_size));
push_flag := '1';
--*********************************************Alu ops*****************************************************************
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('+'), word_size))) then
alu_op <= "000";
alu_en <= '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('-'), word_size))) then
alu_op <= "001";
alu_en <= '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('*'), word_size))) then
alu_op <= "010";
alu_en <= '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('/'), word_size))) then
alu_op <= "011";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('%'), word_size))) then
alu_op <= "100";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop2 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('!'), word_size))) then
alu_op <= "101";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop1 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('''), word_size))) then
alu_op <= "110";
alu_en <= '1';
push_flag := '1';
fde_cycle <= alu;
stack_en <= '1';
stack_pop1 <= '1';
--*********************************************Control flow************************************************************
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('<'), word_size))) then --move left!!
INSTRUCTION_OUT <= X"00";
dir <= "10";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('>'), word_size))) then --move right!!
INSTRUCTION_OUT <= X"01";
dir <= "00";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('^'), word_size))) then --move up!!
INSTRUCTION_OUT <= X"02";
dir <= "01";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('v'), word_size))) then --move down!!
INSTRUCTION_OUT <= X"03";
dir <= "11";
--fde_cycle <= nop;
--fde_previous <= idle;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('|'), word_size))) then --verticle switch!!
fde_cycle <= step;
stack_en <= '1';
stack_pop1 <= '1';
if ( stack_0 = word_zero ) then
dir <= "11";
else
dir <= "01";
end if;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('_'), word_size))) then --horizontal switch!!
fde_cycle <= step;
stack_en <= '1';
stack_pop1 <= '1';
if ( stack_0 = word_zero ) then
dir <= "00";
else
dir <= "10";
end if;
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('?'), word_size))) then --move in random direction
fde_cycle <= step;
dir <= "10"; --High quality random number obtained using http://www.random.org/integers/
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos(':'), word_size))) then --duplicate stack
fde_cycle <= step;
stack_i <= stack_0;
push_flag := '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('\'), word_size))) then --swap stack
fde_cycle <= step;
stack_en <= '1';
stack_swap <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('$'), word_size))) then --discard stack
fde_cycle <= step;
stack_en <= '1';
stack_pop1 <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('$'), word_size))) then --trampoline
fde_cycle <= step;
pc_skip <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('"'), word_size))) then --String mode
fde_cycle <= step;
string_mode <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('p'), word_size))) then --put
fde_cycle <= put;
grid_access_address((grid_power * 2)-1 downto ((grid_power*2)/2)) <= stack_0(grid_power-1 downto 0);
grid_access_address(((grid_power * 2)/2)-1 downto 0) <= stack_1(grid_power-1 downto 0);
grid_access <= '1';
stack_pop2 <= '1';
stack_en <= '1';
elsif ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('g'), word_size))) then --get
fde_cycle <= get;
grid_access <= '1';
stack_pop2 <= '1';
stack_en <= '1';
grid_access_address((grid_power * 2)-1 downto ((grid_power*2)/2)) <= stack_0(grid_power-1 downto 0);
grid_access_address(((grid_power * 2)/2)-1 downto 0) <= stack_1(grid_power-1 downto 0);
else
INSTRUCTION_OUT <= X"04";
--fde_cycle <= nop;
--fde_previous <= idle;
end if;
else -- string mode
fde_cycle <= step;
if ( grid_data_out = std_logic_vector(to_Unsigned(character'pos('"'), word_size))) then -- end string mode
string_mode <= '0';
else
push_flag := '1';
stack_i <= grid_data_out;
end if;
end if;
when alu =>
FDE_OUT <= X"04";
alu_en <= '0';
stack_en <= '0';
stack_pop1 <= '0';
stack_pop2 <= '0';
fde_cycle <= alu2;
when alu2 =>
FDE_OUT <= X"05";
if ( alu_working = '0' ) then
fde_cycle <= step;
stack_i <= alu_result;
push_flag := '1';
else
fde_cycle <= alu;
end if;
when get =>
fde_cycle <= get2;
stack_en <= '0';
stack_pop2 <= '0';
grid_load <= '1';
when get2 =>
fde_cycle <= step;
stack_i <= grid_data_out;
grid_load <= '0';
push_flag := '1';
when put =>
fde_cycle <= put2;
stack_en <= '1';
stack_pop1 <= '1';
grid_data_in <= stack_0;
when put2 =>
fde_cycle <= step;
stack_en <= '0';
stack_pop1 <= '0';
grid_store <= '1';
when step =>
if ( push_flag = '1' ) then
stack_en <= '1';
stack_push <= '1';
push_flag := '0';
else
stack_en <= '0';
end if;
stack_pop1 <= '0';
stack_pop2 <= '0';
stack_swap <= '0';
FDE_OUT <= X"06";
grid_load <= '0';
grid_store <= '0';
pc_enable <= '1';
fde_cycle <= idle;
grid_access <= '0';
end case;
--only write the grid when the grid_store flag is enabled
if (grid_store = '1') then
INSTRUCTION_OUT <= X"AD";
grid(to_integer(unsigned(grid_address))) <= grid_data_in;
end if;
if (grid_load = '1') then
INSTRUCTION_OUT <= X"FF";
grid_data_out <= grid(to_integer(unsigned(grid_address)));
--else
-- grid_data_out <= grid(pc_address);
end if;
end if;
end if;
end process;
end processor_v1;
| unlicense | 94beb714e61a44d0c4bb55772d6c8571 | 0.405225 | 4.530727 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-08B.vhd | 1 | 7,529 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08B.vhd
-- Creation Date: 21:55:54 27/01/2010
-- Description:
-- Q Register and Storage Protection
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Gates_package.all;
use work.PH;
entity QReg_STP is
Port (
-- Inputs
SA_REG : in STD_LOGIC_VECTOR (0 to 7); -- Stack address, F0-FF are MS storage keys, 00-EF are CCW storage keys
Z_BUS : in STD_LOGIC_VECTOR (0 to 8); -- Z bus used to write to Q reg
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : in STD_LOGIC; -- Selector channel cycle inputs
N_SEL_SHARE_HOLD : in STD_LOGIC; -- Selector channel share cycle
MAIN_STG : in STD_LOGIC; -- Main Storage usage
H_REG_5_PWR : in STD_LOGIC; -- Priority Reg from 04C
FORCE_M_REG_123 : in STD_LOGIC; -- When setting M reg for LS, from 04D
GT_LOCAL_STORAGE : in STD_LOGIC; -- Local Storage usage
GT_T_REG_TO_MN, GT_CK_TO_MN : in STD_LOGIC; -- These operations inhibit storage protect when used with LS
MAIN_STG_CP_1 : in STD_LOGIC; -- Main Storage clock pulse
N_MEM_SELECT : in STD_LOGIC;
N_STACK_MEMORY_SELECT : in STD_LOGIC; -- Indicates that Stack memory should be read/written
STACK_RD_WR_CONTROL : in STD_LOGIC; -- T to indicate Stack is being Read, F to indicate Write
E_SW_SEL_Q : in STD_LOGIC; -- E switch Q Reg selection
MAN_STORE_PWR : in STD_LOGIC; -- Manual Store switch for setting Q Reg
T4 : in STD_LOGIC; -- Main clock phase
MACH_RST_2B : in STD_LOGIC; -- Main system reset
Z_BUS_LO_DIG_PARITY : in STD_LOGIC; -- Parity of Z bus bits 4-7
CD_REG : in STD_LOGIC_VECTOR (0 to 3); -- ALU destination - 0011 specifies Q Reg
CLOCK_OFF : in STD_LOGIC; -- CPU clock stop
GK, HK : in STD_LOGIC_VECTOR (0 to 3); -- Storage key from SX1, SX2
CLK : in STD_LOGIC; -- 50MHz FPGA clock
-- Outputs
Q_REG_BUS : out STD_LOGIC_VECTOR (0 to 8); -- Q Reg output
SEL_CPU_BUMP : out STD_LOGIC; -- Select usage of Aux Storage
STACK_PC : out STD_LOGIC; -- Stack data Parity Check error
MPX_CP : out STD_LOGIC; -- MPX clock pulse
MAIN_STG_CP : out STD_LOGIC; -- MS clock pulse
PROTECT_LOC_CPU_OR_MPX : out STD_LOGIC; -- Storage Protection check from CPU or MPX
PROTECT_LOC_SEL_CHNL : out STD_LOGIC -- Storage Protection check from SX1 or SX2
);
end QReg_STP;
architecture FMD of QReg_STP is
signal Q_REG : STD_LOGIC_VECTOR(0 to 8);
signal INH_STG_PROT : STD_LOGIC;
signal sSTACK_PC : STD_LOGIC;
signal UseQ : STD_LOGIC;
signal SET_Q_HI, SET_Q_LO : STD_LOGIC;
subtype stackData is STD_LOGIC_VECTOR(4 to 8);
type stack is array(0 to 255) of stackData;
signal STP_STACK : stack;
signal STACK_DATA : stackData;
signal Q0_GK0_HK0, Q1_GK1_HK1, Q2_GK2_HK2, Q3_GK3_HK3 : STD_LOGIC;
signal STP : STD_LOGIC;
signal HDWR_STG_KEYS_MAT : STD_LOGIC;
signal CD0011 : STD_LOGIC;
signal STACK_DATA_STROBE, READ_GATE, WRITE_GATE, INHIBIT_TIMING : STD_LOGIC;
type delay is array(0 to 24) of std_logic;
signal delayLine : delay := (others=>'0');
signal setLatch, resetLatch : std_logic;
signal latch : std_logic;
signal INH_STG_PROT_PH_D : std_logic;
signal Q47P_D : std_logic_vector(4 to 8);
begin
Q0_GK0_HK0 <= (HK(0) and SX2_SHARE_CYCLE) or (GK(0) and SX1_SHARE_CYCLE) or (Q_REG(0) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q1_GK1_HK1 <= (HK(1) and SX2_SHARE_CYCLE) or (GK(1) and SX1_SHARE_CYCLE) or (Q_REG(1) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q2_GK2_HK2 <= (HK(2) and SX2_SHARE_CYCLE) or (GK(2) and SX1_SHARE_CYCLE) or (Q_REG(2) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
Q3_GK3_HK3 <= (HK(3) and SX2_SHARE_CYCLE) or (GK(3) and SX1_SHARE_CYCLE) or (Q_REG(3) and N_SEL_SHARE_HOLD); -- BE3E4 BE3F3
STP <= not INH_STG_PROT and MAIN_STG and (Q0_GK0_HK0 or Q1_GK1_HK1 or Q2_GK2_HK2 or Q3_GK3_HK3); -- BE3F4
HDWR_STG_KEYS_MAT <= (Q0_GK0_HK0 xnor Q_REG(0)) and (Q1_GK1_HK1 xnor Q_REG(1)) and (Q2_GK2_HK2 xnor Q_REG(2)) and (Q3_GK3_HK3 xnor Q_REG(3)); -- BE3F3
PROTECT_LOC_CPU_OR_MPX <= (not H_REG_5_PWR) and STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
PROTECT_LOC_SEL_CHNL <= STP and (sSTACK_PC or not HDWR_STG_KEYS_MAT); -- BE3F2
INH_STG_PROT_PH_D <= GT_T_REG_TO_MN or GT_CK_TO_MN;
INH_STG_PROT_PH: entity PH port map(INH_STG_PROT_PH_D,GT_LOCAL_STORAGE,INH_STG_PROT); -- AA1F4
SEL_CPU_BUMP_PH: entity PH port map(FORCE_M_REG_123,GT_LOCAL_STORAGE,SEL_CPU_BUMP); -- AA1F4
STACK_PC <= sSTACK_PC;
MPX_CP <= not MAIN_STG_CP_1; -- BE3D3 BE3G4
MAIN_STG_CP <= MAIN_STG_CP_1; -- BE3G4
CD0011 <= '1' when CD_REG="0011" else '0';
UseQ <= (CD0011 and (N_SEL_SHARE_HOLD or (not CLOCK_OFF))) or (CLOCK_OFF and N_MEM_SELECT and N_SEL_SHARE_HOLD); -- BE3J3 BE3G4 BE3J3
SET_Q_HI <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ); -- BE3J4
SET_Q_LO <= MACH_RST_2B or (MAN_STORE_PWR and E_SW_SEL_Q) or (T4 and UseQ) or (STACK_RD_WR_CONTROL and STACK_DATA_STROBE); -- BE3J4
Q03: PHV4 port map(Z_BUS(0 to 3),SET_Q_HI,Q_REG(0 to 3)); -- BE3H2
Q47P_D <= ((Z_BUS(4 to 7) & Z_BUS_LO_DIG_PARITY) and (4 to 8 => UseQ)) or (STACK_DATA(4 to 8) and not (4 to 8 => UseQ));
Q47P: PHV5 port map(Q47P_D, SET_Q_LO, Q_REG(4 to 8));
Q_REG_BUS <= Q_REG;
sSTACK_PC <= EvenParity(Q_REG(4 to 7));
STP_FL: process(clk)
begin
if rising_edge(clk) then
setLatch <= not N_STACK_MEMORY_SELECT;
delayLine <= setLatch & delayLine(0 to 23);
STACK_DATA_STROBE <= delayLine(7); -- 140ns
resetLatch <= not delayLine(24);
if (setLatch='1') then latch <= '1'; end if;
if (resetLatch='1') then latch <= '0'; end if;
READ_GATE <= latch and STACK_RD_WR_CONTROL;
WRITE_GATE <= latch and not STACK_RD_WR_CONTROL;
INHIBIT_TIMING <= latch and not READ_GATE;
if WRITE_GATE='1' then
STP_STACK(Conv_Integer(SA_REG)) <= Q_REG(4 to 8);
elsif READ_GATE='1' then
STACK_DATA <= STP_STACK(Conv_Integer(SA_REG));
end if;
end if;
end process;
end FMD;
| gpl-3.0 | 8bc1e257c5ab959d1fc4b55d861b921e | 0.636871 | 2.712176 | false | false | false | false |
TheMassController/VHDL_experimenting | project/deppSlave/test/depp_tb_pkg.vhd | 1 | 18,785 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library src;
use src.depp_pkg.all;
use src.bus_pkg.all;
package depp_tb_pkg is
type depp_slave_state_type is record
address : bus_address_type;
writeData : bus_data_type;
readData : bus_data_type;
writeMask : bus_write_mask;
deppMode : depp_data_type;
fault : boolean;
end record;
constant DEPP_SLAVE_STATE_TYPE_IDLE : depp_slave_state_type := (
address => (others => '0'),
writeData => (others => '0'),
readData => (others => '0'),
writeMask => (others => '0'),
deppMode => (others => '0'),
fault => false
);
procedure depp_tb_depp_set_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant addr : in depp_address_type
);
procedure depp_tb_depp_set_data (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant data : in depp_data_type;
constant expect_completion : in boolean
);
procedure depp_tb_depp_get_data (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
variable data : out depp_data_type;
constant expect_completion : in boolean
);
procedure depp_tb_depp_write_to_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant addr : in depp_address_type;
constant data : in depp_data_type
);
procedure depp_tb_depp_read_from_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant addr : in depp_address_type;
variable data : out depp_data_type
);
procedure depp_tb_bus_set_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant address : in bus_address_type
);
procedure depp_tb_bus_prepare_write (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant address : in bus_address_type;
constant writeData : in bus_data_type;
constant writeMask : in bus_write_mask
);
procedure depp_tb_bus_prepare_read (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant address : in bus_address_type
);
procedure depp_tb_bus_start_transaction (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant doRead : in boolean
);
procedure depp_tb_bus_finish_write_transaction (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic
);
procedure depp_tb_bus_finish_read_transaction (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
variable data : out depp_data_type
);
procedure depp_tb_slave_check_state (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
variable actualState : out depp_slave_state_type
);
end depp_tb_pkg;
package body depp_tb_pkg is
procedure depp_tb_depp_set_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant addr : in std_logic_vector(7 downto 0)
) is
begin
usb_write <= '1';
usb_astb <= '1';
usb_dstb <= '1';
usb_db <= (others => 'Z');
wait until usb_wait = '0' and falling_edge(clk);
usb_db <= addr;
usb_astb <= '0';
usb_write <= '0';
wait until usb_wait = '1' and falling_edge(clk);
end procedure;
procedure depp_tb_depp_set_data (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant data : in depp_data_type;
constant expect_completion : in boolean
) is
begin
usb_db <= (others => 'Z');
usb_astb <= '1';
usb_dstb <= '1';
usb_write <= '1';
wait until usb_wait = '0' and falling_edge(clk);
usb_db <= data;
usb_dstb <= '0';
usb_write <= '0';
if expect_completion then
wait until usb_wait = '1' and falling_edge(clk);
usb_db <= (others => 'Z');
usb_dstb <= '1';
usb_write <= '1';
end if;
end procedure;
procedure depp_tb_depp_get_data (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
variable data : out depp_data_type;
constant expect_completion : in boolean
) is
begin
usb_db <= (others => 'Z');
usb_astb <= '1';
usb_dstb <= '1';
usb_write <= '1';
wait until usb_wait = '0' and falling_edge(clk);
usb_dstb <= '0';
if expect_completion then
wait until usb_wait = '1' and falling_edge(clk);
data := usb_db;
usb_dstb <= '1';
else
data := (others => '0');
end if;
end procedure;
procedure depp_tb_depp_write_to_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant addr : in std_logic_vector(7 downto 0);
constant data : in std_logic_vector(7 downto 0)
) is
begin
depp_tb_depp_set_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => addr
);
depp_tb_depp_set_data(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
data => data,
expect_completion => true
);
end procedure;
procedure depp_tb_depp_read_from_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant addr : in depp_address_type;
variable data : out depp_data_type
) is
begin
depp_tb_depp_set_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => addr
);
depp_tb_depp_get_data(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
data => data,
expect_completion => true
);
end procedure;
procedure depp_tb_bus_set_address (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant address : in bus_address_type
) is
begin
for b in 0 to depp2bus_addr_reg_len - 1 loop
depp_tb_depp_write_to_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_addr_reg_start + b, usb_db'length)),
data => address((b+1)*8 - 1 downto b*8)
);
end loop;
end procedure;
procedure depp_tb_bus_prepare_write (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant address : in bus_address_type;
constant writeData : in bus_data_type;
constant writeMask : in bus_write_mask
) is
variable writeMaskReg : std_logic_vector(7 downto 0);
begin
writeMaskReg := (others => '0');
writeMaskReg(writeMask'range) := writeMask;
-- Address
depp_tb_bus_set_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
address => address
);
-- writeData
for b in 0 to depp2bus_writeData_reg_len - 1 loop
depp_tb_depp_write_to_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_writeData_reg_start + b, usb_db'length)),
data => writeData((b+1)*8 - 1 downto b*8)
);
end loop;
depp_tb_depp_write_to_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_write_mask_reg_start, usb_db'length)),
data => writeMaskReg
);
end procedure;
procedure depp_tb_bus_prepare_read (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant address : in bus_address_type
) is
begin
depp_tb_bus_set_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
address => address
);
end procedure;
procedure depp_tb_bus_start_transaction (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
constant doRead : in boolean
) is
variable activateReg : std_logic_vector(7 downto 0) := (others => '0');
begin
if doRead then
activateReg(0) := '1';
end if;
usb_write <= '1';
usb_astb <= '1';
usb_dstb <= '1';
usb_db <= (others => 'Z');
wait until usb_wait = '0' and falling_edge(clk);
usb_db <= std_logic_vector(to_unsigned(depp2bus_activation_register_start, usb_db'length));
usb_astb <= '0';
usb_write <= '0';
wait until usb_wait = '1' and falling_edge(clk);
usb_db <= (others => 'Z');
usb_astb <= '1';
usb_write <= '1';
wait until usb_wait = '0' and falling_edge(clk);
usb_db <= activateReg;
usb_dstb <= '0';
usb_write <= '0';
end procedure;
procedure depp_tb_bus_finish_write_transaction (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic
) is
begin
wait until usb_wait = '1' and falling_edge(clk);
usb_db <= (others => 'Z');
usb_dstb <= '1';
usb_write <= '1';
wait until usb_wait = '0' and falling_edge(clk);
end procedure;
procedure depp_tb_bus_finish_read_transaction (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
variable data : out depp_data_type
) is
begin
wait until usb_wait = '1' and falling_edge(clk);
data := usb_db;
usb_dstb <= '1';
usb_write <= '1';
wait until usb_wait = '0' and falling_edge(clk);
usb_db <= (others => 'Z');
end procedure;
procedure depp_tb_slave_check_state (
signal clk : in std_logic;
signal usb_db : inout std_logic_vector(7 downto 0);
signal usb_write : out std_logic;
signal usb_astb : out std_logic;
signal usb_dstb : out std_logic;
signal usb_wait : in std_logic;
variable actualState : out depp_slave_state_type
) is
variable faultReg : depp_data_type := (others => '0');
variable writeMaskReg : depp_data_type := (others => '0');
begin
for b in 0 to depp2bus_addr_reg_len - 1 loop
depp_tb_depp_read_from_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_addr_reg_start + b, usb_db'length)),
data => actualState.address((b+1)*8 - 1 downto b*8)
);
end loop;
for b in 0 to depp2bus_writeData_reg_len - 1 loop
depp_tb_depp_read_from_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_writeData_reg_start + b, usb_db'length)),
data => actualState.writeData((b+1)*8 - 1 downto b*8)
);
end loop;
for b in 0 to depp2bus_readData_reg_len - 1 loop
depp_tb_depp_read_from_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_readData_reg_start + b, usb_db'length)),
data => actualState.readData((b+1)*8 - 1 downto b*8)
);
end loop;
depp_tb_depp_read_from_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_write_mask_reg_start, usb_db'length)),
data => writeMaskReg
);
actualState.writeMask := writeMaskReg(actualState.writeMask'range);
depp_tb_depp_read_from_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_mode_register_start, usb_db'length)),
data => actualState.deppMode
);
depp_tb_depp_read_from_address(
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => std_logic_vector(to_unsigned(depp2bus_fault_register_start, usb_db'length)),
data => faultReg
);
actualState.fault := faultReg(0) = '1';
end procedure;
end depp_tb_pkg;
| mit | 1c566f16ab546923cc51e2a0965620b4 | 0.532499 | 3.762267 | false | false | false | false |
chastell/art-decomp | kiss/tav_jed.vhd | 1 | 4,968 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tav_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end tav_jed;
architecture behaviour of tav_jed is
constant st0: std_logic_vector(1 downto 0) := "11";
constant st1: std_logic_vector(1 downto 0) := "00";
constant st2: std_logic_vector(1 downto 0) := "01";
constant st3: std_logic_vector(1 downto 0) := "10";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "1000") then next_state <= st1; output <= "1000";
elsif std_match(input, "0100") then next_state <= st1; output <= "0100";
elsif std_match(input, "0010") then next_state <= st1; output <= "0010";
elsif std_match(input, "0001") then next_state <= st1; output <= "0001";
elsif std_match(input, "0000") then next_state <= st1; output <= "0000";
elsif std_match(input, "11--") then next_state <= st1; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st1; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st1; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st1; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st1; output <= "0000";
elsif std_match(input, "--11") then next_state <= st1; output <= "0000";
end if;
when st1 =>
if std_match(input, "1000") then next_state <= st2; output <= "1000";
elsif std_match(input, "0100") then next_state <= st2; output <= "0100";
elsif std_match(input, "0010") then next_state <= st2; output <= "0010";
elsif std_match(input, "0001") then next_state <= st2; output <= "0001";
elsif std_match(input, "1100") then next_state <= st2; output <= "1100";
elsif std_match(input, "1010") then next_state <= st2; output <= "1010";
elsif std_match(input, "1001") then next_state <= st2; output <= "1001";
elsif std_match(input, "0110") then next_state <= st2; output <= "0000";
elsif std_match(input, "0000") then next_state <= st2; output <= "0000";
elsif std_match(input, "0011") then next_state <= st2; output <= "0011";
elsif std_match(input, "0101") then next_state <= st2; output <= "0101";
elsif std_match(input, "0111") then next_state <= st2; output <= "0001";
elsif std_match(input, "1011") then next_state <= st2; output <= "1011";
elsif std_match(input, "1101") then next_state <= st2; output <= "1101";
elsif std_match(input, "1110") then next_state <= st2; output <= "1000";
elsif std_match(input, "1111") then next_state <= st2; output <= "1001";
end if;
when st2 =>
if std_match(input, "1000") then next_state <= st3; output <= "1000";
elsif std_match(input, "0100") then next_state <= st3; output <= "0100";
elsif std_match(input, "0010") then next_state <= st3; output <= "0010";
elsif std_match(input, "0001") then next_state <= st3; output <= "0001";
elsif std_match(input, "0000") then next_state <= st3; output <= "0000";
elsif std_match(input, "11--") then next_state <= st3; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st3; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st3; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st3; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st3; output <= "0000";
elsif std_match(input, "--11") then next_state <= st3; output <= "0000";
end if;
when st3 =>
if std_match(input, "1000") then next_state <= st0; output <= "1000";
elsif std_match(input, "0100") then next_state <= st0; output <= "0100";
elsif std_match(input, "0010") then next_state <= st0; output <= "0010";
elsif std_match(input, "0001") then next_state <= st0; output <= "0001";
elsif std_match(input, "0000") then next_state <= st0; output <= "0000";
elsif std_match(input, "11--") then next_state <= st0; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st0; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st0; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st0; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st0; output <= "0000";
elsif std_match(input, "--11") then next_state <= st0; output <= "0000";
end if;
when others => next_state <= "--"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | 099d5b87f4e99a6875a44325b42613d1 | 0.588164 | 3.314209 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-03B.vhd | 1 | 6,400 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Storage Wrap (references >8k, >16k, >32k or wrapping over 64k)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Reset UMPX latch on RECYCLE_RST
-- Change to 64k wrap
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY StorageWrap IS
port
(
-- Inputs
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
ANY_PRIORITY_PULSE_2 : IN STD_LOGIC; -- 03A
H_REG_5_PWR,H_REG_6 : IN STD_LOGIC; -- 04C
NTRUE : IN STD_LOGIC; -- 06B
CARRY_0 : IN STD_LOGIC; -- 06B
COMPLEMENT : IN STD_LOGIC; -- 06B
GT_J_TO_N_REG,GT_V_TO_N_REG : IN STD_LOGIC; -- 05B
M012 : IN STD_LOGIC_VECTOR(0 to 2); -- 07B
RECYCLE_RST : IN STD_LOGIC; -- 04A
ALLOW_WRITE : IN STD_LOGIC; -- 03D
READ_CALL : IN STD_LOGIC; -- 05D
MAIN_STORAGE : IN STD_LOGIC; -- 04D
DATA_READY_1,DATA_READY_2 : IN STD_LOGIC; -- 05D
-- Outputs
GT_CK_DECO : OUT STD_LOGIC; -- 03C,04C
SEL_DATA_READY : OUT STD_LOGIC; -- 11C,13C,06C
MEM_WRAP_REQ : OUT STD_LOGIC; -- 03A
MEM_WRAP : OUT STD_LOGIC; -- 06C,11A,13A
I_WRAPPED_CPU,U_WRAPPED_MPX : OUT STD_LOGIC; -- 02A
-- Clocks
T1,T2,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END StorageWrap;
ARCHITECTURE FMD OF StorageWrap IS
signal RESTORE_WRAP,STORE_WRAP : STD_LOGIC;
signal U_WRAP_CPU,WRAP_BUFF : STD_LOGIC; -- PH outputs
signal NOT_MPX_OR_SEL,ALL_B_GATED,DEST_U,DEST_I_OR_RESTORE,CARRY_OUT_TRUE,CARRY_OUT_COMP,WRAP_TRUE,RESET_WRAP,CHECK_U_WRAP,CHECK_I_WRAP,CHECK_MPX_WRAP,CARRY_OUT : STD_LOGIC;
signal WRAP64 : STD_LOGIC;
signal sGT_CK_DECO : STD_LOGIC;
signal sMEM_WRAP_REQ : STD_LOGIC;
signal sMEM_WRAP : STD_LOGIC;
signal sI_WRAPPED_CPU, sU_WRAPPED_MPX : STD_LOGIC;
signal UWRAP_LCH_Reset,MWR_LCH_Set,MWR_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-03B
sGT_CK_DECO <= not ANY_PRIORITY_PULSE_2 and SALS.SALS_AK and P1; -- AB3B3,AB3F6 ??
GT_CK_DECO <= sGT_CK_DECO;
RESTORE_WRAP <= '1' when SALS.SALS_AK='1' and SALS.SALS_CK="0010" else '0'; -- AB3E6
STORE_WRAP <= '1' when not (sGT_CK_DECO='1' and SALS.SALS_CK="1100") else '0'; -- AB3E6,AB3L6
-- The Wrap latches remember whether a carry was associated with values stored in the U or I registers
-- If so that means we wrapped around from 64k to 0. The Wrap latches are only used if the UV/IJ value is
-- subsequently moved into MN
NOT_MPX_OR_SEL <= not(H_REG_5_PWR or H_REG_6); -- AB2L4
-- "ALL_B_GATED" means reset U wrap ??
-- "not ALL_B_GATED" means check U wrap ??
-- The FMD doesn't seem to show this way around, but microcode (e.g. QA781:C3) implies it
ALL_B_GATED <= not (not CTRL.GT_B_REG_HI or not CTRL.GT_B_REG_LO); -- AB2M3
DEST_U <= '1' when CTRL.CTRL_CD="1101" and T4='1' else '0'; -- AB2M3
DEST_I_OR_RESTORE <= '1' when (T4='1' and CTRL.CTRL_CD="1111") or (T1='1' and RESTORE_WRAP='1') else '0'; -- AB2M2 AB2M5
CARRY_OUT_TRUE <= not RESTORE_WRAP and NTRUE and CARRY_0; -- AB2M3 AB2L3
CARRY_OUT_COMP <= COMPLEMENT and not CARRY_0; -- AB2M3
WRAP_TRUE <= CARRY_OUT_TRUE or (RESTORE_WRAP and WRAP_BUFF); -- AB2L3
RESET_WRAP <= NOT_MPX_OR_SEL and ALL_B_GATED and DEST_U; -- AB2M3
CHECK_U_WRAP <= NOT_MPX_OR_SEL and DEST_U and not ALL_B_GATED; -- AB2L4
CHECK_I_WRAP <= NOT_MPX_OR_SEL and DEST_I_OR_RESTORE; -- AB2L4
CHECK_MPX_WRAP <= H_REG_6 and not H_REG_5_PWR; -- AB2L4
CARRY_OUT <= CARRY_OUT_TRUE or CARRY_OUT_COMP; -- AB2L3
UWRAP_LCH_Reset <= RECYCLE_RST or RESET_WRAP;
UWRAP_LCH: entity work.PHR port map(D=>WRAP_TRUE,L=>CHECK_U_WRAP,R=>UWRAP_LCH_Reset,Q=>U_WRAP_CPU); -- AB2M4
IWRAP_LCH: entity work.PHR port map(D=>WRAP_TRUE,L=>CHECK_I_WRAP,R=>RECYCLE_RST,Q=>sI_WRAPPED_CPU); -- AB2M4
I_WRAPPED_CPU <= sI_WRAPPED_CPU;
UMPX_LCH: entity work.PHR port map(D=>CARRY_OUT,L=>CHECK_MPX_WRAP,R=>RECYCLE_RST,Q=>sU_WRAPPED_MPX); -- AB2M4 ?? Doesn't have reset in FMD - causes Diag failure
U_WRAPPED_MPX <= sU_WRAPPED_MPX;
WBUFF_LCH: entity work.PH port map(D=>sI_WRAPPED_CPU,L=>STORE_WRAP,Q=>WRAP_BUFF); -- AB2M4 ?? *not* sI_WRAPPED_CPU ??
WRAP64 <= (not H_REG_6 and GT_V_TO_N_REG and U_WRAP_CPU) or
(GT_J_TO_N_REG and not H_REG_6 and sI_WRAPPED_CPU) or
(GT_V_TO_N_REG and H_REG_6 and sU_WRAPPED_MPX);
-- Select the appropriate wrap condition based on storage size:
-- sMEM_WRAP <= M012(0) or M012(1) or M012(2); -- 8k
-- sMEM_WRAP <= M012(0) or M012(1); -- 16k
-- sMEM_WRAP <= M012(0); -- 32k
sMEM_WRAP <= WRAP64; -- 64k
MEM_WRAP <= sMEM_WRAP;
MWR_LCH_Set <= MAIN_STORAGE and T2 and (sMEM_WRAP and not ALLOW_WRITE); -- ?? ALLOW_WRITE use unclear - dot logic
MWR_LCH_Reset <= READ_CALL or RECYCLE_RST;
MWR_LCH: entity work.FLL port map(MWR_LCH_Set,MWR_LCH_Reset,sMEM_WRAP_REQ);
MEM_WRAP_REQ <= sMEM_WRAP_REQ;
SEL_DATA_READY <= (DATA_READY_1 or DATA_READY_2) and not sMEM_WRAP_REQ;
END FMD;
| gpl-3.0 | d347b325d2fd95d4ba3bceff2d13b7a1 | 0.645469 | 2.770563 | false | false | false | false |
chastell/art-decomp | spec/fixtures/mark1.vhd | 1 | 3,501 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1 is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1;
architecture behaviour of mark1 is
type state is (state1, state2, state3, state4, state5, state6, state7, state8, state9, state10, state11, state12, state13, state14, state0);
signal current_state, next_state: state;
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= state1; output <= "----------------";
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
else
case current_state is
when state1 =>
if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
end if;
when state2 =>
if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
end if;
when state3 =>
if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
end if;
when state4 =>
if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
end if;
when state5 =>
if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
end if;
when state6 =>
if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
end if;
when state7 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
end if;
when state8 =>
if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
end if;
when state9 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
end if;
when state10 =>
if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
end if;
when state11 =>
if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
end if;
when state12 =>
if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
end if;
when state13 =>
if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
end if;
when state14 =>
if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
end if;
when state0 =>
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
end if;
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 7680a8f4700cb64f7845137d997d98c9 | 0.538418 | 3.456071 | false | false | false | false |
chastell/art-decomp | kiss/s832_rnd.vhd | 1 | 30,735 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_rnd;
architecture behaviour of s832_rnd is
constant s00000: std_logic_vector(4 downto 0) := "11101";
constant s10000: std_logic_vector(4 downto 0) := "00010";
constant s01110: std_logic_vector(4 downto 0) := "11011";
constant s10001: std_logic_vector(4 downto 0) := "11110";
constant s01111: std_logic_vector(4 downto 0) := "11111";
constant s00010: std_logic_vector(4 downto 0) := "10001";
constant s00001: std_logic_vector(4 downto 0) := "10110";
constant s00100: std_logic_vector(4 downto 0) := "01011";
constant s00011: std_logic_vector(4 downto 0) := "01111";
constant s00101: std_logic_vector(4 downto 0) := "00001";
constant s00110: std_logic_vector(4 downto 0) := "10000";
constant s11111: std_logic_vector(4 downto 0) := "11010";
constant s00111: std_logic_vector(4 downto 0) := "11000";
constant s10111: std_logic_vector(4 downto 0) := "01000";
constant s01011: std_logic_vector(4 downto 0) := "00100";
constant s01000: std_logic_vector(4 downto 0) := "01001";
constant s01100: std_logic_vector(4 downto 0) := "00110";
constant s01101: std_logic_vector(4 downto 0) := "11100";
constant s01001: std_logic_vector(4 downto 0) := "00011";
constant s01010: std_logic_vector(4 downto 0) := "10111";
constant s11000: std_logic_vector(4 downto 0) := "10011";
constant s11011: std_logic_vector(4 downto 0) := "10010";
constant s11001: std_logic_vector(4 downto 0) := "00111";
constant s11010: std_logic_vector(4 downto 0) := "01100";
constant s11100: std_logic_vector(4 downto 0) := "10101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0001000000000010000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0001000000000010000";
elsif std_match(input, "-001------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-011------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000010000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000010001";
end if;
when s10000 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000001000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000000001000000000";
end if;
when s01111 =>
if std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000010000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000010000000010000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000010000000010000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000001000000000100";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000001000001000100";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000001000000000100";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000001000001000100";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000001000000000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000001000000000000";
end if;
when s00100 =>
if std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0-0001-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0--101-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0---11-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s00001 =>
if std_match(input, "------0--------0-1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------0--------000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------101") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------111") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10---------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-10--------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10--------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------110--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-110-------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------110-------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------111--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------1110-----010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1110-----110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----101--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0------11--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----1-----1------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----11---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----10---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1-----0------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----0----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----0----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0-----01---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---110") then next_state <= s01011; output <= "0000000100000000000";
end if;
when s11111 =>
if std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s00111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s01011 =>
if std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
end if;
when s01100 =>
if std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0000000010000100000";
elsif std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0000000010000100000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0000000000000101000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0000000000000101000";
end if;
when s01101 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0101000000000000010";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0101000000000000010";
elsif std_match(input, "-0---------------1") then next_state <= s00000; output <= "0100000000000000010";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0100000000000000010";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0100000000000000010";
elsif std_match(input, "-0-1-------------0") then next_state <= s00000; output <= "0100000000000000010";
end if;
when s01000 =>
if std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "0000000100100000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000100100000001";
end if;
when s01001 =>
if std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "1000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
end if;
when s01010 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s11000 =>
if std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
end if;
when s11001 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "1000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000100000000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11010 =>
if std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11011 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-0--------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----111") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1--0-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-0--1-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
end if;
when s11100 =>
if std_match(input, "----0------------1") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00011 =>
if std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000100000000000";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | e9211ffac674c2528f4b35655dbd4bd2 | 0.582723 | 4.181633 | false | false | false | false |
chastell/art-decomp | kiss/dk16_hot.vhd | 1 | 12,878 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_hot;
architecture behaviour of dk16_hot is
constant state_1: std_logic_vector(26 downto 0) := "100000000000000000000000000";
constant state_3: std_logic_vector(26 downto 0) := "010000000000000000000000000";
constant state_2: std_logic_vector(26 downto 0) := "001000000000000000000000000";
constant state_4: std_logic_vector(26 downto 0) := "000100000000000000000000000";
constant state_5: std_logic_vector(26 downto 0) := "000010000000000000000000000";
constant state_6: std_logic_vector(26 downto 0) := "000001000000000000000000000";
constant state_7: std_logic_vector(26 downto 0) := "000000100000000000000000000";
constant state_9: std_logic_vector(26 downto 0) := "000000010000000000000000000";
constant state_8: std_logic_vector(26 downto 0) := "000000001000000000000000000";
constant state_15: std_logic_vector(26 downto 0) := "000000000100000000000000000";
constant state_10: std_logic_vector(26 downto 0) := "000000000010000000000000000";
constant state_14: std_logic_vector(26 downto 0) := "000000000001000000000000000";
constant state_11: std_logic_vector(26 downto 0) := "000000000000100000000000000";
constant state_12: std_logic_vector(26 downto 0) := "000000000000010000000000000";
constant state_20: std_logic_vector(26 downto 0) := "000000000000001000000000000";
constant state_13: std_logic_vector(26 downto 0) := "000000000000000100000000000";
constant state_16: std_logic_vector(26 downto 0) := "000000000000000010000000000";
constant state_17: std_logic_vector(26 downto 0) := "000000000000000001000000000";
constant state_18: std_logic_vector(26 downto 0) := "000000000000000000100000000";
constant state_19: std_logic_vector(26 downto 0) := "000000000000000000010000000";
constant state_21: std_logic_vector(26 downto 0) := "000000000000000000001000000";
constant state_22: std_logic_vector(26 downto 0) := "000000000000000000000100000";
constant state_23: std_logic_vector(26 downto 0) := "000000000000000000000010000";
constant state_24: std_logic_vector(26 downto 0) := "000000000000000000000001000";
constant state_25: std_logic_vector(26 downto 0) := "000000000000000000000000100";
constant state_26: std_logic_vector(26 downto 0) := "000000000000000000000000010";
constant state_27: std_logic_vector(26 downto 0) := "000000000000000000000000001";
signal current_state, next_state: std_logic_vector(26 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------------------------"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "00") then next_state <= state_3; output <= "001";
elsif std_match(input, "01") then next_state <= state_10; output <= "001";
elsif std_match(input, "10") then next_state <= state_11; output <= "001";
elsif std_match(input, "11") then next_state <= state_12; output <= "001";
end if;
when state_2 =>
if std_match(input, "00") then next_state <= state_1; output <= "001";
elsif std_match(input, "01") then next_state <= state_2; output <= "001";
elsif std_match(input, "10") then next_state <= state_8; output <= "001";
elsif std_match(input, "11") then next_state <= state_9; output <= "001";
end if;
when state_3 =>
if std_match(input, "00") then next_state <= state_4; output <= "001";
elsif std_match(input, "01") then next_state <= state_5; output <= "001";
elsif std_match(input, "10") then next_state <= state_6; output <= "001";
elsif std_match(input, "11") then next_state <= state_7; output <= "001";
end if;
when state_4 =>
if std_match(input, "00") then next_state <= state_4; output <= "010";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "010";
elsif std_match(input, "11") then next_state <= state_7; output <= "010";
end if;
when state_5 =>
if std_match(input, "00") then next_state <= state_1; output <= "010";
elsif std_match(input, "01") then next_state <= state_2; output <= "010";
elsif std_match(input, "10") then next_state <= state_16; output <= "010";
elsif std_match(input, "11") then next_state <= state_17; output <= "010";
end if;
when state_6 =>
if std_match(input, "00") then next_state <= state_3; output <= "010";
elsif std_match(input, "01") then next_state <= state_21; output <= "010";
elsif std_match(input, "10") then next_state <= state_10; output <= "010";
elsif std_match(input, "11") then next_state <= state_22; output <= "010";
end if;
when state_7 =>
if std_match(input, "00") then next_state <= state_9; output <= "010";
elsif std_match(input, "01") then next_state <= state_18; output <= "010";
elsif std_match(input, "10") then next_state <= state_19; output <= "010";
elsif std_match(input, "11") then next_state <= state_20; output <= "010";
end if;
when state_8 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_26; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_9 =>
if std_match(input, "00") then next_state <= state_1; output <= "000";
elsif std_match(input, "01") then next_state <= state_5; output <= "000";
elsif std_match(input, "10") then next_state <= state_6; output <= "000";
elsif std_match(input, "11") then next_state <= state_7; output <= "000";
end if;
when state_10 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_1; output <= "000";
elsif std_match(input, "11") then next_state <= state_2; output <= "000";
end if;
when state_11 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_24; output <= "000";
elsif std_match(input, "11") then next_state <= state_25; output <= "000";
end if;
when state_12 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_13 =>
if std_match(input, "00") then next_state <= state_3; output <= "101";
elsif std_match(input, "01") then next_state <= state_10; output <= "101";
elsif std_match(input, "10") then next_state <= state_11; output <= "101";
elsif std_match(input, "11") then next_state <= state_12; output <= "101";
end if;
when state_14 =>
if std_match(input, "00") then next_state <= state_1; output <= "101";
elsif std_match(input, "01") then next_state <= state_2; output <= "101";
elsif std_match(input, "10") then next_state <= state_8; output <= "101";
elsif std_match(input, "11") then next_state <= state_9; output <= "101";
end if;
when state_15 =>
if std_match(input, "00") then next_state <= state_4; output <= "101";
elsif std_match(input, "01") then next_state <= state_5; output <= "101";
elsif std_match(input, "10") then next_state <= state_6; output <= "101";
elsif std_match(input, "11") then next_state <= state_7; output <= "101";
end if;
when state_16 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_17 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_27; output <= "000";
end if;
when state_18 =>
if std_match(input, "00") then next_state <= state_4; output <= "100";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "100";
elsif std_match(input, "11") then next_state <= state_7; output <= "100";
end if;
when state_19 =>
if std_match(input, "00") then next_state <= state_18; output <= "100";
elsif std_match(input, "01") then next_state <= state_23; output <= "010";
elsif std_match(input, "10") then next_state <= state_24; output <= "100";
elsif std_match(input, "11") then next_state <= state_25; output <= "100";
end if;
when state_20 =>
if std_match(input, "00") then next_state <= state_19; output <= "100";
elsif std_match(input, "01") then next_state <= state_20; output <= "010";
elsif std_match(input, "10") then next_state <= state_9; output <= "100";
elsif std_match(input, "11") then next_state <= state_26; output <= "100";
end if;
when state_21 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_22 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "100";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_23 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_24 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_25 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_26 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_21; output <= "000";
end if;
when state_27 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when others => next_state <= "---------------------------"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | b9685057ad43a62f484358a86657c259 | 0.603199 | 3.449772 | false | false | false | false |
thommyj/slotcar | de0/sc_fpga.vhd | 1 | 14,797 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity sc_fpga is
port(
CLOCK_50 : in std_logic;
LED_GREEN : out std_logic_vector(7 downto 0);
KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(3 downto 0);
RPI : in std_logic_vector(3 downto 0);
SS_async : in std_logic;
SCLK_async : in std_logic;
MOSI_async : in std_logic;
MISO_async : out std_logic;
SS_out : out std_logic;
SCLK_out : buffer std_logic;
MOSI_out : out std_logic;
MISO_out : out std_logic;
UART0_out : out std_logic;
UART0_in : in std_logic;
UART0_rts : out std_logic;
UART1_out : out std_logic;
UART1_in : in std_logic;
UART1_rts : out std_logic
);
end entity sc_fpga;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of sc_fpga is
type uartstate_type is (IDLE0,UART0TX,UART1RX,IDLE1,UART1TX,UART0RX);
signal uartstate : uartstate_type;
--
-- Define all components which are included here
--
component pll
port (
inclk0 : in std_logic := '0';
c0 : out std_logic ;
locked : out std_logic
);
end component pll;
component spi
port(
clk : in std_logic;
rst : in std_logic;
SS_async : in std_logic;
SCLK_async : in std_logic;
MOSI_async : in std_logic;
MISO_async : out std_logic;
data_out : buffer std_logic_vector(7 downto 0); --from rpi
data_in : in std_logic_vector(7 downto 0); --to rpi
data_out_valid : buffer std_logic
);
end component;
component spi_decoder
port(
clk : in std_logic;
rst : in std_logic;
spidata_out : out std_logic_vector(7 downto 0); --to rpi
spidata_in : in std_logic_vector(7 downto 0); --from rpi
spidata_valid_in : in std_logic;
leds : out std_logic_vector(7 downto 0);
pll_locked : in std_logic;
version : in std_logic_vector(7 downto 0);
extreg_dataout : out std_logic_vector(7 downto 0);
extreg_addressout : out std_logic_vector(7 downto 0);
extreg_read_req : out std_logic;
extreg_enable : out std_logic;
extreg_datain : in std_logic_vector(7 downto 0);
extreg_data_valid : in std_logic;
extreg_addressin : out std_logic_vector(7 downto 0)
);
end component;
component registerfile is
port(
clk : in std_logic;
rst : in std_logic;
writer_data : in std_logic_vector(7 downto 0);
writer_address : in std_logic_vector(7 downto 0);
writer_enable : in std_logic;
writer2_data : in std_logic_vector(7 downto 0);
writer2_address: in std_logic_vector(7 downto 0);
writer2_enable : in std_logic;
reader_data : out std_logic_vector(7 downto 0);
reader_data_valid : out std_logic;
reader_read_req : in std_logic;
reader_address : in std_logic_vector(7 downto 0);
reader2_data : out std_logic_vector(7 downto 0);
reader2_data_valid : out std_logic;
reader2_read_req : in std_logic;
reader2_address : in std_logic_vector(7 downto 0)
);
end component;
component uart_halfduplex is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : out std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
rts : out std_logic
);
end component;
component uart_controller
port (
clk : in std_logic;
rst : in std_logic;
rts_screen : out std_logic;
datarec_screen : in std_logic;
data_from_screen : in std_logic_vector(7 downto 0);
data_to_screen : out std_logic_vector(7 downto 0);
write_address : out std_logic_vector(7 downto 0);
write_data : out std_logic_vector(7 downto 0);
write_en : out std_logic;
read_req : out std_logic;
read_address : out std_logic_vector(7 downto 0);
read_data : in std_logic_vector(7 downto 0);
read_data_valid : in std_logic;
rts_track : out std_logic;
datarec_track : in std_logic;
data_from_track : in std_logic_vector(7 downto 0);
data_to_track : out std_logic_vector(7 downto 0)
);
end component uart_controller;
signal clk : std_logic;
signal rst : std_logic;
signal rst_cnt : std_logic_vector(15 downto 0):= "0000000000000000";
signal pll_locked : std_logic;
signal spidata_from_master : std_logic_vector(7 downto 0);
signal spidata_to_master : std_logic_vector(7 downto 0);
signal spidata_valid_from_master : std_logic;
constant VERSION : std_logic_vector(7 downto 0):= "00001001";
signal uart_controller_to_rf_write_data : std_logic_vector(7 downto 0);
signal uart_controller_to_rf_write_address : std_logic_vector(7 downto 0);
signal uart_controller_to_rf_write_valid : std_logic;
signal uart_controller_to_rf_read_req : std_logic;
signal rf_to_uart_controller_read_address : std_logic_vector(7 downto 0);
signal rf_to_uart_controller_read_data : std_logic_vector(7 downto 0);
signal rf_to_uart_controller_data_valid : std_logic;
signal spi_decoder_to_rf_data_valid : std_logic;
signal spi_decoder_to_rf_data : std_logic_vector(7 downto 0);
signal rf_to_spi_decoder_read_req : std_logic;
signal spi_decoder_to_rf_address : std_logic_vector(7 downto 0);
signal rs485data_to_spi : std_logic_vector(7 downto 0);
signal rf_to_spi_decoder_data_valid : std_logic;
signal rs485address_to_spi : std_logic_vector(7 downto 0);
--UART
signal UART0_parallell_data_out : std_logic_vector(7 downto 0);
signal UART0_parallell_data_out_valid : std_logic;
signal UART0_parallell_data_in : std_logic_vector(7 downto 0);
signal UART0_parallell_data_in_valid : std_logic;
signal UART0_parallell_data_in_sent : std_logic;
signal UART1_parallell_data_out : std_logic_vector(7 downto 0);
signal UART1_parallell_data_out_valid : std_logic;
signal UART1_parallell_data_in : std_logic_vector(7 downto 0);
signal UART1_parallell_data_in_valid : std_logic;
signal UART1_parallell_data_in_sent : std_logic;
signal UART_payload : std_logic_vector(7 downto 0);
begin
inst_pll : pll
port map (
inclk0 => CLOCK_50,
c0 => clk,
locked => pll_locked
);
inst_spi : spi
port map (
clk => clk,
rst => rst,
SS_async => SS_async,
SCLK_async => SCLK_async,
MOSI_async => MOSI_async,
MISO_async => MISO_async,
data_out => spidata_from_master,
data_in => spidata_to_master,
data_out_valid => spidata_valid_from_master
);
inst_spi_decoder : spi_decoder
port map (
clk => clk,
rst => rst,
spidata_out => spidata_to_master,
spidata_in => spidata_from_master,
spidata_valid_in => spidata_valid_from_master,
pll_locked => pll_locked,
version => VERSION,
leds => LED_GREEN,
extreg_dataout => spi_decoder_to_rf_data, --should later come from rs485 block
extreg_addressout => spi_decoder_to_rf_address, --should later come from rs485 block
extreg_read_req => rf_to_spi_decoder_read_req,
extreg_enable => spi_decoder_to_rf_data_valid,
extreg_datain => rs485data_to_spi,
extreg_data_valid => rf_to_spi_decoder_data_valid,
extreg_addressin => rs485address_to_spi
);
inst_registerfile : registerfile
port map(
clk => clk,
rst => rst,
writer_data => spi_decoder_to_rf_data,
writer_address => spi_decoder_to_rf_address,
writer_enable => spi_decoder_to_rf_data_valid,
writer2_data => uart_controller_to_rf_write_data,
writer2_address => uart_controller_to_rf_write_address,
writer2_enable => uart_controller_to_rf_write_valid,
reader_read_req => rf_to_spi_decoder_read_req,
reader_data => rs485data_to_spi,
reader_data_valid => rf_to_spi_decoder_data_valid,
reader_address => rs485address_to_spi,
reader2_read_req => uart_controller_to_rf_read_req,
reader2_data => rf_to_uart_controller_read_data,
reader2_data_valid => rf_to_uart_controller_data_valid,
reader2_address => rf_to_uart_controller_read_address
);
inst_UART0 : uart_halfduplex
port map(
clk => clk,
rst => rst,
parallell_data_out => UART0_parallell_data_out,
parallell_data_out_valid => UART0_parallell_data_out_valid,
uart_data_in => UART0_in,
parallell_data_in => UART0_parallell_data_in,
parallell_data_in_valid => UART0_parallell_data_in_valid,
parallell_data_in_sent => UART0_parallell_data_in_sent,
uart_data_out => UART0_out,
rts => UART0_rts
);
inst_UART1 : uart_halfduplex
port map(
clk => clk,
rst => rst,
parallell_data_out => UART1_parallell_data_out,
parallell_data_out_valid => UART1_parallell_data_out_valid,
uart_data_in => UART1_in,
parallell_data_in => UART1_parallell_data_in,
parallell_data_in_valid => UART1_parallell_data_in_valid,
parallell_data_in_sent => UART1_parallell_data_in_sent,
uart_data_out => UART1_out,
rts => UART1_rts
);
inst_UART_CONTROLLER : uart_controller
port map(
clk => clk,
rst => rst,
rts_screen => UART1_parallell_data_in_valid,
datarec_screen => UART1_parallell_data_out_valid,
data_from_screen => UART1_parallell_data_out,
data_to_screen => UART1_parallell_data_in,
write_address => uart_controller_to_rf_write_address,
write_data => uart_controller_to_rf_write_data,
write_en => uart_controller_to_rf_write_valid,
read_req => uart_controller_to_rf_read_req,
read_address => rf_to_uart_controller_read_address,
read_data => rf_to_uart_controller_read_data,
read_data_valid => rf_to_uart_controller_data_valid,
rts_track => UART0_parallell_data_in_valid,
datarec_track => UART0_parallell_data_out_valid,
data_from_track => UART0_parallell_data_out,
data_to_track => UART0_parallell_data_in
);
--async trigg of reset, sync release
process(clk,pll_locked)
begin
if(pll_locked = '0') then
rst <= '1';
elsif(clk'event and clk = '1') then
if(rst_cnt = x"FFFF") then
rst <= '0';
else
rst_cnt <= rst_cnt + 1;
end if;
end if;
end process;
--UART1_parallell_data_in <= UART0_parallell_data_out;
--UART0_parallell_data_in <= UART1_parallell_data_out;
--SS_out <= '0';
--SCLK_out <= '0';
MOSI_out <= '0';
MISO_out <= '0';
-- LED_GREEN <= uart_controller_to_rf_write_address;
-- LED_GREEN <= UART1_parallell_data_in;
-- LED_GREEN <= UART0_parallell_data_out;
end architecture syn;
-- *** EOF ***
| mit | 618ae45a49a00dbf0e3ab90b852735b3 | 0.555586 | 3.486569 | false | false | false | false |
chastell/art-decomp | kiss/donfile_hot.vhd | 1 | 10,682 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity donfile_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end donfile_hot;
architecture behaviour of donfile_hot is
constant st0: std_logic_vector(23 downto 0) := "100000000000000000000000";
constant st6: std_logic_vector(23 downto 0) := "010000000000000000000000";
constant st12: std_logic_vector(23 downto 0) := "001000000000000000000000";
constant st18: std_logic_vector(23 downto 0) := "000100000000000000000000";
constant st1: std_logic_vector(23 downto 0) := "000010000000000000000000";
constant st7: std_logic_vector(23 downto 0) := "000001000000000000000000";
constant st2: std_logic_vector(23 downto 0) := "000000100000000000000000";
constant st19: std_logic_vector(23 downto 0) := "000000010000000000000000";
constant st3: std_logic_vector(23 downto 0) := "000000001000000000000000";
constant st13: std_logic_vector(23 downto 0) := "000000000100000000000000";
constant st4: std_logic_vector(23 downto 0) := "000000000010000000000000";
constant st5: std_logic_vector(23 downto 0) := "000000000001000000000000";
constant st14: std_logic_vector(23 downto 0) := "000000000000100000000000";
constant st20: std_logic_vector(23 downto 0) := "000000000000010000000000";
constant st8: std_logic_vector(23 downto 0) := "000000000000001000000000";
constant st21: std_logic_vector(23 downto 0) := "000000000000000100000000";
constant st9: std_logic_vector(23 downto 0) := "000000000000000010000000";
constant st15: std_logic_vector(23 downto 0) := "000000000000000001000000";
constant st10: std_logic_vector(23 downto 0) := "000000000000000000100000";
constant st11: std_logic_vector(23 downto 0) := "000000000000000000010000";
constant st22: std_logic_vector(23 downto 0) := "000000000000000000001000";
constant st23: std_logic_vector(23 downto 0) := "000000000000000000000100";
constant st16: std_logic_vector(23 downto 0) := "000000000000000000000010";
constant st17: std_logic_vector(23 downto 0) := "000000000000000000000001";
signal current_state, next_state: std_logic_vector(23 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st6 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st8 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st9 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st10 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st11 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st12 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st13 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st14 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st15 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st16 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st17 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st18 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st19 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st20 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st21 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st22 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st23 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when others => next_state <= "------------------------"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 06078b383dcb4476bf4445c361b917ec | 0.586313 | 3.348589 | false | false | false | false |
chastell/art-decomp | kiss/dk14_hot.vhd | 1 | 6,120 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_hot is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_hot;
architecture behaviour of dk14_hot is
constant state_1: std_logic_vector(6 downto 0) := "1000000";
constant state_3: std_logic_vector(6 downto 0) := "0100000";
constant state_2: std_logic_vector(6 downto 0) := "0010000";
constant state_4: std_logic_vector(6 downto 0) := "0001000";
constant state_5: std_logic_vector(6 downto 0) := "0000100";
constant state_6: std_logic_vector(6 downto 0) := "0000010";
constant state_7: std_logic_vector(6 downto 0) := "0000001";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "-----";
case current_state is
when state_1 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_2 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_1; output <= "00001";
elsif std_match(input, "010") then next_state <= state_2; output <= "00001";
end if;
when state_3 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_4 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "10100";
elsif std_match(input, "010") then next_state <= state_7; output <= "10000";
end if;
when state_5 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_6 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10100";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_7 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when others => next_state <= "-------"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 1522c90e37986867df6696bc1d0e764d | 0.600327 | 3.388704 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-07B2.vhd | 1 | 6,009 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B2.vhd
-- Creation Date: 01/11/09
-- Description:
-- S Register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change GT_CS_OPT to level-triggered latch
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
-- use work.all;
ENTITY SReg IS
port
(
SA : IN STD_LOGIC; -- 01C
CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
GT_CARRY_TO_S3 : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(0 to 7);
GT_Z_BUS_TO_S : OUT STD_LOGIC;
S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC; -- 01C
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
STORE_S_REG_RST : IN STD_LOGIC; -- 03D
E_SW_SEL_S : IN STD_LOGIC; -- 04C
MACH_RST_2C : IN STD_LOGIC; -- 06B
T_REQUEST : IN STD_LOGIC; -- 10BC6
FB_K_T2_PULSE : OUT STD_LOGIC;
CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
BASIC_CS_0 : OUT STD_LOGIC; -- 03C
P1, T1, T2, T3, T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END SReg;
ARCHITECTURE FMD OF SReg IS
signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
signal CD_0110 : STD_LOGIC;
signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
signal sGT_Z_BUS_TO_S : STD_LOGIC;
signal sS_REG_RST : STD_LOGIC;
signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-07B
CS_X000 <= '1' when CS(1 to 3)="000" else '0';
CS_X001 <= '1' when CS(1 to 3)="001" else '0';
CS_DECODE_X001 <= CS_X001;
CS_X010 <= '1' when CS(1 to 3)="010" else '0';
CS_X011 <= '1' when CS(1 to 3)="011" else '0';
CS_X100 <= '1' when CS(1 to 3)="100" else '0';
CS_X101 <= '1' when CS(1 to 3)="101" else '0';
CS_X110 <= '1' when CS(1 to 3)="110" else '0';
CS_X111 <= '1' when CS(1 to 3)="111" else '0';
CS_X01X <= '1' when CS(1 to 2)="01" else '0';
CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
-- GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_OPT: entity work.FLL port map(S=>GT_CS_OPT_Set, R=>GT_CS_OPT_Reset, Q=>GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
BASIC_CS_0 <= sBASIC_CS_0;
FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
S_REG_RST <= sS_REG_RST;
SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS); -- ?? "T4 and not T1" to prevent erroneous S4 value
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;
| gpl-3.0 | 03c46011a14c988cfbb6fb9a1e847ce7 | 0.616076 | 2.457669 | false | false | false | false |
chastell/art-decomp | spec/fixtures/mark1_hot.vhd | 2 | 4,559 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_hot;
architecture behaviour of mark1_hot is
constant state1: std_logic_vector(14 downto 0) := "100000000000000";
constant state3: std_logic_vector(14 downto 0) := "010000000000000";
constant state2: std_logic_vector(14 downto 0) := "001000000000000";
constant state0: std_logic_vector(14 downto 0) := "000100000000000";
constant state4: std_logic_vector(14 downto 0) := "000010000000000";
constant state13: std_logic_vector(14 downto 0) := "000001000000000";
constant state10: std_logic_vector(14 downto 0) := "000000100000000";
constant state9: std_logic_vector(14 downto 0) := "000000010000000";
constant state8: std_logic_vector(14 downto 0) := "000000001000000";
constant state7: std_logic_vector(14 downto 0) := "000000000100000";
constant state6: std_logic_vector(14 downto 0) := "000000000010000";
constant state5: std_logic_vector(14 downto 0) := "000000000001000";
constant state14: std_logic_vector(14 downto 0) := "000000000000100";
constant state11: std_logic_vector(14 downto 0) := "000000000000010";
constant state12: std_logic_vector(14 downto 0) := "000000000000001";
signal current_state, next_state: std_logic_vector(14 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------------"; output <= "----------------";
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
else
case current_state is
when state1 =>
if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
end if;
when state2 =>
if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
end if;
when state3 =>
if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
end if;
when state4 =>
if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
end if;
when state5 =>
if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
end if;
when state6 =>
if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
end if;
when state7 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
end if;
when state8 =>
if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
end if;
when state9 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
end if;
when state10 =>
if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
end if;
when state11 =>
if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
end if;
when state12 =>
if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
end if;
when state13 =>
if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
end if;
when state14 =>
if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
end if;
when state0 =>
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
end if;
when others => next_state <= "---------------"; output <= "----------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 0b117261411ede89c4fde0313f74c09f | 0.572494 | 3.578493 | false | false | false | false |
chastell/art-decomp | kiss/dk512_nov.vhd | 1 | 4,539 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_nov;
architecture behaviour of dk512_nov is
constant state_1: std_logic_vector(3 downto 0) := "0001";
constant state_2: std_logic_vector(3 downto 0) := "1101";
constant state_3: std_logic_vector(3 downto 0) := "0011";
constant state_4: std_logic_vector(3 downto 0) := "0000";
constant state_5: std_logic_vector(3 downto 0) := "0101";
constant state_6: std_logic_vector(3 downto 0) := "0100";
constant state_7: std_logic_vector(3 downto 0) := "1100";
constant state_8: std_logic_vector(3 downto 0) := "0010";
constant state_9: std_logic_vector(3 downto 0) := "1000";
constant state_10: std_logic_vector(3 downto 0) := "0110";
constant state_11: std_logic_vector(3 downto 0) := "1110";
constant state_12: std_logic_vector(3 downto 0) := "1001";
constant state_13: std_logic_vector(3 downto 0) := "1011";
constant state_14: std_logic_vector(3 downto 0) := "1010";
constant state_15: std_logic_vector(3 downto 0) := "1111";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 01fd6fc3f6cadf38c49aac75b774eec7 | 0.582287 | 3.251433 | false | false | false | false |
chastell/art-decomp | kiss/tbk_hot.vhd | 1 | 133,997 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_hot is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_hot;
architecture behaviour of tbk_hot is
constant st0: std_logic_vector(31 downto 0) := "10000000000000000000000000000000";
constant st16: std_logic_vector(31 downto 0) := "01000000000000000000000000000000";
constant st1: std_logic_vector(31 downto 0) := "00100000000000000000000000000000";
constant st2: std_logic_vector(31 downto 0) := "00010000000000000000000000000000";
constant st3: std_logic_vector(31 downto 0) := "00001000000000000000000000000000";
constant st4: std_logic_vector(31 downto 0) := "00000100000000000000000000000000";
constant st5: std_logic_vector(31 downto 0) := "00000010000000000000000000000000";
constant st6: std_logic_vector(31 downto 0) := "00000001000000000000000000000000";
constant st7: std_logic_vector(31 downto 0) := "00000000100000000000000000000000";
constant st8: std_logic_vector(31 downto 0) := "00000000010000000000000000000000";
constant st9: std_logic_vector(31 downto 0) := "00000000001000000000000000000000";
constant st10: std_logic_vector(31 downto 0) := "00000000000100000000000000000000";
constant st11: std_logic_vector(31 downto 0) := "00000000000010000000000000000000";
constant st12: std_logic_vector(31 downto 0) := "00000000000001000000000000000000";
constant st13: std_logic_vector(31 downto 0) := "00000000000000100000000000000000";
constant st15: std_logic_vector(31 downto 0) := "00000000000000010000000000000000";
constant st14: std_logic_vector(31 downto 0) := "00000000000000001000000000000000";
constant st29: std_logic_vector(31 downto 0) := "00000000000000000100000000000000";
constant st31: std_logic_vector(31 downto 0) := "00000000000000000010000000000000";
constant st30: std_logic_vector(31 downto 0) := "00000000000000000001000000000000";
constant st17: std_logic_vector(31 downto 0) := "00000000000000000000100000000000";
constant st18: std_logic_vector(31 downto 0) := "00000000000000000000010000000000";
constant st19: std_logic_vector(31 downto 0) := "00000000000000000000001000000000";
constant st20: std_logic_vector(31 downto 0) := "00000000000000000000000100000000";
constant st21: std_logic_vector(31 downto 0) := "00000000000000000000000010000000";
constant st22: std_logic_vector(31 downto 0) := "00000000000000000000000001000000";
constant st23: std_logic_vector(31 downto 0) := "00000000000000000000000000100000";
constant st24: std_logic_vector(31 downto 0) := "00000000000000000000000000010000";
constant st25: std_logic_vector(31 downto 0) := "00000000000000000000000000001000";
constant st26: std_logic_vector(31 downto 0) := "00000000000000000000000000000100";
constant st27: std_logic_vector(31 downto 0) := "00000000000000000000000000000010";
constant st28: std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(31 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------------------"; output <= "---";
case current_state is
when st0 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st16 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st1 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st1; output <= "000";
elsif std_match(input, "000010") then next_state <= st1; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "010";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st17 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st17; output <= "000";
elsif std_match(input, "000010") then next_state <= st17; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "010";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st2 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st2; output <= "000";
elsif std_match(input, "000010") then next_state <= st2; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "010";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st18 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st18; output <= "000";
elsif std_match(input, "000010") then next_state <= st18; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "010";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st3 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st3; output <= "000";
elsif std_match(input, "000010") then next_state <= st3; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "010";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st19 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st19; output <= "000";
elsif std_match(input, "000010") then next_state <= st19; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "010";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st4 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st4; output <= "000";
elsif std_match(input, "000010") then next_state <= st4; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "010";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st20 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st20; output <= "000";
elsif std_match(input, "000010") then next_state <= st20; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "010";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st5 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st5; output <= "000";
elsif std_match(input, "000010") then next_state <= st5; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "010";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st21 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st21; output <= "000";
elsif std_match(input, "000010") then next_state <= st21; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "010";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st6 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st6; output <= "000";
elsif std_match(input, "000010") then next_state <= st6; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "010";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st22 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st22; output <= "000";
elsif std_match(input, "000010") then next_state <= st22; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "010";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st7 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st7; output <= "000";
elsif std_match(input, "000010") then next_state <= st7; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "010";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st23 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st23; output <= "000";
elsif std_match(input, "000010") then next_state <= st23; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "010";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st8 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st8; output <= "000";
elsif std_match(input, "000010") then next_state <= st8; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "010";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st24 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st24; output <= "000";
elsif std_match(input, "000010") then next_state <= st24; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "010";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st9 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st9; output <= "000";
elsif std_match(input, "000000") then next_state <= st9; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "010";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st25 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st25; output <= "000";
elsif std_match(input, "000000") then next_state <= st25; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "010";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st10 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st10; output <= "000";
elsif std_match(input, "000000") then next_state <= st10; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "010";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st26 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st26; output <= "000";
elsif std_match(input, "000000") then next_state <= st26; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "010";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st11 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st11; output <= "000";
elsif std_match(input, "000000") then next_state <= st11; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "010";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st27 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st27; output <= "000";
elsif std_match(input, "000000") then next_state <= st27; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "010";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st12 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st12; output <= "000";
elsif std_match(input, "000000") then next_state <= st12; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st28 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st28; output <= "000";
elsif std_match(input, "000000") then next_state <= st28; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st13 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st13; output <= "100";
elsif std_match(input, "000010") then next_state <= st13; output <= "100";
elsif std_match(input, "000000") then next_state <= st13; output <= "100";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st29 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st29; output <= "100";
elsif std_match(input, "000010") then next_state <= st29; output <= "100";
elsif std_match(input, "000000") then next_state <= st29; output <= "100";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st15 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st15; output <= "000";
elsif std_match(input, "000010") then next_state <= st15; output <= "000";
elsif std_match(input, "000000") then next_state <= st15; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st31 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st31; output <= "000";
elsif std_match(input, "000010") then next_state <= st31; output <= "000";
elsif std_match(input, "000000") then next_state <= st31; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st14 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st14; output <= "000";
elsif std_match(input, "000010") then next_state <= st14; output <= "000";
elsif std_match(input, "000000") then next_state <= st14; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st30 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st30; output <= "000";
elsif std_match(input, "000010") then next_state <= st30; output <= "000";
elsif std_match(input, "000000") then next_state <= st30; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when others => next_state <= "--------------------------------"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 6fb14b158970d3185d475ce1dca0c2c0 | 0.593312 | 3.360595 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_clk_100_hz.vhd | 1 | 1,883 | -------------------------------------------------------------------------------
-- Title : Testbench for design "prescaler"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_prescaler.vhd
-- Author : Martin Angermair
-- Company :
-- Created : 29.10.2017
-- Last update: 29.10.2017
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 29.10.2017 1.0 Martin Angermair init
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_clk_100_hz is
end tb_clk_100_hz;
architecture sim of tb_clk_100_hz is
component clk_100_hz
port (clk_i : IN std_logic;
reset_i : IN std_logic;
clk_100_hz_o : OUT std_logic);
end component clk_100_hz;
-- System clock 100MHz
constant system_clk : time := 10 ns;
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal clk_100_hz_o : std_logic;
begin
-- Instantiate the design under test
i_clk_100_hz : clk_100_hz
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_100_hz_o => clk_100_hz_o);
-- Generate clock
p_clk : process
begin
clk_i <= '0';
wait for system_clk / 2;
clk_i <= '1';
wait for system_clk / 2;
end process p_clk;
p_stimuli : process
begin
reset_i <= '1';
wait for 10 ns;
reset_i <= '0';
wait;
end process p_stimuli;
end sim; | mit | 8ed4e578d37e83bf04be68bb9bd3b6da | 0.412108 | 4.184444 | false | false | false | false |
digital-sound-antiques/vm2413 | SineTable.vhd | 2 | 3,133 | --
-- SineTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This entity represents a sine wave table which allow to choose one of
-- the normal sine or half sine wave. The table only contains quarter of
-- full wave to reduce hardware resources.
--
entity SineTable is
port (
clk : in std_logic;
wf : in std_logic;
addr : in integer range 0 to 2 ** (PGOUT_TYPE'high+1) - 1;
data : out SIGNED_DB_TYPE
);
end SineTable;
architecture RTL of SineTable is
constant TABLE_WIDTH : integer := (addr'high-addr'low+1)/4;
type sin_type is array (0 to TABLE_WIDTH-1) of DB_TYPE;
constant sin_data : sin_type := (
"1111111","1100101","1010101","1001100",
"1000101","1000000","0111100","0111000",
"0110101","0110011","0110000","0101110",
"0101100","0101010","0101000","0100111",
"0100101","0100100","0100011","0100001",
"0100000","0011111","0011110","0011101",
"0011100","0011011","0011010","0011010",
"0011001","0011000","0010111","0010110",
"0010110","0010101","0010100","0010100",
"0010011","0010011","0010010","0010001",
"0010001","0010000","0010000","0001111",
"0001111","0001110","0001110","0001110",
"0001101","0001101","0001100","0001100",
"0001011","0001011","0001011","0001010",
"0001010","0001010","0001001","0001001",
"0001001","0001000","0001000","0001000",
"0001000","0000111","0000111","0000111",
"0000110","0000110","0000110","0000110",
"0000101","0000101","0000101","0000101",
"0000101","0000100","0000100","0000100",
"0000100","0000100","0000011","0000011",
"0000011","0000011","0000011","0000011",
"0000010","0000010","0000010","0000010",
"0000010","0000010","0000010","0000001",
"0000001","0000001","0000001","0000001",
"0000001","0000001","0000001","0000001",
"0000001","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
if addr < TABLE_WIDTH then
data <= ( sign=>'0', value=>sin_data(addr) );
elsif addr < TABLE_WIDTH * 2 then
data <= ( sign=>'0', value=>sin_data(TABLE_WIDTH * 2 - 1 - addr) );
elsif addr < TABLE_WIDTH * 3 then
if wf = '0' then
data <= ( sign=>'1', value=>sin_data(addr - TABLE_WIDTH * 2));
else
data <= ( sign=>'1', value=>sin_data(0) );
end if ;
else
if wf = '0' then
data <= ( sign=>'1', value=>sin_data( TABLE_WIDTH * 4 - 1 - addr));
else
data <= ( sign=>'1', value=>sin_data(0) );
end if;
end if;
end if;
end process;
end RTL; | mit | defd4db24ecb1c75e9dfc0077af79ba8 | 0.551867 | 4.021823 | false | false | false | false |
TheMassController/VHDL_experimenting | project/sevenSegment/test/seven_seg_controller_tb.vhd | 1 | 12,957 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
use src.seven_seg_pkg.all;
library tb;
use tb.bus_tb_pkg.all;
entity seven_seg_controller_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of seven_seg_controller_tb is
constant clk_period : time := 20 ns;
constant ss1_ticks : natural := 1;
constant ss1_digit_count : natural := 1;
constant ss2_ticks : natural := 10;
constant ss2_digit_count : natural := 4;
constant all_one_digit : digit_info_type := (others => '1');
constant digit_others_zeros : std_logic_vector(bus_data_type'high - digit_info_type'high - 1 downto 0) := (others => '0');
signal mst2ss1 : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss1_2mst : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal mst2ss2 : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal ss2_2mst : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ss1_digit_anodes : std_logic_vector(ss1_digit_count - 1 downto 0);
signal ss1_kathode : seven_seg_kath_type;
signal ss2_digit_anodes : std_logic_vector(ss2_digit_count - 1 downto 0);
signal ss2_kathode : seven_seg_kath_type;
begin
clk <= not clk after (clk_period/2);
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Address out of range") then
wait until falling_edge(clk);
mst2ss1 <= bus_tb_mst2slv(address => 10, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '1');
check(ss1_2mst.ack = '1');
mst2ss1 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= bus_tb_mst2slv(address => 1, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '1');
check(ss1_2mst.ack = '1');
end if;
if run("Memory check") then
wait until falling_edge(clk);
mst2ss1 <= bus_tb_mst2slv(address => 0, writeData => 255, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
mst2ss1 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
check(to_integer(unsigned(ss1_2mst.readData)) = 255);
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
mst2ss1 <= bus_tb_mst2slv(address => 0, writeData => 0, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
mst2ss1 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
check(to_integer(unsigned(ss1_2mst.readData)) = 0);
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '0');
end if;
if run("Single output check") then
wait until rising_edge(clk);
wait until falling_edge(clk);
-- Default register content should be all zeros.
check(ss1_digit_anodes(0) = '0');
check(ss1_kathode = "11000000");
-- Only enable the dot
mst2ss1 <= bus_tb_mst2slv(address => 0, writeData => 16#10#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss1_2mst.fault = '0');
check(ss1_2mst.ack = '1');
mst2ss1 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss1_digit_anodes(0) = '0');
check(ss1_kathode = "01000000");
end if;
if run("Multiple output check") then
wait until falling_edge(clk);
-- First, enter all values
-- Digit 1: 1, with dot
mst2ss2 <= bus_tb_mst2slv(address => 0, writeData => 16#11#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Digit 2: 8, no dot
mst2ss2 <= bus_tb_mst2slv(address => 1, writeData => 16#08#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Digit 3: a, with dot
mst2ss2 <= bus_tb_mst2slv(address => 2, writeData => 16#1a#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Digit 4: f, no dot
mst2ss2 <= bus_tb_mst2slv(address => 3, writeData => 16#0f#, writeEnable => '1', writeMask => 1);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
-- Check the actual outputs. We expect digit 1 to be active right now
check(ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
-- Wait the timeout for the next digit to activate..
wait for ss2_ticks * clk_period;
-- We expect digit 2 to be active right now.
check(ss2_digit_anodes = "1101");
check(ss2_kathode = "10000000");
wait for ss2_ticks * clk_period;
-- We expect digit 3 to be active right now.
check(ss2_digit_anodes = "1011");
check(ss2_kathode = "00001000");
wait for ss2_ticks * clk_period;
-- We expect digit 4 to be active right now.
check(ss2_digit_anodes = "0111");
check(ss2_kathode = "10001110");
end if;
if run("Multiple byte write") then
wait until falling_edge(clk);
mst2ss2 <= bus_tb_mst2slv(address => 0, writeData => 16#14131211#, writeEnable => '1', writeMask => 15);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
-- Check the actual outputs. We expect digit 1 to be active right now
check(ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
-- Wait the timeout for the next digit to activate..
wait for ss2_ticks * clk_period;
-- We expect digit 2 to be active right now.
check(ss2_digit_anodes = "1101");
check(ss2_kathode = "00100100");
wait for ss2_ticks * clk_period;
-- We expect digit 3 to be active right now.
check(ss2_digit_anodes = "1011");
check(ss2_kathode = "00110000");
wait for ss2_ticks * clk_period;
-- We expect digit 4 to be active right now.
check(ss2_digit_anodes = "0111");
check(ss2_kathode = "00011001");
mst2ss2 <= bus_tb_mst2slv(address => 1, writeData => 16#14131211#, writeEnable => '1', writeMask => 15);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
wait until (ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1101");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1011");
check(ss2_kathode = "00100100");
wait until (ss2_digit_anodes = "0111");
check(ss2_kathode = "00110000");
wait until falling_edge(clk);
mst2ss2 <= bus_tb_mst2slv(address => 2, writeData => 16#18181818#, writeEnable => '1', writeMask => 16#9#);
wait until (ss2_digit_anodes = "1110");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1101");
check(ss2_kathode = "01111001");
wait until (ss2_digit_anodes = "1011");
check(ss2_kathode = "00000000");
wait until (ss2_digit_anodes = "0111");
check(ss2_kathode = "00110000");
end if;
if run("Multiple byte read") then
wait until falling_edge(clk);
mst2ss2 <= bus_tb_mst2slv(address => 0, writeData => 16#14131211#, writeEnable => '1', writeMask => 15);
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 0, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#14131211#);
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 1, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#141312#);
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 2, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#1413#);
mst2ss2 <= BUS_MST2SLV_IDLE;
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '0');
mst2ss2 <= bus_tb_mst2slv(address => 3, readEnable => '1');
wait for clk_period;
check(ss2_2mst.fault = '0');
check(ss2_2mst.ack = '1');
check_equal(to_integer(unsigned(ss2_2mst.readData)), 16#14#);
mst2ss2 <= BUS_MST2SLV_IDLE;
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
ss_1 : entity src.seven_seg_controller
generic map (
hold_count => ss1_ticks,
digit_count => ss1_digit_count
)
port map (
clk => clk,
rst => rst,
mst2slv => mst2ss1,
slv2mst => ss1_2mst,
digit_anodes => ss1_digit_anodes,
kathode => ss1_kathode
);
ss_2 : entity src.seven_seg_controller
generic map (
hold_count => ss2_ticks,
digit_count => ss2_digit_count
)
port map (
clk => clk,
rst => rst,
mst2slv => mst2ss2,
slv2mst => ss2_2mst,
digit_anodes => ss2_digit_anodes,
kathode => ss2_kathode
);
end architecture;
| mit | 6a7f4bcd8b8ab02a4ff9da343835c23e | 0.495099 | 3.684106 | false | false | false | false |
chastell/art-decomp | kiss/dk17_jed.vhd | 1 | 4,134 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk17_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk17_jed;
architecture behaviour of dk17_jed is
constant s10000000: std_logic_vector(2 downto 0) := "010";
constant s01000000: std_logic_vector(2 downto 0) := "000";
constant s00100000: std_logic_vector(2 downto 0) := "100";
constant s00010000: std_logic_vector(2 downto 0) := "110";
constant s00001000: std_logic_vector(2 downto 0) := "101";
constant s00000100: std_logic_vector(2 downto 0) := "001";
constant s00000010: std_logic_vector(2 downto 0) := "111";
constant s00000001: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "---";
case current_state is
when s10000000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s00010000; output <= "010";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s00001000; output <= "010";
end if;
when s01000000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00000100; output <= "000";
end if;
when s00100000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00010000 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "101";
elsif std_match(input, "10") then next_state <= s00010000; output <= "010";
elsif std_match(input, "11") then next_state <= s00001000; output <= "101";
end if;
when s00001000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000100 =>
if std_match(input, "00") then next_state <= s00000010; output <= "000";
elsif std_match(input, "01") then next_state <= s00000001; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000010 =>
if std_match(input, "00") then next_state <= s00010000; output <= "010";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s00001000; output <= "010";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00000001 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when others => next_state <= "---"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 75818e06eb64d174fef94659fe2cbc95 | 0.609821 | 3.479798 | false | false | false | false |
chastell/art-decomp | kiss/bbtas_nov.vhd | 1 | 3,027 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbtas_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbtas_nov;
architecture behaviour of bbtas_nov is
constant st0: std_logic_vector(2 downto 0) := "011";
constant st1: std_logic_vector(2 downto 0) := "000";
constant st2: std_logic_vector(2 downto 0) := "101";
constant st3: std_logic_vector(2 downto 0) := "110";
constant st4: std_logic_vector(2 downto 0) := "001";
constant st5: std_logic_vector(2 downto 0) := "010";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st1; output <= "00";
elsif std_match(input, "10") then next_state <= st1; output <= "00";
elsif std_match(input, "11") then next_state <= st1; output <= "00";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st2; output <= "00";
elsif std_match(input, "10") then next_state <= st2; output <= "00";
elsif std_match(input, "11") then next_state <= st2; output <= "00";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st1; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "00";
elsif std_match(input, "10") then next_state <= st3; output <= "00";
elsif std_match(input, "11") then next_state <= st3; output <= "00";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st4; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "01";
elsif std_match(input, "10") then next_state <= st3; output <= "10";
elsif std_match(input, "11") then next_state <= st3; output <= "11";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st5; output <= "00";
elsif std_match(input, "01") then next_state <= st4; output <= "00";
elsif std_match(input, "10") then next_state <= st4; output <= "00";
elsif std_match(input, "11") then next_state <= st4; output <= "00";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st5; output <= "00";
elsif std_match(input, "10") then next_state <= st5; output <= "00";
elsif std_match(input, "11") then next_state <= st5; output <= "00";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 3c45da9ebea51e5d3567987ff6c38fcd | 0.582094 | 3.230523 | false | false | false | false |
chastell/art-decomp | kiss/bbara_hot.vhd | 1 | 6,347 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_hot;
architecture behaviour of bbara_hot is
constant st0: std_logic_vector(9 downto 0) := "1000000000";
constant st1: std_logic_vector(9 downto 0) := "0100000000";
constant st4: std_logic_vector(9 downto 0) := "0010000000";
constant st2: std_logic_vector(9 downto 0) := "0001000000";
constant st3: std_logic_vector(9 downto 0) := "0000100000";
constant st7: std_logic_vector(9 downto 0) := "0000010000";
constant st5: std_logic_vector(9 downto 0) := "0000001000";
constant st6: std_logic_vector(9 downto 0) := "0000000100";
constant st8: std_logic_vector(9 downto 0) := "0000000010";
constant st9: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "--01") then next_state <= st0; output <= "00";
elsif std_match(input, "--10") then next_state <= st0; output <= "00";
elsif std_match(input, "--00") then next_state <= st0; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st1 =>
if std_match(input, "--01") then next_state <= st1; output <= "00";
elsif std_match(input, "--10") then next_state <= st1; output <= "00";
elsif std_match(input, "--00") then next_state <= st1; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st2; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st2 =>
if std_match(input, "--01") then next_state <= st2; output <= "00";
elsif std_match(input, "--10") then next_state <= st2; output <= "00";
elsif std_match(input, "--00") then next_state <= st2; output <= "00";
elsif std_match(input, "0011") then next_state <= st1; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st3 =>
if std_match(input, "--01") then next_state <= st3; output <= "10";
elsif std_match(input, "--10") then next_state <= st3; output <= "10";
elsif std_match(input, "--00") then next_state <= st3; output <= "10";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "10";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st4 =>
if std_match(input, "--01") then next_state <= st4; output <= "00";
elsif std_match(input, "--10") then next_state <= st4; output <= "00";
elsif std_match(input, "--00") then next_state <= st4; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st5; output <= "00";
end if;
when st5 =>
if std_match(input, "--01") then next_state <= st5; output <= "00";
elsif std_match(input, "--10") then next_state <= st5; output <= "00";
elsif std_match(input, "--00") then next_state <= st5; output <= "00";
elsif std_match(input, "0011") then next_state <= st4; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "00";
end if;
when st6 =>
if std_match(input, "--01") then next_state <= st6; output <= "01";
elsif std_match(input, "--10") then next_state <= st6; output <= "01";
elsif std_match(input, "--00") then next_state <= st6; output <= "01";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "01";
end if;
when st7 =>
if std_match(input, "--01") then next_state <= st7; output <= "00";
elsif std_match(input, "--10") then next_state <= st7; output <= "00";
elsif std_match(input, "--00") then next_state <= st7; output <= "00";
elsif std_match(input, "0011") then next_state <= st8; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st8 =>
if std_match(input, "--01") then next_state <= st8; output <= "00";
elsif std_match(input, "--10") then next_state <= st8; output <= "00";
elsif std_match(input, "--00") then next_state <= st8; output <= "00";
elsif std_match(input, "0011") then next_state <= st9; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st9 =>
if std_match(input, "--01") then next_state <= st9; output <= "00";
elsif std_match(input, "--10") then next_state <= st9; output <= "00";
elsif std_match(input, "--00") then next_state <= st9; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when others => next_state <= "----------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 563521b8a0d67918ef96d65cd77c2140 | 0.574445 | 3.317825 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/l_barrel.vhd | 2 | 1,058 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------
-- Entity implementing shiftrow operation.
-- amount<0> controls rotation by one byte to the left
-- amount<1> controls rotation by two bytes
-- Input size configurable through generic parameter SIZE
-----------------------------------------------------------------------
-- Component Declaration
entity L_barrel is
generic ( SIZE : integer := 32 );
port (
d_in : in std_logic_vector (SIZE-1 downto 0);
amount : in std_logic_vector (1 downto 0); -- 0 to 3
d_out : out std_logic_vector (SIZE-1 downto 0) ) ;
end L_barrel;
-- Architecture of the Component
architecture a_L_barrel of L_barrel is
signal inner : std_logic_vector (SIZE-1 downto 0);
begin
inner <= d_in( SIZE/4*3-1 downto 0 ) & d_in( SIZE-1 downto SIZE/4*3 )
when ( amount(0)='1' ) else d_in;
d_out <= inner( SIZE/2-1 downto 0 ) & inner( SIZE-1 downto SIZE/2 )
when ( amount(1)='1' ) else inner;
end a_L_barrel;
| mit | cb1c6dfb0dc133fb21f0cfa2cf22505b | 0.57656 | 3.712281 | false | false | false | false |
caiopo/battleship-vhdl | src/clock_conv.vhd | 1 | 1,271 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity clock_conv is
port
(
IN_50MHz : in std_logic;
-- Output ports
OUT_0_1Hz : out std_logic;
OUT_1Hz : out std_logic;
OUT_10Hz : out std_logic
);
end clock_conv;
architecture clock_convimpl of clock_conv is
signal count_a: integer range 0 to 5000000;
signal count_b,count_c: integer range 0 to 10;
signal aux,aux2: STD_LOGIC;
begin
process (IN_50MHz)
begin
if rising_edge(IN_50MHz) then
count_a <= count_a + 1;
if (count_a < 2500000) then
OUT_10Hz <= '0';
aux <= '0';
else
OUT_10Hz <= '1';
aux <= '1';
if (count_a = 4999999) then
count_a <= 0;
end if;
end if;
end if;
end process;
process (aux)
begin
if rising_edge(aux) then
count_b <= count_b + 1;
if (count_b < 5) then
OUT_1Hz <= '0';
aux2 <= '0';
else
OUT_1Hz <= '1';
aux2 <= '1';
if (count_b = 9) then
count_b <= 0;
end if;
end if;
end if;
end process;
process (aux2)
begin
if rising_edge(aux2) then
count_c <= count_c + 1;
if (count_c < 5) then
OUT_0_1Hz <= '0';
else
OUT_0_1Hz <= '1';
if (count_c = 9) then
count_c <= 0;
end if;
end if;
end if;
end process;
end clock_convimpl; | mit | 45a310d33cd65558c36d52f6fbd5e039 | 0.557828 | 2.458414 | false | false | false | false |
chastell/art-decomp | kiss/s1488_hot.vhd | 1 | 33,613 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1488_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1488_hot;
architecture behaviour of s1488_hot is
constant s000000: std_logic_vector(47 downto 0) := "100000000000000000000000000000000000000000000000";
constant s001110: std_logic_vector(47 downto 0) := "010000000000000000000000000000000000000000000000";
constant s011000: std_logic_vector(47 downto 0) := "001000000000000000000000000000000000000000000000";
constant s010000: std_logic_vector(47 downto 0) := "000100000000000000000000000000000000000000000000";
constant s010100: std_logic_vector(47 downto 0) := "000010000000000000000000000000000000000000000000";
constant s110011: std_logic_vector(47 downto 0) := "000001000000000000000000000000000000000000000000";
constant s010011: std_logic_vector(47 downto 0) := "000000100000000000000000000000000000000000000000";
constant s000100: std_logic_vector(47 downto 0) := "000000010000000000000000000000000000000000000000";
constant s100011: std_logic_vector(47 downto 0) := "000000001000000000000000000000000000000000000000";
constant s010110: std_logic_vector(47 downto 0) := "000000000100000000000000000000000000000000000000";
constant s010111: std_logic_vector(47 downto 0) := "000000000010000000000000000000000000000000000000";
constant s000111: std_logic_vector(47 downto 0) := "000000000001000000000000000000000000000000000000";
constant s101011: std_logic_vector(47 downto 0) := "000000000000100000000000000000000000000000000000";
constant s001111: std_logic_vector(47 downto 0) := "000000000000010000000000000000000000000000000000";
constant s111100: std_logic_vector(47 downto 0) := "000000000000001000000000000000000000000000000000";
constant s101100: std_logic_vector(47 downto 0) := "000000000000000100000000000000000000000000000000";
constant s001100: std_logic_vector(47 downto 0) := "000000000000000010000000000000000000000000000000";
constant s010001: std_logic_vector(47 downto 0) := "000000000000000001000000000000000000000000000000";
constant s011011: std_logic_vector(47 downto 0) := "000000000000000000100000000000000000000000000000";
constant s110110: std_logic_vector(47 downto 0) := "000000000000000000010000000000000000000000000000";
constant s011111: std_logic_vector(47 downto 0) := "000000000000000000001000000000000000000000000000";
constant s101110: std_logic_vector(47 downto 0) := "000000000000000000000100000000000000000000000000";
constant s010101: std_logic_vector(47 downto 0) := "000000000000000000000010000000000000000000000000";
constant s111110: std_logic_vector(47 downto 0) := "000000000000000000000001000000000000000000000000";
constant s000011: std_logic_vector(47 downto 0) := "000000000000000000000000100000000000000000000000";
constant s111010: std_logic_vector(47 downto 0) := "000000000000000000000000010000000000000000000000";
constant s011010: std_logic_vector(47 downto 0) := "000000000000000000000000001000000000000000000000";
constant s111011: std_logic_vector(47 downto 0) := "000000000000000000000000000100000000000000000000";
constant s100000: std_logic_vector(47 downto 0) := "000000000000000000000000000010000000000000000000";
constant s101000: std_logic_vector(47 downto 0) := "000000000000000000000000000001000000000000000000";
constant s110000: std_logic_vector(47 downto 0) := "000000000000000000000000000000100000000000000000";
constant s011110: std_logic_vector(47 downto 0) := "000000000000000000000000000000010000000000000000";
constant s010010: std_logic_vector(47 downto 0) := "000000000000000000000000000000001000000000000000";
constant s001010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000100000000000000";
constant s000010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000010000000000000";
constant s111000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000001000000000000";
constant s100100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000100000000000";
constant s001000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000010000000000";
constant s001011: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000001000000000";
constant s110100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000100000000";
constant s100110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000010000000";
constant s011101: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000001000000";
constant s000110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000100000";
constant s110010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000010000";
constant s011100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000001000";
constant s101010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000100";
constant s100010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000010";
constant s100111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(47 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------------------------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-11----") then next_state <= s000000; output <= "0100011010010010111";
elsif std_match(input, "0-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0100011010010010111";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "--00----") then next_state <= s000000; output <= "0000000010000110000";
elsif std_match(input, "--10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "00------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0010100010001110000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---0---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "0010100010001110000";
end if;
when s011000 =>
if std_match(input, "0-10-010") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000010000000000101";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000010000000000100";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000011000011011101";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "0000000000001111101";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "0000000000001111100";
elsif std_match(input, "0-00-000") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "0000010001001101101";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "0000010001001101100";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "0-----01") then next_state <= s000000; output <= "0000001100111010011";
elsif std_match(input, "0-----11") then next_state <= s000000; output <= "0000001100111010010";
elsif std_match(input, "1-----11") then next_state <= s010100; output <= "0000001100111010010";
elsif std_match(input, "1-----01") then next_state <= s010100; output <= "0000001100111010011";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "0000010001001101101";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "0000010001001101100";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "0000010001001101001";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "0000010001001101000";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000011000011011101";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "0000000000001111101";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "0000000000001111100";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "0000000000001111001";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "0000000000001111000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000010000000000001";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000010000000000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000010000000000100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000010000000000101";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000001010001010000";
end if;
when s010011 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0000001010000110011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0000001010000110111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010000110111";
end if;
when s000100 =>
if std_match(input, "11---01-") then next_state <= s100011; output <= "0000001010001010000";
elsif std_match(input, "01---01-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "01---11-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10----1-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "00----1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0-----0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000001010001010000";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000001000011011001";
end if;
when s110011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s000111; output <= "0000001010001010000";
end if;
when s000111 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000001000011011110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000001000011011010";
end if;
when s101011 =>
if std_match(input, "1-------") then next_state <= s001111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s001111 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0001000000101011011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0001000000101011111";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000101011111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001000000101011011";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0100001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "0000010001001101000";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "0000000000001111000";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000010000000000000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010010010111";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "0000010001001101000";
end if;
when s111100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "1-------") then next_state <= s100011; output <= "0000001110001010000";
end if;
when s101100 =>
if std_match(input, "1-------") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010111 =>
if std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000110010010";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000000110010110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110010010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000110010110";
end if;
when s001100 =>
if std_match(input, "1----0--") then next_state <= s010001; output <= "0000001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010001 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011110111";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "0000001000011110111";
elsif std_match(input, "1----0--") then next_state <= s110110; output <= "0000001000011110011";
end if;
when s110110 =>
if std_match(input, "1-------") then next_state <= s011111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110111111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110111110";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110111010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110111011";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110111010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110111011";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110111110";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110111111";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010101 =>
if std_match(input, "1----1--") then next_state <= s111110; output <= "0000001000001111101";
elsif std_match(input, "1----0--") then next_state <= s111110; output <= "0000001000001111001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000001111101";
end if;
when s111110 =>
if std_match(input, "00--1-0-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "01--1-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "10--1--1") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "10--1--0") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--1-11") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "11--0-11") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-10") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--0-10") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "11--1-01") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--0-0-") then next_state <= s000011; output <= "0000001010001010000";
end if;
when s000011 =>
if std_match(input, "1----0-1") then next_state <= s001110; output <= "0000001010010010011";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "0000001010010110011";
elsif std_match(input, "1----1--") then next_state <= s001110; output <= "0000001010010010111";
elsif std_match(input, "0----0-1") then next_state <= s000000; output <= "0000001010010010011";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000001010010010011";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010010010011";
end if;
when s100000 =>
if std_match(input, "00--1---") then next_state <= s000000; output <= "0000101010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "11--1---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000101010001010000";
elsif std_match(input, "11--0---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000001010001010000";
end if;
when s101000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "1-------") then next_state <= s010010; output <= "0000001010000110011";
end if;
when s010010 =>
if std_match(input, "1---0---") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0---0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000001010001010000";
end if;
when s011110 =>
if std_match(input, "0-00-00-") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0--0-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0--1-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "1-0--1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "0000000000001111000";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "0000000000001111001";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "0000010001001101001";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "0000010001001101000";
elsif std_match(input, "1-10-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000010000000000001";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000010000000000000";
elsif std_match(input, "1-11-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0001001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001010 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000001010100010001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
end if;
when s111000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000001010001010000";
elsif std_match(input, "1---00--") then next_state <= s001000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001000; output <= "0000001010001010000";
end if;
when s001000 =>
if std_match(input, "1----0--") then next_state <= s100100; output <= "0000001000011011001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
end if;
when s100100 =>
if std_match(input, "1-------") then next_state <= s001011; output <= "0001001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001011 =>
if std_match(input, "1----0--") then next_state <= s110100; output <= "0000001000011011010";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000001000011011110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0001001010001010000";
end if;
when s011011 =>
if std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000011010111";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000011010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000011010010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000011010011";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000001000011010010";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000001000011010011";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000001000011010110";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000001000011010111";
end if;
when s100110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011101; output <= "0000001010001010000";
end if;
when s011101 =>
if std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110011000";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011001";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110011101";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110011100";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110011101";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110011100";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110011000";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011001";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "0000001000001111001";
end if;
when s000110 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010001010000";
elsif std_match(input, "1---01--") then next_state <= s011000; output <= "0100001010001010000";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0001001010001010000";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0100001010001010000";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0001001010001010000";
end if;
when s011010 =>
if std_match(input, "1----1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000001010100010001";
elsif std_match(input, "1----01-") then next_state <= s110010; output <= "0000001010100010000";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001010100010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s110010 =>
if std_match(input, "1----00-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011100 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000111010111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000111010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000111010011";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000111010010";
elsif std_match(input, "1----10-") then next_state <= s101010; output <= "0000001000111010110";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000001000111010111";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000001000111010011";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000001000111010010";
end if;
when s101010 =>
if std_match(input, "1-------") then next_state <= s111010; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s100010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011010; output <= "0000001010001010000";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "0000001010010110011";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010101010010010111";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0010101010010010111";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000001000011010010";
end if;
when others => next_state <= "------------------------------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 2d136ee9d87f584b6d9fbd6412993a52 | 0.64722 | 4.06937 | false | false | false | false |
chastell/art-decomp | kiss/s27_jed.vhd | 1 | 3,869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_jed;
architecture behaviour of s27_jed is
constant s000: std_logic_vector(2 downto 0) := "110";
constant s001: std_logic_vector(2 downto 0) := "100";
constant s101: std_logic_vector(2 downto 0) := "000";
constant s100: std_logic_vector(2 downto 0) := "010";
constant s010: std_logic_vector(2 downto 0) := "011";
constant s011: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | e006203b5989e07f6bf3222edac28e58 | 0.576376 | 3.181743 | false | false | false | false |
chastell/art-decomp | kiss/dk15_hot.vhd | 1 | 3,728 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk15_hot is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk15_hot;
architecture behaviour of dk15_hot is
constant state1: std_logic_vector(3 downto 0) := "1000";
constant state2: std_logic_vector(3 downto 0) := "0100";
constant state3: std_logic_vector(3 downto 0) := "0010";
constant state4: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-----";
case current_state is
when state1 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state2 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state3; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state3 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "10100";
elsif std_match(input, "101") then next_state <= state2; output <= "01000";
elsif std_match(input, "110") then next_state <= state4; output <= "01010";
end if;
when state4 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "10000";
end if;
when others => next_state <= "----"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 634bccb91a3fe609934b120f35d499f5 | 0.60971 | 3.464684 | false | false | false | false |
ibm2030/IBM2030 | panel_Switches.vhd | 1 | 11,959 | ---------------------------------------------------------------------------
-- Copyright © 2015 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: panel_Switches.vhd
-- Creation Date: 13:26:00 25/11/2015
-- Description:
-- 360/30 Front Panel Switch reading and status LED drivers
-- This reads all the front panel rotary and pushbutton switches
-- and also drives the 5 status LEDs at the lower-right
-- A Maxim MAX7318 device is used to scan (3 outputs) and read (8 inputs)
-- the switches, and also to drive the LEDs (5 outputs)
--
-- Revision History:
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity panel_Switches is
Generic (
Clock_divider : integer := 9; -- Fastest allowed is 1.4MHz / 36 for 50MHz clk
Read_delay : integer := 700; -- Number of divided clocks to wait between scan drive and switch read
Number_Switches : integer := 64;
Number_LEDs : integer := 5;
MAX7318_address : std_logic_vector(6 downto 0) := "0100000"
);
Port ( -- Lamp input vector
LEDs : in std_logic_vector(0 to Number_LEDs-1);
-- Switch output vector
Switches : out std_logic_vector(0 to Number_Switches-1);
-- Other inputs
clk : in STD_LOGIC; -- 50MHz default
reset : in STD_LOGIC := '0';
-- Driver outputs
SCL : out std_logic;
SDA : inout std_logic
);
end panel_Switches;
architecture Behavioral of panel_Switches is
signal clk_out : std_logic := '0';
signal MAX7318_SCL, new_MAX7318_SCL, MAX7318_SDA, new_MAX7318_SDA : std_logic := '1';
type SPI_state_type is (idle_h,start_h,start_hl,data_l,data_lh,data_hl,ack_l,ack_l2,ack_lh,ack_h,ack_hl,stop_l,stop_lh,stop_h, stop_h2);
signal SPI_state, new_SPI_state : SPI_state_type := idle_h;
type MAX7318_state_type is (idle,writing45,writing67,writing2,delay,reading1);
signal MAX7318_state, new_MAX7318_state : MAX7318_state_type := idle;
signal SPI_error,new_SPI_error : Boolean := false;
signal bit_counter, new_bit_counter : integer range 0 to 8;
signal byteCount, new_byteCount : integer range 0 to 4;
signal delayCounter, new_delayCounter : integer range 0 to 50000;
constant top_data_out_bit : integer := 31;
signal dataOut, new_dataOut : std_logic_vector(top_data_out_bit downto 0);
signal dataIn, new_dataIn : std_logic_vector(7 downto 0);
signal writeByte, new_writeByte : std_logic_vector(3 downto 0);
signal switchBank, new_switchBank : std_logic_vector(2 downto 0) := "000";
type switchArrayType is array(0 to (Number_Switches+7)/8-1) of std_logic_vector(7 downto 0);
signal switchVector, new_switchVector : switchArrayType := (others=>"00000000");
-- MAX7318 stream is: start, address(7), r/w(1),
-- Address is 0x40 (AD0,1,2=0)
-- Registers are:
-- 00 Input 1 Unused
-- 01 Input 2 Scan inputs
-- 02 Output 1 0,1,2=Scan outputs 3,4,5,6,7=LEDs
-- 03 Output 2 Unused
-- 04 Port 1 Invert 1=Invert 00
-- 05 Port 2 Invert 1=Invert 00
-- 06 Port 1 Config 1=Input 00
-- 07 Port 2 Config 1=Input FF
-- FSM sequence is:
-- Write 04,05: Write Command=4, Register4, Register5
-- Write 06,07: Write Command=6, Register6, Register7
-- Write 02, Wait 1ms, Read 01: Write Command=2, Register2, Wait, Write Command=1, Read Register1
-- Basic scan allocation is:
-- Scan Switches
-- 0 ROS,RATE,ADDR_COMP
-- 1 CHECK_CTL,A
-- 2 B,C
-- 3 D,E
-- 4 E_O,SwSpare,E_I
-- 5 G,H
-- 6 J,SwPower,SwLeft1
-- 7 SwLeft2
-- Switch bit allocation is:
-- Pos Scan Bit Switch Position
-- 0 0 7 ROSCTL_1 INH CF STOP
-- 1 0 6 ROSCTL_3 ROS SCAN
-- 2 0 5 RATE_1 INSN STEP
-- 3 0 4 RATE_3 SINGLE CYC
-- 4 0 3 ADDR_COMP_3
-- 5 0 2 ADDR_COMP_2
-- 6 0 1 ADDR_COMP_1
-- 7 0 0 ADDR_COMP_0
-- 8 1 7 CHECK_CTL_1 DIAGNOSTIC
-- 9 1 6 CHECK_CTL_2 DISABLE
-- 10 1 5 CHECK_CTL_4 STOP
-- 11 1 4 CHECK_CTL_5 RESTART
-- 12 1 3 A_3
-- 13 1 2 A_2
-- 14 1 1 A_1
-- 15 1 0 A_0
-- 16 2 7 B_3
-- 17 2 6 B_2
-- 18 2 5 B_1
-- 19 2 4 B_0
-- 20 2 3 C_3
-- 21 2 2 C_2
-- 22 2 1 C_1
-- 23 2 0 C_0
-- 24 3 7 D_3
-- 25 3 6 D_2
-- 26 3 5 D_1
-- 27 3 4 D_0
-- 28 3 3 F_3
-- 29 3 2 F_2
-- 30 3 1 F_1
-- 31 3 0 F_0
-- 32 4 7 SPARE_4
-- 33 4 6 SPARE_2
-- 34 4 5 EI_1 Black/Inner
-- 35 4 4 EI_3 Grey/Outer
-- 36 4 3 EO_3 \
-- 37 4 2 EO_2 \ 0
-- 38 4 1 EO_1 \ =
-- 39 4 0 EO_0 \ ?
-- 40 5 7 G_3
-- 41 5 6 G_2
-- 42 5 5 G_1
-- 43 5 4 G_0
-- 44 5 3 H_3
-- 45 5 2 H_2
-- 46 5 1 H_1
-- 47 5 0 H_0
-- 48 6 7 J_3
-- 49 6 6 J_2
-- 50 6 5 J_1
-- 51 6 4 J_0
-- 52 6 3 PWR_4 LOAD
-- 53 6 2 PWR_2 INTERRUPT
-- 54 6 1 PB_20 DISPLAY
-- 55 6 0 PB_18 STOP
-- 56 7 7 PB_16 START
-- 57 7 6 PB_14 LAMP TEST
-- 58 7 5 PB_12 CHECK RESET
-- 59 7 4 PB_10 STORE
-- 60 7 3 PB_8 SET IC
-- 61 7 2 PB_6 ROAR RESET
-- 62 7 1 PB_4 INT TMR
-- 63 7 0 PB_2 SYSTEM RESET
-- LED Driver allocation
-- Bit Output Lamp
-- 4 7 LOAD
-- 3 6 TEST
-- 2 5 WAIT
-- 1 4 MAN
-- 0 3 SYS
begin
gen_clk : process (clk) is
variable divider : integer := Clock_divider;
begin
if rising_edge(clk) then
if (divider=0) then
divider := Clock_divider;
clk_out <= not clk_out;
else
divider := divider - 1;
end if;
end if;
end process;
max7318 : process (clk_out) is
begin
if rising_edge(clk_out) then
new_bit_counter <= bit_counter;
new_byteCount <= byteCount;
new_SPI_state <= SPI_state;
new_MAX7318_state <= MAX7318_state;
new_delayCounter <= delayCounter;
new_dataOut <= dataOut;
new_dataIn <= dataIn;
new_writeByte <= writeByte;
new_switchBank <= switchBank;
new_switchVector <= switchVector;
new_SPI_error <= SPI_error;
case (SPI_state) is
when idle_h =>
new_MAX7318_SDA <= '1';
new_MAX7318_SCL <= '1';
when start_h =>
new_MAX7318_SDA <= '0';
new_MAX7318_SCL <= '1';
new_SPI_state <= start_hl;
new_SPI_error <= false;
when start_hl =>
-- Min 600ns (tSU STA)
new_MAX7318_SDA <= '0';
new_MAX7318_SCL <= '0';
new_SPI_state <= data_l;
new_bit_counter <= 7;
when data_l =>
-- Min 1300ns including data_lh state (tLOW)
if (writeByte(3)='0') then
new_MAX7318_SDA <= dataOut(top_data_out_bit);
new_dataOut <= dataOut(top_data_out_bit-1 downto 0) & '0';
else
new_MAX7318_SDA <= '1';
new_dataIn <= dataIn(6 downto 0) & MAX7318_SDA;
end if;
new_SPI_state <= data_lh;
when data_lh =>
-- Min 100ns (tSU DAT)
new_MAX7318_SCL <= '1';
new_SPI_state <= data_hl;
when data_hl =>
-- Min 700ns (tHIGH)
new_MAX7318_SCL <= '0';
if (bit_counter = 0) then
new_SPI_state <= ack_l;
else
new_bit_counter <= bit_counter - 1;
new_SPI_state <= data_l;
end if;
when ack_l =>
-- Min 1300ns including ack_lh (tLOW)
new_MAX7318_SCL <= '0';
new_SPI_state <= ack_l2;
when ack_l2 =>
if (writeByte(3)='1') then
new_MAX7318_SDA <= '0';
else
new_MAX7318_SDA <= '1';
end if;
new_SPI_state <= ack_lh;
when ack_lh =>
-- Min 300ns (tHD DAT)
new_MAX7318_SCL <= '1';
new_SPI_state <= ack_h;
when ack_h =>
-- Min 700ns (tHIGH)
if (writeByte(3)='0') then
if (MAX7318_SDA = '0') then
-- Ok
else
-- Error
new_SPI_error <= true;
end if;
else
new_MAX7318_SDA <= '0';
end if;
new_SPI_state <= ack_hl;
when ack_hl =>
-- Min 300ns (tHD DAT)
new_MAX7318_SCL <= '0';
if (byteCount = 1) then
-- new_MAX7318_SDA <= '0';
new_SPI_state <= stop_l;
else
new_SPI_state <= data_l;
new_byteCount <= byteCount - 1;
new_writeByte <= writeByte(2 downto 0) & "0";
new_bit_counter <= 7;
end if;
when stop_l =>
new_MAX7318_SDA <= '0';
new_SPI_state <= stop_lh;
when stop_lh =>
-- new_MAX7318_SDA <= '0';
new_MAX7318_SCL <= '1';
new_SPI_state <= stop_h;
when stop_h =>
-- Min 600ns (tSU STO)
new_MAX7318_SDA <= '1';
new_MAX7318_SCL <= '1';
new_SPI_state <= stop_h2;
when stop_h2 =>
-- Min 1300ns including idle_h (tBUF)
new_SPI_state <= idle_h;
end case;
case MAX7318_state is
when idle =>
if (SPI_state = idle_h) then
new_dataOut <= MAX7318_address & "0" & "00000100" & "00000000" & "00000000"; -- 4,5 = 00,00
new_writeByte <= "0000";
new_byteCount <= 4;
new_SPI_state <= start_h;
new_MAX7318_state <= writing45;
end if;
when writing45 =>
if (SPI_state = idle_h) then
new_dataOut <= MAX7318_address & "0" & "00000110" & "00000000" & "11111111"; -- 6,7 = 00,FF
new_writeByte <= "0000";
new_byteCount <= 4;
new_SPI_state <= start_h;
new_MAX7318_state <= writing67;
end if;
when writing67 =>
if (SPI_state = idle_h) then
new_dataOut <= MAX7318_address & "0" & "00000010" & LEDs & switchBank & "00000000"; -- 2 = LLLLLSSS
new_writeByte <= "0000";
new_byteCount <= 3;
new_SPI_state <= start_h;
new_MAX7318_state <= writing2;
end if;
when writing2 =>
if (SPI_state = idle_h) then
new_delayCounter <= Read_delay;
new_MAX7318_state <= delay;
end if;
when delay =>
if (delayCounter = 0) then
new_dataOut <= MAX7318_address & "1" & "00000001" & "11111111" & "00000000"; -- 1 = RRRRRRRR
new_writeByte <= "0010";
new_byteCount <= 3;
new_SPI_state <= start_h;
new_MAX7318_state <= reading1;
else
new_delayCounter <= delayCounter - 1;
end if;
when reading1 =>
if (SPI_state = idle_h) then
if (not SPI_error) then
new_switchVector(to_integer(unsigned(switchBank))) <= dataIn(7 downto 0);
end if;
new_switchBank <= std_logic_vector(unsigned(switchBank) + 1);
new_MAX7318_state <= idle;
end if;
end case;
-- State variable updates
MAX7318_SCL <= new_MAX7318_SCL;
MAX7318_SDA <= new_MAX7318_SDA;
bit_counter <= new_bit_counter;
byteCount <= new_byteCount;
if (reset='0') then
SPI_state <= new_SPI_state;
MAX7318_state <= new_MAX7318_state;
SPI_error <= new_SPI_error;
else
SPI_state <= idle_h;
MAX7318_state <= idle;
SPI_error <= false;
end if;
delayCounter <= new_delayCounter;
dataOut <= new_dataOut;
dataIn <= new_dataIn;
writeByte <= new_writeByte;
switchBank <= new_SwitchBank;
switchVector <= new_SwitchVector;
-- Outputs
switches <= switchVector(0) & switchVector(1) & switchVector(2) & switchVector(3) & switchVector(4) & switchVector(5) & switchVector(6) & switchVector(7);
SCL <= new_MAX7318_SCL;
if (new_MAX7318_SDA = '0') then
-- Simulate Open Collector output - pin is defined in UCF to be PULLUP
SDA <= '0';
else
SDA <= 'Z';
end if;
end if;
end process;
end behavioral;
| gpl-3.0 | b7a6e66aa42da880b41a786b80b5ef2a | 0.588594 | 2.634141 | false | false | false | false |
ibm2030/IBM2030 | cpu.vhd | 1 | 26,316 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: cpu.vhd
-- Creation Date: 22:15:23 2010-06-30
-- Description:
-- Top level of the CPU proper, combining all the various modules
-- including Processor, Storage, Multiplexor and (eventually) Selector(s)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
--
--
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity cpu is
Port (
WX_IND : OUT std_logic_vector(0 to 12);
W_IND_P : OUT std_logic;
X_IND_P : OUT std_logic;
IND_SALS : OUT SALS_Bus;
IND_EX,IND_CY_MATCH,IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P: OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M : OUT STD_LOGIC_VECTOR(0 to 8);
IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG : OUT STD_LOGIC;
IND_LOC_STG : OUT STD_LOGIC;
IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG : OUT STD_LOGIC;
IND_CHK_B_REG : OUT STD_LOGIC;
IND_CHK_STOR_ADDR : OUT STD_LOGIC;
IND_CHK_CTRL_REG : OUT STD_LOGIC;
IND_CHK_ROS_SALS : OUT STD_LOGIC;
IND_CHK_ROS_ADDR : OUT STD_LOGIC;
IND_CHK_STOR_DATA : OUT STD_LOGIC;
IND_CHK_ALU : OUT STD_LOGIC;
IND_SYST : OUT STD_LOGIC;
IND_MAN : OUT STD_LOGIC;
IND_WAIT : OUT STD_LOGIC;
IND_TEST : OUT STD_LOGIC;
IND_LOAD : OUT STD_LOGIC;
SW_START,SW_LOAD,SW_SET_IC,SW_STOP,SW_POWER_OFF : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_LAMP_TEST,SW_DSPLY,SW_STORE,SW_SYS_RST : IN STD_LOGIC;
SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : IN STD_LOGIC;
SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : IN STD_LOGIC;
SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
SW_INTRP_TIMER, SW_CONS_INTRP : IN STD_LOGIC;
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
E_SW : E_SW_BUS_Type;
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
DEBUG : OUT STD_LOGIC;
USE_MAN_DECODER_PWR : OUT STD_LOGIC;
N60_CY_TIMER_PULSE : IN STD_LOGIC;
M_CONV_OSC : OUT STD_LOGIC;
SwSlow : in std_logic;
clk : in std_logic);
end cpu;
architecture FMD of cpu is
-- Outputs from UDC1 (5-01 through 5-05)
signal sSALS : SALS_Bus;
signal CTRL : CTRL_REG;
signal T1,T2,T3,T4 : std_logic;
signal SEL_T1, SEL_T3, SEL_T4 : std_logic;
signal P1,P2,P3,P4 : std_logic;
signal A_BUS, B_BUS : std_logic_vector(0 to 8);
signal CLOCK_START : std_logic;
signal CLOCK_ON : std_logic;
signal STORE_S_REG_RST : std_logic; -- 03DC2
signal CTRL_REG_RST : std_logic; -- 01CB2
signal TO_KEY_SW : std_logic;
signal METERING_OUT : std_logic;
signal GT_1050_TAGS : std_logic;
signal GT_1050_BUS : std_logic;
signal SET_IND_ROSAR : STD_LOGIC;
signal GT_LOCAL_STORAGE : STD_LOGIC;
signal GT_T_REG_TO_MN : STD_LOGIC;
signal GT_CK_TO_MN : STD_LOGIC;
signal N_STACK_MEM_SELECT : STD_LOGIC;
signal WX_CHK : STD_LOGIC;
-- Outputs from UDC2 (5-06 through 5-09C)
signal Z_BUS,R : std_logic_vector(0 to 8);
signal MN : std_logic_vector(0 to 15);
signal CLOCK_OFF : std_logic;
signal A_REG_PC : std_logic;
signal MN_PC : std_logic;
signal Z0_BUS_0 : std_logic;
signal Z_0 : std_logic;
signal N_CTRL_N : std_logic;
signal ALU_CHK_LCH : std_logic;
signal SELECT_CPU_BUMP : std_logic;
signal sMPX_BUS_O : std_logic_vector(0 to 8);
-- Outputs from UDC3 (5-10A through 5-14D)
signal SEL_WR_CALL : STD_LOGIC := '0';
signal SX1_SHARE_CYCLE : STD_LOGIC := '0';
signal SX2_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_AUX_WR_CALL : STD_LOGIC := '0';
signal SEL_AUX_RD_CALL : STD_LOGIC := '0';
signal SEL_CONV_OSC : STD_LOGIC;
signal SEL_BASIC_CLOCK_OFF : STD_LOGIC;
signal SEL_SHARE_HOLD : STD_LOGIC := '0';
signal SEL_SHARE_CYCLE : STD_LOGIC := '0';
signal SEL_CHNL_DATA_XFER : STD_LOGIC := '0';
signal SEL_ROS_REQ : STD_LOGIC := '0';
signal SEL_READ_CALL : STD_LOGIC := '0';
signal SEL_RD_WR_CTRL : STD_LOGIC := '0';
signal SEL_RD_CALL_TO_STP : STD_LOGIC := '0';
signal SEL_CC_ROS_REQ : STD_LOGIC := '0';
signal MAN_DSPLY_GUV_HUV : STD_LOGIC := '0';
signal HSMPX_TRAP : STD_LOGIC := '0';
-- Inputs to UDC3
signal SEL_DATA_READY : STD_LOGIC;
signal SEL_CHNL_CPU_CLOCK_STOP : STD_LOGIC;
signal RST_SEL_CHNL_DIAG_LCHS : STD_LOGIC;
signal LOAD_REQ_LCH : STD_LOGIC;
signal USE_GR_OR_HR : STD_LOGIC;
signal SX_CHAIN_PULSE_1 : STD_LOGIC;
signal CHK_RST_SW : STD_LOGIC;
signal S : std_logic_vector(0 to 7);
signal sM_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : std_logic;
signal MACH_RST_2A,MACH_RST_2B,MACH_RST_3, MACH_RST_6 : std_logic;
signal CARRY_0 : STD_LOGIC;
signal COMPLEMENT,NTRUE : STD_LOGIC;
signal FT0,FT1,FT2,FT3,FT5,FT6,FT7 : STD_LOGIC;
signal M_ASSM_BUS1, N_ASSM_BUS1 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS2, N_ASSM_BUS2 : STD_LOGIC_VECTOR(0 to 8);
signal M_ASSM_BUS3, N_ASSM_BUS3 : STD_LOGIC_VECTOR(0 to 8) := "000000000";
signal N1050_INTRV_REQ : STD_LOGIC := '0';
signal TT6_POS_ATTN : STD_LOGIC := '0';
signal FT2_MPX_OPNL : STD_LOGIC := '0';
signal MPX_METERING_IN,METER_IN_SX1,METER_IN_SX2 : STD_LOGIC;
signal KEY_SW : STD_LOGIC;
signal GT_SWS_TO_WX_PWR : STD_LOGIC;
signal GT_MAN_SET_MN : STD_LOGIC;
signal EXT_TRAP_MASK_ON : STD_LOGIC;
signal MANUAL_STORE,MAN_STOR_OR_DSPLY : STD_LOGIC;
signal RECYCLE_RST : STD_LOGIC;
signal T_REQUEST : STD_LOGIC := '0';
signal MACH_RST_SET_LCH : STD_LOGIC;
signal RST_LOAD : STD_LOGIC;
signal CARRY_0_LCHD,CARRY_1_LCHD : STD_LOGIC;
signal ALU_CHK : STD_LOGIC;
signal CTRL_N,N_CTRL_LM : STD_LOGIC;
signal SX1_RD_CYCLE,SX2_RD_CYCLE : STD_LOGIC;
signal SX1_WR_CYCLE,SX2_WR_CYCLE : STD_LOGIC;
signal GT_DETECTORS_TO_HR : STD_LOGIC;
signal CPU_RD_PWR : STD_LOGIC;
signal XH,XL,XXH : STD_LOGIC;
signal SET_FW : STD_LOGIC;
signal keyboard_data : STD_LOGIC_VECTOR(7 downto 0);
signal keyboard_error : STD_LOGIC;
signal USE_MANUAL_DECODER : STD_LOGIC;
signal sUSE_MAN_DECODER_PWR : STD_LOGIC;
signal LOCAL_STORAGE_CP, MAIN_STORAGE_CP : STD_LOGIC;
signal STACK_RD_WR_CONTROL : STD_LOGIC;
signal H_REG_5_PWR : STD_LOGIC;
signal FORCE_M_REG_123 : STD_LOGIC;
signal N_SEL_SHARE_HOLD : STD_LOGIC;
signal GK,HK : STD_LOGIC_VECTOR(0 to 3);
signal PROT_LOC_CPU_OR_MPX : STD_LOGIC;
signal PROT_LOC_SEL_CHNL : STD_LOGIC;
signal EARLY_M_REG_0 : STD_LOGIC;
signal ODD : STD_LOGIC; -- 06B to 04A
signal SUPPR_A_REG_CHK : STD_LOGIC;
signal STATUS_IN_LCHD : STD_LOGIC;
signal M_REG_0 : STD_LOGIC;
signal SYS_RST_PRIORITY_LCH : STD_LOGIC;
signal STORE_R : STD_LOGIC;
signal SAL_PC : STD_LOGIC;
signal R_REG_PC : STD_LOGIC;
signal N2ND_ERROR_STOP : STD_LOGIC;
signal MEM_WRAP : STD_LOGIC;
signal MACH_RST_PROT : STD_LOGIC;
signal MACH_RST_MPX : STD_LOGIC;
signal GM_WM_DETECTED : STD_LOGIC;
signal FIRST_MACH_CHK_REQ : STD_LOGIC;
signal FIRST_MACH_CHK : STD_LOGIC;
signal DECIMAL : STD_LOGIC;
signal INTRODUCE_ALU_CHK : STD_LOGIC;
signal SERV_IN_LCHD, ADDR_IN_LCHD, OPNL_IN_LCHD : STD_LOGIC;
signal MPX_SHARE_REQ, MPX_INTERRUPT : STD_LOGIC;
signal CS_DECODE_X001 : STD_LOGIC;
signal SX1_INTERRUPT, SX2_INTERRUPT : STD_LOGIC;
signal SX_1_GATE, SX_2_GATE : STD_LOGIC;
signal SX_1_R_W_CTRL, SX_2_R_W_CTRL : STD_LOGIC;
signal SX_2_BUMP_SW_GT : STD_LOGIC;
signal FT3_MPX_SHARE_REQ : STD_LOGIC;
signal CONNECT : STD_LOGIC;
signal P_8F_DETECTED : STD_LOGIC;
signal BASIC_CS0 : STD_LOGIC;
signal USE_R : STD_LOGIC;
signal ANY_MACH_CHK : STD_LOGIC;
signal USE_MAIN_MEMORY, USE_LOCAL_MAIN_MEMORY : STD_LOGIC;
signal ALLOW_PROTECT : STD_LOGIC;
signal USE_BASIC_CA_DECO, USE_ALT_CA_DECODER : STD_LOGIC;
signal ALLOW_PC_SALS : STD_LOGIC;
signal SUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal N1401_MODE : STD_LOGIC;
signal MEM_PROTECT_REQUEST : STD_LOGIC;
signal MANUAL_DISPLAY : STD_LOGIC;
signal MAIN_STORAGE : STD_LOGIC;
signal MACH_RST_SET_LCH_DLY : STD_LOGIC;
signal MACH_RST_SW : STD_LOGIC;
signal MACH_CHK_RST : STD_LOGIC;
signal MACH_CHK_PULSE : STD_LOGIC;
signal GT_D_REG_TO_A_BUS : STD_LOGIC;
signal GT_CA_TO_W_REG : STD_LOGIC;
signal DATA_READY : STD_LOGIC;
signal CTRL_REG_CHK : STD_LOGIC;
signal CPU_WRITE_IN_R_REG : STD_LOGIC;
signal CPU_SET_ALLOW_WR_LCH : STD_LOGIC;
signal ANY_PRIORITY_LCH : STD_LOGIC;
signal ALLOW_WRITE_DLYD : STD_LOGIC;
signal ALLOW_WRITE : STD_LOGIC;
signal STORE_HR : STD_LOGIC;
signal STORE_GR : STD_LOGIC;
signal SEL_R_W_CTRL : STD_LOGIC;
signal SEL_CHNL_CHK : STD_LOGIC;
signal HR_REG_0_7, GR_REG_0_7 : STD_LOGIC_VECTOR(0 to 7);
signal STORE_BITS : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal HR_REG_P_BIT : STD_LOGIC;
signal GR_REG_P_BIT : STD_LOGIC;
signal GT_DETECTORS_TO_GR : STD_LOGIC;
signal EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : STD_LOGIC;
signal CHANNEL_RD_CALL : STD_LOGIC;
signal MPX_ROS_LCH : STD_LOGIC;
signal CK_SAL_P_BIT_TO_MPX : STD_LOGIC;
signal STG_MEM_SEL : STD_LOGIC;
signal GATED_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal CLOCK_START_LCH : STD_LOGIC;
signal LOAD_IND : STD_LOGIC;
signal CLOCK_OUT : STD_LOGIC;
signal READ_ECHO_1, READ_ECHO_2, WRITE_ECHO_1, WRITE_ECHO_2 : STD_LOGIC;
signal DIAGNOSTIC_SW : STD_LOGIC;
begin
firstBit: entity udc1 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
WX_IND => WX_IND,
X_IND_P => X_IND_P,
W_IND_P => W_IND_P,
A_BUS => A_BUS,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
MPX_BUS => sMPX_BUS_O,
S => S,
R => R,
MN => MN,
M_ASSM_BUS => M_ASSM_BUS1,
N_ASSM_BUS => N_ASSM_BUS1,
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_PWR_OFF => SW_POWER_OFF,
SW_LAMP_TEST => SW_LAMP_TEST,
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,SW_B => SW_B,SW_C => SW_C,SW_D => SW_D,
SW_F => SW_F,SW_G => SW_G,SW_H => SW_H,SW_J => SW_J,
SW_AP => SW_AP,SW_BP => SW_BP,SW_CP => SW_CP,SW_DP => SW_DP,
SW_FP => SW_FP,SW_GP => SW_GP,SW_HP => SW_HP,SW_JP => SW_JP,
TO_KEY_SW => TO_KEY_SW,
E_SW => E_SW, -- Main E switch bus
IND_SYST => IND_SYST,
IND_MAN => IND_MAN,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_LOAD => IND_LOAD,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
CARRY_0 => CARRY_0,
CARRY_0_LCHD => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
COMPLEMENT => COMPLEMENT,
NTRUE => NTRUE,
MPX_METERING_IN => MPX_METERING_IN,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
METER_IN_SX1 => METER_IN_SX1,
METER_IN_SX2 => METER_IN_SX2,
KEY_SW => KEY_SW,
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE,
N1050_INTRV_REQ => N1050_INTRV_REQ,
GT_1050_TAGS => GT_1050_TAGS,
GT_1050_BUS => GT_1050_BUS,
TT6_POS_ATTN => TT6_POS_ATTN,
FT2_MPX_OPNL => FT2_MPX_OPNL,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
FT0 => FT0,
FT1 => FT1,
FT2 => FT2,
FT3 => FT3,
FT5 => FT5,
FT6 => FT6,
FT7 => FT7,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
ALU_CHK => ALU_CHK,
CTRL_N => CTRL_N,
N_CTRL_N => N_CTRL_N,
N_CTRL_LM => N_CTRL_LM,
STORE_S_REG_RST => STORE_S_REG_RST,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
LOCAL_STORAGE_CP => LOCAL_STORAGE_CP,
SET_IND_ROSAR => SET_IND_ROSAR,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_TO_MN_REG => GT_T_REG_TO_MN,
GT_CK_TO_MN_REG => GT_CK_TO_MN,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
PROT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
WX_CHK => WX_CHK,
EARLY_M_REG_0 => EARLY_M_REG_0,
ODD => ODD,
XH => XH,
XL => XL,
XXH => XXH,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
M_REG_0 => M_REG_0,
SYS_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
STORE_R => STORE_R,
SAL_PC => SAL_PC,
R_REG_PC => R_REG_PC,
RST_LOAD => RST_LOAD,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
MACH_RST_PROT => MACH_RST_PROT,
MACH_RST_MPX => MACH_RST_MPX,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
GM_WM_DETECTED => GM_WM_DETECTED,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MPX_SHARE_REQ => MPX_SHARE_REQ,
MPX_INTERRUPT => MPX_INTERRUPT,
CS_DECODE_X001 => CS_DECODE_X001,
CLOCK_OFF => CLOCK_OFF,
CONNECT => CONNECT,
P_8F_DETECTED => P_8F_DETECTED,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALU_CHK_LCH => ALU_CHK_LCH,
ALLOW_PROTECT => ALLOW_PROTECT,
ALLOW_PC_SALS => ALLOW_PC_SALS,
USE_R => USE_R,
USE_BASIC_CA_DECODER => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SEL => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STORAGE => MAIN_STORAGE,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WRITE_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
GT_MAN_SET_MN => GT_MAN_SET_MN,
MPX_ROS_LCH => MPX_ROS_LCH,
CTRL_REG_RST => CTRL_REG_RST,
CK_SAL_P_BIT_TO_MPX => CK_SAL_P_BIT_TO_MPX,
CHANNEL_RD_CALL => CHANNEL_RD_CALL,
GTD_CA_BITS => GATED_CA_BITS,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_MAIN_MEMORY => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
SELECT_CPU_BUMP => SELECT_CPU_BUMP,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
CPU_RD_PWR => CPU_RD_PWR,
LOAD_IND => LOAD_IND,
SET_FW => SET_FW,
MACH_RST_SW => MACH_RST_SW,
LOAD_REQ_LCH => LOAD_REQ_LCH,
USE_GR_OR_HR => USE_GR_OR_HR,
SX_CHAIN_PULSE_1 => SX_CHAIN_PULSE_1,
CHK_RST_SW => CHK_RST_SW,
DIAGNOSTIC_SW => DIAGNOSTIC_SW,
MAN_DSPLY_GUV_HUV => MAN_DSPLY_GUV_HUV,
HSMPX_TRAP => HSMPX_TRAP,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SX_1_R_W_CTRL => SX_1_R_W_CTRL,
SX_2_R_W_CTRL => SX_2_R_W_CTRL,
SX_2_BUMP_SW_GT => SX_2_BUMP_SW_GT,
SEL_WR_CALL => SEL_WR_CALL,
SEL_AUX_WR_CALL => SEL_AUX_WR_CALL,
SEL_AUX_RD_CALL => SEL_AUX_RD_CALL,
SEL_T1 => SEL_T1,
SEL_T4 => SEL_T4,
SEL_CONV_OSC => SEL_CONV_OSC,
SEL_BASIC_CLOCK_OFF => SEL_BASIC_CLOCK_OFF,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_CHNL_DATA_XFER => SEL_CHNL_DATA_XFER,
SEL_ROS_REQ => SEL_ROS_REQ,
SEL_READ_CALL => SEL_READ_CALL,
SEL_RD_WR_CTRL => SEL_RD_WR_CTRL,
SEL_RD_CALL_TO_STP => SEL_RD_CALL_TO_STP,
SEL_CHNL_CPU_CLOCK_STOP => SEL_CHNL_CPU_CLOCK_STOP,
RST_SEL_CHNL_DIAG_LCHS => RST_SEL_CHNL_DIAG_LCHS,
SEL_CC_ROS_REQ => SEL_CC_ROS_REQ,
SX1_INTERRUPT => SX1_INTERRUPT,
SX2_INTERRUPT => SX2_INTERRUPT,
SX_1_GATE => SX_1_GATE,
SX_2_GATE => SX_2_GATE,
CLOCK_ON => CLOCK_ON,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_START => CLOCK_START,
CLOCK_START_LCH => CLOCK_START_LCH,
-- UDC1 Debug stuff
DEBUG => DEBUG,
-- End of Debug stuff
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P4 => P4,
CLK => CLK
);
IND_SALS <= sSALS;
USE_MAN_DECODER_PWR <= sUSE_MAN_DECODER_PWR;
secondBit: entity udc2 (FMD) port map (
SALS => sSALS,
CTRL => CTRL,
A_BUS1 => A_BUS,
B_BUS => B_BUS,
Z_BUS => Z_BUS,
E_BUS => E_SW,
M_ASSM_BUS => M_ASSM_BUS2,
N_ASSM_BUS => N_ASSM_BUS2,
S => S,
R => R,
MN => MN,
Sw_Slow => SwSlow,
CLOCK_START => CLOCK_START,
MACH_RST_3 => MACH_RST_3,
MACH_RST_6 => MACH_RST_6,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
CLOCK_IN => clk,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => P_CONV_OSC,
M_CONV_OSC_2 => M_CONV_OSC_2,
CLOCK_ON => CLOCK_ON,
LAMP_TEST => SW_LAMP_TEST,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
DIAG_SW => DIAGNOSTIC_SW,
CHK_SW_PROC_SW => SW_CHK_SW_PROCESS,
ROS_SCAN => SW_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
CARRY_0_LATCHED => CARRY_0_LCHD,
CARRY_1_LCHD => CARRY_1_LCHD,
ALU_CHK => ALU_CHK,
NTRUE => NTRUE,
COMPLEMENT => COMPLEMENT,
P_CTRL_N => CTRL_N,
N_CTRL_LM => N_CTRL_LM,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
CPU_RD_PWR => CPU_RD_PWR,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHANNEL_RD_CALL,
XH => XH,
XL => XL,
XXH => XXH,
MAN_STOR_PWR => MANUAL_STORE,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW.S_SEL,
CTRL_REG_RST => CTRL_REG_RST,
CLOCK_OFF => CLOCK_OFF,
A_REG_PC => A_REG_PC,
Z0_BUS_0 => Z0_BUS_0,
Z_0 => Z_0,
P_CONNECT => CONNECT,
N_CTRL_N => N_CTRL_N,
ALU_CHK_LCH => ALU_CHK_LCH,
MN_PC => MN_PC,
SET_IND_ROSAR => SET_IND_ROSAR,
N_STACK_MEMORY_SELECT => N_STACK_MEM_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN, -- from 05B
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STORAGE_CP,
N_STACK_MEM_SELECT => N_STACK_MEM_SELECT,
SEL_CPU_BUMP => SELECT_CPU_BUMP,
PROTECT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROT_LOC_SEL_CHNL,
WX_CHK => WX_CHK,
EARLY_M0 => EARLY_M_REG_0,
ODD => ODD,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
STATUS_IN_LCHD => STATUS_IN_LCHD,
STORE_R => STORE_R,
SALS_PC => SAL_PC,
R_REG_PC => R_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
MEM_WRAP => MEM_WRAP,
USE_R => USE_R,
USE_MAIN_MEM => USE_MAIN_MEMORY,
USE_LOC_MAIN_MEM => USE_LOCAL_MAIN_MEMORY,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
SEL_DATA_READY => SEL_DATA_READY,
N1401_MODE => N1401_MODE,
STG_MEM_SELECT => STG_MEM_SEL,
MEM_PROT_REQUEST => MEM_PROTECT_REQUEST,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAIN_STG => MAIN_STORAGE,
MACH_RST_SW => MACH_RST_SW,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
MACH_CHK_RST => MACH_CHK_RST,
MACH_CHK_PULSE => MACH_CHK_PULSE,
LOCAL_STG => LOCAL_STORAGE_CP,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
DATA_READY => DATA_READY,
CTRL_REG_CHK => CTRL_REG_CHK,
CPU_WR_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
ALLOW_WRITE_DLYD => ALLOW_WRITE_DLYD,
ALLOW_WRITE => ALLOW_WRITE,
T_REQUEST => T_REQUEST,
P_8F_DETECTED => P_8F_DETECTED,
CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
GATED_CA_BITS => GATED_CA_BITS,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
FIRST_MACH_CHK => FIRST_MACH_CHK,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_2B => MACH_RST_2B,
BASIC_CS0 => BASIC_CS0,
ANY_MACH_CHK => ANY_MACH_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
CARRY_0 => CARRY_0,
ALLOW_PROTECT => ALLOW_PROTECT,
CS_DECODE_X001 => CS_DECODE_X001,
DECIMAL => DECIMAL,
M_REG_0 => M_REG_0,
MACH_RST_PROT => MACH_RST_PROT,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
MPX_ROS_LCH => MPX_ROS_LCH,
FT7 => FT7,
FT6 => FT6,
FT5 => FT5,
FT2 => FT2,
FT0 => FT0,
FT3 => FT3,
MPX_INTERRUPT => MPX_INTERRUPT,
MPX_METERING_IN => MPX_METERING_IN,
STORE_BITS => STORE_BITS,
READ_ECHO_1 => READ_ECHO_1,
READ_ECHO_2 => READ_ECHO_2,
WRITE_ECHO_1 => WRITE_ECHO_1,
WRITE_ECHO_2 => WRITE_ECHO_2,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
MACH_RST_MPX => MACH_RST_MPX,
SET_FW => SET_FW,
MPX_SHARE_REQ => MPX_SHARE_REQ,
LOAD_IND => LOAD_IND,
CLOCK_OUT => CLOCK_OUT,
METERING_OUT => METERING_OUT,
-- Signals from UDC3
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD, -- from 12D
GK => GK, -- from 11B
HK => HK, -- from 13B
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SEL_CHNL_CHK => SEL_CHNL_CHK,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
GT_HSMPX_INTO_R_REG => '0',
DR_CORR_P_BIT => '0',
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
-- Indicators
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
IND_CHK_A_REG => IND_CHK_A_REG,
IND_CHK_B_REG => IND_CHK_B_REG,
IND_CHK_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_CHK_CTRL_REG => IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS => IND_CHK_ROS_SALS,
IND_CHK_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_CHK_STOR_DATA => IND_CHK_STOR_DATA,
IND_CHK_ALU => IND_CHK_ALU,
-- Selector & Mpx channels
MPX_BUS_O => sMPX_BUS_O,
MPX_BUS_I => MPX_BUS_I,
MPX_TAGS_O => MPX_TAGS_O,
MPX_TAGS_I => MPX_TAGS_I,
-- UDC2 Debug stuff
-- DEBUG => DEBUG,
SEL_T1 => SEL_T1,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
SEL_T3 => SEL_T3,
Clk => Clk
);
M_CONV_OSC <= sM_CONV_OSC;
-- Temporary substitutes for UDC3
SEL_CONV_OSC <= P_CONV_OSC; -- 12A
SEL_BASIC_CLOCK_OFF <= not CLOCK_ON and not CLOCK_START_LCH; -- 12A
-- Combining buses
M_ASSM_BUS2 <= M_ASSM_BUS1 or M_ASSM_BUS3;
N_ASSM_BUS2 <= N_ASSM_BUS1 or N_ASSM_BUS3;
end FMD;
| gpl-3.0 | 8a3ee9bfa0d13dbac9348dea366701fd | 0.630415 | 2.392364 | false | false | false | false |
chastell/art-decomp | kiss/tma_nov.vhd | 1 | 6,129 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_nov;
architecture behaviour of tma_nov is
constant I0: std_logic_vector(4 downto 0) := "11110";
constant T1: std_logic_vector(4 downto 0) := "00000";
constant T3: std_logic_vector(4 downto 0) := "00001";
constant T4: std_logic_vector(4 downto 0) := "01101";
constant T5: std_logic_vector(4 downto 0) := "00101";
constant T6: std_logic_vector(4 downto 0) := "11010";
constant T7: std_logic_vector(4 downto 0) := "11111";
constant T8: std_logic_vector(4 downto 0) := "11100";
constant T9: std_logic_vector(4 downto 0) := "10011";
constant T2: std_logic_vector(4 downto 0) := "10100";
constant R1: std_logic_vector(4 downto 0) := "00100";
constant R2: std_logic_vector(4 downto 0) := "01011";
constant R3: std_logic_vector(4 downto 0) := "00011";
constant R4: std_logic_vector(4 downto 0) := "00010";
constant R6: std_logic_vector(4 downto 0) := "00111";
constant R7: std_logic_vector(4 downto 0) := "11011";
constant R8: std_logic_vector(4 downto 0) := "11000";
constant R5: std_logic_vector(4 downto 0) := "00110";
constant I2: std_logic_vector(4 downto 0) := "01000";
constant I1: std_logic_vector(4 downto 0) := "01001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when I0 =>
if std_match(input, "11110--") then next_state <= T1; output <= "000000";
elsif std_match(input, "101-1--") then next_state <= R1; output <= "000000";
end if;
when T1 =>
if std_match(input, "1110---") then next_state <= T3; output <= "100000";
elsif std_match(input, "100----") then next_state <= T9; output <= "100000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "100000";
end if;
when T3 =>
if std_match(input, "111----") then next_state <= T4; output <= "110000";
elsif std_match(input, "100----") then next_state <= T9; output <= "110000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "110000";
end if;
when T4 =>
if std_match(input, "111----") then next_state <= T5; output <= "001000";
elsif std_match(input, "100----") then next_state <= T9; output <= "001000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "001000";
end if;
when T5 =>
if std_match(input, "111-0--") then next_state <= T6; output <= "101000";
elsif std_match(input, "100----") then next_state <= T9; output <= "101000";
elsif std_match(input, "101-1--") then next_state <= T9; output <= "101000";
end if;
when T6 =>
if std_match(input, "101-0--") then next_state <= T7; output <= "011000";
elsif std_match(input, "101-1--") then next_state <= T8; output <= "011000";
elsif std_match(input, "100----") then next_state <= T9; output <= "011000";
end if;
when T7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111000";
end if;
when T8 =>
if std_match(input, "10-----") then next_state <= I2; output <= "000100";
end if;
when T9 =>
if std_match(input, "101-0--") then next_state <= T2; output <= "100100";
elsif std_match(input, "100----") then next_state <= T2; output <= "100100";
end if;
when T2 =>
if std_match(input, "10-----") then next_state <= T8; output <= "010100";
end if;
when R1 =>
if std_match(input, "101-1--") then next_state <= R2; output <= "100010";
elsif std_match(input, "100----") then next_state <= I1; output <= "100010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "100010";
end if;
when R2 =>
if std_match(input, "101-1--") then next_state <= R3; output <= "010010";
elsif std_match(input, "100----") then next_state <= I1; output <= "010010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "010010";
end if;
when R3 =>
if std_match(input, "101-1--") then next_state <= R4; output <= "110010";
elsif std_match(input, "101-0-0") then next_state <= R6; output <= "110010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "110010";
elsif std_match(input, "100----") then next_state <= R5; output <= "110010";
end if;
when R4 =>
if std_match(input, "101-0-0") then next_state <= R6; output <= "001010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "001010";
elsif std_match(input, "100----") then next_state <= R5; output <= "001010";
end if;
when R6 =>
if std_match(input, "101-0--") then next_state <= R7; output <= "011010";
elsif std_match(input, "101-1--") then next_state <= R5; output <= "011010";
elsif std_match(input, "100----") then next_state <= R5; output <= "011010";
end if;
when R7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111010";
end if;
when R8 =>
if std_match(input, "10-----") then next_state <= R5; output <= "000110";
end if;
when R5 =>
if std_match(input, "101----") then next_state <= I2; output <= "100110";
elsif std_match(input, "100----") then next_state <= I1; output <= "100110";
end if;
when I2 =>
if std_match(input, "-------") then next_state <= I0; output <= "000001";
end if;
when I1 =>
if std_match(input, "111-0--") then next_state <= I0; output <= "010111";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 732e528790e437f94bbc112839ba2d12 | 0.564856 | 3.300485 | false | false | false | false |
chastell/art-decomp | kiss/beecount_jed.vhd | 1 | 3,518 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity beecount_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(3 downto 0)
);
end beecount_jed;
architecture behaviour of beecount_jed is
constant st0: std_logic_vector(2 downto 0) := "100";
constant st1: std_logic_vector(2 downto 0) := "101";
constant st4: std_logic_vector(2 downto 0) := "110";
constant st2: std_logic_vector(2 downto 0) := "001";
constant st3: std_logic_vector(2 downto 0) := "010";
constant st5: std_logic_vector(2 downto 0) := "000";
constant st6: std_logic_vector(2 downto 0) := "111";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "000") then next_state <= st0; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st1 =>
if std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "0-0") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st2 =>
if std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st3 =>
if std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "0110";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st4 =>
if std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "-00") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st5 =>
if std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st6 =>
if std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "1001";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when others => next_state <= "---"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | 92cb20114e47f708affe7e0f17125e1d | 0.58556 | 3.309501 | false | false | false | false |
chastell/art-decomp | kiss/s208_hot.vhd | 1 | 16,820 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s208_hot is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s208_hot;
architecture behaviour of s208_hot is
constant s11111111: std_logic_vector(17 downto 0) := "100000000000000000";
constant s00000000: std_logic_vector(17 downto 0) := "010000000000000000";
constant s00010000: std_logic_vector(17 downto 0) := "001000000000000000";
constant s00100000: std_logic_vector(17 downto 0) := "000100000000000000";
constant s00110000: std_logic_vector(17 downto 0) := "000010000000000000";
constant s01000000: std_logic_vector(17 downto 0) := "000001000000000000";
constant s01010000: std_logic_vector(17 downto 0) := "000000100000000000";
constant s01100000: std_logic_vector(17 downto 0) := "000000010000000000";
constant s01110000: std_logic_vector(17 downto 0) := "000000001000000000";
constant s10000000: std_logic_vector(17 downto 0) := "000000000100000000";
constant s10010000: std_logic_vector(17 downto 0) := "000000000010000000";
constant s10100000: std_logic_vector(17 downto 0) := "000000000001000000";
constant s10110000: std_logic_vector(17 downto 0) := "000000000000100000";
constant s11000000: std_logic_vector(17 downto 0) := "000000000000010000";
constant s11010000: std_logic_vector(17 downto 0) := "000000000000001000";
constant s11100000: std_logic_vector(17 downto 0) := "000000000000000100";
constant s11110000: std_logic_vector(17 downto 0) := "000000000000000010";
constant s00000001: std_logic_vector(17 downto 0) := "000000000000000001";
signal current_state, next_state: std_logic_vector(17 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------"; output <= "--";
case current_state is
when s11111111 =>
if std_match(input, "0--------01") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------01") then next_state <= s00000000; output <= "11";
elsif std_match(input, "0--------11") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------11") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------10") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------00") then next_state <= s00000000; output <= "10";
elsif std_match(input, "0---------0") then next_state <= s00000000; output <= "10";
end if;
when s00000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10--------0") then next_state <= s00010000; output <= "00";
end if;
when s00010000 =>
if std_match(input, "10-------00") then next_state <= s00100000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s00100000; output <= "01";
elsif std_match(input, "10-------1-") then next_state <= s00100000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
end if;
when s00100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s00110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s00110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s00110000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s00110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s01000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01000000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s01000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-----1--0") then next_state <= s01010000; output <= "01";
elsif std_match(input, "10-----0--0") then next_state <= s01010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01010000; output <= "01";
end if;
when s01010000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s01100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01100000; output <= "01";
end if;
when s01100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1-0") then next_state <= s01110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s01110000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01110000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s01110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s10000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10----0---0") then next_state <= s10010000; output <= "00";
elsif std_match(input, "10----1---0") then next_state <= s10010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s10010000; output <= "01";
elsif std_match(input, "11----1---0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11----0---0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s10010000 =>
if std_match(input, "10--------1") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10100000; output <= "00";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s10100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s10110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s10110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s10110000; output <= "01";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when s10110000 =>
if std_match(input, "10--------1") then next_state <= s11000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11000000; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s11000000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s11000000 =>
if std_match(input, "10-----0--0") then next_state <= s11010000; output <= "00";
elsif std_match(input, "10-----1--0") then next_state <= s11010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s11010000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s11010000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s11100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s11100000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01--------1") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s11100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10------1--") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-1") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s11110000; output <= "00";
end if;
when s11110000 =>
if std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------01") then next_state <= s00000001; output <= "00";
elsif std_match(input, "-0-------00") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------11") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------11") then next_state <= s00000001; output <= "00";
elsif std_match(input, "00-------10") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s00000001; output <= "01";
end if;
when s00000001 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10---1----0") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10---0----0") then next_state <= s00010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "11---0----0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11---1----0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when others => next_state <= "------------------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | f5fded79f212a6ff32683fc284d6ee5b | 0.571284 | 3.56961 | false | false | false | false |
Subsets and Splits