repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
freecores/gamepads | gcpad/rtl/vhdl/gcpad_sampler.vhd | 1 | 5,636 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_sampler.vhd,v 1.3 2004-10-09 00:33:12 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gcpad_sampler is
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Control Interface ------------------------------------------------------
wrap_sample_i : in boolean;
sync_sample_i : in boolean;
sample_underflow_o : out boolean;
-- Pad Interface ----------------------------------------------------------
pad_data_i : in std_logic;
pad_data_o : out std_logic;
sample_o : out std_logic
);
end gcpad_sampler;
use work.gcpad_pack.all;
architecture rtl of gcpad_sampler is
signal pad_data_sync_q : std_logic_vector(1 downto 0);
signal pad_data_s : std_logic;
constant cnt_sample_high_c : natural := clocks_per_1us_g * 4 - 1;
subtype cnt_sample_t is natural range 0 to cnt_sample_high_c;
signal cnt_zeros_q : cnt_sample_t;
signal cnt_ones_q : cnt_sample_t;
signal sample_underflow_q : boolean;
signal more_ones_q : boolean;
begin
seq: process (reset_i, clk_i)
variable dec_timeout_v : boolean;
begin
if reset_i = reset_level_g then
cnt_zeros_q <= cnt_sample_high_c;
cnt_ones_q <= cnt_sample_high_c;
more_ones_q <= false;
sample_underflow_q <= false;
pad_data_sync_q <= (others => '1');
elsif clk_i'event and clk_i = '1' then
-- synchronizer for pad data
pad_data_sync_q(0) <= pad_data_i;
pad_data_sync_q(1) <= pad_data_sync_q(0);
-- sample counter
dec_timeout_v := false;
if sync_sample_i then
-- explicit preload
cnt_zeros_q <= cnt_sample_high_c;
cnt_ones_q <= cnt_sample_high_c;
else
if cnt_zeros_q = 0 then
if wrap_sample_i then
cnt_zeros_q <= cnt_sample_high_c;
end if;
dec_timeout_v := true;
elsif pad_data_s = '0' then
cnt_zeros_q <= cnt_zeros_q - 1;
end if;
if cnt_ones_q = 0 then
if wrap_sample_i then
cnt_ones_q <= cnt_sample_high_c;
end if;
dec_timeout_v := true;
elsif pad_data_s /= '0' then
cnt_ones_q <= cnt_ones_q - 1;
end if;
end if;
if cnt_ones_q < cnt_zeros_q then
more_ones_q <= true;
else
more_ones_q <= false;
end if;
-- detect sample underflow
sample_underflow_q <= dec_timeout_v;
end if;
end process seq;
pad_data_s <= pad_data_sync_q(1);
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pad_data_o <= pad_data_s;
sample_o <= '1'
when more_ones_q else
'0';
sample_underflow_o <= sample_underflow_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/10/08 21:35:08 arniml
-- comments
--
-------------------------------------------------------------------------------
| gpl-2.0 | 5b8707a72fb2bf29b9261e0f23a6fe3b | 0.552165 | 4.054676 | false | false | false | false |
eiglss/VHDL | UART/shiftRegister.vhd | 1 | 1,903 | --******************************************************************************
-- @TITRE : shiftRegister.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shiftRegister IS
GENERIC(length : POSITIVE := 8;
rightNotLeft : BOOLEAN := TRUE
);
PORT(clk, aNRst : IN STD_LOGIC;
shEn, ldEn : IN STD_LOGIC;
serialIn : IN STD_LOGIC;
datIn : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0);
datOut : OUT STD_LOGIC_VECTOR(length-1 DOWNTO 0);
serialOut : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE behavioral OF shiftRegister IS
SIGNAL shReg : STD_LOGIC_VECTOR(length-1 DOWNTO 0);
BEGIN
datOut <= shReg;
PROCESS(clk, aNRst) IS
BEGIN
IF aNRst = '0' THEN
shReg <= (OTHERS => '0');
ELSIF RISING_EDGE(clk) THEN
IF ldEn = '1' THEN
shReg <= datIn;
ELSIF shEn = '1' THEN
IF rightNotLeft THEN
shReg(length-1) <= serialIn;
shReg(length-2 DOWNTO 0) <= shReg(length-1 DOWNTO 1);
ELSE
shReg(0) <= serialIn;
shReg(length-1 DOWNTO 1) <= shReg(length-2 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS;
sreialOutRight_gen : IF rightNotLeft GENERATE
serialOut <= shReg(0);
END GENERATE;
sreialOutLeft_gen : IF NOT rightNotLeft GENERATE
serialOut <= shReg(length-1);
END GENERATE;
END ARCHITECTURE behavioral;
| mit | 927ad071dd45157d541807a669807ec0 | 0.476616 | 4.394919 | false | false | false | false |
freecores/gamepads | snespad/rtl/vhdl/snespad_ctrl.vhd | 1 | 6,441 | -------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad_ctrl.vhd,v 1.3 2005-09-15 17:28:17 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity snespad_ctrl is
generic (
reset_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_o : out boolean;
-- Control Interface ------------------------------------------------------
shift_buttons_o : out boolean;
save_buttons_o : out boolean;
-- Pad Interface ----------------------------------------------------------
pad_clk_o : out std_logic;
pad_latch_o : out std_logic
);
end snespad_ctrl;
use work.snespad_pack.all;
architecture rtl of snespad_ctrl is
subtype clocks_per_6us_t is natural range 0 to clocks_per_6us_g;
type state_t is (IDLE,
IDLE2,
LATCH,
READ_PAD);
signal pad_latch_q,
pad_latch_s : std_logic;
signal pad_clk_q,
pad_clk_s : std_logic;
signal num_buttons_read_q : num_buttons_read_t;
signal clocks_per_6us_q : clocks_per_6us_t;
signal state_q,
state_s : state_t;
signal clk_en_s : boolean;
signal shift_buttons_s : boolean;
begin
-- pragma translate_off
-----------------------------------------------------------------------------
-- Check generics
-----------------------------------------------------------------------------
assert (reset_level_g = 0) or (reset_level_g = 1)
report "reset_level_g must be either 0 or 1!"
severity failure;
assert clocks_per_6us_g > 1
report "clocks_per_6us_g must be at least 2!"
severity failure;
-- pragma translate_on
seq: process (reset_i, clk_i)
begin
if reset_i = reset_level_g then
pad_latch_q <= '1';
pad_clk_q <= '1';
num_buttons_read_q <= num_buttons_c-1;
clocks_per_6us_q <= 0;
state_q <= IDLE;
elsif clk_i'event and clk_i = '1' then
if clk_en_s then
clocks_per_6us_q <= 0;
else
clocks_per_6us_q <= clocks_per_6us_q + 1;
end if;
if clk_en_s and shift_buttons_s then
if num_buttons_read_q = 0 then
num_buttons_read_q <= num_buttons_c-1;
else
num_buttons_read_q <= num_buttons_read_q - 1;
end if;
end if;
if clk_en_s then
state_q <= state_s;
end if;
pad_clk_q <= pad_clk_s;
pad_latch_q <= pad_latch_s;
end if;
end process;
clk_en_s <= clocks_per_6us_q = clocks_per_6us_g-1;
fsm: process (state_q,
num_buttons_read_q)
begin
-- default assignments
pad_clk_s <= '1';
pad_latch_s <= '1';
shift_buttons_s <= false;
save_buttons_o <= false;
state_s <= IDLE;
case state_q is
when IDLE =>
save_buttons_o <= true;
state_s <= IDLE2;
when IDLE2 =>
state_s <= LATCH;
when LATCH =>
pad_latch_s <= '0';
state_s <= READ_PAD;
when READ_PAD =>
pad_latch_s <= '0';
-- set clock low
-- pad data will be read at end of 6us cycle
pad_clk_s <= '0';
shift_buttons_s <= true;
if num_buttons_read_q = 0 then
-- return to IDLE after last button bit has been read
state_s <= IDLE;
else
state_s <= LATCH;
end if;
when others =>
null;
end case;
end process fsm;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
clk_en_o <= clk_en_s;
shift_buttons_o <= shift_buttons_s;
pad_clk_o <= pad_clk_q;
pad_latch_o <= pad_latch_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2005/07/03 21:36:00 arniml
-- removed obsolete state CLOCK
--
-- Revision 1.1 2004/10/05 17:01:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | ea37cb381eab44bfc5a382b8fa623847 | 0.539668 | 3.983302 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/CTRL_InAB_INPUT/CTRL_InAB_INPUT_VHDL.vhd | 6 | 28,652 | -- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; | gpl-2.0 | e58eb244051bfb872ee564e81038fc1e | 0.46105 | 2.820356 | false | false | false | false |
jrrk2/greth_library | greth_library/gnsslib/rf3b/axi_rfctrl.vhd | 2 | 10,489 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief This file implements RF-controller entity axi_rfctrl.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief RF-front controller based on MAX2769 ICs.
--! @details This unit implements SPI interface with MAX2769 ICs
--! and interacts with the antenna control signals.
entity axi_rfctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
nrst : in std_logic;
clk : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
--! @name Synthezator's SPI interface signals:
--! @brief Connects to MAX2769 IC.
--! @{
outSCLK : out std_logic;
outSDATA : out std_logic;
outCSn : out std_logic_vector(1 downto 0);
--! @}
--! @name Antenna control signals:
--! @brief RF front-end IO analog signals.
--! @{
inExtAntStat : in std_logic;
inExtAntDetect : in std_logic;
outExtAntEna : out std_logic;
outIntAntContr : out std_logic
--! @}
);
end;
architecture rtl of axi_rfctrl is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_RF_CONTROL,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type registers is record
bank_axi : nasti_slave_bank_type;
conf1 : std_logic_vector(27 downto 0);
conf2 : std_logic_vector(27 downto 0);
conf3 : std_logic_vector(27 downto 0);
pllconf : std_logic_vector(27 downto 0);
div : std_logic_vector(27 downto 0);
fdiv : std_logic_vector(27 downto 0);
strm : std_logic_vector(27 downto 0);
clkdiv : std_logic_vector(27 downto 0);
test1 : std_logic_vector(27 downto 0);
test2 : std_logic_vector(27 downto 0);
scale : std_logic_vector(31 downto 0);
load_run : std_ulogic;
select_spi : std_logic_vector(1 downto 0);
loading : std_ulogic;
ScaleCnt : std_logic_vector(31 downto 0);
SClkPosedge : std_ulogic;
SClkNegedge : std_ulogic;
SCLK : std_ulogic;
BitCnt : integer range 0 to 33;
CS : std_ulogic; --!! not inversed!!
WordSelector : std_logic_vector(8 downto 0);
SendWord : std_logic_vector(31 downto 0);
ExtAntEna : std_ulogic;
IntAntContr : std_ulogic;
end record;
signal r, rin : registers;
begin
comblogic : process(nrst, r, i_axi, i_glo_ld, i_gps_ld, inExtAntStat, inExtAntDetect)
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable v : registers;
variable readdata : std_logic_vector(31 downto 0);
variable wNewWord : std_ulogic;
begin
v := r;
v.load_run := '0';
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
-- read registers:
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := "0000" & r.conf1;
when 1 => tmp := "0000" & r.conf2;
when 2 => tmp := "0000" & r.conf3;
when 3 => tmp := "0000" & r.pllconf;
when 4 => tmp := "0000" & r.div;
when 5 => tmp := "0000" & r.fdiv;
when 6 => tmp := "0000" & r.strm;
when 7 => tmp := "0000" & r.clkdiv;
when 8 => tmp := "0000" & r.test1;
when 9 => tmp := "0000" & r.test2;
when 10 => tmp := r.scale;
when 11 =>
tmp(9 downto 0):= conv_std_logic_vector(r.BitCnt,6) & '0' & r.loading & i_glo_ld & i_gps_ld;
when 15 =>
tmp(5 downto 0) := inExtAntStat & inExtAntDetect & "00"& r.IntAntContr & r.ExtAntEna;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
-- write registers
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i_axi.w_data(32*(n+1)-1 downto 32*n);
wstrb := i_axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 0 => v.conf1 := tmp(27 downto 0);
when 1 => v.conf2 := tmp(27 downto 0);
when 2 => v.conf3 := tmp(27 downto 0);
when 3 => v.pllconf := tmp(27 downto 0);
when 4 => v.div := tmp(27 downto 0);
when 5 => v.fdiv := tmp(27 downto 0);
when 6 => v.strm := tmp(27 downto 0);
when 7 => v.clkdiv := tmp(27 downto 0);
when 8 => v.test1 := tmp(27 downto 0);
when 9 => v.test2 := tmp(27 downto 0);
when 10 =>
if tmp(31 downto 1) = zero32(31 downto 1) then
v.scale := conv_std_logic_vector(2,32);
else
v.scale := tmp;
end if;
when 11 =>
v.load_run := '1';
v.ScaleCnt := (others => '0');
v.BitCnt := 0;
if tmp = zero32 then
v.select_spi := "01";
elsif tmp = conv_std_logic_vector(1,32) then
v.select_spi := "10";
else
v.select_spi := "00";
end if;
when 15 =>
v.ExtAntEna := tmp(0);
v.IntAntContr := tmp(1);
when others =>
end case;
end if;
end loop;
end if;
-- loading procedure:
if((r.SClkNegedge='1') and (r.BitCnt=33)) then wNewWord := '1';
else wNewWord := '0'; end if;
if(r.load_run='1') then v.loading := '1';
elsif((wNewWord='1')and(r.WordSelector="000000000")) then v.loading := '0'; end if;
if((r.loading and r.SClkNegedge)='1') then v.ScaleCnt := (others => '0');
elsif(r.loading='1') then v.ScaleCnt := r.ScaleCnt+1; end if;
-- scaler pulse:
if((r.scale/=zero32)and(r.ScaleCnt=r.scale)) then v.SClkNegedge := '1';
else v.SClkNegedge := '0'; end if;
if((r.scale/=zero32)and(r.ScaleCnt=('0'& r.scale(31 downto 1)))) then v.SClkPosedge := '1';
else v.SClkPosedge := '0'; end if;
-- SCLK former:
if(r.SClkPosedge='1') then v.SCLK := '1';
elsif(r.SClkNegedge='1') then v.SCLK := '0'; end if;
-- Not inversed CS signal:
if((r.SClkNegedge='1')and(r.BitCnt=33)) then v.BitCnt := 0;
elsif(r.SClkNegedge='1') then v.BitCnt := r.BitCnt + 1; end if;
if((r.BitCnt=0)or((r.BitCnt=33))) then v.CS := '0';
else v.CS := '1'; end if;
-- Word multiplexer:
if(r.load_run='1') then v.WordSelector := "000000001";
elsif(wNewWord='1') then v.WordSelector := r.WordSelector(7 downto 0) & '0'; end if;
if(r.load_run='1') then v.SendWord := r.conf1 & "0000";
elsif((wNewWord='1')and(r.WordSelector(0)='1')) then v.SendWord := r.conf2 & "0001";
elsif((wNewWord='1')and(r.WordSelector(1)='1')) then v.SendWord := r.conf3 & "0010";
elsif((wNewWord='1')and(r.WordSelector(2)='1')) then v.SendWord := r.pllconf & "0011";
elsif((wNewWord='1')and(r.WordSelector(3)='1')) then v.SendWord := r.div & "0100";
elsif((wNewWord='1')and(r.WordSelector(4)='1')) then v.SendWord := r.fdiv & "0101";
elsif((wNewWord='1')and(r.WordSelector(5)='1')) then v.SendWord := r.strm & "0110";
elsif((wNewWord='1')and(r.WordSelector(6)='1')) then v.SendWord := r.clkdiv & "0111";
elsif((wNewWord='1')and(r.WordSelector(7)='1')) then v.SendWord := r.test1 & "1000";
elsif((wNewWord='1')and(r.WordSelector(8)='1')) then v.SendWord := r.test2 & "1001";
elsif((r.SClkNegedge='1')and(r.BitCnt/=0)and(r.BitCnt/=33)) then v.SendWord := r.SendWord(30 downto 0)&'0'; end if;
-- reset operation
if nrst = '0' then
v.bank_axi := NASTI_SLAVE_BANK_RESET;
v.load_run := '0';
v.conf1 := (others => '0');
v.conf2 := (others => '0');
v.conf3 := (others => '0');
v.pllconf := (others => '0');
v.div := (others => '0');
v.fdiv := (others => '0');
v.strm := (others => '0');
v.clkdiv := (others => '0');
v.test1 := (others => '0');
v.test2 := (others => '0');
v.scale := (others => '0');
v.SCLK := '0';
v.BitCnt := 0;
v.CS := '0';
v.select_spi := (others => '0');
v.ExtAntEna := '0';
v.SendWord := (others=>'0');
v.loading := '0';
v.ScaleCnt := (others => '0');
v.WordSelector := (others => '0');
v.IntAntContr := '0';
end if;
rin <= v;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
end process;
o_cfg <= xconfig;
outSCLK <= r.SCLK;
outCSn(0) <= not(r.CS and r.select_spi(0));
outCSn(1) <= not(r.CS and r.select_spi(1));
outSDATA <= r.SendWord(31);
outExtAntEna <= r.ExtAntEna;
outIntAntContr <= r.IntAntContr;
-- registers:
regs : process(clk, nrst) begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 870d9f749a725349c6f04e0d72b37023 | 0.527886 | 3.353261 | false | false | false | false |
freecores/gamepads | gcpad/bench/vhdl/gcpad_mod.vhd | 1 | 6,076 | -------------------------------------------------------------------------------
--
-- A testbench model for the
-- GCpad controller core
--
-- $Id: gcpad_mod.vhd,v 1.3 2004-10-10 20:12:06 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gcpad_mod is
generic (
clocks_per_1us_g : natural := 2
);
port (
clk_i : in std_logic;
pad_data_io : inout std_logic;
rx_data_i : in std_logic_vector(63 downto 0)
);
end gcpad_mod;
architecture behav of gcpad_mod is
-----------------------------------------------------------------------------
-- Procedure wait_n_us
--
-- Purpose:
-- Waits for the given number of clk_i cycles.
--
procedure wait_n_us(clocks : in natural) is
begin
wait until clk_i = '0';
for i in 1 to clocks loop
wait until clk_i = '1';
wait until clk_i = '0';
end loop;
end wait_n_us;
--
-----------------------------------------------------------------------------
signal time_cnt_q : natural;
signal timeout_s : boolean;
begin
-----------------------------------------------------------------------------
-- Process timeout
--
-- Purpose:
-- Detects a timeout on incoming pad data stream after 5 us of
-- inactivity. Resynchronizes upon falling edge of pad_data_io.
--
timeout: process (clk_i, pad_data_io)
begin
if pad_data_io = '0' then
timeout_s <= false;
time_cnt_q <= 0;
elsif clk_i'event and clk_i = '1' then
time_cnt_q <= time_cnt_q + 1;
if time_cnt_q > 5 * clocks_per_1us_g then
timeout_s <= true;
else
timeout_s <= false;
end if;
end if;
end process timeout;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process model
--
-- Purpose:
-- Simple model for the functionality of a GC controller pad.
--
model: process
procedure send_packet(packet : in std_logic_vector) is
variable time_low_v, time_high_v : time;
begin
for i in packet'high downto 0 loop
if packet(i) = '0' then
time_low_v := 3 us;
time_high_v := 1 us;
else
time_low_v := 1 us;
time_high_v := 3 us;
end if;
pad_data_io <= '0';
wait for time_low_v;
pad_data_io <= 'H';
wait for time_high_v;
end loop;
end send_packet;
variable command_v : std_logic_vector(24 downto 0);
constant id_c : std_logic_vector(23 downto 0) := "000010010000000000000000";
begin
loop
command_v := (others => '1');
pad_data_io <= 'Z';
-------------------------------------------------------------------------
-- Step 1:
-- Receive command and associated data.
--
wait until pad_data_io = '0';
wait for 1 ns;
for i in 24 downto 0 loop
-- skip rest if timeout occured
if not timeout_s then
wait_n_us(2 * clocks_per_1us_g);
command_v(i) := pad_data_io;
if pad_data_io = '0' then
wait until pad_data_io /= '0';
end if;
-- wait for high -> low edge
wait until (pad_data_io = '0') or timeout_s;
end if;
wait for 1 ns;
end loop;
-------------------------------------------------------------------------
-- Detect command and send response
--
case command_v(24 downto 17) is
-- get ID
when "00000000" =>
wait_n_us(5 * clocks_per_1us_g);
send_packet(id_c);
send_packet("1");
-- poll status
when "0H000000" =>
wait_n_us(5 * clocks_per_1us_g);
send_packet(rx_data_i);
send_packet("1");
when others =>
null;
end case;
end loop;
end process model;
--
-----------------------------------------------------------------------------
end behav;
| gpl-2.0 | 4e027d26371f47fd43203494274e8921 | 0.537854 | 4.228253 | false | false | false | false |
jrrk2/greth_library | greth_library/gnsslib/types_gnss.vhd | 2 | 10,029 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Components declaration of the types_gnss package..
-----------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Math and data type transforamtion library
library commonlib;
use commonlib.types_common.all;
--! Leon3 technologies definition library
library techmap;
use techmap.gencomp.all; -- technology enumerator
--! AMBA AXI4 interconnect types
library ambalib;
use ambalib.types_amba4.all;
--! @brief Declaration of the GNSS modules visible outside of the package.
--! @details This package provides User's API and general configuration
--! of the library. User should directly include this package into
--! developing System with appropriate configuration values.
--! Configuraiton constants allow to enable/disable GNSS systems
--! separetedly, change channels configuration and flexibly tune
--! Fast Search Engines.
--!
--! This library provides several key features:
--! <ul>
--! <li>Control external RF-boards including loading synthezises</li>
--! <li>DSP of the input quantized samples such as correlation with
--! reference signals</li>
--! <li>Generate the raw measurements independenetly from the firmware</li>
--! <li>Implement hardware symbol synchronization</li>
--! <li>Hardware timescale counter for different systems</li>
--! <li>Implementing multi-path mitigation algrothims</li>
--! <li>Noise estimators</li>
--! <li>Multi-systems Fast Engines component</li>
--! </ul>
package types_gnss is
--! Maximal input bus width per complex component
constant ADC_BIT_WIDTH : integer := 2;
--! @brief Recording time interval for the FSE samples in msec.
--! @details Fast Search Engine processing is splitted on two phases:
--! recording samples, post-processing. Duration of the recording
--! phase defines memory requirements and maximal accumulation
--! interval. Each milliseconds requires 2 KB of the dual-port RAM.
constant CFG_FSE_MSEC_MAX : integer := 16;
--! Instantiated number of the GPS L1-CA channels. 0 is the valid value.
constant CFG_GNSS_GPS_L1CA_NUM : integer := 12;
--! Instantiated number of the Glonass L1-CA channels. 0 is the valid value.
constant CFG_GNSS_GLONASS_L1_NUM : integer := 12;
--! Instantiated number of the SBAS L1-CA channels. 0 is the valid value.
constant CFG_GNSS_SBAS_L1_NUM : integer := 2;
--! Instantiated number of the Galileo E1 channels. 0 is the valid value.
constant CFG_GNSS_GALILEO_E1_NUM : integer := 6;
--! @brief Total number of the instantiated channels
--! @details This value computes as a sum of all channels and is limited
--! only by address bus width that connects System Bus and GNSS
--! Top level.
--! @todo refine maximal possible number
constant CFG_GNSS_CHANNELS_TOTAL : integer := (CFG_GNSS_GPS_L1CA_NUM
+ CFG_GNSS_GLONASS_L1_NUM
+ CFG_GNSS_SBAS_L1_NUM
+ CFG_GNSS_GALILEO_E1_NUM);
--! Total number of GNSS timers. Shouldn't be modified by user.
constant CFG_GNSS_TIMERS_TOTAL : integer := 1;
--! Total number of GNSS noise estimators. Shouldn't be modified by user.
constant CFG_GNSS_NOISE : integer := 1;
--! Total number of Misc. modules. Shouldn't be modified by user.
constant CFG_GNSS_MISC : integer := 1;
--! Total number of GNSS modules connected to internal Core Simplified Bus
--! (SCB)
constant CFG_GNSS_MODULES_TOTAL : integer := CFG_GNSS_CHANNELS_TOTAL
+ CFG_GNSS_TIMERS_TOTAL
+ CFG_GNSS_NOISE
+ CFG_GNSS_MISC;
constant CFG_GNSS_DWORD_PER_MODULE : integer := 8;
constant CFG_GNSS_ADDR_WIDTH : integer := log2(CFG_GNSS_MODULES_TOTAL)+6;
constant MODULE_ID_MISC : integer := 0;
constant MODULE_ID_GLB_TIMER : integer := MODULE_ID_MISC+CFG_GNSS_MISC;
constant MODULE_ID_NOISE : integer := MODULE_ID_GLB_TIMER+CFG_GNSS_TIMERS_TOTAL;
constant MODULE_ID_CHN : integer := MODULE_ID_NOISE + CFG_GNSS_NOISE;
constant GEN_SYSTEM_GPSCA : integer := 0;
constant GEN_SYSTEM_GLOCA : integer := GEN_SYSTEM_GPSCA+1;
constant GEN_SYSTEM_SBAS : integer := GEN_SYSTEM_GLOCA+1;
constant GEN_SYSTEM_GALE1 : integer := GEN_SYSTEM_SBAS+1;
constant GEN_SYSTEM_TOTAL : integer := GEN_SYSTEM_GALE1+1;
type gnss_system_type is array (0 to GEN_SYSTEM_TOTAL) of integer;
constant fse_section_num : gnss_system_type := (GEN_SYSTEM_GLOCA => 1, others => 4);
constant CFG_GNSS_PRNROM_BUSWIDTH : integer := 5+8;--256 words(pilot+data) x 32 prn
-- Galileo E1-pilot overlay code:
constant CODE_CS25_1 : std_logic_vector(24 downto 0) := "0011100000001010110110010";
constant CODE_CS25_1I : std_logic_vector(24 downto 0) := "1100011111110101001001101";
type sys_parameter is array (0 to GEN_SYSTEM_TOTAL-1) of integer;
------------------------------------------------------------------------------
-- GNSS Engine, top level
type gns_in_type is record
nrst : std_ulogic;
clk_bus : std_ulogic;
axi : nasti_slave_in_type;
clk_adc : std_ulogic;
gps_I : std_logic_vector(1 downto 0);
gps_Q : std_logic_vector(1 downto 0);
glo_I : std_logic_vector(1 downto 0);
glo_Q : std_logic_vector(1 downto 0);
end record;
type gns_out_type is record
ms_pulse : std_logic;
pps : std_logic;
axi : nasti_slave_out_type;
cfg : nasti_slave_config_type;
end record;
component gnssengine is
generic
(
tech : integer range 0 to NTECH := 0;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#
);
port
(
i : in gns_in_type;
o : out gns_out_type
);
end component;
------------------------------------------------------------------------------
-- Fast Search Engine v.2 (GPS only, 32 channels)
type fse_in_type is record
nrst : std_logic;
clk_bus : std_logic;
clk_fse : std_logic;
axi : nasti_slave_in_type;
clk_adc : std_logic;
I : std_logic_vector(1 downto 0);
Q : std_logic_vector(1 downto 0);
ms_pulse : std_logic;
pps : std_logic;
test_mode : std_logic;
end record;
type fse_out_type is record
axi : nasti_slave_out_type;
cfg : nasti_slave_config_type;
end record;
component TopFSE is
generic
(
tech : integer := 0;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
sys : integer := GEN_SYSTEM_GPSCA
);
port (
i : in fse_in_type;
o : out fse_out_type
);
end component;
-- Use this stub-version when CFG_FSE_ENABLE == 0
component TopFSE_stub is
generic
(
tech : integer := 0;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
sys : integer := GEN_SYSTEM_GPSCA
);
port (
i : in fse_in_type;
o : out fse_out_type
);
end component;
--! @brief RF-front controller based on MAX2769 ICs.
--! @details This unit implements SPI interface with MAX2769 ICs
--! and interacts with the antenna control signals.
component axi_rfctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
nrst : in std_logic;
clk : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
--! @name Synthezator's SPI interface signals:
--! @brief Connects to MAX2769 IC.
--! @{
outSCLK : out std_logic;
outSDATA : out std_logic;
outCSn : out std_logic_vector(1 downto 0);
--! @}
--! @name Antenna control signals:
--! @brief RF front-end IO analog signals.
--! @{
inExtAntStat : in std_logic;
inExtAntDetect : in std_logic;
outExtAntEna : out std_logic;
outIntAntContr : out std_logic
--! @}
);
end component;
------------------------------------------------------------------------------
-- 3-axis STMicroelectronics Gyroscope SPI controller (4-wires mode)
component gyrospi is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
inInt1 : in std_ulogic;
inInt2 : in std_ulogic;
inSDI : in std_ulogic;
outSPC : out std_ulogic;
outSDO : out std_ulogic;
outCSn : out std_ulogic
);
end component;
------------------------------------------------------------------------------
-- 3-axis STMicroelectronics Accelerometer SPI controller (4-wires mode)
component accelspi is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
inInt1 : in std_ulogic;
inInt2 : in std_ulogic;
inSDI : in std_ulogic;
outSPC : out std_ulogic;
outSDO : out std_ulogic;
outCSn : out std_ulogic
);
end component;
end;
| bsd-2-clause | 1356cadad45bd383a54d40f6c9d390df | 0.582212 | 3.798864 | false | false | false | false |
akshayp/college-projects | vhdl/pong/LCD_Display.vhd | 1 | 8,793 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of Hex digit data values to display from hardware
-- (do not count ASCII character constants)
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use X"20" (ASCII space)
-- To dislay a "live" hex digit using values from hardware on LCD use the following:
-- make array element for that character location X"0" & 4-bit field from Hex_Display_Data
-- state machine sees X"0" in high 4-bits & grabs the next lower 4-bits from Hex_Display_Data input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to Hex_Display_Data input
-- To display less than 32 characters, terminate string with an entry of X"FE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is X"41"
-- *see LCD Controller's Datasheet for other graphics characters available
--
PORT(reset, clk_48Mhz : IN STD_LOGIC;
HexOut : IN STD_LOGIC_Vector(127 downto 0);
LCD_RS, LCD_E : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY LCD_Display;
ARCHITECTURE a OF LCD_Display IS
TYPE character_string IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, Print_String,
LINE2, RETURN_HOME, DROP_LCD_E, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL LCD_display_string : character_string;
-- Enter new ASCII hex data above for LCD Display
SIGNAL DATA_BUS_VALUE, Next_Char: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CHAR_COUNT: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL CLK_400HZ_Enable,LCD_RW_INT : STD_LOGIC;
SIGNAL Line1_chars, Line2_chars: STD_LOGIC_VECTOR(127 DOWNTO 0);
BEGIN
LCD_display_string <= (hexout(127 downto 120), hexout(119 downto 112), hexout(111 downto 104), hexout(103 downto 96), hexout(95 downto 88), hexout(87 downto 80), hexout(79 downto 72), hexout(71 downto 64), hexout(63 downto 56),
hexout(55 downto 48), hexout(47 downto 40), hexout(39 downto 32), hexout(31 downto 24), hexout(23 downto 16), hexout(15 downto 8), hexout(7 downto 0),X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20");
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW_INT = '0' ELSE "ZZZZZZZZ";
-- get next character in display string
Next_Char <= LCD_display_string(CONV_INTEGER(CHAR_COUNT));
LCD_RW <= LCD_RW_INT;
PROCESS
BEGIN
WAIT UNTIL CLK_48MHZ'EVENT AND CLK_48MHZ = '1';
IF RESET = '0' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0EA60" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
CLK_400HZ_Enable <= '0';
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (CLK_48MHZ, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '1';
ELSIF CLK_48MHZ'EVENT AND CLK_48MHZ = '1' THEN
IF CLK_400Hz_Enable = '1' THEN
-- State Machine to send commands and data to LCD DISPLAY
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= RESET2;
CHAR_COUNT <= "00000";
WHEN RESET2 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= RESET3;
WHEN RESET3 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"08";
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
-- Clear Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"01";
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"0C";
state <= DROP_LCD_E;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"06";
state <= DROP_LCD_E;
next_command <= Print_String;
-- Write ASCII hex character in first LCD character location
WHEN Print_String =>
state <= DROP_LCD_E;
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW_INT <= '0';
-- ASCII character to output
IF Next_Char(7 DOWNTO 4) /= X"0" THEN
DATA_BUS_VALUE <= Next_Char;
ELSE
-- Convert 4-bit value to an ASCII hex digit
IF Next_Char(3 DOWNTO 0) >9 THEN
-- ASCII A...F
DATA_BUS_VALUE <= X"4" & (Next_Char(3 DOWNTO 0)-9);
ELSE
-- ASCII 0...9
DATA_BUS_VALUE <= X"3" & Next_Char(3 DOWNTO 0);
END IF;
END IF;
state <= DROP_LCD_E;
-- Loop to send out 32 characters to LCD Display (16 by 2 lines)
IF (CHAR_COUNT < 31) AND (Next_Char /= X"FE") THEN
CHAR_COUNT <= CHAR_COUNT +1;
ELSE
CHAR_COUNT <= "00000";
END IF;
-- Jump to second line?
IF CHAR_COUNT = 15 THEN next_command <= line2;
-- Return to first line?
ELSIF (CHAR_COUNT = 31) OR (Next_Char = X"FE") THEN
next_command <= return_home;
ELSE next_command <= Print_String; END IF;
-- Set write address to line 2 character 1
WHEN LINE2 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"C0";
state <= DROP_LCD_E;
next_command <= Print_String;
-- Return write address to first character postion on line 1
WHEN RETURN_HOME =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"80";
state <= DROP_LCD_E;
next_command <= Print_String;
-- The next three states occur at the end of each command or data transfer to the LCD
-- Drop LCD E line - falling edge loads inst/data to LCD controller
WHEN DROP_LCD_E =>
LCD_E <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END IF;
END PROCESS;
END a;
| mit | 6ce9dfa342e090a97ae910df850246c9 | 0.557944 | 3.078782 | false | false | false | false |
graphman65/linter-vhdl | examples/main.vhd | 1 | 421 | library ieee;
use ieee.std_logic_1164.all;
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;
architecture OR_arch of OR_ent is
begin
process(x, y)
begin
-- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;
end OR_arch;
architecture OR_beh of OR_ent is
begin
F <= x or y;
end OR_beh;
| mit | 6341bf723fe8ad3454b55f3c81025f9c | 0.584323 | 2.681529 | false | false | false | false |
TheMassController/VHDL_experimenting | project/complete_system/test/two_brams_tb.vhd | 1 | 6,382 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library tb;
use tb.bus_tb_pkg.all;
use tb.depp_tb_pkg.all;
library src;
use src.bus_pkg.all;
use src.depp_pkg.all;
entity two_brams_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of two_brams_tb is
constant clk_period : time := 20 ns;
signal clk : std_logic := '0';
signal usb_db : std_logic_vector(7 downto 0);
signal usb_write : std_logic;
signal usb_astb : std_logic;
signal usb_dstb : std_logic;
signal usb_wait : std_logic;
signal addr : bus_address_type;
signal data : bus_data_type;
signal wMask : bus_write_mask;
begin
clk <= not clk after (clk_period/2);
main : process
variable bus_address : bus_address_type := (others => '0');
variable bus_writeData : bus_data_type := (others => '0');
variable bus_readData : bus_data_type := (others => '0');
variable depp_address : depp_address_type := (others => '0');
variable depp_data : depp_data_type := (others => '0');
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Write then read") then
-- Set both fast read and fast write
depp_data(depp_mode_fast_write_bit) := '1';
depp_data(depp_mode_fast_read_bit) := '1';
depp_address := std_logic_vector(to_unsigned(depp2bus_mode_register_start, depp_address'length));
depp_tb_depp_write_to_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address,
data => depp_data
);
-- Set the bus address to all zeros
depp_tb_bus_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
address => bus_address
);
-- Set the writemask to all 1
depp_address := std_logic_vector(to_unsigned(depp2bus_write_mask_reg_start, depp_address'length));
depp_data := (others => '1');
depp_tb_depp_write_to_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address,
data => depp_data
);
-- Set the depp address to writeData start
depp_address := std_logic_vector(to_unsigned(depp2bus_writeData_reg_start, depp_address'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address
);
-- Start with writing
for i in 0 to 1023 loop
bus_writeData := std_logic_vector(to_unsigned(i, bus_writeData'length));
for j in 0 to 3 loop
depp_tb_depp_set_data (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
data => bus_writeData((j+1)*8 - 1 downto j*8),
expect_completion => true
);
end loop;
end loop;
-- Set the bus address to all zeros
bus_address := (others => '0');
depp_tb_bus_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
address => bus_address
);
-- Set the depp address to readData_start
depp_address := std_logic_vector(to_unsigned(depp2bus_readData_reg_start, depp_address'length));
depp_tb_depp_set_address (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
addr => depp_address
);
-- Now read it back
for i in 0 to 1023 loop
for j in 0 to 3 loop
depp_tb_depp_get_data (
clk => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait,
data => bus_readData((j+1)*8 - 1 downto j*8),
expect_completion => true
);
end loop;
check_equal(to_integer(unsigned(bus_readData)), i);
end loop;
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
test_runner_watchdog(runner, 1 ms);
two_brams_system : entity src.two_brams
port map (
clk_50mhz => clk,
usb_db => usb_db,
usb_write => usb_write,
usb_astb => usb_astb,
usb_dstb => usb_dstb,
usb_wait => usb_wait
);
end architecture;
| mit | 62b65f2aee08c6153bcb2bf619dfd559 | 0.438421 | 4.344452 | false | false | false | false |
chastell/art-decomp | kiss/keyb_jed.vhd | 1 | 16,319 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_jed;
architecture behaviour of keyb_jed is
constant st0: std_logic_vector(4 downto 0) := "10100";
constant st1: std_logic_vector(4 downto 0) := "10111";
constant st2: std_logic_vector(4 downto 0) := "10110";
constant st3: std_logic_vector(4 downto 0) := "10010";
constant st4: std_logic_vector(4 downto 0) := "11000";
constant st5: std_logic_vector(4 downto 0) := "10000";
constant st6: std_logic_vector(4 downto 0) := "00000";
constant st7: std_logic_vector(4 downto 0) := "11110";
constant st8: std_logic_vector(4 downto 0) := "11100";
constant st9: std_logic_vector(4 downto 0) := "11001";
constant st10: std_logic_vector(4 downto 0) := "11101";
constant st11: std_logic_vector(4 downto 0) := "10101";
constant st12: std_logic_vector(4 downto 0) := "10001";
constant st13: std_logic_vector(4 downto 0) := "00101";
constant st14: std_logic_vector(4 downto 0) := "00100";
constant st15: std_logic_vector(4 downto 0) := "01000";
constant st16: std_logic_vector(4 downto 0) := "01100";
constant st17: std_logic_vector(4 downto 0) := "11010";
constant st18: std_logic_vector(4 downto 0) := "00110";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | e9276ed5505b59fbecde2bfa1ce8577c | 0.541026 | 3.343372 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/cntr_top.vhd | 1 | 2,705 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_top.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Top Structure of the counter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture struc of cntr_top is
component io_ctrl is
port (
clk_i : in std_logic; -- clock input
reset_i : in std_logic; -- central reset
digits_i : in std_logic_vector(13 downto 0); -- four digit in one digits vector
sw_i : in std_logic_vector(15 downto 0); -- 16 input switches
pb_i : in std_logic_vector(3 downto 0); -- 4 control buttons
ss_o : out std_logic_vector(7 downto 0); -- data for all 7-segment digits
ss_sel_o : out std_logic_vector(3 downto 0); -- selection vector for the 7-segment digit
swclean_o : out std_logic_vector(15 downto 0); -- 16 switches to internal logic
pbclean_o : out std_logic_vector(3 downto 0)); -- 4 buttons to internal logic
end component;
component cntr is
port(
clk_i : in std_logic;
reset_i : in std_logic;
cntrup_i : in std_logic;
cntrdown_i : in std_logic;
cntrreset_i : in std_logic;
cntrhold_i : in std_logic;
digits_o : out std_logic_vector(13 downto 0));
end component;
signal s_pbclean : std_logic_vector(3 downto 0);
signal s_swclean : std_logic_vector(15 downto 0);
signal s_digits : std_logic_vector(13 downto 0);
begin
p_io_ctrl : io_ctrl
port map (
clk_i => clk_i,
reset_i => reset_i,
digits_i => s_digits,
sw_i => sw_i,
pb_i => pb_i,
ss_o => ss_o,
ss_sel_o => ss_sel_o,
swclean_o => s_swclean,
pbclean_o => s_pbclean);
p_cntr : cntr
port map (
clk_i => clk_i,
reset_i => reset_i,
cntrup_i => s_swclean(13),
cntrdown_i => s_swclean(12),
cntrreset_i => s_swclean(15),
cntrhold_i => s_swclean(14),
digits_o => s_digits);
end struc; | mit | b1338d4869747020a3b18049dc20c141 | 0.488725 | 3.809859 | false | false | false | false |
chastell/art-decomp | kiss/bbara_jed.vhd | 1 | 6,275 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_jed;
architecture behaviour of bbara_jed is
constant st0: std_logic_vector(3 downto 0) := "0111";
constant st1: std_logic_vector(3 downto 0) := "0100";
constant st4: std_logic_vector(3 downto 0) := "0110";
constant st2: std_logic_vector(3 downto 0) := "0101";
constant st3: std_logic_vector(3 downto 0) := "0000";
constant st7: std_logic_vector(3 downto 0) := "0010";
constant st5: std_logic_vector(3 downto 0) := "1100";
constant st6: std_logic_vector(3 downto 0) := "1110";
constant st8: std_logic_vector(3 downto 0) := "0011";
constant st9: std_logic_vector(3 downto 0) := "1111";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "--01") then next_state <= st0; output <= "00";
elsif std_match(input, "--10") then next_state <= st0; output <= "00";
elsif std_match(input, "--00") then next_state <= st0; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st1 =>
if std_match(input, "--01") then next_state <= st1; output <= "00";
elsif std_match(input, "--10") then next_state <= st1; output <= "00";
elsif std_match(input, "--00") then next_state <= st1; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st2; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st2 =>
if std_match(input, "--01") then next_state <= st2; output <= "00";
elsif std_match(input, "--10") then next_state <= st2; output <= "00";
elsif std_match(input, "--00") then next_state <= st2; output <= "00";
elsif std_match(input, "0011") then next_state <= st1; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st3 =>
if std_match(input, "--01") then next_state <= st3; output <= "10";
elsif std_match(input, "--10") then next_state <= st3; output <= "10";
elsif std_match(input, "--00") then next_state <= st3; output <= "10";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "10";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st4 =>
if std_match(input, "--01") then next_state <= st4; output <= "00";
elsif std_match(input, "--10") then next_state <= st4; output <= "00";
elsif std_match(input, "--00") then next_state <= st4; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st5; output <= "00";
end if;
when st5 =>
if std_match(input, "--01") then next_state <= st5; output <= "00";
elsif std_match(input, "--10") then next_state <= st5; output <= "00";
elsif std_match(input, "--00") then next_state <= st5; output <= "00";
elsif std_match(input, "0011") then next_state <= st4; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "00";
end if;
when st6 =>
if std_match(input, "--01") then next_state <= st6; output <= "01";
elsif std_match(input, "--10") then next_state <= st6; output <= "01";
elsif std_match(input, "--00") then next_state <= st6; output <= "01";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "01";
end if;
when st7 =>
if std_match(input, "--01") then next_state <= st7; output <= "00";
elsif std_match(input, "--10") then next_state <= st7; output <= "00";
elsif std_match(input, "--00") then next_state <= st7; output <= "00";
elsif std_match(input, "0011") then next_state <= st8; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st8 =>
if std_match(input, "--01") then next_state <= st8; output <= "00";
elsif std_match(input, "--10") then next_state <= st8; output <= "00";
elsif std_match(input, "--00") then next_state <= st8; output <= "00";
elsif std_match(input, "0011") then next_state <= st9; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st9 =>
if std_match(input, "--01") then next_state <= st9; output <= "00";
elsif std_match(input, "--10") then next_state <= st9; output <= "00";
elsif std_match(input, "--00") then next_state <= st9; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 842f8a0af157836352a3ef4f464cc52e | 0.571474 | 3.280188 | false | false | false | false |
chastell/art-decomp | kiss/s27_nov.vhd | 1 | 3,869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_nov;
architecture behaviour of s27_nov is
constant s000: std_logic_vector(2 downto 0) := "010";
constant s001: std_logic_vector(2 downto 0) := "100";
constant s101: std_logic_vector(2 downto 0) := "101";
constant s100: std_logic_vector(2 downto 0) := "110";
constant s010: std_logic_vector(2 downto 0) := "000";
constant s011: std_logic_vector(2 downto 0) := "111";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | c190e62344d5c1210931c15d526bee03 | 0.576376 | 3.181743 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_ff_.vhd | 1 | 2,144 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_ff_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_ff is
end tb_ff;
architecture sim of tb_ff is
-- Declaration of the component under test
component ff
port (
data_i : in std_logic;
clk_i : in std_logic;
reset_i : in std_logic;
qout_o : out std_logic);
end component;
-- System clock 100MHz
constant system_clk : time := 10 ns;
signal data_i : std_logic;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal qout_o : std_logic;
begin
-- Instantiate the design under test
i_ff : ff
port map (
data_i => data_i,
clk_i => clk_i,
reset_i => reset_i,
qout_o => qout_o);
-- Generate clock
p_clk : process
begin
clk_i <= '0';
wait for system_clk / 2;
clk_i <= '1';
wait for system_clk / 2;
end process p_clk;
-- Generate reset
p_reset : process
begin
reset_i <= '1';
wait for 120 ns;
reset_i <= '0';
wait;
end process p_reset;
p_stim : process
begin
data_i <= '0';
wait for 320 ns;
data_i <= '1';
wait for 400 ns;
data_i <= '0';
wait for 400 ns;
data_i <= '1';
wait for 400 ns;
-- stop simulation
assert false report "END OF SIMULATION" severity error;
end process p_stim;
end sim;
| mit | ac7848ad389ccd62b6ee85fc6898f586 | 0.470616 | 4.076046 | false | false | false | false |
chastell/art-decomp | kiss/mark1_rnd.vhd | 1 | 4,356 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_rnd;
architecture behaviour of mark1_rnd is
constant state1: std_logic_vector(3 downto 0) := "1101";
constant state3: std_logic_vector(3 downto 0) := "0010";
constant state2: std_logic_vector(3 downto 0) := "1011";
constant state0: std_logic_vector(3 downto 0) := "1110";
constant state4: std_logic_vector(3 downto 0) := "1111";
constant state13: std_logic_vector(3 downto 0) := "0001";
constant state10: std_logic_vector(3 downto 0) := "0110";
constant state9: std_logic_vector(3 downto 0) := "0000";
constant state8: std_logic_vector(3 downto 0) := "1010";
constant state7: std_logic_vector(3 downto 0) := "1000";
constant state6: std_logic_vector(3 downto 0) := "0100";
constant state5: std_logic_vector(3 downto 0) := "1001";
constant state14: std_logic_vector(3 downto 0) := "1100";
constant state11: std_logic_vector(3 downto 0) := "0011";
constant state12: std_logic_vector(3 downto 0) := "0111";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "----------------";
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
else
case current_state is
when state1 =>
if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
end if;
when state2 =>
if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
end if;
when state3 =>
if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
end if;
when state4 =>
if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
end if;
when state5 =>
if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
end if;
when state6 =>
if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
end if;
when state7 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
end if;
when state8 =>
if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
end if;
when state9 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
end if;
when state10 =>
if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
end if;
when state11 =>
if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
end if;
when state12 =>
if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
end if;
when state13 =>
if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
end if;
when state14 =>
if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
end if;
when state0 =>
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
end if;
when others => next_state <= "----"; output <= "----------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 9ab03639adcd0f1e5d31a87176f74ac2 | 0.557622 | 3.424528 | false | false | false | false |
chastell/art-decomp | kiss/lion_nov.vhd | 1 | 1,832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_nov;
architecture behaviour of lion_nov is
constant st0: std_logic_vector(1 downto 0) := "00";
constant st1: std_logic_vector(1 downto 0) := "01";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "10";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "-0") then next_state <= st0; output <= "0";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "0-") then next_state <= st1; output <= "1";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "1-") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "0-") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 714ec80ac3d39eaba59d33b7b664b5f3 | 0.587882 | 3.231041 | false | false | false | false |
chastell/art-decomp | kiss/s8_jed.vhd | 1 | 2,612 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s8_jed is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s8_jed;
architecture behaviour of s8_jed is
constant s1: std_logic_vector(2 downto 0) := "100";
constant s2: std_logic_vector(2 downto 0) := "110";
constant s3: std_logic_vector(2 downto 0) := "111";
constant s5: std_logic_vector(2 downto 0) := "101";
constant s4: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s1 =>
if std_match(input, "1000") then next_state <= s1; output <= "1";
elsif std_match(input, "0100") then next_state <= s1; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s2; output <= "1";
end if;
when s2 =>
if std_match(input, "1000") then next_state <= s2; output <= "1";
elsif std_match(input, "0100") then next_state <= s3; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s1; output <= "1";
end if;
when s3 =>
if std_match(input, "1000") then next_state <= s3; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s5; output <= "1";
end if;
when s4 =>
if std_match(input, "1000") then next_state <= s4; output <= "1";
elsif std_match(input, "0100") then next_state <= s2; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s3; output <= "1";
end if;
when s5 =>
if std_match(input, "1000") then next_state <= s5; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s1; output <= "1";
elsif std_match(input, "0001") then next_state <= s4; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 5c4a1ba3ead1f8b29b4b5d4b18e17776 | 0.582695 | 3.20098 | false | false | false | false |
TheMassController/VHDL_experimenting | project/sevenSegment/seven_seg_controller.vhd | 1 | 3,316 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.seven_seg_pkg.all;
entity seven_seg_controller is
generic (
-- The controller cycles through the seven segment displays
-- This variable controls how long (in clk cycles) every digit is turned on.
hold_count : natural range 1 to natural'high;
digit_count : natural range 1 to natural'high
);
port (
clk : in std_logic;
rst : in std_logic;
-- Bus connection
mst2slv : in bus_mst2slv_type;
slv2mst : out bus_slv2mst_type;
digit_anodes : out std_logic_vector(digit_count - 1 downto 0);
kathode : out seven_seg_kath_type
);
end seven_seg_controller;
architecture behaviourial of seven_seg_controller is
constant check_range : addr_range_type := (
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(digit_count - 1, bus_address_type'length))
);
signal digit_storage : bus_byte_array(digit_count - 1 downto 0) := (others => (others => '0'));
signal timer_done : std_logic;
begin
sequential : process(clk)
variable full_addr : natural range 0 to 2*digit_count;
variable addr : natural range 0 to digit_count - 1 := 0;
variable cur_digit : natural range 0 to digit_count - 1 := 0;
begin
if rising_edge(clk) then
-- Bus interaction
slv2mst.readData <= (others => '0');
if bus_addr_in_range(mst2slv.address, check_range) then
full_addr := to_integer(unsigned(mst2slv.address(mst2slv.address'range)));
for b in 0 to bus_bytes_per_word - 1 loop
if (full_addr + b < digit_count) then
addr := full_addr + b;
if mst2slv.writeEnable = '1' and mst2slv.writeMask(b) = '1' then
digit_storage(addr) <= mst2slv.writeData((b+1) * bus_byte_size - 1 downto b*bus_byte_size);
end if;
slv2mst.readData((b+1) * bus_byte_size - 1 downto b*bus_byte_size) <= digit_storage(addr);
end if;
end loop;
slv2mst.fault <= '0';
else
slv2mst.fault <= '1';
end if;
if rst = '1' then
slv2mst.ack <= '0';
else
slv2mst.ack <= bus_requesting(mst2slv);
end if;
-- Digit control
if timer_done = '1' then
if cur_digit = digit_count - 1 then
cur_digit := 0;
else
cur_digit := cur_digit + 1;
end if;
end if;
-- Set the output to the digits
kathode <= hex_to_seven_seg(digit_storage(cur_digit)(digit_info_type'range));
digit_anodes <= (others => '1');
digit_anodes(cur_digit) <= '0';
end if;
end process;
timer : entity work.simple_multishot_timer
generic map (
match_val => hold_count
)
port map (
clk => clk,
rst => '0',
done => timer_done
);
end behaviourial;
| mit | 7c4dd8d1dbdff52a4b986706c3b5bcca | 0.53076 | 3.864802 | false | false | false | false |
chastell/art-decomp | spec/fixtures/mark1_jed.vhd | 2 | 4,356 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_jed is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_jed;
architecture behaviour of mark1_jed is
constant state1: std_logic_vector(3 downto 0) := "0001";
constant state3: std_logic_vector(3 downto 0) := "1111";
constant state2: std_logic_vector(3 downto 0) := "0011";
constant state0: std_logic_vector(3 downto 0) := "1101";
constant state4: std_logic_vector(3 downto 0) := "1001";
constant state13: std_logic_vector(3 downto 0) := "1010";
constant state10: std_logic_vector(3 downto 0) := "1000";
constant state9: std_logic_vector(3 downto 0) := "1100";
constant state8: std_logic_vector(3 downto 0) := "0010";
constant state7: std_logic_vector(3 downto 0) := "0000";
constant state6: std_logic_vector(3 downto 0) := "0110";
constant state5: std_logic_vector(3 downto 0) := "0100";
constant state14: std_logic_vector(3 downto 0) := "1110";
constant state11: std_logic_vector(3 downto 0) := "0111";
constant state12: std_logic_vector(3 downto 0) := "1011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "----------------";
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
else
case current_state is
when state1 =>
if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
end if;
when state2 =>
if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
end if;
when state3 =>
if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
end if;
when state4 =>
if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
end if;
when state5 =>
if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
end if;
when state6 =>
if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
end if;
when state7 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
end if;
when state8 =>
if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
end if;
when state9 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
end if;
when state10 =>
if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
end if;
when state11 =>
if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
end if;
when state12 =>
if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
end if;
when state13 =>
if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
end if;
when state14 =>
if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
end if;
when state0 =>
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
end if;
when others => next_state <= "----"; output <= "----------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 3c9f72dd7f4e50b3b2e4e0f7bbbb5016 | 0.557622 | 3.424528 | false | false | false | false |
chastell/art-decomp | kiss/s298_rnd.vhd | 1 | 128,772 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_rnd;
architecture behaviour of s298_rnd is
constant s00000000000000: std_logic_vector(7 downto 0) := "10111101";
constant s00000001100000: std_logic_vector(7 downto 0) := "00000010";
constant s10000001100010: std_logic_vector(7 downto 0) := "10011011";
constant s10000001100011: std_logic_vector(7 downto 0) := "10111110";
constant s10000001100001: std_logic_vector(7 downto 0) := "01111111";
constant s10000001100000: std_logic_vector(7 downto 0) := "01010001";
constant s01000001100001: std_logic_vector(7 downto 0) := "10010110";
constant s01000001100000: std_logic_vector(7 downto 0) := "00001011";
constant s01000001100011: std_logic_vector(7 downto 0) := "11001111";
constant s01000001100010: std_logic_vector(7 downto 0) := "10011110";
constant s11001001100011: std_logic_vector(7 downto 0) := "11011011";
constant s11001001100010: std_logic_vector(7 downto 0) := "00101011";
constant s11001001100000: std_logic_vector(7 downto 0) := "01100001";
constant s11001001100001: std_logic_vector(7 downto 0) := "11110000";
constant s00100001100011: std_logic_vector(7 downto 0) := "01101111";
constant s00100001100010: std_logic_vector(7 downto 0) := "00001111";
constant s00100001100001: std_logic_vector(7 downto 0) := "11101011";
constant s00100001100000: std_logic_vector(7 downto 0) := "01011010";
constant s10101001100010: std_logic_vector(7 downto 0) := "00111000";
constant s10101001100011: std_logic_vector(7 downto 0) := "10110110";
constant s10101001100000: std_logic_vector(7 downto 0) := "01001000";
constant s10101001100001: std_logic_vector(7 downto 0) := "00000001";
constant s01101001100010: std_logic_vector(7 downto 0) := "10100100";
constant s01101001100011: std_logic_vector(7 downto 0) := "10111111";
constant s01101001100001: std_logic_vector(7 downto 0) := "10001001";
constant s01101001100000: std_logic_vector(7 downto 0) := "10101001";
constant s11101001100011: std_logic_vector(7 downto 0) := "10100110";
constant s11101001100010: std_logic_vector(7 downto 0) := "10111011";
constant s11101001100000: std_logic_vector(7 downto 0) := "01011100";
constant s11101001100001: std_logic_vector(7 downto 0) := "01100011";
constant s00010001100010: std_logic_vector(7 downto 0) := "11111000";
constant s00010001100011: std_logic_vector(7 downto 0) := "00100010";
constant s00010001100000: std_logic_vector(7 downto 0) := "00111101";
constant s00010001100001: std_logic_vector(7 downto 0) := "01001001";
constant s10010100011010: std_logic_vector(7 downto 0) := "10111000";
constant s10010100011011: std_logic_vector(7 downto 0) := "00011000";
constant s10010100011000: std_logic_vector(7 downto 0) := "01010110";
constant s10010100011001: std_logic_vector(7 downto 0) := "00100011";
constant s00000000011000: std_logic_vector(7 downto 0) := "01000011";
constant s00001100000001: std_logic_vector(7 downto 0) := "10110111";
constant s00001100000000: std_logic_vector(7 downto 0) := "00010011";
constant s00001100000010: std_logic_vector(7 downto 0) := "10110010";
constant s00001100000011: std_logic_vector(7 downto 0) := "11000111";
constant s10000100011001: std_logic_vector(7 downto 0) := "11111111";
constant s10000100011000: std_logic_vector(7 downto 0) := "00001100";
constant s10000100011010: std_logic_vector(7 downto 0) := "10110101";
constant s10000100011011: std_logic_vector(7 downto 0) := "01010100";
constant s10100001100010: std_logic_vector(7 downto 0) := "00000000";
constant s10100001100011: std_logic_vector(7 downto 0) := "01000001";
constant s10100001100001: std_logic_vector(7 downto 0) := "10100010";
constant s10100001100000: std_logic_vector(7 downto 0) := "01011011";
constant s01100001100001: std_logic_vector(7 downto 0) := "11100111";
constant s01100001100000: std_logic_vector(7 downto 0) := "01011101";
constant s01100001100011: std_logic_vector(7 downto 0) := "01001011";
constant s01100001100010: std_logic_vector(7 downto 0) := "00011011";
constant s11101000100110: std_logic_vector(7 downto 0) := "10101111";
constant s11101000100111: std_logic_vector(7 downto 0) := "01101101";
constant s11101000100101: std_logic_vector(7 downto 0) := "01011000";
constant s11101000100100: std_logic_vector(7 downto 0) := "00100101";
constant s00000000100100: std_logic_vector(7 downto 0) := "10100000";
constant s00011000100110: std_logic_vector(7 downto 0) := "00010001";
constant s00011000100111: std_logic_vector(7 downto 0) := "01111100";
constant s00011000100101: std_logic_vector(7 downto 0) := "11000100";
constant s00011000100100: std_logic_vector(7 downto 0) := "00110011";
constant s10011000100100: std_logic_vector(7 downto 0) := "11010111";
constant s10011000100101: std_logic_vector(7 downto 0) := "00000111";
constant s10011000100111: std_logic_vector(7 downto 0) := "11111010";
constant s10011000100110: std_logic_vector(7 downto 0) := "11010110";
constant s00000000100111: std_logic_vector(7 downto 0) := "11111001";
constant s00000000100110: std_logic_vector(7 downto 0) := "10001100";
constant s00000000100101: std_logic_vector(7 downto 0) := "01101000";
constant s01001001100011: std_logic_vector(7 downto 0) := "01000100";
constant s01001001100010: std_logic_vector(7 downto 0) := "01100000";
constant s01001001100000: std_logic_vector(7 downto 0) := "10111001";
constant s01001001100001: std_logic_vector(7 downto 0) := "10000101";
constant s11000001100000: std_logic_vector(7 downto 0) := "00010100";
constant s11000001100001: std_logic_vector(7 downto 0) := "11001100";
constant s11000001100011: std_logic_vector(7 downto 0) := "01111011";
constant s11000001100010: std_logic_vector(7 downto 0) := "11010011";
constant s00011001100001: std_logic_vector(7 downto 0) := "01110100";
constant s00011001100000: std_logic_vector(7 downto 0) := "01001010";
constant s00011001100011: std_logic_vector(7 downto 0) := "01110011";
constant s00011001100010: std_logic_vector(7 downto 0) := "11000110";
constant s10010001100010: std_logic_vector(7 downto 0) := "00110111";
constant s10010001100011: std_logic_vector(7 downto 0) := "11011001";
constant s10010001100001: std_logic_vector(7 downto 0) := "11100000";
constant s10010001100000: std_logic_vector(7 downto 0) := "11110100";
constant s10001100011000: std_logic_vector(7 downto 0) := "11100101";
constant s10001100011001: std_logic_vector(7 downto 0) := "11101110";
constant s10001100011011: std_logic_vector(7 downto 0) := "01110001";
constant s10001100011010: std_logic_vector(7 downto 0) := "11101000";
constant s01001100000001: std_logic_vector(7 downto 0) := "10111100";
constant s01001100000000: std_logic_vector(7 downto 0) := "10100001";
constant s01001100000010: std_logic_vector(7 downto 0) := "00111011";
constant s01001100000011: std_logic_vector(7 downto 0) := "10101000";
constant s11000100011001: std_logic_vector(7 downto 0) := "00011111";
constant s11000100011000: std_logic_vector(7 downto 0) := "10000010";
constant s11000100011010: std_logic_vector(7 downto 0) := "10011010";
constant s11000100011011: std_logic_vector(7 downto 0) := "11111101";
constant s00101100000000: std_logic_vector(7 downto 0) := "11110110";
constant s00101100000001: std_logic_vector(7 downto 0) := "11010000";
constant s00101100000010: std_logic_vector(7 downto 0) := "10010000";
constant s00101100000011: std_logic_vector(7 downto 0) := "00100111";
constant s10101100011001: std_logic_vector(7 downto 0) := "10110000";
constant s10101100011000: std_logic_vector(7 downto 0) := "10000100";
constant s10101100011010: std_logic_vector(7 downto 0) := "01110010";
constant s10101100011011: std_logic_vector(7 downto 0) := "01111110";
constant s10100100011011: std_logic_vector(7 downto 0) := "11111100";
constant s10100100011010: std_logic_vector(7 downto 0) := "01101110";
constant s10100100011001: std_logic_vector(7 downto 0) := "00010110";
constant s10100100011000: std_logic_vector(7 downto 0) := "00110100";
constant s00100100000011: std_logic_vector(7 downto 0) := "01110110";
constant s00100100000010: std_logic_vector(7 downto 0) := "00110101";
constant s00100100000001: std_logic_vector(7 downto 0) := "00110001";
constant s00100100000000: std_logic_vector(7 downto 0) := "11111011";
constant s11001100011000: std_logic_vector(7 downto 0) := "10100011";
constant s11001100011001: std_logic_vector(7 downto 0) := "11001011";
constant s11001100011010: std_logic_vector(7 downto 0) := "10011001";
constant s11001100011011: std_logic_vector(7 downto 0) := "01101001";
constant s01000100000000: std_logic_vector(7 downto 0) := "11110001";
constant s01000100000001: std_logic_vector(7 downto 0) := "11000001";
constant s01000100000010: std_logic_vector(7 downto 0) := "00011010";
constant s01000100000011: std_logic_vector(7 downto 0) := "01110101";
constant s00001010010001: std_logic_vector(7 downto 0) := "11001110";
constant s00001010010000: std_logic_vector(7 downto 0) := "01001100";
constant s00001010010011: std_logic_vector(7 downto 0) := "01000010";
constant s00001010010010: std_logic_vector(7 downto 0) := "00111110";
constant s00000010010000: std_logic_vector(7 downto 0) := "00000100";
constant s10000000011010: std_logic_vector(7 downto 0) := "10010011";
constant s10000000011011: std_logic_vector(7 downto 0) := "00100100";
constant s10000000011001: std_logic_vector(7 downto 0) := "11001000";
constant s10000000011000: std_logic_vector(7 downto 0) := "01101010";
constant s00101001100010: std_logic_vector(7 downto 0) := "11101100";
constant s00101001100011: std_logic_vector(7 downto 0) := "10010010";
constant s00101001100000: std_logic_vector(7 downto 0) := "10000111";
constant s00101001100001: std_logic_vector(7 downto 0) := "00001001";
constant s10001000011000: std_logic_vector(7 downto 0) := "11010100";
constant s10001000011001: std_logic_vector(7 downto 0) := "01100010";
constant s10001000011011: std_logic_vector(7 downto 0) := "11100010";
constant s10001000011010: std_logic_vector(7 downto 0) := "01001111";
constant s01001000011011: std_logic_vector(7 downto 0) := "11011101";
constant s01001000011010: std_logic_vector(7 downto 0) := "10101010";
constant s01001000011001: std_logic_vector(7 downto 0) := "01000000";
constant s01001000011000: std_logic_vector(7 downto 0) := "01100100";
constant s01000000011011: std_logic_vector(7 downto 0) := "10001000";
constant s01000000011010: std_logic_vector(7 downto 0) := "01111010";
constant s01000000011001: std_logic_vector(7 downto 0) := "01000110";
constant s01000000011000: std_logic_vector(7 downto 0) := "10011111";
constant s10011001100001: std_logic_vector(7 downto 0) := "01101011";
constant s10011001100000: std_logic_vector(7 downto 0) := "11100011";
constant s10011001100011: std_logic_vector(7 downto 0) := "11110010";
constant s10011001100010: std_logic_vector(7 downto 0) := "10110011";
constant s00000001100001: std_logic_vector(7 downto 0) := "00111111";
constant s00000001100010: std_logic_vector(7 downto 0) := "10010100";
constant s00000001100011: std_logic_vector(7 downto 0) := "10011101";
constant s10001001100000: std_logic_vector(7 downto 0) := "11000011";
constant s10001001100001: std_logic_vector(7 downto 0) := "01111001";
constant s10001001100010: std_logic_vector(7 downto 0) := "10100101";
constant s10001001100011: std_logic_vector(7 downto 0) := "00010000";
constant s10011010010000: std_logic_vector(7 downto 0) := "00001010";
constant s10011010010001: std_logic_vector(7 downto 0) := "11100100";
constant s10011010010010: std_logic_vector(7 downto 0) := "01010010";
constant s10011010010011: std_logic_vector(7 downto 0) := "11011110";
constant s00000010010011: std_logic_vector(7 downto 0) := "00011110";
constant s00000010010010: std_logic_vector(7 downto 0) := "10100111";
constant s00000010010001: std_logic_vector(7 downto 0) := "01010111";
constant s10010010010011: std_logic_vector(7 downto 0) := "01011111";
constant s10010010010010: std_logic_vector(7 downto 0) := "10001011";
constant s10010010010000: std_logic_vector(7 downto 0) := "01110000";
constant s10010010010001: std_logic_vector(7 downto 0) := "00111001";
constant s10011100011000: std_logic_vector(7 downto 0) := "11111110";
constant s10011100011001: std_logic_vector(7 downto 0) := "00001101";
constant s10011100011011: std_logic_vector(7 downto 0) := "00101010";
constant s10011100011010: std_logic_vector(7 downto 0) := "11010001";
constant s00000100000010: std_logic_vector(7 downto 0) := "10011000";
constant s00000100000011: std_logic_vector(7 downto 0) := "01011110";
constant s00000100000000: std_logic_vector(7 downto 0) := "00100000";
constant s00000100000001: std_logic_vector(7 downto 0) := "00010010";
constant s11100001100001: std_logic_vector(7 downto 0) := "01100110";
constant s11100001100000: std_logic_vector(7 downto 0) := "00100001";
constant s11100001100010: std_logic_vector(7 downto 0) := "10001010";
constant s11100001100011: std_logic_vector(7 downto 0) := "10000000";
constant s10010000100111: std_logic_vector(7 downto 0) := "01001101";
constant s10010000100110: std_logic_vector(7 downto 0) := "10101110";
constant s10010000100101: std_logic_vector(7 downto 0) := "11100110";
constant s10010000100100: std_logic_vector(7 downto 0) := "01111000";
constant s00010000100100: std_logic_vector(7 downto 0) := "00101100";
constant s00010000100101: std_logic_vector(7 downto 0) := "10101101";
constant s00010000100110: std_logic_vector(7 downto 0) := "11001101";
constant s00010000100111: std_logic_vector(7 downto 0) := "10001110";
constant s11100000100111: std_logic_vector(7 downto 0) := "11011100";
constant s11100000100110: std_logic_vector(7 downto 0) := "00110000";
constant s11100000100100: std_logic_vector(7 downto 0) := "11010101";
constant s11100000100101: std_logic_vector(7 downto 0) := "00011001";
constant s01100100000010: std_logic_vector(7 downto 0) := "11001001";
constant s01100100000011: std_logic_vector(7 downto 0) := "01100111";
constant s01100100000001: std_logic_vector(7 downto 0) := "00011100";
constant s01100100000000: std_logic_vector(7 downto 0) := "10111010";
constant s11100100011011: std_logic_vector(7 downto 0) := "10101011";
constant s11100100011010: std_logic_vector(7 downto 0) := "10000001";
constant s11100100011001: std_logic_vector(7 downto 0) := "00000011";
constant s11100100011000: std_logic_vector(7 downto 0) := "01010011";
constant s00011100000001: std_logic_vector(7 downto 0) := "10000110";
constant s00011100000000: std_logic_vector(7 downto 0) := "01001110";
constant s00011100000010: std_logic_vector(7 downto 0) := "00010101";
constant s00011100000011: std_logic_vector(7 downto 0) := "00010111";
constant s00010100000000: std_logic_vector(7 downto 0) := "00101110";
constant s00010100000001: std_logic_vector(7 downto 0) := "11110111";
constant s00010100000010: std_logic_vector(7 downto 0) := "00000110";
constant s00010100000011: std_logic_vector(7 downto 0) := "10110100";
constant s11101100011001: std_logic_vector(7 downto 0) := "00111100";
constant s11101100011000: std_logic_vector(7 downto 0) := "11101010";
constant s11101100011010: std_logic_vector(7 downto 0) := "10001111";
constant s11101100011011: std_logic_vector(7 downto 0) := "11101001";
constant s01101100000000: std_logic_vector(7 downto 0) := "11101101";
constant s01101100000001: std_logic_vector(7 downto 0) := "11000000";
constant s01101100000011: std_logic_vector(7 downto 0) := "11000101";
constant s01101100000010: std_logic_vector(7 downto 0) := "00110010";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "------";
case current_state is
when s00000000000000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "000000";
end if;
when s00000001100000 =>
if std_match(input, "000") then next_state <= s10000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10000001100000 =>
if std_match(input, "010") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100001 =>
if std_match(input, "001") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100011 =>
if std_match(input, "000") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100011 =>
if std_match(input, "010") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100010 =>
if std_match(input, "000") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100001; output <= "100001";
end if;
when s11101001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100001; output <= "100001";
end if;
when s00010001100010 =>
if std_match(input, "000") then next_state <= s10010100011010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10010100011010 =>
if std_match(input, "011") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011011; output <= "000000";
end if;
when s00000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "010100";
end if;
when s10000001100010 =>
if std_match(input, "010") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "100001";
end if;
when s11001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100010; output <= "100001";
end if;
when s00100001100000 =>
if std_match(input, "001") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100010 =>
if std_match(input, "011") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100001 =>
if std_match(input, "011") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100110 =>
if std_match(input, "000") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100110 =>
if std_match(input, "001") then next_state <= s10011000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100100; output <= "100010";
end if;
when s00000000100100 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100010";
end if;
when s10000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100001; output <= "100001";
end if;
when s01001001100011 =>
if std_match(input, "011") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100000; output <= "100001";
end if;
when s00100001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100001; output <= "100001";
end if;
when s10100001100011 =>
if std_match(input, "011") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100000; output <= "100001";
end if;
when s11101001100010 =>
if std_match(input, "011") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100001 =>
if std_match(input, "011") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10010001100010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100001";
end if;
when s00001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011010; output <= "000000";
end if;
when s10001100011000 =>
if std_match(input, "010") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011011; output <= "000000";
end if;
when s11000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000011; output <= "010100";
end if;
when s00101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000001 =>
if std_match(input, "001") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011010; output <= "000000";
end if;
when s11000100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000000; output <= "010100";
end if;
when s00100100000011 =>
if std_match(input, "011") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011010; output <= "000000";
end if;
when s00100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011011; output <= "000000";
end if;
when s00100100000000 =>
if std_match(input, "000") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11000100011010 =>
if std_match(input, "011") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11000100011011 =>
if std_match(input, "010") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000000 =>
if std_match(input, "000") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11001100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000011; output <= "010100";
end if;
when s11001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000010; output <= "010100";
end if;
when s11001100011010 =>
if std_match(input, "000") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11001100011011 =>
if std_match(input, "001") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011001; output <= "000000";
end if;
when s01001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011010; output <= "000000";
end if;
when s10001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000011; output <= "010100";
end if;
when s01000100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011001; output <= "000000";
end if;
when s01000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011001; output <= "000000";
end if;
when s01000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011010; output <= "000000";
end if;
when s01000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011010; output <= "000000";
end if;
when s10001100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000000; output <= "010100";
end if;
when s10001100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000011; output <= "010100";
end if;
when s00001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011011; output <= "000000";
end if;
when s10000100011000 =>
if std_match(input, "001") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000000; output <= "010100";
end if;
when s10000100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000011; output <= "010100";
end if;
when s10000100011011 =>
if std_match(input, "011") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000000 =>
if std_match(input, "011") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10010001100011 =>
if std_match(input, "001") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
end if;
when s10010001100001 =>
if std_match(input, "000") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00001010010001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000000011000; output <= "001100";
end if;
when s10000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "010100";
end if;
when s01000001100010 =>
if std_match(input, "000") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100010 =>
if std_match(input, "000") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100000; output <= "100001";
end if;
when s11000001100011 =>
if std_match(input, "010") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100010 =>
if std_match(input, "001") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100011 =>
if std_match(input, "011") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100000 =>
if std_match(input, "001") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100001; output <= "100001";
end if;
when s11000001100001 =>
if std_match(input, "001") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "100001";
end if;
when s10000000011011 =>
if std_match(input, "001") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "100001";
end if;
when s01001001100000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100001; output <= "100001";
end if;
when s11001001100010 =>
if std_match(input, "001") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01001001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "100001";
end if;
when s10000000011001 =>
if std_match(input, "010") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10000000011000 =>
if std_match(input, "000") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s00001010010000 =>
if std_match(input, "000") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s10001000011000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "010100";
end if;
when s01001000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100000; output <= "010100";
end if;
when s01001000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "010100";
end if;
when s01001000011001 =>
if std_match(input, "001") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001000011000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10001000011001 =>
if std_match(input, "001") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s01000000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "010100";
end if;
when s01000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "010100";
end if;
when s01000000011001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "010100";
end if;
when s01000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "010100";
end if;
when s10001000011011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "010100";
end if;
when s10001000011010 =>
if std_match(input, "000") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s00001010010011 =>
if std_match(input, "010") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00001010010010 =>
if std_match(input, "000") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00000010010000 =>
if std_match(input, "011") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s10000001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100000; output <= "100001";
end if;
when s10010001100000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00011001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100010; output <= "100001";
end if;
when s10011001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100011; output <= "100001";
end if;
when s00000001100001 =>
if std_match(input, "010") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10001001100000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "100001";
end if;
when s10001001100001 =>
if std_match(input, "000") then next_state <= s01000000011001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100010 =>
if std_match(input, "010") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "100001";
end if;
when s00000001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100001";
end if;
when s00000001100011 =>
if std_match(input, "011") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100000 =>
if std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "110") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "-00") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100010 =>
if std_match(input, "000") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "1-0") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100001; output <= "100001";
end if;
when s00011001100011 =>
if std_match(input, "011") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100011; output <= "100001";
end if;
when s11101001100001 =>
if std_match(input, "000") then next_state <= s00010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00010001100001 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100001";
end if;
when s10011010010000 =>
if std_match(input, "011") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010000; output <= "001100";
end if;
when s00000010010011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "001100";
end if;
when s00000010010010 =>
if std_match(input, "011") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s00000010010001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "001100";
end if;
when s10011010010001 =>
if std_match(input, "001") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "100") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "-10") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010010 =>
if std_match(input, "000") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "111") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "-01") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010011 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010010; output <= "001100";
end if;
when s00010001100000 =>
if std_match(input, "011") then next_state <= s10010010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s10010010010011 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
end if;
when s10010010010010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "001100";
end if;
when s10010010010000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s10010010010001 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s00010001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100001";
end if;
when s10011100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000001; output <= "010100";
end if;
when s00000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011000; output <= "000000";
end if;
when s00000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011010; output <= "000000";
end if;
when s00000100000000 =>
if std_match(input, "001") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011010; output <= "000000";
end if;
when s10011100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000001; output <= "010100";
end if;
when s10011100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000011; output <= "010100";
end if;
when s10011100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000001; output <= "010100";
end if;
when s11101001100000 =>
if std_match(input, "011") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100001 =>
if std_match(input, "000") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11100001100001 =>
if std_match(input, "001") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s00011000100111 =>
if std_match(input, "000") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10010000100111 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
end if;
when s10010000100110 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100010";
end if;
when s10010000100101 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
end if;
when s10010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100010";
end if;
when s00011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100100; output <= "100010";
end if;
when s10011000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100111; output <= "100010";
end if;
when s00000000100101 =>
if std_match(input, "001") then next_state <= s10001001100011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
end if;
when s00000000100110 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100010";
end if;
when s00000000100111 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100010";
end if;
when s10011000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100101 =>
if std_match(input, "011") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "1-1") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "1-0") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100101 =>
if std_match(input, "000") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100001100000 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100111; output <= "100001";
end if;
when s00010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010010010011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100010";
end if;
when s00010000100101 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100010";
end if;
when s00010000100110 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "100010";
end if;
when s10010100011000 =>
if std_match(input, "010") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011001 =>
if std_match(input, "010") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "010100";
end if;
when s00010000100111 =>
if std_match(input, "011") then next_state <= s10011100011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
end if;
when s11100001100010 =>
if std_match(input, "001") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100001100011 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100001";
end if;
when s01101001100011 =>
if std_match(input, "000") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100000 =>
if std_match(input, "011") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100011 =>
if std_match(input, "010") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100100; output <= "100010";
end if;
when s11101000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100110; output <= "100010";
end if;
when s11101000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100100; output <= "100010";
end if;
when s01100001100010 =>
if std_match(input, "010") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100000100111 =>
if std_match(input, "011") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100010";
end if;
when s11100000100100 =>
if std_match(input, "011") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100010";
end if;
when s01100001100000 =>
if std_match(input, "001") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s10100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100000; output <= "100001";
end if;
when s10101001100011 =>
if std_match(input, "001") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100010; output <= "100001";
end if;
when s10101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100010; output <= "100001";
end if;
when s10100100011000 =>
if std_match(input, "001") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011000; output <= "000000";
end if;
when s11100100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000011; output <= "010100";
end if;
when s00011100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011000; output <= "000000";
end if;
when s00011100000000 =>
if std_match(input, "000") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00011100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011001; output <= "000000";
end if;
when s00011100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011010; output <= "000000";
end if;
when s11100100011010 =>
if std_match(input, "001") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00010100000000 =>
if std_match(input, "010") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011000; output <= "000000";
end if;
when s00010100000010 =>
if std_match(input, "001") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000011 =>
if std_match(input, "000") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000010; output <= "010100";
end if;
when s11100100011000 =>
if std_match(input, "010") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011011; output <= "000000";
end if;
when s11101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000001; output <= "010100";
end if;
when s11101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000001; output <= "010100";
end if;
when s11101100011010 =>
if std_match(input, "011") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000000; output <= "010100";
end if;
when s01100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011011; output <= "000000";
end if;
when s01100100000000 =>
if std_match(input, "000") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000010; output <= "010100";
end if;
when s01101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011000; output <= "000000";
end if;
when s01101100000001 =>
if std_match(input, "011") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s01101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011001; output <= "000000";
end if;
when s01101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011010; output <= "000000";
end if;
when s10100100011011 =>
if std_match(input, "011") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10100100011010 =>
if std_match(input, "001") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000010; output <= "010100";
end if;
when s10101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000010; output <= "010100";
end if;
when s10101100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000000; output <= "010100";
end if;
when s10101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000011; output <= "010100";
end if;
when others => next_state <= "--------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 1cc1c0959a1596e3a4337e5b9957bd82 | 0.644434 | 3.947397 | false | false | false | false |
chastell/art-decomp | kiss/s8_hot.vhd | 1 | 2,626 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s8_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s8_hot;
architecture behaviour of s8_hot is
constant s1: std_logic_vector(4 downto 0) := "10000";
constant s2: std_logic_vector(4 downto 0) := "01000";
constant s3: std_logic_vector(4 downto 0) := "00100";
constant s5: std_logic_vector(4 downto 0) := "00010";
constant s4: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-";
case current_state is
when s1 =>
if std_match(input, "1000") then next_state <= s1; output <= "1";
elsif std_match(input, "0100") then next_state <= s1; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s2; output <= "1";
end if;
when s2 =>
if std_match(input, "1000") then next_state <= s2; output <= "1";
elsif std_match(input, "0100") then next_state <= s3; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s1; output <= "1";
end if;
when s3 =>
if std_match(input, "1000") then next_state <= s3; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s5; output <= "1";
end if;
when s4 =>
if std_match(input, "1000") then next_state <= s4; output <= "1";
elsif std_match(input, "0100") then next_state <= s2; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s3; output <= "1";
end if;
when s5 =>
if std_match(input, "1000") then next_state <= s5; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s1; output <= "1";
elsif std_match(input, "0001") then next_state <= s4; output <= "1";
end if;
when others => next_state <= "-----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | b4d40d92d920156106b6f1657ec73ad2 | 0.583397 | 3.218137 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/GFMap.vhd | 2 | 749 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity gfmap is port (
-- a -> Data Input (8 std_logic)
-- ah -> High Data Output (mapped) (4 std_logic)
-- al -> Low Data Output (mapped) (4 std_logic)
a : in std_logic_vector (7 downto 0);
ah, al : out std_logic_vector (3 downto 0));
end gfmap;
-- Architecture of the Component
architecture a_gfmap of gfmap is
begin
-- Mapping Process
ah(3) <= a(5) xor a(7);
ah(2) <= a(5) xor a(7) xor a(2) xor a(3);
ah(1) <= a(1) xor a(7) xor a(4) xor a(6);
ah(0) <= a(4) xor a(6) xor a(5);
al(3) <= a(2) xor a(4);
al(2) <= a(1) xor a(7);
al(1) <= a(1) xor a(2);
al(0) <= a(4) xor a(6) xor a(5) xor a(0);
end a_gfmap;
| mit | 6c0c84f69712b048eda2d277719e6b27 | 0.568758 | 2.521886 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/linear.vhd | 2 | 2,559 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- Linear layer of the AES:
-- + key addition when deciphering
-- + mixcolumns operation
-- + stabilization layer for synchronization
-- + key addition during loading and encryption
-----------------------------------------------------------------------
-- Component Declaration
entity linear is
generic ( G_ROW : integer range 0 to 3 );
port (
b_in : in std_logic_vector (7 downto 0);
out_2_mc : out std_logic_vector (7 downto 0);
in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
h_in : in std_logic_vector (7 downto 0);
round_key : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
clock : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end linear;
-- Architecture of the Component
architecture a_linear of linear is
component mixcolumn is
generic( G_ROW : integer range 0 to 3 );
port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
ctrl_dec : in T_ENCDEC;
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
signal data_in, mc_out, addkey_in, key_in_post_mc, addkey_out_post_mc : std_logic_vector (7 downto 0);
signal mc_input, key_in_pre_mc : std_logic_vector (7 downto 0);
begin
dec0 : if ( not C_INCLUDE_DECODING_LOGIC ) generate
mc_input <= b_in;
end generate; -- not C_INCLUDE_DECODING_LOGIC
dec1 : if ( C_INCLUDE_DECODING_LOGIC ) generate
key_in_pre_mc <= round_key when ( enable_key_pre_add = C_ENABLE ) else ( others=>'0' );
mc_input <= b_in xor key_in_pre_mc;
end generate; -- C_INCLUDE_DECODING_LOGIC
out_2_mc <= mc_input;
mc : mixcolumn generic map( G_ROW )
port map( mc_input, in_1, in_2, in_3,
ctrl_dec, mc_out );
data_in <= b_in when ( enable_H_in = C_DISABLE ) else h_in;
--- STABILIZATION OF DATA
STAB_PROC : process( clock, mc_out, enable_MixCol, data_in )
begin
if ( clock='1' ) then
if ( enable_MixCol = C_ENABLE ) then
addkey_in <= mc_out;
else
addkey_in <= data_in;
end if;
end if; -- clock
end process STAB_PROC;
key_in_post_mc <= round_key when ( enable_key_add = C_ENABLE ) else ( others=>'0' );
addkey_out_post_mc <= addkey_in xor key_in_post_mc;
b_out <= addkey_out_post_mc;
end a_linear;
| mit | a26a59859f6738d871b73d8e9fafc4fa | 0.586166 | 3.293436 | false | false | false | false |
chastell/art-decomp | kiss/ex6_jed.vhd | 1 | 4,231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_jed is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_jed;
architecture behaviour of ex6_jed is
constant s1: std_logic_vector(2 downto 0) := "000";
constant s3: std_logic_vector(2 downto 0) := "010";
constant s2: std_logic_vector(2 downto 0) := "111";
constant s4: std_logic_vector(2 downto 0) := "110";
constant s5: std_logic_vector(2 downto 0) := "001";
constant s6: std_logic_vector(2 downto 0) := "011";
constant s7: std_logic_vector(2 downto 0) := "100";
constant s8: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "---"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | 002e6e5a79d40286d17282e33858ef55 | 0.579532 | 3.379393 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-07C.vhd | 1 | 4,234 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- A Register Assembly
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ARegAssm IS
port
(
-- Inputs
USE_MANUAL_DECODER : IN STD_LOGIC; -- 03D
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02A
E_SEL_SW_BUS : IN E_SW_BUS_Type; -- 04C
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
CHK_SW_DISABLE : IN STD_LOGIC; -- 04A
S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B
MC_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 7); -- 07A
Q_REG : IN STD_LOGIC_VECTOR(0 to 8); -- 08B
SEL_CHNL_GJ_BUS : IN STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- 11B
GT_GJ_TO_A_REG : IN STD_LOGIC := '0'; -- 12C
-- Outputs
-- GT_DDC_TO_A_BUS : OUT STD_LOGIC; -- 07A
GT_Q_REG_TO_A_BUS : OUT STD_LOGIC; -- 07A
A_BUS : INOUT STD_LOGIC_VECTOR(0 to 8)
);
END ARegAssm;
ARCHITECTURE FMD OF ARegAssm IS
signal GT_MC_REG_TO_A_BUS : STD_LOGIC;
signal sGT_Q_REG_TO_A_BUS : STD_LOGIC;
signal sGT_DDC_TO_A_BUS : STD_LOGIC;
signal GT_S_REG_TO_A : STD_LOGIC;
signal JI_REG : STD_LOGIC_VECTOR(0 to 8) := "000000000"; -- BE3D5
BEGIN
-- Fig 5-07C
GT_MC_REG_TO_A_BUS <= '1' when USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0010" else '0'; -- AB1F5
sGT_Q_REG_TO_A_BUS <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.Q_SEL='1') or (USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0101") else '0'; -- AB3C7
GT_Q_REG_TO_A_BUS <= sGT_Q_REG_TO_A_BUS;
sGT_DDC_TO_A_BUS <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.JI_SEL='1') or (USE_ALT_CA_DECODER='1' and GTD_CA_BITS="0110") else '0'; -- AB3C7
-- GT_DDC_TO_A_BUS <= sGT_DDC_TO_A_BUS;
GT_S_REG_TO_A <= '1' when (USE_MANUAL_DECODER='1' and E_SEL_SW_BUS.S_SEL='1') or (USE_BASIC_CA_DECO='1' and GTD_CA_BITS="0100") else '0'; -- AB3C3
A_BUS <= not(S & '0') when GT_S_REG_TO_A='1' else
not(MC_CTRL_REG & '0') when GT_MC_REG_TO_A_BUS='1' and CHK_SW_DISABLE='0' else -- ABJK6 AB3L6
not JI_REG when sGT_DDC_TO_A_BUS='1' else
not SEL_CHNL_GJ_BUS when GT_GJ_TO_A_REG='1' else
not Q_REG when sGT_Q_REG_TO_A_BUS='1' else -- AC2D2
"111111111";
-- A_REG_BUS_2 <= ((S & '0') and (A_REG_BUS_2'range => GT_S_REG_TO_A)) or ((MC_CTRL_REG & '0') and (A_REG_BUS_2'range => (GT_MC_REG_TO_A_BUS and not CHK_SW_DISABLE))); -- ABJK6 AB3L6
-- A_REG_BUS_3 <= (JI_REG and (A_REG_BUS_3'range => sGT_DDC_TO_A_BUS)) or (SEL_CHNL_GJ_BUS and (A_REG_BUS_3'range => GT_GJ_TO_A_REG)) or (Q_REG and (A_REG_BUS_3'range => GT_Q_REG_TO_A_BUS)); -- AC2D2
END FMD;
| gpl-3.0 | aae8eb6afca3f0117f3f0cae737214f0 | 0.59589 | 2.649562 | false | false | false | false |
chastell/art-decomp | kiss/s298_jed.vhd | 1 | 128,772 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_jed;
architecture behaviour of s298_jed is
constant s00000000000000: std_logic_vector(7 downto 0) := "00110101";
constant s00000001100000: std_logic_vector(7 downto 0) := "00100101";
constant s10000001100010: std_logic_vector(7 downto 0) := "00011010";
constant s10000001100011: std_logic_vector(7 downto 0) := "00010110";
constant s10000001100001: std_logic_vector(7 downto 0) := "00000110";
constant s10000001100000: std_logic_vector(7 downto 0) := "00011000";
constant s01000001100001: std_logic_vector(7 downto 0) := "00100111";
constant s01000001100000: std_logic_vector(7 downto 0) := "00111001";
constant s01000001100011: std_logic_vector(7 downto 0) := "00110110";
constant s01000001100010: std_logic_vector(7 downto 0) := "00111000";
constant s11001001100011: std_logic_vector(7 downto 0) := "00000000";
constant s11001001100010: std_logic_vector(7 downto 0) := "00000010";
constant s11001001100000: std_logic_vector(7 downto 0) := "00010010";
constant s11001001100001: std_logic_vector(7 downto 0) := "00000100";
constant s00100001100011: std_logic_vector(7 downto 0) := "01001011";
constant s00100001100010: std_logic_vector(7 downto 0) := "01011011";
constant s00100001100001: std_logic_vector(7 downto 0) := "01000001";
constant s00100001100000: std_logic_vector(7 downto 0) := "01000011";
constant s10101001100010: std_logic_vector(7 downto 0) := "00110001";
constant s10101001100011: std_logic_vector(7 downto 0) := "00010011";
constant s10101001100000: std_logic_vector(7 downto 0) := "01010001";
constant s10101001100001: std_logic_vector(7 downto 0) := "01010011";
constant s01101001100010: std_logic_vector(7 downto 0) := "10001010";
constant s01101001100011: std_logic_vector(7 downto 0) := "10101010";
constant s01101001100001: std_logic_vector(7 downto 0) := "10001110";
constant s01101001100000: std_logic_vector(7 downto 0) := "10001100";
constant s11101001100011: std_logic_vector(7 downto 0) := "11011111";
constant s11101001100010: std_logic_vector(7 downto 0) := "11011011";
constant s11101001100000: std_logic_vector(7 downto 0) := "11011101";
constant s11101001100001: std_logic_vector(7 downto 0) := "11010111";
constant s00010001100010: std_logic_vector(7 downto 0) := "10100011";
constant s00010001100011: std_logic_vector(7 downto 0) := "01100001";
constant s00010001100000: std_logic_vector(7 downto 0) := "11000011";
constant s00010001100001: std_logic_vector(7 downto 0) := "11000001";
constant s10010100011010: std_logic_vector(7 downto 0) := "00011101";
constant s10010100011011: std_logic_vector(7 downto 0) := "00001101";
constant s10010100011000: std_logic_vector(7 downto 0) := "00001001";
constant s10010100011001: std_logic_vector(7 downto 0) := "00011111";
constant s00000000011000: std_logic_vector(7 downto 0) := "01100101";
constant s00001100000001: std_logic_vector(7 downto 0) := "00001010";
constant s00001100000000: std_logic_vector(7 downto 0) := "00001000";
constant s00001100000010: std_logic_vector(7 downto 0) := "00001100";
constant s00001100000011: std_logic_vector(7 downto 0) := "00001110";
constant s10000100011001: std_logic_vector(7 downto 0) := "01001101";
constant s10000100011000: std_logic_vector(7 downto 0) := "01001001";
constant s10000100011010: std_logic_vector(7 downto 0) := "10001111";
constant s10000100011011: std_logic_vector(7 downto 0) := "01001111";
constant s10100001100010: std_logic_vector(7 downto 0) := "01010100";
constant s10100001100011: std_logic_vector(7 downto 0) := "11010100";
constant s10100001100001: std_logic_vector(7 downto 0) := "11010000";
constant s10100001100000: std_logic_vector(7 downto 0) := "01010000";
constant s01100001100001: std_logic_vector(7 downto 0) := "00101111";
constant s01100001100000: std_logic_vector(7 downto 0) := "00101101";
constant s01100001100011: std_logic_vector(7 downto 0) := "00111111";
constant s01100001100010: std_logic_vector(7 downto 0) := "00101100";
constant s11101000100110: std_logic_vector(7 downto 0) := "01110111";
constant s11101000100111: std_logic_vector(7 downto 0) := "01111001";
constant s11101000100101: std_logic_vector(7 downto 0) := "01110001";
constant s11101000100100: std_logic_vector(7 downto 0) := "01110101";
constant s00000000100100: std_logic_vector(7 downto 0) := "00100100";
constant s00011000100110: std_logic_vector(7 downto 0) := "00001111";
constant s00011000100111: std_logic_vector(7 downto 0) := "00001011";
constant s00011000100101: std_logic_vector(7 downto 0) := "00011011";
constant s00011000100100: std_logic_vector(7 downto 0) := "00000011";
constant s10011000100100: std_logic_vector(7 downto 0) := "10111010";
constant s10011000100101: std_logic_vector(7 downto 0) := "10111110";
constant s10011000100111: std_logic_vector(7 downto 0) := "10110110";
constant s10011000100110: std_logic_vector(7 downto 0) := "10111100";
constant s00000000100111: std_logic_vector(7 downto 0) := "00101000";
constant s00000000100110: std_logic_vector(7 downto 0) := "00100000";
constant s00000000100101: std_logic_vector(7 downto 0) := "01100100";
constant s01001001100011: std_logic_vector(7 downto 0) := "01011001";
constant s01001001100010: std_logic_vector(7 downto 0) := "00010111";
constant s01001001100000: std_logic_vector(7 downto 0) := "01000111";
constant s01001001100001: std_logic_vector(7 downto 0) := "10011000";
constant s11000001100000: std_logic_vector(7 downto 0) := "00011110";
constant s11000001100001: std_logic_vector(7 downto 0) := "00010000";
constant s11000001100011: std_logic_vector(7 downto 0) := "00010100";
constant s11000001100010: std_logic_vector(7 downto 0) := "00011100";
constant s00011001100001: std_logic_vector(7 downto 0) := "11100010";
constant s00011001100000: std_logic_vector(7 downto 0) := "10110000";
constant s00011001100011: std_logic_vector(7 downto 0) := "10100010";
constant s00011001100010: std_logic_vector(7 downto 0) := "11011000";
constant s10010001100010: std_logic_vector(7 downto 0) := "11000101";
constant s10010001100011: std_logic_vector(7 downto 0) := "11001001";
constant s10010001100001: std_logic_vector(7 downto 0) := "11001101";
constant s10010001100000: std_logic_vector(7 downto 0) := "11000111";
constant s10001100011000: std_logic_vector(7 downto 0) := "01101011";
constant s10001100011001: std_logic_vector(7 downto 0) := "01101111";
constant s10001100011011: std_logic_vector(7 downto 0) := "01101100";
constant s10001100011010: std_logic_vector(7 downto 0) := "01101110";
constant s01001100000001: std_logic_vector(7 downto 0) := "00110010";
constant s01001100000000: std_logic_vector(7 downto 0) := "00110011";
constant s01001100000010: std_logic_vector(7 downto 0) := "00111011";
constant s01001100000011: std_logic_vector(7 downto 0) := "00111010";
constant s11000100011001: std_logic_vector(7 downto 0) := "11001110";
constant s11000100011000: std_logic_vector(7 downto 0) := "11011010";
constant s11000100011010: std_logic_vector(7 downto 0) := "11001100";
constant s11000100011011: std_logic_vector(7 downto 0) := "11011110";
constant s00101100000000: std_logic_vector(7 downto 0) := "10001101";
constant s00101100000001: std_logic_vector(7 downto 0) := "10000100";
constant s00101100000010: std_logic_vector(7 downto 0) := "10011101";
constant s00101100000011: std_logic_vector(7 downto 0) := "10000101";
constant s10101100011001: std_logic_vector(7 downto 0) := "11000000";
constant s10101100011000: std_logic_vector(7 downto 0) := "11000010";
constant s10101100011010: std_logic_vector(7 downto 0) := "10000010";
constant s10101100011011: std_logic_vector(7 downto 0) := "11000100";
constant s10100100011011: std_logic_vector(7 downto 0) := "01111110";
constant s10100100011010: std_logic_vector(7 downto 0) := "01111010";
constant s10100100011001: std_logic_vector(7 downto 0) := "01111000";
constant s10100100011000: std_logic_vector(7 downto 0) := "01111100";
constant s00100100000011: std_logic_vector(7 downto 0) := "01100000";
constant s00100100000010: std_logic_vector(7 downto 0) := "00110000";
constant s00100100000001: std_logic_vector(7 downto 0) := "01110000";
constant s00100100000000: std_logic_vector(7 downto 0) := "01110100";
constant s11001100011000: std_logic_vector(7 downto 0) := "01100010";
constant s11001100011001: std_logic_vector(7 downto 0) := "00100010";
constant s11001100011010: std_logic_vector(7 downto 0) := "11001010";
constant s11001100011011: std_logic_vector(7 downto 0) := "01101010";
constant s01000100000000: std_logic_vector(7 downto 0) := "10010101";
constant s01000100000001: std_logic_vector(7 downto 0) := "10010001";
constant s01000100000010: std_logic_vector(7 downto 0) := "00010101";
constant s01000100000011: std_logic_vector(7 downto 0) := "10000001";
constant s00001010010001: std_logic_vector(7 downto 0) := "00101010";
constant s00001010010000: std_logic_vector(7 downto 0) := "01001110";
constant s00001010010011: std_logic_vector(7 downto 0) := "01001010";
constant s00001010010010: std_logic_vector(7 downto 0) := "01011010";
constant s00000010010000: std_logic_vector(7 downto 0) := "00100001";
constant s10000000011010: std_logic_vector(7 downto 0) := "11010101";
constant s10000000011011: std_logic_vector(7 downto 0) := "11010001";
constant s10000000011001: std_logic_vector(7 downto 0) := "11011001";
constant s10000000011000: std_logic_vector(7 downto 0) := "11010011";
constant s00101001100010: std_logic_vector(7 downto 0) := "11010010";
constant s00101001100011: std_logic_vector(7 downto 0) := "01110110";
constant s00101001100000: std_logic_vector(7 downto 0) := "01110010";
constant s00101001100001: std_logic_vector(7 downto 0) := "01010010";
constant s10001000011000: std_logic_vector(7 downto 0) := "11001011";
constant s10001000011001: std_logic_vector(7 downto 0) := "11001111";
constant s10001000011011: std_logic_vector(7 downto 0) := "11101110";
constant s10001000011010: std_logic_vector(7 downto 0) := "11011100";
constant s01001000011011: std_logic_vector(7 downto 0) := "00100110";
constant s01001000011010: std_logic_vector(7 downto 0) := "01101000";
constant s01001000011001: std_logic_vector(7 downto 0) := "01100110";
constant s01001000011000: std_logic_vector(7 downto 0) := "11001000";
constant s01000000011011: std_logic_vector(7 downto 0) := "10001001";
constant s01000000011010: std_logic_vector(7 downto 0) := "11000110";
constant s01000000011001: std_logic_vector(7 downto 0) := "10001000";
constant s01000000011000: std_logic_vector(7 downto 0) := "10000110";
constant s10011001100001: std_logic_vector(7 downto 0) := "01111111";
constant s10011001100000: std_logic_vector(7 downto 0) := "01101101";
constant s10011001100011: std_logic_vector(7 downto 0) := "01100111";
constant s10011001100010: std_logic_vector(7 downto 0) := "01111101";
constant s00000001100001: std_logic_vector(7 downto 0) := "00111101";
constant s00000001100010: std_logic_vector(7 downto 0) := "00110100";
constant s00000001100011: std_logic_vector(7 downto 0) := "00110111";
constant s10001001100000: std_logic_vector(7 downto 0) := "00000111";
constant s10001001100001: std_logic_vector(7 downto 0) := "01011000";
constant s10001001100010: std_logic_vector(7 downto 0) := "01000110";
constant s10001001100011: std_logic_vector(7 downto 0) := "00011001";
constant s10011010010000: std_logic_vector(7 downto 0) := "10100100";
constant s10011010010001: std_logic_vector(7 downto 0) := "10101100";
constant s10011010010010: std_logic_vector(7 downto 0) := "10100000";
constant s10011010010011: std_logic_vector(7 downto 0) := "10101000";
constant s00000010010011: std_logic_vector(7 downto 0) := "00101011";
constant s00000010010010: std_logic_vector(7 downto 0) := "00101001";
constant s00000010010001: std_logic_vector(7 downto 0) := "00100011";
constant s10010010010011: std_logic_vector(7 downto 0) := "01110011";
constant s10010010010010: std_logic_vector(7 downto 0) := "01111011";
constant s10010010010000: std_logic_vector(7 downto 0) := "01101001";
constant s10010010010001: std_logic_vector(7 downto 0) := "01100011";
constant s10011100011000: std_logic_vector(7 downto 0) := "01000010";
constant s10011100011001: std_logic_vector(7 downto 0) := "00010001";
constant s10011100011011: std_logic_vector(7 downto 0) := "00000001";
constant s10011100011010: std_logic_vector(7 downto 0) := "00000101";
constant s00000100000010: std_logic_vector(7 downto 0) := "10010100";
constant s00000100000011: std_logic_vector(7 downto 0) := "10010010";
constant s00000100000000: std_logic_vector(7 downto 0) := "10010000";
constant s00000100000001: std_logic_vector(7 downto 0) := "10000000";
constant s11100001100001: std_logic_vector(7 downto 0) := "10101001";
constant s11100001100000: std_logic_vector(7 downto 0) := "10101111";
constant s11100001100010: std_logic_vector(7 downto 0) := "10100111";
constant s11100001100011: std_logic_vector(7 downto 0) := "10101011";
constant s10010000100111: std_logic_vector(7 downto 0) := "11101010";
constant s10010000100110: std_logic_vector(7 downto 0) := "10100110";
constant s10010000100101: std_logic_vector(7 downto 0) := "11101000";
constant s10010000100100: std_logic_vector(7 downto 0) := "11100110";
constant s00010000100100: std_logic_vector(7 downto 0) := "01001100";
constant s00010000100101: std_logic_vector(7 downto 0) := "01000000";
constant s00010000100110: std_logic_vector(7 downto 0) := "01001000";
constant s00010000100111: std_logic_vector(7 downto 0) := "01000100";
constant s11100000100111: std_logic_vector(7 downto 0) := "10110010";
constant s11100000100110: std_logic_vector(7 downto 0) := "10111000";
constant s11100000100100: std_logic_vector(7 downto 0) := "10011001";
constant s11100000100101: std_logic_vector(7 downto 0) := "10110100";
constant s01100100000010: std_logic_vector(7 downto 0) := "10001011";
constant s01100100000011: std_logic_vector(7 downto 0) := "10000111";
constant s01100100000001: std_logic_vector(7 downto 0) := "10000011";
constant s01100100000000: std_logic_vector(7 downto 0) := "10010011";
constant s11100100011011: std_logic_vector(7 downto 0) := "01011101";
constant s11100100011010: std_logic_vector(7 downto 0) := "01011111";
constant s11100100011001: std_logic_vector(7 downto 0) := "01011100";
constant s11100100011000: std_logic_vector(7 downto 0) := "01011110";
constant s00011100000001: std_logic_vector(7 downto 0) := "10010110";
constant s00011100000000: std_logic_vector(7 downto 0) := "10011110";
constant s00011100000010: std_logic_vector(7 downto 0) := "11010110";
constant s00011100000011: std_logic_vector(7 downto 0) := "10010111";
constant s00010100000000: std_logic_vector(7 downto 0) := "10011011";
constant s00010100000001: std_logic_vector(7 downto 0) := "10011100";
constant s00010100000010: std_logic_vector(7 downto 0) := "10011010";
constant s00010100000011: std_logic_vector(7 downto 0) := "10011111";
constant s11101100011001: std_logic_vector(7 downto 0) := "01010110";
constant s11101100011000: std_logic_vector(7 downto 0) := "01010101";
constant s11101100011010: std_logic_vector(7 downto 0) := "01000101";
constant s11101100011011: std_logic_vector(7 downto 0) := "01010111";
constant s01101100000000: std_logic_vector(7 downto 0) := "00111110";
constant s01101100000001: std_logic_vector(7 downto 0) := "00101110";
constant s01101100000011: std_logic_vector(7 downto 0) := "00111100";
constant s01101100000010: std_logic_vector(7 downto 0) := "10101110";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "------";
case current_state is
when s00000000000000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "000000";
end if;
when s00000001100000 =>
if std_match(input, "000") then next_state <= s10000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10000001100000 =>
if std_match(input, "010") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100001 =>
if std_match(input, "001") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100011 =>
if std_match(input, "000") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100011 =>
if std_match(input, "010") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100010 =>
if std_match(input, "000") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100001; output <= "100001";
end if;
when s11101001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100001; output <= "100001";
end if;
when s00010001100010 =>
if std_match(input, "000") then next_state <= s10010100011010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10010100011010 =>
if std_match(input, "011") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011011; output <= "000000";
end if;
when s00000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "010100";
end if;
when s10000001100010 =>
if std_match(input, "010") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "100001";
end if;
when s11001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100010; output <= "100001";
end if;
when s00100001100000 =>
if std_match(input, "001") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100010 =>
if std_match(input, "011") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100001 =>
if std_match(input, "011") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100110 =>
if std_match(input, "000") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100110 =>
if std_match(input, "001") then next_state <= s10011000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100100; output <= "100010";
end if;
when s00000000100100 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100010";
end if;
when s10000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100001; output <= "100001";
end if;
when s01001001100011 =>
if std_match(input, "011") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100000; output <= "100001";
end if;
when s00100001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100001; output <= "100001";
end if;
when s10100001100011 =>
if std_match(input, "011") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100000; output <= "100001";
end if;
when s11101001100010 =>
if std_match(input, "011") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100001 =>
if std_match(input, "011") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10010001100010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100001";
end if;
when s00001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011010; output <= "000000";
end if;
when s10001100011000 =>
if std_match(input, "010") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011011; output <= "000000";
end if;
when s11000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000011; output <= "010100";
end if;
when s00101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000001 =>
if std_match(input, "001") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011010; output <= "000000";
end if;
when s11000100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000000; output <= "010100";
end if;
when s00100100000011 =>
if std_match(input, "011") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011010; output <= "000000";
end if;
when s00100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011011; output <= "000000";
end if;
when s00100100000000 =>
if std_match(input, "000") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11000100011010 =>
if std_match(input, "011") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11000100011011 =>
if std_match(input, "010") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000000 =>
if std_match(input, "000") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11001100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000011; output <= "010100";
end if;
when s11001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000010; output <= "010100";
end if;
when s11001100011010 =>
if std_match(input, "000") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11001100011011 =>
if std_match(input, "001") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011001; output <= "000000";
end if;
when s01001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011010; output <= "000000";
end if;
when s10001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000011; output <= "010100";
end if;
when s01000100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011001; output <= "000000";
end if;
when s01000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011001; output <= "000000";
end if;
when s01000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011010; output <= "000000";
end if;
when s01000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011010; output <= "000000";
end if;
when s10001100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000000; output <= "010100";
end if;
when s10001100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000011; output <= "010100";
end if;
when s00001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011011; output <= "000000";
end if;
when s10000100011000 =>
if std_match(input, "001") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000000; output <= "010100";
end if;
when s10000100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000011; output <= "010100";
end if;
when s10000100011011 =>
if std_match(input, "011") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000000 =>
if std_match(input, "011") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10010001100011 =>
if std_match(input, "001") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
end if;
when s10010001100001 =>
if std_match(input, "000") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00001010010001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000000011000; output <= "001100";
end if;
when s10000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "010100";
end if;
when s01000001100010 =>
if std_match(input, "000") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100010 =>
if std_match(input, "000") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100000; output <= "100001";
end if;
when s11000001100011 =>
if std_match(input, "010") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100010 =>
if std_match(input, "001") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100011 =>
if std_match(input, "011") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100000 =>
if std_match(input, "001") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100001; output <= "100001";
end if;
when s11000001100001 =>
if std_match(input, "001") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "100001";
end if;
when s10000000011011 =>
if std_match(input, "001") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "100001";
end if;
when s01001001100000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100001; output <= "100001";
end if;
when s11001001100010 =>
if std_match(input, "001") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01001001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "100001";
end if;
when s10000000011001 =>
if std_match(input, "010") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10000000011000 =>
if std_match(input, "000") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s00001010010000 =>
if std_match(input, "000") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s10001000011000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "010100";
end if;
when s01001000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100000; output <= "010100";
end if;
when s01001000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "010100";
end if;
when s01001000011001 =>
if std_match(input, "001") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001000011000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10001000011001 =>
if std_match(input, "001") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s01000000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "010100";
end if;
when s01000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "010100";
end if;
when s01000000011001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "010100";
end if;
when s01000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "010100";
end if;
when s10001000011011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "010100";
end if;
when s10001000011010 =>
if std_match(input, "000") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s00001010010011 =>
if std_match(input, "010") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00001010010010 =>
if std_match(input, "000") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00000010010000 =>
if std_match(input, "011") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s10000001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100000; output <= "100001";
end if;
when s10010001100000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00011001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100010; output <= "100001";
end if;
when s10011001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100011; output <= "100001";
end if;
when s00000001100001 =>
if std_match(input, "010") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10001001100000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "100001";
end if;
when s10001001100001 =>
if std_match(input, "000") then next_state <= s01000000011001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100010 =>
if std_match(input, "010") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "100001";
end if;
when s00000001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100001";
end if;
when s00000001100011 =>
if std_match(input, "011") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100000 =>
if std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "110") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "-00") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100010 =>
if std_match(input, "000") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "1-0") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100001; output <= "100001";
end if;
when s00011001100011 =>
if std_match(input, "011") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100011; output <= "100001";
end if;
when s11101001100001 =>
if std_match(input, "000") then next_state <= s00010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00010001100001 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100001";
end if;
when s10011010010000 =>
if std_match(input, "011") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010000; output <= "001100";
end if;
when s00000010010011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "001100";
end if;
when s00000010010010 =>
if std_match(input, "011") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s00000010010001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "001100";
end if;
when s10011010010001 =>
if std_match(input, "001") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "100") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "-10") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010010 =>
if std_match(input, "000") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "111") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "-01") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010011 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010010; output <= "001100";
end if;
when s00010001100000 =>
if std_match(input, "011") then next_state <= s10010010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s10010010010011 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
end if;
when s10010010010010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "001100";
end if;
when s10010010010000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s10010010010001 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s00010001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100001";
end if;
when s10011100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000001; output <= "010100";
end if;
when s00000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011000; output <= "000000";
end if;
when s00000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011010; output <= "000000";
end if;
when s00000100000000 =>
if std_match(input, "001") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011010; output <= "000000";
end if;
when s10011100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000001; output <= "010100";
end if;
when s10011100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000011; output <= "010100";
end if;
when s10011100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000001; output <= "010100";
end if;
when s11101001100000 =>
if std_match(input, "011") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100001 =>
if std_match(input, "000") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11100001100001 =>
if std_match(input, "001") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s00011000100111 =>
if std_match(input, "000") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10010000100111 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
end if;
when s10010000100110 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100010";
end if;
when s10010000100101 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
end if;
when s10010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100010";
end if;
when s00011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100100; output <= "100010";
end if;
when s10011000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100111; output <= "100010";
end if;
when s00000000100101 =>
if std_match(input, "001") then next_state <= s10001001100011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
end if;
when s00000000100110 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100010";
end if;
when s00000000100111 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100010";
end if;
when s10011000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100101 =>
if std_match(input, "011") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "1-1") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "1-0") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100101 =>
if std_match(input, "000") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100001100000 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100111; output <= "100001";
end if;
when s00010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010010010011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100010";
end if;
when s00010000100101 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100010";
end if;
when s00010000100110 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "100010";
end if;
when s10010100011000 =>
if std_match(input, "010") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011001 =>
if std_match(input, "010") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "010100";
end if;
when s00010000100111 =>
if std_match(input, "011") then next_state <= s10011100011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
end if;
when s11100001100010 =>
if std_match(input, "001") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100001100011 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100001";
end if;
when s01101001100011 =>
if std_match(input, "000") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100000 =>
if std_match(input, "011") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100011 =>
if std_match(input, "010") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100100; output <= "100010";
end if;
when s11101000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100110; output <= "100010";
end if;
when s11101000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100100; output <= "100010";
end if;
when s01100001100010 =>
if std_match(input, "010") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100000100111 =>
if std_match(input, "011") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100010";
end if;
when s11100000100100 =>
if std_match(input, "011") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100010";
end if;
when s01100001100000 =>
if std_match(input, "001") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s10100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100000; output <= "100001";
end if;
when s10101001100011 =>
if std_match(input, "001") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100010; output <= "100001";
end if;
when s10101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100010; output <= "100001";
end if;
when s10100100011000 =>
if std_match(input, "001") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011000; output <= "000000";
end if;
when s11100100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000011; output <= "010100";
end if;
when s00011100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011000; output <= "000000";
end if;
when s00011100000000 =>
if std_match(input, "000") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00011100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011001; output <= "000000";
end if;
when s00011100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011010; output <= "000000";
end if;
when s11100100011010 =>
if std_match(input, "001") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00010100000000 =>
if std_match(input, "010") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011000; output <= "000000";
end if;
when s00010100000010 =>
if std_match(input, "001") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000011 =>
if std_match(input, "000") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000010; output <= "010100";
end if;
when s11100100011000 =>
if std_match(input, "010") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011011; output <= "000000";
end if;
when s11101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000001; output <= "010100";
end if;
when s11101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000001; output <= "010100";
end if;
when s11101100011010 =>
if std_match(input, "011") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000000; output <= "010100";
end if;
when s01100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011011; output <= "000000";
end if;
when s01100100000000 =>
if std_match(input, "000") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000010; output <= "010100";
end if;
when s01101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011000; output <= "000000";
end if;
when s01101100000001 =>
if std_match(input, "011") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s01101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011001; output <= "000000";
end if;
when s01101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011010; output <= "000000";
end if;
when s10100100011011 =>
if std_match(input, "011") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10100100011010 =>
if std_match(input, "001") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000010; output <= "010100";
end if;
when s10101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000010; output <= "010100";
end if;
when s10101100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000000; output <= "010100";
end if;
when s10101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000011; output <= "010100";
end if;
when others => next_state <= "--------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 96bf14454c52a13f9bd5e509ea05e064 | 0.644434 | 3.947397 | false | false | false | false |
chastell/art-decomp | kiss/donfile_jed.vhd | 1 | 10,163 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity donfile_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end donfile_jed;
architecture behaviour of donfile_jed is
constant st0: std_logic_vector(4 downto 0) := "10111";
constant st6: std_logic_vector(4 downto 0) := "10110";
constant st12: std_logic_vector(4 downto 0) := "10001";
constant st18: std_logic_vector(4 downto 0) := "10000";
constant st1: std_logic_vector(4 downto 0) := "10101";
constant st7: std_logic_vector(4 downto 0) := "10100";
constant st2: std_logic_vector(4 downto 0) := "11111";
constant st19: std_logic_vector(4 downto 0) := "00000";
constant st3: std_logic_vector(4 downto 0) := "01111";
constant st13: std_logic_vector(4 downto 0) := "01001";
constant st4: std_logic_vector(4 downto 0) := "00101";
constant st5: std_logic_vector(4 downto 0) := "00111";
constant st14: std_logic_vector(4 downto 0) := "11101";
constant st20: std_logic_vector(4 downto 0) := "11100";
constant st8: std_logic_vector(4 downto 0) := "11110";
constant st21: std_logic_vector(4 downto 0) := "11000";
constant st9: std_logic_vector(4 downto 0) := "01110";
constant st15: std_logic_vector(4 downto 0) := "11001";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "00110";
constant st22: std_logic_vector(4 downto 0) := "01000";
constant st23: std_logic_vector(4 downto 0) := "01100";
constant st16: std_logic_vector(4 downto 0) := "00001";
constant st17: std_logic_vector(4 downto 0) := "01101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st6 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st8 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st9 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st10 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st11 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st12 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st13 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st14 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st15 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st16 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st17 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st18 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st19 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st20 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st21 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st22 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st23 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when others => next_state <= "-----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 1c49e6a00bbe2b81b9b46100be0737c4 | 0.568926 | 3.207005 | false | false | false | false |
mike7c2/befunge_processor | befunge_stack_tb.vhd | 1 | 4,004 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:01:24 12/15/2014
-- Design Name:
-- Module Name: /media/media/Dropbox/Dropbox/befunge_processor/befunge_stack_tb.vhd
-- Project Name: befunge_processor
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: befunge_stack
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY befunge_stack_tb IS
END befunge_stack_tb;
ARCHITECTURE behavior OF befunge_stack_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT befunge_stack
PORT(
clk : IN std_logic;
reset : IN std_logic;
stack_0_o : OUT std_logic_vector(7 downto 0);
stack_1_o : OUT std_logic_vector(7 downto 0);
stack_i : IN std_logic_vector(7 downto 0);
pop1 : IN std_logic;
pop2 : IN std_logic;
push : IN std_logic;
swap : IN std_logic;
en : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal stack_i : std_logic_vector(7 downto 0) := (others => '0');
signal pop1 : std_logic := '0';
signal pop2 : std_logic := '0';
signal push : std_logic := '0';
signal swap : std_logic := '0';
signal en : std_logic := '0';
--Outputs
signal stack_0_o : std_logic_vector(7 downto 0);
signal stack_1_o : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: befunge_stack PORT MAP (
clk => clk,
reset => reset,
stack_0_o => stack_0_o,
stack_1_o => stack_1_o,
stack_i => stack_i,
pop1 => pop1,
pop2 => pop2,
push => push,
swap => swap,
en => en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
stack_i <= "00000000";
swap <= '0';
push <= '0';
en <= '0';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait until falling_edge(clk);
stack_i <= "11111111";
push <= '1';
en <= '1';
wait until falling_edge(clk);
stack_i <= "10101010";
push <= '1';
en <= '1';
wait until falling_edge(clk);
stack_i <= "01010101";
push <= '1';
en <= '1';
wait until falling_edge(clk);
stack_i <= "11001100";
push <= '1';
en <= '1';
wait until falling_edge(clk);
stack_i <= "00000000";
push <= '0';
swap <= '1';
en <= '1';
wait until falling_edge(clk);
stack_i <= "00000000";
push <= '0';
swap <= '0';
en <= '0';
-- insert stimulus here
wait;
end process;
END;
| unlicense | 1e32a3032d3cb90df4f3a1b25c7cfc18 | 0.506993 | 3.902534 | false | false | false | false |
chastell/art-decomp | kiss/ex6_nov.vhd | 1 | 4,231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_nov;
architecture behaviour of ex6_nov is
constant s1: std_logic_vector(2 downto 0) := "010";
constant s2: std_logic_vector(2 downto 0) := "110";
constant s3: std_logic_vector(2 downto 0) := "000";
constant s4: std_logic_vector(2 downto 0) := "100";
constant s5: std_logic_vector(2 downto 0) := "111";
constant s6: std_logic_vector(2 downto 0) := "011";
constant s7: std_logic_vector(2 downto 0) := "001";
constant s8: std_logic_vector(2 downto 0) := "101";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "---"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | 9717a81fc42e69c3f48dc720a2694286 | 0.579532 | 3.379393 | false | false | false | false |
chastell/art-decomp | kiss/opus_hot.vhd | 1 | 3,568 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_hot;
architecture behaviour of opus_hot is
constant init0: std_logic_vector(9 downto 0) := "1000000000";
constant init1: std_logic_vector(9 downto 0) := "0100000000";
constant init2: std_logic_vector(9 downto 0) := "0010000000";
constant init4: std_logic_vector(9 downto 0) := "0001000000";
constant IOwait: std_logic_vector(9 downto 0) := "0000100000";
constant read0: std_logic_vector(9 downto 0) := "0000010000";
constant write0: std_logic_vector(9 downto 0) := "0000001000";
constant RMACK: std_logic_vector(9 downto 0) := "0000000100";
constant WMACK: std_logic_vector(9 downto 0) := "0000000010";
constant read1: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----------"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | ab271f3e4995230d6af908e76e20fa23 | 0.59361 | 3.564436 | false | false | false | false |
chastell/art-decomp | kiss/sse_rnd.vhd | 1 | 6,957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_rnd;
architecture behaviour of sse_rnd is
constant st11: std_logic_vector(3 downto 0) := "1101";
constant st10: std_logic_vector(3 downto 0) := "0010";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st12: std_logic_vector(3 downto 0) := "1110";
constant st7: std_logic_vector(3 downto 0) := "1111";
constant st6: std_logic_vector(3 downto 0) := "0001";
constant st1: std_logic_vector(3 downto 0) := "0110";
constant st0: std_logic_vector(3 downto 0) := "0000";
constant st8: std_logic_vector(3 downto 0) := "1010";
constant st9: std_logic_vector(3 downto 0) := "1000";
constant st3: std_logic_vector(3 downto 0) := "0100";
constant st2: std_logic_vector(3 downto 0) := "1001";
constant st5: std_logic_vector(3 downto 0) := "1100";
constant st13: std_logic_vector(3 downto 0) := "0011";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 5acc3c281ab4b9d458f28fd2f374b79b | 0.559724 | 3.31128 | false | false | false | false |
chastell/art-decomp | kiss/dk15_jed.vhd | 1 | 3,716 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk15_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk15_jed;
architecture behaviour of dk15_jed is
constant state1: std_logic_vector(1 downto 0) := "01";
constant state2: std_logic_vector(1 downto 0) := "00";
constant state3: std_logic_vector(1 downto 0) := "10";
constant state4: std_logic_vector(1 downto 0) := "11";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when state1 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state2 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state3; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state3 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "10100";
elsif std_match(input, "101") then next_state <= state2; output <= "01000";
elsif std_match(input, "110") then next_state <= state4; output <= "01010";
end if;
when state4 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "10000";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 774c582fa027606d6bdb5ef8bbd73bc7 | 0.609526 | 3.453532 | false | false | false | false |
Diego-HR/HL-Object-Oriented | QAMDemodulator/src/solution1/syn/vhdl/qam_dem_top_mul_16s_12s_27_2.vhd | 4 | 2,467 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity qam_dem_top_mul_16s_12s_27_2_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(12 - 1 downto 0);
p: out std_logic_vector(27 - 1 downto 0));
end entity;
architecture behav of qam_dem_top_mul_16s_12s_27_2_MulnS_0 is
signal tmp_product : std_logic_vector(27 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(12 - 1 downto 0);
signal p_tmp : std_logic_vector(27 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_i) * signed(b_i))), 27));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
p_tmp <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity qam_dem_top_mul_16s_12s_27_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of qam_dem_top_mul_16s_12s_27_2 is
component qam_dem_top_mul_16s_12s_27_2_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
qam_dem_top_mul_16s_12s_27_2_MulnS_0_U : component qam_dem_top_mul_16s_12s_27_2_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-2.0 | ea37d41f2595ad249a245aa32437e75a | 0.550061 | 3.195596 | false | false | false | false |
chastell/art-decomp | kiss/styr_hot.vhd | 1 | 19,543 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_hot is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_hot;
architecture behaviour of styr_hot is
constant st0: std_logic_vector(29 downto 0) := "100000000000000000000000000000";
constant st12: std_logic_vector(29 downto 0) := "010000000000000000000000000000";
constant st10: std_logic_vector(29 downto 0) := "001000000000000000000000000000";
constant st1: std_logic_vector(29 downto 0) := "000100000000000000000000000000";
constant st2: std_logic_vector(29 downto 0) := "000010000000000000000000000000";
constant st8: std_logic_vector(29 downto 0) := "000001000000000000000000000000";
constant st3: std_logic_vector(29 downto 0) := "000000100000000000000000000000";
constant st7: std_logic_vector(29 downto 0) := "000000010000000000000000000000";
constant st4: std_logic_vector(29 downto 0) := "000000001000000000000000000000";
constant st5: std_logic_vector(29 downto 0) := "000000000100000000000000000000";
constant st6: std_logic_vector(29 downto 0) := "000000000010000000000000000000";
constant st29: std_logic_vector(29 downto 0) := "000000000001000000000000000000";
constant st9: std_logic_vector(29 downto 0) := "000000000000100000000000000000";
constant st28: std_logic_vector(29 downto 0) := "000000000000010000000000000000";
constant st11: std_logic_vector(29 downto 0) := "000000000000001000000000000000";
constant st13: std_logic_vector(29 downto 0) := "000000000000000100000000000000";
constant st14: std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant st15: std_logic_vector(29 downto 0) := "000000000000000001000000000000";
constant st16: std_logic_vector(29 downto 0) := "000000000000000000100000000000";
constant st22: std_logic_vector(29 downto 0) := "000000000000000000010000000000";
constant st19: std_logic_vector(29 downto 0) := "000000000000000000001000000000";
constant st17: std_logic_vector(29 downto 0) := "000000000000000000000100000000";
constant st18: std_logic_vector(29 downto 0) := "000000000000000000000010000000";
constant st20: std_logic_vector(29 downto 0) := "000000000000000000000001000000";
constant st21: std_logic_vector(29 downto 0) := "000000000000000000000000100000";
constant st25: std_logic_vector(29 downto 0) := "000000000000000000000000010000";
constant st23: std_logic_vector(29 downto 0) := "000000000000000000000000001000";
constant st24: std_logic_vector(29 downto 0) := "000000000000000000000000000100";
constant st26: std_logic_vector(29 downto 0) := "000000000000000000000000000010";
constant st27: std_logic_vector(29 downto 0) := "000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(29 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------"; output <= "----------";
case current_state is
when st0 =>
if std_match(input, "1-0000---") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-10-----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-1-0----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0010---") then next_state <= st10; output <= "1000----10";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "1010100110";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st1 =>
if std_match(input, "------0--") then next_state <= st2; output <= "0110010000";
elsif std_match(input, "------1--") then next_state <= st8; output <= "0110100100";
end if;
when st2 =>
if std_match(input, "1-00000--") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0011---") then next_state <= st2; output <= "010100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st7; output <= "010000--00";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st3 =>
if std_match(input, "1-0000---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st3; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st5; output <= "0110001100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st4 =>
if std_match(input, "---------") then next_state <= st6; output <= "0110010000";
end if;
when st5 =>
if std_match(input, "---------") then next_state <= st1; output <= "0110010100";
end if;
when st6 =>
if std_match(input, "1-00000--") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st6; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st7 =>
if std_match(input, "1-0000---") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st7; output <= "110100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0010------";
elsif std_match(input, "1-010----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st29 =>
if std_match(input, "1-0000---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st29; output <= "110100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st8 =>
if std_match(input, "---------") then next_state <= st9; output <= "0110010000";
end if;
when st9 =>
if std_match(input, "1-00000--") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-001----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-00001--") then next_state <= st28; output <= "010010--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st28 =>
if std_match(input, "1-0000---") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-001----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st10 =>
if std_match(input, "1--0---00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1---0--00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1--0---10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0----1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0---1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st11 =>
if std_match(input, "1--011-0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0--0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--010-0-") then next_state <= st10; output <= "0100----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0---1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st12 =>
if std_match(input, "1--011---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--10----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--000---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0001---") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1--010---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st13 =>
if std_match(input, "1--000---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--01----") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--001---") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st14 =>
if std_match(input, "1--000---") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--01----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--001---") then next_state <= st15; output <= "0010100100";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st15 =>
if std_match(input, "--1------") then next_state <= st16; output <= "0010010000";
elsif std_match(input, "--0------") then next_state <= st22; output <= "0010010000";
end if;
when st16 =>
if std_match(input, "1--000---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--011---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st17 =>
if std_match(input, "1--000---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st18; output <= "0010001100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st18 =>
if std_match(input, "---------") then next_state <= st19; output <= "0010010100";
end if;
when st19 =>
if std_match(input, "---------") then next_state <= st16; output <= "0010010000";
end if;
when st20 =>
if std_match(input, "---------") then next_state <= st21; output <= "0010010000";
end if;
when st21 =>
if std_match(input, "1--000---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st22 =>
if std_match(input, "1-0000---") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st23 =>
if std_match(input, "1-0000---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st24; output <= "0010001100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st24 =>
if std_match(input, "---------") then next_state <= st25; output <= "0010010100";
end if;
when st25 =>
if std_match(input, "---------") then next_state <= st22; output <= "0010010000";
end if;
when st26 =>
if std_match(input, "---------") then next_state <= st27; output <= "0010010000";
end if;
when st27 =>
if std_match(input, "1-0000---") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when others => next_state <= "------------------------------"; output <= "----------";
end case;
end process;
end behaviour;
| agpl-3.0 | 5ec40adf15fd35794638f50a2130083e | 0.569513 | 3.562341 | false | false | false | false |
chastell/art-decomp | kiss/s1_jed.vhd | 1 | 11,803 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_jed;
architecture behaviour of s1_jed is
constant st0: std_logic_vector(4 downto 0) := "11100";
constant st1: std_logic_vector(4 downto 0) := "11101";
constant st2: std_logic_vector(4 downto 0) := "11000";
constant st5: std_logic_vector(4 downto 0) := "01000";
constant st3: std_logic_vector(4 downto 0) := "11001";
constant st4: std_logic_vector(4 downto 0) := "11110";
constant st6: std_logic_vector(4 downto 0) := "10111";
constant st7: std_logic_vector(4 downto 0) := "00001";
constant st12: std_logic_vector(4 downto 0) := "01101";
constant st13: std_logic_vector(4 downto 0) := "01100";
constant st8: std_logic_vector(4 downto 0) := "10100";
constant st11: std_logic_vector(4 downto 0) := "00000";
constant st15: std_logic_vector(4 downto 0) := "10110";
constant st9: std_logic_vector(4 downto 0) := "10000";
constant st10: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10101";
constant st16: std_logic_vector(4 downto 0) := "10011";
constant st17: std_logic_vector(4 downto 0) := "00100";
constant st18: std_logic_vector(4 downto 0) := "10010";
constant st19: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 073d53c70290ebc9468f4e8131c02458 | 0.565026 | 3.300615 | false | false | false | false |
es17m014/vhdl-counter | src/tb/cntr_top_tb.vhd | 1 | 2,406 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_top_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Testbench for the counter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 19.11.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity cntr_top_tb is
end cntr_top_tb;
architecture sim of cntr_top_tb is
component cntr_top is
port (
clk_i : in std_logic;
reset_i : in std_logic;
sw_i : in std_logic_vector(15 downto 0);
pb_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(7 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0));
end component;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal sw_i : std_logic_vector(15 downto 0);
signal pb_i : std_logic_vector(3 downto 0);
signal ss_o : std_logic_vector(7 downto 0);
signal ss_sel_o : std_logic_vector(3 downto 0);
begin
-- Generate system clock 100 MHz
p_clk : process
begin
clk_i <= '0';
wait for 5 ns;
clk_i <= '1';
wait for 5 ns;
end process;
-- Component under test
p_io_ctrl : cntr_top
port map (
clk_i => clk_i,
reset_i => reset_i,
sw_i => sw_i,
pb_i => pb_i,
ss_o => ss_o,
ss_sel_o =>ss_sel_o);
p_sim : process
begin
reset_i <= '1';
sw_i <= "0000000000000000";
pb_i <= "0000";
wait for 200 ns;
reset_i <= '0';
-- set count direction up
sw_i <= "0001000000000000";
wait for 50 ms;
-- hold counter
sw_i <= "0101000000000000";
wait for 1 ms;
-- test reset
reset_i <= '0';
wait for 100 ns;
reset_i <= '1';
wait for 20 ms;
-- set count directon down
sw_i <= "0000100000000000";
wait for 200 ms;
end process;
end sim; | mit | 1fcb405b44ed0d4154c11ee5ce9700a4 | 0.461762 | 3.861958 | false | false | false | false |
TheMassController/VHDL_experimenting | project/deppSlave/depp_slave_controller.vhd | 1 | 9,549 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.depp_pkg.all;
entity depp_slave_controller is
port (
clk : in std_logic;
rst : in std_logic;
-- Bus connection
slv2mst : in bus_slv2mst_type;
mst2slv : out bus_mst2slv_type;
-- Physical USB/DEPP connection
USB_DB : inout STD_LOGIC_VECTOR(7 DOWNTO 0);
USB_WRITE : in STD_LOGIC;
USB_ASTB : in STD_LOGIC;
USB_DSTB : in STD_LOGIC;
USB_WAIT : out STD_LOGIC
);
end depp_slave_controller;
architecture behaviourial of depp_slave_controller is
signal usb_astb_delayed : std_logic;
signal usb_dstb_delayed : std_logic;
signal mst2slv_out : bus_mst2slv_type := BUS_MST2SLV_IDLE;
begin
sequential : process(clk)
variable wait_dstb_finish : boolean := false;
variable address : natural range 0 to 2**8 - 1;
variable address_tmp : natural range 0 to 2**8 - 1;
variable read_latch : depp_data_type := (others => '0');
variable bus_active : boolean := false;
variable reread : boolean := false;
variable write_mask_reg : std_logic_vector(depp2bus_write_mask_length_ceil*8 - 1 downto 0) := (others => '0');
variable slv2mst_cpy : bus_slv2mst_type := BUS_SLV2MST_IDLE;
variable depp_mode : depp_data_type := (others => '0');
variable next_bus_address : bus_address_type := (others => '0');
begin
if rising_edge(clk) then
-- We are crossing clock domains. Therefore, if either of these is high, other signals might still be settling.
-- Therefore, delay these by one cycle so that by the time interpretation starts, everything has settled.
usb_astb_delayed <= USB_ASTB;
usb_dstb_delayed <= USB_DSTB;
USB_WAIT <= '0';
USB_DB <= (others => 'Z');
if rst = '1' then
USB_WAIT <= '1';
wait_dstb_finish := false;
mst2slv_out <= BUS_MST2SLV_IDLE;
slv2mst_cpy := BUS_SLV2MST_IDLE;
write_mask_reg := (others => '0');
bus_active := false;
address := 0;
else
if bus_active then
if bus_slave_finished(slv2mst) = '1' then
bus_active := false;
mst2slv_out.writeEnable <= '0';
mst2slv_out.readEnable <= '0';
mst2slv_out.address <= next_bus_address;
wait_dstb_finish := true;
slv2mst_cpy := slv2mst;
if reread then
read_latch := slv2mst_cpy.readData(7 downto 0);
reread := false;
end if;
end if;
elsif usb_astb_delayed = '0' then
USB_WAIT <= '1';
if USB_WRITE = '0' then
address := to_integer(unsigned(USB_DB));
elsif USB_WRITE = '1' then
USB_DB <= std_logic_vector(to_unsigned(address, usb_db'length));
end if;
elsif usb_dstb_delayed = '0' and wait_dstb_finish = false then
wait_dstb_finish := true;
if USB_WRITE = '0' then
if address >= depp2bus_addr_reg_start and address <= depp2bus_addr_reg_end then
address_tmp := address - depp2bus_addr_reg_start;
mst2slv_out.address(8*(address_tmp + 1) - 1 downto 8*address_tmp) <= usb_db;
elsif address >= depp2bus_writeData_reg_start and address <= depp2bus_writeData_reg_end then
address_tmp := address - depp2bus_writeData_reg_start;
mst2slv_out.writeData(8*(address_tmp + 1) - 1 downto 8*address_tmp) <= usb_db;
if depp_mode_fast_write_active(depp_mode) then
address := address + 1;
if address > depp2bus_writeData_reg_end then
next_bus_address := std_logic_vector(to_unsigned(
to_integer(unsigned(mst2slv_out.address)) + depp2bus_addr_reg_len,
next_bus_address'length));
address := depp2bus_writeData_reg_start;
mst2slv_out.writeEnable <= '1';
bus_active := true;
wait_dstb_finish := false;
end if;
end if;
elsif address >= depp2bus_write_mask_reg_start and address <= depp2bus_write_mask_reg_end then
address_tmp := address - depp2bus_write_mask_reg_start;
write_mask_reg(8*(address_tmp + 1) - 1 downto 8*address_tmp) := usb_db;
mst2slv_out.writeMask <= write_mask_reg(mst2slv_out.writeMask'range);
elsif address >= depp2bus_mode_register_start and address <= depp2bus_mode_register_end then
depp_mode := usb_db;
elsif address >= depp2bus_activation_register_start and address <= depp2bus_activation_register_end then
next_bus_address := mst2slv_out.address;
mst2slv_out.writeEnable <= '1';
for i in 0 to usb_db'high loop
if usb_db(i) = '1' then
mst2slv_out.writeEnable <= '0';
mst2slv_out.readEnable <= '1';
end if;
end loop;
bus_active := true;
wait_dstb_finish := false;
end if;
elsif USB_WRITE = '1' then
read_latch := (others => '0');
if address >= depp2bus_addr_reg_start and address <= depp2bus_addr_reg_end then
address_tmp := address - depp2bus_addr_reg_start;
read_latch := mst2slv_out.address(8*address_tmp + 7 downto 8*address_tmp);
elsif address >= depp2bus_writeData_reg_start and address <= depp2bus_writeData_reg_end then
address_tmp := address - depp2bus_writeData_reg_start;
read_latch := mst2slv_out.writeData(8*address_tmp + 7 downto 8*address_tmp);
elsif address >= depp2bus_readData_reg_start and address <= depp2bus_readData_reg_end then
address_tmp := address - depp2bus_readData_reg_start;
if depp_mode_fast_read_active(depp_mode) then
if address = depp2bus_readData_reg_start then
next_bus_address := std_logic_vector(to_unsigned(
to_integer(unsigned(mst2slv_out.address)) + depp2bus_addr_reg_len,
next_bus_address'length));
mst2slv_out.readEnable <= '1';
bus_active := true;
wait_dstb_finish := false;
reread := true;
end if;
address := address + 1;
if address > depp2bus_readData_reg_end then
address := depp2bus_readData_reg_start;
end if;
end if;
read_latch := slv2mst_cpy.readData(8*address_tmp + 7 downto 8*address_tmp);
elsif address >= depp2bus_write_mask_reg_start and address <= depp2bus_write_mask_reg_end then
address_tmp := address - depp2bus_write_mask_reg_start;
read_latch := write_mask_reg(8*(address_tmp + 1) - 1 downto 8*address_tmp);
elsif address >= depp2bus_mode_register_start and address <= depp2bus_mode_register_end then
read_latch := depp_mode;
elsif address >= depp2bus_fault_register_start and address <= depp2bus_fault_register_end then
read_latch := (others => '0');
read_latch(0) := slv2mst_cpy.fault;
end if;
end if;
end if;
if usb_dstb_delayed = '0' and usb_write = '1' then
usb_db <= read_latch;
end if;
if wait_dstb_finish then
if usb_dstb_delayed = '1' then
wait_dstb_finish := false;
else
USB_WAIT <= '1';
end if;
end if;
end if;
end if;
end process;
concurrent : process(mst2slv_out)
begin
mst2slv <= mst2slv_out;
end process;
end behaviourial;
| mit | 736992c70eb8945f1b219a00378da1eb | 0.466227 | 4.525592 | false | false | false | false |
chastell/art-decomp | kiss/opus_rnd.vhd | 1 | 3,496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_rnd;
architecture behaviour of opus_rnd is
constant init0: std_logic_vector(3 downto 0) := "1101";
constant init1: std_logic_vector(3 downto 0) := "0010";
constant init2: std_logic_vector(3 downto 0) := "1011";
constant init4: std_logic_vector(3 downto 0) := "1110";
constant IOwait: std_logic_vector(3 downto 0) := "1111";
constant read0: std_logic_vector(3 downto 0) := "0001";
constant write0: std_logic_vector(3 downto 0) := "0110";
constant RMACK: std_logic_vector(3 downto 0) := "0000";
constant WMACK: std_logic_vector(3 downto 0) := "1010";
constant read1: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | d380dbcaca17f76e36942c6c215ab3a6 | 0.588673 | 3.492507 | false | false | false | false |
chastell/art-decomp | kiss/ex2_hot.vhd | 1 | 8,089 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_hot;
architecture behaviour of ex2_hot is
constant s1: std_logic_vector(18 downto 0) := "1000000000000000000";
constant s2: std_logic_vector(18 downto 0) := "0100000000000000000";
constant s4: std_logic_vector(18 downto 0) := "0010000000000000000";
constant s0: std_logic_vector(18 downto 0) := "0001000000000000000";
constant s3: std_logic_vector(18 downto 0) := "0000100000000000000";
constant s6: std_logic_vector(18 downto 0) := "0000010000000000000";
constant s9: std_logic_vector(18 downto 0) := "0000001000000000000";
constant s7: std_logic_vector(18 downto 0) := "0000000100000000000";
constant s8: std_logic_vector(18 downto 0) := "0000000010000000000";
constant s5: std_logic_vector(18 downto 0) := "0000000001000000000";
constant s10: std_logic_vector(18 downto 0) := "0000000000100000000";
constant s11: std_logic_vector(18 downto 0) := "0000000000010000000";
constant s13: std_logic_vector(18 downto 0) := "0000000000001000000";
constant s12: std_logic_vector(18 downto 0) := "0000000000000100000";
constant s15: std_logic_vector(18 downto 0) := "0000000000000010000";
constant s18: std_logic_vector(18 downto 0) := "0000000000000001000";
constant s16: std_logic_vector(18 downto 0) := "0000000000000000100";
constant s17: std_logic_vector(18 downto 0) := "0000000000000000010";
constant s14: std_logic_vector(18 downto 0) := "0000000000000000001";
signal current_state, next_state: std_logic_vector(18 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-------------------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 41dc4626b527373282eaca695eef5025 | 0.566077 | 3.46424 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_UDC2.vhd | 1 | 25,988 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: fmd2030_udc2.vhd
-- Creation Date:
-- Description:
-- Second section of the 360/30, corresponding to Unit Data & Control Diagram 2
-- in the MDM.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Add Mpx and 1050 buses, and Storage interface
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
USE work.Gates_package.all;
USE work.Buses_package.all;
USE work.all;
entity UDC2 is
port(
-- Buses
SALS : IN SALS_Bus;
CTRL : IN CTRL_REG;
Z_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
A_BUS1 : IN STD_LOGIC_VECTOR(0 to 8);
B_BUS : IN STD_LOGIC_VECTOR(0 to 8);
M_ASSM_BUS,N_ASSM_BUS : IN STD_LOGIC_VECTOR(0 to 8);
R : OUT STD_LOGIC_VECTOR(0 to 8);
S : OUT STD_LOGIC_VECTOR(0 to 7);
MN : OUT STD_LOGIC_VECTOR(0 to 15);
-- M_P, N_P : OUT STD_LOGIC;
E_BUS : IN E_SW_BUS_Type;
-- External MPX connections:
MPX_BUS_O : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_BUS_I : IN STD_LOGIC_VECTOR(0 to 8);
MPX_TAGS_O : OUT MPX_TAGS_OUT;
MPX_TAGS_I : IN MPX_TAGS_IN;
-- Switches
LAMP_TEST : IN STD_LOGIC;
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04A
CHK_SW_DISABLE : IN STD_LOGIC; -- 04A
Sw_Slow : IN STD_LOGIC;
-- Indicators
IND_OPNL_IN : OUT STD_LOGIC;
IND_ADDR_IN : OUT STD_LOGIC;
IND_STATUS_IN : OUT STD_LOGIC;
IND_SERV_IN : OUT STD_LOGIC;
IND_SEL_OUT : OUT STD_LOGIC;
IND_ADDR_OUT : OUT STD_LOGIC;
IND_CMMD_OUT : OUT STD_LOGIC;
IND_SERV_OUT : OUT STD_LOGIC;
IND_SUPPR_OUT : OUT STD_LOGIC;
IND_FO : OUT STD_LOGIC_VECTOR(0 to 7);
IND_FO_P : OUT STD_LOGIC;
IND_A : OUT STD_LOGIC_VECTOR(0 to 8);
IND_B : OUT STD_LOGIC_VECTOR(0 to 8);
IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8);
IND_M, IND_N : OUT STD_LOGIC_VECTOR(0 to 8);
IND_MAIN_STG, IND_LOC_STG, IND_COMP_MODE : OUT STD_LOGIC;
IND_CHK_A_REG, IND_CHK_B_REG, IND_CHK_STOR_ADDR, IND_CHK_CTRL_REG,
IND_CHK_ROS_SALS, IND_CHK_ROS_ADDR, IND_CHK_STOR_DATA, IND_CHK_ALU : OUT STD_LOGIC;
-- Hardware interface
StorageIn : IN STORAGE_IN_INTERFACE;
StorageOut : OUT STORAGE_OUT_INTERFACE;
-- Controls
CLOCK_START : IN STD_LOGIC;
MACH_RST_3,MACH_RST_6 : IN STD_LOGIC;
CLOCK_ON : OUT STD_LOGIC;
CLOCK_OFF : OUT STD_LOGIC;
MANUAL_STORE : IN STD_LOGIC;
RECYCLE_RST : IN STD_LOGIC;
MAN_STOR_OR_DSPLY : IN STD_LOGIC;
MAN_STOR_PWR : IN STD_LOGIC;
STORE_S_REG_RST : IN STD_LOGIC;
E_SW_SEL_S : IN STD_LOGIC;
MACH_RST_SET_LCH : IN STD_LOGIC;
DIAG_SW : IN STD_LOGIC;
-- S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC;
ROS_SCAN : IN STD_LOGIC;
GT_SWS_TO_WX_PWR : IN STD_LOGIC;
RST_LOAD : IN STD_LOGIC;
SYSTEM_RST_PRIORITY_LCH : IN STD_LOGIC;
A_REG_PC : OUT STD_LOGIC;
-- B_REG_PC : OUT STD_LOGIC;
CARRY_1_LCHD : OUT STD_LOGIC;
CARRY_0_LATCHED : OUT STD_LOGIC;
ALU_CHK : OUT STD_LOGIC;
NTRUE,COMPLEMENT : OUT STD_LOGIC;
P_CONNECT,P_CTRL_N,N_CTRL_N,N_CTRL_LM : OUT STD_LOGIC;
ALU_CHK_LCH : OUT STD_LOGIC;
CPU_RD_PWR : IN STD_LOGIC; -- 04B
GT_MAN_SET_MN : IN STD_LOGIC; -- 03B
CHNL_RD_CALL : IN STD_LOGIC; -- 04D
XH, XL, XXH : OUT STD_LOGIC; -- 08C
MN_PC : OUT STD_LOGIC; -- 07AD3
SET_IND_ROSAR : IN STD_LOGIC;
N_STACK_MEMORY_SELECT, STACK_RD_WR_CONTROL : IN STD_LOGIC;
H_REG_5_PWR : IN STD_LOGIC;
FORCE_M_REG_123 : IN STD_LOGIC;
GT_LOCAL_STORAGE : IN STD_LOGIC;
GT_T_REG_TO_MN : IN STD_LOGIC;
GT_CK_TO_MN : IN STD_LOGIC;
MAIN_STG_CP_1 : IN STD_LOGIC;
N_STACK_MEM_SELECT : IN STD_LOGIC;
SEL_CPU_BUMP : OUT STD_LOGIC; -- 04D
WX_CHK : IN STD_LOGIC; -- 01A
EARLY_M0 : OUT STD_LOGIC; -- 07B to 05D
MEM_WRAP : IN STD_LOGIC;
SUPPR_A_REG_CHK : OUT STD_LOGIC;
ODD : OUT STD_LOGIC;
STATUS_IN_LCHD : OUT STD_LOGIC;
SALS_PC : IN STD_LOGIC;
R_REG_PC : IN STD_LOGIC;
STORE_R : IN STD_LOGIC;
N2ND_ERROR_STOP : IN STD_LOGIC;
DECIMAL : OUT STD_LOGIC;
-- Inputs from UDC1
USE_R : IN STD_LOGIC;
USE_MAIN_MEM, USE_LOC_MAIN_MEM : IN STD_LOGIC;
USE_BASIC_CA_DECO : IN STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
SEL_DATA_READY : IN STD_LOGIC; -- 03B
N1401_MODE : IN STD_LOGIC; -- 05A
STG_MEM_SELECT : IN STD_LOGIC; -- 03D
MEM_PROT_REQUEST : IN STD_LOGIC; -- 03A
MANUAL_DISPLAY : IN STD_LOGIC; -- 03D
MAIN_STG : IN STD_LOGIC; -- 04D
MACH_RST_SW : IN STD_LOGIC; -- 03D
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04B
MACH_CHK_RST : IN STD_LOGIC; -- 04A
MACH_CHK_PULSE : IN STD_LOGIC; -- 03A
LOCAL_STG : IN STD_LOGIC; -- 04D
GT_D_REG_TO_A_BUS : IN STD_LOGIC; -- 05C
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02B
DATA_READY : IN STD_LOGIC; -- 03A
CTRL_REG_CHK : IN STD_LOGIC; -- 01A
CPU_WR_IN_R_REG : IN STD_LOGIC; -- 04D
CPU_SET_ALLOW_WR_LCH : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
ALLOW_WRITE_DLYD, ALLOW_WRITE : IN STD_LOGIC; -- 03D
USE_MANUAL_DECODER : IN STD_LOGIC;
GATED_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
MPX_ROS_LCH : IN STD_LOGIC; -- 02A
SET_FW : IN STD_LOGIC; -- 01B
LOAD_IND : IN STD_LOGIC; -- 03C
CLOCK_OUT : IN STD_LOGIC; -- 04A
METERING_OUT : IN STD_LOGIC; -- 04A
READ_ECHO_1,READ_ECHO_2,WRITE_ECHO_1,WRITE_ECHO_2 : IN STD_LOGIC;
-- Outputs to UDC1
FIRST_MACH_CHK_REQ : OUT STD_LOGIC; -- 03A
FIRST_MACH_CHK : OUT STD_LOGIC; -- 03C
ANY_MACH_CHK : OUT STD_LOGIC; -- 01A, 03C, 04A
ALLOW_PROTECT : OUT STD_LOGIC; -- 03A
ALLOW_PC_SALS : OUT STD_LOGIC; -- 01B
P_8F_DETECTED : OUT STD_LOGIC; -- 03A
M_REG_0 : OUT STD_LOGIC; -- 05D
Z0_BUS_0 : OUT STD_LOGIC;
Z_0 : OUT STD_LOGIC;
EXT_TRAP_MASK_ON : OUT STD_LOGIC; -- 08C to 04C
MACH_RST_PROT : OUT STD_LOGIC; -- 07B to 04C
CS_DECODE_X001 : OUT STD_LOGIC; -- 07B to 03C
BASIC_CS0 : OUT STD_LOGIC; -- 07B to 03C
MACH_RST_2A : OUT STD_LOGIC;
MACH_RST_2B : OUT STD_LOGIC;
CARRY_0 : OUT STD_LOGIC;
INTRODUCE_ALU_CHK : OUT STD_LOGIC;
FT0, FT2, FT3, FT5, FT6, FT7 : OUT STD_LOGIC; -- 08C,D to 05C
MPX_INTERRUPT : OUT STD_LOGIC;
MACH_RST_MPX : OUT STD_LOGIC;
MPX_SHARE_REQ : OUT STD_LOGIC;
MPX_METERING_IN : OUT STD_LOGIC;
ADDR_IN_LCHD : OUT STD_LOGIC;
OPNL_IN_LCHD : OUT STD_LOGIC;
SERV_IN_LCHD : OUT STD_LOGIC;
-- Inputs from UDC3
T_REQUEST : IN STD_LOGIC; -- 10B
STORE_HR, STORE_GR : IN STD_LOGIC; -- 14D, 12D
SEL_SHARE_CYCLE : IN STD_LOGIC; -- 12D
SEL_R_W_CTRL : IN STD_LOGIC; -- 12C
SEL_CHNL_CHK : IN STD_LOGIC; -- 11A
HR_REG_0_7, GR_REG_0_7 : IN STD_LOGIC_VECTOR(0 TO 7); -- 13C, 11C
HR_REG_P_BIT, GR_REG_P_BIT : IN STD_LOGIC; -- 13A, 11A
GT_HSMPX_INTO_R_REG : IN STD_LOGIC; -- ???
DR_CORR_P_BIT : IN STD_LOGIC; -- ??? (HSMPX)
GT_DETECTORS_TO_HR, GT_DETECTORS_TO_GR : IN STD_LOGIC; -- 12D, 14D
EVEN_HR_0_7_BITS, EVEN_GR_0_7_BITS : IN STD_LOGIC; -- 13A, 11A
-- Outputs to UDC3
STORE_BITS : OUT STD_LOGIC_VECTOR(0 TO 8); -- 11C
-- Selector & Mpx channels
SX1_RD_CYCLE,SX2_RD_CYCLE,SX1_WR_CYCLE,SX2_WR_CYCLE : IN STD_LOGIC;
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : IN STD_LOGIC;
N_SEL_SHARE_HOLD : IN STD_LOGIC;
GK,HK : IN STD_LOGIC_VECTOR(0 to 3);
PROTECT_LOC_CPU_OR_MPX, PROTECT_LOC_SEL_CHNL : OUT STD_LOGIC;
FO, FI : OUT STD_LOGIC_VECTOR(0 to 8);
MPX_OPN_LT_GATE : OUT STD_LOGIC;
ADDR_OUT : OUT STD_LOGIC;
MPX_BUS_IN_TO_CPU : OUT STD_LOGIC_VECTOR(0 to 8);
n1050_SEL_IN : OUT STD_LOGIC;
n1050_INSTALLED : IN STD_LOGIC;
n1050_REQ_IN : IN STD_LOGIC;
n1050_OP_IN : IN STD_LOGIC;
n1050_CE_MODE : IN STD_LOGIC;
n1050_SEL_O : IN STD_LOGIC;
P_1050_SEL_OUT : OUT STD_LOGIC;
P_1050_SEL_IN : OUT STD_LOGIC;
-- Debug
DEBUG : INOUT DEBUG_BUS;
-- Clocks
CLOCK_IN : IN STD_LOGIC;
T1,T2,T3,T4 : OUT STD_LOGIC;
P1,P2,P3,P4 : OUT STD_LOGIC;
SEL_T1, SEL_T3 : IN STD_LOGIC;
M_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : OUT STD_LOGIC;
Clk : IN STD_LOGIC
);
end entity UDC2;
architecture FMD of UDC2 is
signal sFO : STD_LOGIC_VECTOR(0 to 7);
signal sFO_P : STD_LOGIC;
signal OPNL_IN : STD_LOGIC;
signal ADDR_IN : STD_LOGIC;
signal STATUS_IN : STD_LOGIC;
signal SERVICE_IN : STD_LOGIC;
signal SELECT_OUT : STD_LOGIC;
signal sADDR_OUT : STD_LOGIC;
signal COMMAND_OUT : STD_LOGIC;
signal SERVICE_OUT : STD_LOGIC;
signal SUPPRESS_OUT : STD_LOGIC;
signal Z_HI_0,Z_LO_0,sZ_0 : STD_LOGIC;
signal sCARRY_0, CARRY_4 : STD_LOGIC;
signal GT_CARRY_TO_S3 : STD_LOGIC;
signal sMACH_RST_2A,sMACH_RST_2B,MACH_RST_2C : STD_LOGIC;
signal MN_REG_CHK_SMPLD : STD_LOGIC;
signal A_BUS, A_BUS2, Q_REG_BUS : STD_LOGIC_VECTOR(0 TO 8);
signal R_0 : STD_LOGIC;
signal READ_1,READ_2,WRITE_1,WRITE_2 : STD_LOGIC;
-- signal PHASE_RD_1, PHASE_RD_2, PHASE_WR_1, PHASE_WR_2 : STD_LOGIC;
signal SA : STD_LOGIC_VECTOR(0 to 7);
signal MPX_CP : STD_LOGIC;
signal OSC_T_LINE : STD_LOGIC;
signal FB_K_T2_PULSE : STD_LOGIC;
signal GT_Q_REG_TO_A_BUS : STD_LOGIC;
signal STACK_PC : STD_LOGIC;
signal MC : STD_LOGIC_VECTOR(0 to 7);
signal MAIN_STORAGE_CP : STD_LOGIC;
signal GATE_Z_BUS_TO_S_REG : STD_LOGIC;
signal GT_DDC_TO_A_BUS : STD_LOGIC;
-- signal A_BUS_2,A_BUS_3 : STD_LOGIC_VECTOR(0 to 8);
-- IO
signal SERV_IN_SIG : STD_LOGIC := '0';
signal STAT_IN_SIG : STD_LOGIC := '0';
signal sT1,sT2,sT3,sT4 : STD_LOGIC;
signal sP1,sP2,sP3,sP4 : STD_LOGIC;
signal sCLOCK_ON, sCLOCK_OFF : STD_LOGIC;
signal sM_CONV_OSC, sP_CONV_OSC, sM_CONV_OSC_2 : STD_LOGIC;
signal sA_REG_PC, sB_REG_PC : STD_LOGIC;
signal sALU_CHK : STD_LOGIC;
signal sMN : STD_LOGIC_VECTOR(0 to 15);
signal sM_P, sN_P : STD_LOGIC;
signal sS : STD_LOGIC_VECTOR(0 to 7);
signal sZ_BUS,sN_Z_BUS,sR : STD_LOGIC_VECTOR(0 to 8);
signal sS_REG_RST : STD_LOGIC;
signal sNTRUE, sCOMPLEMENT : STD_LOGIC;
signal sP_CONNECT, sP_CTRL_N, sN_CTRL_N, sN_CTRL_LM : STD_LOGIC;
signal sALU_CHK_LCH : STD_LOGIC;
signal sZ_BUS_LO_DIGIT_PARITY : STD_LOGIC;
signal sMN_PC : STD_LOGIC;
signal sPROTECT_LOC_CPU_OR_MPX : STD_LOGIC;
signal sXL,sXH,sXXH : STD_LOGIC;
signal SUPPR_CTRL_LCH,OP_OUT_SIG,SX1_MASK,SX2_MASK,FAK,SET_BUS_O_CTRL_LCH : STD_LOGIC;
-- signal sMPX_BUS_O_REG : STD_LOGIC_VECTOR(0 to 8);
signal sFT2, sFT7 : STD_LOGIC;
begin
-- Clock
clock_sect: entity Clock (FMD) port map (
CLOCK_IN => CLOCK_IN,
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
P2 => sP2,
P3 => sP3,
P4 => sP4,
CLOCK_START => CLOCK_START,
CLOCK_ON => sCLOCK_ON,
CLOCK_OFF => sCLOCK_OFF,
MACH_RST_3 => MACH_RST_3,
M_CONV_OSC => sM_CONV_OSC,
P_CONV_OSC => sP_CONV_OSC,
M_CONV_OSC_2 => sM_CONV_OSC_2,
OSC_T_LINE => OSC_T_LINE,
Sw_Slow => Sw_Slow
);
T1 <= sT1;
T2 <= sT2;
T3 <= sT3;
T4 <= sT4;
P1 <= sP1;
P2 <= sP2;
P3 <= sP3;
P4 <= sP4;
M_CONV_OSC <= sM_CONV_OSC;
P_CONV_OSC <= sP_CONV_OSC;
M_CONV_OSC_2 <= sM_CONV_OSC_2;
CLOCK_ON <= sCLOCK_ON;
CLOCK_OFF <= sCLOCK_OFF;
MpxInd_sect: entity MpxInd (FMD) port map (
FO => sFO,
FO_P => sFO_P,
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => sADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT,
IND_OPNL_IN => IND_OPNL_IN,
IND_ADDR_IN => IND_ADDR_IN,
IND_STATUS_IN => IND_STATUS_IN,
IND_SERV_IN => IND_SERV_IN,
IND_SEL_OUT => IND_SEL_OUT,
IND_ADDR_OUT => IND_ADDR_OUT,
IND_CMMD_OUT => IND_CMMD_OUT,
IND_SERV_OUT => IND_SERV_OUT,
IND_SUPPR_OUT => IND_SUPPR_OUT,
IND_FO => IND_FO,
IND_FO_P => IND_FO_P,
TEST_LAMP => LAMP_TEST
);
A_BUS <= A_BUS1 and A_BUS2; -- Combine buses - input buses are 11111111 when inactive, values are inverted
ALU: entity ABALU port map(
-- Inputs
LAMP_TEST => LAMP_TEST,
SALS => SALS,
MANUAL_STORE => MANUAL_STORE,
RECYCLE_RST => RECYCLE_RST,
S_REG_3 => sS(3),
SERV_IN_SIG => SERV_IN_SIG,
STAT_IN_SIG => STAT_IN_SIG,
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
T_REQUEST => T_REQUEST,
A_BUS => A_BUS,
B_BUS => B_BUS,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
MACH_RST_SET_LCH => MACH_RST_SET_LCH,
S_REG_0 => sS(0),
CTRL => CTRL,
DIAG_SW => DIAG_SW,
S_REG_RST => sS_REG_RST,
GT_Z_BUS_TO_S_REG => GATE_Z_BUS_TO_S_REG,
ROS_SCAN => ROS_SCAN,
GT_SWS_TO_WX_PWR => GT_SWS_TO_WX_PWR,
RST_LOAD => RST_LOAD,
SYSTEM_RST_PRIORITY_LCH => SYSTEM_RST_PRIORITY_LCH,
-- Outputs
IND_A => IND_A,
IND_B => IND_B,
IND_ALU => IND_ALU,
A_REG_PC => sA_REG_PC,
B_REG_PC => sB_REG_PC,
OPNL_IN_LCHD => OPNL_IN_LCHD,
STATUS_IN_LCHD => STATUS_IN_LCHD,
Z0_BUS_0 => Z0_BUS_0,
SERV_IN_LCHD => SERV_IN_LCHD,
ADDR_IN_LCHD => ADDR_IN_LCHD,
CARRY_0 => sCARRY_0,
CARRY_1_LCHD => CARRY_1_LCHD,
CARRY_0_LATCHED => CARRY_0_LATCHED,
ALU_CHK => sALU_CHK,
NTRUE => sNTRUE,
COMPLEMENT => sCOMPLEMENT,
P_CONNECT => sP_CONNECT,
P_CTRL_N => sP_CTRL_N,
N_CTRL_N => sN_CTRL_N,
N_CTRL_LM => sN_CTRL_LM,
P_Z_BUS => sZ_BUS,
N_Z_BUS => sN_Z_BUS,
Z_HI_0 => Z_HI_0,
Z_LO_0 => Z_LO_0,
Z_0 => sZ_0,
Z_BUS_LO_DIGIT_PARITY => sZ_BUS_LO_DIGIT_PARITY,
MACH_RST_2A => sMACH_RST_2A,
MACH_RST_2B => sMACH_RST_2B,
MACH_RST_2C => MACH_RST_2C,
ALU_CHK_LCH => sALU_CHK_LCH,
ODD => ODD,
GT_CARRY_TO_S3 => GT_CARRY_TO_S3,
DECIMAL => DECIMAL,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
-- Debug
-- DEBUG => DEBUG,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
Clk => Clk
);
A_REG_PC <= sA_REG_PC;
-- B_REG_PC <= sB_REG_PC;
ALU_CHK <= sALU_CHK;
Z_BUS <= sZ_BUS;
-- S_REG_RST <= sS_REG_RST;
NTRUE <= sNTRUE;
COMPLEMENT <= sCOMPLEMENT;
P_CONNECT <= sP_CONNECT;
P_CTRL_N <= sP_CTRL_N;
N_CTRL_N <= sN_CTRL_N;
N_CTRL_LM <= sN_CTRL_LM;
ALU_CHK_LCH <= sALU_CHK_LCH;
MACH_RST_2A <= sMACH_RST_2A;
MACH_RST_2B <= sMACH_RST_2B;
CARRY_0 <= sCARRY_0;
Z_0 <= sZ_0;
r_reg: entity RREG_STG port map (
-- Inputs
SALS => SALS,
CTRL => CTRL,
SX2_RD_CYCLE => SX2_RD_CYCLE,
SEL_T3 => SEL_T3,
GT_DETECTORS_TO_HR => GT_DETECTORS_TO_HR,
SEL_DATA_READY => SEL_DATA_READY,
SEL_R_W_CTRL => SEL_R_W_CTRL,
SX2_WR_CYCLE => SX2_WR_CYCLE,
SX1_RD_CYCLE => SX1_RD_CYCLE,
SX1_WR_CYCLE => SX1_WR_CYCLE,
GT_DETECTORS_TO_GR => GT_DETECTORS_TO_GR,
EVEN_HR_0_7_BITS => EVEN_HR_0_7_BITS,
EVEN_GR_0_7_BITS => EVEN_GR_0_7_BITS,
HR_REG_0_7 => HR_REG_0_7,
GR_REG_0_7 => GR_REG_0_7,
DR_CORR_P_BIT => DR_CORR_P_BIT,
HR_REG_P_BIT => HR_REG_P_BIT,
GR_REG_P_BIT => GR_REG_P_BIT,
STORE_HR => STORE_HR,
STORE_GR => STORE_GR,
STORE_R => STORE_R,
MEM_SELECT => STG_MEM_SELECT,
MAN_STORE_PWR => MANUAL_STORE,
E_SW_SEL_R => E_BUS.R_SEL,
GT_HSMPX_INTO_R_REG => GT_HSMPX_INTO_R_REG,
COMPUTE_CY_LCH => CTRL.COMPUTE_CY_LCH,
CLOCK_OFF => sCLOCK_OFF,
ALLOW_WRITE_1 => ALLOW_WRITE_DLYD,
PROT_LOC_CPU_OR_MPX => sPROTECT_LOC_CPU_OR_MPX,
USE_R => USE_R,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAN_STORE => MANUAL_STORE,
DATA_READY => DATA_READY,
MACH_RST_2A => sMACH_RST_2A,
MACH_RST_SET_LCH_DLY => MACH_RST_SET_LCH_DLY,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
MN_REG_CHK_SMPLD => MN_REG_CHK_SMPLD,
MEM_WRAP => MEM_WRAP,
MAIN_STG => MAIN_STG,
MACH_RST_6 => MACH_RST_6,
ALLOW_WRITE => ALLOW_WRITE,
ALLOW_PROTECT => ALLOW_PROTECT,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
N1401_MODE => N1401_MODE,
MACH_RST_SW => MACH_RST_SW,
MN => sMN,
N_Z_BUS => sN_Z_BUS,
USE_MAIN_MEM => USE_MAIN_MEM,
USE_LOC_MAIN_MEM => USE_LOC_MAIN_MEM,
PHASE_RD_1 => READ_ECHO_1,
PHASE_RD_2 => READ_ECHO_2,
PHASE_WR_1 => WRITE_ECHO_1,
PHASE_WR_2 => WRITE_ECHO_2,
-- Outputs
STORE_BITS => STORE_BITS,
R_0 => R_0,
R_REG_BUS => sR,
P_8F_DETECTED => P_8F_DETECTED,
StorageIn => StorageIn,
StorageOut => StorageOut,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3, -- not really needed
T4 => sT4,
clk => clk
);
R <= sR;
SAR_SA : entity SARSA port map (
M_ASSM_BUS => M_ASSM_BUS,
N_ASSM_BUS => N_ASSM_BUS,
MACH_RST_SW => MACH_RST_SW,
MACH_RESET_SET_LCH_DLY => MACH_RST_SET_LCH_DLY ,
MAN_STOR_OR_DSPLY => MAN_STOR_OR_DSPLY,
CPU_RD_PWR => CPU_RD_PWR,
SEL_RDWR_CTRL => SEL_R_W_CTRL,
GT_MAN_SET_MN => GT_MAN_SET_MN,
CHNL_RD_CALL => CHNL_RD_CALL,
XH => sXH,
XL => sXL,
XXH => sXXH,
MAIN_STORAGE_CP => MAIN_STORAGE_CP,
MPX_CP => MPX_CP,
MN => sMN,
M_P => sM_P,
N_P => sN_P,
MACH_RST_PROTECT => MACH_RST_PROT,
EARLY_M0 => EARLY_M0,
M_REG_0 => M_REG_0,
SA_REG => SA,
SEL_T1 => SEL_T1,
T1 => sT1
);
S_Reg : entity SReg port map (
CS => CTRL.CTRL_CS,
SA => SALS.SALS_SA,
CD => CTRL.CTRL_CD,
N_Z_BUS => sN_Z_BUS(0 to 7),
Z_BUS0 => sZ_0,
CARRY_0 => sCARRY_0,
Z_BUS_HI_0 => Z_HI_0,
Z_BUS_LO_0 => Z_LO_0,
GT_CARRY_TO_S3 => GT_CARRY_TO_S3,
CTRL_REG_RST => CTRL_REG_RST,
MAN_STOR_PWR => MAN_STOR_PWR,
STORE_S_REG_RST => STORE_S_REG_RST,
E_SW_SEL_S => E_SW_SEL_S,
MACH_RST_2C => MACH_RST_2C,
T_REQUEST => T_REQUEST,
GT_Z_BUS_TO_S => GATE_Z_BUS_TO_S_REG,
S_REG_RST => sS_REG_RST,
FB_K_T2_PULSE => FB_K_T2_PULSE,
CS_DECODE_X001 => CS_DECODE_X001,
BASIC_CS_0 => BASIC_CS0,
P1 => sP1,
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
S => sS,
clk => clk
);
S <= sS;
MN_Ind : entity MNInd port map (
-- Inputs
MN => sMN,
M_P => sM_P,
N_P => sN_P,
LAMP_TEST => LAMP_TEST,
MAIN_STG => MAIN_STG,
LOCAL_STG => LOCAL_STG,
N1401_MODE => N1401_MODE,
-- Outputs
IND_M => IND_M,
IND_N => IND_N,
IND_MAIN_STG => IND_MAIN_STG,
IND_LOC_STG => IND_LOC_STG,
IND_COMP_MODE => IND_COMP_MODE,
MN_PC => sMN_PC
);
MN <= sMN;
-- M_P <= sM_P;
-- N_P <= sN_P;
MN_PC <= sMN_PC;
ChkReg_Ind : entity ChkRegInd port map (
-- Inputs
LAMP_TEST => LAMP_TEST,
GT_CA_TO_W_REG => GT_CA_TO_W_REG,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
CA_SALS => SALS.SALS_CA,
ROS_SCAN => ROS_SCAN,
MACH_CHK_PULSE => MACH_CHK_PULSE,
GT_D_REG_TO_A_BUS => GT_D_REG_TO_A_BUS,
MACH_RST_SW => MACH_RST_SW,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
SET_IND_ROSAR => SET_IND_ROSAR,
MACH_RST_6 => MACH_RST_6,
WX_CHK => WX_CHK,
A_REG_PC => sA_REG_PC,
B_REG_PC => sB_REG_PC,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
ALLOW_WRITE => ALLOW_WRITE,
CTRL_REG_CHK => CTRL_REG_CHK,
SALS_PC => SALS_PC,
R_REG_PC => R_REG_PC,
ALU_CHK => sALU_CHK,
CHK_SW_PROC_SW => CHK_SW_PROC_SW,
SUPPR_MACH_CHK_TRAP => SUPPR_MACH_CHK_TRAP,
CPU_WR_IN_R_REG => CPU_WR_IN_R_REG,
GT_Q_REG_TO_A_BUS => GT_Q_REG_TO_A_BUS,
STACK_PC => STACK_PC,
MEM_PROT_REQUEST => MEM_PROT_REQUEST,
SEL_CHNL_CHK => SEL_CHNL_CHK,
MACH_CHK_RST => MACH_CHK_RST,
AK_SAL_BIT => SALS.SALS_AK,
CK_SALS => SALS.SALS_CK,
MN_PC => sMN_PC,
N1401_MODE => N1401_MODE,
-- Outputs
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
ALLOW_PC_SALS => ALLOW_PC_SALS,
MN_REG_CHK_SMPLD => MN_REG_CHK_SMPLD,
FIRST_MACH_CHK => FIRST_MACH_CHK,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
ANY_MACH_CHK => ANY_MACH_CHK,
IND_MC_A_REG => IND_CHK_A_REG,
IND_MC_B_REG => IND_CHK_B_REG,
IND_MC_STOR_ADDR => IND_CHK_STOR_ADDR,
IND_MC_CTRL_REG => IND_CHK_CTRL_REG,
IND_MC_ROS_SALS => IND_CHK_ROS_SALS,
IND_MC_ROS_ADDR => IND_CHK_ROS_ADDR,
IND_MC_STOR_DATA => IND_CHK_STOR_DATA,
IND_MC_ALU => IND_CHK_ALU,
MC => MC,
-- Clocks
T1 => sT1,
T2 => sT2,
T3 => sT3,
T4 => sT4,
P1 => sP1,
clk => clk
);
STP : entity QReg_STP port map (
-- Inputs
SA_REG => SA,
Z_BUS => sZ_BUS,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
MAIN_STG => MAIN_STG,
H_REG_5_PWR => H_REG_5_PWR,
FORCE_M_REG_123 => FORCE_M_REG_123,
GT_LOCAL_STORAGE => GT_LOCAL_STORAGE,
GT_T_REG_TO_MN => GT_T_REG_TO_MN,
GT_CK_TO_MN => GT_CK_TO_MN,
MAIN_STG_CP_1 => MAIN_STG_CP_1,
N_STACK_MEMORY_SELECT => N_STACK_MEMORY_SELECT,
STACK_RD_WR_CONTROL => STACK_RD_WR_CONTROL,
E_SW_SEL_Q => E_BUS.Q_SEL,
MAN_STORE_PWR => MANUAL_STORE,
T4 => sT4,
MACH_RST_2B => sMACH_RST_2B,
Z_BUS_LO_DIG_PARITY => sZ_BUS_LO_DIGIT_PARITY,
CD_REG => CTRL.CTRL_CD,
CLOCK_OFF => sCLOCK_OFF,
N_SEL_SHARE_HOLD => N_SEL_SHARE_HOLD,
N_MEM_SELECT => N_STACK_MEM_SELECT,
GK => GK,
HK => HK,
CLK => CLOCK_IN,
-- Outputs
Q_REG_BUS => Q_REG_BUS,
SEL_CPU_BUMP => SEL_CPU_BUMP,
STACK_PC => STACK_PC,
MPX_CP => MPX_CP,
MAIN_STG_CP => MAIN_STORAGE_CP,
PROTECT_LOC_CPU_OR_MPX => sPROTECT_LOC_CPU_OR_MPX,
PROTECT_LOC_SEL_CHNL => PROTECT_LOC_SEL_CHNL
);
PROTECT_LOC_CPU_OR_MPX <= sPROTECT_LOC_CPU_OR_MPX;
ARegA : entity ARegAssm port map (
-- Inputs
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
E_SEL_SW_BUS => E_BUS,
GTD_CA_BITS => GATED_CA_BITS,
CHK_SW_DISABLE => CHK_SW_DISABLE,
S => sS,
MC_CTRL_REG => MC,
Q_REG => Q_REG_BUS,
-- Outputs
A_BUS => A_BUS2,
GT_Q_REG_TO_A_BUS => GT_Q_REG_TO_A_BUS
);
MpxReg1 : entity MpxFOFB port map (
-- Inputs
MPX_ROS_LCH => MPX_ROS_LCH, -- 02A
S_REG_0 => sS(0), -- 07B
SET_FW => SET_FW, -- 01B
S_REG_1 => sS(1), -- 07B
S_REG_2 => sS(2), -- 07B
T3 => sT3,
CK_SALS => SALS.SALS_CK,
PK_SALS => SALS.SALS_PK,
FBK_T2 => FB_K_T2_PULSE, -- 07B
MACH_RST_SET_LCH => MACH_RST_SET_LCH, -- 04B
SALS_CS => SALS.SALS_CS,
SALS_SA => SALS.SALS_SA,
CK_0_PWR => SALS.SALS_CK(0), -- 01C
R_REG => sR, -- 06C
T1 => sT1,
T2 => sT2,
-- Outputs
XXH => sXXH, -- 05B 07B
XH => sXH, -- 05B 07B
XL => sXL, -- 05B 07B
FT_7_BIT_MPX_CHNL_INTRP => sFT7, -- 05C 08D
FT_2_BIT_MPX_OPN_LCH => FT2, -- 04A 05C
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH, -- 08D
OP_OUT_SIG => OP_OUT_SIG, -- 08D
MPX_OPN_LT_GATE => MPX_OPN_LT_GATE, -- 10B
MACH_RST_MPX => MACH_RST_MPX, -- 01C
MPX_INTRPT => MPX_INTERRUPT, -- 02A
SX1_MASK => SX1_MASK, -- 12D
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON, -- 04C
SX2_MASK => SX2_MASK, -- 14D
FAK => FAK, -- 08D
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH, -- 08D
MPX_BUS_O_REG(0 to 7) => sFO,-- 08A 08D 05C 11D 13D
MPX_BUS_O_REG(8) => sFO_P,
clk => clk
);
XL <= sXL;
XH <= sXH;
XXH <= sXXH;
FO <= sFO & sFO_P;
FT7 <= sFT7;
MpxChnlCtrls: entity MpxFA port map ( -- 5-08D
BUS_O_REG(0 to 7) => sFO,
BUS_O_REG(8) => sFO_P,
DIAG_SW => DIAG_SW,
-- MPX physical I/O
MPX_BUS_OUT_BITS => MPX_BUS_O,
MPX_BUS_IN_BITS => MPX_BUS_I,
TAGS_OUT => MPX_TAGS_O,
TAGS_IN => MPX_TAGS_I,
FI => FI,
FAK => FAK,
RECYCLE_RST => RECYCLE_RST,
CK_P_BIT => SALS.SALS_PK,
ALU_CHK_LCH => sALU_CHK_LCH,
CHK_SW_PROC_SW => CHK_SW_PROC_SW,
ROS_SCAN => ROS_SCAN,
FBK_T2 => FB_K_T2_PULSE,
FT5_BIT_SEL_IN => FT5,
SERV_IN_SIGNAL => SERV_IN_SIG,
STATUS_IN_SIGNAL => STAT_IN_SIG,
FT3_BIT_MPX_SHARE_REQ => FT3,
MPX_SHARE_REQ => MPX_SHARE_REQ,
T1 => sT1,
T2 => sT2,
T3 => sT3,
ANY_PRIORITY_LCH => ANY_PRIORITY_LCH,
CK_SALS_PWR => SALS.SALS_CK,
SET_BUS_O_CTRL_LCH => SET_BUS_O_CTRL_LCH,
N1401_MODE => N1401_MODE,
-- 1050 attachment
N1050_INSTALLED => n1050_INSTALLED,
N1050_REQ_IN => n1050_REQ_IN,
N1050_OP_IN => n1050_OP_IN,
N1050_CE_MODE => n1050_CE_MODE,
N1050_SEL_IN => n1050_SEL_IN,
N1050_SEL_O => n1050_SEL_O,
P_1050_SEL_OUT => P_1050_SEL_OUT,
P_1050_SEL_IN => P_1050_SEL_IN,
MPX_METERING_IN => MPX_METERING_IN,
FT7_MPX_CHNL_IN => sFT7,
LOAD_IND => LOAD_IND,
SUPPR_CTRL_LCH => SUPPR_CTRL_LCH,
OP_OUT_SIGNAL => OP_OUT_SIG,
-- RECYCLE_RESET => RECYCLE_RST,
OP_OUT_SIG => OP_OUT_SIG,
SEL_O_FT6 => FT6,
-- N1050_SEL_OUT => N1050_SEL_OUT,
SUPPR_O => FT0 ,
-- SUPPR_O_FT0 => FT0,
-- OP_OUT => OP_OUT,
METERING_OUT => METERING_OUT,
CLOCK_OUT => CLOCK_OUT,
CLK => CLK,
DEBUG => DEBUG,
-- Mpx Indicators
OPNL_IN => OPNL_IN,
ADDR_IN => ADDR_IN,
STATUS_IN => STATUS_IN,
SERVICE_IN => SERVICE_IN,
SELECT_OUT => SELECT_OUT,
ADDR_OUT => sADDR_OUT,
COMMAND_OUT => COMMAND_OUT,
SERVICE_OUT => SERVICE_OUT,
SUPPRESS_OUT => SUPPRESS_OUT
);
ADDR_OUT <= sADDR_OUT;
end FMD;
| gpl-3.0 | ce4fa441d528ad6f70da7b6348a76e6a | 0.590003 | 2.430375 | false | false | false | false |
chastell/art-decomp | kiss/planet_hot.vhd | 1 | 18,670 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_hot;
architecture behaviour of planet_hot is
constant st0: std_logic_vector(47 downto 0) := "100000000000000000000000000000000000000000000000";
constant st1: std_logic_vector(47 downto 0) := "010000000000000000000000000000000000000000000000";
constant st2: std_logic_vector(47 downto 0) := "001000000000000000000000000000000000000000000000";
constant st3: std_logic_vector(47 downto 0) := "000100000000000000000000000000000000000000000000";
constant st4: std_logic_vector(47 downto 0) := "000010000000000000000000000000000000000000000000";
constant st42: std_logic_vector(47 downto 0) := "000001000000000000000000000000000000000000000000";
constant st5: std_logic_vector(47 downto 0) := "000000100000000000000000000000000000000000000000";
constant st6: std_logic_vector(47 downto 0) := "000000010000000000000000000000000000000000000000";
constant st7: std_logic_vector(47 downto 0) := "000000001000000000000000000000000000000000000000";
constant st41: std_logic_vector(47 downto 0) := "000000000100000000000000000000000000000000000000";
constant st38: std_logic_vector(47 downto 0) := "000000000010000000000000000000000000000000000000";
constant st8: std_logic_vector(47 downto 0) := "000000000001000000000000000000000000000000000000";
constant st10: std_logic_vector(47 downto 0) := "000000000000100000000000000000000000000000000000";
constant st9: std_logic_vector(47 downto 0) := "000000000000010000000000000000000000000000000000";
constant st11: std_logic_vector(47 downto 0) := "000000000000001000000000000000000000000000000000";
constant st12: std_logic_vector(47 downto 0) := "000000000000000100000000000000000000000000000000";
constant st13: std_logic_vector(47 downto 0) := "000000000000000010000000000000000000000000000000";
constant st14: std_logic_vector(47 downto 0) := "000000000000000001000000000000000000000000000000";
constant st15: std_logic_vector(47 downto 0) := "000000000000000000100000000000000000000000000000";
constant st16: std_logic_vector(47 downto 0) := "000000000000000000010000000000000000000000000000";
constant st17: std_logic_vector(47 downto 0) := "000000000000000000001000000000000000000000000000";
constant st18: std_logic_vector(47 downto 0) := "000000000000000000000100000000000000000000000000";
constant st19: std_logic_vector(47 downto 0) := "000000000000000000000010000000000000000000000000";
constant st46: std_logic_vector(47 downto 0) := "000000000000000000000001000000000000000000000000";
constant st24: std_logic_vector(47 downto 0) := "000000000000000000000000100000000000000000000000";
constant st20: std_logic_vector(47 downto 0) := "000000000000000000000000010000000000000000000000";
constant st25: std_logic_vector(47 downto 0) := "000000000000000000000000001000000000000000000000";
constant st21: std_logic_vector(47 downto 0) := "000000000000000000000000000100000000000000000000";
constant st22: std_logic_vector(47 downto 0) := "000000000000000000000000000010000000000000000000";
constant st23: std_logic_vector(47 downto 0) := "000000000000000000000000000001000000000000000000";
constant st26: std_logic_vector(47 downto 0) := "000000000000000000000000000000100000000000000000";
constant st28: std_logic_vector(47 downto 0) := "000000000000000000000000000000010000000000000000";
constant st30: std_logic_vector(47 downto 0) := "000000000000000000000000000000001000000000000000";
constant st27: std_logic_vector(47 downto 0) := "000000000000000000000000000000000100000000000000";
constant st29: std_logic_vector(47 downto 0) := "000000000000000000000000000000000010000000000000";
constant st31: std_logic_vector(47 downto 0) := "000000000000000000000000000000000001000000000000";
constant st32: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000100000000000";
constant st33: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000010000000000";
constant st35: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000001000000000";
constant st34: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000100000000";
constant st36: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000010000000";
constant st37: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000001000000";
constant st39: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000100000";
constant st40: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000010000";
constant st43: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000001000";
constant st44: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000100";
constant st45: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000010";
constant st47: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(47 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------------------------"; output <= "-------------------";
case current_state is
when st0 =>
if std_match(input, "-------") then next_state <= st1; output <= "001011101000000---0";
end if;
when st1 =>
if std_match(input, "----01-") then next_state <= st1; output <= "--------0000000---0";
elsif std_match(input, "----10-") then next_state <= st1; output <= "--------0100000---1";
elsif std_match(input, "----00-") then next_state <= st1; output <= "1000----1000000---1";
elsif std_match(input, "----11-") then next_state <= st2; output <= "1000111110011001000";
end if;
when st2 =>
if std_match(input, "------0") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---0---") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "1010----1010010---1";
end if;
when st3 =>
if std_match(input, "11-----") then next_state <= st4; output <= "001111101000000-010";
elsif std_match(input, "10-----") then next_state <= st4; output <= "0011111110000000-10";
elsif std_match(input, "0-0-01-") then next_state <= st4; output <= "--------000010000-0";
elsif std_match(input, "0-0-10-") then next_state <= st4; output <= "--------010010000-1";
elsif std_match(input, "0-0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "0-0-00-") then next_state <= st4; output <= "0110----100000000-1";
elsif std_match(input, "0-1-01-") then next_state <= st4; output <= "--------00011000000";
elsif std_match(input, "0-1-10-") then next_state <= st4; output <= "--------01011000001";
elsif std_match(input, "0-1-11-") then next_state <= st42; output <= "011011011001100--00";
elsif std_match(input, "0-1-00-") then next_state <= st4; output <= "0110----10010000001";
end if;
when st4 =>
if std_match(input, "-------") then next_state <= st5; output <= "1010010010000000000";
end if;
when st5 =>
if std_match(input, "--0----") then next_state <= st6; output <= "1000011110000000001";
elsif std_match(input, "--1----") then next_state <= st6; output <= "1000011110010000001";
end if;
when st6 =>
if std_match(input, "-1----0") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-110--1") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-10---1") then next_state <= st41; output <= "101001001000000--00";
elsif std_match(input, "-111--1") then next_state <= st38; output <= "101001001000000--00";
elsif std_match(input, "-0-----") then next_state <= st7; output <= "1010010010000000-00";
end if;
when st7 =>
if std_match(input, "--1----") then next_state <= st8; output <= "0001101010010000000";
elsif std_match(input, "--0----") then next_state <= st8; output <= "0001101010000000000";
end if;
when st8 =>
if std_match(input, "--0----") then next_state <= st10; output <= "1010010010000000000";
elsif std_match(input, "--1----") then next_state <= st9; output <= "1010010010000000000";
end if;
when st9 =>
if std_match(input, "-11----") then next_state <= st11; output <= "001011101001000-000";
elsif std_match(input, "-01----") then next_state <= st11; output <= "0010111110010000-00";
elsif std_match(input, "-10----") then next_state <= st11; output <= "001011101000000-000";
elsif std_match(input, "-00----") then next_state <= st11; output <= "0010111110000000-00";
end if;
when st10 =>
if std_match(input, "--1----") then next_state <= st12; output <= "0010----10010000001";
elsif std_match(input, "--0----") then next_state <= st12; output <= "0010----10000000001";
end if;
when st11 =>
if std_match(input, "-------") then next_state <= st13; output <= "1010010010000000000";
end if;
when st12 =>
if std_match(input, "-------") then next_state <= st14; output <= "1010010010000000000";
end if;
when st13 =>
if std_match(input, "-11----") then next_state <= st15; output <= "010110011001000-000";
elsif std_match(input, "-10----") then next_state <= st15; output <= "010110011000000-000";
elsif std_match(input, "-01----") then next_state <= st15; output <= "0101100010010000-00";
elsif std_match(input, "-00----") then next_state <= st15; output <= "0101100010000000-00";
end if;
when st14 =>
if std_match(input, "--1----") then next_state <= st15; output <= "0101----10010000001";
elsif std_match(input, "--0----") then next_state <= st15; output <= "0101----10000000001";
end if;
when st15 =>
if std_match(input, "-------") then next_state <= st16; output <= "1010010010000000000";
end if;
when st16 =>
if std_match(input, "--1----") then next_state <= st17; output <= "0110010110010000001";
elsif std_match(input, "--0----") then next_state <= st17; output <= "0110010110000000001";
end if;
when st17 =>
if std_match(input, "---0---") then next_state <= st18; output <= "1010010010000000000";
elsif std_match(input, "01-1---") then next_state <= st19; output <= "101001001000001-0-0";
elsif std_match(input, "00-1--0") then next_state <= st19; output <= "1010010010000010--0";
elsif std_match(input, "00-1--1") then next_state <= st46; output <= "101001001000000---0";
elsif std_match(input, "11-1---") then next_state <= st24; output <= "101001001000001-000";
elsif std_match(input, "10-1--0") then next_state <= st24; output <= "1010010010000010-00";
elsif std_match(input, "10-1--1") then next_state <= st18; output <= "1010010010000000-00";
end if;
when st18 =>
if std_match(input, "--1----") then next_state <= st2; output <= "1000111110010000000";
elsif std_match(input, "0-0----") then next_state <= st2; output <= "1000----10000000001";
elsif std_match(input, "1-0----") then next_state <= st2; output <= "1000111110000000000";
end if;
when st19 =>
if std_match(input, "-10----") then next_state <= st20; output <= "100101001000000-0-0";
elsif std_match(input, "-00----") then next_state <= st20; output <= "1001010110000000--0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st20 =>
if std_match(input, "-10----") then next_state <= st19; output <= "101001001000000-0-0";
elsif std_match(input, "-11----") then next_state <= st21; output <= "101001001000000-0-0";
elsif std_match(input, "-01----") then next_state <= st19; output <= "1010010010000000--0";
elsif std_match(input, "-00----") then next_state <= st21; output <= "1010010010000000--0";
end if;
when st21 =>
if std_match(input, "-10----") then next_state <= st22; output <= "001111111000000-0-0";
elsif std_match(input, "-11----") then next_state <= st23; output <= "001111111001000--00";
elsif std_match(input, "-00----") then next_state <= st22; output <= "0011111010000000--0";
elsif std_match(input, "-01----") then next_state <= st23; output <= "001111101001000--00";
end if;
when st22 =>
if std_match(input, "-------") then next_state <= st19; output <= "10100100100000000-0";
end if;
when st23 =>
if std_match(input, "-------") then next_state <= st24; output <= "101001001000000--00";
end if;
when st24 =>
if std_match(input, "-------") then next_state <= st25; output <= "100011111000000--00";
end if;
when st25 =>
if std_match(input, "---0--0") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1--0") then next_state <= st28; output <= "101001001000010--00";
elsif std_match(input, "------1") then next_state <= st30; output <= "101001001000000--10";
end if;
when st26 =>
if std_match(input, "--0-01-") then next_state <= st27; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st27; output <= "--------0100100---1";
elsif std_match(input, "--0-00-") then next_state <= st27; output <= "0110----1000000---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st27 =>
if std_match(input, "-------") then next_state <= st26; output <= "101001001000000---0";
end if;
when st28 =>
if std_match(input, "-------") then next_state <= st29; output <= "011001011000000--01";
end if;
when st29 =>
if std_match(input, "---1---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "--10---") then next_state <= st3; output <= "1010010010000001000";
elsif std_match(input, "--00---") then next_state <= st3; output <= "1010010010000000100";
end if;
when st30 =>
if std_match(input, "-------") then next_state <= st31; output <= "100001111000000---1";
end if;
when st31 =>
if std_match(input, "---0---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st32; output <= "101001001000000---0";
end if;
when st32 =>
if std_match(input, "--0----") then next_state <= st33; output <= "100101011000000---0";
elsif std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
end if;
when st33 =>
if std_match(input, "--10---") then next_state <= st32; output <= "101001001000000---0";
elsif std_match(input, "--0----") then next_state <= st34; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st34; output <= "101001001000000---0";
end if;
when st34 =>
if std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
elsif std_match(input, "--0----") then next_state <= st35; output <= "011011011000000---0";
end if;
when st35 =>
if std_match(input, "-------") then next_state <= st36; output <= "101001001000000--00";
end if;
when st36 =>
if std_match(input, "--0----") then next_state <= st37; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st37; output <= "011011101001000--00";
end if;
when st37 =>
if std_match(input, "-------") then next_state <= st9; output <= "1010010010000000100";
end if;
when st38 =>
if std_match(input, "--0-01-") then next_state <= st39; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st39; output <= "--------0100100---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--0-00-") then next_state <= st39; output <= "0110----1000000---1";
elsif std_match(input, "--1----") then next_state <= st40; output <= "100011111001000--00";
end if;
when st39 =>
if std_match(input, "-------") then next_state <= st38; output <= "101001001000000---0";
end if;
when st40 =>
if std_match(input, "-------") then next_state <= st41; output <= "101001001000000--10";
end if;
when st41 =>
if std_match(input, "-------") then next_state <= st42; output <= "011011011000000---0";
end if;
when st42 =>
if std_match(input, "-------") then next_state <= st43; output <= "101001001000000--00";
end if;
when st43 =>
if std_match(input, "--0----") then next_state <= st44; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st44; output <= "011011101001000--00";
end if;
when st44 =>
if std_match(input, "-------") then next_state <= st45; output <= "101001001000000--00";
end if;
when st45 =>
if std_match(input, "--0----") then next_state <= st6; output <= "0111001110000000100";
elsif std_match(input, "--1----") then next_state <= st6; output <= "0111001110010000100";
end if;
when st46 =>
if std_match(input, "--0----") then next_state <= st47; output <= "1000----1000000---1";
elsif std_match(input, "--1----") then next_state <= st0; output <= "100011111011010---0";
end if;
when st47 =>
if std_match(input, "-------") then next_state <= st46; output <= "101001001000000---0";
end if;
when others => next_state <= "------------------------------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 7ad44ce1104962d7fdabc6caa8a92b63 | 0.623299 | 4.021107 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/aes_core.vhd | 2 | 7,238 | ------------------------------------------------------
------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity aes_core is port (
data_inH : in std_logic_vector( 127 downto 0 );
input_key : in std_logic_vector( 127 downto 0 );
go_cipher, go_key, enc_command : in std_logic;
data_outH : out std_logic_vector( 127 downto 0 );
data_out_ok : out std_logic;
ready_out : out std_logic;
error : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
rst, ck : in std_logic;
fault_aes_port : in std_logic_vector( 7 downto 0 )
);
end aes_core;
-- Architecture of the Component
architecture arch of aes_core is
component dataunit_ddr is port (
inH : in std_logic_vector( 127 downto 0 );
key : in std_logic_vector( 127 downto 0 );
aux_sbox_in : in std_logic_vector(31 downto 0);
ctrl_dec : in T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : in T_ENABLE;
enable_SBox_sharing : in T_ENABLE;
ctrl_barrel : in std_logic_vector( 1 downto 0 );
enable_main, enable_dual, select_dual1, select_dual2 : in T_ENABLE;
check_dual : in T_ENABLE;
clock, reset : in std_logic;
broken: out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
outH : out std_logic_vector( 127 downto 0 );
outKey : out std_logic_vector(31 downto 0);
fault_data_unit_port : in std_logic_vector( 7 downto 0 )
);
end component;
component control_ddr is port (
go_crypt, go_key : in std_logic; -- active HIGH
encdec : in std_logic; -- 0=encrypt, 1=decrypt
--key_size : in std_logic_vector( 1 downto 0 ); -- 01=128, 10=192, 11=256
ready_out : out T_READY; -- device state: S_READY or S_BUSY
data_out_ok : out T_ENABLE; -- Validity bit for the output
ctrl_dec : out T_ENCDEC; -- S_ENC / S_DEC
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : out T_ENABLE;
enable_SBox_sharing : out T_ENABLE;
ctrl_barrel : out std_logic_vector( 1 downto 0 ); --
next_roundkey, next_rcon, save_key : out T_ENABLE; -- Active HIGH
rewind_key : out T_ENABLE; -- Key rewinding; active according to config file
enable_main, enable_dual : out T_ENABLE; -- C_DISABLE / C_ENABLE
select_dual1, select_dual2 : out T_ENABLE; -- C_DISABLE / C_ENABLE
check_dual : out T_ENABLE; -- C_DISABLE / C_ENABLE
control_error : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
reset, clk : in std_logic ); -- Global signals; active according to config file
end component;
component keyunit is port (
key_in : in std_logic_vector (127 downto 0);
in_ready : in T_READY;
load_key : in std_logic;
advance_key : in T_ENABLE; -- next_step
reset_key : in T_ENABLE; -- rewind
save_key : in T_ENABLE; -- checkpoint: saved key for later rewind
ctrl_dec : in T_ENCDEC;
next_rcon : in T_ENABLE; -- next_step
reset, clk : in std_logic;
data_to_sbox : out std_logic_vector (31 downto 0); -- data to DU's Sboxes
data_from_sbox: in std_logic_vector (31 downto 0); --- data from DU's Sboxes
key_out : out std_logic_vector (127 downto 0) ); -- ROUND KEY
end component;
-- Data signals: -------------------------------------------------------------
signal s_data_in_H, s_data_out_H : std_logic_vector( 127 downto 0 );
signal s_round_key : std_logic_vector( 127 downto 0 );
signal s_KS_to_DU, s_DU_to_KS : std_logic_vector( 31 downto 0 );
-- Control signals: ----------------------------------------------------------
signal s_ready : T_READY;
signal s_data_out_ok : T_ENABLE;
signal s_go_key : std_logic;
signal s_go_crypt : std_logic;
signal s_ctrl_dec : T_ENCDEC;
signal s_enable_key_pre_add, s_enable_key_add, s_enable_MixCol,
s_enable_H_in, s_enable_SBox_sharing : T_ENABLE;
signal s_ctrl_barrel : std_logic_vector( 1 downto 0 );
signal s_enable_main, s_enable_dual, s_select_dual1, s_select_dual2, s_check_dual : T_ENABLE;
signal s_control_error, s_broken: std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
signal s_advance_round_key, s_advance_rcon, s_save_key, s_rewind_key : T_ENABLE;
signal fault_sig : std_logic_vector( 7 downto 0 );
begin
s_go_crypt <= go_cipher;
s_go_key <= go_key;
s_data_in_H <= data_inH;
fault_sig <= fault_aes_port;
DU : dataunit_ddr port map(
inH => s_data_in_H,
key => s_round_key,
aux_sbox_in => s_KS_to_DU,
ctrl_dec => s_ctrl_dec,
enable_key_pre_add => s_enable_key_pre_add,
enable_key_add => s_enable_key_add,
enable_MixCol => s_enable_MixCol,
enable_H_in => s_enable_H_in,
enable_SBox_sharing => s_enable_SBox_sharing,
ctrl_barrel => s_ctrl_barrel,
enable_main => s_enable_main,
enable_dual => s_enable_dual,
select_dual1 => s_select_dual1,
select_dual2 => s_select_dual2,
check_dual => s_check_dual,
clock => ck,
reset => rst,
broken => s_broken,
outH => s_data_out_H,
outKey => s_DU_to_KS,
fault_data_unit_port => fault_sig
);
CU : control_ddr port map(
go_crypt => s_go_crypt,
go_key => s_go_key,
encdec => enc_command,
ready_out => s_ready,
data_out_ok => s_data_out_ok,
ctrl_dec => s_ctrl_dec,
enable_key_pre_add => s_enable_key_pre_add,
enable_key_add => s_enable_key_add,
enable_MixCol => s_enable_MixCol,
enable_H_in => s_enable_H_in,
enable_SBox_sharing => s_enable_SBox_sharing,
ctrl_barrel => s_ctrl_barrel,
next_roundkey => s_advance_round_key,
next_rcon => s_advance_rcon, --*
save_key => s_save_key,
rewind_key => s_rewind_key,
enable_main => s_enable_main,
enable_dual => s_enable_dual,
select_dual1 => s_select_dual1,
select_dual2 => s_select_dual2,
check_dual => s_check_dual,
control_error => s_control_error,
reset => rst,
clk => ck );
KU : keyunit port map(
key_in => input_key,
in_ready => s_ready,
load_key => s_go_key,
advance_key => s_advance_round_key,
reset_key => s_rewind_key,
save_key => s_save_key,
ctrl_dec => s_ctrl_dec,
next_rcon => s_advance_rcon,
reset => rst,
clk => ck,
data_to_sbox => s_KS_to_DU,
data_from_sbox => s_DU_to_KS,
key_out => s_round_key );
-- DATA OUT PROCESS ----------------------------------------------------------
-- Latch (transparent on high clock) to filter DDR data
DATA_OUT_PROCESS : process( ck )
begin
if ( ck'event and ck='0' ) then
if ( s_data_out_ok=C_ENABLE ) then
data_outH <= s_data_out_H;
data_out_ok <= '1';
else
data_outH <= ( others => '0' );
data_out_ok <= '0';
end if;
end if;
end process DATA_OUT_PROCESS;
ready_out <= '0' when ( s_ready=C_BUSY ) else '1';
error <= ( not C_BROKEN )
when ( s_broken = not C_BROKEN ) and
( s_control_error = not C_BROKEN )
else C_BROKEN;
end arch;
| mit | 86763ddca5bf62804b4d95b1ff5e3c19 | 0.572948 | 3.212605 | false | false | false | false |
chastell/art-decomp | kiss/train11_jed.vhd | 1 | 3,530 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train11_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train11_jed;
architecture behaviour of train11_jed is
constant st0: std_logic_vector(3 downto 0) := "1110";
constant st1: std_logic_vector(3 downto 0) := "0110";
constant st2: std_logic_vector(3 downto 0) := "1011";
constant st3: std_logic_vector(3 downto 0) := "1100";
constant st5: std_logic_vector(3 downto 0) := "0010";
constant st7: std_logic_vector(3 downto 0) := "1111";
constant st9: std_logic_vector(3 downto 0) := "0011";
constant st4: std_logic_vector(3 downto 0) := "1000";
constant st6: std_logic_vector(3 downto 0) := "1010";
constant st8: std_logic_vector(3 downto 0) := "0111";
constant st10: std_logic_vector(3 downto 0) := "0100";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st2; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st5; output <= "1";
end if;
when st2 =>
if std_match(input, "01") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "11") then next_state <= st9; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st4; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st5 =>
if std_match(input, "11") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "10") then next_state <= st8; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st9 =>
if std_match(input, "11") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st10; output <= "1";
end if;
when st10 =>
if std_match(input, "10") then next_state <= st10; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 673c692a6ea30f0862778f967f950b05 | 0.572521 | 3.232601 | false | false | false | false |
es17m014/vhdl-counter | src/old/vhdl/bcd_driver.vhd | 1 | 3,181 | -- --------------------------------------------------------------
-- Title : BCD driver
-- Project : Counter
-- --------------------------------------------------------------
-- File : bcd_dekoder.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 29.10.2017
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description : This unit is the driver for the BCD 7-seg module
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 29.10.2017 1.0 Martin Angermair init
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seven_segment_driver is
generic (g_refresh_rate : positive := 100000);
port ( clk_i : in std_logic; -- 100Mhz clock on Basys 3 FPGA board
reset_i : in std_logic; -- reset_i
dig0_i : in std_logic_vector(7 downto 0); -- first digit value
dig1_i : in std_logic_vector(7 downto 0); -- second digit value
dig2_i : in std_logic_vector(7 downto 0); -- third digit value
dig3_i : in std_logic_vector(7 downto 0); -- fourth digit value
ss_sel_o : out std_logic_vector(3 downto 0); -- 4 anode signals
ss_o : out std_logic_vector(7 downto 0)); -- cathode patterns of 7-segment display
end seven_segment_driver;
architecture rtl of seven_segment_driver is
TYPE led_refresh_state IS (SEG1, SEG2, SEG3, SEG4);
signal s_bcd_state : led_refresh_state;
signal s_1kHz : std_logic;
begin
-- refresh rate at which the 4 7-seg digits will be updated
e_1kHz_prescaler: entity work.prescaler generic map (G_N => g_refresh_rate) port map (clk_i, reset_i, s_1kHz, '0');
-- 4-to-1 MUX to generate anode activating signals for 4 LEDs
p_bcd_mux_state: process(clk_i)
begin
if reset_i = '0' then -- asynchronous reset (active low)
ss_sel_o <= "1111"; -- disable all LED
ss_o <= "11111111";
s_bcd_state <= SEG1;
elsif rising_edge(clk_i) and s_1kHz = '1' then
case s_bcd_state is
when SEG1 =>
ss_sel_o <= "0111"; -- activate only LED1
ss_o <= dig0_i;
s_bcd_state <= SEG2;
when SEG2 =>
ss_sel_o <= "1011"; -- activate only LED2
ss_o <= dig1_i;
s_bcd_state <= SEG3;
when SEG3 =>
ss_sel_o <= "1101"; -- activate only LED3
ss_o <= dig2_i;
s_bcd_state <= SEG4;
when SEG4 =>
ss_sel_o <= "1110"; -- activate only LED4
ss_o <= dig3_i;
s_bcd_state <= SEG1;
end case;
end if;
end process p_bcd_mux_state;
end rtl; | mit | 9b8b74dba287c3bd74d4b51a211b7cff | 0.45426 | 3.97625 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_debounce_.vhd | 1 | 2,077 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : tb_debounce.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_debounce is
end tb_debounce;
architecture sim of tb_debounce is
-- Declaration of the component under test
component debounce
port (
clk_i : in std_logic; --input clock
btn_i : in std_logic; --input signal to be debounced
deb_o : out std_logic); --debounced signal
end component;
signal clk_i : std_logic;
signal btn_i : std_logic;
signal deb_o : std_logic;
begin
-- Instantiate the design under test
i_debounce : debounce
port map (
clk_i => clk_i,
btn_i => btn_i,
deb_o => deb_o);
-- Generate clock
p_clk : process
begin
clk_i <= '0';
wait for 50 ns;
clk_i <= '1';
wait for 50 ns;
end process p_clk;
-- Generate reset
p_reset : process
begin
reset_i <= '1';
wait for 120 ns;
reset_i <= '0';
wait;
end process p_reset;
p_stim : process
begin
data_i <= '0';
wait for 320 ns;
data_i <= '1';
wait for 400 ns;
data_i <= '0';
wait for 400 ns;
data_i <= '1';
wait for 400 ns;
-- stop simulation
assert false report "END OF SIMULATION" severity error;
end process p_stim;
end sim;
| mit | c5584b8da9744a281d644db58f238486 | 0.476649 | 4.273663 | false | false | false | false |
Diego-HR/HL-Object-Oriented | QAMDemodulator/src/solution1/syn/vhdl/qam_dem_top.vhd | 4 | 10,015 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity qam_dem_top is
port (
din_i_V : IN STD_LOGIC_VECTOR (15 downto 0);
din_q_V : IN STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_q_V : OUT STD_LOGIC_VECTOR (15 downto 0);
ph_in_i_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_in_q_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_q_V : OUT STD_LOGIC_VECTOR (11 downto 0);
loop_integ_V : OUT STD_LOGIC_VECTOR (27 downto 0);
control_qam_V : IN STD_LOGIC_VECTOR (1 downto 0);
control_lf_p : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_i : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_out_gain : IN STD_LOGIC_VECTOR (7 downto 0);
control_reg_clr : IN STD_LOGIC_VECTOR (0 downto 0);
control_reg_init_V : IN STD_LOGIC_VECTOR (27 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC );
end;
architecture behav of qam_dem_top is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"qam_dem_top,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc6slx45tfgg484-3,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.646000,HLS_SYN_LAT=14,HLS_SYN_TPT=15,HLS_SYN_MEM=1,HLS_SYN_DSP=0,HLS_SYN_FF=436,HLS_SYN_LUT=1285}";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv28_0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
signal qam_dem_top_mounstrito_U0_ap_start : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_ap_done : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_ap_continue : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_ap_idle : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_ap_ready : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_din_i_V : STD_LOGIC_VECTOR (15 downto 0);
signal qam_dem_top_mounstrito_U0_din_q_V : STD_LOGIC_VECTOR (15 downto 0);
signal qam_dem_top_mounstrito_U0_dout_mix_i_V : STD_LOGIC_VECTOR (15 downto 0);
signal qam_dem_top_mounstrito_U0_dout_mix_i_V_ap_vld : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_dout_mix_q_V : STD_LOGIC_VECTOR (15 downto 0);
signal qam_dem_top_mounstrito_U0_dout_mix_q_V_ap_vld : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_ph_in_i_V : STD_LOGIC_VECTOR (11 downto 0);
signal qam_dem_top_mounstrito_U0_ph_in_q_V : STD_LOGIC_VECTOR (11 downto 0);
signal qam_dem_top_mounstrito_U0_ph_out_i_V : STD_LOGIC_VECTOR (11 downto 0);
signal qam_dem_top_mounstrito_U0_ph_out_i_V_ap_vld : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_ph_out_q_V : STD_LOGIC_VECTOR (11 downto 0);
signal qam_dem_top_mounstrito_U0_ph_out_q_V_ap_vld : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_loop_integ_V : STD_LOGIC_VECTOR (27 downto 0);
signal qam_dem_top_mounstrito_U0_loop_integ_V_ap_vld : STD_LOGIC;
signal qam_dem_top_mounstrito_U0_control_lf_p : STD_LOGIC_VECTOR (7 downto 0);
signal qam_dem_top_mounstrito_U0_control_lf_i : STD_LOGIC_VECTOR (7 downto 0);
signal qam_dem_top_mounstrito_U0_control_lf_out_gain : STD_LOGIC_VECTOR (7 downto 0);
signal qam_dem_top_mounstrito_U0_control_reg_clr : STD_LOGIC_VECTOR (0 downto 0);
signal qam_dem_top_mounstrito_U0_control_reg_init_V : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_hs_continue : STD_LOGIC;
signal ap_reg_procdone_qam_dem_top_mounstrito_U0 : STD_LOGIC := '0';
signal ap_sig_hs_done : STD_LOGIC;
signal ap_CS : STD_LOGIC;
signal ap_sig_top_allready : STD_LOGIC;
component qam_dem_top_mounstrito IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
din_i_V : IN STD_LOGIC_VECTOR (15 downto 0);
din_q_V : IN STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V_ap_vld : OUT STD_LOGIC;
dout_mix_q_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_q_V_ap_vld : OUT STD_LOGIC;
ph_in_i_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_in_q_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V_ap_vld : OUT STD_LOGIC;
ph_out_q_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_q_V_ap_vld : OUT STD_LOGIC;
loop_integ_V : OUT STD_LOGIC_VECTOR (27 downto 0);
loop_integ_V_ap_vld : OUT STD_LOGIC;
control_lf_p : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_i : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_out_gain : IN STD_LOGIC_VECTOR (7 downto 0);
control_reg_clr : IN STD_LOGIC_VECTOR (0 downto 0);
control_reg_init_V : IN STD_LOGIC_VECTOR (27 downto 0) );
end component;
begin
qam_dem_top_mounstrito_U0 : component qam_dem_top_mounstrito
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => qam_dem_top_mounstrito_U0_ap_start,
ap_done => qam_dem_top_mounstrito_U0_ap_done,
ap_continue => qam_dem_top_mounstrito_U0_ap_continue,
ap_idle => qam_dem_top_mounstrito_U0_ap_idle,
ap_ready => qam_dem_top_mounstrito_U0_ap_ready,
din_i_V => qam_dem_top_mounstrito_U0_din_i_V,
din_q_V => qam_dem_top_mounstrito_U0_din_q_V,
dout_mix_i_V => qam_dem_top_mounstrito_U0_dout_mix_i_V,
dout_mix_i_V_ap_vld => qam_dem_top_mounstrito_U0_dout_mix_i_V_ap_vld,
dout_mix_q_V => qam_dem_top_mounstrito_U0_dout_mix_q_V,
dout_mix_q_V_ap_vld => qam_dem_top_mounstrito_U0_dout_mix_q_V_ap_vld,
ph_in_i_V => qam_dem_top_mounstrito_U0_ph_in_i_V,
ph_in_q_V => qam_dem_top_mounstrito_U0_ph_in_q_V,
ph_out_i_V => qam_dem_top_mounstrito_U0_ph_out_i_V,
ph_out_i_V_ap_vld => qam_dem_top_mounstrito_U0_ph_out_i_V_ap_vld,
ph_out_q_V => qam_dem_top_mounstrito_U0_ph_out_q_V,
ph_out_q_V_ap_vld => qam_dem_top_mounstrito_U0_ph_out_q_V_ap_vld,
loop_integ_V => qam_dem_top_mounstrito_U0_loop_integ_V,
loop_integ_V_ap_vld => qam_dem_top_mounstrito_U0_loop_integ_V_ap_vld,
control_lf_p => qam_dem_top_mounstrito_U0_control_lf_p,
control_lf_i => qam_dem_top_mounstrito_U0_control_lf_i,
control_lf_out_gain => qam_dem_top_mounstrito_U0_control_lf_out_gain,
control_reg_clr => qam_dem_top_mounstrito_U0_control_reg_clr,
control_reg_init_V => qam_dem_top_mounstrito_U0_control_reg_init_V);
-- ap_reg_procdone_qam_dem_top_mounstrito_U0 assign process. --
ap_reg_procdone_qam_dem_top_mounstrito_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_procdone_qam_dem_top_mounstrito_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_qam_dem_top_mounstrito_U0 <= ap_const_logic_0;
elsif ((qam_dem_top_mounstrito_U0_ap_done = ap_const_logic_1)) then
ap_reg_procdone_qam_dem_top_mounstrito_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_CS assign process. --
ap_CS_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
ap_CS <= ap_const_logic_0;
end if;
end process;
ap_done <= ap_sig_hs_done;
-- ap_idle assign process. --
ap_idle_assign_proc : process(qam_dem_top_mounstrito_U0_ap_idle)
begin
if ((qam_dem_top_mounstrito_U0_ap_idle = ap_const_logic_1)) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_sig_top_allready;
ap_sig_hs_continue <= ap_const_logic_1;
-- ap_sig_hs_done assign process. --
ap_sig_hs_done_assign_proc : process(qam_dem_top_mounstrito_U0_ap_done)
begin
if ((qam_dem_top_mounstrito_U0_ap_done = ap_const_logic_1)) then
ap_sig_hs_done <= ap_const_logic_1;
else
ap_sig_hs_done <= ap_const_logic_0;
end if;
end process;
ap_sig_top_allready <= qam_dem_top_mounstrito_U0_ap_ready;
dout_mix_i_V <= qam_dem_top_mounstrito_U0_dout_mix_i_V;
dout_mix_q_V <= qam_dem_top_mounstrito_U0_dout_mix_q_V;
loop_integ_V <= qam_dem_top_mounstrito_U0_loop_integ_V;
ph_out_i_V <= qam_dem_top_mounstrito_U0_ph_out_i_V;
ph_out_q_V <= qam_dem_top_mounstrito_U0_ph_out_q_V;
qam_dem_top_mounstrito_U0_ap_continue <= ap_sig_hs_continue;
qam_dem_top_mounstrito_U0_ap_start <= ap_start;
qam_dem_top_mounstrito_U0_control_lf_i <= control_lf_i;
qam_dem_top_mounstrito_U0_control_lf_out_gain <= control_lf_out_gain;
qam_dem_top_mounstrito_U0_control_lf_p <= control_lf_p;
qam_dem_top_mounstrito_U0_control_reg_clr <= control_reg_clr;
qam_dem_top_mounstrito_U0_control_reg_init_V <= control_reg_init_V;
qam_dem_top_mounstrito_U0_din_i_V <= din_i_V;
qam_dem_top_mounstrito_U0_din_q_V <= din_q_V;
qam_dem_top_mounstrito_U0_ph_in_i_V <= ph_in_i_V;
qam_dem_top_mounstrito_U0_ph_in_q_V <= ph_in_q_V;
end behav;
| gpl-2.0 | 193599eed6d94e19594cb6213e7e953f | 0.625262 | 2.7804 | false | false | false | false |
chastell/art-decomp | kiss/dk14_jed.vhd | 1 | 6,084 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_jed;
architecture behaviour of dk14_jed is
constant state_1: std_logic_vector(2 downto 0) := "010";
constant state_3: std_logic_vector(2 downto 0) := "100";
constant state_2: std_logic_vector(2 downto 0) := "000";
constant state_4: std_logic_vector(2 downto 0) := "001";
constant state_5: std_logic_vector(2 downto 0) := "110";
constant state_6: std_logic_vector(2 downto 0) := "101";
constant state_7: std_logic_vector(2 downto 0) := "111";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-----";
case current_state is
when state_1 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_2 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_1; output <= "00001";
elsif std_match(input, "010") then next_state <= state_2; output <= "00001";
end if;
when state_3 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_4 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "10100";
elsif std_match(input, "010") then next_state <= state_7; output <= "10000";
end if;
when state_5 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_6 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10100";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_7 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when others => next_state <= "---"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 515ee4c0799b47b33708d0e1374fb8a1 | 0.599277 | 3.368771 | false | false | false | false |
ibm2030/IBM2030 | ibm2030-vga.vhd | 1 | 50,567 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-vga.vhd
-- Creation Date:
-- Description:
-- Virtual front panel with indicators via VGA
-- Uses the vga_controller_640-60 module provided by Digilent
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Add Multiplexor Tag indicators
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
entity vga_panel IS
port
(
-- Inputs
Indicators : in std_logic_vector(IndicatorRange);
-- Outputs
Red,Green,Blue,HS,VS : out std_logic;
-- Clocks
Clock50 : in std_logic -- 50MHz clock
);
end entity vga_panel;
architecture behavioural of vga_panel is
-- Layout is 640x480 pixels, divided into 32 columns and 24 rows of 20x20 pixel 'characters'
constant totalLines : integer := 24;
constant totalColumns : integer := 32;
subtype lines is integer range 0 to (totalLines-1);
subtype columns is integer range 0 to (totalColumns-1);
constant totalCharacters : integer := (lines'right+1)*(columns'right+1);
subtype screenCharacterOffset is integer range 0 to totalCharacters-1;
-- Basic screen layout as characters, should correspond to indLayout
type screenType is array(lines,columns) of character;
constant screen : screenType :=
(" CN ADR W X ",
" P012345 P ! P18421 P84218421 ",
"SA CH CL CA CBCM CU CK ",
" P0123 0123 A0123 0101201AP0123 ",
"CR CD CF CG CV CC CS ",
" P 0123 012 01 01012A0123 ",
" COUNT REG ",
" P84218421 P84218421 ",
" DATA KEY COMM ",
" P84218421 P8421 8421 ",
" FLAGS TAGS CHECKS ",
" ***** **** $$$$$$ ",
" ***** ",
" ",
" TAGS BUS OUT ",
" stuvwxyz{ P84218421 ",
" MSAR a ",
" P84218421 P84218421 b ",
" MSDR ALU STAT CHKS ",
" P84218421 P84218421 cde fg ",
" B REG A REG h i jkl ",
" P84218421 P84218421 mno pqr ",
"A****B****C****D**** ",
" F****G****H****J**** "
);
-- Screen layout in terms of signals, 0 for fixed characters
type screenIndicators is array(lines,columns) of IndicatorRange;
constant indLayout : screenIndicators :=
(
-- CN,ADRP,W,X
1=>(1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>7, -- CN
10=>8, -- PA
12=>9, -- LP
14=>10,15=>11,16=>12,17=>13,18=>14,19=>15, -- W
22=>16,23=>17,24=>18,25=>19,26=>20,27=>21,28=>22,29=>23,30=>24, -- X
others=>0),
3=>(1=>25,2=>26,3=>27,4=>28,5=>29, -- SA,CH
7=>30,8=>31,9=>32,10=>33, -- CL
12=>34,13=>35,14=>36,15=>37,16=>38, -- AA,CA
18=>39,19=>40,20=>41,21=>42,22=>43,23=>44,24=>45,25=>46,26=>47,27=>48,28=>49,29=>50,30=>51, -- CB,CM,CU,AK,PK,CK
others=>0),
5=>(1=>52, -- PC
3=>53,4=>54,5=>55,6=>56, -- CD
13=>57,14=>58,15=>59, -- CF
18=>60,19=>61, -- CG
21=>62,22=>63,23=>64,24=>65,25=>66,26=>67,27=>68,28=>69,29=>70,30=>71, -- CV,CC,SA,CS
others=>0),
-- Skip SX1 6-12
-- Skip SX2 13-15
-- 13=>(0=>222,1=>218,2=>219,3=>220,4=>221,others => 0), -- P1,2,3,4 for now
-- 14=>(1=>223,2=>224,3=>225,4=>226,others => 0), -- T1,2,3,4 for now
-- 15=>(0=>235,1=>227,2=>228,3=>229,4=>230,5=>231,6=>232,7=>233,8=>234,others=>0),
-- End of SX
15=>(1=>128,2=>129,3=>130,4=>131,5=>132,6=>133,7=>134,8=>135,9=>136, -- Mpx Tags
16=>137,17=>138,18=>139,19=>140,20=>141,21=>142,22=>143,23=>144,24=>145, -- Mpx Bus
others=>0),
16=>(21=>146, -- MAIN STG
others=>0),
17=>(1=>147,2=>148,3=>149,4=>150,5=>151,6=>152,7=>153,8=>154,9=>155, -- M
11=>156,12=>157,13=>158,14=>159,15=>160,16=>161,17=>162,18=>163,19=>164, -- N
21=>165, -- LOC STG
others=>0),
19=>(1=>166,2=>167,3=>168,4=>169,5=>170,6=>171,7=>172,8=>173,9=>174, -- MSDR
11=>175,12=>176,13=>177,14=>178,15=>179,16=>180,17=>181,18=>182,19=>183, -- ALU
22=>184,23=>185,24=>186, -- Stat
27=>187,28=>188, -- Chks
others=>0),
20=>(22=>189,24=>190, -- Stat
27=>191,28=>192,29=>193, -- Chks
others=>0),
21=>(1=>203,2=>204,3=>205,4=>206,5=>207,6=>208,7=>209,8=>210,9=>211, -- B
11=>194,12=>195,13=>196,14=>197,15=>198,16=>199,17=>200,18=>201,19=>202, -- A
22=>212,23=>213,24=>214, -- Stat
27=>215,28=>216,29=>217, -- Chks
others=>0),
22=>(1=>218,2=>219,3=>220,4=>221,6=>222,7=>223,8=>224,9=>225,11=>226,12=>227,13=>228,14=>229,16=>230,17=>231,18=>232,19=>233,others=>0),
23=>(12=>234,13=>235,14=>236,15=>237,17=>238,18=>239,19=>240,20=>241,22=>242,23=>243,24=>244,25=>245,27=>246,28=>247,29=>248,30=>249,others=>0),
others=>(others => 0));
-- To convert ASCII to the internal 6-bit representation...
-- Not all characters are needed, so some special ones are added
subtype characterCode is std_logic_vector(6 downto 0);
type charArray is array(32 to 123) of characterCode;
constant charTranslate : charArray := (
-- 20->62, 21 ! ->61, 22-23->127, 24->59, 25-29->127, 2A->60, 2B-2F->127
"0111110","0111101","1111111","1111111","0111011","1111111","1111111","1111111",
"1111111","1111111","0111100","1111111","1111111","1111111","1111111","1111111",
-- 30 0 to 39 9 -> 0 to 9, 3A : to 3F ? -> 127
"0000000","0000001","0000010","0000011","0000100","0000101","0000110","0000111",
"0001000","0001001","1111111","1111111","1111111","1111111","1111111","1111111",
-- 40 @ -> 127, 41 A to 4F O -> 10 to 24
"1111111","0001010","0001011","0001100","0001101","0001110","0001111","0010000",
"0010001","0010010","0010011","0010100","0010101","0010110","0010111","0011000",
-- 50 P to 5A Z -> 25 to 35
"0011001","0011010","0011011","0011100","0011101","0011110","0011111","0100000",
"0100001","0100010","0100011",
-- 5B to 60 -> 127
"1111111","1111111","1111111","1111111","1111111","1111111",
-- 61 a to 6F o -> 63 to 77
"0111111","1000000","1000001","1000010","1000011","1000100","1000101","1000110",
"1000111","1001000","1001001","1001010","1001011","1001100","1001101",
-- 70 p to 7A z -> 78 to 88, 7B { -> 89
"1001110","1001111","1010000","1010001","1010010","1010011","1010100","1010101",
"1010110","1010111","1011000","1011001"
);
-- Character bitmaps
-- Fairly self-explanatory
constant characterHeight : integer := 20;
constant characterWidth : integer := 20;
subtype pixLinesRange is integer range 0 to (characterHeight-1);
subtype pixColsRange is integer range 0 to (characterWidth-1);
subtype pixelType is std_logic_vector(1 to 3); -- RGB
subtype pixelRow is std_logic_vector(pixColsRange); -- One scan line
subtype characterRange is integer range 0 to (2**(characterCode'left+1)-1);
type characterGeneratorType is array(characterRange,pixLinesRange) of pixelRow;
constant characterGenerator : characterGeneratorType :=
( 0 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000111100000000",
"00000001111110000000",
"00000011100111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011100111000000",
"00000001111110000000",
"00000000111100000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
1 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000011000000000",
"00000000111000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000111100000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
2 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000111110000000",
"00000001111111000000",
"00000011000011000000",
"00000000000011000000",
"00000000000011000000",
"00000000000110000000",
"00000000001100000000",
"00000000011000000000",
"00000000110000000000",
"00000001111111000000",
"00000011111111000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
3 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000010000011000000",
"00000000000011000000",
"00000000000111000000",
"00000000011110000000",
"00000000000110000000",
"00000000000011000000",
"00000010000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
4 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000001100000000",
"00000000011100000000",
"00000000011100000000",
"00000000111100000000",
"00000000101100000000",
"00000001101100000000",
"00000011001100000000",
"00000011111111000000",
"00000011111111000000",
"00000000001100000000",
"00000000001100000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
5 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111111000000",
"00000011111111000000",
"00000011000000000000",
"00000011000000000000",
"00000011111110000000",
"00000011111111000000",
"00000000000011000000",
"00000000000011000000",
"00000000000011000000",
"00000011111111000000",
"00000011111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
6 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000000000000",
"00000011111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
7 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111111000000",
"00000011111111000000",
"00000000000011000000",
"00000000000110000000",
"00000000000110000000",
"00000000001100000000",
"00000000001100000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
8 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000111100000000",
"00000001111110000000",
"00000011000011000000",
"00000011000011000000",
"00000001111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
10 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000011000000000",
"00000000111100000000",
"00000001100110000000",
"00000001100110000000",
"00000001000010000000",
"00000011111111000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
11 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011111110000000",
"00000011111110000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000011111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
12 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
13 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000011111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
14 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111111000000",
"00000011111111000000",
"00000011000000000000",
"00000011000000000000",
"00000011111100000000",
"00000011111100000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011111111000000",
"00000011111111000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
15 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111111000000",
"00000011111111000000",
"00000011000000000000",
"00000011000000000000",
"00000011111100000000",
"00000011111100000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
16 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000000000000",
"00000011000000000000",
"00000011001111000000",
"00000011001111000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000001111111000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
17 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
19 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111111000000",
"00000011111111000000",
"00000000001100000000",
"00000000001100000000",
"00000000001100000000",
"00000000001100000000",
"00000000001100000000",
"00000011001100000000",
"00000011001100000000",
"00000011111100000000",
"00000001111000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
20=> ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000110000000",
"00000011001100000000",
"00000011011000000000",
"00000011110000000000",
"00000011100000000000",
"00000011110000000000",
"00000011011000000000",
"00000011001100000000",
"00000011000110000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
21 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011111111000000",
"00000011111111000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
22 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011100111000000",
"00000011111111000000",
"00000011111111000000",
"00000011011011000000",
"00000011011011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
23 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011100011000000",
"00000011110011000000",
"00000011110011000000",
"00000011011011000000",
"00000011011011000000",
"00000011011011000000",
"00000011001111000000",
"00000011001111000000",
"00000011000111000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
24 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
25 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000011111110000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000011000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
27 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000011111110000000",
"00000011111000000000",
"00000011011100000000",
"00000011001110000000",
"00000011000111000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
28 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000011000011000000",
"00000011100000000000",
"00000001110000000000",
"00000000111100000000",
"00000000001110000000",
"00000000000111000000",
"00000011000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
29 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011111111000000",
"00000011111111000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
30=> ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
31 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011100111000000",
"00000011100111000000",
"00000001100110000000",
"00000001111110000000",
"00000000111100000000",
"00000000111100000000",
"00000000011000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
32 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011000011000000",
"00000011011011000000",
"00000011011011000000",
"00000011111111000000",
"00000011100111000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
33 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000011000000",
"00000011100111000000",
"00000000111100000000",
"00000000011000000000",
"00000000011000000000",
"00000000111100000000",
"00000001100110000000",
"00000011100111000000",
"00000011000011000000",
"00000011000011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
34 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000011000011000000",
"00000011000011000000",
"00000011100111000000",
"00000001111110000000",
"00000000111100000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000011000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
59 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000111111111100000",
"00001111111111110000",
"00001111111111110000",
"00001111111111110000",
"00001111111111110000",
"00001111111111110000",
"00000111111111100000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
60 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000001111110000000",
"00000011111111000000",
"00000111111111100000",
"00001111111111110000",
"00001111111111110000",
"00001111111111110000",
"00001111111111110000",
"00001111111111110000",
"00000111111111100000",
"00000011111111000000",
"00000001111110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
61 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"01100000000111111100",
"01100000000111111110",
"01100000000110000110",
"01100000000110000110",
"01100000000111111110",
"01100000000111111100",
"01100000000110000000",
"01100000000110000000",
"01100000000110000000",
"01111111100110000000",
"01111111100110000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
62 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
63 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"10001001000111010001",
"11011010100010011001",
"10101111110010010101",
"10001100010010010011",
"10001100010010010001",
"00000000000000000000",
"01110111110111011110",
"10000001001000110001",
"01110001001000111110",
"00001001001000110010",
"01110001000111010001",
"00000000000000000000",
"00000000000000000000"),
64 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00001000100010100010",
"00010100100010010100",
"00111110100010001000",
"00100010100010010100",
"00100010011100100010",
"00000000000000000000",
"01110111110111011110",
"10000001001000110001",
"01110001001000111110",
"00001001001000110010",
"01110001000111010001",
"00000000000000000000",
"00000000000000000000"),
65 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00011111010001000000",
"00010000001010000000",
"00011100000100000000",
"00010000001010000000",
"00011111010001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
66 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"10010110111011010100",
"11111001010100110100",
"10011111010100011100",
"10011001010100110100",
"10011001010011010100",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
67 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"01101000100001101001",
"10011000100010011001",
"11111000100010011001",
"10011000100010011111",
"10011111111101101001",
"00000000000000000000",
"10011110010111011110",
"10011001010010010000",
"10011110010010011100",
"11111010010010010000",
"10011001010010011110",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
68 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111111101100111000",
"01000001010010100100",
"01110001010010111000",
"00001001010010101000",
"01110001001100100100",
"00000000000000000000",
"00110111011100000000",
"01001100110010000000",
"01111100111100000000",
"01001100110100000000",
"01001111010010000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
69 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111111101100111000",
"01000001010010100100",
"01110001010010111000",
"00001001010010101000",
"01110001001100100100",
"00000000000000000000",
"01110011001110110000",
"01001100100101001000",
"01001111100101111000",
"01001100100101001000",
"01110100101101001000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
70 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00010011001111001100",
"00010100101000010010",
"00010100101110010010",
"00010100100001010010",
"00010011001110001100",
"00000000000000000000",
"00111010010111010010",
"00010011010010010010",
"00010010110010010010",
"00010010010010001100",
"00111010010010001100",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
71 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00010011001111001100",
"00010100101000010010",
"00010100101110010010",
"00010100100001010010",
"00010011001110001100",
"00000000000000000000",
"00011100111100110000",
"00010010100001001000",
"00011100111001001000",
"00010100100001011000",
"00010010111100111000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
72 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00011100000000000000",
"00010010000000000000",
"00011100000000000000",
"00010010000000000000",
"00011100000000000000",
"00000000000000000000",
"00011100111100110000",
"00010010100001000000",
"00011100111001011000",
"00010100100001001000",
"00010010111100110000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
73 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00001100000000000000",
"00010010000000000000",
"00011110000000000000",
"00010010000000000000",
"00010010000000000000",
"00000000000000000000",
"00011100111100110000",
"00010010100001000000",
"00011100111001011000",
"00010100100001001000",
"00010010111100110000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
74 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00001100100001001000",
"00010010100001001000",
"00011110100001001000",
"00010010100001001000",
"00010010111100110000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
75 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00010010111001001000",
"00011110100100111000",
"00010010111000110000",
"00010010100000110000",
"00010010100001001000",
"00000000000000000000",
"00111010010100101000",
"01000010010110101000",
"01000011110111101000",
"01000010010101101000",
"00111010010100101111",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
76 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00001110111101000000",
"00010000100001000000",
"00001100111001000000",
"00000010100001000000",
"00011100111101111000",
"00000000000000000000",
"00111010010100101000",
"01000010010110101000",
"01000011110111101000",
"01000010010101101000",
"00111010010100101111",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
77 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011010011110000",
"01001100111111001000",
"01000100110011110000",
"01001100110011000000",
"00110011010011000000",
"00000000000000000000",
"01001011011101111000",
"01111100110011000000",
"01001100110011110000",
"01001100110011000000",
"01001011011101111000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
78 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"01110001100011100000",
"01001010010100000000",
"01111010010011000000",
"01010010010000100000",
"01001001100111000000",
"00000000000000000000",
"00110111011100000000",
"01001100110010000000",
"01111100111100000000",
"01001100110100000000",
"01001111010010000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
79 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"01110001100011100000",
"01001010010100000000",
"01111010010011000000",
"01010010010000100000",
"01001001100111000000",
"00000000000000000000",
"00111001100100000111",
"01000010010100001000",
"00110011110100000110",
"00001010010100000001",
"01110011010111101110",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
80 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011101110010000",
"01000001001001010000",
"01000001001110010000",
"01000001001010010000",
"00111001001001011110",
"00000000000000000000",
"01110011110011100000",
"01001010000100000000",
"01110011100101100000",
"01010010000100100000",
"01001011110011000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
81 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011100100101000",
"01001010010110101000",
"01001011100111101000",
"01001010000101101000",
"00110010000100101111",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
82 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011100111001110",
"01001010010100101001",
"01111010010100101110",
"01001010010100101010",
"01001011100111101001",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
83 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011100110011100",
"01000001001001001000",
"00110001001111001000",
"00001001001001001000",
"01110001001001001000",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
84 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011110111001001",
"01000010000100101001",
"00110011100111001001",
"00001010000101000110",
"01110011110100100110",
"00000000000000000000",
"00000011101001000000",
"00000001001101000000",
"00000001001111000000",
"00000001001011000000",
"00000011101001000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
85 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00001110111101000000",
"00010000100001000000",
"00001100111001000000",
"00000010100001000000",
"00011110111101111000",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
86 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00110011100111001110",
"01001010010100101001",
"01111010010100101110",
"01001010010100101010",
"01001011100111101001",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
87 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111010010100101110",
"01000011110111101001",
"01000010010100101001",
"01000010010100101001",
"00111010010100101110",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
88 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111011110111001001",
"01000010000100101001",
"00110011100111001001",
"00001010000101000110",
"01110011110100100110",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
89 => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00111010010111001110",
"01000010010100101001",
"00110010010111001110",
"00001010010100001000",
"01110011110100001000",
"00000000000000000000",
"00001100100101111100",
"00010010100100010000",
"00010010100100010000",
"00010010100100010000",
"00001100111100010000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000"),
others => ("00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000111100000000",
"00000011111111000000",
"00000110000001100000",
"00000110000001100000",
"00000000000011100000",
"00000000000110000000",
"00000000001100000000",
"00000000011000000000",
"00000000011000000000",
"00000000000000000000",
"00000000011000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000")
);
-- Palette definition
-- Each of the 64 characters has its own palette with a FG and BG
-- colour for the Off and On states
-- The bitmaps above provide the FG/BG selection, the Indicators
-- input signals provide the Off/On selection
subtype sigRange is integer range 0 to 1;
subtype paletteRange is integer range 0 to 1;
type paletteType is array(sigRange,paletteRange) of pixelType;
type fullPaletteType is array(characterRange) of paletteType;
constant characterPalette : fullPaletteType :=
( -- Order is: BGOff FGOff BGOn FGOn
59 => (("011","000"),("011","100")),-- Chks are red
61 => (("011","000"),("011","100")),-- LP is red
68 => (("011","000"),("011","100")),-- STOR ADDR is red
69 => (("011","000"),("011","100")),-- STOR DATA is red
72 => (("011","000"),("011","100")),-- B REG is red
73 => (("011","000"),("011","100")),-- A REG is red
74 => (("011","000"),("011","100")),-- ALU is red
78 => (("011","000"),("011","100")),-- ROS ADR is red
79 => (("011","000"),("011","100")),-- ROS SALS is red
80 => (("011","000"),("011","100")),-- CTRL REG is red
others => (("011","000"),("011","110"))
);
-- VGA generation
constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line (800)
constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display (529)
constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch (144)
constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch (784)
-- constant hbp : std_logic_vector(9 downto 0) := "0010100000"; --Horizontal back porch (160)
-- constant hfp : std_logic_vector(9 downto 0) := "1100000000"; --Horizontal front porch (768)
constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch (31)
constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch (511)
signal hc, vc : std_logic_vector(10 downto 0) := (others=>'0'); --These are the Horizontal and Vertical counters
signal clkdiv : std_logic := '0'; --Clock divider
signal vidoff : std_logic; --Tells whether or not its ok to display data
signal currentLP : std_logic_vector(5 downto 0) := (others=>'0'); -- Vertical Pixel 0 to 19
signal currentCP : std_logic_vector(5 downto 0) := (others=>'0'); -- Horizontal Pixel 0 to 19
signal currentLine : std_logic_vector(10 downto 0) := (others=>'0'); -- Line 0 to 23
signal currentColumn : std_logic_vector(10 downto 0) := (others=>'0'); -- Column 0 to 31
-- Keyboard handling
signal keyboard_data_rdy : std_logic;
signal keyboard_busy : std_logic;
signal keyboard_error : std_logic;
type screenCharacters is array(lines,columns) of characterCode;
-- This function converts the ASCII screen layout into the internal version
function initScreen (constant screen : screenType) return screenCharacters is
variable sc : screenCharacters;
begin
for r in lines loop
for c in columns loop
sc(r,c) := charTranslate(character'pos(screen(r,c)));
end loop;
end loop;
return sc;
end function;
constant charLayout : screenCharacters := initScreen(screen);
begin
vgaController : entity work.vga_controller_640_60 port map (
rst => '0',
pixel_clk => clkdiv,
HS => HS,
VS => VS,
hcount => hc,
vcount => vc,
hchar => currentColumn,
vchar => currentLine,
hpixel => currentCP,
vpixel => currentLP,
blank => vidoff
);
--This cuts the 50Mhz clock in half
process(Clock50)
variable currentInd : IndicatorRange;
variable currentChar : characterCode;
variable pixRow : pixelRow;
variable pixPalette : paletteType;
variable pix : pixelType;
variable fgbg : paletteRange;
variable ind : sigRange;
begin
if(Clock50 = '1' and Clock50'EVENT) then
clkdiv <= not clkdiv;
currentInd := indLayout(lines(CONV_INTEGER(currentLine)),columns(CONV_INTEGER(currentColumn)));
currentChar := charLayout(lines(CONV_INTEGER(currentLine)),columns(CONV_INTEGER(currentColumn)));
if Indicators(currentInd)='1' then ind := 1; else ind := 0; end if;
pixRow := characterGenerator(characterRange(CONV_INTEGER(currentChar)),pixLinesRange(CONV_INTEGER(currentLP)));
if pixRow(pixColsRange(CONV_INTEGER(currentCP)))='1' then fgbg := 1; else fgbg := 0; end if;
pixPalette := characterPalette(characterRange(characterRange(CONV_INTEGER(currentChar))));
pix := pixPalette(ind,fgbg);
Red <= pix(1) and not vidoff;
Green <= pix(2) and not vidoff;
Blue <= pix(3) and not vidoff;
end if;
end process;
END behavioural;
| gpl-3.0 | 0e81e0230a422a9198bd304c571886c1 | 0.667708 | 5.116564 | false | false | false | false |
chastell/art-decomp | kiss/s820_hot.vhd | 1 | 29,832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s820_hot is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s820_hot;
architecture behaviour of s820_hot is
constant s00000: std_logic_vector(24 downto 0) := "1000000000000000000000000";
constant s01110: std_logic_vector(24 downto 0) := "0100000000000000000000000";
constant s10000: std_logic_vector(24 downto 0) := "0010000000000000000000000";
constant s10001: std_logic_vector(24 downto 0) := "0001000000000000000000000";
constant s01111: std_logic_vector(24 downto 0) := "0000100000000000000000000";
constant s00010: std_logic_vector(24 downto 0) := "0000010000000000000000000";
constant s00001: std_logic_vector(24 downto 0) := "0000001000000000000000000";
constant s00100: std_logic_vector(24 downto 0) := "0000000100000000000000000";
constant s00011: std_logic_vector(24 downto 0) := "0000000010000000000000000";
constant s00101: std_logic_vector(24 downto 0) := "0000000001000000000000000";
constant s00110: std_logic_vector(24 downto 0) := "0000000000100000000000000";
constant s11111: std_logic_vector(24 downto 0) := "0000000000010000000000000";
constant s10111: std_logic_vector(24 downto 0) := "0000000000001000000000000";
constant s01011: std_logic_vector(24 downto 0) := "0000000000000100000000000";
constant s00111: std_logic_vector(24 downto 0) := "0000000000000010000000000";
constant s11000: std_logic_vector(24 downto 0) := "0000000000000001000000000";
constant s11011: std_logic_vector(24 downto 0) := "0000000000000000100000000";
constant s11001: std_logic_vector(24 downto 0) := "0000000000000000010000000";
constant s11010: std_logic_vector(24 downto 0) := "0000000000000000001000000";
constant s11100: std_logic_vector(24 downto 0) := "0000000000000000000100000";
constant s01100: std_logic_vector(24 downto 0) := "0000000000000000000010000";
constant s01101: std_logic_vector(24 downto 0) := "0000000000000000000001000";
constant s01000: std_logic_vector(24 downto 0) := "0000000000000000000000100";
constant s01001: std_logic_vector(24 downto 0) := "0000000000000000000000010";
constant s01010: std_logic_vector(24 downto 0) := "0000000000000000000000001";
signal current_state, next_state: std_logic_vector(24 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------------"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000000000000110000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------00") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-1--------------00") then next_state <= s10000; output <= "0000000000000110000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000100001";
elsif std_match(input, "-1--------------10") then next_state <= s10000; output <= "0000000000000110000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000010000000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000010000000000000";
end if;
when s01111 =>
if std_match(input, "----------------11") then next_state <= s00000; output <= "0000000100000100000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000100000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000100000100000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000000000110000000";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000000000111000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000000000010000000";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000000000110000000";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000000000111000000";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000000000010000000";
end if;
when s00100 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------10") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-11-1-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1011-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0-1--0-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1--------010") then next_state <= s00100; output <= "0000000000000001000";
end if;
when s00001 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----1----111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----1-1--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----1-----0-1--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----011--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----0-0--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------1----10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------1---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0------1----00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1------1----00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1------0-----0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------0---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0------0---000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0------01--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----001--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----000--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----000--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----0-----100--100") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11111 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000000000001000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11000 =>
if std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "1000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000000000001000";
end if;
when s11001 =>
if std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "0100000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000000000001000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11010 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11011 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-0---------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----001") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1111-----011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----1-1") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-0--------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-0--------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-110------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1110-----110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000000000001010";
elsif std_match(input, "----0-11-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11100 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01100 =>
if std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0010100000000000000";
elsif std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0010100000000000000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0001100000000000000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0001100000000000000";
end if;
when s01101 =>
if std_match(input, "-1---------------0") then next_state <= s10000; output <= "0000001010000010000";
elsif std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000001010000010000";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0000001010000000000";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0000001010000000000";
elsif std_match(input, "-0-0-------------1") then next_state <= s00000; output <= "0000001010000000000";
elsif std_match(input, "-0-1--------------") then next_state <= s00000; output <= "0000001010000000000";
end if;
when s10000 =>
if std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
elsif std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s01011 =>
if std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
end if;
when s00111 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01000 =>
if std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "1000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s01001 =>
if std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "0100000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01010 =>
if std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
end if;
when s00011 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
end if;
when others => next_state <= "-------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 8cd52f6d7f3617ada408d7fbf31966eb | 0.588663 | 4.225496 | false | false | false | false |
chastell/art-decomp | kiss/bbsse_rnd.vhd | 1 | 6,983 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_rnd;
architecture behaviour of bbsse_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st11: std_logic_vector(3 downto 0) := "1011";
constant st4: std_logic_vector(3 downto 0) := "1110";
constant st2: std_logic_vector(3 downto 0) := "1111";
constant st3: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "0110";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st7: std_logic_vector(3 downto 0) := "1010";
constant st8: std_logic_vector(3 downto 0) := "1000";
constant st9: std_logic_vector(3 downto 0) := "0100";
constant st10: std_logic_vector(3 downto 0) := "1001";
constant st12: std_logic_vector(3 downto 0) := "1100";
constant st13: std_logic_vector(3 downto 0) := "0011";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "0------") then next_state <= st0; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010";
end if;
when st1 =>
if std_match(input, "100----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st2 =>
if std_match(input, "10-----") then next_state <= st3; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st4 =>
if std_match(input, "10-----") then next_state <= st5; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10---0-") then next_state <= st6; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st8; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10---0-") then next_state <= st8; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st10 =>
if std_match(input, "1001---") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st11 =>
if std_match(input, "0----0-") then next_state <= st11; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0";
end if;
when st12 =>
if std_match(input, "11-----") then next_state <= st12; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | a84d4363c0fa05539655e2f680d9560d | 0.561363 | 3.323655 | false | false | false | false |
chastell/art-decomp | kiss/ex2_rnd.vhd | 1 | 7,775 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_rnd;
architecture behaviour of ex2_rnd is
constant s1: std_logic_vector(4 downto 0) := "11101";
constant s2: std_logic_vector(4 downto 0) := "00010";
constant s4: std_logic_vector(4 downto 0) := "11011";
constant s0: std_logic_vector(4 downto 0) := "11110";
constant s3: std_logic_vector(4 downto 0) := "11111";
constant s6: std_logic_vector(4 downto 0) := "10001";
constant s9: std_logic_vector(4 downto 0) := "10110";
constant s7: std_logic_vector(4 downto 0) := "01011";
constant s8: std_logic_vector(4 downto 0) := "01111";
constant s5: std_logic_vector(4 downto 0) := "00001";
constant s10: std_logic_vector(4 downto 0) := "10000";
constant s11: std_logic_vector(4 downto 0) := "11010";
constant s13: std_logic_vector(4 downto 0) := "11000";
constant s12: std_logic_vector(4 downto 0) := "01000";
constant s15: std_logic_vector(4 downto 0) := "00100";
constant s18: std_logic_vector(4 downto 0) := "01001";
constant s16: std_logic_vector(4 downto 0) := "00110";
constant s17: std_logic_vector(4 downto 0) := "11100";
constant s14: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | b8d904fd0b042d79e8e0984953ae4a3c | 0.552154 | 3.338343 | false | false | false | false |
thommyj/slotcar | de0/pll.vhd | 1 | 15,099 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit | beb7a234dd4fbab19b30f0eb9bc8e9dd | 0.698391 | 3.353843 | false | false | false | false |
chastell/art-decomp | kiss/s208_nov.vhd | 1 | 16,541 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s208_nov is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s208_nov;
architecture behaviour of s208_nov is
constant s11111111: std_logic_vector(4 downto 0) := "11111";
constant s00000000: std_logic_vector(4 downto 0) := "00000";
constant s00010000: std_logic_vector(4 downto 0) := "00011";
constant s00100000: std_logic_vector(4 downto 0) := "00010";
constant s00110000: std_logic_vector(4 downto 0) := "00101";
constant s01000000: std_logic_vector(4 downto 0) := "00100";
constant s01010000: std_logic_vector(4 downto 0) := "00111";
constant s01100000: std_logic_vector(4 downto 0) := "00110";
constant s01110000: std_logic_vector(4 downto 0) := "01001";
constant s10000000: std_logic_vector(4 downto 0) := "01000";
constant s10010000: std_logic_vector(4 downto 0) := "01011";
constant s10100000: std_logic_vector(4 downto 0) := "01010";
constant s10110000: std_logic_vector(4 downto 0) := "01101";
constant s11000000: std_logic_vector(4 downto 0) := "01100";
constant s11010000: std_logic_vector(4 downto 0) := "01111";
constant s11100000: std_logic_vector(4 downto 0) := "01110";
constant s11110000: std_logic_vector(4 downto 0) := "10111";
constant s00000001: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s11111111 =>
if std_match(input, "0--------01") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------01") then next_state <= s00000000; output <= "11";
elsif std_match(input, "0--------11") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------11") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------10") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------00") then next_state <= s00000000; output <= "10";
elsif std_match(input, "0---------0") then next_state <= s00000000; output <= "10";
end if;
when s00000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10--------0") then next_state <= s00010000; output <= "00";
end if;
when s00010000 =>
if std_match(input, "10-------00") then next_state <= s00100000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s00100000; output <= "01";
elsif std_match(input, "10-------1-") then next_state <= s00100000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
end if;
when s00100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s00110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s00110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s00110000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s00110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s01000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01000000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s01000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-----1--0") then next_state <= s01010000; output <= "01";
elsif std_match(input, "10-----0--0") then next_state <= s01010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01010000; output <= "01";
end if;
when s01010000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s01100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01100000; output <= "01";
end if;
when s01100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1-0") then next_state <= s01110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s01110000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01110000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s01110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s10000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10----0---0") then next_state <= s10010000; output <= "00";
elsif std_match(input, "10----1---0") then next_state <= s10010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s10010000; output <= "01";
elsif std_match(input, "11----1---0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11----0---0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s10010000 =>
if std_match(input, "10--------1") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10100000; output <= "00";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s10100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s10110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s10110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s10110000; output <= "01";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when s10110000 =>
if std_match(input, "10--------1") then next_state <= s11000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11000000; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s11000000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s11000000 =>
if std_match(input, "10-----0--0") then next_state <= s11010000; output <= "00";
elsif std_match(input, "10-----1--0") then next_state <= s11010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s11010000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s11010000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s11100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s11100000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01--------1") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s11100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10------1--") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-1") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s11110000; output <= "00";
end if;
when s11110000 =>
if std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------01") then next_state <= s00000001; output <= "00";
elsif std_match(input, "-0-------00") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------11") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------11") then next_state <= s00000001; output <= "00";
elsif std_match(input, "00-------10") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s00000001; output <= "01";
end if;
when s00000001 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10---1----0") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10---0----0") then next_state <= s00010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "11---0----0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11---1----0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 103b281fda858aff15b4efe4d43d2ccf | 0.565625 | 3.517865 | false | false | false | false |
TheMassController/VHDL_experimenting | project/complete_system/two_brams.vhd | 1 | 2,749 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity two_brams is
Port (
clk_50mhz : in STD_LOGIC;
usb_db : inout std_logic_vector(7 downto 0);
usb_write : in std_logic;
usb_astb : in std_logic;
usb_dstb : in std_logic;
usb_wait : out std_logic
);
end two_brams;
architecture Behavioral of two_brams is
constant address_map : addr_range_and_mapping_array := (
address_range_and_map(
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(2047, bus_address_type'length)),
mapping => bus_map_constant(bus_address_type'high - 10, '0') & bus_map_range(10, 0)
),
address_range_and_map(
low => std_logic_vector(to_unsigned(2048, bus_address_type'length)),
high => std_logic_vector(to_unsigned(4095, bus_address_type'length)),
mapping => bus_map_constant(bus_address_type'high - 10, '0') & bus_map_range(10, 0)
));
signal rst : STD_LOGIC := '0';
signal depp2demux : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal demux2depp : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2bramA : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal bramA2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2bramB : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal bramB2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
depp_slave_controller : entity work.depp_slave_controller
port map (
rst => rst,
clk => clk_50mhz,
mst2slv => depp2demux,
slv2mst => demux2depp,
USB_DB => usb_db,
USB_WRITE => usb_write,
USB_ASTB => usb_astb,
USB_DSTB => usb_dstb,
USB_WAIT => usb_wait
);
demux : entity work.bus_demux
generic map (
ADDRESS_MAP => address_map
)
port map (
rst => rst,
mst2demux => depp2demux,
demux2mst => demux2depp,
demux2slv(0) => demux2bramA,
demux2slv(1) => demux2bramB,
slv2demux(0) => bramA2demux,
slv2demux(1) => bramB2demux
);
bramA : entity work.bus_singleport_ram
generic map (
DEPTH_LOG2B => 11
)
port map (
rst => rst,
clk => clk_50mhz,
mst2mem => demux2bramA,
mem2mst => bramA2demux
);
bramB : entity work.bus_singleport_ram
generic map (
DEPTH_LOG2B => 11
)
port map (
rst => rst,
clk => clk_50mhz,
mst2mem => demux2bramB,
mem2mst => bramB2demux
);
end Behavioral;
| mit | 926d78430d5b7a2a2ebe4fa71e030e4a | 0.563841 | 3.352439 | false | false | false | false |
chastell/art-decomp | kiss/tav_hot.vhd | 1 | 4,980 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tav_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end tav_hot;
architecture behaviour of tav_hot is
constant st0: std_logic_vector(3 downto 0) := "1000";
constant st1: std_logic_vector(3 downto 0) := "0100";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st3: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "1000") then next_state <= st1; output <= "1000";
elsif std_match(input, "0100") then next_state <= st1; output <= "0100";
elsif std_match(input, "0010") then next_state <= st1; output <= "0010";
elsif std_match(input, "0001") then next_state <= st1; output <= "0001";
elsif std_match(input, "0000") then next_state <= st1; output <= "0000";
elsif std_match(input, "11--") then next_state <= st1; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st1; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st1; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st1; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st1; output <= "0000";
elsif std_match(input, "--11") then next_state <= st1; output <= "0000";
end if;
when st1 =>
if std_match(input, "1000") then next_state <= st2; output <= "1000";
elsif std_match(input, "0100") then next_state <= st2; output <= "0100";
elsif std_match(input, "0010") then next_state <= st2; output <= "0010";
elsif std_match(input, "0001") then next_state <= st2; output <= "0001";
elsif std_match(input, "1100") then next_state <= st2; output <= "1100";
elsif std_match(input, "1010") then next_state <= st2; output <= "1010";
elsif std_match(input, "1001") then next_state <= st2; output <= "1001";
elsif std_match(input, "0110") then next_state <= st2; output <= "0000";
elsif std_match(input, "0000") then next_state <= st2; output <= "0000";
elsif std_match(input, "0011") then next_state <= st2; output <= "0011";
elsif std_match(input, "0101") then next_state <= st2; output <= "0101";
elsif std_match(input, "0111") then next_state <= st2; output <= "0001";
elsif std_match(input, "1011") then next_state <= st2; output <= "1011";
elsif std_match(input, "1101") then next_state <= st2; output <= "1101";
elsif std_match(input, "1110") then next_state <= st2; output <= "1000";
elsif std_match(input, "1111") then next_state <= st2; output <= "1001";
end if;
when st2 =>
if std_match(input, "1000") then next_state <= st3; output <= "1000";
elsif std_match(input, "0100") then next_state <= st3; output <= "0100";
elsif std_match(input, "0010") then next_state <= st3; output <= "0010";
elsif std_match(input, "0001") then next_state <= st3; output <= "0001";
elsif std_match(input, "0000") then next_state <= st3; output <= "0000";
elsif std_match(input, "11--") then next_state <= st3; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st3; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st3; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st3; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st3; output <= "0000";
elsif std_match(input, "--11") then next_state <= st3; output <= "0000";
end if;
when st3 =>
if std_match(input, "1000") then next_state <= st0; output <= "1000";
elsif std_match(input, "0100") then next_state <= st0; output <= "0100";
elsif std_match(input, "0010") then next_state <= st0; output <= "0010";
elsif std_match(input, "0001") then next_state <= st0; output <= "0001";
elsif std_match(input, "0000") then next_state <= st0; output <= "0000";
elsif std_match(input, "11--") then next_state <= st0; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st0; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st0; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st0; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st0; output <= "0000";
elsif std_match(input, "--11") then next_state <= st0; output <= "0000";
end if;
when others => next_state <= "----"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | 0ae197cb97b7e20a3535280c4140d447 | 0.588353 | 3.322215 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/Rcon.vhd | 2 | 1,953 |
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity rcon is port (
next_value : in T_ENABLE; -- to be connected to next_rcon from controller
ctrl_dec : in T_ENCDEC;
reset, clock : in std_logic;
rcon_byte : out std_logic_vector (7 downto 0);
reset_key : in T_ENABLE;
last_key : in T_ENABLE);
end rcon;
architecture a_rcon of rcon is
signal rc_reg, s_next_rc, s_last_rcon : std_logic_vector( 7 downto 0 );
begin
SAVE_RCON_PROC : process( clock, reset )
begin
if ( reset=RESET_ACTIVE ) then
s_last_rcon <= "00000001";
elsif ( clock'event and clock='1' ) then
if (last_key = C_ENABLE) then
s_last_rcon <= rc_reg;
end if; -- nextval
end if;
end process SAVE_RCON_PROC;
process( clock, reset, reset_key, last_key )
begin
if ( reset=RESET_ACTIVE ) then
rc_reg <= "00000001";
elsif ( clock'event and clock='1' ) then
if ( next_value/=C_DISABLE ) then -- v. 1.2
rc_reg <= s_next_rc;
elsif ( reset_key = C_ENABLE ) then
rc_reg <= s_last_rcon;
end if; -- nextval
end if; -- reset, clock
end process;
idec : if ( C_INCLUDE_DECODING_LOGIC ) generate
s_next_rc <= ( rc_reg(6 downto 0) & '0' ) xor ( "000" & rc_reg(7) & rc_reg(7) & '0' & rc_reg(7) & rc_reg(7) )
when ( ctrl_dec = C_ENC )
else ( '0' & rc_reg(7 downto 1) ) xor ( rc_reg(0) & "000" & rc_reg(0) & rc_reg(0) & '0' & rc_reg(0) );
end generate; -- C_INCLUDE_DECODING_LOGIC
ienc : if ( not C_INCLUDE_DECODING_LOGIC ) generate
s_next_rc(7 downto 5) <= rc_reg(6 downto 4);
s_next_rc(4 downto 3) <= rc_reg(3 downto 2) xor ( rc_reg(7) & rc_reg(7) );
s_next_rc(2) <= rc_reg(1);
s_next_rc(1) <= rc_reg(0) xor rc_reg(7);
s_next_rc(0) <= rc_reg(7);
end generate; -- not C_INCLUDE_DECODING_LOGIC
rcon_byte <= rc_reg;
end a_rcon;
| mit | 7644af164bc462793b911f464566ec38 | 0.566308 | 2.897626 | false | false | false | false |
chastell/art-decomp | kiss/s386_hot.vhd | 1 | 7,880 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s386_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s386_hot;
architecture behaviour of s386_hot is
constant s000000: std_logic_vector(12 downto 0) := "1000000000000";
constant s001100: std_logic_vector(12 downto 0) := "0100000000000";
constant s010010: std_logic_vector(12 downto 0) := "0010000000000";
constant s010000: std_logic_vector(12 downto 0) := "0001000000000";
constant s001000: std_logic_vector(12 downto 0) := "0000100000000";
constant s000100: std_logic_vector(12 downto 0) := "0000010000000";
constant s000011: std_logic_vector(12 downto 0) := "0000001000000";
constant s010001: std_logic_vector(12 downto 0) := "0000000100000";
constant s010011: std_logic_vector(12 downto 0) := "0000000010000";
constant s110000: std_logic_vector(12 downto 0) := "0000000001000";
constant s100000: std_logic_vector(12 downto 0) := "0000000000100";
constant s000010: std_logic_vector(12 downto 0) := "0000000000010";
constant s000001: std_logic_vector(12 downto 0) := "0000000000001";
signal current_state, next_state: std_logic_vector(12 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "----11-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----100") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1-101") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0-101") then next_state <= s010000; output <= "0000001";
elsif std_match(input, "----0-0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----011") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----001") then next_state <= s000000; output <= "0000000";
end if;
when s001100 =>
if std_match(input, "-1---00") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---00") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
elsif std_match(input, "-0---10") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---10") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---11") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---11") then next_state <= s000100; output <= "0010000";
end if;
when s001000 =>
if std_match(input, "-----00") then next_state <= s001000; output <= "0000000";
elsif std_match(input, "0----01") then next_state <= s000000; output <= "0101100";
elsif std_match(input, "1----01") then next_state <= s000000; output <= "0101000";
elsif std_match(input, "0----11") then next_state <= s001100; output <= "0101100";
elsif std_match(input, "1----11") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "-----10") then next_state <= s001000; output <= "0000000";
end if;
when s000100 =>
if std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----10") then next_state <= s001100; output <= "0110000";
elsif std_match(input, "-----11") then next_state <= s000100; output <= "0010000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
end if;
when s010010 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000011; output <= "0000000";
end if;
when s000011 =>
if std_match(input, "--01-01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--00-01") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s010001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-1---01") then next_state <= s010011; output <= "0000010";
elsif std_match(input, "-0---01") then next_state <= s010001; output <= "0000010";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s010011 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s110000; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s110000 =>
if std_match(input, "-1---01") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "-0---01") then next_state <= s110000; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s100000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000010; output <= "0000000";
end if;
when s000010 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--10-00") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "--00-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1101") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "--10101") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--00101") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--10001") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--11001") then next_state <= s000010; output <= "0000000";
elsif std_match(input, "--00001") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--01001") then next_state <= s000010; output <= "0000000";
end if;
when s010000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000001; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
end if;
when s000001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0--01") then next_state <= s010000; output <= "0000001";
end if;
when others => next_state <= "-------------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 9c431475d5fbae7a6590448238e6d12f | 0.596701 | 3.668529 | false | false | false | false |
chastell/art-decomp | kiss/tbk_jed.vhd | 1 | 133,046 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_jed is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_jed;
architecture behaviour of tbk_jed is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st16: std_logic_vector(4 downto 0) := "00001";
constant st1: std_logic_vector(4 downto 0) := "01110";
constant st2: std_logic_vector(4 downto 0) := "01100";
constant st3: std_logic_vector(4 downto 0) := "11000";
constant st4: std_logic_vector(4 downto 0) := "11100";
constant st5: std_logic_vector(4 downto 0) := "10110";
constant st6: std_logic_vector(4 downto 0) := "10100";
constant st7: std_logic_vector(4 downto 0) := "00110";
constant st8: std_logic_vector(4 downto 0) := "11110";
constant st9: std_logic_vector(4 downto 0) := "01010";
constant st10: std_logic_vector(4 downto 0) := "10010";
constant st11: std_logic_vector(4 downto 0) := "00100";
constant st12: std_logic_vector(4 downto 0) := "11010";
constant st13: std_logic_vector(4 downto 0) := "00010";
constant st15: std_logic_vector(4 downto 0) := "10000";
constant st14: std_logic_vector(4 downto 0) := "01000";
constant st29: std_logic_vector(4 downto 0) := "00011";
constant st31: std_logic_vector(4 downto 0) := "10001";
constant st30: std_logic_vector(4 downto 0) := "01001";
constant st17: std_logic_vector(4 downto 0) := "01111";
constant st18: std_logic_vector(4 downto 0) := "01101";
constant st19: std_logic_vector(4 downto 0) := "11001";
constant st20: std_logic_vector(4 downto 0) := "11101";
constant st21: std_logic_vector(4 downto 0) := "10111";
constant st22: std_logic_vector(4 downto 0) := "10101";
constant st23: std_logic_vector(4 downto 0) := "00111";
constant st24: std_logic_vector(4 downto 0) := "11111";
constant st25: std_logic_vector(4 downto 0) := "01011";
constant st26: std_logic_vector(4 downto 0) := "10011";
constant st27: std_logic_vector(4 downto 0) := "00101";
constant st28: std_logic_vector(4 downto 0) := "11011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when st0 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st16 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st1 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st1; output <= "000";
elsif std_match(input, "000010") then next_state <= st1; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "010";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st17 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st17; output <= "000";
elsif std_match(input, "000010") then next_state <= st17; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "010";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st2 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st2; output <= "000";
elsif std_match(input, "000010") then next_state <= st2; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "010";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st18 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st18; output <= "000";
elsif std_match(input, "000010") then next_state <= st18; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "010";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st3 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st3; output <= "000";
elsif std_match(input, "000010") then next_state <= st3; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "010";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st19 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st19; output <= "000";
elsif std_match(input, "000010") then next_state <= st19; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "010";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st4 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st4; output <= "000";
elsif std_match(input, "000010") then next_state <= st4; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "010";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st20 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st20; output <= "000";
elsif std_match(input, "000010") then next_state <= st20; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "010";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st5 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st5; output <= "000";
elsif std_match(input, "000010") then next_state <= st5; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "010";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st21 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st21; output <= "000";
elsif std_match(input, "000010") then next_state <= st21; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "010";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st6 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st6; output <= "000";
elsif std_match(input, "000010") then next_state <= st6; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "010";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st22 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st22; output <= "000";
elsif std_match(input, "000010") then next_state <= st22; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "010";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st7 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st7; output <= "000";
elsif std_match(input, "000010") then next_state <= st7; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "010";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st23 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st23; output <= "000";
elsif std_match(input, "000010") then next_state <= st23; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "010";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st8 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st8; output <= "000";
elsif std_match(input, "000010") then next_state <= st8; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "010";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st24 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st24; output <= "000";
elsif std_match(input, "000010") then next_state <= st24; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "010";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st9 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st9; output <= "000";
elsif std_match(input, "000000") then next_state <= st9; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "010";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st25 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st25; output <= "000";
elsif std_match(input, "000000") then next_state <= st25; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "010";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st10 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st10; output <= "000";
elsif std_match(input, "000000") then next_state <= st10; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "010";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st26 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st26; output <= "000";
elsif std_match(input, "000000") then next_state <= st26; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "010";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st11 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st11; output <= "000";
elsif std_match(input, "000000") then next_state <= st11; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "010";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st27 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st27; output <= "000";
elsif std_match(input, "000000") then next_state <= st27; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "010";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st12 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st12; output <= "000";
elsif std_match(input, "000000") then next_state <= st12; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st28 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st28; output <= "000";
elsif std_match(input, "000000") then next_state <= st28; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st13 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st13; output <= "100";
elsif std_match(input, "000010") then next_state <= st13; output <= "100";
elsif std_match(input, "000000") then next_state <= st13; output <= "100";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st29 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st29; output <= "100";
elsif std_match(input, "000010") then next_state <= st29; output <= "100";
elsif std_match(input, "000000") then next_state <= st29; output <= "100";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st15 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st15; output <= "000";
elsif std_match(input, "000010") then next_state <= st15; output <= "000";
elsif std_match(input, "000000") then next_state <= st15; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st31 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st31; output <= "000";
elsif std_match(input, "000010") then next_state <= st31; output <= "000";
elsif std_match(input, "000000") then next_state <= st31; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st14 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st14; output <= "000";
elsif std_match(input, "000010") then next_state <= st14; output <= "000";
elsif std_match(input, "000000") then next_state <= st14; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st30 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st30; output <= "000";
elsif std_match(input, "000010") then next_state <= st30; output <= "000";
elsif std_match(input, "000000") then next_state <= st30; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 86593516be535e16f9bacba3dd8b8637 | 0.590811 | 3.336744 | false | false | false | false |
chastell/art-decomp | kiss/s832_nov.vhd | 1 | 30,735 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_nov is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_nov;
architecture behaviour of s832_nov is
constant s00000: std_logic_vector(4 downto 0) := "00000";
constant s10000: std_logic_vector(4 downto 0) := "00111";
constant s01110: std_logic_vector(4 downto 0) := "01011";
constant s01111: std_logic_vector(4 downto 0) := "01000";
constant s00010: std_logic_vector(4 downto 0) := "00110";
constant s00100: std_logic_vector(4 downto 0) := "10100";
constant s00101: std_logic_vector(4 downto 0) := "10011";
constant s00001: std_logic_vector(4 downto 0) := "11000";
constant s00110: std_logic_vector(4 downto 0) := "10010";
constant s11111: std_logic_vector(4 downto 0) := "01111";
constant s00111: std_logic_vector(4 downto 0) := "10001";
constant s01011: std_logic_vector(4 downto 0) := "10110";
constant s01100: std_logic_vector(4 downto 0) := "01001";
constant s01101: std_logic_vector(4 downto 0) := "00100";
constant s01000: std_logic_vector(4 downto 0) := "10000";
constant s01001: std_logic_vector(4 downto 0) := "11111";
constant s01010: std_logic_vector(4 downto 0) := "11110";
constant s10111: std_logic_vector(4 downto 0) := "11101";
constant s11000: std_logic_vector(4 downto 0) := "11100";
constant s11001: std_logic_vector(4 downto 0) := "11011";
constant s11010: std_logic_vector(4 downto 0) := "11010";
constant s11011: std_logic_vector(4 downto 0) := "10111";
constant s11100: std_logic_vector(4 downto 0) := "10101";
constant s00011: std_logic_vector(4 downto 0) := "11001";
constant s10001: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0001000000000010000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0001000000000010000";
elsif std_match(input, "-001------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-011------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000010000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000010001";
end if;
when s10000 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000001000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000000001000000000";
end if;
when s01111 =>
if std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000010000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000010000000010000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000010000000010000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000001000000000100";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000001000001000100";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000001000000000100";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000001000001000100";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000001000000000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000001000000000000";
end if;
when s00100 =>
if std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0-0001-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0--101-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0---11-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s00001 =>
if std_match(input, "------0--------0-1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------0--------000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------101") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------111") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10---------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-10--------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10--------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------110--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-110-------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------110-------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------111--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------1110-----010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1110-----110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----101--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0------11--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----1-----1------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----11---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----10---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1-----0------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----0----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----0----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0-----01---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---110") then next_state <= s01011; output <= "0000000100000000000";
end if;
when s11111 =>
if std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s00111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s01011 =>
if std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
end if;
when s01100 =>
if std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0000000010000100000";
elsif std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0000000010000100000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0000000000000101000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0000000000000101000";
end if;
when s01101 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0101000000000000010";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0101000000000000010";
elsif std_match(input, "-0---------------1") then next_state <= s00000; output <= "0100000000000000010";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0100000000000000010";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0100000000000000010";
elsif std_match(input, "-0-1-------------0") then next_state <= s00000; output <= "0100000000000000010";
end if;
when s01000 =>
if std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "0000000100100000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000100100000001";
end if;
when s01001 =>
if std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "1000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
end if;
when s01010 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s11000 =>
if std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
end if;
when s11001 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "1000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000100000000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11010 =>
if std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11011 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-0--------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----111") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1--0-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-0--1-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
end if;
when s11100 =>
if std_match(input, "----0------------1") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00011 =>
if std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000100000000000";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | ea2e1983575d63be9748b2cd4a58a6ae | 0.582723 | 4.181633 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_counter.vhd | 1 | 1,931 | -------------------------------------------------------------------------------
-- Title : Testbench for design "clkdiv"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_counter.vhd
-- Author : Martin Angermair
-- Company :
-- Created : 29.10.2017
-- Last update: 29.10.2017
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 29.10.2017 1.0 Martin Angermair init
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_counter is
end tb_counter;
architecture sim of tb_counter is
-- System clock 100MHz
constant system_clk : time := 1000 ms;
component counter
generic(N : integer := 24);
port (
clk_i : in std_logic;
reset_i : in std_logic;
q_o : out std_logic_vector(N-1 downto 0)
);
end component counter;
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal q_o : std_logic_vector(23 downto 0);
begin
-- Instantiate the design under test
i_counter : counter
generic map(N => 24)
port map (
clk_i => clk_i,
reset_i => reset_i,
q_o => q_o);
-- Generate clock
p_clk : process
begin
clk_i <= '0';
wait for system_clk / 2;
clk_i <= '1';
wait for system_clk / 2;
end process p_clk;
p_stimuli : process
begin
reset_i <= '1';
wait for 12 ns;
reset_i <= '0';
wait;
end process p_stimuli;
end sim; | mit | 6bfb157535bfa5882b29d83476debf16 | 0.413257 | 4.388636 | false | false | false | false |
es17m014/vhdl-counter | src/old/tb/tb_clkdiv.vhd | 1 | 1,928 | -------------------------------------------------------------------------------
-- Title : Testbench for design "clkdiv"
-- Project :
-------------------------------------------------------------------------------
-- File : tb_clkdiv.vhd
-- Author : Martin Angermair
-- Company :
-- Created : 29.10.2017
-- Last update: 29.10.2017
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 29.10.2017 1.0 Martin Angermair init
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_clkdiv is
end tb_clkdiv;
architecture sim of tb_clkdiv is
-- System clock 100MHz
constant system_clk : time := 10 ns;
component clkdiv
generic(N : integer := 8);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_o : out std_logic_vector(N-1 downto 0)
);
end component clkdiv;
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal clk_o : std_logic_vector(26 downto 0);
begin
-- Instantiate the design under test
i_clkdiv : clkdiv
generic map(N => 15)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_o => clk_o);
-- Generate clock
p_clk : process
begin
clk_i <= '0';
wait for system_clk / 2;
clk_i <= '1';
wait for system_clk / 2;
end process p_clk;
p_stimuli : process
begin
reset_i <= '1';
wait for 12 ns;
reset_i <= '0';
wait;
end process p_stimuli;
end sim; | mit | 61cc45936baa47db8858eb052d214892 | 0.412344 | 4.381818 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/Aff_Trans.vhd | 2 | 803 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans;
architecture a_aff_trans of aff_trans is
begin
-- Tranformation Process
b_out(0) <= not (a(0)) xor a(4) xor a(5) xor a(6) xor a(7);
b_out(1) <= not (a(5)) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(2) <= a(2) xor a(0) xor a(1) xor a(6) xor a(7);
b_out(3) <= a(7) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(4) <= a(4) xor a(0) xor a(1) xor a(2) xor a(3);
b_out(5) <= not (a(1)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(6) <= not (a(6)) xor a(2) xor a(3) xor a(4) xor a(5);
b_out(7) <= a(3) xor a(4) xor a(5) xor a(6) xor a(7);
end a_aff_trans;
| mit | d7312807bb6036978e22feb23aac85f5 | 0.56538 | 2.2 | false | false | false | false |
chastell/art-decomp | kiss/sse_nov.vhd | 1 | 6,957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_nov;
architecture behaviour of sse_nov is
constant st11: std_logic_vector(3 downto 0) := "1100";
constant st10: std_logic_vector(3 downto 0) := "0000";
constant st7: std_logic_vector(3 downto 0) := "0111";
constant st6: std_logic_vector(3 downto 0) := "0001";
constant st12: std_logic_vector(3 downto 0) := "0110";
constant st1: std_logic_vector(3 downto 0) := "0011";
constant st0: std_logic_vector(3 downto 0) := "0101";
constant st8: std_logic_vector(3 downto 0) := "0100";
constant st9: std_logic_vector(3 downto 0) := "1011";
constant st3: std_logic_vector(3 downto 0) := "1010";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st4: std_logic_vector(3 downto 0) := "1101";
constant st5: std_logic_vector(3 downto 0) := "1001";
constant st13: std_logic_vector(3 downto 0) := "1000";
constant st14: std_logic_vector(3 downto 0) := "1111";
constant st15: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | b9651027b72d5167efbe8077e975ed3d | 0.559724 | 3.31128 | false | false | false | false |
chastell/art-decomp | kiss/lion9_hot.vhd | 1 | 3,401 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion9_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion9_hot;
architecture behaviour of lion9_hot is
constant st0: std_logic_vector(8 downto 0) := "100000000";
constant st1: std_logic_vector(8 downto 0) := "010000000";
constant st2: std_logic_vector(8 downto 0) := "001000000";
constant st3: std_logic_vector(8 downto 0) := "000100000";
constant st4: std_logic_vector(8 downto 0) := "000010000";
constant st5: std_logic_vector(8 downto 0) := "000001000";
constant st6: std_logic_vector(8 downto 0) := "000000100";
constant st7: std_logic_vector(8 downto 0) := "000000010";
constant st8: std_logic_vector(8 downto 0) := "000000001";
signal current_state, next_state: std_logic_vector(8 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "00") then next_state <= st0; output <= "0";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
elsif std_match(input, "01") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
end if;
when st7 =>
if std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when others => next_state <= "---------"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | c1d7f97772b118e9f95cd479f3bf1f04 | 0.579241 | 3.245229 | false | false | false | false |
caiopo/battleship-vhdl | src/fsm.vhd | 1 | 4,851 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity fsm is
port (dif: in std_logic_vector(1 downto 0);
clock, init, fire, reset: in std_logic;
memaddr: in std_logic_vector(1 downto 0);
linha: in std_logic_vector(13 downto 0);
displaycont: out std_logic_vector(7 downto 0);
displayaddr: out std_logic_vector(1 downto 0);
displaylinha: out std_logic_vector(13 downto 0);
user, compara: out std_logic;
difout: out std_logic_vector(1 downto 0)
);
end fsm;
architecture behv of fsm is
component cronometro is
port (
clock_50: in std_logic;
dificuldade: in std_logic_vector(1 downto 0);
reset: in std_logic;
restante: out std_logic_vector(7 downto 0);
atual: out std_logic_vector(7 downto 0)
);
end component;
type states is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9);
signal EA, PE: states;
signal resetCont, contTerminou: std_logic;
signal tempo_restante: std_logic_vector(7 downto 0);
signal tempdifout: std_logic_vector(1 downto 0);
begin
difout <= tempdifout;
chrono: cronometro port map (clock, tempdifout, resetCont, tempo_restante, open);
P1: process(clock, reset)
begin
-- reset assincrono
if reset = '0' then
EA <= S0;
elsif rising_edge(clock) then
-- a cada ciclo de clock, o proximo estado (PE) se torna o estado atual (EA)
EA <= PE;
end if;
end process;
P2: process(clock, EA, init, fire)
begin
if rising_edge(clock) then
-- a cada ciclo de clock, levando em conta o estado atual, o proximo estado é determinado
case EA is
when S0 =>
-- zera todas as variaveis e espera pela dificuldade ser escolhida
tempdifout <= "00";
displaycont <= "00000000";
displayaddr <= "00";
displaylinha <= "00000000000000";
compara <= '0';
-- quando init for apertado, passa para S1
if init = '1' then
PE <= S0;
else
PE <= S1;
end if;
when S1 =>
-- passa a dificuldade escolhida nos switches 17 e 16 para a saida, impossibilitando mudanca na dificuldade no meio do jogo
tempdifout <= dif;
-- inicia o reset do contador
resetCont <= '1';
--espera o jogador soltar o init
if init = '1' then
PE <= S2;
else
PE <= S1;
end if;
when S2 =>
-- termina de resetar o contador
resetCont <= '0';
-- determina o jogador atual como jogador1
user <= '0';
-- passa as informacoes necessarias para os displays
displayaddr <= memaddr; -- endereco de memoria (switches 15 e 14)
displaylinha <= linha; -- linha de tiro (switches 13 downto 0)
displaycont <= tempo_restante; --(tempo restante)
-- se o tempo acabar, termina o turno sem atirar, se fire for apertado, contabiliza o tiro
if ("00000000" >= tempo_restante) then
PE <= S5;
elsif fire = '1' then
PE <= S2;
else
PE <= S3;
end if;
when S3 =>
-- espera soltar o fire
if fire = '1' then
PE <= S4;
else
PE <= S3;
end if;
when S4 =>
-- ativa o enable do comparador e do contador de pontos
compara <= '1';
PE <= S5;
when S5 =>
-- reseta os displays e o enable do comparador/contador de pontos
displaycont <= "00000000";
displayaddr <= "00";
displaylinha <= "00000000000000";
compara <= '0';
-- inicia o reset do contador
resetCont <= '1';
PE <= S6;
when S6 =>
-- termina de resetar o contador
resetCont <= '0';
-- determina o jogador atual como jogador2
user <= '1';
-- passa as informacoes necessarias para os displays
displayaddr <= memaddr;
displaylinha <= linha;
displaycont <= tempo_restante;
-- se o tempo acabar, termina o turno sem atirar, se fire for apertado, contabiliza o tiro
if ("00000000" >= tempo_restante) then
PE <= S9;
elsif fire = '1' then
PE <= S6;
else
PE <= S7;
end if;
when S7 =>
-- espera soltar o fire
if fire = '1' then
PE <= S8;
else
PE <= S7;
end if;
when S8 =>
-- ativa o enable do comparador e do contador de pontos
compara <= '1';
PE <= S9;
when S9 =>
-- reseta os displays e o enable do comparador/contador de pontos
displaycont <= "00000000";
displayaddr <= "00";
displaylinha <= "00000000000000";
compara <= '0';
-- inicia o reset do contador
resetCont <= '1';
PE <= S2;
end case;
end if;
end process;
end behv; | mit | 0bc0c64416b28692a2fc22e581704f97 | 0.561031 | 3.429986 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-10A.vhd | 1 | 6,107 | ---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-10A.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console clock control and generation
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
Library UNISIM;
use UNISIM.vcomponents.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.FLL;
ENTITY n1050_CLOCK IS
port
(
-- Inputs
WRITE_LCH : IN STD_LOGIC; -- 09CD2
READ_OR_READ_INQ : IN STD_LOGIC; -- 09CC5
RST_ATTACH : IN STD_LOGIC; -- 10BC2
PUNCH_1_CLUTCH : IN STD_LOGIC; -- 10DD5
READ_CLK_INTLK_LCH : IN STD_LOGIC; -- 10BA2
RDR_1_CLUTCH : IN STD_LOGIC; -- 10DD5
CRLF : IN STD_LOGIC; -- ?
-- Outputs
CLOCK_1 : OUT STD_LOGIC; -- 10CD1 10CA4
W_TIME, X_TIME, Y_TIME, Z_TIME : OUT STD_LOGIC;
CLK_STT_RST : OUT STD_LOGIC; -- 09CE1
-- Temp
-- POSTRIG, NEGTRIG : OUT STD_LOGIC;
-- OSCOut,C1,C2 : OUT STD_LOGIC;
-- OSCOut,C1,C2 : OUT STD_LOGIC;
-- Clocks
clk : IN STD_LOGIC -- 50MHz clock
);
END n1050_CLOCK;
ARCHITECTURE FMD OF n1050_CLOCK IS
-- Output rate is 9600bps or 960chars/sec or 1.04ms/char. We set the clock to run at 1.2ms/4 or 300us (300 * 50 = 15000 cycles)
-- constant ClockDivider : integer := 15000;
constant ClockDivider : integer := 250; -- Gives 5us OSC rate
signal OSC : STD_LOGIC; -- Inverted signal
signal CLK_START : STD_LOGIC;
signal TRIGER : STD_LOGIC;
signal nTRIG : STD_LOGIC;
signal BIN_CNTR : STD_LOGIC_VECTOR(1 to 2);
signal Counter : integer;
signal sCLK_STT_RST : STD_LOGIC;
signal CLK_START_SET, CLK_START_RESET : STD_LOGIC;
signal W_SET, X_SET, Y_SET, Z_SET : STD_LOGIC;
signal W_RESET, X_RESET, Y_RESET, Z_RESET : STD_LOGIC;
signal sW_TIME, sX_TIME, sY_TIME, sZ_TIME : STD_LOGIC;
BEGIN
-- Fig 5-10A
sCLK_STT_RST <= OSC and not BIN_CNTR(1) and sZ_TIME and not sW_TIME; -- AC2H4
CLK_STT_RST <= sCLK_STT_RST;
CLK_START_SET <= (PUNCH_1_CLUTCH and not READ_CLK_INTLK_LCH and READ_OR_READ_INQ)
or (RDR_1_CLUTCH and WRITE_LCH and not CRLF);
CLK_START_RESET <= RST_ATTACH or sCLK_STT_RST;
CLK_START_FL : entity FLL port map(CLK_START_SET,CLK_START_RESET,CLK_START); -- AC2G6 AC2F6
BIN_CNTR_P: process(OSC,RST_ATTACH) is
begin
if RST_ATTACH='1' then
BIN_CNTR <= "01";
else if rising_edge(OSC) then
BIN_CNTR <= BIN_CNTR + "01";
end if;
end if;
end process;
OSC_P : process(CLK_START,clk) is
begin
if falling_edge(clk) then
if (CLK_START='0') then
OSC <= '1';
Counter <= 0;
else
Counter <= Counter + 1;
if Counter=ClockDivider then
Counter <= 0;
end if;
if (Counter > (ClockDivider/2)) then
OSC <= '1';
else
OSC <= '0';
end if;
end if;
end if;
end process;
TRIGER <= (not BIN_CNTR(1) and WRITE_LCH) or (READ_OR_READ_INQ and BIN_CNTR(2)); -- AC2G7
nTRIG <= (not BIN_CNTR(2) and not WRITE_LCH) or (BIN_CNTR(1) and WRITE_LCH); -- AC2F7 AC2M2
-- POSTRIG <= TRIGER;
-- NEGTRIG <= nTRIG;
-- OSCOut <= OSC;
-- C1 <= BIN_CNTR(1);
-- C2 <= BIN_CNTR(2);
W_SET <= not sY_TIME and sZ_TIME and (TRIGER and CLK_START); -- AC2E7 AC2F6 ?? 'not' gate ignored
X_SET <= not sZ_TIME and sW_TIME and nTRIG;
Y_SET <= not sW_TIME and sX_TIME and TRIGER; -- AC2G2
Z_SET <= (not sX_TIME and sY_TIME and nTRIG) or RST_ATTACH or (OSC and not CLK_START); -- AC2E7 ?? RST_ATTACH or (OSC and not CLK_START) ??
W_RESET <= (sX_TIME and TRIGER) or RST_ATTACH; -- AC2D7
X_RESET <= (sY_TIME and nTRIG) or RST_ATTACH; -- AC2G3
Y_RESET <= (sZ_TIME and TRIGER) or RST_ATTACH or (OSC and not CLK_START); -- AC2F7
Z_RESET <= (sW_TIME and nTRIG); -- AC2G3
W_JK: FDRSE port map(C=>clk,Q=>sW_TIME,R=>W_RESET,S=>W_SET,CE=>'0',D=>'0');
-- W_FL : FLL port map(W_SET,W_RESET,sW_TIME); -- AC2G2
W_TIME <= sW_TIME;
X_JK: FDRSE port map(C=>clk,Q=>sX_TIME,R=>X_RESET,S=>X_SET,CE=>'0',D=>'0');
-- X_FL : FLL port map(X_SET,X_RESET,sX_TIME); -- AC2G2
X_TIME <= sX_TIME;
Y_JK: FDRSE port map(C=>clk,Q=>sY_TIME,R=>Y_RESET,S=>Y_SET,CE=>'0',D=>'0');
-- Y_FL : FLL port map(Y_SET,Y_RESET,sY_TIME); -- AC2G2
Y_TIME <= sY_TIME;
Z_JK: FDRSE port map(C=>clk,Q=>sZ_TIME,R=>Z_RESET,S=>Z_SET,CE=>'0',D=>'0');
-- Z_FL : FLL port map(Z_SET,Z_RESET,sZ_TIME); -- AC2F5
Z_TIME <= sZ_TIME;
CLOCK1_FL : entity FLL port map(W_SET,X_RESET,CLOCK_1); -- ?? CLOCK_1 isn't defined in the diagrams
-- This is a guess at CLOCK_1 being W_TIME OR X_TIME, but can't do that directly without possible glitches
END FMD;
| gpl-3.0 | d75425fd7e605ca05102f21eb7ee4979 | 0.607991 | 2.796245 | false | false | false | false |
TheMassController/VHDL_experimenting | project/common/simple_multishot_timer.vhd | 1 | 1,241 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simple_multishot_timer is
generic (
match_val : natural range 1 to natural'high
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC
);
end simple_multishot_timer;
architecture behavioral of simple_multishot_timer is
function check_timer_match(X : UNSIGNED; Y: natural) return boolean is
begin
return to_integer(X) = Y;
end check_timer_match;
constant count_bits_count : integer := (integer(ceil(log2(real(match_val)))));
signal timer_value : UNSIGNED(count_bits_count DOWNTO 0) := (others => '0');
begin
process (clk, rst)
begin
if (rst = '1') then
timer_value <= to_unsigned(0, timer_value'length);
done <= '0';
elsif rising_edge(clk) then
if check_timer_match(timer_value, match_val) then
done <= '1';
timer_value <= to_unsigned(1, timer_value'length);
else
timer_value <= timer_value + 1;
done <= '0';
end if;
end if;
end process;
end behavioral;
| mit | 3052b1d484c13fbbc39e868ae1e4de9f | 0.56245 | 3.795107 | false | false | false | false |
chastell/art-decomp | kiss/s1a_jed.vhd | 1 | 11,806 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1a_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1a_jed;
architecture behaviour of s1a_jed is
constant st0: std_logic_vector(4 downto 0) := "11100";
constant st1: std_logic_vector(4 downto 0) := "11101";
constant st2: std_logic_vector(4 downto 0) := "11000";
constant st5: std_logic_vector(4 downto 0) := "01000";
constant st3: std_logic_vector(4 downto 0) := "11001";
constant st4: std_logic_vector(4 downto 0) := "11110";
constant st6: std_logic_vector(4 downto 0) := "10111";
constant st7: std_logic_vector(4 downto 0) := "00001";
constant st12: std_logic_vector(4 downto 0) := "01101";
constant st13: std_logic_vector(4 downto 0) := "01100";
constant st8: std_logic_vector(4 downto 0) := "10100";
constant st11: std_logic_vector(4 downto 0) := "00000";
constant st15: std_logic_vector(4 downto 0) := "10110";
constant st9: std_logic_vector(4 downto 0) := "10000";
constant st10: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10101";
constant st16: std_logic_vector(4 downto 0) := "10011";
constant st17: std_logic_vector(4 downto 0) := "00100";
constant st18: std_logic_vector(4 downto 0) := "10010";
constant st19: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "000000";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "000000";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "000000";
elsif std_match(input, "----1---") then next_state <= st3; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "000000";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "000000";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "000000";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "000000";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "000000";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "000000";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "000000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000000";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000000";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "000000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "000000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "000000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "000000";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "000000";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "------1-") then next_state <= st7; output <= "000000";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "000000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "000000";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "000000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000000";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "000000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 71f4e0f6faf7cc5d702921f3c04cf523 | 0.565136 | 3.298687 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/KeyUnit_ddr.vhd | 2 | 4,234 | ------------------------------------------------------
-- next_key(127 downto 96) = Subword(RotWord(prev_key(32 downto 0)) XOR rcon
-- next_key(95 downto 64) = prev_key(95 downto 64) XOR next_key(127 downto 96)
-- next_key(63 downto 32) = prev_key(63 downto 32) XOR next_key(95 downto 64)
-- next_key(31 downto 0) = prev_key(31 downto 0) XOR next_key(63 downto 32)
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity keyunit is port (
key_in : in std_logic_vector (127 downto 0);
in_ready : in T_READY;
load_key : in std_logic;
advance_key : in T_ENABLE; -- store the next round key
reset_key : in T_ENABLE; -- rewind the first round key
save_key : in T_ENABLE; -- checkpoint: saved key for later rewind
ctrl_dec : in T_ENCDEC;
next_rcon : in T_ENABLE; -- next_step for RCon constant
reset, clk : in std_logic;
data_to_sbox : out std_logic_vector (31 downto 0); -- data to DU's Sboxes
data_from_sbox: in std_logic_vector (31 downto 0); --- data from DU's Sboxes
key_out : out std_logic_vector (127 downto 0) ); -- ROUND KEY
end keyunit;
architecture a_keyunit of keyunit is
component rcon port (
next_value : in T_ENABLE;
ctrl_dec : in T_ENCDEC;
reset, clock : in std_logic;
rcon_byte : out std_logic_vector (7 downto 0);
reset_key: in T_ENABLE ;
last_key : in T_ENABLE);
end component;
signal regs_out, next_key, s_1st_round_key : std_logic_vector( 127 downto 0 );
signal rcon_in, rcon_out : std_logic_vector( 31 downto 0 );
signal RCon_byte : std_logic_vector( 7 downto 0 );
begin
key_out <= regs_out;
rcon_in <= data_from_sbox; -- data coming from the SBoxes in the DataUnit
RCon_inst : RCon port map ( next_RCon, ctrl_dec, reset, clk, RCon_byte, reset_key, save_key );
rcon_out <= rcon_in xor ( RCon_byte & X"000000");
next_key( 127 downto 96 ) <= regs_out( 127 downto 96 ) xor rcon_out;
save_key_proc : process( reset, clk )
begin
if ( reset=RESET_ACTIVE ) then
s_1st_round_key <= ( others=>'0');
elsif ( clk'event and clk='1' ) then
if ( save_key=C_ENABLE ) then
s_1st_round_key <= regs_out;
end if; -- save_key
end if; -- reset, clock
end process save_key_proc;
key_reg_pr : process( reset, clk )
begin
if ( reset=RESET_ACTIVE ) then
regs_out <= ( others=>'0' );
elsif ( clk'event and clk='1' ) then -- not reset, hence if clock
if ( advance_key/=C_DISABLE ) then
regs_out <= next_key;
elsif ( in_ready=C_READY ) then -- device ready for loading
if ( load_key='1' ) then -- valid key
regs_out <= key_in;
end if; -- load_key
-- device busy computing
elsif ( reset_key=C_ENABLE ) then -- rewinding key
regs_out <= s_1st_round_key;
end if; -- in_ready, reset_key, advance_key
end if; -- reset, clock
end process;
g002e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
data_to_sbox <= ( regs_out( 23 downto 0 ) & regs_out( 31 downto 24 ) );
next_key( 95 downto 64 ) <= regs_out( 95 downto 64 ) xor next_key( 127 downto 96 );
next_key( 63 downto 32 ) <= regs_out( 63 downto 32 ) xor next_key( 95 downto 64 );
next_key( 31 downto 0 ) <= regs_out( 31 downto 0 ) xor next_key( 63 downto 32 );
end generate; -- not C_INCLUDE_DECODING_LOGIC
g002d : if ( C_INCLUDE_DECODING_LOGIC ) generate
data_to_sbox <= ( regs_out( 23 downto 0 ) & regs_out( 31 downto 24 ) ) when ( ctrl_dec = C_ENC )
else ( next_key( 23 downto 0 ) & next_key( 31 downto 24 ) );
next_key( 95 downto 64 ) <= ( regs_out( 95 downto 64 ) xor next_key( 127 downto 96 ) ) when ( ctrl_dec=C_ENC )
else ( regs_out( 95 downto 64 ) xor regs_out( 127 downto 96 ) );
next_key( 63 downto 32 ) <= ( regs_out( 63 downto 32 ) xor next_key( 95 downto 64 ) ) when ( ctrl_dec=C_ENC )
else ( regs_out( 63 downto 32 ) xor regs_out( 95 downto 64 ) );
next_key( 31 downto 0 ) <= ( regs_out( 31 downto 0 ) xor next_key( 63 downto 32 ) ) when ( ctrl_dec=C_ENC )
else ( regs_out( 31 downto 0 ) xor regs_out( 63 downto 32 ) );
end generate; -- C_INCLUDE_DECODING_LOGIC
end a_keyunit;
| mit | 756aaf2f36a133340135a4a2497cc7e5 | 0.607227 | 3.143281 | false | false | false | false |
chastell/art-decomp | kiss/s1a_nov.vhd | 1 | 11,806 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1a_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1a_nov;
architecture behaviour of s1a_nov is
constant st0: std_logic_vector(4 downto 0) := "10110";
constant st1: std_logic_vector(4 downto 0) := "11010";
constant st2: std_logic_vector(4 downto 0) := "10101";
constant st3: std_logic_vector(4 downto 0) := "01010";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00110";
constant st6: std_logic_vector(4 downto 0) := "00011";
constant st7: std_logic_vector(4 downto 0) := "01110";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "11111";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "01001";
constant st12: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10010";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "11110";
constant st17: std_logic_vector(4 downto 0) := "01101";
constant st18: std_logic_vector(4 downto 0) := "00010";
constant st19: std_logic_vector(4 downto 0) := "11101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "000000";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "000000";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "000000";
elsif std_match(input, "----1---") then next_state <= st3; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "000000";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "000000";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "000000";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "000000";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "000000";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "000000";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "000000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000000";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000000";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "000000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "000000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "000000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "000000";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "000000";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "------1-") then next_state <= st7; output <= "000000";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "000000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "000000";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "000000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000000";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "000000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | d5543b724527f098fb0355e85b6ea4b6 | 0.565136 | 3.298687 | false | false | false | false |
chastell/art-decomp | kiss/dk16_jed.vhd | 1 | 12,212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_jed;
architecture behaviour of dk16_jed is
constant state_1: std_logic_vector(4 downto 0) := "11000";
constant state_3: std_logic_vector(4 downto 0) := "11100";
constant state_2: std_logic_vector(4 downto 0) := "01000";
constant state_4: std_logic_vector(4 downto 0) := "01010";
constant state_5: std_logic_vector(4 downto 0) := "01001";
constant state_6: std_logic_vector(4 downto 0) := "11011";
constant state_7: std_logic_vector(4 downto 0) := "11001";
constant state_9: std_logic_vector(4 downto 0) := "11010";
constant state_8: std_logic_vector(4 downto 0) := "10010";
constant state_15: std_logic_vector(4 downto 0) := "11110";
constant state_10: std_logic_vector(4 downto 0) := "10100";
constant state_14: std_logic_vector(4 downto 0) := "11101";
constant state_11: std_logic_vector(4 downto 0) := "10110";
constant state_12: std_logic_vector(4 downto 0) := "10000";
constant state_20: std_logic_vector(4 downto 0) := "01110";
constant state_13: std_logic_vector(4 downto 0) := "11111";
constant state_16: std_logic_vector(4 downto 0) := "10011";
constant state_17: std_logic_vector(4 downto 0) := "10001";
constant state_18: std_logic_vector(4 downto 0) := "01111";
constant state_19: std_logic_vector(4 downto 0) := "01100";
constant state_21: std_logic_vector(4 downto 0) := "00100";
constant state_22: std_logic_vector(4 downto 0) := "00101";
constant state_23: std_logic_vector(4 downto 0) := "01101";
constant state_24: std_logic_vector(4 downto 0) := "10111";
constant state_25: std_logic_vector(4 downto 0) := "10101";
constant state_26: std_logic_vector(4 downto 0) := "01011";
constant state_27: std_logic_vector(4 downto 0) := "00111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "00") then next_state <= state_3; output <= "001";
elsif std_match(input, "01") then next_state <= state_10; output <= "001";
elsif std_match(input, "10") then next_state <= state_11; output <= "001";
elsif std_match(input, "11") then next_state <= state_12; output <= "001";
end if;
when state_2 =>
if std_match(input, "00") then next_state <= state_1; output <= "001";
elsif std_match(input, "01") then next_state <= state_2; output <= "001";
elsif std_match(input, "10") then next_state <= state_8; output <= "001";
elsif std_match(input, "11") then next_state <= state_9; output <= "001";
end if;
when state_3 =>
if std_match(input, "00") then next_state <= state_4; output <= "001";
elsif std_match(input, "01") then next_state <= state_5; output <= "001";
elsif std_match(input, "10") then next_state <= state_6; output <= "001";
elsif std_match(input, "11") then next_state <= state_7; output <= "001";
end if;
when state_4 =>
if std_match(input, "00") then next_state <= state_4; output <= "010";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "010";
elsif std_match(input, "11") then next_state <= state_7; output <= "010";
end if;
when state_5 =>
if std_match(input, "00") then next_state <= state_1; output <= "010";
elsif std_match(input, "01") then next_state <= state_2; output <= "010";
elsif std_match(input, "10") then next_state <= state_16; output <= "010";
elsif std_match(input, "11") then next_state <= state_17; output <= "010";
end if;
when state_6 =>
if std_match(input, "00") then next_state <= state_3; output <= "010";
elsif std_match(input, "01") then next_state <= state_21; output <= "010";
elsif std_match(input, "10") then next_state <= state_10; output <= "010";
elsif std_match(input, "11") then next_state <= state_22; output <= "010";
end if;
when state_7 =>
if std_match(input, "00") then next_state <= state_9; output <= "010";
elsif std_match(input, "01") then next_state <= state_18; output <= "010";
elsif std_match(input, "10") then next_state <= state_19; output <= "010";
elsif std_match(input, "11") then next_state <= state_20; output <= "010";
end if;
when state_8 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_26; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_9 =>
if std_match(input, "00") then next_state <= state_1; output <= "000";
elsif std_match(input, "01") then next_state <= state_5; output <= "000";
elsif std_match(input, "10") then next_state <= state_6; output <= "000";
elsif std_match(input, "11") then next_state <= state_7; output <= "000";
end if;
when state_10 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_1; output <= "000";
elsif std_match(input, "11") then next_state <= state_2; output <= "000";
end if;
when state_11 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_24; output <= "000";
elsif std_match(input, "11") then next_state <= state_25; output <= "000";
end if;
when state_12 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_13 =>
if std_match(input, "00") then next_state <= state_3; output <= "101";
elsif std_match(input, "01") then next_state <= state_10; output <= "101";
elsif std_match(input, "10") then next_state <= state_11; output <= "101";
elsif std_match(input, "11") then next_state <= state_12; output <= "101";
end if;
when state_14 =>
if std_match(input, "00") then next_state <= state_1; output <= "101";
elsif std_match(input, "01") then next_state <= state_2; output <= "101";
elsif std_match(input, "10") then next_state <= state_8; output <= "101";
elsif std_match(input, "11") then next_state <= state_9; output <= "101";
end if;
when state_15 =>
if std_match(input, "00") then next_state <= state_4; output <= "101";
elsif std_match(input, "01") then next_state <= state_5; output <= "101";
elsif std_match(input, "10") then next_state <= state_6; output <= "101";
elsif std_match(input, "11") then next_state <= state_7; output <= "101";
end if;
when state_16 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_17 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_27; output <= "000";
end if;
when state_18 =>
if std_match(input, "00") then next_state <= state_4; output <= "100";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "100";
elsif std_match(input, "11") then next_state <= state_7; output <= "100";
end if;
when state_19 =>
if std_match(input, "00") then next_state <= state_18; output <= "100";
elsif std_match(input, "01") then next_state <= state_23; output <= "010";
elsif std_match(input, "10") then next_state <= state_24; output <= "100";
elsif std_match(input, "11") then next_state <= state_25; output <= "100";
end if;
when state_20 =>
if std_match(input, "00") then next_state <= state_19; output <= "100";
elsif std_match(input, "01") then next_state <= state_20; output <= "010";
elsif std_match(input, "10") then next_state <= state_9; output <= "100";
elsif std_match(input, "11") then next_state <= state_26; output <= "100";
end if;
when state_21 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_22 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "100";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_23 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_24 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_25 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_26 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_21; output <= "000";
end if;
when state_27 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 00d5255b639ac0e74e703665b01c8dc8 | 0.585162 | 3.295197 | false | false | false | false |
caiopo/battleship-vhdl | src/decod.vhd | 1 | 791 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity decod is
port (C: in std_logic_vector(3 downto 0);
S: out std_logic_vector(6 downto 0)
);
end decod;
architecture circuito of decod is
begin
-- decodifica binario para 7 segmentos
S <= "1000000" when C = "0000" else
"1111001" when C = "0001" else
"0100100" when C = "0010" else
"0110000" when C = "0011" else
"0011001" when C = "0100" else
"0010010" when C = "0101" else
"0000010" when C = "0110" else
"1111000" when C = "0111" else
"0000000" when C = "1000" else
"0011000" when C = "1001" else
"0001000" when C = "1010" else
"0000011" when C = "1011" else
"1000110" when C = "1100" else
"0100001" when C = "1101" else
"0000110" when C = "1110" else
"0001110" when C = "1111" else
"1111111";
end circuito;
| mit | 79d4bf0c65d7b69dd746980fcd041229 | 0.648546 | 2.785211 | false | false | false | false |
chastell/art-decomp | kiss/ex7_jed.vhd | 1 | 4,215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_jed;
architecture behaviour of ex7_jed is
constant s1: std_logic_vector(3 downto 0) := "0101";
constant s7: std_logic_vector(3 downto 0) := "0010";
constant s0: std_logic_vector(3 downto 0) := "0011";
constant s2: std_logic_vector(3 downto 0) := "0001";
constant s5: std_logic_vector(3 downto 0) := "0111";
constant s3: std_logic_vector(3 downto 0) := "1111";
constant s8: std_logic_vector(3 downto 0) := "0110";
constant s4: std_logic_vector(3 downto 0) := "1011";
constant s6: std_logic_vector(3 downto 0) := "1010";
constant s9: std_logic_vector(3 downto 0) := "1001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s7; output <= "11";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "11";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s7; output <= "00";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "00";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s4; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s4; output <= "11";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s6; output <= "11";
elsif std_match(input, "01") then next_state <= s3; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | d10c63c58b505871bfe326c5113a8e03 | 0.560854 | 3.280156 | false | false | false | false |
chastell/art-decomp | kiss/dk14_nov.vhd | 1 | 6,084 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_nov;
architecture behaviour of dk14_nov is
constant state_1: std_logic_vector(2 downto 0) := "101";
constant state_2: std_logic_vector(2 downto 0) := "111";
constant state_3: std_logic_vector(2 downto 0) := "001";
constant state_4: std_logic_vector(2 downto 0) := "100";
constant state_5: std_logic_vector(2 downto 0) := "011";
constant state_6: std_logic_vector(2 downto 0) := "010";
constant state_7: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-----";
case current_state is
when state_1 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_2 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_1; output <= "00001";
elsif std_match(input, "010") then next_state <= state_2; output <= "00001";
end if;
when state_3 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_4 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "10100";
elsif std_match(input, "010") then next_state <= state_7; output <= "10000";
end if;
when state_5 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_6 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10100";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_7 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when others => next_state <= "---"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 587d4fa412b3bd3955d867c78b2c5d46 | 0.599277 | 3.368771 | false | false | false | false |
chastell/art-decomp | kiss/donfile_rnd.vhd | 1 | 10,163 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity donfile_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end donfile_rnd;
architecture behaviour of donfile_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st6: std_logic_vector(4 downto 0) := "00010";
constant st12: std_logic_vector(4 downto 0) := "11011";
constant st18: std_logic_vector(4 downto 0) := "11110";
constant st1: std_logic_vector(4 downto 0) := "11111";
constant st7: std_logic_vector(4 downto 0) := "10001";
constant st2: std_logic_vector(4 downto 0) := "10110";
constant st19: std_logic_vector(4 downto 0) := "01011";
constant st3: std_logic_vector(4 downto 0) := "01111";
constant st13: std_logic_vector(4 downto 0) := "00001";
constant st4: std_logic_vector(4 downto 0) := "10000";
constant st5: std_logic_vector(4 downto 0) := "11010";
constant st14: std_logic_vector(4 downto 0) := "11000";
constant st20: std_logic_vector(4 downto 0) := "01000";
constant st8: std_logic_vector(4 downto 0) := "00100";
constant st21: std_logic_vector(4 downto 0) := "01001";
constant st9: std_logic_vector(4 downto 0) := "00110";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st10: std_logic_vector(4 downto 0) := "00011";
constant st11: std_logic_vector(4 downto 0) := "10111";
constant st22: std_logic_vector(4 downto 0) := "10011";
constant st23: std_logic_vector(4 downto 0) := "10010";
constant st16: std_logic_vector(4 downto 0) := "00111";
constant st17: std_logic_vector(4 downto 0) := "01100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st6 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st8 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st9 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st10 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st11 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st12 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st13 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st14 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st15 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st16 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st17 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st18 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st19 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st20 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st21 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st22 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st23 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when others => next_state <= "-----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | f31da4145723d07d76544790be76df44 | 0.568926 | 3.207005 | false | false | false | false |
chastell/art-decomp | kiss/lion9_jed.vhd | 1 | 3,346 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion9_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion9_jed;
architecture behaviour of lion9_jed is
constant st0: std_logic_vector(3 downto 0) := "0101";
constant st1: std_logic_vector(3 downto 0) := "1101";
constant st2: std_logic_vector(3 downto 0) := "1111";
constant st3: std_logic_vector(3 downto 0) := "0111";
constant st4: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "1001";
constant st6: std_logic_vector(3 downto 0) := "1011";
constant st7: std_logic_vector(3 downto 0) := "0011";
constant st8: std_logic_vector(3 downto 0) := "0000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "00") then next_state <= st0; output <= "0";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
elsif std_match(input, "01") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
end if;
when st7 =>
if std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 5d4770ac60dca64b602509daedf562ba | 0.575314 | 3.192748 | false | false | false | false |
chastell/art-decomp | kiss/s208_jed.vhd | 1 | 16,541 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s208_jed is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s208_jed;
architecture behaviour of s208_jed is
constant s11111111: std_logic_vector(4 downto 0) := "11001";
constant s00000000: std_logic_vector(4 downto 0) := "00011";
constant s00010000: std_logic_vector(4 downto 0) := "00111";
constant s00100000: std_logic_vector(4 downto 0) := "01011";
constant s00110000: std_logic_vector(4 downto 0) := "01111";
constant s01000000: std_logic_vector(4 downto 0) := "10011";
constant s01010000: std_logic_vector(4 downto 0) := "10010";
constant s01100000: std_logic_vector(4 downto 0) := "01001";
constant s01110000: std_logic_vector(4 downto 0) := "00110";
constant s10000000: std_logic_vector(4 downto 0) := "00000";
constant s10010000: std_logic_vector(4 downto 0) := "11011";
constant s10100000: std_logic_vector(4 downto 0) := "00010";
constant s10110000: std_logic_vector(4 downto 0) := "01010";
constant s11000000: std_logic_vector(4 downto 0) := "00101";
constant s11010000: std_logic_vector(4 downto 0) := "10111";
constant s11100000: std_logic_vector(4 downto 0) := "10001";
constant s11110000: std_logic_vector(4 downto 0) := "00100";
constant s00000001: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s11111111 =>
if std_match(input, "0--------01") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------01") then next_state <= s00000000; output <= "11";
elsif std_match(input, "0--------11") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------11") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------10") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------00") then next_state <= s00000000; output <= "10";
elsif std_match(input, "0---------0") then next_state <= s00000000; output <= "10";
end if;
when s00000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10--------0") then next_state <= s00010000; output <= "00";
end if;
when s00010000 =>
if std_match(input, "10-------00") then next_state <= s00100000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s00100000; output <= "01";
elsif std_match(input, "10-------1-") then next_state <= s00100000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
end if;
when s00100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s00110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s00110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s00110000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s00110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s01000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01000000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s01000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-----1--0") then next_state <= s01010000; output <= "01";
elsif std_match(input, "10-----0--0") then next_state <= s01010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01010000; output <= "01";
end if;
when s01010000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s01100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01100000; output <= "01";
end if;
when s01100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1-0") then next_state <= s01110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s01110000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01110000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s01110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s10000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10----0---0") then next_state <= s10010000; output <= "00";
elsif std_match(input, "10----1---0") then next_state <= s10010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s10010000; output <= "01";
elsif std_match(input, "11----1---0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11----0---0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s10010000 =>
if std_match(input, "10--------1") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10100000; output <= "00";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s10100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s10110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s10110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s10110000; output <= "01";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when s10110000 =>
if std_match(input, "10--------1") then next_state <= s11000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11000000; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s11000000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s11000000 =>
if std_match(input, "10-----0--0") then next_state <= s11010000; output <= "00";
elsif std_match(input, "10-----1--0") then next_state <= s11010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s11010000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s11010000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s11100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s11100000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01--------1") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s11100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10------1--") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-1") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s11110000; output <= "00";
end if;
when s11110000 =>
if std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------01") then next_state <= s00000001; output <= "00";
elsif std_match(input, "-0-------00") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------11") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------11") then next_state <= s00000001; output <= "00";
elsif std_match(input, "00-------10") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s00000001; output <= "01";
end if;
when s00000001 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10---1----0") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10---0----0") then next_state <= s00010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "11---0----0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11---1----0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 11fee153242c84466f5fb1bd211e5cfc | 0.565625 | 3.517865 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/io_ctrl.vhd | 1 | 3,071 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : io_ctrl.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: io control module according spec
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of io_ctrl is
constant C_COUNT_1KHZ : integer := 50000; -- 1 kHZ clock for counting
component gen_debouncer
generic (
N : integer := 16);
port (
clk_i : in std_logic; -- input clock
reset_i : in std_logic; -- input reset
data_i : in std_logic_vector(N-1 downto 0); -- N signals to debounce
q_o : out std_logic_vector(N-1 downto 0)); -- debounced signal
end component;
component clk_gen is
port(
clk_i : in std_logic;
reset_i : in std_logic;
count_val_i : in integer;
signal_o : out std_logic);
end component;
component bin2bcd is
port(
digits_i : in std_logic_vector(13 downto 0);
bcd_o : out std_logic_vector(16 downto 0)
);
end component;
component x7seg is
port (
clk_i : in std_logic;
reset_i : in std_logic;
digits_i : in std_logic_vector(15 downto 0);
aen_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(7 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0));
end component;
signal s_bcd : std_logic_vector(16 downto 0);
signal s_aen : std_logic_vector(3 downto 0);
signal s_clk_1kHz : std_logic;
begin
s_aen <= "1111"; -- set all 7-seg to on
p_pb_clean : gen_debouncer
generic map (
N => 4)
port map (
clk_i => s_clk_1kHz,
reset_i => reset_i,
data_i => pb_i,
q_o => pbclean_o);
p_sw_clean : gen_debouncer
generic map(
N => 16)
port map (
clk_i => s_clk_1kHz,
reset_i => reset_i,
data_i => sw_i,
q_o => swclean_o);
p_clk_1kHz : clk_gen
port map (
clk_i => clk_i,
reset_i => reset_i,
count_val_i => C_COUNT_1KHZ,
signal_o => s_clk_1kHz);
p_bin2bcd: bin2bcd
port map (
digits_i => digits_i,
bcd_o => s_bcd);
p_x7seg: x7seg
port map (
clk_i => s_clk_1kHz,
reset_i => reset_i,
digits_i => s_bcd(15 downto 0),
aen_i => s_aen,
ss_o => ss_o,
ss_sel_o => ss_sel_o);
end rtl; | mit | 67b847d50d1c01872ed0906061c283db | 0.469228 | 3.587617 | false | false | false | false |
chastell/art-decomp | kiss/bbara_nov.vhd | 1 | 6,275 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_nov is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_nov;
architecture behaviour of bbara_nov is
constant st0: std_logic_vector(3 downto 0) := "0100";
constant st1: std_logic_vector(3 downto 0) := "0000";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st3: std_logic_vector(3 downto 0) := "0011";
constant st4: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "1101";
constant st6: std_logic_vector(3 downto 0) := "1100";
constant st7: std_logic_vector(3 downto 0) := "0111";
constant st8: std_logic_vector(3 downto 0) := "0110";
constant st9: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "--01") then next_state <= st0; output <= "00";
elsif std_match(input, "--10") then next_state <= st0; output <= "00";
elsif std_match(input, "--00") then next_state <= st0; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st1 =>
if std_match(input, "--01") then next_state <= st1; output <= "00";
elsif std_match(input, "--10") then next_state <= st1; output <= "00";
elsif std_match(input, "--00") then next_state <= st1; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st2; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st2 =>
if std_match(input, "--01") then next_state <= st2; output <= "00";
elsif std_match(input, "--10") then next_state <= st2; output <= "00";
elsif std_match(input, "--00") then next_state <= st2; output <= "00";
elsif std_match(input, "0011") then next_state <= st1; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st3 =>
if std_match(input, "--01") then next_state <= st3; output <= "10";
elsif std_match(input, "--10") then next_state <= st3; output <= "10";
elsif std_match(input, "--00") then next_state <= st3; output <= "10";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "10";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st4 =>
if std_match(input, "--01") then next_state <= st4; output <= "00";
elsif std_match(input, "--10") then next_state <= st4; output <= "00";
elsif std_match(input, "--00") then next_state <= st4; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st5; output <= "00";
end if;
when st5 =>
if std_match(input, "--01") then next_state <= st5; output <= "00";
elsif std_match(input, "--10") then next_state <= st5; output <= "00";
elsif std_match(input, "--00") then next_state <= st5; output <= "00";
elsif std_match(input, "0011") then next_state <= st4; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "00";
end if;
when st6 =>
if std_match(input, "--01") then next_state <= st6; output <= "01";
elsif std_match(input, "--10") then next_state <= st6; output <= "01";
elsif std_match(input, "--00") then next_state <= st6; output <= "01";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "01";
end if;
when st7 =>
if std_match(input, "--01") then next_state <= st7; output <= "00";
elsif std_match(input, "--10") then next_state <= st7; output <= "00";
elsif std_match(input, "--00") then next_state <= st7; output <= "00";
elsif std_match(input, "0011") then next_state <= st8; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st8 =>
if std_match(input, "--01") then next_state <= st8; output <= "00";
elsif std_match(input, "--10") then next_state <= st8; output <= "00";
elsif std_match(input, "--00") then next_state <= st8; output <= "00";
elsif std_match(input, "0011") then next_state <= st9; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st9 =>
if std_match(input, "--01") then next_state <= st9; output <= "00";
elsif std_match(input, "--10") then next_state <= st9; output <= "00";
elsif std_match(input, "--00") then next_state <= st9; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | fbeda89504a4a2254f80f7ddc49028c0 | 0.571474 | 3.280188 | false | false | false | false |
ibm2030/IBM2030 | ibm2030-storage.vhd | 1 | 14,836 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-storage.vhd
-- Creation Date: 19:55:00 20/07/10
-- Description:
-- 360/30 Storage Handling - Main and Local (Bump) Storage
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-20 Initial Release
-- Revision 1.1 2012-03-06 Modified to parse PCH files from Hercules (ESD/TXT/TXT/TXT/RLD/RLD/END)
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity storage is
Port ( -- Physical storage I/O from FPGA
phys_address : out std_logic_vector(16 downto 0);
phys_data : inout std_logic_vector(8 downto 0);
phys_CE : out std_logic;
phys_OE : out std_logic;
phys_WE : out std_logic;
phys_UB,phys_LB : out std_logic;
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
-- Interface to config ROM
din : in STD_LOGIC;
reset_prom : out STD_LOGIC;
cclk : out STD_LOGIC;
-- Storage interface to CPU
StorageIn : out STORAGE_IN_INTERFACE;
StorageOut : in STORAGE_OUT_INTERFACE;
debug : out STD_LOGIC
);
end storage;
architecture Behavioral of storage is
--
-- declaration of serial configuration PROM reading interface
--
component prom_reader_serial
generic( length : integer := 5; --sync pattern 2^length
frequency : integer := 50 ); --system clock speed in MHz
port( clock : in std_logic;
reset : in std_logic; --active high
read : in std_logic; --active low single cycle pulse
next_sync : in std_logic; --active low single cycle pulse
din : in std_logic;
sync_pattern : in std_logic_vector((2**length) - 1 downto 0);
cclk : out std_logic;
sync : out std_logic; --active low single cycle pulse
data_ready : out std_logic; --active low single cycle pulse
reset_prom : out std_logic; --active high to /OE of PROM (reset when high)
dout : out std_logic_vector(7 downto 0));
end component;
-- Signals for RAM clearing and initialisation purposes (at startup)
signal drive_out : std_logic;
signal addr : std_logic_vector(15 downto 0) := "0000000000000000";
signal len : std_logic_vector(15 downto 0) := "0000000000000000";
signal init_CE : std_logic;
signal init_WE : std_logic;
signal init_OE : std_logic;
signal init_drive_out, clear_data_out, clear_local_data_out, init_data_out: std_logic;
signal clear_data : std_logic_vector(7 downto 0) := "00000000"; -- Value written into storage locations when clearing
signal init_data : std_logic_vector(7 downto 0);
type init_state is (
initClearMainStorage,initClearLocalStorage,
resetProm,resetProm2,
wait_for_first_high_length_byte,wait_for_high_length_byte,got_high_length_byte,wait_for_low_length_byte,got_low_length_byte,
wait_for_high_address_byte,got_high_address_byte,wait_for_low_address_byte,got_low_address_byte,
wait_for_data_byte, write_byte, written_byte, finished);
signal state : init_state := initClearMainStorage;
--
-- Signals for serial PROM reader
--
signal reset_prom_reader : std_logic;
signal prom_read_pulse : std_logic;
signal prom_sync_pulse : std_logic;
signal prom_data_ready_pulse : std_logic;
begin
-- See Xilinx XAPP694 for how to store user data in the platform flash
-- Input file format is
-- Header 8F9FAFBF (see XAPP694)
-- LL High byte of data segment length
-- LL Low byte of data segment length
-- AA High byte of destination address
-- AA Low byte of destination address
-- DD Data byte (repeated a total of LLLL times)
-- LL LL AA AA DD DD ... DD repeated as required
-- 00 00 Length of 0000 to terminate
Initialise: process(clk) is
begin
-- Initialise storage
if clk'event and clk='1' then -- Wait for rising edge of 50MHz clock
case state is
-- Clear the 64k of main storage space
when initClearMainStorage =>
init_data_out <= '0'; -- '1' if we're initialising RAM from PROM
clear_data_out <= '1'; -- '1' if we're clearing the 64k main storage space
clear_local_data_out <= '0'; -- '1' if we're clearing the local storage space
addr <= (others=>'0'); -- Start clearing at 0000
len <= (others=>'0'); -- Clear 64k
state <= write_byte; -- Will come back to initClearLocalStorage
-- Clear 64k of local storage space, though only a small portion is actually used
when initClearLocalStorage =>
clear_data_out <= '0'; -- Done with clearing main storage...
clear_local_data_out <= '1'; -- ... so on to clearing local storage
addr <= (others=>'0'); -- Start clearing at 0000
len <= (others=>'0'); -- Clear 64k
state <= write_byte; -- Will come back to resetProm
when resetProm =>
clear_data_out <= '0'; -- Done with clearing main storage...
clear_local_data_out <= '0'; -- ...and local storage...
init_data_out <= '1'; -- ...so on to initialising storage from PROM
state <= resetProm2;
when resetProm2 =>
state <= wait_for_first_high_length_byte;
when wait_for_first_high_length_byte =>
-- Wait until we get the first data byte, which is the high byte of the length
-- Note we don't need to assert the PROM read pulse in this state
-- as the first byte following the sync pattern is automatically read
if (prom_data_ready_pulse = '0') then
len(15 downto 8) <= init_data;
state <= got_high_length_byte;
else
state <= wait_for_high_length_byte;
end if;
when wait_for_high_length_byte =>
-- Wait until we get a high length byte
if (prom_data_ready_pulse = '0') then
-- Store it in len (high)
len(15 downto 8) <= init_data;
state <= got_high_length_byte;
else
state <= wait_for_high_length_byte;
end if;
when got_high_length_byte =>
state <= wait_for_low_length_byte;
when wait_for_low_length_byte =>
-- Wait until we get a low length byte
if (prom_data_ready_pulse = '0') then
-- Store it in len (low)
len(7 downto 0) <= init_data;
-- Check if both bytes are 00, finish if so
-- Note: Can't check len(7 downto 0) as it isn't in there yet
if len(15 downto 8)="00000000" and init_data="00000000" then
state <= finished;
else
-- Not 0 length, go on to getting address & data bytes
state <= got_low_length_byte;
end if;
else
state <= wait_for_low_length_byte;
end if;
when got_low_length_byte =>
state <= wait_for_high_address_byte;
when wait_for_high_address_byte =>
-- Wait until we get the high address byte
if (prom_data_ready_pulse = '0') then
-- Store it in addr (high)
addr(15 downto 8) <= init_data;
state <= got_high_address_byte;
else
state <= wait_for_high_address_byte;
end if;
when got_high_address_byte =>
-- prom_read_pulse <= '0';
state <= wait_for_low_address_byte;
when wait_for_low_address_byte =>
-- Wait until we get the low address byte
if (prom_data_ready_pulse = '0') then
-- Store it in addr (low)
addr(7 downto 0) <= init_data;
state <= got_low_address_byte;
else
state <= wait_for_low_address_byte;
end if;
when got_low_address_byte =>
state <= wait_for_data_byte;
when wait_for_data_byte =>
-- Wait until we get one of our data bytes from the PROM
if (prom_data_ready_pulse = '0') then
state <= write_byte;
else
state <= wait_for_data_byte;
end if;
when write_byte =>
-- WE* is asserted during this state and does the actual write
state <= written_byte;
when written_byte =>
-- Bump address and count
addr <= addr + "0000000000000001";
len <= len - "0000000000000001";
-- Compare length to 1 (not 0) as it is about to be decremented
if (len="0000000000000001") then
-- Ok, have done all the bytes now
if clear_data_out='1' then
-- If we were clearing main storage, go on to clearing local storage
state <= initClearLocalStorage;
else if clear_local_data_out='1' then
-- If we were clearing local storage, go on to initialising storage
state <= resetProm;
else
-- Doing initialisation, so look for a further length value
state <= wait_for_high_length_byte;
end if;
end if;
else
-- Not finished yet
if clear_data_out='1' or clear_local_data_out='1' then
-- Clearing storage can go straight back and do another byte
state <= write_byte;
else
-- Initialising storage needs to fetch a byte from PROM
state <= wait_for_data_byte;
end if;
end if;
when finished =>
-- Make sure we can't interfere with CPU operation
init_data_out <= '0';
when others =>
end case;
end if;
end process;
-- Outputs generated as a function of the initialisation machine state:
init_drive_out <= '0' when state=finished else '1';
init_ce <= '0' when state=wait_for_data_byte or state=write_byte or state=written_byte else '1';
init_oe <= '1';
init_we <= '0' when state=write_byte else '1'; -- Only assert WE* from the one state
reset_prom_reader <= '1' when state=resetProm or state=resetProm2 else '0';
-- reset_prom_reader <= '1' when state=resetProm else '0';
prom_read_pulse <= '0' when state=wait_for_high_length_byte
or state=wait_for_low_length_byte
or state=wait_for_high_address_byte
or state=wait_for_low_address_byte
or state=wait_for_data_byte; -- Trigger a further PROM read when in these states
phys_CE <= init_ce when init_drive_out='1' else '0' when StorageOut.ReadPulse='1' or StorageOut.WritePulse='1' else '1'; -- Select which CE* to use
phys_WE <= init_we when init_drive_out='1' else '0' when StorageOut.WritePulse='1' else '1'; -- Select which WE* to use
phys_UB <= '0'; -- Always select upper byte
phys_LB <= '0'; -- Always select lower byte
phys_OE <= init_oe when init_drive_out='1' else '0' when StorageOut.ReadPulse='1' or StorageOut.WritePulse='0' else '1'; -- Assert OE* if reading
drive_out <= '1' when init_drive_out='1' else '0' when StorageOut.ReadPulse='1' else '1'; -- Whether data bus is driving out, or tristated for input
-- Read in and latch data when doing a real memory read (note - this does not erase the memory as real core would)
StorageIn.ReadData <= phys_data when StorageOut.ReadPulse='1';
-- Select initialisation data or real (R reg) data to go out when writing
phys_data <= init_data & evenParity(init_data) when init_drive_out='1' and init_data_out='1'
else clear_data & evenParity(clear_data) when init_drive_out='1' and (clear_data_out='1' or clear_local_data_out='1')
else StorageOut.WriteData when drive_out='1'
else "ZZZZZZZZZ";
-- Select initialisation address or real (MN reg) address to go out
-- Top bit is 0 for Local Storage and 1 for Main Storage
phys_address <= (not clear_local_data_out) & addr when init_drive_out='1' else StorageOut.MainStorage & StorageOut.MSAR;
-- This turns the debug light on during initialisation
-- (if configured in the higher-level blocks)
debug <= init_drive_out;
--
----------------------------------------------------------------------------------------------------------------------------------
-- Serial configuration PROM reader
----------------------------------------------------------------------------------------------------------------------------------
--
-- This macro enables data stored afater the Spartan-3 configuration data to be located and then read
-- sequentially.
--
prom_access: prom_reader_serial
generic map( length => 5, --Synchronisation pattern is 2^5 = 32 bits
frequency => 50) --System clock rate is 50MHz
port map( clock => clk,
reset => reset_prom_reader, --reset reader and initiates search for sync pattern
read => prom_read_pulse, --active low pulse initiates retrieval of next byte
next_sync => '1', --would be used to find another sync pattern
din => din, --from XCF04S device
sync_pattern => X"8F9FAFBF", --32bit synchronisation pattern is constant in this application
cclk => cclk, --to XCF04S device
sync => prom_sync_pulse, --active low pulse indicates sync pattern located
data_ready => prom_data_ready_pulse, --active low pulse indicates data byte received
reset_prom => reset_prom, --to XCF04S device
dout => init_data); --byte received from serial prom
end behavioral;
| gpl-3.0 | bc228c4f5259f427b32a0258ac80b43f | 0.608318 | 3.639843 | false | false | false | false |
chastell/art-decomp | kiss/lion9_nov.vhd | 1 | 3,346 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion9_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion9_nov;
architecture behaviour of lion9_nov is
constant st0: std_logic_vector(3 downto 0) := "0010";
constant st1: std_logic_vector(3 downto 0) := "0000";
constant st2: std_logic_vector(3 downto 0) := "0100";
constant st3: std_logic_vector(3 downto 0) := "0110";
constant st4: std_logic_vector(3 downto 0) := "0111";
constant st5: std_logic_vector(3 downto 0) := "0101";
constant st6: std_logic_vector(3 downto 0) := "0011";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st8: std_logic_vector(3 downto 0) := "1011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "00") then next_state <= st0; output <= "0";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
elsif std_match(input, "01") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
end if;
when st7 =>
if std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 5d97d06802a5d4c3f2df9f2391fc5165 | 0.575314 | 3.192748 | false | false | false | false |
ibm2030/IBM2030 | PROM_reader_serial.vhd | 1 | 8,281 | --*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you "as is". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- MODULE : PROM_reader_serial.vhd
-- AUTHOR : Stephan Neuhold
-- VERSION : v1.00
--
--
-- REVISION HISTORY:
-- -----------------
-- No revisions
--
--
-- FUNCTION DESCRIPTION:
-- ---------------------
-- This module provides the control state machine
-- for reading data from the PROM. This includes
-- searching for synchronisation patterns, retrieving
-- data, resetting the PROMs address counter.
--***************************
--* Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--***********************
--* Entity declaration
--***********************
entity PROM_reader_serial is
generic(
length : integer := 5;
frequency : integer := 50
);
port(
clock : in std_logic;
reset : in std_logic; --active high
read : in std_logic; --active low
next_sync : in std_logic; --active low
din : in std_logic;
sync_pattern : in std_logic_vector((2**length) - 1 downto 0);
cclk : out std_logic;
sync : out std_logic; --active low
data_ready : out std_logic; --active low
reset_prom : out std_logic; --active high
dout : out std_logic_vector(7 downto 0)
);
end PROM_reader_serial;
architecture Behavioral of PROM_reader_serial is
component clock_management
generic(
length : integer := 5;
frequency : integer := 50
);
port(
clock : in std_logic;
enable : in std_logic;
read_enable : out std_logic;
cclk : out std_logic
);
end component;
component shift_compare_serial
generic(
length : integer := 5
);
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
din : in std_logic;
b : in std_logic_vector((2**length) - 1 downto 0);
eq : out std_logic;
din_shifted : out std_logic_vector(7 downto 0)
);
end component;
type state_type is (Look4Sync, Wait4Active, GetData, PresentData);
signal current_state : state_type;
signal count : std_logic_vector(length downto 0);
signal din_read_enable : std_logic;
signal sync_found : std_logic;
signal data : std_logic_vector(7 downto 0);
signal sync_int : std_logic;
signal cclk_on : std_logic;
signal reset_n : std_logic;
begin
--Clock generation and clock enable generation
Clock_Manager: clock_management
generic map(
length => length,
frequency => frequency
)
port map(
clock => clock,
enable => cclk_on,
read_enable => din_read_enable,
cclk => cclk
);
--Shift and compare operation
Shift_And_Compare: shift_compare_serial
generic map(
length => length
)
port map(
clock => clock,
reset => reset,
enable => din_read_enable,
din => din,
b => sync_pattern,
eq => sync_found,
din_shifted => data
);
--State machine
process (clock, reset, current_state, sync_int, read, count,
data, sync_found)
begin
if (reset = '1') then
current_state <= Look4Sync; --this can be changed to Wait4Active so that the FPGA doesnt go looking for data immediately after config
dout <= (others => '0');
count <= (others => '0');
sync_int <= '0';
data_ready <= '1';
reset_PROM <= '0';
cclk_on <= '1';
elsif rising_edge(clock) then
case current_state is
--*************************************************************
--* This state clocks in one bit of data at a time from the
--* PROM. With every new bit clocked in a comparison is done
--* to check whether it matches the synchronisation pattern.
--* If the pattern is found then a further bits are read
--* from the PROM to provide the first byte of data appearing
--* after the synchronisation pattern.
--*************************************************************
when Look4Sync =>
count <= (others => '0');
data_ready <= '1';
sync_int <= '0';
reset_PROM <= '1';
if (sync_found = '1') then
current_state <= Wait4Active;
sync_int <= '1';
cclk_on <= '0';
end if;
--*********************************************************
--* At this point the state machine waits for user input.
--* If the user pulses the "read" signal then 8 bits of
--* are retrieved from the PROM. If the user wants to
--* look for another synchronisation pattern and pulses
--* the "next_sync" signal, then the state machine goes
--* into the "Look4Sync" state.
--*********************************************************
when Wait4Active =>
count <= (others => '0');
data_ready <= '1';
if (read = '0' or sync_int = '1') then
current_state <= GetData;
cclk_on <= '1';
end if;
if (next_sync = '0') then
current_state <= Look4Sync;
cclk_on <= '1';
end if;
--*********************************************************
--* This state gets the data from the PROM. If the
--* synchronisation pattern has just been found then
--* enough data is retrieved to present the first
--* 8 bits after the pattern. This is dependant on the
--* synchronisation pattern length.
--* If the synchronisation pattern has already been found
--* previously then only the next 8 bits of data are
--* retrieved.
--*********************************************************
when GetData =>
if (din_read_enable = '1') then
count <= count + 1;
if (sync_int = '1') then
if (count = (2**length) - 1) then
current_state <= PresentData;
sync_int <= '0';
cclk_on <= '0';
end if;
else
if (count = 7) then
current_state <= PresentData;
sync_int <= '0';
cclk_on <= '0';
end if;
end if;
end if;
--*******************************************************
--* This state tells the user that 8 bits of data have
--* been retrieved and is presented on the "dout" port.
--* The "Wait4Active" state is then entered to wait for
--* another user request.
--*******************************************************
when PresentData =>
dout <= data;
data_ready <= '0';
current_state <= Wait4Active;
when others =>
null;
end case;
end if;
sync <= not sync_found;
end process;
end Behavioral;
| gpl-3.0 | 5c04aa6d0ee04f3c62179676fa4003b7 | 0.554039 | 3.867819 | false | false | false | false |
es17m014/vhdl-counter | src/old/vhdl/x7seg_top.vhd | 1 | 2,302 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : x7seg_top.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: For testing
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity x7seg_top is
port (
clk_i : in std_logic;
btn_i : in std_logic_vector(3 downto 3);
aen_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end x7seg_top;
architecture rtl of x7seg_top is
component clkdiv
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk190_o : out std_logic
);
end component clkdiv;
component x7seg is
port (
digits_i : in std_logic_vector(15 downto 0);
clk_i : in std_logic;
reset_i : in std_logic;
aen_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end component;
signal reset_i : std_logic;
signal digits_i : std_logic_vector(15 downto 0);
signal clk190Hz_o : std_logic;
begin
digits_i <= X"ABCD";
reset_i <= btn_i(3);
comp1: clkdiv
port map(
clk_i => clk_i,
reset_i => reset_i,
clk190Hz_o => clk190Hz_o
);
comp2: x7seg
port map(
digits_i => digits_i,
clk_i => clk190Hz_o,
reset_i => reset_i,
aen_i => aen_i,
ss_o => ss_o,
ss_sel_o => ss_sel_o,
dp_o => dp_o
);
end rtl; | mit | 6234df1a9d690b58a85dd8235e790132 | 0.430061 | 3.895093 | false | false | false | false |
chastell/art-decomp | kiss/lion_rnd.vhd | 1 | 1,832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_rnd;
architecture behaviour of lion_rnd is
constant st0: std_logic_vector(1 downto 0) := "01";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "00";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "-0") then next_state <= st0; output <= "0";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "0-") then next_state <= st1; output <= "1";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "1-") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "0-") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 9f98de2d4d1b029ec5d26b4312a8bf36 | 0.587882 | 3.231041 | false | false | false | false |
chastell/art-decomp | kiss/shiftreg_hot.vhd | 1 | 2,608 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_hot;
architecture behaviour of shiftreg_hot is
constant st0: std_logic_vector(7 downto 0) := "10000000";
constant st4: std_logic_vector(7 downto 0) := "01000000";
constant st1: std_logic_vector(7 downto 0) := "00100000";
constant st2: std_logic_vector(7 downto 0) := "00010000";
constant st5: std_logic_vector(7 downto 0) := "00001000";
constant st3: std_logic_vector(7 downto 0) := "00000100";
constant st6: std_logic_vector(7 downto 0) := "00000010";
constant st7: std_logic_vector(7 downto 0) := "00000001";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st0; output <= "1";
elsif std_match(input, "1") then next_state <= st4; output <= "1";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st1; output <= "1";
elsif std_match(input, "1") then next_state <= st5; output <= "1";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st2; output <= "1";
elsif std_match(input, "1") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st3; output <= "1";
elsif std_match(input, "1") then next_state <= st7; output <= "1";
end if;
when others => next_state <= "--------"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | d7db8ea0ae4218c6467d769a831b2e46 | 0.581672 | 3.25593 | false | false | false | false |
chastell/art-decomp | kiss/ex2_jed.vhd | 1 | 7,775 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_jed;
architecture behaviour of ex2_jed is
constant s1: std_logic_vector(4 downto 0) := "00001";
constant s2: std_logic_vector(4 downto 0) := "00011";
constant s4: std_logic_vector(4 downto 0) := "00101";
constant s0: std_logic_vector(4 downto 0) := "01011";
constant s3: std_logic_vector(4 downto 0) := "01101";
constant s6: std_logic_vector(4 downto 0) := "01010";
constant s9: std_logic_vector(4 downto 0) := "00111";
constant s7: std_logic_vector(4 downto 0) := "11010";
constant s8: std_logic_vector(4 downto 0) := "01110";
constant s5: std_logic_vector(4 downto 0) := "01001";
constant s10: std_logic_vector(4 downto 0) := "11111";
constant s11: std_logic_vector(4 downto 0) := "11011";
constant s13: std_logic_vector(4 downto 0) := "11101";
constant s12: std_logic_vector(4 downto 0) := "11001";
constant s15: std_logic_vector(4 downto 0) := "10011";
constant s18: std_logic_vector(4 downto 0) := "10111";
constant s16: std_logic_vector(4 downto 0) := "00010";
constant s17: std_logic_vector(4 downto 0) := "01000";
constant s14: std_logic_vector(4 downto 0) := "01111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 600e1e623ab231e9fa1dda6cfa600985 | 0.552154 | 3.338343 | false | false | false | false |
chastell/art-decomp | kiss/cse_rnd.vhd | 1 | 10,008 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_rnd;
architecture behaviour of cse_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st9: std_logic_vector(3 downto 0) := "1011";
constant st6: std_logic_vector(3 downto 0) := "1110";
constant st8: std_logic_vector(3 downto 0) := "1111";
constant st2: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "0110";
constant st3: std_logic_vector(3 downto 0) := "0000";
constant st4: std_logic_vector(3 downto 0) := "1010";
constant st7: std_logic_vector(3 downto 0) := "1000";
constant st10: std_logic_vector(3 downto 0) := "0100";
constant st11: std_logic_vector(3 downto 0) := "1001";
constant st12: std_logic_vector(3 downto 0) := "1100";
constant st13: std_logic_vector(3 downto 0) := "0011";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "1-000--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-11---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-1-1--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-10";
elsif std_match(input, "10011--") then next_state <= st9; output <= "0010001";
elsif std_match(input, "10001--") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10100--") then next_state <= st8; output <= "0000--0";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st1 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "0100-00";
elsif std_match(input, "1000---") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st2 =>
if std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "10000--") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "10001--") then next_state <= st3; output <= "1000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----1") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "0000-10";
end if;
when st3 =>
if std_match(input, "10001--") then next_state <= st3; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st4 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "1000---") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st5; output <= "0000-00";
elsif std_match(input, "10-0---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st6 =>
if std_match(input, "10--1--") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st7 =>
if std_match(input, "100--0-") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "101--0-") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10---1-") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st8 =>
if std_match(input, "10-00--") then next_state <= st8; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st9; output <= "0010101";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "0000-10";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st9 =>
if std_match(input, "10-1---") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st7; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st10 =>
if std_match(input, "10-0---") then next_state <= st10; output <= "0000-00";
elsif std_match(input, "10-10--") then next_state <= st11; output <= "0000100";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st11 =>
if std_match(input, "10-10--") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st12 =>
if std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "10-10--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st13 =>
if std_match(input, "10-10--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10-01--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st14 =>
if std_match(input, "--111--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--110--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--101--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--0----") then next_state <= st0; output <= "0001000";
end if;
when st15 =>
if std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "10010--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "10001--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "101----") then next_state <= st8; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0001000";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0001000";
elsif std_match(input, "10011--") then next_state <= st0; output <= "0001000";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | a8ef03728e701ce233e7ab25cacfc7c8 | 0.565248 | 3.317203 | false | false | false | false |
es17m014/vhdl-counter | src/tb/clk_gen_tb.vhd | 1 | 1,619 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_tb.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Testbench for the generic counter
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 19.11.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity clk_gen_tb is
end clk_gen_tb;
architecture sim of clk_gen_tb is
component clk_gen is
port(
clk_i : in std_logic;
reset_i : in std_logic;
count_val_i : in integer;
signal_o : out std_logic);
end component;
signal clk_i : std_logic;
signal reset_i : std_logic;
signal signal_o : std_logic;
begin
-- Generate system clock 100 MHz
p_clk : process
begin
clk_i <= '0';
wait for 5 ns;
clk_i <= '1';
wait for 5 ns;
end process;
p_clk_gen : clk_gen
port map (
clk_i => clk_i,
reset_i => reset_i,
count_val_i => 50000,
signal_o => signal_o);
-- do the simulation
p_sim : process
begin
reset_i <= '0';
wait for 100 ms;
end process;
end sim; | mit | 5dbfc8ff5aec7467445b228431956188 | 0.432983 | 4.340483 | false | false | false | false |
chastell/art-decomp | kiss/sse_jed.vhd | 1 | 6,957 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_jed;
architecture behaviour of sse_jed is
constant st11: std_logic_vector(3 downto 0) := "0010";
constant st10: std_logic_vector(3 downto 0) := "0011";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st12: std_logic_vector(3 downto 0) := "1001";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st6: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1000";
constant st0: std_logic_vector(3 downto 0) := "1111";
constant st8: std_logic_vector(3 downto 0) := "1110";
constant st9: std_logic_vector(3 downto 0) := "1101";
constant st3: std_logic_vector(3 downto 0) := "0101";
constant st2: std_logic_vector(3 downto 0) := "0111";
constant st5: std_logic_vector(3 downto 0) := "1010";
constant st13: std_logic_vector(3 downto 0) := "1100";
constant st14: std_logic_vector(3 downto 0) := "0100";
constant st15: std_logic_vector(3 downto 0) := "0110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | c7b806f931f9083682e73049ad3e6255 | 0.559724 | 3.31128 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/hex7seg.vhd | 1 | 2,605 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : hex7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Convert a hex digit to 7 segment dislplay according
--
-- +-------+---+---+---+---+---+---+---+
-- | digit | a | b | c | d | e | f | g |
-- +-------+---+---+---+---+---+---+---+
-- | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
-- | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
-- | 2 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
-- | 3 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
-- | 4 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
-- | 5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |
-- | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
-- | 7 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
-- | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
-- | 9 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
-- | A | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
-- | b | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
-- | C | 0 | 1 | 1 | 0 | 0 | 0 | 1 |
-- | d | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
-- | E | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
-- | F | 0 | 1 | 1 | 1 | 0 | 0 | 0 |
-- +-------+---+---+---+---+---+---+---+
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of hex7seg is
begin
process(digit_i)
begin
case digit_i is
when "0000" => ss_o <= "0000001"; -- 0
when "0001" => ss_o <= "1001111"; -- 1
when "0010" => ss_o <= "0010010"; -- 2
when "0011" => ss_o <= "0000110"; -- 3
when "0100" => ss_o <= "1001100"; -- 4
when "0101" => ss_o <= "0100100"; -- 5
when "0110" => ss_o <= "0100000"; -- 6
when "0111" => ss_o <= "0001101"; -- 7
when "1000" => ss_o <= "0000000"; -- 8
when "1001" => ss_o <= "0000100"; -- 9
when "1010" => ss_o <= "0001000"; -- A
when "1011" => ss_o <= "1100000"; -- b
when "1100" => ss_o <= "0110001"; -- C
when "1101" => ss_o <= "1000010"; -- d
when "1110" => ss_o <= "0110000"; -- E
when others => ss_o <= "0111000"; -- F
end case;
end process;
end rtl;
| mit | 2360828385c0b7e5144e099e819bc9a6 | 0.326679 | 3.260325 | false | false | false | false |
chastell/art-decomp | kiss/tav_nov.vhd | 1 | 4,968 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tav_nov is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end tav_nov;
architecture behaviour of tav_nov is
constant st0: std_logic_vector(1 downto 0) := "00";
constant st1: std_logic_vector(1 downto 0) := "11";
constant st2: std_logic_vector(1 downto 0) := "01";
constant st3: std_logic_vector(1 downto 0) := "10";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "1000") then next_state <= st1; output <= "1000";
elsif std_match(input, "0100") then next_state <= st1; output <= "0100";
elsif std_match(input, "0010") then next_state <= st1; output <= "0010";
elsif std_match(input, "0001") then next_state <= st1; output <= "0001";
elsif std_match(input, "0000") then next_state <= st1; output <= "0000";
elsif std_match(input, "11--") then next_state <= st1; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st1; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st1; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st1; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st1; output <= "0000";
elsif std_match(input, "--11") then next_state <= st1; output <= "0000";
end if;
when st1 =>
if std_match(input, "1000") then next_state <= st2; output <= "1000";
elsif std_match(input, "0100") then next_state <= st2; output <= "0100";
elsif std_match(input, "0010") then next_state <= st2; output <= "0010";
elsif std_match(input, "0001") then next_state <= st2; output <= "0001";
elsif std_match(input, "1100") then next_state <= st2; output <= "1100";
elsif std_match(input, "1010") then next_state <= st2; output <= "1010";
elsif std_match(input, "1001") then next_state <= st2; output <= "1001";
elsif std_match(input, "0110") then next_state <= st2; output <= "0000";
elsif std_match(input, "0000") then next_state <= st2; output <= "0000";
elsif std_match(input, "0011") then next_state <= st2; output <= "0011";
elsif std_match(input, "0101") then next_state <= st2; output <= "0101";
elsif std_match(input, "0111") then next_state <= st2; output <= "0001";
elsif std_match(input, "1011") then next_state <= st2; output <= "1011";
elsif std_match(input, "1101") then next_state <= st2; output <= "1101";
elsif std_match(input, "1110") then next_state <= st2; output <= "1000";
elsif std_match(input, "1111") then next_state <= st2; output <= "1001";
end if;
when st2 =>
if std_match(input, "1000") then next_state <= st3; output <= "1000";
elsif std_match(input, "0100") then next_state <= st3; output <= "0100";
elsif std_match(input, "0010") then next_state <= st3; output <= "0010";
elsif std_match(input, "0001") then next_state <= st3; output <= "0001";
elsif std_match(input, "0000") then next_state <= st3; output <= "0000";
elsif std_match(input, "11--") then next_state <= st3; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st3; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st3; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st3; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st3; output <= "0000";
elsif std_match(input, "--11") then next_state <= st3; output <= "0000";
end if;
when st3 =>
if std_match(input, "1000") then next_state <= st0; output <= "1000";
elsif std_match(input, "0100") then next_state <= st0; output <= "0100";
elsif std_match(input, "0010") then next_state <= st0; output <= "0010";
elsif std_match(input, "0001") then next_state <= st0; output <= "0001";
elsif std_match(input, "0000") then next_state <= st0; output <= "0000";
elsif std_match(input, "11--") then next_state <= st0; output <= "0000";
elsif std_match(input, "1-1-") then next_state <= st0; output <= "0000";
elsif std_match(input, "1--1") then next_state <= st0; output <= "0000";
elsif std_match(input, "-11-") then next_state <= st0; output <= "0000";
elsif std_match(input, "-1-1") then next_state <= st0; output <= "0000";
elsif std_match(input, "--11") then next_state <= st0; output <= "0000";
end if;
when others => next_state <= "--"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | 6c8fd8bf806c2d18039a36edfc6a410c | 0.588164 | 3.314209 | false | false | false | false |
chastell/art-decomp | kiss/shiftreg_jed.vhd | 1 | 2,558 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity shiftreg_jed is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end shiftreg_jed;
architecture behaviour of shiftreg_jed is
constant st0: std_logic_vector(2 downto 0) := "100";
constant st4: std_logic_vector(2 downto 0) := "101";
constant st1: std_logic_vector(2 downto 0) := "110";
constant st2: std_logic_vector(2 downto 0) := "010";
constant st5: std_logic_vector(2 downto 0) := "111";
constant st3: std_logic_vector(2 downto 0) := "000";
constant st6: std_logic_vector(2 downto 0) := "011";
constant st7: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st0; output <= "1";
elsif std_match(input, "1") then next_state <= st4; output <= "1";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st1; output <= "1";
elsif std_match(input, "1") then next_state <= st5; output <= "1";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st2; output <= "1";
elsif std_match(input, "1") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st3; output <= "1";
elsif std_match(input, "1") then next_state <= st7; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 8e862aa90a1b174900b4941a5d5a25af | 0.577404 | 3.193508 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_UDC3.vhd | 1 | 15,359 | ---------------------------------------------------------------------------
-- Copyright 2012 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_UDC3.vhd
-- Creation Date:
-- Description:
-- 1050 Typewriter Console interface section
-- Will also include Selector Channel(s) eventually
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY udc3 IS
port
(
-- Inputs
E_SW_SEL_BUS : IN E_SW_BUS_Type;
USE_MANUAL_DECODER : IN STD_LOGIC;
USE_ALT_CA_DECODER, USE_BASIC_CA_DECO : IN STD_LOGIC;
GTD_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8);
GT_1050_TAGS_OUT : IN STD_LOGIC;
GT_1050_BUS_OUT : IN STD_LOGIC;
-- PCH_CONN_ENTRY : IN PCH_CONN;
P_1050_SEL_IN : IN STD_LOGIC;
P_1050_SEL_OUT : IN STD_LOGIC;
SUPPRESS_OUT : IN STD_LOGIC;
CK_SAL_P_BIT : IN STD_LOGIC;
RECYCLE_RESET : IN STD_LOGIC;
MPX_OPN_LT_GATE : IN STD_LOGIC;
ADDR_OUT : IN STD_LOGIC;
-- Outputs
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 111111111 when inactive
M_ASSM_BUS,N_ASSM_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
T_REQUEST : OUT STD_LOGIC;
n1050_INTRV_REQ : OUT STD_LOGIC;
TT6_POS_ATTN : OUT STD_LOGIC;
n1050_INSTALLED : OUT STD_LOGIC;
n1050_REQ_IN : OUT STD_LOGIC;
n1050_OP_IN : OUT STD_LOGIC;
n1050_CE_MODE : OUT STD_LOGIC;
n1050_SEL_O : OUT STD_LOGIC;
DEBUG : INOUT DEBUG_BUS;
-- Hardware Serial Port
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- Clocks
clk : IN STD_LOGIC;
Clock1ms : IN STD_LOGIC;
Clock60Hz : IN STD_LOGIC;
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P2,P3,P4 : IN STD_LOGIC
);
END udc3;
ARCHITECTURE FMD OF udc3 IS
signal WRITE_LCH : STD_LOGIC;
signal RST_ATTACH : STD_LOGIC;
signal PUNCH_1_CLUTCH, RDR_1_CLUTCH : STD_LOGIC;
signal READ_CLK_INTLK_LCH : STD_LOGIC;
signal CRLF : STD_LOGIC;
signal CLOCK_1 : STD_LOGIC;
signal CLK_STT_RST : STD_LOGIC;
signal W_TIME,X_TIME,Y_TIME,Z_TIME : STD_LOGIC;
signal RD_OR_RD_INQ : STD_LOGIC;
signal RD_INLK_RST : STD_LOGIC;
signal WRITE_LCH_RST : STD_LOGIC;
signal TT2_POS_END : STD_LOGIC;
signal CE_DATA_ENTER_GT : STD_LOGIC;
signal CE_TA_DECODE : STD_LOGIC;
signal CE_RESET : STD_LOGIC;
signal RUN : STD_LOGIC;
signal TAGS_OUT_BUS : STD_LOGIC_VECTOR(0 to 7);
signal sn1050_CE_MODE : STD_LOGIC;
signal EXIT_MPLX_SHARE : STD_LOGIC;
signal RD_SHARE_REQ : STD_LOGIC;
signal WR_SHARE_REQ : STD_LOGIC;
signal CE_SEL_O : STD_LOGIC;
signal sn1050_INTRV_REQ : STD_LOGIC;
signal UNGATED_RUN : STD_LOGIC;
signal REQUEST_KEY : STD_LOGIC;
signal n1050_RST_LCH : STD_LOGIC;
signal HOME_RDR_START_LCH : STD_LOGIC;
signal HOME_RDR_STOP : STD_LOGIC;
signal PROCEED_LCH : STD_LOGIC;
signal MICRO_SHARE_LCH : STD_LOGIC;
signal RDR_ON_LCH : STD_LOGIC;
signal TA_REG_POS_4 : STD_LOGIC;
signal AUDIBLE_ALARM : STD_LOGIC;
signal TA_REG_POS_6_ATTENTION_RST : STD_LOGIC;
signal SHARE_REQ_RST : STD_LOGIC;
signal CPU_REQUEST_IN : STD_LOGIC;
signal sTT6_POS_ATTN : STD_LOGIC;
signal XLATE_UC : STD_LOGIC;
signal sn1050_OP_IN : STD_LOGIC;
signal SET_SHIFT_LCH : STD_LOGIC;
signal TA_REG_SET : STD_LOGIC;
signal n1050_OPER : STD_LOGIC;
signal READ_INQ : STD_LOGIC;
signal RD_SHARE_REQ_LCH : STD_LOGIC;
signal READ : STD_LOGIC;
signal RESTORE : STD_LOGIC;
signal OUTPUT_SEL_AND_READY : STD_LOGIC;
signal UC_CHARACTER, LC_CHARACTER : STD_LOGIC;
signal PCH_BITS : STD_LOGIC_VECTOR(0 to 6);
signal CE_GT_TA_OR_TE, CE_TE_DECODE : STD_LOGIC;
signal CE_RUN_MODE : STD_LOGIC;
signal CE_BITS : STD_LOGIC_VECTOR(0 to 7);
signal DATA_REG_BUS : STD_LOGIC_VECTOR(0 to 7);
signal TE_LCH : STD_LOGIC;
signal ALLOW_STROBE : STD_LOGIC;
signal GT_WRITE_REG : STD_LOGIC;
signal FORCE_SHIFT_CHAR, FORCE_LC_SHIFT : STD_LOGIC;
signal SET_LOWER_CASE : STD_LOGIC;
signal READY_SHARE : STD_LOGIC;
signal TT_BUS : STD_LOGIC_VECTOR(0 to 7);
signal WRITE_MODE : STD_LOGIC;
signal NPL_BITS : STD_LOGIC_VECTOR(0 to 7);
signal PTT_BITS : STD_LOGIC_VECTOR(0 to 6);
signal WRITE_UC : STD_LOGIC;
signal WR_STROBE : STD_LOGIC;
signal PCH_1_HOME : STD_LOGIC;
signal TT5_POS_INTRV_REQ : STD_LOGIC;
signal CPU_LINES_ENTRY : CONN_1050;
signal CE_MODE_AND_TE_LCH : STD_LOGIC;
signal CE_SEL_OUT : STD_LOGIC;
signal CE_TI_DECODE : STD_LOGIC;
signal CE_BUS : STD_LOGIC_VECTOR(0 to 7);
signal CE_DATA_ENTER_NC : STD_LOGIC;
signal GTD_TT3 : STD_LOGIC;
BEGIN
M_ASSM_BUS <= (others=>'0');
N_ASSM_BUS <= (others=>'0');
-- Fig 5-09C
n1050_TRANSLATE : entity work.n1050_TRANSLATE port map(
-- Inputs
DATA_REG_BUS => DATA_REG_BUS,
RDR_ON_LCH => RDR_ON_LCH,
PUNCH_1_CLUTCH_1050 => PUNCH_1_CLUTCH,
HOME_RDR_STT_LCH => HOME_RDR_START_LCH,
CLOCK_STT_RST => CLK_STT_RST,
RST_ATTACH => RST_ATTACH,
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
n1050_RST => n1050_RST_LCH,
ALLOW_STROBE => ALLOW_STROBE,
PROCEED_LCH => PROCEED_LCH,
SHARE_REQ_RST => SHARE_REQ_RST,
CE_RUN_MODE => CE_RUN_MODE,
CE_TI_DECODE => CE_TI_DECODE,
SET_LOWER_CASE => SET_LOWER_CASE,
n1050_RST_LCH => n1050_RST_LCH,
READY_SHARE => READY_SHARE,
-- Outputs
TT2_POS_END => TT2_POS_END,
XLATE_UC => XLATE_UC,
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH,
READ_SHARE_REQ => RD_SHARE_REQ,
WRITE_UC => WRITE_UC,
SET_SHIFT_LCH => SET_SHIFT_LCH,
PCH_1_HOME => PCH_1_HOME,
RUN => RUN,
UNGATED_RUN => UNGATED_RUN,
READ => READ,
READ_INQ => READ_INQ,
RD_OR_RD_INQ => RD_OR_RD_INQ,
LC_CHARACTER =>LC_CHARACTER,
UC_CHARACTER => UC_CHARACTER,
WRITE_LCH => WRITE_LCH,
WRITE_MODE => WRITE_MODE,
WRITE_STROBE => WR_STROBE,
WRITE_LCH_RST => WRITE_LCH_RST,
DEBUG => open
);
-- Fig 5-10A
n1050_CLOCK : entity work.n1050_CLOCK port map (
-- Inputs
WRITE_LCH => WRITE_LCH, -- 09CD2
READ_OR_READ_INQ => RD_OR_RD_INQ, -- 09CC5
RST_ATTACH => RST_ATTACH, -- 10BC2
PUNCH_1_CLUTCH => PUNCH_1_CLUTCH, -- 10DD5
READ_CLK_INTLK_LCH => READ_CLK_INTLK_LCH, -- 10BA2
RDR_1_CLUTCH => RDR_1_CLUTCH, -- 10DD5
CRLF => CRLF, -- ?
-- Outputs
CLOCK_1 => CLOCK_1, -- 10CD1 10CA4
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
CLK_STT_RST => CLK_STT_RST, -- 09CE1
clk => clk -- 50MHz
);
-- Fig 5-10B
n1050_TAGS : entity work.n1050_TAGS port map (
-- Inputs
RD_OR_RD_INQ => RD_OR_RD_INQ, -- 09CC5
Y_TIME => Y_TIME, -- 10AXX
RD_INLK_RST => RD_INLK_RST, -- 10DC5
WRITE_LCH_RST => WRITE_LCH_RST, -- 09CE2
PCH_1_CLUTCH => PUNCH_1_CLUTCH, -- 10DD5
TT2_POS_END => TT2_POS_END, -- 09CB5
WRITE_LCH => WRITE_LCH, -- 09CD2
Z_TIME => Z_TIME, -- 10AXX
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT, -- 10DA2
CE_TA_DECODE => CE_TA_DECODE, -- 10DA1
GT_1050_TAGS_OUT => GT_1050_TAGS_OUT, -- 10CE2
RECYCLE_RESET => RECYCLE_RESET, -- 04CA5
CE_RESET => CE_RESET, -- 10DC2
RUN => RUN, -- 09CE6
TT3_POS_1050_OPER => TT_BUS(3), -- 10DD4
TAGS_OUT_BUS => TAGS_OUT_BUS, -- 10CD1
n1050_CE_MODE => sn1050_CE_MODE, -- 10DB3
n1050_SEL_O => n1050_SEL_O, -- 08DD6
P_1050_SEL_IN => P_1050_SEL_IN, -- 08DC1
P_1050_SEL_OUT => P_1050_SEL_OUT, -- 08DD6
MPX_OPN_LCH_GT => MPX_OPN_LT_GATE, -- 08CE3
CK_SAL_P_BIT => CK_SAL_P_BIT, -- 01CXX
EXIT_MPLX_SHARE => EXIT_MPLX_SHARE, -- 10DB3
ADDR_OUT => ADDR_OUT, -- 08DA5
RD_SHARE_REQ => RD_SHARE_REQ, -- 09CC6
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH, -- 09CC6
SUPPRESS_OUT => SUPPRESS_OUT, -- 08DD6
WR_SHARE_REQ => WR_SHARE_REQ, -- 10CA6
CE_SEL_O => CE_SEL_O, -- 10DB2
INTRV_REQ => sn1050_INTRV_REQ, -- 10CD6
RDY_SHARE => READY_SHARE, -- 10CE6
UNGATED_RUN => UNGATED_RUN, -- 09CE6
REQUEST_KEY => REQUEST_KEY, -- 10DE5
-- Outputs
n1050_RST_LCH => n1050_RST_LCH, -- 10DF2 09CD1 10CA5 09CE5
HOME_RDR_START_LCH => HOME_RDR_START_LCH, -- 09CE4 09CE1 10DE2
HOME_RDR_STOP => HOME_RDR_STOP, -- 10DC5
PROCEED_LCH => PROCEED_LCH, -- 09CE4 10CC2 10DE2
MICRO_SHARE_LCH => MICRO_SHARE_LCH, -- 10DE2
RDR_ON_LCH => RDR_ON_LCH, -- 09CE4 10DE2 09CE1
TA_REG_POS_4 => TA_REG_POS_4, -- 10DE2
AUDIBLE_ALARM => AUDIBLE_ALARM, -- 14AXX
CR_LF => CRLF, -- 10AC1 10DE2
TA_REG_POS_6_ATTENTION_RST => TA_REG_POS_6_ATTENTION_RST, -- ---D4 10DE2 10CE5
CPU_LINES_TO_1050 => CPU_LINES_ENTRY, -- 10DE3
SHARE_REQ_RST => SHARE_REQ_RST, -- 09CC5 10CE4 10CA5
T_REQUEST => T_REQUEST, -- 07BD3 06BA3 07BB3
CPU_REQUEST_IN => CPU_REQUEST_IN, -- 10DE3
n1050_OP_IN => sn1050_OP_IN, -- 08DD4 10CA4
n1050_REQ_IN => n1050_REQ_IN, -- 08DD2
TT6_POS_ATTN => sTT6_POS_ATTN, -- 10DC4 04AB6
n1050_INSTALLED => n1050_INSTALLED, -- 08DC1
TA_REG_SET => TA_REG_SET,
RD_CLK_INLK_LCH => READ_CLK_INTLK_LCH,
RESTORE => RESTORE,
RST_ATTACH => RST_ATTACH,
DEBUG => DEBUG,
-- Clocks
clk => clk,
Clock1ms => Clock1ms,
Clock60Hz => Clock60Hz,
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4
);
TT6_POS_ATTN <= sTT6_POS_ATTN;
n1050_OP_IN <= sn1050_OP_IN;
-- Fig 5-10C
n1050_DATA : entity work.n1050_DATA port map (
-- Inputs
E_SW_SEL_BUS => E_SW_SEL_BUS,
USE_MANUAL_DECODER => USE_MANUAL_DECODER,
USE_ALT_CA_DECODER => USE_ALT_CA_DECODER,
USE_BASIC_CA_DECO => USE_BASIC_CA_DECO,
GTD_CA_BITS => GTD_CA_BITS,
XLATE_UC => XLATE_UC,
WR_LCH => WRITE_LCH,
RUN => RUN,
PROCEED_LCH => PROCEED_LCH,
-- TT4_POS_HOME_STT => TT4_POS_HOME_STT,
RD_OR_RD_INQ => RD_OR_RD_INQ,
W_TIME => W_TIME,
X_TIME => X_TIME,
Y_TIME => Y_TIME,
Z_TIME => Z_TIME,
Z_BUS => Z_BUS,
CLOCK_1 => CLOCK_1,
PCH_1_CLUTCH => PUNCH_1_CLUTCH,
GT_1050_BUS_OUT => GT_1050_BUS_OUT,
GT_1050_TAGS_OUT => GT_1050_TAGS_OUT,
n1050_OP_IN => sn1050_OP_IN,
SET_SHIFT_LCH => SET_SHIFT_LCH,
TA_REG_SET => TA_REG_SET,
RST_ATTACH => RST_ATTACH,
n1050_OPER => n1050_OPER,
READ_INQ => READ_INQ,
RD_SHARE_REQ_LCH => RD_SHARE_REQ_LCH,
READ => READ,
WRITE_MODE => WRITE_MODE,
RESTORE => RESTORE,
OUTPUT_SEL_AND_READY => OUTPUT_SEL_AND_READY,
SHARE_REQ_RST => SHARE_REQ_RST,
n1050_RST_LCH => n1050_RST_LCH,
RDR_1_CLUTCH => RDR_1_CLUTCH,
UC_CHARACTER => UC_CHARACTER,
LC_CHARACTER => LC_CHARACTER,
-- Z_BUS_0 => Z_BUS(0),
-- Z_BUS_3 => Z_BUS(3),
-- TT3_POS_1050_OPER => TT3_POS_1050_OPER,
TA_REG_POS_6_ATTN_RST => TA_REG_POS_6_ATTENTION_RST,
PCH_BITS => PCH_BITS,
-- CE controls
CE_GT_TA_OR_TE => CE_GT_TA_OR_TE,
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT,
CE_TE_DECODE => CE_TE_DECODE,
CE_RUN_MODE => CE_RUN_MODE,
n1050_CE_MODE => sn1050_CE_MODE,
CE_BITS => CE_BITS,
-- Outputs
A_REG_BUS => A_BUS,
DATA_REG_BUS => DATA_REG_BUS,
TAGS_OUT => TAGS_OUT_BUS,
NPL_BITS => NPL_BITS,
PTT_BITS => PTT_BITS,
TE_LCH => TE_LCH,
WR_SHARE_REQ => WR_SHARE_REQ,
ALLOW_STROBE => ALLOW_STROBE,
GT_WRITE_REG => GT_WRITE_REG,
FORCE_SHIFT_CHAR => FORCE_SHIFT_CHAR,
FORCE_LC_SHIFT => FORCE_LC_SHIFT,
SET_LOWER_CASE => SET_LOWER_CASE,
n1050_INTRV_REQ => sn1050_INTRV_REQ,
READY_SHARE => READY_SHARE,
TT5_POS_INTRV_REQ => TT5_POS_INTRV_REQ,
-- Buses
TT_BUS => TT_BUS,
GTD_TT3 => GTD_TT3,
DEBUG => open,
-- Clocks
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4
);
n1050_INTRV_REQ <= sn1050_INTRV_REQ;
-- Fig 5-10D
n1050_ATTACH : entity work.n1050_ATTACH port map (
-- Inputs
-- CE Cable
CE_CABLE_IN => open,
-- CE DATA BUS From 1050 DATA section
PTT_BITS => PTT_BITS,
DATA_REG => DATA_REG_BUS,
NPL_BITS => NPL_BITS,
-- Other stuff
TE_LCH => TE_LCH,
WRITE_UC => WRITE_UC,
XLATE_UC => XLATE_UC,
CPU_REQUEST_IN => CPU_REQUEST_IN,
n1050_OP_IN => sn1050_OP_IN,
HOME_RDR_STT_LCH => HOME_RDR_START_LCH,
RDR_ON_LCH => RDR_ON_LCH,
MICRO_SHARE_LCH => MICRO_SHARE_LCH,
PROCEED_LCH => PROCEED_LCH,
TA_REG_POS_4 => TA_REG_POS_4,
CR_LF => CRLF,
TA_REG_POS_6 => TA_REG_POS_6_ATTENTION_RST,
n1050_RST => n1050_RST_LCH,
GT_WR_REG => GT_WRITE_REG,
FORCE_LC_SHIFT => FORCE_LC_SHIFT,
FORCE_SHIFT_CHAR => FORCE_SHIFT_CHAR,
WR_STROBE => WR_STROBE,
PCH_1_HOME => PCH_1_HOME,
HOME_RDR_STOP => HOME_RDR_STOP,
TT2_POS_END => TT2_POS_END,
TT5_POS_INTRV_REQ => TT5_POS_INTRV_REQ,
TT6_POS_ATTN => sTT6_POS_ATTN,
CPU_LINES_ENTRY => CPU_LINES_ENTRY,
-- PCH_CONN_ENTRY => PCH_CONN_ENTRY,
RDR_1_CLUTCH => RDR_1_CLUTCH,
-- Outputs
-- CE Cable
CE_CABLE_OUT => open,
-- CE DATA BUS to 10C (1050 DATA)
CE_GT_TA_OR_TE => CE_GT_TA_OR_TE,
CE_DATA_ENTER_GT => CE_DATA_ENTER_GT,
CE_TE_DECODE => CE_TE_DECODE,
CE_MODE_AND_TE_LCH => CE_MODE_AND_TE_LCH,
n1050_CE_MODE => sn1050_CE_MODE,
-- Other stuff
CE_SEL_OUT => CE_SEL_OUT,
CE_TI_DECODE => CE_TI_DECODE,
CE_RUN_MODE => CE_RUN_MODE,
CE_TA_DECODE => CE_TA_DECODE,
CE_BUS => CE_BUS,
EXIT_MPLX_SHARE => EXIT_MPLX_SHARE,
CE_DATA_ENTER_NC => CE_DATA_ENTER_NC,
-- TT3_POS_1050_OPER => TT_BUS(3),
-- TT4_POS_HOME_STT => TT_BUS(4),
OUTPUT_SEL_AND_RDY => OUTPUT_SEL_AND_READY,
n1050_OPER => n1050_OPER,
PUNCH_BITS => PCH_BITS,
READ_INTLK_RST => RD_INLK_RST,
PUNCH_1_CLUTCH => PUNCH_1_CLUTCH,
-- PCH_1_CLUTCH_1050 => PCH_1_CLUTCH_1050,
REQUEST_KEY => REQUEST_KEY,
-- RDR_1_CONN_EXIT => RDR_1_CONN_EXIT,
-- CPU_LINES_EXIT => n1050_CONTROL,
-- In/Out TT bus
TT_BUS => TT_BUS,
GTD_TT3 => GTD_TT3,
SerialInput => SerialInput,
SerialOutput => SerialOutput,
-- Clocks
P1 => P1,
P2 => P2,
P3 => P3,
P4 => P4,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
clk => clk
);
n1050_CE_MODE <= sn1050_CE_MODE;
-- PCH_1_CLUTCH <= PCH_CONN_ENTRY.PCH_1_CLUTCH_1050;
END FMD;
| gpl-3.0 | 50d159b536dbb2a9b7952abecf5ff008 | 0.610652 | 2.514983 | false | false | false | false |
chastell/art-decomp | kiss/ex3_rnd.vhd | 1 | 4,215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_rnd;
architecture behaviour of ex3_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101";
constant s2: std_logic_vector(3 downto 0) := "0010";
constant s4: std_logic_vector(3 downto 0) := "1011";
constant s3: std_logic_vector(3 downto 0) := "1110";
constant s0: std_logic_vector(3 downto 0) := "1111";
constant s7: std_logic_vector(3 downto 0) := "0001";
constant s8: std_logic_vector(3 downto 0) := "0110";
constant s6: std_logic_vector(3 downto 0) := "0000";
constant s5: std_logic_vector(3 downto 0) := "1010";
constant s9: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 916259ed08ac3cd9b32ed0f688691a45 | 0.557533 | 3.316286 | false | false | false | false |
chastell/art-decomp | kiss/lion9_rnd.vhd | 1 | 3,346 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion9_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion9_rnd;
architecture behaviour of lion9_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st2: std_logic_vector(3 downto 0) := "1011";
constant st3: std_logic_vector(3 downto 0) := "1110";
constant st4: std_logic_vector(3 downto 0) := "1111";
constant st5: std_logic_vector(3 downto 0) := "0001";
constant st6: std_logic_vector(3 downto 0) := "0110";
constant st7: std_logic_vector(3 downto 0) := "0000";
constant st8: std_logic_vector(3 downto 0) := "1010";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "00") then next_state <= st0; output <= "0";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "10") then next_state <= st1; output <= "0";
elsif std_match(input, "11") then next_state <= st2; output <= "0";
elsif std_match(input, "01") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "10") then next_state <= st5; output <= "1";
elsif std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
end if;
when st7 =>
if std_match(input, "11") then next_state <= st6; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "00") then next_state <= st8; output <= "1";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 7bddc6e11aecd3e07e55e3c9977b7fd8 | 0.575314 | 3.192748 | false | false | false | false |
chastell/art-decomp | kiss/pma_nov.vhd | 1 | 9,226 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pma_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0)
);
end pma_nov;
architecture behaviour of pma_nov is
constant s0: std_logic_vector(4 downto 0) := "00011";
constant s1: std_logic_vector(4 downto 0) := "00000";
constant s2: std_logic_vector(4 downto 0) := "00101";
constant s3: std_logic_vector(4 downto 0) := "10100";
constant s4: std_logic_vector(4 downto 0) := "11010";
constant s5: std_logic_vector(4 downto 0) := "11000";
constant s6: std_logic_vector(4 downto 0) := "01010";
constant s7: std_logic_vector(4 downto 0) := "01011";
constant s8: std_logic_vector(4 downto 0) := "10111";
constant s9: std_logic_vector(4 downto 0) := "10101";
constant s10: std_logic_vector(4 downto 0) := "10000";
constant s11: std_logic_vector(4 downto 0) := "10001";
constant s12: std_logic_vector(4 downto 0) := "00100";
constant s13: std_logic_vector(4 downto 0) := "00010";
constant s14: std_logic_vector(4 downto 0) := "10110";
constant s21: std_logic_vector(4 downto 0) := "11001";
constant s22: std_logic_vector(4 downto 0) := "11101";
constant s23: std_logic_vector(4 downto 0) := "11110";
constant s24: std_logic_vector(4 downto 0) := "11100";
constant s25: std_logic_vector(4 downto 0) := "11111";
constant s26: std_logic_vector(4 downto 0) := "11011";
constant s27: std_logic_vector(4 downto 0) := "00111";
constant s28: std_logic_vector(4 downto 0) := "01100";
constant s30: std_logic_vector(4 downto 0) := "01101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--------";
case current_state is
when s0 =>
if std_match(input, "----1---") then next_state <= s1; output <= "00000000";
elsif std_match(input, "1---01--") then next_state <= s21; output <= "00000000";
end if;
when s1 =>
if std_match(input, "---0---1") then next_state <= s2; output <= "00001000";
elsif std_match(input, "---0--1-") then next_state <= s2; output <= "00001000";
elsif std_match(input, "1--1----") then next_state <= s3; output <= "00001000";
end if;
when s2 =>
if std_match(input, "1--1----") then next_state <= s3; output <= "00000100";
end if;
when s3 =>
if std_match(input, "1--1----") then next_state <= s4; output <= "10000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "10000000";
end if;
when s4 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "01000000";
end if;
when s5 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "11000000";
end if;
when s6 =>
if std_match(input, "1-----01") then next_state <= s0; output <= "00100000";
elsif std_match(input, "1-----1-") then next_state <= s10; output <= "00100000";
end if;
when s7 =>
if std_match(input, "-1--1---") then next_state <= s8; output <= "11101010";
elsif std_match(input, "-1--0--1") then next_state <= s6; output <= "11101010";
elsif std_match(input, "-1--0-1-") then next_state <= s6; output <= "11101010";
end if;
when s8 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01110000";
elsif std_match(input, "---0---1") then next_state <= s9; output <= "01110000";
elsif std_match(input, "---0--1-") then next_state <= s9; output <= "01110000";
end if;
when s9 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11100100";
end if;
when s10 =>
if std_match(input, "1--10--0") then next_state <= s11; output <= "10101100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10101100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10101100";
end if;
when s11 =>
if std_match(input, "-11-0--0") then next_state <= s12; output <= "11111101";
elsif std_match(input, "11-----1") then next_state <= s0; output <= "11111101";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "11111101";
end if;
when s12 =>
if std_match(input, "---00--0") then next_state <= s13; output <= "10111100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10111100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10111100";
end if;
when s13 =>
if std_match(input, "1-------") then next_state <= s14; output <= "11111100";
end if;
when s14 =>
if std_match(input, "1---0--0") then next_state <= s10; output <= "01100000";
elsif std_match(input, "1------1") then next_state <= s0; output <= "01100000";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "01100000";
end if;
when s21 =>
if std_match(input, "1---0-00") then next_state <= s22; output <= "00011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "00011100";
end if;
when s22 =>
if std_match(input, "1---0100") then next_state <= s23; output <= "10011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "10011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "10011100";
end if;
when s23 =>
if std_match(input, "1---0100") then next_state <= s24; output <= "01011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "01011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01011100";
end if;
when s24 =>
if std_match(input, "1---0000") then next_state <= s25; output <= "11011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11011100";
end if;
when s25 =>
if std_match(input, "---10-00") then next_state <= s26; output <= "01111100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111100";
end if;
when s26 =>
if std_match(input, "011---00") then next_state <= s27; output <= "01111101";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111101";
end if;
when s27 =>
if std_match(input, "0--00-00") then next_state <= s28; output <= "11101100";
elsif std_match(input, "1--00-00") then next_state <= s0; output <= "11101100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11101100";
end if;
when s28 =>
if std_match(input, "1-------") then next_state <= s0; output <= "10111000";
end if;
when s30 =>
if std_match(input, "1-------") then next_state <= s0; output <= "00110000";
end if;
when others => next_state <= "-----"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | 75f222f7c2849d1a659d1be7f079e614 | 0.563516 | 3.307996 | false | false | false | false |
chastell/art-decomp | kiss/bbtas_jed.vhd | 1 | 3,027 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbtas_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbtas_jed;
architecture behaviour of bbtas_jed is
constant st0: std_logic_vector(2 downto 0) := "000";
constant st1: std_logic_vector(2 downto 0) := "001";
constant st2: std_logic_vector(2 downto 0) := "100";
constant st3: std_logic_vector(2 downto 0) := "101";
constant st4: std_logic_vector(2 downto 0) := "111";
constant st5: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st1; output <= "00";
elsif std_match(input, "10") then next_state <= st1; output <= "00";
elsif std_match(input, "11") then next_state <= st1; output <= "00";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st2; output <= "00";
elsif std_match(input, "10") then next_state <= st2; output <= "00";
elsif std_match(input, "11") then next_state <= st2; output <= "00";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st1; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "00";
elsif std_match(input, "10") then next_state <= st3; output <= "00";
elsif std_match(input, "11") then next_state <= st3; output <= "00";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st4; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "01";
elsif std_match(input, "10") then next_state <= st3; output <= "10";
elsif std_match(input, "11") then next_state <= st3; output <= "11";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st5; output <= "00";
elsif std_match(input, "01") then next_state <= st4; output <= "00";
elsif std_match(input, "10") then next_state <= st4; output <= "00";
elsif std_match(input, "11") then next_state <= st4; output <= "00";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st5; output <= "00";
elsif std_match(input, "10") then next_state <= st5; output <= "00";
elsif std_match(input, "11") then next_state <= st5; output <= "00";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 036b75e624157117dba73a65364f9454 | 0.582094 | 3.230523 | false | false | false | false |
chastell/art-decomp | kiss/modulo12_nov.vhd | 1 | 3,524 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity modulo12_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end modulo12_nov;
architecture behaviour of modulo12_nov is
constant st0: std_logic_vector(3 downto 0) := "0000";
constant st1: std_logic_vector(3 downto 0) := "1111";
constant st2: std_logic_vector(3 downto 0) := "0001";
constant st3: std_logic_vector(3 downto 0) := "1110";
constant st4: std_logic_vector(3 downto 0) := "0010";
constant st5: std_logic_vector(3 downto 0) := "1101";
constant st6: std_logic_vector(3 downto 0) := "0011";
constant st7: std_logic_vector(3 downto 0) := "1100";
constant st8: std_logic_vector(3 downto 0) := "0100";
constant st9: std_logic_vector(3 downto 0) := "1011";
constant st10: std_logic_vector(3 downto 0) := "0101";
constant st11: std_logic_vector(3 downto 0) := "1010";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st1; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st4; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st5; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st6; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st7; output <= "0";
elsif std_match(input, "1") then next_state <= st8; output <= "0";
end if;
when st8 =>
if std_match(input, "0") then next_state <= st8; output <= "0";
elsif std_match(input, "1") then next_state <= st9; output <= "0";
end if;
when st9 =>
if std_match(input, "0") then next_state <= st9; output <= "0";
elsif std_match(input, "1") then next_state <= st10; output <= "0";
end if;
when st10 =>
if std_match(input, "0") then next_state <= st10; output <= "0";
elsif std_match(input, "1") then next_state <= st11; output <= "0";
end if;
when st11 =>
if std_match(input, "0") then next_state <= st11; output <= "0";
elsif std_match(input, "1") then next_state <= st0; output <= "0";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | f8ae21f169b25d210f54e5804bbf9649 | 0.571226 | 3.180505 | false | false | false | false |
chastell/art-decomp | kiss/modulo12_rnd.vhd | 1 | 3,524 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity modulo12_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end modulo12_rnd;
architecture behaviour of modulo12_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st2: std_logic_vector(3 downto 0) := "1011";
constant st3: std_logic_vector(3 downto 0) := "1110";
constant st4: std_logic_vector(3 downto 0) := "1111";
constant st5: std_logic_vector(3 downto 0) := "0001";
constant st6: std_logic_vector(3 downto 0) := "0110";
constant st7: std_logic_vector(3 downto 0) := "0000";
constant st8: std_logic_vector(3 downto 0) := "1010";
constant st9: std_logic_vector(3 downto 0) := "1000";
constant st10: std_logic_vector(3 downto 0) := "0100";
constant st11: std_logic_vector(3 downto 0) := "1001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st1; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st4; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st5; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st6; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st7; output <= "0";
elsif std_match(input, "1") then next_state <= st8; output <= "0";
end if;
when st8 =>
if std_match(input, "0") then next_state <= st8; output <= "0";
elsif std_match(input, "1") then next_state <= st9; output <= "0";
end if;
when st9 =>
if std_match(input, "0") then next_state <= st9; output <= "0";
elsif std_match(input, "1") then next_state <= st10; output <= "0";
end if;
when st10 =>
if std_match(input, "0") then next_state <= st10; output <= "0";
elsif std_match(input, "1") then next_state <= st11; output <= "0";
end if;
when st11 =>
if std_match(input, "0") then next_state <= st11; output <= "0";
elsif std_match(input, "1") then next_state <= st0; output <= "0";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 6b5c0b37017b33c47fd6dd638856bd2c | 0.571226 | 3.180505 | false | false | false | false |
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