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es17m014/vhdl-counter | src/old/vhdl/debouncer.vhd | 1 | 2,216 | -- --------------------------------------------------------------
-- Title : Debounce Logic
-- Project : Counter
-- -------- ------------------------------------------------------
-- File : debounce.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 31.10.2017
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description : Debounce input signals from switches and buttons
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 31.10.2017 1.0 Martin Angermair https://eewiki.net/pages/viewpage.action?pageId=4980758
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debouncer is
generic(
counter_size : integer := 100);
port(
clk_i : in std_logic; --input clock
reset_i : in std_logic; --input reset
btn_i : in std_logic; --input signal to be debounced
deb_o : out std_logic); --debounced signal
end debouncer;
architecture rtl of debouncer is
signal ff : std_logic_vector(1 downto 0) := (others => '0'); --input flip flops and initialize
signal counter_reset : std_logic; --sync reset to zero
signal counter : integer range 0 to counter_size := 0; --counter output
begin
counter_reset <= ff(0) xor ff(1); --determine when to start/reset counter
process(clk_i, reset_i)
begin
if reset_i = '1' then
counter <= 0;
ff <= (others => '0');
counter <= 0;
elsif(rising_edge(clk_i)) then
ff(1) <= ff(0);
ff(0) <= btn_i;
if(counter_reset = '1') then --reset counter because input is changing
counter <= 0;
elsif(counter < counter_size) then --stable input time is not yet met
counter <= counter + 1;
else --stable input time is met
deb_o <= ff(1);
end if;
end if;
end process;
end rtl;
| mit | c646f7d18b632b34593ef9312df36e63 | 0.472473 | 4.261538 | false | false | false | false |
chastell/art-decomp | kiss/ex6_rnd.vhd | 1 | 4,231 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_rnd;
architecture behaviour of ex6_rnd is
constant s1: std_logic_vector(2 downto 0) := "101";
constant s3: std_logic_vector(2 downto 0) := "010";
constant s2: std_logic_vector(2 downto 0) := "011";
constant s4: std_logic_vector(2 downto 0) := "110";
constant s5: std_logic_vector(2 downto 0) := "111";
constant s6: std_logic_vector(2 downto 0) := "001";
constant s7: std_logic_vector(2 downto 0) := "000";
constant s8: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "---"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | 24976003513a4c812693efadb0a30e69 | 0.579532 | 3.379393 | false | false | false | false |
chastell/art-decomp | kiss/s1_hot.vhd | 1 | 12,154 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_hot;
architecture behaviour of s1_hot is
constant st0: std_logic_vector(19 downto 0) := "10000000000000000000";
constant st1: std_logic_vector(19 downto 0) := "01000000000000000000";
constant st2: std_logic_vector(19 downto 0) := "00100000000000000000";
constant st5: std_logic_vector(19 downto 0) := "00010000000000000000";
constant st3: std_logic_vector(19 downto 0) := "00001000000000000000";
constant st4: std_logic_vector(19 downto 0) := "00000100000000000000";
constant st6: std_logic_vector(19 downto 0) := "00000010000000000000";
constant st7: std_logic_vector(19 downto 0) := "00000001000000000000";
constant st12: std_logic_vector(19 downto 0) := "00000000100000000000";
constant st13: std_logic_vector(19 downto 0) := "00000000010000000000";
constant st8: std_logic_vector(19 downto 0) := "00000000001000000000";
constant st11: std_logic_vector(19 downto 0) := "00000000000100000000";
constant st15: std_logic_vector(19 downto 0) := "00000000000010000000";
constant st9: std_logic_vector(19 downto 0) := "00000000000001000000";
constant st10: std_logic_vector(19 downto 0) := "00000000000000100000";
constant st14: std_logic_vector(19 downto 0) := "00000000000000010000";
constant st16: std_logic_vector(19 downto 0) := "00000000000000001000";
constant st17: std_logic_vector(19 downto 0) := "00000000000000000100";
constant st18: std_logic_vector(19 downto 0) := "00000000000000000010";
constant st19: std_logic_vector(19 downto 0) := "00000000000000000001";
signal current_state, next_state: std_logic_vector(19 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "--------------------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 4132c496f05bb28c711e40987af2b80f | 0.575119 | 3.39213 | false | false | false | false |
chastell/art-decomp | kiss/mc_jed.vhd | 1 | 1,790 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mc_jed is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end mc_jed;
architecture behaviour of mc_jed is
constant HG: std_logic_vector(1 downto 0) := "00";
constant HY: std_logic_vector(1 downto 0) := "10";
constant FG: std_logic_vector(1 downto 0) := "11";
constant FY: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when HG =>
if std_match(input, "0--") then next_state <= HG; output <= "00010";
elsif std_match(input, "-0-") then next_state <= HG; output <= "00010";
elsif std_match(input, "11-") then next_state <= HY; output <= "10010";
end if;
when HY =>
if std_match(input, "--0") then next_state <= HY; output <= "00110";
elsif std_match(input, "--1") then next_state <= FG; output <= "10110";
end if;
when FG =>
if std_match(input, "10-") then next_state <= FG; output <= "01000";
elsif std_match(input, "0--") then next_state <= FY; output <= "11000";
elsif std_match(input, "-1-") then next_state <= FY; output <= "11000";
end if;
when FY =>
if std_match(input, "--0") then next_state <= FY; output <= "01001";
elsif std_match(input, "--1") then next_state <= HG; output <= "11001";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | e3903fd0e37d594e2807d7b1b090bb4d | 0.584916 | 3.396584 | false | false | false | false |
chastell/art-decomp | kiss/s1494_hot.vhd | 1 | 33,509 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_hot;
architecture behaviour of s1494_hot is
constant s000000: std_logic_vector(47 downto 0) := "100000000000000000000000000000000000000000000000";
constant s001110: std_logic_vector(47 downto 0) := "010000000000000000000000000000000000000000000000";
constant s011000: std_logic_vector(47 downto 0) := "001000000000000000000000000000000000000000000000";
constant s010000: std_logic_vector(47 downto 0) := "000100000000000000000000000000000000000000000000";
constant s010100: std_logic_vector(47 downto 0) := "000010000000000000000000000000000000000000000000";
constant s110011: std_logic_vector(47 downto 0) := "000001000000000000000000000000000000000000000000";
constant s010011: std_logic_vector(47 downto 0) := "000000100000000000000000000000000000000000000000";
constant s000100: std_logic_vector(47 downto 0) := "000000010000000000000000000000000000000000000000";
constant s010111: std_logic_vector(47 downto 0) := "000000001000000000000000000000000000000000000000";
constant s010110: std_logic_vector(47 downto 0) := "000000000100000000000000000000000000000000000000";
constant s100011: std_logic_vector(47 downto 0) := "000000000010000000000000000000000000000000000000";
constant s001100: std_logic_vector(47 downto 0) := "000000000001000000000000000000000000000000000000";
constant s011011: std_logic_vector(47 downto 0) := "000000000000100000000000000000000000000000000000";
constant s010001: std_logic_vector(47 downto 0) := "000000000000010000000000000000000000000000000000";
constant s100110: std_logic_vector(47 downto 0) := "000000000000001000000000000000000000000000000000";
constant s011101: std_logic_vector(47 downto 0) := "000000000000000100000000000000000000000000000000";
constant s101110: std_logic_vector(47 downto 0) := "000000000000000010000000000000000000000000000000";
constant s010101: std_logic_vector(47 downto 0) := "000000000000000001000000000000000000000000000000";
constant s111110: std_logic_vector(47 downto 0) := "000000000000000000100000000000000000000000000000";
constant s000011: std_logic_vector(47 downto 0) := "000000000000000000010000000000000000000000000000";
constant s111011: std_logic_vector(47 downto 0) := "000000000000000000001000000000000000000000000000";
constant s011010: std_logic_vector(47 downto 0) := "000000000000000000000100000000000000000000000000";
constant s111010: std_logic_vector(47 downto 0) := "000000000000000000000010000000000000000000000000";
constant s100111: std_logic_vector(47 downto 0) := "000000000000000000000001000000000000000000000000";
constant s110010: std_logic_vector(47 downto 0) := "000000000000000000000000100000000000000000000000";
constant s100000: std_logic_vector(47 downto 0) := "000000000000000000000000010000000000000000000000";
constant s011100: std_logic_vector(47 downto 0) := "000000000000000000000000001000000000000000000000";
constant s101010: std_logic_vector(47 downto 0) := "000000000000000000000000000100000000000000000000";
constant s100010: std_logic_vector(47 downto 0) := "000000000000000000000000000010000000000000000000";
constant s101000: std_logic_vector(47 downto 0) := "000000000000000000000000000001000000000000000000";
constant s011110: std_logic_vector(47 downto 0) := "000000000000000000000000000000100000000000000000";
constant s110000: std_logic_vector(47 downto 0) := "000000000000000000000000000000010000000000000000";
constant s010010: std_logic_vector(47 downto 0) := "000000000000000000000000000000001000000000000000";
constant s001010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000100000000000000";
constant s100100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000010000000000000";
constant s111000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000001000000000000";
constant s001011: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000100000000000";
constant s110100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000010000000000";
constant s001000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000001000000000";
constant s000010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000100000000";
constant s000111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000010000000";
constant s101011: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000001000000";
constant s001111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000100000";
constant s000110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000010000";
constant s110110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000001000";
constant s011111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000100";
constant s111100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000010";
constant s101100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(47 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------------------------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------------------------------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | bbedde17d827817eff5ceb756a9153c2 | 0.647319 | 4.068107 | false | false | false | false |
TheMassController/VHDL_experimenting | project/bus/test/bus_demux_tb.vhd | 1 | 6,131 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
library src;
use src.bus_pkg.all;
library tb;
use tb.bus_tb_pkg.all;
entity bus_demux_tb is
generic (
runner_cfg : string);
end entity;
architecture tb of bus_demux_tb is
constant clk_period : time := 20 ns;
constant firstRange : addr_range_and_mapping_type := address_range_and_map(
low => std_logic_vector(to_unsigned(0, bus_address_type'length)),
high => std_logic_vector(to_unsigned(15, bus_address_type'length))
);
constant secondRangeMap : addrMapping_type := bus_map_constant(bus_address_type'high - 4, '0') & bus_map_range(4, 0);
constant secondRange : addr_range_and_mapping_type := address_range_and_map(
low => std_logic_vector(to_unsigned(32, bus_address_type'length)),
high => std_logic_vector(to_unsigned(63, bus_address_type'length)),
mapping => secondRangeMap
);
signal demux2firstSlave : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal demux2secondSlave : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal firstSlave2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal secondSlave2demux : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal demux2master : bus_slv2mst_type := BUS_SLV2MST_IDLE;
signal master2demux : bus_mst2slv_type := BUS_MST2SLV_IDLE;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal helper_master : bus_mst2slv_type := BUS_MST2SLV_IDLE;
begin
clk <= not clk after (clk_period/2);
main : process
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Complete run") then
master2demux <= bus_tb_mst2slv(address => 10, readEnable => '1');
wait for clk_period/4;
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2firstSlave = master2demux);
firstSlave2demux.ack <= '1';
firstSlave2demux.readData <= std_logic_vector(to_unsigned(34, bus_data_type'length));
wait for clk_period/4;
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2firstSlave = master2demux);
check(demux2master = firstSlave2demux);
master2demux <= BUS_MST2SLV_IDLE;
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2master = BUS_SLV2MST_IDLE);
firstSlave2demux <= BUS_SLV2MST_IDLE;
master2demux <= bus_tb_mst2slv(address => 40, writeEnable => '1');
helper_master <= bus_tb_mst2slv(address => 8, writeEnable => '1');
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = helper_master);
check(demux2master = BUS_SLV2MST_IDLE);
secondSlave2demux.fault <= '1';
secondSlave2demux.readData <= std_logic_vector(to_unsigned(14, bus_data_type'length));
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = helper_master);
check(demux2master = secondSlave2demux);
master2demux <= BUS_MST2SLV_IDLE;
helper_master <= BUS_MST2SLV_IDLE;
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2master = BUS_SLV2MST_IDLE);
secondSlave2demux <= BUS_SLV2MST_IDLE;
master2demux <= bus_tb_mst2slv(address => 50, readEnable => '1');
helper_master <= bus_tb_mst2slv(address => 18, readEnable => '1');
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = helper_master);
check(demux2master = BUS_SLV2MST_IDLE);
secondSlave2demux.ack <= '1';
secondSlave2demux.readData <= std_logic_vector(to_unsigned(45, bus_data_type'length));
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = helper_master);
check(demux2master = secondSlave2demux);
master2demux <= BUS_MST2SLV_IDLE;
helper_master <= BUS_MST2SLV_IDLE;
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2master = BUS_SLV2MST_IDLE);
master2demux <= bus_tb_mst2slv(address => 20, readEnable => '1');
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2master.fault = '1');
for i in bus_address_type'range loop
check(demux2master.readData(i) = '1');
end loop;
rst <= '1';
wait for clk_period/4;
check(demux2firstSlave = BUS_MST2SLV_IDLE);
check(demux2secondSlave = BUS_MST2SLV_IDLE);
check(demux2master = BUS_SLV2MST_IDLE);
end if;
end loop;
wait until rising_edge(clk) or falling_edge(clk);
test_runner_cleanup(runner);
wait;
end process;
demux : entity src.bus_demux
generic map (
ADDRESS_MAP(0) => firstRange,
ADDRESS_MAP(1) => secondRange
)
port map (
rst => rst,
mst2demux => master2demux,
demux2mst => demux2master,
demux2slv(0) => demux2firstSlave,
demux2slv(1) => demux2secondSlave,
slv2demux(0) => firstSlave2demux,
slv2demux(1) => secondSlave2demux
);
end architecture;
| mit | 45b7126d1d15271c3306e94efefd9bd9 | 0.583102 | 3.782233 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-08A1.vhd | 1 | 7,899 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-08A1.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock generator - 4 phase (T1,T2,T3,T4 and P1,P2,P3,P4)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Add registers to all clock outputs and delay rising edge of Px and Tx clocks
---------------------------------------------------------------------------
library IEEE;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Gates_package.all;
use work.all;
entity Clock is Port (
-- Clock stuff
CLOCK_IN : in std_logic;
T1,T2,T3,T4 : out std_logic;
P1,P2,P3,P4 : out std_logic;
OSC_T_LINE : out std_logic; -- 12A
M_CONV_OSC : out std_logic; -- 03C
P_CONV_OSC : out std_logic; -- 03D,03C
M_CONV_OSC_2 : out std_logic; -- 03C
CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B
CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D
CLOCK_START : in std_logic; -- 03C
MACH_RST_3 : in std_logic; -- 03D
Sw_Slow : in std_logic -- '1' to run slow
);
end Clock;
architecture FMD of Clock is
-- Following 2 lines to run clock at 5.33MHz (standard)
-- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0);
subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0);
constant RATIOFast : DividerSize := "00000000000000000000001000"; -- 5 gives 10MHz => 720ns cycle
-- Following 2 lines to run clock at 5Hz
constant RATIOSlow : DividerSize := "00100010010101010001000000"; -- 5M gives 10Hz => 720ms cycle
constant ZERO : DividerSize := (others=>'0');
constant ONE : DividerSize := (0=>'1',others=>'0');
signal DIVIDER : DividerSize := (others=>'0');
signal DIVIDER_MAX : DividerSize;
signal OSC2,OSC,M_DLYD_OSC,DLYN_OSC,T1A,T2A,T3A,T4A,OSC2_DLYD : STD_LOGIC := '0';
-- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4);
signal CLK : STD_LOGIC_VECTOR(1 to 4) := "0001";
signal P1D,P2D,P3D,P4D : STD_LOGIC;
signal OSC_T_LINEA, CLOCK_ONA, CLOCK_OFFA, P_CONV_OSCA,M_CONV_OSC_2A, N_OSC : STD_LOGIC;
begin
-- Divide the 50MHz FPGA clock down
-- 1.5us storage cycle means T1-4 takes 750ns, or 1.33MHz
-- The clock to generate the four phases is therefore 2.66MHz
-- OSC2 is actually double the original oscillator (5.33MHz) as only one edge is used
DIVIDER_MAX <= RatioSlow when Sw_Slow='1' else RATIOFast;
OSC2 <= '1' when DIVIDER > '0' & DIVIDER_MAX(DIVIDER_MAX'left downto 1) else '0';
N_OSC <= not OSC;
process (CLOCK_IN)
begin
if CLOCK_IN'event and CLOCK_IN='1' then
if DIVIDER>=DIVIDER_MAX then
DIVIDER <= ZERO;
else
DIVIDER <= DIVIDER + ONE;
end if;
end if;
end process;
-- AC1K6,AC1C6 Probably have to re-do this lot to get it work
--SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4);
--SETS(2) <= DLYD_OSC not CLK(4) and CLK(1);
--SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2);
--SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1';
--RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1';
--RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1';
--RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1';
--RSTS(4) <= OSC and CLK(1);
--FLV(SETS,RSTS,CLK); -- AC1C6
-- The following process forms a ring counter
-- MACH_RST_3 forces the counter to 0001
-- If CLOCK_START is false, the counter stays at 0001
-- When CLOCK_START goes true, the counter cycles through
-- 0001 0001 0001 1001 1100 0110 0011 1001 1100 ....
-- When CLOCK_START subsequently goes false, the sequence continues
-- until reaching 0011, after which it stays at 0001
-- ... 1001 1100 0110 0011 0001 0001 0001 ...
-- The original counter used a level-triggered implementation, driven by
-- both levels of the OSC signal. Here it is easier to make it edge triggered
-- which requires a clock of twice the frequency, hence OSC2
process (OSC2, MACH_RST_3, CLOCK_START)
begin
if OSC2'event and OSC2='1' then
if OSC='0' then -- OSC Rising edge: +P1 (P4=1 & START) -P3 (P4=1) or -P1 +P3 (P2=1)
OSC <= '1';
if CLK(2)='1' or MACH_RST_3='1' then
CLK(1) <= '0';
elsif CLOCK_START='1' and CLK(4)='1' then
CLK(1) <= '1';
end if;
if CLK(4)='1' or MACH_RST_3='1' then
CLK(3) <= '0';
elsif CLK(2)='1' then
CLK(3) <= '1';
end if;
else -- OSC Falling edge: +P2 -P4 (P1=1) or -P2 +P4 (P3=1)
OSC <= '0';
if CLK(3)='1' or MACH_RST_3='1' then
CLK(2) <= '0';
elsif CLK(1)='1' then
CLK(2) <= '1';
end if;
if CLK(3)='1' or MACH_RST_3='1' then
CLK(4) <= '1';
elsif CLK(1)='1' then
CLK(4) <= '0';
end if;
end if;
end if;
end process;
OSC_T_LINEA <= OSC; -- AC1B6
OSC_T_LINED : FDCE port map(D=>OSC_T_LINEA,Q=>OSC_T_LINE,CE=>'1',C=>CLOCK_IN,CLR=>'0');
M_CONV_OSCD : FDCE port map(D=>N_OSC,Q=>M_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0'); -- AC1C6
M_DLYD_OSC <= not OSC; -- AC1C6
DLYN_OSC <= OSC; -- AC1C6
-- P1 <= CLK(1);
-- P2 <= CLK(2);
-- P3 <= CLK(3);
-- P4 <= CLK(4);
-- Delay the rising edge of each P pulse to ensure that the T pulses never overlap
P1DLY: entity DelayRisingEdgeX port map (D=>CLK(1),CLK=>CLOCK_IN,Q=>P1D);
P2DLY: entity DelayRisingEdgeX port map (D=>CLK(2),CLK=>CLOCK_IN,Q=>P2D);
P3DLY: entity DelayRisingEdgeX port map (D=>CLK(3),CLK=>CLOCK_IN,Q=>P3D);
P4DLY: entity DelayRisingEdgeX port map (D=>CLK(4),CLK=>CLOCK_IN,Q=>P4D);
T1A <= P4D and P1D;
T2A <= P1D and P2D;
T3A <= P2D and P3D;
T4A <= P3D and P4D;
T1D : FDCE port map(D=>T1A,Q=>T1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T2D : FDCE port map(D=>T2A,Q=>T2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T3D : FDCE port map(D=>T3A,Q=>T3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
T4D : FDCE port map(D=>T4A,Q=>T4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P1C : FDCE port map(D=>P1D,Q=>P1,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P2C : FDCE port map(D=>P2D,Q=>P2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P3C : FDCE port map(D=>P3D,Q=>P3,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P4C : FDCE port map(D=>P4D,Q=>P4,CE=>'1',C=>CLOCK_IN,CLR=>'0');
CLOCK_ONA <= CLK(1) or CLK(2) or CLK(3);
CLOCK_OND : FDCE port map(D=>CLOCK_ONA,Q=>CLOCK_ON,CE=>'1',C=>CLOCK_IN,CLR=>'0');
CLOCK_OFFA <= not CLOCK_ONA;
CLOCK_OFFD : FDCE port map(D=>CLOCK_OFFA,Q=>CLOCK_OFF,CE=>'1',C=>CLOCK_IN,CLR=>'0');
P_CONV_OSCA <= OSC and CLOCK_OFFA;
P_CONV_OSCD : FDCE port map(D=>P_CONV_OSCA,Q=>P_CONV_OSC,CE=>'1',C=>CLOCK_IN,CLR=>'0');
M_CONV_OSC_2A <= not(P_CONV_OSCA);
M_CONV_OSC_2D : FDCE port map(D=>M_CONV_OSC_2A,Q=>M_CONV_OSC_2,CE=>'1',C=>CLOCK_IN,CLR=>'0');
end FMD;
| gpl-3.0 | 154f910e9dc1c19250c1bced14398040 | 0.620205 | 2.706064 | false | false | false | false |
TheMassController/VHDL_experimenting | project/SPI/spi_tb.vhd | 1 | 12,925 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.txt_util.all;
use IEEE.numeric_std.ALL;
use IEEE.math_real.ALL;
entity spi_tb is
generic (
clock_period : time;
randVal : natural
);
port (
clk : in STD_LOGIC;
done : out boolean;
success : out boolean
);
end spi_tb;
architecture Behavioral of spi_tb is
constant sclk_period : time := clock_period * 2; -- Run eight times slower than the system clock
constant FRAME_SIZE_L2 : natural := 5;
constant FRAME_SIZE : natural := 2**FRAME_SIZE_L2;
-- inout signals slave 1
signal slave_1_rst : STD_LOGIC;
signal slave_1_sclk : STD_LOGIC;
signal slave_1_mosi : STD_LOGIC;
signal slave_1_miso : STD_LOGIC;
signal slave_1_ss : STD_LOGIC;
signal slave_1_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_1_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_1_done : boolean;
-- meta signals slave 1
signal spi_slave_1_done : boolean;
signal spi_slave_1_suc : boolean := true;
-- inout signals slave 2
signal slave_2_rst : STD_LOGIC;
signal slave_2_sclk : STD_LOGIC;
signal slave_2_mosi : STD_LOGIC;
signal slave_2_miso : STD_LOGIC;
signal slave_2_ss : STD_LOGIC;
signal slave_2_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_2_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_2_done : boolean;
-- meta signals slave 2
signal spi_slave_2_done : boolean;
signal spi_slave_2_suc : boolean := true;
-- inout signals slave 3
signal slave_3_rst : STD_LOGIC;
signal slave_3_sclk : STD_LOGIC;
signal slave_3_mosi : STD_LOGIC;
signal slave_3_miso : STD_LOGIC;
signal slave_3_ss : STD_LOGIC;
signal slave_3_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_3_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_3_done : boolean;
-- meta signals slave 3
signal spi_slave_3_done : boolean;
signal spi_slave_3_suc : boolean := true;
-- inout signals slave 4
signal slave_4_rst : STD_LOGIC;
signal slave_4_sclk : STD_LOGIC;
signal slave_4_mosi : STD_LOGIC;
signal slave_4_miso : STD_LOGIC;
signal slave_4_ss : STD_LOGIC;
signal slave_4_data_in : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_4_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
signal slave_4_done : boolean;
-- meta signals slave 4
signal spi_slave_4_done : boolean;
signal spi_slave_4_suc : boolean := true;
begin
success <= spi_slave_1_suc and spi_slave_2_suc and spi_slave_3_suc and spi_slave_4_suc;
done <= spi_slave_1_done and spi_slave_2_done and spi_slave_3_done and spi_slave_4_done;
-- Frame size 16 bit
-- SPO = SPH = 0
spi_slave_1 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2
)
port map (
rst => slave_1_rst,
clk => clk,
sclk => slave_1_sclk,
mosi => slave_1_mosi,
miso => slave_1_miso,
ss => slave_1_ss,
trans_data => slave_1_data_in,
receiv_data => slave_1_data_out,
done => slave_1_done
);
-- Frame size 16 bit
spi_slave_2 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2,
POLARITY => '1',
PHASE => '0'
)
port map (
rst => slave_2_rst,
clk => clk,
sclk => slave_2_sclk,
mosi => slave_2_mosi,
miso => slave_2_miso,
ss => slave_2_ss,
trans_data => slave_2_data_in,
receiv_data => slave_2_data_out,
done => slave_2_done
);
-- Frame size 16 bit
spi_slave_3 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2,
POLARITY => '0',
PHASE => '1'
)
port map (
rst => slave_3_rst,
clk => clk,
sclk => slave_3_sclk,
mosi => slave_3_mosi,
miso => slave_3_miso,
ss => slave_3_ss,
trans_data => slave_3_data_in,
receiv_data => slave_3_data_out,
done => slave_3_done
);
-- Frame size 16 bit
spi_slave_4 : entity work.spi_slave
generic map (
FRAME_SIZE_BIT_L2 => FRAME_SIZE_L2,
POLARITY => '1',
PHASE => '1'
)
port map (
rst => slave_4_rst,
clk => clk,
sclk => slave_4_sclk,
mosi => slave_4_mosi,
miso => slave_4_miso,
ss => slave_4_ss,
trans_data => slave_4_data_in,
receiv_data => slave_4_data_out,
done => slave_4_done
);
slave_1_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_1_rst <= '1';
slave_1_ss <= '0';
slave_1_sclk <= '0';
slave_1_data_in <= (others => '0');
slave_1_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_1_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_1_data_in <= cur_data_out;
-- Pre set
slave_1_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 2 downto 0 loop
-- Get/read
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
assert(slave_1_miso = cur_data_out(B + 1));
-- Set/write
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
slave_1_mosi <= cur_data_out(B);
end loop;
-- End the loop prematurely, since the last set is not actually a set, since we are already out of data
-- Get/read
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
assert(slave_1_miso = cur_data_out(0));
-- Finishing edge
wait for sclk_period/2;
slave_1_sclk <= not slave_1_sclk;
slave_1_mosi <= '0';
wait for (1.5)*clock_period;
assert slave_1_done = true;
assert(slave_1_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_1_sclk <= '0';
spi_slave_1_done <= true;
report "SPI slave 1 tests done" severity note;
wait;
end process;
slave_2_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_2_rst <= '1';
slave_2_ss <= '0';
slave_2_sclk <= '1';
slave_2_data_in <= (others => '0');
slave_2_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_2_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_2_data_in <= cur_data_out;
-- Pre set
slave_2_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 1 downto 0 loop
-- Set/write
wait for sclk_period/2;
slave_2_sclk <= not slave_2_sclk;
slave_2_mosi <= cur_data_out(B);
-- Get/read
wait for sclk_period/2;
slave_2_sclk <= not slave_2_sclk;
assert(slave_2_miso = cur_data_out(B));
end loop;
wait for (1.5)*clock_period;
assert slave_2_done = true;
assert(slave_2_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_2_sclk <= '0';
spi_slave_2_done <= true;
report "SPI slave 2 tests done" severity note;
wait;
end process;
slave_3_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_3_rst <= '1';
slave_3_ss <= '0';
slave_3_sclk <= '0';
slave_3_data_in <= (others => '0');
slave_3_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_3_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_3_data_in <= cur_data_out;
-- Pre set
slave_3_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 1 downto 0 loop
-- Set/write
wait for sclk_period/2;
slave_3_sclk <= not slave_3_sclk;
slave_3_mosi <= cur_data_out(B);
-- Get/read
wait for sclk_period/2;
slave_3_sclk <= not slave_3_sclk;
assert(slave_3_miso = cur_data_out(B));
end loop;
slave_3_sclk <= not slave_3_sclk;
wait for (1.5)*clock_period;
assert slave_3_done = true;
assert(slave_3_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_3_sclk <= '0';
spi_slave_3_done <= true;
report "SPI slave 3 tests done" severity note;
wait;
end process;
slave_4_test : process
variable cur_data_out : STD_LOGIC_VECTOR(FRAME_SIZE - 1 downto 0);
begin
slave_4_rst <= '1';
slave_4_ss <= '0';
slave_4_sclk <= '1';
slave_4_data_in <= (others => '0');
slave_4_mosi <= '0';
wait for clock_period/2;
-- Easy opener, run the values 0-15 trough both in- and output and see if it works as expected. 0 is selected already
-- Wait for 2 cycles
wait for 2*clock_period;
-- Drop the reset
slave_4_rst <= '0';
-- Wait for 2 cycles
wait for 2*clock_period;
for D in 1 to 3 loop
cur_data_out := STD_LOGIC_VECTOR(to_unsigned(D, cur_data_out'length));
-- The system should be waiting for the first sclk, after which it tries to read data
slave_4_data_in <= cur_data_out;
-- Pre set
slave_4_mosi <= cur_data_out(FRAME_SIZE - 1);
for B in FRAME_SIZE - 2 downto 0 loop
-- Get/read
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
assert(slave_4_miso = cur_data_out(B + 1));
-- Set/write
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
slave_4_mosi <= cur_data_out(B);
end loop;
-- End the loop prematurely, since the last set is not actually a set, since we are already out of data
-- Get/read
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
assert(slave_4_miso = cur_data_out(0));
-- Finishing edge
wait for sclk_period/2;
slave_4_sclk <= not slave_4_sclk;
slave_4_mosi <= '0';
wait for (1.5)*clock_period;
assert slave_4_done = true;
assert(slave_4_data_out = std_logic_vector(to_unsigned(D, slave_1_data_out'LENGTH)));
wait for sclk_period - (1.5)*clock_period;
wait for sclk_period;
end loop;
slave_4_sclk <= '0';
spi_slave_4_done <= true;
report "SPI slave 4 tests done" severity note;
wait;
end process;
end Behavioral;
| mit | 961d9f65ba2e39c92eda64120c048a0e | 0.533849 | 3.51988 | false | false | false | false |
chastell/art-decomp | kiss/mc_nov.vhd | 1 | 1,790 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mc_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end mc_nov;
architecture behaviour of mc_nov is
constant HG: std_logic_vector(1 downto 0) := "00";
constant HY: std_logic_vector(1 downto 0) := "11";
constant FG: std_logic_vector(1 downto 0) := "01";
constant FY: std_logic_vector(1 downto 0) := "10";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when HG =>
if std_match(input, "0--") then next_state <= HG; output <= "00010";
elsif std_match(input, "-0-") then next_state <= HG; output <= "00010";
elsif std_match(input, "11-") then next_state <= HY; output <= "10010";
end if;
when HY =>
if std_match(input, "--0") then next_state <= HY; output <= "00110";
elsif std_match(input, "--1") then next_state <= FG; output <= "10110";
end if;
when FG =>
if std_match(input, "10-") then next_state <= FG; output <= "01000";
elsif std_match(input, "0--") then next_state <= FY; output <= "11000";
elsif std_match(input, "-1-") then next_state <= FY; output <= "11000";
end if;
when FY =>
if std_match(input, "--0") then next_state <= FY; output <= "01001";
elsif std_match(input, "--1") then next_state <= HG; output <= "11001";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 630023d22533128f4f48b5a14d741c4b | 0.584916 | 3.396584 | false | false | false | false |
chastell/art-decomp | kiss/donfile_nov.vhd | 1 | 10,163 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity donfile_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end donfile_nov;
architecture behaviour of donfile_nov is
constant st0: std_logic_vector(4 downto 0) := "01110";
constant st1: std_logic_vector(4 downto 0) := "01100";
constant st2: std_logic_vector(4 downto 0) := "10111";
constant st3: std_logic_vector(4 downto 0) := "00111";
constant st4: std_logic_vector(4 downto 0) := "01101";
constant st5: std_logic_vector(4 downto 0) := "00101";
constant st6: std_logic_vector(4 downto 0) := "01011";
constant st7: std_logic_vector(4 downto 0) := "01111";
constant st8: std_logic_vector(4 downto 0) := "11011";
constant st9: std_logic_vector(4 downto 0) := "11000";
constant st10: std_logic_vector(4 downto 0) := "01010";
constant st11: std_logic_vector(4 downto 0) := "01000";
constant st12: std_logic_vector(4 downto 0) := "11110";
constant st13: std_logic_vector(4 downto 0) := "10101";
constant st14: std_logic_vector(4 downto 0) := "01001";
constant st15: std_logic_vector(4 downto 0) := "10001";
constant st16: std_logic_vector(4 downto 0) := "10100";
constant st17: std_logic_vector(4 downto 0) := "00001";
constant st18: std_logic_vector(4 downto 0) := "11100";
constant st19: std_logic_vector(4 downto 0) := "00110";
constant st20: std_logic_vector(4 downto 0) := "00011";
constant st21: std_logic_vector(4 downto 0) := "00010";
constant st22: std_logic_vector(4 downto 0) := "00100";
constant st23: std_logic_vector(4 downto 0) := "00000";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st6 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st8 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st9 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st10 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st11 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st12 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st13 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st14 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st15 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st16 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st17 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st18 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st19 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st20 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st21 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st22 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st23 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when others => next_state <= "-----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | fc3ac15d55c1e444cb2998491584c5e1 | 0.568926 | 3.207005 | false | false | false | false |
caiopo/battleship-vhdl | src/ROM.vhd | 1 | 2,119 |
-- Esse exemplo de descricao de memoria ROM em VHDL foi obtido no
-- site: http://www.edaboard.com/thread38052.html
--
-- Esse site foi encontrado ao se realizar uma busca no google com
-- a expressao (sem aspas): ROM VHDL
--
-- O exemplo original do site foi adaptado (pequenas modificacoes) para
-- se adequar a especificacao do trabalho pratico da disciplina de
-- Circuitos e Tecnicas Digitais, semestre 2015/1. Podem ser necessarias
-- modificacoes adicionais.
--
-- Esse exemplo foi compilado e simulado utilizando a ferramenta on-line:
-- http://www.edaplayground.com/
--
-- Nao foi testado com o Quartus/ModelSim, logo nao existe garantia de
-- funcionamento, principalmente por ter sido encontrado na Internet.
-- Podem existir, inclusive, erros de sintaxe ao ser utilizado no Quartus.
--
-- Eduardo Bezerra, junho de 2015.
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM IS
PORT(
player : in std_logic;
address : in std_logic_vector(1 downto 0);
data : out std_logic_vector(13 downto 0)
);
END ENTITY;
ARCHITECTURE BEV OF ROM IS
type mem is array ( 0 to 2**2 - 1) of std_logic_vector(13 downto 0);
constant p1 : mem := (
-- memoria do player 1
0 => "00011100000000",
1 => "01000000000010",
2 => "01000000010000",
3 => "00000000010000"
);
constant p2 : mem := (
-- memoria do player 2
0 => "00000001000000",
1 => "00010001000010",
2 => "00010001000000",
3 => "01100000000000"
);
BEGIN
process (player, address)
begin
if player = '1' then
case address is
when "00" => data <= p1(0);
when "01" => data <= p1(1);
when "10" => data <= p1(2);
when "11" => data <= p1(3);
when others => data <= (others => '0');
end case;
else
case address is
when "00" => data <= p2(0);
when "01" => data <= p2(1);
when "10" => data <= p2(2);
when "11" => data <= p2(3);
when others => data <= (others => '0');
end case;
end if;
end process;
END BEV;
| mit | 693a3baa05b21a2ee89a6049f551be4a | 0.609722 | 3.245023 | false | false | false | false |
TheMassController/VHDL_experimenting | project/UART/uart_transmit.vhd | 1 | 11,282 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
-- Handles the outgoing data.
-- A note about parity:
-- 0: odd parity
-- 1: even parity
-- 2: always 0 parity
-- 3: always 1 parity
-- if parity_bit is false, this parameter is ignored
-- On the next clockcycle from data_send_start the component will lock the data and send all the data, unless reset is asserted in the process.
-- If ready is low the uart transmitter is busy.
-- It is a violation of the UART standard to send 9 bits and a parity bit. This component will not care, however.
entity uart_transmit is
generic (
baudrate : Natural;
clk_freq : Natural;
parity_bit_en : boolean;
parity_bit_type : Natural range 0 to 3;
bit_count : Natural range 5 to 9;
stop_bits : Natural range 1 to 2
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
uart_tx : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(8 DOWNTO 0);
data_send_start : in STD_LOGIC; -- Signals that the data can now be send
ready : out STD_LOGIC
);
end uart_transmit;
architecture Behavioral of uart_transmit is
function BOOL_TO_INT(X : boolean) return integer is
begin
if X then
return 1;
else
return 0;
end if;
end BOOL_TO_INT;
-- Type definition
type state_type is (reset, wait_send, start_one, start_two, bit_one, bit_two, bit_end, parity_one, parity_two, stop_one, stop_two, restore_timing);
type output_type is (start, bits, parity, stop);
-- Constant definition
constant totalBitsSend : integer := 1 + bit_count + stop_bits + BOOL_TO_INT(parity_bit_en);
constant ticksPerHalfSend : integer := integer(clk_freq/(baudrate*2));
constant restorationTicks : natural := (clk_freq * totalBitsSend)/baudrate - (ticksPerHalfSend * totalBitsSend * 2);
-- Signals
-- Related to the timer
signal ticker_rst : STD_LOGIC := '1';
signal ticker_done : STD_LOGIC;
signal restore_rst : STD_LOGIC := '1';
signal restore_done : STD_LOGIC;
-- Related to the mux
signal cur_output : output_type := stop;
-- Related to the bit output selector and the parity generator.
-- On the falling edge of next_bit the next bit is send to the output_bit line and the parity_output is updated
signal lock_data : boolean := false;
signal next_bit : boolean := false;
signal output_bit : STD_LOGIC;
signal parity_output : STD_LOGIC;
-- The state variable of the FSM
signal state : state_type := reset;
-- Helper function for state transitions
function simple_state_transition(if0: state_type; if1 : state_type; var: STD_LOGIC) return state_type is
begin
if var = '1' then
return if1;
else
return if0;
end if;
end simple_state_transition;
begin
-- The ticker
ticker : entity work.simple_multishot_timer
generic map (
match_val => ticksPerHalfSend
)
port map (
clk => clk,
rst => ticker_rst,
done => ticker_done
);
-- Restoration ticker
rest_ticker : entity work.simple_multishot_timer
generic map (
match_val => restorationTicks
)
port map (
clk => clk,
rst => restore_rst,
done => restore_done
);
-- The mux
output_mux : process (cur_output, output_bit, parity_output)
begin
case cur_output is
when start =>
uart_tx <= '0';
when bits =>
uart_tx <= output_bit;
when parity =>
uart_tx <= parity_output;
when stop =>
uart_tx <= '1';
end case;
end process;
-- The parity generator
parity_gen : process(clk)
variable even : STD_LOGIC := '1';
variable last_next_bit : boolean := false;
begin
if rising_edge(clk) then
if not lock_data then
even := '1';
elsif next_bit then
last_next_bit := true;
elsif last_next_bit then
last_next_bit := false;
if output_bit = '1' then
even := not even;
end if;
end if;
end if;
case parity_bit_type is
when 0 =>
parity_output <= not even;
when 1 =>
parity_output <= even;
when 2 =>
parity_output <= '0';
when 3 =>
parity_output <= '1';
end case;
end process;
-- The data storage facility
bit_selector : process(clk)
variable cur_data : STD_LOGIC_VECTOR(bit_count - 1 DOWNTO 0) := (others => '0');
variable last_next_bit : boolean := false;
begin
if rising_edge(clk) then
if not lock_data then
cur_data := data_in(bit_count-1 DOWNTO 0);
elsif next_bit then
last_next_bit := true;
elsif last_next_bit then
last_next_bit := false;
cur_data := '0' & cur_data(bit_count - 1 DOWNTO 1);
end if;
end if;
output_bit <= cur_data(0);
end process;
state_selector : process(clk, rst)
variable bits_send : natural := 0;
variable stop_bits_send : natural := 0;
begin
if rst = '1' then
bits_send := 0;
stop_bits_send := 0;
state <= reset;
elsif rising_edge(clk) then
case state is
when reset =>
state <= wait_send;
when wait_send =>
bits_send := 0;
stop_bits_send := 0;
state <= simple_state_transition(wait_send, start_one, data_send_start);
when start_one =>
state <= simple_state_transition(start_one, start_two, ticker_done);
when start_two =>
state <= simple_state_transition(start_two, bit_one, ticker_done);
when bit_one =>
if ticker_done = '1' then
if bits_send = bit_count - 1 then
state <= bit_end;
else
state <= bit_two;
end if;
else
state <= bit_one;
end if;
when bit_two =>
if ticker_done = '1' then
bits_send := bits_send + 1;
state <= bit_one;
else
state <= bit_two;
end if;
when bit_end =>
if ticker_done = '1' then
if parity_bit_en then
state <= parity_one;
else
state <= stop_one;
end if;
else
state <= bit_end;
end if;
when parity_one =>
state <= simple_state_transition(parity_one, parity_two, ticker_done);
when parity_two =>
state <= simple_state_transition(parity_two, stop_one, ticker_done);
when stop_one =>
state <= simple_state_transition(stop_one, stop_two, ticker_done);
when stop_two =>
if ticker_done = '1' then
if stop_bits = 2 then
stop_bits_send := stop_bits_send + 1;
if stop_bits_send = stop_bits then
state <= restore_timing;
else
state <= stop_one;
end if;
else
state <= restore_timing;
end if;
else
state <= stop_two;
end if;
when restore_timing =>
if restore_done = '1' or restorationTicks = 0 then
state <= wait_send;
else
state <= restore_timing;
end if;
end case;
end if;
end process;
-- The state behaviour
state_output : process (state)
begin
case state is
when reset =>
ready <= '0';
ticker_rst <= '1';
cur_output <= stop;
lock_data <= false;
next_bit <= false;
restore_rst <= '1';
when wait_send =>
ready <= '1';
ticker_rst <= '1';
cur_output <= stop;
lock_data <= false;
next_bit <= false;
restore_rst <= '1';
when start_one =>
ready <= '0';
ticker_rst <= '0';
cur_output <= start;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when start_two =>
ready <= '0';
ticker_rst <= '0';
cur_output <= start;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when bit_one =>
ready <= '0';
ticker_rst <= '0';
cur_output <= bits;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when bit_two|bit_end =>
ready <= '0';
ticker_rst <= '0';
cur_output <= bits;
lock_data <= true;
next_bit <= true;
restore_rst <= '1';
when parity_one|parity_two =>
ready <= '0';
ticker_rst <= '0';
cur_output <= parity;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when stop_one|stop_two =>
ready <= '0';
ticker_rst <= '0';
cur_output <= stop;
lock_data <= true;
next_bit <= false;
restore_rst <= '1';
when restore_timing =>
ready <= '0';
ticker_rst <= '1';
cur_output <= stop;
lock_data <= false;
next_bit <= false;
restore_rst <= '0';
end case;
end process;
end Behavioral;
| mit | 0378751bd5785685b14cd6b75d1f7b68 | 0.4376 | 4.565763 | false | false | false | false |
chastell/art-decomp | kiss/modulo12_hot.vhd | 1 | 3,649 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity modulo12_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end modulo12_hot;
architecture behaviour of modulo12_hot is
constant st0: std_logic_vector(11 downto 0) := "100000000000";
constant st1: std_logic_vector(11 downto 0) := "010000000000";
constant st2: std_logic_vector(11 downto 0) := "001000000000";
constant st3: std_logic_vector(11 downto 0) := "000100000000";
constant st4: std_logic_vector(11 downto 0) := "000010000000";
constant st5: std_logic_vector(11 downto 0) := "000001000000";
constant st6: std_logic_vector(11 downto 0) := "000000100000";
constant st7: std_logic_vector(11 downto 0) := "000000010000";
constant st8: std_logic_vector(11 downto 0) := "000000001000";
constant st9: std_logic_vector(11 downto 0) := "000000000100";
constant st10: std_logic_vector(11 downto 0) := "000000000010";
constant st11: std_logic_vector(11 downto 0) := "000000000001";
signal current_state, next_state: std_logic_vector(11 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st1; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st4; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st5; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st6; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st7; output <= "0";
elsif std_match(input, "1") then next_state <= st8; output <= "0";
end if;
when st8 =>
if std_match(input, "0") then next_state <= st8; output <= "0";
elsif std_match(input, "1") then next_state <= st9; output <= "0";
end if;
when st9 =>
if std_match(input, "0") then next_state <= st9; output <= "0";
elsif std_match(input, "1") then next_state <= st10; output <= "0";
end if;
when st10 =>
if std_match(input, "0") then next_state <= st10; output <= "0";
elsif std_match(input, "1") then next_state <= st11; output <= "0";
end if;
when st11 =>
if std_match(input, "0") then next_state <= st11; output <= "0";
elsif std_match(input, "1") then next_state <= st0; output <= "0";
end if;
when others => next_state <= "------------"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | b4044141419ed747337192454bf263a8 | 0.581529 | 3.287387 | false | false | false | false |
chastell/art-decomp | kiss/scf_hot.vhd | 1 | 53,522 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_hot is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_hot;
architecture behaviour of scf_hot is
constant state1: std_logic_vector(120 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state3: std_logic_vector(120 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state2: std_logic_vector(120 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state4: std_logic_vector(120 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state5: std_logic_vector(120 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state7: std_logic_vector(120 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state6: std_logic_vector(120 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state9: std_logic_vector(120 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state8: std_logic_vector(120 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state17: std_logic_vector(120 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state12: std_logic_vector(120 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state10: std_logic_vector(120 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state11: std_logic_vector(120 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state15: std_logic_vector(120 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state13: std_logic_vector(120 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state29: std_logic_vector(120 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state14: std_logic_vector(120 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state59: std_logic_vector(120 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state16: std_logic_vector(120 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state18: std_logic_vector(120 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state19: std_logic_vector(120 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state21: std_logic_vector(120 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state20: std_logic_vector(120 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state22: std_logic_vector(120 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state23: std_logic_vector(120 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state24: std_logic_vector(120 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state26: std_logic_vector(120 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state25: std_logic_vector(120 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state28: std_logic_vector(120 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state27: std_logic_vector(120 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state36: std_logic_vector(120 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state34: std_logic_vector(120 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state32: std_logic_vector(120 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state30: std_logic_vector(120 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state38: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state31: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state37: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state55: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state33: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state57: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state35: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state43: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state41: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state39: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state45: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state40: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state44: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant state50: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant state42: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant state48: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant state46: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant state47: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant state49: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant state52: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant state51: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant state54: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant state53: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant state56: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant state58: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant state67: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant state60: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant state65: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant state63: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant state61: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant state82: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant state62: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant state83: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant state64: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant state89: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant state66: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant state81: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant state80: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant state78: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant state76: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant state74: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant state72: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant state70: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant state68: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant state96: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant state69: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant state98: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant state71: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant state103: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant state73: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant state107: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant state75: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant state115: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant state77: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant state117: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant state79: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant state84: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant state86: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant state85: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant state88: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant state87: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant state91: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant state90: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant state92: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant state95: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant state93: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant state94: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant state97: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant state101: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant state99: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant state100: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant state102: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant state105: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant state104: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant state106: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant state112: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant state108: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant state110: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant state109: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant state111: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant state114: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant state113: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant state116: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant state118: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant state121: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant state119: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant state120: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(120 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------------------------------------------------------------------------------------------------------------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------------------------------------------------------------------------------------------------------------------------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 64b802e5e1602f72297992aa75559347 | 0.677983 | 5.469801 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/column.vhd | 2 | 8,119 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- The column entity implements all the components needed by a single
-- column of the AES state:
-- + two linear layer for the first two rows
-- + a DDR register, used to store the first two rows of the state
-- + two other linear layer for the last two rows
-- + another DDR register, used to store the last two rows of the state
-- + the Substitution Box (SBox)
-- The barrel shifter is instantiated in the DataUnit, since it operates
-- on a whole row.
-----------------------------------------------------------------------
-- Component Declaration
entity column is port (
in_hi, in_lo : in std_logic_vector (7 downto 0);
side_in : in std_logic_vector( 31 downto 0 ); -- horizontal input for I/O
roundkey : in std_logic_vector( 31 downto 0 );
aux_sbox_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
enable_SBox_sharing : T_ENABLE;
enable_main, enable_dual, select_dual1, select_dual2 : in T_ENABLE;
check_dual : in T_ENABLE;
clock, reset : in std_logic;
broken : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
side_out : out std_logic_vector( 31 downto 0 );
aux_sbox_out : out std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0);
-- For the fault injection
fault_injection : in std_logic_vector( 7 downto 0 )
);
end column;
-- Architecture of the Component
architecture a_column of column is
component DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 ); --
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component DDR_dual is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable_main, enable_dual, select_dual, check_dual : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
error_on_diff_hi, error_on_diff_lo : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component sbox is port (
b_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
clock, reset : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end component;
component linear is
generic ( G_ROW : integer range 0 to 3 );
port (
b_in : in std_logic_vector (7 downto 0);
out_2_mc : out std_logic_vector (7 downto 0);
in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
h_in : in std_logic_vector (7 downto 0);
round_key : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
clock : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end component;
component trigger is port (
switch : in std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
clock, reset : in std_logic;
value : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 ) );
end component;
signal lin_0_in, lin_1_in, lin_2_in, lin_3_in,
lin_0_out, lin_1_out, lin_2_out, lin_3_out : std_logic_vector( 7 downto 0 );
signal out_2_mc_0, out_2_mc_1, out_2_mc_2, out_2_mc_3 : std_logic_vector( 7 downto 0 );
signal layer_2_out, sbox_in, sbox_out : std_logic_vector( 7 downto 0 );
signal t_ctrl_dec : T_ENCDEC;
signal cell_0, cell_1, cell_2, cell_3 : std_logic_vector( 7 downto 0 );
signal cell_faulty : std_logic_vector( 4*C_ERR_SIGNAL_SIZE-1 downto 0 );
-- for fault injection
signal in_hi_sig : std_logic_vector( 7 downto 0);
signal fault_sig: std_logic_vector( 7 downto 0);
begin
fault_sig <= fault_injection;
in_hi_sig <= in_hi;
lin_0_in <= in_hi_sig XOR fault_sig;
lin_1_in <= in_lo;
-- Here first linear block: rows 0 and 1
lin_0 : linear generic map ( G_ROW => 0 ) port map(
b_in => lin_0_in, out_2_mc => out_2_mc_0,
in_1 => out_2_mc_1, in_2 => out_2_mc_2, in_3 => out_2_mc_3,
h_in => side_in(31 downto 24),
round_key => roundkey(31 downto 24),
ctrl_dec => ctrl_dec,
enable_key_pre_add => enable_key_pre_add,
enable_key_add => enable_key_add,
enable_MixCol => enable_MixCol,
enable_H_in => enable_H_in,
clock => clock,
b_out => lin_0_out );
lin_1 : linear generic map( G_ROW => 1 ) port map(
b_in => lin_1_in, out_2_mc => out_2_mc_1,
in_1 => out_2_mc_0, in_2 => out_2_mc_2, in_3 => out_2_mc_3,
h_in => side_in(23 downto 16),
round_key => roundkey(23 downto 16),
ctrl_dec => ctrl_dec,
enable_key_pre_add => enable_key_pre_add,
enable_key_add => enable_key_add,
enable_MixCol => enable_MixCol,
enable_H_in => enable_H_in,
clock => clock,
b_out => lin_1_out );
ddr_layer_1 : DDR_dual port map( din_hi => lin_0_out, din_lo => lin_1_out,
enable_main => enable_main,
enable_dual => enable_dual,
select_dual => select_dual1,
check_dual => check_dual,
dout_hi => cell_0, dout_lo => cell_1,
error_on_diff_hi => cell_faulty( C_ERR_SIGNAL_SIZE-1 downto 0 ),
error_on_diff_lo => cell_faulty( 2*C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE ),
rst => reset, clk => clock );
lin_2_in <= cell_0;
lin_3_in <= cell_1;
-- Here second linear block: rows 2 and 3
lin_2 : linear generic map ( G_ROW => 2 ) port map(
b_in => lin_2_in, out_2_mc => out_2_mc_2,
in_1 => out_2_mc_0, in_2 => out_2_mc_1, in_3 => out_2_mc_3,
h_in => side_in(15 downto 8),
round_key => roundkey(15 downto 8),
ctrl_dec => ctrl_dec,
enable_key_pre_add => enable_key_pre_add,
enable_key_add => enable_key_add,
enable_MixCol => enable_MixCol,
enable_H_in => enable_H_in,
clock => clock,
b_out => lin_2_out );
lin_3 : linear generic map( G_ROW => 3 ) port map(
b_in => lin_3_in, out_2_mc => out_2_mc_3,
in_1 => out_2_mc_0, in_2 => out_2_mc_1, in_3 => out_2_mc_2,
h_in => side_in( 7 downto 0),
round_key => roundkey( 7 downto 0),
ctrl_dec => ctrl_dec,
enable_key_pre_add => enable_key_pre_add,
enable_key_add => enable_key_add,
enable_MixCol => enable_MixCol,
enable_H_in => enable_H_in,
clock => clock,
b_out => lin_3_out );
ddr_layer_2 : DDR_dual port map( din_hi => lin_2_out, din_lo => lin_3_out,
enable_main => enable_main,
enable_dual => enable_dual,
select_dual => select_dual2,
check_dual => check_dual,
dout_hi => cell_2, dout_lo => cell_3,
error_on_diff_hi => cell_faulty( 3*C_ERR_SIGNAL_SIZE-1 downto 2*C_ERR_SIGNAL_SIZE ),
error_on_diff_lo => cell_faulty( 4*C_ERR_SIGNAL_SIZE-1 downto 3*C_ERR_SIGNAL_SIZE ),
rst => reset, clk => clock );
layer_2_out <= cell_2 when ( clock='1' ) else cell_3;
-- Here sbox layer
t_ctrl_dec <= ctrl_dec when ( enable_SBox_sharing = C_DISABLE )
else c_ENC;
sbox_in <= layer_2_out when ( enable_SBox_sharing = C_DISABLE )
else aux_sbox_in;
i_sbox : sbox port map( sbox_in, t_ctrl_dec,
clock, reset, sbox_out );
aux_sbox_out <= sbox_out;
b_out <= sbox_out;
side_out <= cell_0 & cell_1 & cell_2 & cell_3;
----- ERROR/FAULT MANAGEMENT ------------------------
broken <= ( not C_BROKEN )
when ( cell_faulty=( not ( C_BROKEN & C_BROKEN & C_BROKEN & C_BROKEN ) ) )
else C_BROKEN;
end a_column;
| mit | df45588ce2271c4f83e34be6bf1aa4e3 | 0.559182 | 3.173964 | false | false | false | false |
chastell/art-decomp | kiss/s1_rnd.vhd | 1 | 11,803 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_rnd;
architecture behaviour of s1_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st1: std_logic_vector(4 downto 0) := "00010";
constant st2: std_logic_vector(4 downto 0) := "11011";
constant st5: std_logic_vector(4 downto 0) := "11110";
constant st3: std_logic_vector(4 downto 0) := "11111";
constant st4: std_logic_vector(4 downto 0) := "10001";
constant st6: std_logic_vector(4 downto 0) := "10110";
constant st7: std_logic_vector(4 downto 0) := "01011";
constant st12: std_logic_vector(4 downto 0) := "01111";
constant st13: std_logic_vector(4 downto 0) := "00001";
constant st8: std_logic_vector(4 downto 0) := "10000";
constant st11: std_logic_vector(4 downto 0) := "11010";
constant st15: std_logic_vector(4 downto 0) := "11000";
constant st9: std_logic_vector(4 downto 0) := "01000";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st14: std_logic_vector(4 downto 0) := "01001";
constant st16: std_logic_vector(4 downto 0) := "00110";
constant st17: std_logic_vector(4 downto 0) := "11100";
constant st18: std_logic_vector(4 downto 0) := "00011";
constant st19: std_logic_vector(4 downto 0) := "10111";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | a01200d58bb4f805bcf32a9cadbd2bd7 | 0.565026 | 3.300615 | false | false | false | false |
chastell/art-decomp | kiss/dk27_nov.vhd | 1 | 2,406 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_nov is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_nov;
architecture behaviour of dk27_nov is
constant START: std_logic_vector(2 downto 0) := "110";
constant state2: std_logic_vector(2 downto 0) := "010";
constant state3: std_logic_vector(2 downto 0) := "001";
constant state4: std_logic_vector(2 downto 0) := "111";
constant state5: std_logic_vector(2 downto 0) := "000";
constant state6: std_logic_vector(2 downto 0) := "100";
constant state7: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | ab524e52503ba58ebc2e3206603ce0c3 | 0.594347 | 3.323204 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/MixColumn0.vhd | 2 | 1,657 |
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity mixcolumn0 is port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
ctrl_dec : in T_ENCDEC;
b_out : out std_logic_vector (7 downto 0) ) ;
end mixcolumn0;
architecture a_mixcolumn0 of mixcolumn0 is
component xtime port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
component x2time port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
component x4time port (
b_in : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) ) ;
end component;
signal a, b, c, d, e, f, g, h, i, out_1, out_2 : std_logic_vector (7 downto 0);
begin
a <= in_0( 7 downto 0 ) xor in_1( 7 downto 0 );
c <= in_2( 7 downto 0 ) xor in_3( 7 downto 0 );
b <= c xor in_1( 7 downto 0 );
e <= in_0( 7 downto 0 ) xor in_2( 7 downto 0 );
f <= a xor c;
xt : xtime port map (a, d);
out_1 <= b xor d;
gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
b_out( 7 downto 0 ) <= out_1;
end generate;
gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate
x2t : x2time port map (e, g);
x4t : x4time port map (f, h);
i <= g xor h;
out_2 <= out_1 xor i; -- x4time(f) XOR x2time(e) XOR xtime(a) XOR b
b_out( 7 downto 0 ) <= out_1 when (ctrl_dec = C_ENC) else out_2; -- out_1 when encryptin, else out_2 when decrypting
end generate;
end a_mixcolumn0;
| mit | b4571b8afec24a25680661b2cb2f2637 | 0.568497 | 2.932743 | false | false | false | false |
chastell/art-decomp | kiss/ex7_nov.vhd | 1 | 4,215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex7_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex7_nov;
architecture behaviour of ex7_nov is
constant s1: std_logic_vector(3 downto 0) := "1100";
constant s2: std_logic_vector(3 downto 0) := "1101";
constant s3: std_logic_vector(3 downto 0) := "0111";
constant s4: std_logic_vector(3 downto 0) := "1010";
constant s5: std_logic_vector(3 downto 0) := "1000";
constant s6: std_logic_vector(3 downto 0) := "1011";
constant s7: std_logic_vector(3 downto 0) := "1001";
constant s8: std_logic_vector(3 downto 0) := "1111";
constant s9: std_logic_vector(3 downto 0) := "1110";
constant s0: std_logic_vector(3 downto 0) := "0000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s7; output <= "11";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "11";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s7; output <= "00";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "00";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s4; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s4; output <= "11";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s6; output <= "11";
elsif std_match(input, "01") then next_state <= s3; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 87de79ac8e4eca258054db30213c5660 | 0.560854 | 3.280156 | false | false | false | false |
caiopo/battleship-vhdl | src/cronometro.vhd | 1 | 1,658 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cronometro is
port (
clock_50: in std_logic;
dificuldade: in std_logic_vector(1 downto 0);
reset: in std_logic;
restante: out std_logic_vector(7 downto 0);
atual: out std_logic_vector(7 downto 0)
);
end cronometro;
architecture circuito of cronometro is
signal clk_1hz: std_logic;
signal contagem: std_logic_vector(7 downto 0);
signal maximo: std_logic_vector(7 downto 0);
component clock_conv
port
(
IN_50MHz : in std_logic;
OUT_0_1Hz : out std_logic;
OUT_1Hz : out std_logic;
OUT_10Hz : out std_logic
);
end component;
begin
converter: clock_conv port map(clock_50, open, clk_1hz, open);
process(dificuldade, clock_50)
begin
-- define o tempo maximo da contagem levando em conta a dificuldade escolhida
case dificuldade is
when "00" =>
maximo <= "00011110";
when "01" =>
maximo <= "00010100";
when "10" =>
maximo <= "00001010";
when "11" =>
maximo <= "00000101";
end case;
end process;
process(clk_1hz, reset)
begin
if (reset = '1') then
-- reset assincrono
contagem <= "00000000";
elsif (rising_edge(clk_1hz)) then
-- se a o tempo atual for maior que o tempo maximo, reseta o tempo atual, senao, adiciona um ao tempo atual
if (contagem >= maximo) then
contagem <= "00000000";
else
contagem <= contagem + '1';
end if;
end if;
end process;
-- para obter o tempo restante, subtraimos o tempo atual do tempo maximo
restante <= maximo - contagem;
atual <= contagem;
end circuito; | mit | c99883a4616108383b2456a427f3ea22 | 0.640531 | 3.140152 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/clk_gen.vhd | 1 | 1,367 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : clk_gen.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Clockgenerator
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
architecture rtl of clk_gen is
signal s_signal : std_logic := '0';
begin
process(clk_i, reset_i)
variable v_count : integer := 0;
begin
if reset_i = '1' then
s_signal <= '0';
v_count := 0;
elsif rising_edge(clk_i) then
if v_count = count_val_i then
v_count := 0;
s_signal <= not s_signal;
else
v_count := v_count + 1;
end if;
end if;
end process;
signal_o <= s_signal;
end rtl; | mit | 8992d04de1f1ccbef1485a9fdf5701e1 | 0.414045 | 4.618243 | false | false | false | false |
ibm2030/IBM2030 | ibm1050.vhd | 1 | 6,845 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm1050.vhd
-- Creation Date: 21:17:39 2005-04-18
-- Description:
-- 1050 (Console Typewriter) attachment
--
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2012-04-07
-- Initial release - no Tilt/Rotate to ASCII conversion on printing or handling
-- of Shift-Up or Shift-Down, also no ASCII to key-code conversion on input
-- (all this is handled inside the CPU)
---------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.Buses_package.all;
use UNISIM.vcomponents.all;
use work.all;
entity ibm1050 is
Port (
SerialIn : inout PCH_CONN; -- Data lines in to CPU
SerialOut : in RDR_CONN; -- Data lines out of CPU
SerialControl : in CONN_1050; -- Control lines out of CPU
-- Serial I/O
serialInput : in Serial_Input_Lines;
serialOutput : out Serial_Output_Lines;
-- 50Mhz clock
clk : in std_logic
);
end ibm1050;
architecture FMD of ibm1050 is
signal SerialBusUngated : STD_LOGIC_VECTOR(7 downto 0);
signal RxDataAvailable : STD_LOGIC;
signal TxBufferEmpty : STD_LOGIC;
signal serialOutputByte : STD_LOGIC_VECTOR(7 downto 0);
signal serialOutputStrobe : STD_LOGIC := '0';
signal RxAck, PunchGate : STD_LOGIC;
signal resetSerial : STD_LOGIC := '0';
type printerStateType is (waitForEnable,printerReset,printerEnabled,printCharacter,waitForCharacter,waitFree,printCR,waitForCR,printLF,waitForLF);
signal printerState : printerStateType := waitForEnable;
signal RDR_1_CLUTCH_timer : STD_LOGIC_VECTOR(15 downto 0);
begin
Printer: process (clk)
begin
if rising_edge(clk) then
case printerState is
when waitForEnable =>
serialIn.HOME_RDR_STT_LCH <= '0'; -- Not running
serialIn.RDR_1_CLUTCH_1050 <= '0'; -- Not ready to receive a character
serialOutputStrobe <= '0';
if (serialControl.HOME_RDR_START='1') then
resetSerial <= '1';
printerState <= printerReset;
elsif (serialControl.CARR_RETURN_AND_LINE_FEED='1') then
printerState <= printCR;
end if;
when printerReset =>
resetSerial <= '0';
printerState <= printerEnabled;
when printerEnabled =>
serialIn.HOME_RDR_STT_LCH <= '1'; -- Running
serialIn.RDR_1_CLUTCH_1050 <= TxBufferEmpty; -- Ready to receive a character
if (serialControl.HOME_RDR_START='0') then
printerState <= waitForEnable;
elsif (serialOut.RD_STROBE='1') then
printerState <= printCharacter;
elsif (serialControl.CARR_RETURN_AND_LINE_FEED='1') then
printerState <= printCR;
end if;
when printCharacter =>
serialIn.RDR_1_CLUTCH_1050 <= '0'; -- Not ready for another character
serialOutputByte <= '0' & SerialOut.RDR_BITS; -- Here we could translate from TILT/ROTATE to ASCII
serialOutputStrobe <= '1';
printerState <= waitForCharacter;
RDR_1_CLUTCH_TIMER <= x"9C40"; -- 9C40 = 40000 = 800us
when waitForCharacter =>
-- Need to wait in this state for long enough to guarantee that
-- RDR_1_CLUTCH is still low at Y_TIME to reset ALLOW_STROBE latch
serialOutputStrobe <= '0';
if (serialOut.RD_STROBE='0') then
RDR_1_CLUTCH_timer <= RDR_1_CLUTCH_timer - "0000000000000001";
if (RDR_1_CLUTCH_timer="0000000000000000") then
printerState <= printerEnabled;
end if;
end if;
when printCR =>
if (TxBufferEmpty='1') then
serialOutputByte <= "00001101"; -- CR
serialOutputStrobe <= '1';
printerState <= waitForCR;
end if;
when waitForCR =>
serialOutputStrobe <= '0';
printerState <= printLF;
when printLF =>
if (TxBufferEmpty='1') then
serialOutputByte <= "00001010"; -- LF
serialOutputStrobe <= '1';
printerState <= waitForLF;
end if;
when waitForLF =>
serialOutputStrobe <= '0';
if (serialControl.CARR_RETURN_AND_LINE_FEED='0') then -- Wait for CRLF to drop
if (serialControl.HOME_RDR_START='0') then
printerState <= waitForEnable;
else
printerState <= printerEnabled;
end if;
end if;
when others =>
printerState <= waitForEnable;
end case;
end if;
end process Printer;
serial_port : entity RS232RefComp port map(
RST => '0', --Master Reset
CLK => clk,
-- Rx (PCH)
RXD => SerialInput.serialRx,
RDA => RxDataAvailable, -- Rx data available
PE => open, -- Parity Error Flag
FE => open, -- Frame Error Flag
OE => open, -- Overwrite Error Flag
DBOUT => SerialBusUngated, -- Rx data (needs to be 0 when RDA=0)
RD => RxAck, -- Read strobe
-- Tx (RDR)
TXD => serialOutput.serialTx,
TBE => TxBufferEmpty, -- Tx buffer empty
DBIN => serialOutputByte, -- Tx data
WR => serialOutputStrobe -- Write Strobe
);
-- Make incoming data 0 when nothing is available
SerialIn.PCH_BITS <= SerialBusUngated(6 downto 0) when PunchGate='1' else "0000000";
PunchStrobeSS : entity SS port map (clk=>clk, count=>2500, D=>RxDataAvailable, Q=>RxAck); -- 50us or so
SerialIn.PCH_1_CLUTCH_1050 <= RxAck;
PunchGateSS : entity SS port map (clk=>clk, count=>3000, D=>RxDataAvailable, Q=>PunchGate); -- A bit more than 50us so Read Interlock is reset after PCH_1_CLUTCH drops
SerialIn.CPU_CONNECTED <= '1'; -- 1050 always on-line
SerialIn.HOME_OUTPUT_DEV_RDY <= '1'; -- Printer always ready
SerialIn.RDR_2_READY <= '0';
-- SerialIn.HOME_RDR_STT_LCH <= SerialControl.HOME_RDR_START;
SerialIn.REQ_KEY <= '0';
SerialOutput.RTS <= '1';
SerialOutput.DTR <= '1';
end FMD;
| gpl-3.0 | 04f617b87a43df67971541012ef82f46 | 0.661651 | 3.476384 | false | false | false | false |
chastell/art-decomp | kiss/s298_hot.vhd | 1 | 175,410 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_hot is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_hot;
architecture behaviour of s298_hot is
constant s00000000000000: std_logic_vector(217 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000001100000: std_logic_vector(217 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000001100010: std_logic_vector(217 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000001100011: std_logic_vector(217 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000001100001: std_logic_vector(217 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000001100000: std_logic_vector(217 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000001100001: std_logic_vector(217 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000001100000: std_logic_vector(217 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000001100011: std_logic_vector(217 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000001100010: std_logic_vector(217 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001001100011: std_logic_vector(217 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001001100010: std_logic_vector(217 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001001100000: std_logic_vector(217 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001001100001: std_logic_vector(217 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100001100011: std_logic_vector(217 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100001100010: std_logic_vector(217 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100001100001: std_logic_vector(217 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100001100000: std_logic_vector(217 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101001100010: std_logic_vector(217 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101001100011: std_logic_vector(217 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101001100000: std_logic_vector(217 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101001100001: std_logic_vector(217 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01101001100010: std_logic_vector(217 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01101001100011: std_logic_vector(217 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01101001100001: std_logic_vector(217 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01101001100000: std_logic_vector(217 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00010001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00010001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00010001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00010001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000000011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01100001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01100001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01100001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01100001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11101000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10011000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10011000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10011000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10011000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00011001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10010001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11000100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10101100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10100100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00100100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s11001100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001010010001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001010010000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001010010011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00001010010010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00000010010000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000000011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000000011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000000011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10000000011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s00101001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001000011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001000011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001000011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s10001000011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001000011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001000011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001000011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01001000011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000000011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000000011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000000011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant s01000000011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant s10011001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant s10011001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant s10011001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant s10011001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant s00000001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant s00000001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant s00000001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant s10001001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant s10001001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant s10001001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant s10001001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant s10011010010000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant s10011010010001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant s10011010010010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant s10011010010011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant s00000010010011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant s00000010010010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant s00000010010001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant s10010010010011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant s10010010010010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant s10010010010000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant s10010010010001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant s10011100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant s10011100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant s10011100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant s10011100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant s00000100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant s00000100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant s00000100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant s00000100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant s11100001100001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant s11100001100000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant s11100001100010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant s11100001100011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant s10010000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant s10010000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant s10010000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant s10010000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant s00010000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant s00010000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant s00010000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant s00010000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant s11100000100111: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant s11100000100110: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant s11100000100100: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant s11100000100101: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant s01100100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant s01100100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant s01100100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant s01100100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant s11100100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant s11100100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant s11100100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant s11100100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant s00011100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant s00011100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant s00011100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant s00011100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant s00010100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant s00010100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant s00010100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant s00010100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant s11101100011001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant s11101100011000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant s11101100011010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant s11101100011011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant s01101100000000: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant s01101100000001: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant s01101100000011: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant s01101100000010: std_logic_vector(217 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(217 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"; output <= "------";
case current_state is
when s00000000000000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "000000";
end if;
when s00000001100000 =>
if std_match(input, "000") then next_state <= s10000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10000001100000 =>
if std_match(input, "010") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100001 =>
if std_match(input, "001") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100011 =>
if std_match(input, "000") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100011 =>
if std_match(input, "010") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100010 =>
if std_match(input, "000") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100001; output <= "100001";
end if;
when s11101001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100001; output <= "100001";
end if;
when s00010001100010 =>
if std_match(input, "000") then next_state <= s10010100011010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10010100011010 =>
if std_match(input, "011") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011011; output <= "000000";
end if;
when s00000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "010100";
end if;
when s10000001100010 =>
if std_match(input, "010") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "100001";
end if;
when s11001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100010; output <= "100001";
end if;
when s00100001100000 =>
if std_match(input, "001") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100010 =>
if std_match(input, "011") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100001 =>
if std_match(input, "011") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100110 =>
if std_match(input, "000") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100110 =>
if std_match(input, "001") then next_state <= s10011000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100100; output <= "100010";
end if;
when s00000000100100 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100010";
end if;
when s10000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100001; output <= "100001";
end if;
when s01001001100011 =>
if std_match(input, "011") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100000; output <= "100001";
end if;
when s00100001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100001; output <= "100001";
end if;
when s10100001100011 =>
if std_match(input, "011") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100000; output <= "100001";
end if;
when s11101001100010 =>
if std_match(input, "011") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100001 =>
if std_match(input, "011") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10010001100010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100001";
end if;
when s00001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011010; output <= "000000";
end if;
when s10001100011000 =>
if std_match(input, "010") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011011; output <= "000000";
end if;
when s11000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000011; output <= "010100";
end if;
when s00101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000001 =>
if std_match(input, "001") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011010; output <= "000000";
end if;
when s11000100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000000; output <= "010100";
end if;
when s00100100000011 =>
if std_match(input, "011") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011010; output <= "000000";
end if;
when s00100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011011; output <= "000000";
end if;
when s00100100000000 =>
if std_match(input, "000") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11000100011010 =>
if std_match(input, "011") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11000100011011 =>
if std_match(input, "010") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000000 =>
if std_match(input, "000") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11001100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000011; output <= "010100";
end if;
when s11001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000010; output <= "010100";
end if;
when s11001100011010 =>
if std_match(input, "000") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11001100011011 =>
if std_match(input, "001") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011001; output <= "000000";
end if;
when s01001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011010; output <= "000000";
end if;
when s10001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000011; output <= "010100";
end if;
when s01000100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011001; output <= "000000";
end if;
when s01000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011001; output <= "000000";
end if;
when s01000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011010; output <= "000000";
end if;
when s01000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011010; output <= "000000";
end if;
when s10001100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000000; output <= "010100";
end if;
when s10001100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000011; output <= "010100";
end if;
when s00001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011011; output <= "000000";
end if;
when s10000100011000 =>
if std_match(input, "001") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000000; output <= "010100";
end if;
when s10000100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000011; output <= "010100";
end if;
when s10000100011011 =>
if std_match(input, "011") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000000 =>
if std_match(input, "011") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10010001100011 =>
if std_match(input, "001") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
end if;
when s10010001100001 =>
if std_match(input, "000") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00001010010001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000000011000; output <= "001100";
end if;
when s10000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "010100";
end if;
when s01000001100010 =>
if std_match(input, "000") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100010 =>
if std_match(input, "000") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100000; output <= "100001";
end if;
when s11000001100011 =>
if std_match(input, "010") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100010 =>
if std_match(input, "001") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100011 =>
if std_match(input, "011") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100000 =>
if std_match(input, "001") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100001; output <= "100001";
end if;
when s11000001100001 =>
if std_match(input, "001") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "100001";
end if;
when s10000000011011 =>
if std_match(input, "001") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "100001";
end if;
when s01001001100000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100001; output <= "100001";
end if;
when s11001001100010 =>
if std_match(input, "001") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01001001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "100001";
end if;
when s10000000011001 =>
if std_match(input, "010") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10000000011000 =>
if std_match(input, "000") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s00001010010000 =>
if std_match(input, "000") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s10001000011000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "010100";
end if;
when s01001000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100000; output <= "010100";
end if;
when s01001000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "010100";
end if;
when s01001000011001 =>
if std_match(input, "001") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001000011000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10001000011001 =>
if std_match(input, "001") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s01000000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "010100";
end if;
when s01000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "010100";
end if;
when s01000000011001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "010100";
end if;
when s01000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "010100";
end if;
when s10001000011011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "010100";
end if;
when s10001000011010 =>
if std_match(input, "000") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s00001010010011 =>
if std_match(input, "010") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00001010010010 =>
if std_match(input, "000") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00000010010000 =>
if std_match(input, "011") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s10000001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100000; output <= "100001";
end if;
when s10010001100000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00011001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100010; output <= "100001";
end if;
when s10011001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100011; output <= "100001";
end if;
when s00000001100001 =>
if std_match(input, "010") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10001001100000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "100001";
end if;
when s10001001100001 =>
if std_match(input, "000") then next_state <= s01000000011001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100010 =>
if std_match(input, "010") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "100001";
end if;
when s00000001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100001";
end if;
when s00000001100011 =>
if std_match(input, "011") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100000 =>
if std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "110") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "-00") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100010 =>
if std_match(input, "000") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "1-0") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100001; output <= "100001";
end if;
when s00011001100011 =>
if std_match(input, "011") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100011; output <= "100001";
end if;
when s11101001100001 =>
if std_match(input, "000") then next_state <= s00010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00010001100001 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100001";
end if;
when s10011010010000 =>
if std_match(input, "011") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010000; output <= "001100";
end if;
when s00000010010011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "001100";
end if;
when s00000010010010 =>
if std_match(input, "011") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s00000010010001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "001100";
end if;
when s10011010010001 =>
if std_match(input, "001") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "100") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "-10") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010010 =>
if std_match(input, "000") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "111") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "-01") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010011 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010010; output <= "001100";
end if;
when s00010001100000 =>
if std_match(input, "011") then next_state <= s10010010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s10010010010011 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
end if;
when s10010010010010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "001100";
end if;
when s10010010010000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s10010010010001 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s00010001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100001";
end if;
when s10011100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000001; output <= "010100";
end if;
when s00000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011000; output <= "000000";
end if;
when s00000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011010; output <= "000000";
end if;
when s00000100000000 =>
if std_match(input, "001") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011010; output <= "000000";
end if;
when s10011100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000001; output <= "010100";
end if;
when s10011100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000011; output <= "010100";
end if;
when s10011100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000001; output <= "010100";
end if;
when s11101001100000 =>
if std_match(input, "011") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100001 =>
if std_match(input, "000") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11100001100001 =>
if std_match(input, "001") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s00011000100111 =>
if std_match(input, "000") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10010000100111 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
end if;
when s10010000100110 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100010";
end if;
when s10010000100101 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
end if;
when s10010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100010";
end if;
when s00011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100100; output <= "100010";
end if;
when s10011000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100111; output <= "100010";
end if;
when s00000000100101 =>
if std_match(input, "001") then next_state <= s10001001100011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
end if;
when s00000000100110 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100010";
end if;
when s00000000100111 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100010";
end if;
when s10011000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100101 =>
if std_match(input, "011") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "1-1") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "1-0") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100101 =>
if std_match(input, "000") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100001100000 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100111; output <= "100001";
end if;
when s00010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010010010011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100010";
end if;
when s00010000100101 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100010";
end if;
when s00010000100110 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "100010";
end if;
when s10010100011000 =>
if std_match(input, "010") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011001 =>
if std_match(input, "010") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "010100";
end if;
when s00010000100111 =>
if std_match(input, "011") then next_state <= s10011100011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
end if;
when s11100001100010 =>
if std_match(input, "001") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100001100011 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100001";
end if;
when s01101001100011 =>
if std_match(input, "000") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100000 =>
if std_match(input, "011") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100011 =>
if std_match(input, "010") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100100; output <= "100010";
end if;
when s11101000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100110; output <= "100010";
end if;
when s11101000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100100; output <= "100010";
end if;
when s01100001100010 =>
if std_match(input, "010") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100000100111 =>
if std_match(input, "011") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100010";
end if;
when s11100000100100 =>
if std_match(input, "011") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100010";
end if;
when s01100001100000 =>
if std_match(input, "001") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s10100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100000; output <= "100001";
end if;
when s10101001100011 =>
if std_match(input, "001") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100010; output <= "100001";
end if;
when s10101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100010; output <= "100001";
end if;
when s10100100011000 =>
if std_match(input, "001") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011000; output <= "000000";
end if;
when s11100100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000011; output <= "010100";
end if;
when s00011100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011000; output <= "000000";
end if;
when s00011100000000 =>
if std_match(input, "000") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00011100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011001; output <= "000000";
end if;
when s00011100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011010; output <= "000000";
end if;
when s11100100011010 =>
if std_match(input, "001") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00010100000000 =>
if std_match(input, "010") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011000; output <= "000000";
end if;
when s00010100000010 =>
if std_match(input, "001") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000011 =>
if std_match(input, "000") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000010; output <= "010100";
end if;
when s11100100011000 =>
if std_match(input, "010") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011011; output <= "000000";
end if;
when s11101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000001; output <= "010100";
end if;
when s11101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000001; output <= "010100";
end if;
when s11101100011010 =>
if std_match(input, "011") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000000; output <= "010100";
end if;
when s01100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011011; output <= "000000";
end if;
when s01100100000000 =>
if std_match(input, "000") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000010; output <= "010100";
end if;
when s01101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011000; output <= "000000";
end if;
when s01101100000001 =>
if std_match(input, "011") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s01101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011001; output <= "000000";
end if;
when s01101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011010; output <= "000000";
end if;
when s10100100011011 =>
if std_match(input, "011") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10100100011010 =>
if std_match(input, "001") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000010; output <= "010100";
end if;
when s10101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000010; output <= "010100";
end if;
when s10101100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000000; output <= "010100";
end if;
when s10101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000011; output <= "010100";
end if;
when others => next_state <= "--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | d230c2d52f1e7e09a152a6540dee902e | 0.736577 | 5.311431 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-05D.vhd | 1 | 9,144 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-05D.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Read/Write Storage Clocks for 1st 32k
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Changed for 64k storage: START_1ST_32K triggered for 1st *and* 2nd 32k
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RWStgClk1st32k IS
port
(
-- Inputs
ALLOW_WRITE : IN STD_LOGIC; -- 03D
CPU_READ_PWR : IN STD_LOGIC; -- 04D
SEL_RD_CALL : IN STD_LOGIC; -- 12C
MAN_RD_CALL : IN STD_LOGIC; -- 03D
ROAR_RESTT_AND_STOR_BYPASS : IN STD_LOGIC; -- 04B
SEL_WR_CALL : IN STD_LOGIC; -- 12C
MAN_WR_CALL : IN STD_LOGIC; -- 03D
CPU_WRITE_PWR : IN STD_LOGIC; -- 04D
EARLY_LOCAL_STG : IN STD_LOGIC; -- 04D
EARLY_M_REG_0 : IN STD_LOGIC; -- 07B
M_REG_0 : IN STD_LOGIC; -- 07B
MACH_RST_SW : IN STD_LOGIC; -- 03D
-- Outputs
READ_CALL : OUT STD_LOGIC; -- 03A,03B
USE_LOCAL_MAIN_MEM : OUT STD_LOGIC; -- 06D
USE_MAIN_MEMORY : OUT STD_LOGIC; -- 06D
READ_ECHO_1, READ_ECHO_2 : OUT STD_LOGIC; -- 03D
DATA_READY_1, DATA_READY_2 : OUT STD_LOGIC; -- 03A 03B
WRITE_ECHO_1, WRITE_ECHO_2 : OUT STD_LOGIC; -- 03D
-- Debug
DEBUG1,DEBUG2,DEBUG3,DEBUG4 : OUT STD_LOGIC;
DEBUG : OUT STD_LOGIC;
DBG_TD1_1, DBG_TD1_2 : OUT STD_LOGIC_VECTOR(1 to 38);
DBG_RD_OR_WR_SET1,DBG_RD_OR_WR_RST1 : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
CLK : IN STD_LOGIC -- 50MHz / 20ns
);
END RWStgClk1st32k;
ARCHITECTURE FMD OF RWStgClk1st32k IS
signal START_RD,START_WR : STD_LOGIC;
signal START_1ST_32K, START_2ND_32K : STD_LOGIC;
signal READ_CALL_TO_MEM,WRITE_CALL_TO_MEM : STD_LOGIC;
signal sREAD_CALL : STD_LOGIC;
signal sUSE_LOCAL_MAIN_MEM : STD_LOGIC;
signal USE_LOCAL_Set,USE_LOCAL_Reset : STD_LOGIC;
signal TD1 : STD_LOGIC_VECTOR(1 to 38) := (others=>'0'); -- 20ns steps 20 to 740ns
signal RD_OR_WR_RST1, RD_OR_WR_SET1, nRD_OR_WR_SET1, CTRL_R_WIDTH1, TD1IN : STD_LOGIC;
signal TD1_80, TD1_150, TD1_200, TD1_500, TD1_560, TD1_660, TD1_680, TD1_700 : STD_LOGIC;
signal RD_OR_WR_SET1_RESET, dRD_OR_WR_SET1_RESET, CTRL_R_WIDTH1_RESET : STD_LOGIC;
signal READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_2_RESET : STD_LOGIC;
signal WRITE_ECHO_1_SET : STD_LOGIC;
signal WRITE_ECHO_1_RESET : STD_LOGIC;
signal READ_RST_SET1, READ_RST_SET2 : STD_LOGIC;
signal READ_RST_RESET1, READ_RST_RESET2 : STD_LOGIC;
signal RD_RST_CTRL1 : STD_LOGIC;
signal WRITE_RST_SET1 : STD_LOGIC;
signal WRITE_RST_RESET1 : STD_LOGIC;
signal WR_RST_CTRL1 : STD_LOGIC;
signal SET_READ_LCHS1 : STD_LOGIC;
signal DATA_READY1_SET, DATA_READY1_RESET : STD_LOGIC;
signal SET_READ_LCHS1_RESET : STD_LOGIC;
signal dT1 : STD_LOGIC;
signal sDATA_READY_1 : STD_LOGIC;
BEGIN
-- Fig 5-05D
START_RD <= not ALLOW_WRITE and CPU_READ_PWR and T1; -- AA1K4
START_WR <= ALLOW_WRITE and CPU_WRITE_PWR and T1; -- AA1K4
sREAD_CALL <= START_RD or SEL_RD_CALL or MAN_RD_CALL; -- AA1J2
READ_CALL <= sREAD_CALL;
READ_CALL_TO_MEM <= sREAD_CALL and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J3,AA1C2
WRITE_CALL_TO_MEM <= (MAN_WR_CALL or SEL_WR_CALL or START_WR) and not ROAR_RESTT_AND_STOR_BYPASS; -- AA1J2,AA1J3
USE_LOCAL_Set <= EARLY_LOCAL_STG and READ_CALL_TO_MEM;
USE_LOCAL_Reset <= not EARLY_LOCAL_STG and READ_CALL_TO_MEM;
USE_LOCAL: entity work.FLL port map(USE_LOCAL_Set,USE_LOCAL_Reset,sUSE_LOCAL_MAIN_MEM); -- CB1E2
USE_LOCAL_MAIN_MEM <= sUSE_LOCAL_MAIN_MEM;
USE_MAIN_MEMORY <= not sUSE_LOCAL_MAIN_MEM; -- CB1H2
-- START_1ST_32K <= (not EARLY_M_REG_0 and READ_CALL_TO_MEM) or (READ_CALL_TO_MEM and EARLY_LOCAL_STG) or (not M_REG_0 and WRITE_CALL_TO_MEM) or (WRITE_CALL_TO_MEM and sUSE_LOCAL_MAIN_MEM); -- CB1E2
-- START_2ND_32K <= (READ_CALL_TO_MEM and EARLY_M_REG_0 and not sUSE_LOCAL_MAIN_MEM) or (WRITE_CALL_TO_MEM and M_REG_0 and not sUSE_LOCAL_MAIN_MEM); -- CB1E2
START_1ST_32K <= READ_CALL_TO_MEM or WRITE_CALL_TO_MEM; -- CB1E2 combined 1st & 2nd 32k
-- Generate timing signals relative to START_xxx_32K
-- READ_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
-- WRITE_ECHO_n ON at 150ns OFF at 720ns (or MACH_RST_SW)
-- DATA_READY_n ON at 640ns OFF at 700ns (or MACH_RST_SW)
-- First 32K
TD1_80 <= TD1(4); -- 80ns
TD1_150 <= TD1(8); -- 160ns
TD1_200 <= TD1(10); -- 200ns
TD1_500 <= TD1(25); -- 500ns
TD1_560 <= TD1(28); -- 560ns
TD1_660 <= TD1(33); -- 660ns
TD1_680 <= TD1(34); -- 680ns
TD1_700 <= TD1(35); -- 700ns
nRD_OR_WR_SET1 <= not RD_OR_WR_SET1;
RD_OR_WR_RST1_FL: entity work.FLL port map(TD1_80, nRD_OR_WR_SET1, RD_OR_WR_RST1);
RD_OR_WR_SET1_RESET <= RD_OR_WR_RST1 or MACH_RST_SW;
-- The delay is to prevent a combinatorial loop:
Delay_RD_OR_WR_SET1_RESET: AR port map (D=>RD_OR_WR_SET1_RESET, clk=>Clk, Q=>dRD_OR_WR_SET1_RESET);
RD_OR_WR_SET1_FL: entity work.FLL port map(START_1ST_32K, dRD_OR_WR_SET1_RESET, RD_OR_WR_SET1);
TD1IN <= not RD_OR_WR_RST1 and RD_OR_WR_SET1;
-- READ CLOCK 0
READ_ECHO_1_SET <= TD1_150 and SET_READ_LCHS1;
READ_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and RD_RST_CTRL1);
READ_ECHO_1_FL: entity work.FLL port map(READ_ECHO_1_SET, READ_ECHO_1_RESET, READ_ECHO_1); -- 150 to 680ns
-- READ CLOCK 4
DATA_READY1_SET <= TD1_560 and SET_READ_LCHS1;
DATA_READY1_RESET <= MACH_RST_SW or (TD1_660 and RD_RST_CTRL1);
DATA_READY1_FL: entity work.FLL port map(DATA_READY1_SET, DATA_READY1_RESET, sDATA_READY_1); -- 560 to 660ns
DATA_READY_1 <= sDATA_READY_1;
-- READ CLOCK 5
READ_RST_SET1 <= TD1_500 and SET_READ_LCHS1;
READ_RST_RESET1 <= MACH_RST_SW or TD1_700;
READ_RST1_FL: entity work.FLL port map(READ_RST_SET1, READ_RST_RESET1, RD_RST_CTRL1); -- 500 to 700ns
-- WRITE CLOCK 0
WRITE_ECHO_1_SET <= TD1_150 and not SET_READ_LCHS1;
WRITE_ECHO_1_RESET <= MACH_RST_SW or (TD1_680 and WR_RST_CTRL1);
WRITE_ECHO_1_FL: entity work.FLL port map(WRITE_ECHO_1_SET, WRITE_ECHO_1_RESET, WRITE_ECHO_1); -- 150 to 680ns
-- WRITE CLOCK 4
SET_READ_LCHS1_RESET <= MACH_RST_SW or WRITE_CALL_TO_MEM; -- ??
SET_READ_LCHS1_FL: entity work.FLL port map(READ_CALL_TO_MEM, SET_READ_LCHS1_RESET, SET_READ_LCHS1); -- RD CALL to WR CALL
-- WRITE CLOCK 5
WRITE_RST_SET1 <= TD1_500 and not SET_READ_LCHS1;
WRITE_RST_RESET1 <= MACH_RST_SW or TD1_150; -- 150ns or 1050ns or 1500ns?
WRITE_RST1_FL: entity work.FLL port map(WRITE_RST_SET1, WRITE_RST_RESET1, WR_RST_CTRL1); -- 500 to 700ns??
-- Second 32K
READ_ECHO_2 <= '0';
DATA_READY_2 <= '0';
WRITE_ECHO_2 <= '0';
-- Debug
DEBUG <= START_RD;
DBG_TD1_1 <= TD1;
DBG_RD_OR_WR_SET1 <= RD_OR_WR_SET1;
DBG_RD_OR_WR_RST1 <= RD_OR_WR_RST1;
delayLine: process(CLK)
begin
if (rising_edge(CLK)) then
TD1 <= TD1IN & TD1(1 to TD1'right-1);
end if;
end process;
-- Debug latch
R_DEBUG: process (clk,T1,TD1IN)
begin
if rising_edge(clk) then
if T1='1' and dT1='0' then
DEBUG1 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T1)='1' then
DEBUG1 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG2 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T2)='1' then
DEBUG2 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG3 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T3)='1' then
DEBUG3 <= '1'; -- Set on any DATA_READY
end if;
end if;
if T1='1' and dT1='0' then
DEBUG4 <= '0'; -- Reset on rising edge of T1
else if (sDATA_READY_1 and T4)='1' then
DEBUG4 <= '1'; -- Set on any DATA_READY
end if;
end if;
dT1 <= T1;
end if;
end process;
END FMD;
| gpl-3.0 | 29651fe47724d8bd81402246607cf2bd | 0.645451 | 2.574324 | false | false | false | false |
TheMassController/VHDL_experimenting | project/bus/bus_pkg.vhd | 1 | 7,368 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package bus_pkg is
-- General information on the bus:
-- The master initiates all communication. When readEnable or writeEnable become high (they must never be high at the same time) address and possibly writeData must be valid.
-- The master must now wait until ack becomes high. Ack has to remain high until readData/writeData is zero.
-- On read, the slave must keep readData valid until readEnable is low again.
-- This finishes the transaction.
-- A fault sets a faultcode on the WriteData bus and is handled similarly to an ack otherwise.
--
-- The bus is byte-adressable. The data width of the bus is called a word and is always a multiple of the amount of bytes.
-- These are the relevant sizes of the bus. They are defined like this because if they are not a power of 2,
-- some things, like remapping, will become impossible.
constant bus_byte_size_log2b : natural := 3;
constant bus_address_width_log2b : natural := 5;
-- Make sure that data_width >= byte_size.
constant bus_data_width_log2b : natural := 5;
constant bus_byte_size : natural := 2**bus_byte_size_log2b;
subtype bus_address_type is std_logic_vector(2**bus_address_width_log2b - 1 downto 0); -- Any bus address.
subtype bus_data_type is std_logic_vector(2**bus_data_width_log2b - 1 downto 0); -- Any data word.
subtype bus_byte_type is std_logic_vector(bus_byte_size - 1 downto 0); -- A byte, lowest adressable unit
type bus_data_array is array (natural range <>) of bus_data_type;
type bus_byte_array is array (natural range <>) of bus_byte_type;
constant bus_bytes_per_word : positive := bus_data_type'length / bus_byte_size;
constant bus_bytes_per_word_log2b : natural := bus_data_width_log2b - bus_byte_size_log2b;
subtype bus_write_mask is std_logic_vector(bus_bytes_per_word - 1 downto 0);
-- The remapping logic.
-- Any range of input can be placed at any range of output. Moreover, parts of the output can be set to 0 or 1.
-- As an example, take a device which has registers on address 0 to 3, but in reality lives on address 1 to 4.
-- A correct remapping would now be: bus_map_constant(1, '0') & bus_map_range(bus_address_type'high - 1, 0)
type bitMapping_array is array (natural range <>) of integer;
-- Using this type makes sure that the bitmapping aray is always exactly long enough.
subtype addrMapping_type is bitMapping_array(bus_address_type'range);
type bus_mst2slv_type is record
address : bus_address_type;
writeData : bus_data_type;
writeMask : bus_write_mask;
readEnable : std_logic;
writeEnable : std_logic;
end record;
type bus_mst2slv_array is array (natural range <>) of bus_mst2slv_type;
type bus_slv2mst_type is record
readData : bus_data_type;
ack : std_logic;
fault : std_logic;
end record;
type bus_slv2mst_array is array (natural range <>) of bus_slv2mst_type;
type addr_range_type is record
low : bus_address_type;
high : bus_address_type;
end record;
type addr_range_and_mapping_type is record
addr_range : addr_range_type;
mapping : addrMapping_type;
end record;
type addr_range_and_mapping_array is array (natural range <>) of addr_range_and_mapping_type;
constant BUS_MST2SLV_IDLE : bus_mst2slv_type := (
address => (others => '0'),
writeData => (others => '0'),
writeMask => (others => '0'),
readEnable => '0',
writeEnable => '0'
);
constant BUS_SLV2MST_IDLE : bus_slv2mst_type := (
readData => (others => '0'),
ack => '0',
fault => '0'
);
-- Returns true when the specified master is requesting something.
function bus_requesting(
b : bus_mst2slv_type
) return std_logic;
function bus_slave_finished(
b : bus_slv2mst_type
) return std_logic;
function bus_addr_in_range(
addr : bus_address_type;
addr_range : addr_range_type
) return boolean;
-- Mapping functions
function bus_map_range(
high : natural;
low : natural
) return bitMapping_array;
function bus_map_constant(
count : natural;
value : std_logic
) return bitMapping_array;
function address_range_and_map (
low : bus_address_type := (others => '0');
high : bus_address_type := (others => '1');
mapping : addrMapping_type := bus_map_range(bus_address_type'high, 0)
) return addr_range_and_mapping_type;
function bus_apply_addr_map(
addr : bus_address_type;
addrMap : addrMapping_type
) return bus_address_type;
end bus_pkg;
package body bus_pkg is
function bus_requesting(
b : bus_mst2slv_type
) return std_logic is
begin
return b.readEnable or b.writeEnable;
end bus_requesting;
function bus_slave_finished(
b : bus_slv2mst_type
) return std_logic is
begin
return b.ack or b.fault;
end bus_slave_finished;
function bus_addr_in_range (
addr : bus_address_type;
addr_range : addr_range_type
) return boolean is
begin
return unsigned(addr) >= unsigned(addr_range.low) and unsigned(addr) <= unsigned(addr_range.high);
end bus_addr_in_range;
function bus_map_range(
high : natural;
low : natural
) return bitMapping_array is
variable res : bitMapping_array(high-low downto 0);
begin
for i in res'range loop
res(i) := i + low;
end loop;
return res;
end bus_map_range;
function bus_map_constant(
count : natural;
value : std_logic
) return bitMapping_array is
variable res : bitMapping_array(count-1 downto 0);
begin
if value = '1' then
res := (others => -2); -- Code for '1'.
else
res := (others => -1); -- Code for '0'.
end if;
return res;
end bus_map_constant;
function address_range_and_map (
low : bus_address_type := (others => '0');
high : bus_address_type := (others => '1');
mapping : addrMapping_type := bus_map_range(bus_address_type'high, 0)
) return addr_range_and_mapping_type is
variable retval : addr_range_and_mapping_type;
begin
retval.addr_range := (
low => low,
high => high
);
retval.mapping := mapping;
return retval;
end address_range_and_map;
function bus_apply_addr_map(
addr : bus_address_type;
addrMap : addrMapping_type
) return bus_address_type is
variable res : bus_address_type;
begin
for i in res'range loop
if addrMap(i) = -2 then -- Code for '1'.
res(i) := '1';
elsif addrMap(i) = -1 then -- Code for '0'.
res(i) := '0';
else
res(i) := addr(addrMap(i));
end if;
end loop;
return res;
end bus_apply_addr_map;
end bus_pkg;
| mit | 75c3be1abd90a30965ff073ed0879b2e | 0.603149 | 3.757267 | false | false | false | false |
TheMassController/VHDL_experimenting | project/common/button_to_single_pulse.vhd | 1 | 2,752 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity button_to_single_pulse is
generic (
debounce_ticks : natural range 2 to natural'high
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
pulse_in : in STD_LOGIC;
pulse_out : out STD_LOGIC
);
end button_to_single_pulse;
architecture behavioral of button_to_single_pulse is
type state_type is (reset, wait_for_begin, debounce_begin, output, wait_for_end, debounce_end);
signal debounce_rst : STD_LOGIC := '1';
signal debounce_done : STD_LOGIC;
signal state : state_type := reset;
begin
debounce_ticker : entity work.simple_multishot_timer
generic map (
match_val => debounce_ticks
)
port map (
clk => clk,
rst => debounce_rst,
done => debounce_done
);
state_selector : process(clk, rst)
begin
if rst = '1' then
state <= reset;
elsif rising_edge(clk) then
case state is
when reset =>
state <= wait_for_begin;
when wait_for_begin =>
if pulse_in = '1' then
state <= debounce_begin;
else
state <= wait_for_begin;
end if;
when debounce_begin =>
if debounce_done = '1' then
state <= output;
else
state <= debounce_begin;
end if;
when output =>
state <= wait_for_end;
when wait_for_end =>
if pulse_in = '0' then
state <= debounce_end;
else
state <= wait_for_end;
end if;
when debounce_end =>
if debounce_done = '1' then
state <= wait_for_begin;
else
state <= debounce_end;
end if;
end case;
end if;
end process;
state_output : process(state)
begin
case state is
when reset|wait_for_begin|wait_for_end =>
debounce_rst <= '1';
pulse_out <= '0';
when debounce_begin|debounce_end =>
debounce_rst <= '0';
pulse_out <= '0';
when output =>
pulse_out <= '1';
debounce_rst <= '1';
end case;
end process;
end behavioral;
| mit | 3192f74be849dbafee777ddbd807bdac | 0.429142 | 4.680272 | false | false | false | false |
chastell/art-decomp | kiss/train11_hot.vhd | 1 | 3,633 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train11_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train11_hot;
architecture behaviour of train11_hot is
constant st0: std_logic_vector(10 downto 0) := "10000000000";
constant st1: std_logic_vector(10 downto 0) := "01000000000";
constant st2: std_logic_vector(10 downto 0) := "00100000000";
constant st3: std_logic_vector(10 downto 0) := "00010000000";
constant st5: std_logic_vector(10 downto 0) := "00001000000";
constant st7: std_logic_vector(10 downto 0) := "00000100000";
constant st9: std_logic_vector(10 downto 0) := "00000010000";
constant st4: std_logic_vector(10 downto 0) := "00000001000";
constant st6: std_logic_vector(10 downto 0) := "00000000100";
constant st8: std_logic_vector(10 downto 0) := "00000000010";
constant st10: std_logic_vector(10 downto 0) := "00000000001";
signal current_state, next_state: std_logic_vector(10 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----------"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st2; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st5; output <= "1";
end if;
when st2 =>
if std_match(input, "01") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "11") then next_state <= st9; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st4; output <= "1";
end if;
when st4 =>
if std_match(input, "01") then next_state <= st4; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st5 =>
if std_match(input, "11") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
end if;
when st6 =>
if std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st8; output <= "1";
end if;
when st8 =>
if std_match(input, "10") then next_state <= st8; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when st9 =>
if std_match(input, "11") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st10; output <= "1";
end if;
when st10 =>
if std_match(input, "10") then next_state <= st10; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "-----------"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 54c709cff4016e3afde1f6d386eface7 | 0.580787 | 3.320841 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/Control_ddr.vhd | 2 | 17,472 |
--------------------------------------------------------------------------------
-- Control unit for DDR implementation of Square AES - Low Area version
-- This architecture computes each round in only 3 clock cycles (regular
-- implementation needs 6), but it computes each round twice to provide
-- error detection.
-- ********************************************************************** ------
-- This version is simplified and tailored to the MARS project: hence, only
-- the following functionalities are supported:
-- *** Encryption only (no decryption support)
-- *** 128-bit keys only (no support for longer keys: key schedule should be re-designed)
-- *** ECB only (No feedback modes)
-- To provide extensibility, the interface includes all the required signals
-- anyway, but they are not used in the implementation
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
entity control_ddr is port (
go_crypt, go_key : in std_logic; -- active HIGH
encdec : in std_logic; -- 0=encrypt, 1=decrypt
-- key_size : in std_logic_vector( 1 downto 0 ); -- 01=128, 10=192, 11=256
ready_out : out T_READY; -- device state: S_READY or S_BUSY
data_out_ok : out T_ENABLE; -- Validity bit for the output
ctrl_dec : out T_ENCDEC; -- S_ENC / S_DEC
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : out T_ENABLE;
enable_SBox_sharing : out T_ENABLE;
ctrl_barrel : out std_logic_vector( 1 downto 0 ); --
next_roundkey, next_rcon, save_key : out T_ENABLE; -- Active HIGH
rewind_key : out T_ENABLE; -- Key rewinding; active according to config file
enable_main, enable_dual : out T_ENABLE; -- C_DISABLE / C_ENABLE
select_dual1, select_dual2 : out T_ENABLE; -- C_DISABLE / C_ENABLE
check_dual : out T_ENABLE;
control_error : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
reset, clk : in std_logic ); -- Global signals; active according to config file
end control_ddr;
-- Architecture of the Component
architecture arch of control_ddr is
signal s_go_crypt : std_logic; -- used to manage the start command
type T_STATE_HI is ( IDLE, ST_K1, ST_K2, ST_K3,
ST_R1A, ST_R2A, ST_R3A, ST_R1B, ST_R2B, ST_R3B, -- round computation (main and dual)
ST_F1A, ST_F2A, ST_F3A, ST_F1B, ST_F2B, ST_F3B ); -- final round (main and dual)
signal state_hi, prev_state_hi : T_STATE_HI; -- MAIN STATE REGISTER
signal s_data_out_ok : T_ENABLE; -- data output is sending actual result
signal s_ready_out : T_READY; -- device is ready (active) or busy (inactive)
signal s_ctrl_dec : T_ENCDEC; -- encryption/decryption flag; see aes_globals.vhd for details
signal s_enable_key_pre_add, s_enable_key_add, s_enable_MixCol, s_enable_H_in : T_ENABLE;
-- They enable, respectively: key addition during decryption; key addition during encryption;
-- computation of the MixColumns (inactive on last round); loading of data (active only at I/O)
signal s_ctrl_barrel_high : std_logic_vector( 1 downto 0 ); -- Shiftrow control for positive FFs
signal s_next_key, s_next_rcon, s_save_key : T_ENABLE; -- Key-related controls
signal s_reset_key : T_ENABLE; -- It restore first round key, activated at the end of computation
signal s_enable_main, s_enable_dual, s_select_dual1 : T_ENABLE;
-- load flags for main and backup registers, and copy selection signal
signal s_start_low_fsm, s_stop_low_fsm : T_ENABLE; -- Synchronization signals between High and Low FSM
-----------------------------------------------------------------------------------------
type T_STATE_LO is ( IDLE,
ST_R1, ST_R2, ST_R3, ST_R4, ST_R5, ST_R6 );
signal state_lo, prev_state_lo : T_STATE_LO; -- Negative edge triggered FSM
signal s_enable_SBox_sharing : T_ENABLE; -- Whene enables, Sbox accepts input from key scheduler
signal s_ctrl_barrel_low : std_logic_vector( 1 downto 0 ); -- Shiftrow control for negative FFs
signal s_select_dual2 : T_ENABLE;
signal s_check_dual : T_ENABLE; -- Enable DDR comparison
-----------------------------------------------------------------------------------------
signal s_iter, s_bkp_iter : integer range 0 to 14; -- variable: current round number
signal error_hi, error_lo, s_control_error, s_misc_error : std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
begin
LOW_FSM : process( reset, clk, error_hi, error_lo )
begin
if ( reset=RESET_ACTIVE or error_hi=C_BROKEN or error_lo=C_BROKEN ) then
state_lo <= IDLE;
prev_state_lo <= IDLE;
s_check_dual <= C_DISABLE;
elsif ( clk'event and clk='0' ) then
prev_state_lo <= state_lo;
case state_lo is
when IDLE => if ( s_start_low_fsm=C_ENABLE ) then
state_lo <= ST_R1; --* ST_L1;
else
state_lo <= IDLE;
end if;
s_check_dual <= C_DISABLE;
--------------------------------------------
when ST_R1 => if ( s_stop_low_fsm=C_ENABLE ) then
state_lo <= IDLE;
else
state_lo <= ST_R2;
end if;
s_check_dual <= C_DISABLE;
when ST_R2 => state_lo <= ST_R3;
s_check_dual <= C_DISABLE;
when ST_R3 => state_lo <= ST_R4;
s_check_dual <= C_DISABLE;
when ST_R4 => state_lo <= ST_R5;
s_check_dual <= C_DISABLE;
when ST_R5 => state_lo <= ST_R6;
s_check_dual <= C_DISABLE;
when ST_R6 => state_lo <= ST_R1;
s_check_dual <= C_ENABLE;
when others => state_lo <= IDLE;
end case;
s_go_crypt <= go_crypt; --*!
end if; -- reset, clk
end process LOW_FSM;
s_select_dual2 <= C_ENABLE when ( state_lo=ST_R4 or state_lo=ST_R5 or state_lo=ST_R6 )
else C_DISABLE;
s_enable_SBox_sharing <= C_ENABLE when (
( state_lo=IDLE and s_start_low_fsm=C_ENABLE )
or ( state_lo=IDLE and state_hi=IDLE and s_ctrl_dec=C_DEC )
or state_lo=ST_R6 or ( state_hi=ST_K1 and state_lo=IDLE ) )
else C_DISABLE; --*
HIGH_FSM : process ( reset, clk, error_hi, error_lo )
begin
if ( reset=RESET_ACTIVE or error_hi=C_BROKEN or error_lo=C_BROKEN ) then
s_iter <= 10; s_bkp_iter <= 10;
state_hi <= IDLE;
prev_state_hi <= IDLE;
s_ctrl_dec <= C_ENC;
s_enable_main <= C_ENABLE;
s_enable_dual <= C_ENABLE;
elsif(clk'event and clk='1') then
prev_state_hi <= state_hi;
case state_hi is
when IDLE =>
s_iter <= 10;
s_bkp_iter <= 10;
if ( go_key='1' ) then -- loading the key
s_ctrl_dec <= C_ENC;
if ( encdec='1' ) then -- if loading key for decryption, start unrolling
state_hi <= ST_K1;
s_enable_main <= C_DISABLE;
s_enable_dual <= C_DISABLE;
end if;
elsif ( s_go_crypt='1' ) then -- start computation process (enc/dec)
state_hi <= ST_R1A;
s_enable_main <= C_ENABLE;
s_enable_dual <= C_DISABLE;
else -- no go_key, no_go_crypt
state_hi <= IDLE;
s_enable_main <= C_ENABLE;
s_enable_dual <= C_ENABLE;
end if; -- go_key, go_crypt
--------------------------------------------------------------------------------
-- KEY UNROLLING
when ST_K1 =>
if ( s_iter=0 ) then
state_hi <= IDLE;
s_ctrl_dec <= C_DEC;
s_enable_main <= C_ENABLE;
s_enable_dual <= C_ENABLE;
else
state_hi <= ST_K2;
end if;
when ST_K2 =>
s_iter <= s_iter-1;
s_bkp_iter <= s_bkp_iter-1;
state_hi <= ST_K3;
when ST_K3 =>
state_hi <= ST_K1;
--------------------------------------------------------------------------------
-------------------------------- STANDARD ROUND --------------------------------
when ST_R1A =>
s_enable_main <= C_ENABLE;
s_enable_dual <= C_DISABLE;
state_hi <= ST_R2A;
when ST_R2A =>
s_enable_main <= C_ENABLE;
s_enable_dual <= C_DISABLE;
state_hi <= ST_R3A;
when ST_R3A =>
s_enable_main <= C_DISABLE;
s_enable_dual <= C_ENABLE;
state_hi <= ST_R1B;
when ST_R1B =>
s_enable_main <= C_DISABLE;
s_enable_dual <= C_ENABLE;
state_hi <= ST_R2B;
when ST_R2B =>
s_enable_main <= C_DISABLE;
s_enable_dual <= C_ENABLE;
s_iter <= s_iter-1;
s_bkp_iter <= s_bkp_iter-1;
state_hi <= ST_R3B;
when ST_R3B =>
s_enable_main <= C_ENABLE;
s_enable_dual <= C_DISABLE;
if ( s_iter=1 ) then
state_hi <= ST_F1A;
else
state_hi <= ST_R1A;
end if;
-------------------------------------------------------------------------------
----------------------------------- FINAL ROUND -------------------------------
when ST_F1A =>
s_enable_main <= C_ENABLE;
s_enable_dual <= C_DISABLE;
state_hi <= ST_F2A;
when ST_F2A =>
s_enable_main <= C_ENABLE;
s_enable_dual <= C_DISABLE;
state_hi <= ST_F3A;
when ST_F3A =>
s_enable_main <= C_DISABLE;
s_enable_dual <= C_ENABLE;
state_hi <= ST_F1B;
when ST_F1B =>
s_enable_main <= C_DISABLE;
s_enable_dual <= C_ENABLE;
state_hi <= ST_F2B;
when ST_F2B =>
s_enable_main <= C_DISABLE;
s_enable_dual <= C_ENABLE;
s_iter <= s_iter-1;
s_bkp_iter <= s_bkp_iter-1;
state_hi <= ST_F3B;
when ST_F3B =>
s_enable_main <= C_ENABLE;
s_enable_dual <= C_ENABLE;
state_hi <= IDLE;
---------------------------------------- ERROR --------------------------------
when others => state_hi <= IDLE;
end case;
end if;
end process;
s_ready_out <= C_READY when ( state_hi=IDLE ) else C_BUSY;
s_enable_H_in <= C_ENABLE when ( state_hi=IDLE ) else C_DISABLE;
s_enable_key_pre_add <= C_ENABLE
when ( state_hi=ST_R3A or state_hi=ST_R3B ) and ( s_ctrl_dec=C_DEC )
else C_DISABLE;
s_enable_key_add <= C_ENABLE
when ( state_hi=IDLE and go_crypt='1' )
or ( ( state_hi=ST_R3A or state_hi=ST_R3B ) and ( s_ctrl_dec=C_ENC ) )
or ( state_hi=ST_F3A or state_hi=ST_F3B )
else C_DISABLE;
s_enable_MixCol <= C_ENABLE when ( state_hi=ST_R3A or state_hi=ST_R3B )
else C_DISABLE;
s_start_low_fsm <= C_ENABLE when ( state_hi=IDLE and go_crypt='1' )
else C_DISABLE;
s_stop_low_fsm <= C_ENABLE when ( state_hi=IDLE and prev_state_hi=ST_F3B )
else C_DISABLE;
s_next_key <= C_ENABLE
when ( ( state_hi=IDLE and go_crypt='1' )
or state_hi=ST_R3B or (state_hi=ST_K1 and s_iter<10) )
else C_DISABLE;
s_next_rcon <= C_ENABLE
when ( ( state_hi=IDLE and go_crypt='1' )
or state_hi=ST_R3B or (state_hi=ST_K1 and s_iter<10 and s_iter>0) )
else C_DISABLE;
s_save_key <= C_ENABLE when ( state_hi=IDLE and go_crypt='1' ) --*
else C_DISABLE;
s_reset_key <= C_ENABLE when ( state_hi=ST_F3B and prev_state_hi=ST_F2B )
else C_DISABLE;
s_select_dual1 <= C_ENABLE when ( state_hi=ST_R1B or state_hi=ST_R2B or state_hi=ST_R3B
or state_hi=ST_F1B or state_hi=ST_F2B or state_hi=ST_F3B )
else C_DISABLE;
dec0 : if ( not C_INCLUDE_DECODING_LOGIC ) generate
s_ctrl_barrel_high <= "11" when ( state_hi=ST_R1A or state_hi=ST_R1B or
state_hi=ST_F1A or state_hi=ST_F1B )
else "01" when ( state_hi=ST_R2A or state_hi=ST_R2B or
state_hi=ST_F2A or state_hi=ST_F2B )
else "00";
end generate; -- not C_INCLUDE_DECODING_LOGIC
dec1 : if ( C_INCLUDE_DECODING_LOGIC ) generate --*
s_ctrl_barrel_high <= "11" when ( ( state_hi=ST_R1A or state_hi=ST_R1B or
state_hi=ST_F1A or state_hi=ST_F1B ) and s_ctrl_dec=C_ENC ) or
( ( state_hi=ST_R2A or state_hi=ST_R2B or state_hi=ST_F2A or
state_hi=ST_F2B ) and s_ctrl_dec=C_DEC )
else "01" when ( ( state_hi=ST_R2A or state_hi=ST_R2B or
state_hi=ST_F2A or state_hi=ST_F2B ) and s_ctrl_dec=C_ENC ) or
( ( state_hi=ST_R1A or state_hi=ST_R1B or state_hi=ST_F1A or
state_hi=ST_F1B ) and s_ctrl_dec=C_DEC )
else "00";
end generate; -- C_INCLUDE_DECODING_LOGIC
s_ctrl_barrel_low <= "10" when ( state_hi=ST_R1A or state_hi=ST_R1B or
state_hi=ST_F1A or state_hi=ST_F1B )
else "00";
s_data_out_ok <= C_ENABLE when ( prev_state_hi=ST_F3B )
else C_DISABLE;
---- Managing faults in controller; commented in order to have vulnerable controller on purpose
------------------------------------------------------------------------------------------------
-- ERROR_FSM_LO : process( reset, clk )
-- begin
-- if ( reset = RESET_ACTIVE ) then
-- error_lo <= not C_BROKEN;
-- elsif ( clk='1' and clk'event ) then
-- -- check for proper state sequence:
-- if ( state_lo=IDLE and not ( prev_state_lo=IDLE or prev_state_lo=ST_R1 ) ) or
-- ( state_lo=ST_R1 and not ( prev_state_lo=IDLE or prev_state_lo=ST_R6 ) ) or
-- ( state_lo=ST_R2 and prev_state_lo/=ST_R1 ) or
-- ( state_lo=ST_R3 and prev_state_lo/=ST_R2 ) or
-- ( state_lo=ST_R4 and prev_state_lo/=ST_R3 ) or
-- ( state_lo=ST_R5 and prev_state_lo/=ST_R4 ) or
-- ( state_lo=ST_R6 and prev_state_lo/=ST_R5 ) then
-- error_lo <= C_BROKEN;
-- end if; -- check for proper state sequence
-- end if; -- reset, clk
-- end process ERROR_FSM_LO;
-- ERROR_FSM_HI : process( reset, clk )
-- begin
-- if ( reset = RESET_ACTIVE ) then
-- error_hi <= not C_BROKEN;
-- elsif ( clk='0' and clk'event ) then
-- -- check for proper state sequence:
-- if ( state_hi=IDLE and not ( prev_state_hi=IDLE or prev_state_hi=ST_K1 or prev_state_hi=ST_F3B ) ) or
-- ( state_hi=ST_K1 and not ( prev_state_hi=IDLE or prev_state_hi=ST_K3 ) ) or
-- ( state_hi=ST_K2 and prev_state_hi/=ST_K1 ) or
-- ( state_hi=ST_K3 and prev_state_hi/=ST_K2 ) or
-- ( state_hi=ST_R1A and not ( prev_state_hi=IDLE or prev_state_hi=ST_R3B ) ) or
-- ( state_hi=ST_R2A and prev_state_hi/=ST_R1A ) or
-- ( state_hi=ST_R3A and prev_state_hi/=ST_R2A ) or
-- ( state_hi=ST_R1B and prev_state_hi/=ST_R3A ) or
-- ( state_hi=ST_R2B and prev_state_hi/=ST_R1B ) or
-- ( state_hi=ST_R3B and prev_state_hi/=ST_R2B ) or
-- ( state_hi=ST_F1A and prev_state_hi/=ST_R3B ) or
-- ( state_hi=ST_F2A and prev_state_hi/=ST_F1A ) or
-- ( state_hi=ST_F3A and prev_state_hi/=ST_F2A ) or
-- ( state_hi=ST_F1B and prev_state_hi/=ST_F3A ) or
-- ( state_hi=ST_F2B and prev_state_hi/=ST_F1B ) or
-- ( state_hi=ST_F3B and prev_state_hi/=ST_F2B )
-- then error_hi <= C_BROKEN;
-- end if; -- check for proper state sequence:
-- end if; -- reset, clk
-- end process ERROR_FSM_HI;
--
-- s_misc_error <= not C_BROKEN --
-- when -- ( s_data_out_ok=C_ENABLE or s_data_out_ok=C_DISABLE ) and
-- -- ( s_ready_out=S_READY or s_ready_out=S_BUSY ) and
-- ( s_ctrl_dec=C_ENC or s_ctrl_dec=C_DEC ) and
-- ( s_enable_main=C_ENABLE or s_enable_main=C_DISABLE ) and
-- ( s_enable_dual=C_ENABLE or s_enable_dual=C_DISABLE ) and
-- ( s_check_dual=C_ENABLE or s_check_dual=C_DISABLE ) and
-- ( s_enable_SBox_sharing=C_ENABLE or s_enable_SBox_sharing=C_DISABLE ) and
-- ( s_bkp_iter=s_iter ) and
-- ( ( state_lo=IDLE and ( state_hi=IDLE or state_hi=ST_K1 or state_hi=ST_K2 or state_hi=ST_K3 ) )
-- or state_lo/=IDLE )
-- else C_BROKEN;
-- ERR_PROC: process( clk, reset )
-- begin
-- if ( reset=RESET_ACTIVE ) then
-- s_control_error <= not C_BROKEN;
-- elsif ( clk'event and clk='1' ) then
-- if ( s_misc_error /= not C_BROKEN ) or ( error_hi /= not C_BROKEN ) or
-- ( error_lo /= not C_BROKEN ) then
-- s_control_error <= C_BROKEN;
-- end if;
-- end if;
-- end process ERR_PROC;
-- s_control_error <= not C_BROKEN when ( s_misc_error = not C_BROKEN ) and
-- ( error_hi = not C_BROKEN ) and ( error_lo = not C_BROKEN )
-- else C_BROKEN;
ready_out <= s_ready_out;
data_out_ok <= s_data_out_ok;
ctrl_dec <= s_ctrl_dec;
enable_key_pre_add <= s_enable_key_pre_add;
enable_key_add <= s_enable_key_add;
enable_MixCol <= s_enable_MixCol;
enable_H_in <= s_enable_H_in;
enable_SBox_sharing <= s_enable_SBox_sharing;
next_roundkey <= s_next_key;
next_rcon <= s_next_rcon;
rewind_key <= s_reset_key;
save_key <= s_save_key;
ctrl_barrel <= s_ctrl_barrel_high when ( clk='1' ) else s_ctrl_barrel_low;
enable_main <= s_enable_main;
enable_dual <= s_enable_dual;
select_dual1 <= s_select_dual1;
select_dual2 <= s_select_dual2;
check_dual <= s_check_dual;
control_error <= not C_BROKEN; -- s_control_error; --
end arch;
| mit | 380b55639fdc613177fa7b971d17a059 | 0.537603 | 3.095128 | false | false | false | false |
chastell/art-decomp | kiss/s8_nov.vhd | 1 | 2,612 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s8_nov is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s8_nov;
architecture behaviour of s8_nov is
constant s1: std_logic_vector(2 downto 0) := "001";
constant s2: std_logic_vector(2 downto 0) := "000";
constant s3: std_logic_vector(2 downto 0) := "110";
constant s4: std_logic_vector(2 downto 0) := "111";
constant s5: std_logic_vector(2 downto 0) := "010";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s1 =>
if std_match(input, "1000") then next_state <= s1; output <= "1";
elsif std_match(input, "0100") then next_state <= s1; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s2; output <= "1";
end if;
when s2 =>
if std_match(input, "1000") then next_state <= s2; output <= "1";
elsif std_match(input, "0100") then next_state <= s3; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s1; output <= "1";
end if;
when s3 =>
if std_match(input, "1000") then next_state <= s3; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s5; output <= "1";
end if;
when s4 =>
if std_match(input, "1000") then next_state <= s4; output <= "1";
elsif std_match(input, "0100") then next_state <= s2; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s3; output <= "1";
end if;
when s5 =>
if std_match(input, "1000") then next_state <= s5; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s1; output <= "1";
elsif std_match(input, "0001") then next_state <= s4; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 2e2ba2a35a5bf423a4472746c113ced0 | 0.582695 | 3.20098 | false | false | false | false |
chastell/art-decomp | kiss/ex4_nov.vhd | 1 | 3,706 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex4_nov is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(8 downto 0)
);
end ex4_nov;
architecture behaviour of ex4_nov is
constant s1: std_logic_vector(3 downto 0) := "0010";
constant s3: std_logic_vector(3 downto 0) := "1101";
constant s2: std_logic_vector(3 downto 0) := "0011";
constant s5: std_logic_vector(3 downto 0) := "1100";
constant s7: std_logic_vector(3 downto 0) := "0000";
constant s11: std_logic_vector(3 downto 0) := "1111";
constant s12: std_logic_vector(3 downto 0) := "0001";
constant s8: std_logic_vector(3 downto 0) := "1110";
constant s4: std_logic_vector(3 downto 0) := "0110";
constant s13: std_logic_vector(3 downto 0) := "1001";
constant s14: std_logic_vector(3 downto 0) := "0111";
constant s6: std_logic_vector(3 downto 0) := "1000";
constant s9: std_logic_vector(3 downto 0) := "0100";
constant s10: std_logic_vector(3 downto 0) := "1011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---------";
case current_state is
when s1 =>
if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
end if;
when s3 =>
if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
end if;
when s2 =>
if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
end if;
when s5 =>
if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
end if;
when s7 =>
if std_match(input, "10----") then next_state <= s7; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
end if;
when s11 =>
if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
end if;
when s12 =>
if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
end if;
when s8 =>
if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
end if;
when s4 =>
if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
end if;
when s13 =>
if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
end if;
when s14 =>
if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
end if;
when s6 =>
if std_match(input, "10----") then next_state <= s6; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
end if;
when s9 =>
if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
end if;
when s10 =>
if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
end if;
when others => next_state <= "----"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 22e9ff19346dddc309e584fc22d813c6 | 0.568268 | 3.338739 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-03A.vhd | 1 | 11,249 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03A.vhd
-- Creation Date:
-- Description:
-- Priority (microcode interruptions)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change Priority Reset latch signal name
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY Priority IS
port
(
-- Inputs
RECYCLE_RST : IN STD_LOGIC; -- 04A
S_REG_1_BIT : IN STD_LOGIC; -- 07B
SALS_CDREG : IN STD_LOGIC_VECTOR(0 to 3); -- 01A?
MACH_RST_SW : IN STD_LOGIC; -- 03D
DATA_READY_1 : IN STD_LOGIC; -- 05D
DATA_READY_2 : IN STD_LOGIC; -- ???
MEM_WRAP_REQ : IN STD_LOGIC; -- 03B
ALLOW_PROTECT : IN STD_LOGIC; -- 06C
PROT_LOC_CPU_OR_MPX : IN STD_LOGIC; -- 08B
READ_CALL : IN STD_LOGIC; -- 05D
XOR_OR_OR : IN STD_LOGIC; -- 02A
CTRL_N : IN STD_LOGIC; -- 06B
STOP_REQ : IN STD_LOGIC; -- 03C
SUPPR_A_REG_CHK : IN STD_LOGIC; -- 07A
H_REG_5_PWR : IN STD_LOGIC; -- 04C
SEL_ROS_REQ : IN STD_LOGIC; -- 12C
FT_3_MPX_SHARE_REQ : IN STD_LOGIC; -- 08D
H_REG_6 : IN STD_LOGIC; -- 04C
P_8F_DETECTED : IN STD_LOGIC; -- 06C
LOAD_IND : IN STD_LOGIC; -- 03C
FORCE_IJ_REQ : IN STD_LOGIC; -- 04A
FIRST_MACH_CHK_REQ : IN STD_LOGIC; -- 07A
MACH_RST_6 : IN STD_LOGIC; -- 03D
ALLOW_WRITE : IN STD_LOGIC; -- 03D
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04A
DIAGNOSTIC_SW : IN STD_LOGIC; -- 04A
MACH_RST_LCH : IN STD_LOGIC; -- 04A
HARD_STOP_LCH : IN STD_LOGIC; -- 03C
R_REG_5 : IN STD_LOGIC; -- 06C
H : IN STD_LOGIC_VECTOR(0 to 7); -- 04C
FORCE_DEAD_CY_LCH : IN STD_LOGIC; -- 04A
-- Outputs
SUPPR_MACH_CHK_TRAP : OUT STD_LOGIC; -- 03C,04A,07A
ANY_PRIORITY_PULSE_2 : OUT STD_LOGIC; -- 03B,04D
ANY_PRIORITY_LCH : OUT STD_LOGIC; -- 04A,07A
S_REG_1_DLYD : OUT STD_LOGIC; -- 03C
GT_SW_TO_WX_LCH : OUT STD_LOGIC; -- 04A
DATA_READY : OUT STD_LOGIC; -- 06C
MEM_PROTECT_REQ : OUT STD_LOGIC; -- 07A
HZ_DEST_RST : OUT STD_LOGIC; -- 03C,04A
GT_SW_MACH_RST : OUT STD_LOGIC; -- 05A
GT_SWS_TO_WX_LCH : OUT STD_LOGIC; -- 01B
FORCE_IJ_REQ_LCH : OUT STD_LOGIC; -- 03C,04A,04B
SYS_RST_PRIORITY_LCH :OUT STD_LOGIC; -- 06B
MACH_CHK_PULSE : OUT STD_LOGIC; -- 03C,07A
FORCE_IJ_PULSE : OUT STD_LOGIC; -- 04A
SX_CHAIN_PULSE_1 : OUT STD_LOGIC; -- 12C
ANY_PRIORITY_PULSE : OUT STD_LOGIC; -- 01C,01B,02B,04C,11C
ANY_PRIORITY_PULSE_PWR : OUT STD_LOGIC; -- 01B,03C
PRIORITY_BUS : OUT STD_LOGIC_VECTOR(0 to 7); -- 01B
PRIORITY_BUS_P : OUT STD_LOGIC;
-- Clocks
T1 : IN STD_LOGIC;
T3 : IN STD_LOGIC;
T4 : IN STD_LOGIC;
P4 : IN STD_LOGIC;
CLK : IN STD_LOGIC
);
END Priority;
ARCHITECTURE FMD OF Priority IS
-- Priority Bus assignments
signal sPRIORITY_BUS : STD_LOGIC_VECTOR(0 to 7);
alias STOP_PULSE : STD_LOGIC is sPRIORITY_BUS(0);
alias PROTECT_PULSE : STD_LOGIC is sPRIORITY_BUS(1);
alias WRAP_PULSE : STD_LOGIC is sPRIORITY_BUS(2);
alias MPX_SHARE_PULSE : STD_LOGIC is sPRIORITY_BUS(3);
alias SX_CHAIN_PULSE : STD_LOGIC is sPRIORITY_BUS(4);
alias PB_MACH_CHK_PULSE : STD_LOGIC is sPRIORITY_BUS(5);
alias IPL_PULSE : STD_LOGIC is sPRIORITY_BUS(6);
alias PB_FORCE_IJ_PULSE : STD_LOGIC is sPRIORITY_BUS(7);
signal CD0101 : STD_LOGIC;
signal PRIOR_RST_CTRL : STD_LOGIC;
signal PRIORITY_LCH : STD_LOGIC;
signal FIRST_MACH_CHK_LCH : STD_LOGIC;
signal LOAD_REQ_LCH : STD_LOGIC;
signal MEM_WRAP_REQ_LCH : STD_LOGIC;
signal MEM_PROTECT_LCH : STD_LOGIC;
signal STOP_REQ_LCH : STD_LOGIC;
signal SEL_CHAIN_REQ_LCH : STD_LOGIC;
signal MPX_SHARE_REQ_LCH : STD_LOGIC;
signal HI_PRIORITY : STD_LOGIC;
signal PRIORITY_STACK_IN, PRIORITY_STACK_OUT : STD_LOGIC_VECTOR(0 to 8);
signal sSUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal sANY_PRIORITY_PULSE_2 : STD_LOGIC;
signal sANY_PRIORITY_LCH : STD_LOGIC;
signal sGT_SW_TO_WX_LCH : STD_LOGIC;
signal sDATA_READY : STD_LOGIC;
signal sMEM_PROTECT_REQ : STD_LOGIC;
signal sHZ_DEST_RST : STD_LOGIC;
signal sGT_SW_MACH_RST : STD_LOGIC;
signal sGT_SWS_TO_WX_LCH : STD_LOGIC;
signal sFORCE_IJ_REQ_LCH : STD_LOGIC;
signal sSYS_RST_PRIORITY_LCH : STD_LOGIC;
signal sMACH_CHK_PULSE : STD_LOGIC;
signal sFORCE_IJ_PULSE : STD_LOGIC;
signal sANY_PRIORITY_PULSE : STD_LOGIC;
signal sMPX_SHARE_PULSE : STD_LOGIC;
signal SUPPR_MACH_TRAP_L,PRIOR_RST_Latch,MEMP_LCH_Set,MEMP_LCH_Reset,PRI_LCH_Set,
PRI_LCH_Reset,PRISTK_LCH_Latch : STD_LOGIC;
BEGIN
-- Fig 5-03A
SUPPR_MACH_TRAP_L <= XOR_OR_OR and CTRL_N and T3;
SUPPR_MALF_TRAP_LCH: PHR port map(not R_REG_5,SUPPR_MACH_TRAP_L,RECYCLE_RST,sSUPPR_MACH_CHK_TRAP); -- AB3D2,AB3J2
-- ?? SUPPR_MACH_CHK_TRAP is from the output of the PH and not from its reset input ??
SUPPR_MACH_CHK_TRAP <= sSUPPR_MACH_CHK_TRAP; -- ??
-- SUPPR_MACH_CHK_TRAP <= not RECYCLE_RST; -- ??
sANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE; -- AB3D7
ANY_PRIORITY_PULSE_2 <= sANY_PRIORITY_PULSE_2;
ANY_PRIORITY: entity work.PH port map(sANY_PRIORITY_PULSE_2,T1,sANY_PRIORITY_LCH); -- AB3D7,AB3J2
ANY_PRIORITY_LCH <= sANY_PRIORITY_LCH;
S1_DLYD: entity work.PH port map(S_REG_1_BIT,T1,S_REG_1_DLYD); -- AB3J2
WX_SABC: entity work.PH port map(sGT_SWS_TO_WX_LCH,T1,sGT_SW_TO_WX_LCH); -- AB3J2
GT_SW_TO_WX_LCH <= sGT_SW_TO_WX_LCH;
CD0101 <= '1' when SALS_CDREG="0101" else '0';
PRIOR_RST_Latch <= T4 or MACH_RST_SW;
PRIOR_RST_CTRL_PH: entity work.PHR port map(D=>CD0101,L=>PRIOR_RST_Latch,R=>sANY_PRIORITY_PULSE,Q=>PRIOR_RST_CTRL); -- AB3J2
MEMP_LCH_Set <= sDATA_READY and ALLOW_PROTECT and PROT_LOC_CPU_OR_MPX;
MEMP_LCH_Reset <= READ_CALL or RECYCLE_RST;
STG_PROT_REQ: entity work.FLL port map(MEMP_LCH_Set,MEMP_LCH_Reset,sMEM_PROTECT_REQ); -- AA1K7
MEM_PROTECT_REQ <= sMEM_PROTECT_REQ;
sHZ_DEST_RST <= (P4 and sGT_SW_TO_WX_LCH) or (T3 and PRIOR_RST_CTRL); -- AB3K5,AB3J4
HZ_DEST_RST <= sHZ_DEST_RST;
sGT_SW_MACH_RST <= MACH_RST_6 or GT_SWS_TO_WX_PWR; -- AB3J3 ??
GT_SW_MACH_RST <= sGT_SW_MACH_RST;
sDATA_READY <= (DATA_READY_1 or DATA_READY_2) and not MEM_WRAP_REQ; -- AA1J6 AA1J4
DATA_READY <= sDATA_READY;
PRI_LCH_Set <= (T1 and DIAGNOSTIC_SW) or MACH_RST_LCH or (not HARD_STOP_LCH and T3 and sANY_PRIORITY_LCH);
PRI_LCH_Reset <= sHZ_DEST_RST or sGT_SW_MACH_RST;
PRIORITY: entity work.FLL port map(S=>PRI_LCH_Set,R=>PRI_LCH_Reset,Q=>PRIORITY_LCH); -- AB3J4,AB3L4
-- Priority stack register - all inputs are inverted AB3L2
PRIORITY_STACK_IN(0) <= GT_SWS_TO_WX_PWR;
PRIORITY_STACK_IN(1) <= FIRST_MACH_CHK_REQ;
PRIORITY_STACK_IN(2) <= P_8F_DETECTED or LOAD_IND;
PRIORITY_STACK_IN(3) <= FORCE_IJ_REQ;
PRIORITY_STACK_IN(4) <= MEM_WRAP_REQ;
PRIORITY_STACK_IN(5) <= sMEM_PROTECT_REQ;
PRIORITY_STACK_IN(6) <= STOP_REQ;
PRIORITY_STACK_IN(7) <= SUPPR_A_REG_CHK and not H_REG_5_PWR and SEL_ROS_REQ;
PRIORITY_STACK_IN(8) <= FT_3_MPX_SHARE_REQ and not H_REG_6 and not H_REG_5_PWR;
PRISTK_LCH_Latch <= MACH_RST_6 or (not ALLOW_WRITE and T3) or (P4 and GT_SWS_TO_WX_PWR);
PRISTK_LCH: entity work.PHV9 port map( D => PRIORITY_STACK_IN,
L => PRISTK_LCH_Latch,
Q => PRIORITY_STACK_OUT);
sGT_SWS_TO_WX_LCH <= PRIORITY_STACK_OUT(0);
GT_SWS_TO_WX_LCH <= sGT_SWS_TO_WX_LCH;
FIRST_MACH_CHK_LCH <= PRIORITY_STACK_OUT(1);
LOAD_REQ_LCH <= PRIORITY_STACK_OUT(2);
sFORCE_IJ_REQ_LCH <= PRIORITY_STACK_OUT(3);
FORCE_IJ_REQ_LCH <= sFORCE_IJ_REQ_LCH;
MEM_WRAP_REQ_LCH <= PRIORITY_STACK_OUT(4);
MEM_PROTECT_LCH <= PRIORITY_STACK_OUT(5);
STOP_REQ_LCH <= PRIORITY_STACK_OUT(6);
SEL_CHAIN_REQ_LCH <= PRIORITY_STACK_OUT(7);
MPX_SHARE_REQ_LCH <= PRIORITY_STACK_OUT(8);
-- HI priorities AB3K3
sMACH_CHK_PULSE <= not sSUPPR_MACH_CHK_TRAP and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and FIRST_MACH_CHK_LCH; -- ?? SUPPRESS_MACH_CHECK_TRAP should be inverted ??
MACH_CHK_PULSE <= sMACH_CHK_PULSE;
PB_MACH_CHK_PULSE <= sMACH_CHK_PULSE;
IPL_PULSE <= not sMACH_CHK_PULSE and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and LOAD_REQ_LCH and not H(0);
sFORCE_IJ_PULSE <= not IPL_PULSE and not sMACH_CHK_PULSE and not sGT_SWS_TO_WX_LCH and not PRIORITY_LCH and sFORCE_IJ_REQ_LCH and not H(4);
FORCE_IJ_PULSE <= sFORCE_IJ_PULSE;
PB_FORCE_IJ_PULSE <= sFORCE_IJ_PULSE;
WRAP_PULSE <= not sFORCE_IJ_PULSE and not PRIORITY_LCH and not sGT_SWS_TO_WX_LCH and not IPL_PULSE and not sMACH_CHK_PULSE and MEM_WRAP_REQ_LCH and not H(2);
HI_PRIORITY <= FORCE_DEAD_CY_LCH or sGT_SWS_TO_WX_LCH or sMACH_CHK_PULSE or IPL_PULSE or sFORCE_IJ_PULSE or WRAP_PULSE; -- AB3K3
PRIORITY_BUS <= sPRIORITY_BUS;
-- LO priorities AB3K4
PROTECT_PULSE <= not HI_PRIORITY and not PRIORITY_LCH and MEM_PROTECT_LCH and not H(3);
STOP_PULSE <= not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and STOP_REQ_LCH;
SX_CHAIN_PULSE <= not STOP_PULSE and not PROTECT_PULSE and not HI_PRIORITY and not PRIORITY_LCH and SEL_CHAIN_REQ_LCH and not H(5);
SX_CHAIN_PULSE_1 <= SX_CHAIN_PULSE;
sMPX_SHARE_PULSE <= not SX_CHAIN_PULSE and not STOP_PULSE and not PROTECT_PULSE and not PRIORITY_LCH and not HI_PRIORITY and MPX_SHARE_REQ_LCH and not (H(5) or H(6)); -- ??
MPX_SHARE_PULSE <= sMPX_SHARE_PULSE;
SRP_LCH: entity work.FLL port map(MACH_RST_SW,T4,sSYS_RST_PRIORITY_LCH); -- AB3L3
SYS_RST_PRIORITY_LCH <= sSYS_RST_PRIORITY_LCH;
sANY_PRIORITY_PULSE <= sMPX_SHARE_PULSE or SX_CHAIN_PULSE or STOP_PULSE or PROTECT_PULSE or HI_PRIORITY or sSYS_RST_PRIORITY_LCH; -- AB3K4 ??
ANY_PRIORITY_PULSE <= sANY_PRIORITY_PULSE;
ANY_PRIORITY_PULSE_PWR <= sANY_PRIORITY_PULSE and not MACH_RST_SW; -- AB3D4
PRIORITY_BUS_P <= (sSYS_RST_PRIORITY_LCH or FORCE_DEAD_CY_LCH) and not GT_SWS_TO_WX_PWR; -- AB3H5 ??
END FMD;
| gpl-3.0 | a5fc2c98496859eb9280a35ad123c520 | 0.652502 | 2.844967 | false | false | false | false |
thommyj/slotcar | de0/uart_rx.vhd | 1 | 5,510 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity rxuart is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : buffer std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in_ext : in std_logic
);
end entity rxuart;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of rxuart is
type clkstate_type is (BAUDRATE_CLK_ON, BAUDRATE_CLK_OFF);
signal uart_clk_re : std_logic;
signal clkstate : clkstate_type;
signal start_baudrate_clk : std_logic;
signal uart_data_in_meta : std_logic_vector(1 downto 0);
signal uart_data_in : std_logic;
begin
--
-- metastability
--
process (clk,rst)
begin
if rst = '1' then
uart_data_in_meta <= "11";
elsif rising_edge(clk) then
uart_data_in_meta <= uart_data_in_meta(0) & uart_data_in_ext;
end if;
end process;
uart_data_in <= uart_data_in_meta(1);
--
--sync in to middle of startbit
--
process (clk,rst)
variable zero_cnt : integer := 0;
begin
if rst = '1' then
zero_cnt := 0;
elsif rising_edge(clk) then
if uart_data_in = '0' then
zero_cnt := zero_cnt + 1;
else
zero_cnt := 0;
end if;
if zero_cnt = 1302 then
start_baudrate_clk <= '1';
else
start_baudrate_clk <= '0';
end if;
end if;
end process;
--
--produce a pulse in middle of each bit
--
process(clk,rst)
variable uart_clk_cnt : integer := 0;
variable uart_bit_cnt : integer := 0;
begin
if rst = '1' then
uart_clk_re <= '0';
clkstate <= BAUDRATE_CLK_OFF;
uart_clk_cnt := 0;
uart_bit_cnt := 0;
parallell_data_out_valid <= '0';
elsif rising_edge(clk) then
parallell_data_out_valid <= '0';
case clkstate is
when BAUDRATE_CLK_OFF =>
if start_baudrate_clk = '1' then
clkstate <= BAUDRATE_CLK_ON;
end if;
uart_clk_cnt := 0;
uart_bit_cnt := 0;
uart_clk_re <= '0';
when BAUDRATE_CLK_ON =>
--50M/(19200)=2604.16
--TODO: fix average frequency
if(uart_clk_cnt = 2604) then
if uart_bit_cnt /= 8 then
uart_clk_re <= '1';
end if;
uart_bit_cnt := uart_bit_cnt + 1;
uart_clk_cnt := 0;
else
uart_clk_re <= '0';
uart_clk_cnt := uart_clk_cnt + 1;
end if;
if uart_bit_cnt = 9 then
clkstate <= BAUDRATE_CLK_OFF;
parallell_data_out_valid <= '1';
end if;
end case;
end if;
end process;
--
-- sample uart data
--
process(clk,rst)
begin
if rst = '1' then
parallell_data_out <= (others => '0');
elsif rising_edge(clk) then
if uart_clk_re = '1' then
parallell_data_out <= uart_data_in & parallell_data_out(7 downto 1);
end if;
end if;
end process;
end architecture syn;
-- *** EOF ***
| mit | 3a2dea9f41b0204d0a57148639c55d90 | 0.536842 | 3.776559 | false | false | false | false |
chastell/art-decomp | kiss/keyb_rnd.vhd | 1 | 16,319 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_rnd;
architecture behaviour of keyb_rnd is
constant st0: std_logic_vector(4 downto 0) := "11101";
constant st1: std_logic_vector(4 downto 0) := "00010";
constant st2: std_logic_vector(4 downto 0) := "11011";
constant st3: std_logic_vector(4 downto 0) := "11110";
constant st4: std_logic_vector(4 downto 0) := "11111";
constant st5: std_logic_vector(4 downto 0) := "10001";
constant st6: std_logic_vector(4 downto 0) := "10110";
constant st7: std_logic_vector(4 downto 0) := "01011";
constant st8: std_logic_vector(4 downto 0) := "01111";
constant st9: std_logic_vector(4 downto 0) := "00001";
constant st10: std_logic_vector(4 downto 0) := "10000";
constant st11: std_logic_vector(4 downto 0) := "11010";
constant st12: std_logic_vector(4 downto 0) := "11000";
constant st13: std_logic_vector(4 downto 0) := "01000";
constant st14: std_logic_vector(4 downto 0) := "00100";
constant st15: std_logic_vector(4 downto 0) := "01001";
constant st16: std_logic_vector(4 downto 0) := "00110";
constant st17: std_logic_vector(4 downto 0) := "11100";
constant st18: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 527b752f9701bb22fb7b56e9ddc3021f | 0.541026 | 3.343372 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-04A-B.vhd | 1 | 13,477 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-04A-B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Recycle Controls (04A) & Address Matching (04B)
-- Recycle Controls handles restarts and resets
-- Address Matching handles ROAR and SAR address matching (Address Compare switch)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY RecycleCtrlsMatch IS
port
(
-- Inputs
N_CTRL_N : IN STD_LOGIC; -- 06B
XOR_OR_OR : IN STD_LOGIC; -- 02A
S_REG_7_BIT : IN STD_LOGIC; -- 07B
CLOCK_ON,CLOCK_OFF : IN STD_LOGIC; -- 08A
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
HARD_STOP_LCH : IN STD_LOGIC; -- 03C
MPX_METERING_IN : IN STD_LOGIC; -- 08D
METER_IN_SX1 : IN STD_LOGIC; -- 11D
METER_IN_SX2 : IN STD_LOGIC; -- 13D
SEL_SHARE_HOLD : IN STD_LOGIC; -- 12D
KEY_SW : IN STD_LOGIC; -- 14A
MACH_RST_SW : IN STD_LOGIC; -- 03D
LOAD_KEY_SW : IN STD_LOGIC; -- 03C
SYSTEM_RESET_SW : IN STD_LOGIC; -- 03D
CL_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
INH_ROSAR_SET : IN STD_LOGIC; -- 03C
ALLOW_WRITE : IN STD_LOGIC; -- 03D
ALLOW_WRITE_DLYD : IN STD_LOGIC; -- 03D
SET_IC_LCH : IN STD_LOGIC; -- 03C
MACH_RST_3 : IN STD_LOGIC; -- 03D
FORCE_IJ_PULSE : IN STD_LOGIC; -- 03A
FORCE_IJ_REQ_LCH : IN STD_LOGIC; -- 03A
START_SW_RST : IN STD_LOGIC; -- 03C
MACH_RST_6 : IN STD_LOGIC; -- 03D
ANY_MACH_CHK : IN STD_LOGIC; -- 07A
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
SUPPR_MACH_CHK_TRAP : IN STD_LOGIC; -- 03A
ALLOW_MAN_OPERATION : IN STD_LOGIC; -- 03D
LOAD_IND : IN STD_LOGIC; -- 03C
N1050_INTRV_REQ : IN STD_LOGIC; -- 10C
TT6_POS_ATTN : IN STD_LOGIC; -- 10B
FT2_MPX_OPNL : IN STD_LOGIC; -- 08C
H_REG_5_PWR : IN STD_LOGIC; -- 04C
ROS_CTRL_PROC_SW : IN STD_LOGIC; -- 03C
RATE_SW_PROC_SW : IN STD_LOGIC; -- 03C
ODD : IN STD_LOGIC; -- 06B
INTRODUCE_ALU_CHK : IN STD_LOGIC; -- 06B
GT_SW_TO_WX_LCH : IN STD_LOGIC; -- 03A
HZ_DEST_RST : IN STD_LOGIC; -- 03A
MAIN_STORAGE : IN STD_LOGIC; -- 03D
WX_REG_BUS : IN STD_LOGIC_VECTOR(0 to 12); -- 01B
ABCD_SW_BUS : IN STD_LOGIC_VECTOR(0 to 15); --04C
MN_REGS_BUS : IN STD_LOGIC_VECTOR(0 to 15); -- 07A
AUX_WRITE_CALL : IN STD_LOGIC; -- 03D
DIAG_LATCH_RST : IN STD_LOGIC; -- NEW
-- Switches
SW_LAMP_TEST : IN STD_LOGIC;
SW_CHK_RST : IN STD_LOGIC;
SW_ROAR_RST : IN STD_LOGIC;
SW_CHK_RESTART,SW_DIAGNOSTIC,SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE : IN STD_LOGIC;
SW_ROAR_RESTT_STOR_BYPASS,SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,
SW_ROAR_STOP,SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
-- Outputs
LAMP_TEST : OUT STD_LOGIC; -- Various
CLOCK_OUT : OUT STD_LOGIC; -- 11D,13D,08D
TO_KEY_SW : OUT STD_LOGIC; -- 14A
METERING_OUT : OUT STD_LOGIC; -- 08D,13D,11D
MACH_RST_SET_LCH : OUT STD_LOGIC; -- 06B,01A
MACH_RST_SET_LCH_DLYD : OUT STD_LOGIC; -- 01B,06C,07B
FORCE_DEAD_CY_LCH : OUT STD_LOGIC; -- 03A
END_OF_E_CY_LCH : OUT STD_LOGIC; -- 03C
FORCE_IJ_REQ : OUT STD_LOGIC; -- 03A,03C
MACH_START_RST : OUT STD_LOGIC; -- 03C
DIAGNOSTIC_SW : OUT STD_LOGIC; -- 03A,03C,06B,08D
CHK_OR_DIAG_STOP_SW : OUT STD_LOGIC; -- 01A,01B,03C,13A,11A,11D,13D
-- CHK_SW_PROCESS_SW : OUT STD_LOGIC; -- 08D,07A,01B,11A
-- CHK_SW_DISABLE_SW : OUT STD_LOGIC; -- 07C
RECYCLE_RST : OUT STD_LOGIC; -- 03A,06B,03D,06B,04C,08D
MACH_CHK_RST : OUT STD_LOGIC; -- 03C,07A
CHK_RST_SW : OUT STD_LOGIC; -- 11A,13A
MACH_RST_LCH : OUT STD_LOGIC; -- 03A
GT_SWS_TO_WX_PWR : OUT STD_LOGIC; -- 01B,03A,06B
MATCH_LCH : OUT STD_LOGIC; -- 03C
MATCH : OUT STD_LOGIC; -- 03C
-- Indicators
IND_SYST,IND_MAN,IND_WAIT,IND_TEST,IND_LOAD,IND_EX,IND_CY_MATCH : OUT STD_LOGIC;
IND_ALLOW_WR,IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
Clk : IN STD_LOGIC
);
END RecycleCtrlsMatch;
ARCHITECTURE FMD OF RecycleCtrlsMatch IS
signal NWAIT : STD_LOGIC;
signal CHNL_TO_METER : STD_LOGIC;
signal SYSTEM_OPERATING : STD_LOGIC;
signal FORCE_DEAD_CY : STD_LOGIC;
signal TEST : STD_LOGIC;
signal END_OF_E_CYCLE : STD_LOGIC;
signal CHK_RESTT_LCH : STD_LOGIC;
signal CHK_RESTART_SW,CHK_STOP_SW : STD_LOGIC;
signal ROAR_RESTT_SW_ORED : STD_LOGIC;
signal RST_MATCH : STD_LOGIC;
signal MATCH_SET_MACH_RST_LCH : STD_LOGIC;
signal GT_MATCH_MN_CKT_1,GT_MATCH_WX_CKT_2 : STD_LOGIC;
signal OEA1,OEA2,OEA3,ANDWX,ANDMN : STD_LOGIC;
signal sTO_KEY_SW : STD_LOGIC;
signal sLAMP_TEST : STD_LOGIC;
signal sCLOCK_OUT : STD_LOGIC;
signal sFORCE_DEAD_CY_LCH : STD_LOGIC;
signal sEND_OF_E_CY_LCH : STD_LOGIC;
signal sFORCE_IJ_REQ : STD_LOGIC;
signal sMACH_RST_SET_LCH : STD_LOGIC;
signal sDIAGNOSTIC_SW : STD_LOGIC;
signal sRECYCLE_RST : STD_LOGIC;
signal sMACH_CHK_RST : STD_LOGIC;
signal sMATCH_LCH : STD_LOGIC;
signal sCHK_SW_PROCESS_SW : STD_LOGIC;
signal sMATCH : STD_LOGIC;
signal sMACH_RST_LCH : STD_LOGIC;
signal sGT_SWS_TO_WX_REG : STD_LOGIC;
signal NW_LCH_Set,NW_LCH_Reset,MRS_LCH_Reset,EEC_LCH_Set,FIJ_LCH_Set,FIJ_LCH_Reset,
CR_LCH_Set,CR_LCH_Reset,MR_LCH_Set,MR_LCH_Reset,GSWX_LCH_Set,GSWX_LCH_Reset,
M_LCH_Set,M_LCH_Reset : STD_LOGIC;
signal DIAG_LATCH : STD_LOGIC;
BEGIN
-- Fig 5-04A
NW_LCH_Set <= N_CTRL_N and XOR_OR_OR and T2;
NW_LCH_Reset <= not S_REG_7_BIT or sRECYCLE_RST;
NW_LCH: entity work.FLL port map(NW_LCH_Set,NW_LCH_Reset,NWAIT); --AC1E6,AC1F6
sCLOCK_OUT <= (not NWAIT and CLOCK_ON) or MAN_STOR_OR_DSPLY; -- AC1G6
CLOCK_OUT <= sCLOCK_OUT;
CHNL_TO_METER <= not HARD_STOP_LCH and (MPX_METERING_IN or METER_IN_SX1 or METER_IN_SX2); -- AC1K4,AC1F2 ??
SYSTEM_OPERATING <= sCLOCK_OUT or CHNL_TO_METER; -- AB2D2
sTO_KEY_SW <= sCLOCK_OUT or CHNL_TO_METER or SEL_SHARE_HOLD; -- AB2D2
TO_KEY_SW <= sTO_KEY_SW;
METERING_OUT <= sTO_KEY_SW and KEY_SW; -- AB2F4
sLAMP_TEST <= SW_LAMP_TEST;
LAMP_TEST <= sLAMP_TEST;
IND_SYST <= SYSTEM_OPERATING or sLAMP_TEST;
IND_MAN <= ALLOW_MAN_OPERATION or sLAMP_TEST;
IND_WAIT <= NWAIT or sLAMP_TEST;
IND_TEST <= TEST or sLAMP_TEST;
IND_LOAD <= LOAD_IND or sLAMP_TEST;
IND_EX <= END_OF_E_CYCLE or sLAMP_TEST;
IND_CY_MATCH <= sMATCH_LCH or sLAMP_TEST;
IND_ALLOW_WR <= ALLOW_WRITE or sLAMP_TEST;
IND_1050_INTRV <= N1050_INTRV_REQ or sLAMP_TEST;
IND_1050_REQ <= TT6_POS_ATTN or sLAMP_TEST;
IND_MPX <= FT2_MPX_OPNL or sLAMP_TEST;
IND_SEL_CHNL <= H_REG_5_PWR or sLAMP_TEST;
TEST <= (not ROS_CTRL_PROC_SW) or (not RATE_SW_PROC_SW) or (not SW_ADDR_COMP_PROC) or (not ODD) or (not sCHK_SW_PROCESS_SW) or INTRODUCE_ALU_CHK; -- AC1C4,AC1K5,AC1D4,AC1K5 ??
MRS_LCH_Reset <= not LOAD_KEY_SW and not SYSTEM_RESET_SW;
MRS_LCH: entity work.FLL port map(MACH_RST_SW,MRS_LCH_Reset,sMACH_RST_SET_LCH); -- AA2H5,AA2F5
MACH_RST_SET_LCH <= sMACH_RST_SET_LCH;
MACH_RST_SET_LCH_DLYD <= sMACH_RST_SET_LCH; -- ?? Should be delayed by 1 gate
-- MACH_RST_DELAY: AR port map(D=>sMACH_RST_SET_LCH,CLK=>Clk,Q=>MACH_RST_SET_LCH_DLYD); -- Delay
FORCE_DEAD_CY <= SW_SAR_RESTART and T4 and MATCH_SET_MACH_RST_LCH; -- AB3B6
FDC_LCH: entity work.FLL port map(FORCE_DEAD_CY,T3,sFORCE_DEAD_CY_LCH); -- AB3L3
FORCE_DEAD_CY_LCH <= sFORCE_DEAD_CY_LCH;
EEC_LCH_Set <= T2 and (CL_SALS(0) and CL_SALS(1) and CL_SALS(2) and CL_SALS(3)); -- ?? additional NOT
EEC_LCH: entity work.FLL port map(EEC_LCH_Set,T1,sEND_OF_E_CY_LCH); -- AC1G4 ?? Reset input is unlabeled
END_OF_E_CY_LCH <= sEND_OF_E_CY_LCH;
END_OF_E_CYCLE <= sEND_OF_E_CY_LCH or INH_ROSAR_SET; -- AC1J7
MATCH_SET_MACH_RST_LCH <= ((SW_SAR_RESTART and sMATCH_LCH and not ALLOW_WRITE_DLYD) or
(not ALLOW_WRITE_DLYD and CHK_RESTT_LCH and not ROAR_RESTT_SW_ORED and not SW_ROAR_RESTT_STOR_BYPASS)); -- AC1D2,AC1E6,AC1D4 ?? AC1D4 removed ??
FIJ_LCH_Set <= (MATCH_SET_MACH_RST_LCH and CLOCK_ON) or SET_IC_LCH; -- ?? *not* MATCH_SET_MACH_RST_LCH & *not* CLOCK_ON ??
FIJ_LCH_Reset <= MACH_RST_3 or (T1 and FORCE_IJ_PULSE);
FIJ_LCH: entity work.FLL port map(FIJ_LCH_Set,FIJ_LCH_Reset,sFORCE_IJ_REQ); -- AC1E6,AC1H6
FORCE_IJ_REQ <= sFORCE_IJ_REQ;
MACH_START_RST <= (sFORCE_IJ_REQ and not FORCE_IJ_REQ_LCH) or START_SW_RST or MACH_RST_6; -- AB3J5,AB3H3
CR_LCH_Set <= ANY_MACH_CHK and CHK_RESTART_SW;
CR_LCH_Reset <= ANY_PRIORITY_LCH or sMACH_CHK_RST;
CR_LCH: entity work.FLL port map(CR_LCH_Set,CR_LCH_Reset,CHK_RESTT_LCH); -- AB3H4,AC1H6
CHK_RESTART_SW <= SW_CHK_RESTART;
-- Diagnostic latch is not in the FMD but must have appeared later
-- It is set on Sys Reset and reset by the YL / 0->DIAG function (Alt-CK=0000)
DIAG_FL: entity work.FLL port map(S=>MACH_RST_6,R=>DIAG_LATCH_RST,Q=>DIAG_LATCH);
sDIAGNOSTIC_SW <= SW_DIAGNOSTIC or DIAG_LATCH;
DIAGNOSTIC_SW <= sDIAGNOSTIC_SW;
CHK_STOP_SW <= SW_CHK_STOP;
sCHK_SW_PROCESS_SW <= SW_CHK_SW_PROCESS;
-- CHK_SW_PROCESS_SW <= sCHK_SW_PROCESS_SW;
-- CHK_SW_DISABLE_SW <= SW_CHK_SW_DISABLE;
CHK_OR_DIAG_STOP_SW <= (sDIAGNOSTIC_SW and SUPPR_MACH_CHK_TRAP) or CHK_STOP_SW; -- AC1H3,AC1F5 ?? *not* SUPPR_MACH_CHK_TRAP ??
sRECYCLE_RST <= sMACH_RST_SET_LCH or
(SW_ROAR_RESTT_STOR_BYPASS and GT_SW_TO_WX_LCH) or
(ANY_PRIORITY_LCH and sFORCE_DEAD_CY_LCH and SW_SAR_RESTART) or
(SW_ROAR_RESTT_WITHOUT_RST and GT_SW_TO_WX_LCH and CHK_RESTART_SW) or
(GT_SW_TO_WX_LCH and SW_ROAR_RESTT); -- AB3K5,AB3L5,AB3L4
RECYCLE_RST <= sRECYCLE_RST;
sMACH_CHK_RST <= sRECYCLE_RST or SW_CHK_RST; -- AB3L3,AB3H5
MACH_CHK_RST <= sMACH_CHK_RST;
CHK_RST_SW <= SW_CHK_RST; -- AB3F5
MR_LCH_Set <= FORCE_DEAD_CY or MACH_RST_6;
MR_LCH_Reset <= HZ_DEST_RST or SW_ROAR_RST; -- ?? *not* SW_ROAR_RST
MR_LCH: entity work.FLL port map(MR_LCH_Set,MR_LCH_Reset,sMACH_RST_LCH); -- AB3F2,AB3J4
MACH_RST_LCH <= sMACH_RST_LCH;
GSWX_LCH_Set <= (SW_ROAR_RST and ALLOW_MAN_OPERATION) or
(SW_ROAR_RESTT_STOR_BYPASS and sMATCH) or
(T3 and ROAR_RESTT_SW_ORED and CHK_RESTT_LCH and not ALLOW_WRITE_DLYD) or
(not ALLOW_WRITE_DLYD and ROAR_RESTT_SW_ORED and sMATCH) or
(SW_ROAR_RESTT_STOR_BYPASS and CHK_RESTT_LCH);
GSWX_LCH_Reset <= MACH_RST_SW or (T3 and GT_SW_TO_WX_LCH);
GSWX_LCH: entity work.FLL port map(GSWX_LCH_Set,GSWX_LCH_Reset,sGT_SWS_TO_WX_REG); -- AC1H5,AC1H7,AC1H4,AC1K5,AC1J7
GT_SWS_TO_WX_PWR <= not sMACH_RST_LCH and sGT_SWS_TO_WX_REG; -- AC1E7
-- Fig 5-04B
ROAR_RESTT_SW_ORED <= SW_ROAR_RESTT or SW_ROAR_RESTT_WITHOUT_RST; -- AC1M5
GT_MATCH_WX_CKT_2 <= SW_ROAR_RESTT or SW_ROAR_RESTT_WITHOUT_RST or SW_EARLY_ROAR_STOP or
SW_ROAR_RESTT_STOR_BYPASS or SW_ROAR_STOP or SW_ROAR_SYNC; -- AC1M6
GT_MATCH_MN_CKT_1 <= SW_ADDR_COMP_PROC or
(MAIN_STORAGE and SW_SAR_DLYD_STOP) or
(MAIN_STORAGE and SW_SAR_STOP) or
(MAIN_STORAGE and SW_SAR_RESTART); -- AC1M6
RST_MATCH <= (SW_ADDR_COMP_PROC and T1) or
(SW_ROAR_SYNC and T1) or
(not ALLOW_WRITE_DLYD and START_SW_RST) or
(FORCE_IJ_REQ_LCH and T1) or
(sGT_SWS_TO_WX_REG and T1); -- AC1H3,AC1K4
OEA1 <= '1' when (not ABCD_SW_BUS(4 to 7) xor ((MN_REGS_BUS(4 to 7) and (4 to 7 => GT_MATCH_MN_CKT_1)) or (WX_REG_BUS(1 to 4) and (1 to 4 => GT_MATCH_WX_CKT_2))))="1111" else '0'; -- AA2C4
OEA2 <= '1' when (not ABCD_SW_BUS(8 to 11) xor ((MN_REGS_BUS(8 to 11) and (8 to 11 => GT_MATCH_MN_CKT_1)) or (WX_REG_BUS(5 to 8) and (5 to 8 => GT_MATCH_WX_CKT_2))))="1111" else '0'; -- AA2C5
OEA3 <= '1' when (not ABCD_SW_BUS(12 to 15) xor ((MN_REGS_BUS(12 to 15) and (12 to 15 => GT_MATCH_MN_CKT_1)) or (WX_REG_BUS(9 to 12) and (9 to 12 => GT_MATCH_WX_CKT_2))))="1111" else '0'; -- AA2D5
ANDMN <= AUX_WRITE_CALL and
(ABCD_SW_BUS(0) xnor MN_REGS_BUS(0)) and
(ABCD_SW_BUS(1) xnor MN_REGS_BUS(1)) and
(ABCD_SW_BUS(2) xnor MN_REGS_BUS(2)) and
(ABCD_SW_BUS(3) xnor MN_REGS_BUS(3)) and
GT_MATCH_MN_CKT_1 and OEA2 and OEA1 and OEA3; -- AC1K7,AC1L7
ANDWX <= (WX_REG_BUS(0) xor not ABCD_SW_BUS(3)) and OEA1 and OEA2 and OEA3 and GT_MATCH_WX_CKT_2 and T3; -- AC1L7
M_LCH_Set <= ANDMN or ANDWX;
M_LCH_Reset <= RST_MATCH or MACH_RST_SW;
M_LCH: entity work.FLL port map(M_LCH_Set,M_LCH_Reset,sMATCH_LCH); -- AC1L7,AC1L4
MATCH_LCH <= sMATCH_LCH;
sMATCH <= sMATCH_LCH and not CLOCK_OFF; -- AC1H5
MATCH <= sMATCH;
END FMD;
| gpl-3.0 | 6eeb8dbc94fd54929fc4f8027eb49839 | 0.663575 | 2.509216 | false | true | false | false |
ibm2030/IBM2030 | Testbench_panel_LEDs.vhd | 1 | 3,582 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:16:46 06/18/2015
-- Design Name:
-- Module Name: C:/Users/lwilkinson/Documents/Xilinx/IBM2030/Testbench_panel_LEDs.vhd
-- Project Name: IBM2030
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: panel_LEDs
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Testbench_panel_LEDs IS
END Testbench_panel_LEDs;
ARCHITECTURE behavior OF Testbench_panel_LEDs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT panel_LEDs
PORT(
LEDs : IN std_logic_vector(0 to 255);
clk : IN std_logic;
MAX7219_CLK : OUT std_logic;
MAX7219_DIN0 : OUT std_logic;
MAX7219_DIN1 : OUT std_logic;
MAX7219_DIN2 : OUT std_logic;
MAX7219_DIN3 : OUT std_logic;
MAX7219_LOAD : OUT std_logic;
MAX6951_CLK : OUT std_logic;
MAX6951_DIN : OUT std_logic;
MAX6951_CS0 : OUT std_logic;
MAX6951_CS1 : OUT std_logic;
MAX6951_CS2 : OUT std_logic;
MAX6951_CS3 : OUT std_logic
);
END COMPONENT;
--Inputs
signal LEDs : std_logic_vector(0 to 255) := (1 => '1',3 => '1',5 => '1',7 => '1',9 => '1',11 => '1',13 => '1',15 => '1',17 => '1',others => '0');
signal clk : std_logic := '0';
--Outputs
signal MAX7219_CLK : std_logic;
signal MAX7219_DIN0 : std_logic;
signal MAX7219_DIN1 : std_logic;
signal MAX7219_DIN2 : std_logic;
signal MAX7219_DIN3 : std_logic;
signal MAX7219_LOAD : std_logic;
signal MAX6951_CLK : std_logic;
signal MAX6951_DIN : std_logic;
signal MAX6951_CS0 : std_logic;
signal MAX6951_CS1 : std_logic;
signal MAX6951_CS2 : std_logic;
signal MAX6951_CS3 : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: panel_LEDs PORT MAP (
LEDs => LEDs,
clk => clk,
MAX7219_CLK => MAX7219_CLK,
MAX7219_DIN0 => MAX7219_DIN0,
MAX7219_DIN1 => MAX7219_DIN1,
MAX7219_DIN2 => MAX7219_DIN2,
MAX7219_DIN3 => MAX7219_DIN3,
MAX7219_LOAD => MAX7219_LOAD,
MAX6951_CLK => MAX6951_CLK,
MAX6951_DIN => MAX6951_DIN,
MAX6951_CS0 => MAX6951_CS0,
MAX6951_CS1 => MAX6951_CS1,
MAX6951_CS2 => MAX6951_CS2,
MAX6951_CS3 => MAX6951_CS3
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for 1ms;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | a0032c60e98a5b3a3a6011137c53228b | 0.587661 | 3.529064 | false | true | false | false |
chastell/art-decomp | kiss/ex4_rnd.vhd | 1 | 3,706 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex4_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(8 downto 0)
);
end ex4_rnd;
architecture behaviour of ex4_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101";
constant s3: std_logic_vector(3 downto 0) := "0010";
constant s2: std_logic_vector(3 downto 0) := "1011";
constant s5: std_logic_vector(3 downto 0) := "1110";
constant s7: std_logic_vector(3 downto 0) := "1111";
constant s11: std_logic_vector(3 downto 0) := "0001";
constant s12: std_logic_vector(3 downto 0) := "0110";
constant s8: std_logic_vector(3 downto 0) := "0000";
constant s4: std_logic_vector(3 downto 0) := "1010";
constant s13: std_logic_vector(3 downto 0) := "1000";
constant s14: std_logic_vector(3 downto 0) := "0100";
constant s6: std_logic_vector(3 downto 0) := "1001";
constant s9: std_logic_vector(3 downto 0) := "1100";
constant s10: std_logic_vector(3 downto 0) := "0011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "---------";
case current_state is
when s1 =>
if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
end if;
when s3 =>
if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
end if;
when s2 =>
if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
end if;
when s5 =>
if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
end if;
when s7 =>
if std_match(input, "10----") then next_state <= s7; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
end if;
when s11 =>
if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
end if;
when s12 =>
if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
end if;
when s8 =>
if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
end if;
when s4 =>
if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
end if;
when s13 =>
if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
end if;
when s14 =>
if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
end if;
when s6 =>
if std_match(input, "10----") then next_state <= s6; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
end if;
when s9 =>
if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
end if;
when s10 =>
if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
end if;
when others => next_state <= "----"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 14bf84610613d99c360c2a7f07bdb8d8 | 0.568268 | 3.338739 | false | false | false | false |
chastell/art-decomp | kiss/s820_nov.vhd | 1 | 29,266 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s820_nov is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s820_nov;
architecture behaviour of s820_nov is
constant s00000: std_logic_vector(4 downto 0) := "00000";
constant s01110: std_logic_vector(4 downto 0) := "01011";
constant s01111: std_logic_vector(4 downto 0) := "01000";
constant s00010: std_logic_vector(4 downto 0) := "00110";
constant s00100: std_logic_vector(4 downto 0) := "10101";
constant s00001: std_logic_vector(4 downto 0) := "11000";
constant s00101: std_logic_vector(4 downto 0) := "10100";
constant s00110: std_logic_vector(4 downto 0) := "10011";
constant s11111: std_logic_vector(4 downto 0) := "00111";
constant s10111: std_logic_vector(4 downto 0) := "10010";
constant s11000: std_logic_vector(4 downto 0) := "10001";
constant s11001: std_logic_vector(4 downto 0) := "10110";
constant s11010: std_logic_vector(4 downto 0) := "10000";
constant s11011: std_logic_vector(4 downto 0) := "11011";
constant s11100: std_logic_vector(4 downto 0) := "11010";
constant s01100: std_logic_vector(4 downto 0) := "01001";
constant s01101: std_logic_vector(4 downto 0) := "00100";
constant s10000: std_logic_vector(4 downto 0) := "01111";
constant s01011: std_logic_vector(4 downto 0) := "11001";
constant s00111: std_logic_vector(4 downto 0) := "11111";
constant s01000: std_logic_vector(4 downto 0) := "11110";
constant s01001: std_logic_vector(4 downto 0) := "10111";
constant s01010: std_logic_vector(4 downto 0) := "11101";
constant s00011: std_logic_vector(4 downto 0) := "11100";
constant s10001: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000000000000110000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------00") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-1--------------00") then next_state <= s10000; output <= "0000000000000110000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000100001";
elsif std_match(input, "-1--------------10") then next_state <= s10000; output <= "0000000000000110000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000010000000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000010000000000000";
end if;
when s01111 =>
if std_match(input, "----------------11") then next_state <= s00000; output <= "0000000100000100000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000100000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000100000100000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000000000110000000";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000000000111000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000000000010000000";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000000000110000000";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000000000111000000";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000000000010000000";
end if;
when s00100 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------10") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-11-1-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1011-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0-1--0-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1--------010") then next_state <= s00100; output <= "0000000000000001000";
end if;
when s00001 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----1----111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----1-1--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----1-----0-1--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----011--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----0-0--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------1----10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------1---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0------1----00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1------1----00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1------0-----0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------0---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0------0---000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0------01--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----001--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----000--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----000--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----0-----100--100") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11111 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000000000001000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11000 =>
if std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "1000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000000000001000";
end if;
when s11001 =>
if std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "0100000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000000000001000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11010 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11011 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-0---------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----001") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1111-----011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----1-1") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-0--------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-0--------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-110------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1110-----110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000000000001010";
elsif std_match(input, "----0-11-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11100 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01100 =>
if std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0010100000000000000";
elsif std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0010100000000000000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0001100000000000000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0001100000000000000";
end if;
when s01101 =>
if std_match(input, "-1---------------0") then next_state <= s10000; output <= "0000001010000010000";
elsif std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000001010000010000";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0000001010000000000";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0000001010000000000";
elsif std_match(input, "-0-0-------------1") then next_state <= s00000; output <= "0000001010000000000";
elsif std_match(input, "-0-1--------------") then next_state <= s00000; output <= "0000001010000000000";
end if;
when s10000 =>
if std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
elsif std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s01011 =>
if std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
end if;
when s00111 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01000 =>
if std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "1000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s01001 =>
if std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "0100000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01010 =>
if std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
end if;
when s00011 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 7dc9a23a1a7dc282ac8c0c06727bfcde | 0.582075 | 4.157102 | false | false | false | false |
chastell/art-decomp | kiss/s420_hot.vhd | 1 | 17,828 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_hot is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_hot;
architecture behaviour of s420_hot is
constant s1111111111111111: std_logic_vector(17 downto 0) := "100000000000000000";
constant s0000000000000000: std_logic_vector(17 downto 0) := "010000000000000000";
constant s0001000000000000: std_logic_vector(17 downto 0) := "001000000000000000";
constant s0010000000000000: std_logic_vector(17 downto 0) := "000100000000000000";
constant s0011000000000000: std_logic_vector(17 downto 0) := "000010000000000000";
constant s0100000000000000: std_logic_vector(17 downto 0) := "000001000000000000";
constant s0101000000000000: std_logic_vector(17 downto 0) := "000000100000000000";
constant s0110000000000000: std_logic_vector(17 downto 0) := "000000010000000000";
constant s0111000000000000: std_logic_vector(17 downto 0) := "000000001000000000";
constant s1000000000000000: std_logic_vector(17 downto 0) := "000000000100000000";
constant s1001000000000000: std_logic_vector(17 downto 0) := "000000000010000000";
constant s1010000000000000: std_logic_vector(17 downto 0) := "000000000001000000";
constant s1011000000000000: std_logic_vector(17 downto 0) := "000000000000100000";
constant s1100000000000000: std_logic_vector(17 downto 0) := "000000000000010000";
constant s1101000000000000: std_logic_vector(17 downto 0) := "000000000000001000";
constant s1110000000000000: std_logic_vector(17 downto 0) := "000000000000000100";
constant s1111000000000000: std_logic_vector(17 downto 0) := "000000000000000010";
constant s0000000100000000: std_logic_vector(17 downto 0) := "000000000000000001";
signal current_state, next_state: std_logic_vector(17 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "------------------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | fabc65b42a1e5ce35a612c9742cff30c | 0.569554 | 4.149907 | false | false | false | false |
chastell/art-decomp | kiss/pma_jed.vhd | 1 | 9,226 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity pma_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(7 downto 0)
);
end pma_jed;
architecture behaviour of pma_jed is
constant s0: std_logic_vector(4 downto 0) := "01010";
constant s1: std_logic_vector(4 downto 0) := "01001";
constant s21: std_logic_vector(4 downto 0) := "01100";
constant s2: std_logic_vector(4 downto 0) := "01111";
constant s3: std_logic_vector(4 downto 0) := "01011";
constant s4: std_logic_vector(4 downto 0) := "10110";
constant s6: std_logic_vector(4 downto 0) := "00110";
constant s7: std_logic_vector(4 downto 0) := "10010";
constant s5: std_logic_vector(4 downto 0) := "00011";
constant s10: std_logic_vector(4 downto 0) := "01110";
constant s8: std_logic_vector(4 downto 0) := "00101";
constant s9: std_logic_vector(4 downto 0) := "00111";
constant s11: std_logic_vector(4 downto 0) := "11010";
constant s12: std_logic_vector(4 downto 0) := "11000";
constant s13: std_logic_vector(4 downto 0) := "11110";
constant s14: std_logic_vector(4 downto 0) := "10011";
constant s22: std_logic_vector(4 downto 0) := "01000";
constant s30: std_logic_vector(4 downto 0) := "00010";
constant s23: std_logic_vector(4 downto 0) := "10000";
constant s25: std_logic_vector(4 downto 0) := "00000";
constant s24: std_logic_vector(4 downto 0) := "00100";
constant s26: std_logic_vector(4 downto 0) := "00001";
constant s27: std_logic_vector(4 downto 0) := "10001";
constant s28: std_logic_vector(4 downto 0) := "10100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--------";
case current_state is
when s0 =>
if std_match(input, "----1---") then next_state <= s1; output <= "00000000";
elsif std_match(input, "1---01--") then next_state <= s21; output <= "00000000";
end if;
when s1 =>
if std_match(input, "---0---1") then next_state <= s2; output <= "00001000";
elsif std_match(input, "---0--1-") then next_state <= s2; output <= "00001000";
elsif std_match(input, "1--1----") then next_state <= s3; output <= "00001000";
end if;
when s2 =>
if std_match(input, "1--1----") then next_state <= s3; output <= "00000100";
end if;
when s3 =>
if std_match(input, "1--1----") then next_state <= s4; output <= "10000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "10000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "10000000";
end if;
when s4 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "01000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "01000000";
end if;
when s5 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11000000";
elsif std_match(input, "1--0---1") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--1-") then next_state <= s6; output <= "11000000";
elsif std_match(input, "1--0--00") then next_state <= s7; output <= "11000000";
end if;
when s6 =>
if std_match(input, "1-----01") then next_state <= s0; output <= "00100000";
elsif std_match(input, "1-----1-") then next_state <= s10; output <= "00100000";
end if;
when s7 =>
if std_match(input, "-1--1---") then next_state <= s8; output <= "11101010";
elsif std_match(input, "-1--0--1") then next_state <= s6; output <= "11101010";
elsif std_match(input, "-1--0-1-") then next_state <= s6; output <= "11101010";
end if;
when s8 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "01110000";
elsif std_match(input, "---0---1") then next_state <= s9; output <= "01110000";
elsif std_match(input, "---0--1-") then next_state <= s9; output <= "01110000";
end if;
when s9 =>
if std_match(input, "1--1----") then next_state <= s5; output <= "11100100";
end if;
when s10 =>
if std_match(input, "1--10--0") then next_state <= s11; output <= "10101100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10101100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10101100";
end if;
when s11 =>
if std_match(input, "-11-0--0") then next_state <= s12; output <= "11111101";
elsif std_match(input, "11-----1") then next_state <= s0; output <= "11111101";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "11111101";
end if;
when s12 =>
if std_match(input, "---00--0") then next_state <= s13; output <= "10111100";
elsif std_match(input, "1------1") then next_state <= s0; output <= "10111100";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "10111100";
end if;
when s13 =>
if std_match(input, "1-------") then next_state <= s14; output <= "11111100";
end if;
when s14 =>
if std_match(input, "1---0--0") then next_state <= s10; output <= "01100000";
elsif std_match(input, "1------1") then next_state <= s0; output <= "01100000";
elsif std_match(input, "1---1---") then next_state <= s0; output <= "01100000";
end if;
when s21 =>
if std_match(input, "1---0-00") then next_state <= s22; output <= "00011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "00011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "00011100";
end if;
when s22 =>
if std_match(input, "1---0100") then next_state <= s23; output <= "10011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "10011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "10011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "10011100";
end if;
when s23 =>
if std_match(input, "1---0100") then next_state <= s24; output <= "01011100";
elsif std_match(input, "1---0000") then next_state <= s25; output <= "01011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01011100";
end if;
when s24 =>
if std_match(input, "1---0000") then next_state <= s25; output <= "11011100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11011100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11011100";
end if;
when s25 =>
if std_match(input, "---10-00") then next_state <= s26; output <= "01111100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111100";
end if;
when s26 =>
if std_match(input, "011---00") then next_state <= s27; output <= "01111101";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "01111101";
elsif std_match(input, "1------1") then next_state <= s30; output <= "01111101";
end if;
when s27 =>
if std_match(input, "0--00-00") then next_state <= s28; output <= "11101100";
elsif std_match(input, "1--00-00") then next_state <= s0; output <= "11101100";
elsif std_match(input, "1---1---") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1-----1-") then next_state <= s30; output <= "11101100";
elsif std_match(input, "1------1") then next_state <= s30; output <= "11101100";
end if;
when s28 =>
if std_match(input, "1-------") then next_state <= s0; output <= "10111000";
end if;
when s30 =>
if std_match(input, "1-------") then next_state <= s0; output <= "00110000";
end if;
when others => next_state <= "-----"; output <= "--------";
end case;
end process;
end behaviour;
| agpl-3.0 | 7d7333a2c86494dce73419ecc7905b77 | 0.563516 | 3.307996 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/DDR_enable.vhd | 2 | 1,220 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_enable is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end DDR_enable;
architecture small of DDR_enable is
signal high_data, low_data : std_logic_vector( SIZE-1 downto 0 );
begin
HIGH_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
high_data <= ( others=>'0' );
elsif ( clk'event and clk='1' ) then
if ( enable/=C_DISABLE ) then -- v. 1.2
high_data <= din_hi;
end if;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
LOW_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
low_data <= ( others=>'0' );
elsif ( clk'event and clk='0' ) then
if ( enable/=C_DISABLE ) then -- v. 1.2
low_data <= din_lo;
end if;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
dout_hi <= high_data;
dout_lo <= low_data;
end small;
| mit | 00987962b2f72fbefae3fba9529bb457 | 0.565574 | 3.227513 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/Aff_Trans_Inv.vhd | 2 | 701 |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans_inv is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans_inv;
-- Architecture of the Component
architecture a_aff_trans_inv of aff_trans_inv is
begin
-- Tranformation Process
b_out(0) <= not (a(5)) xor a(2) xor a(7);
b_out(1) <= a(0) xor a(3) xor a(6);
b_out(2) <= not (a(7)) xor a(1) xor a(4);
b_out(3) <= a(2) xor a(0) xor a(5);
b_out(4) <= a(1) xor a(3) xor a(6);
b_out(5) <= a(4) xor a(2) xor a(7);
b_out(6) <= a(3) xor a(0) xor a(5);
b_out(7) <= a(1) xor a(4) xor a(6);
end a_aff_trans_inv;
| mit | 3e951316da186cfc599eed04b75da112 | 0.583452 | 2.360269 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/mux44to1.vhd | 1 | 1,304 | -------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : mux44to1.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Multiplexer 4 inputs, 4 selector and one output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of mux44to1 is
begin
process(sel_i, digits_i)
begin
case sel_i is
when "00" => digit_o <= digits_i(3 downto 0); -- Digit 1
when "01" => digit_o <= digits_i(7 downto 4); -- Digit 2
when "10" => digit_o <= digits_i(11 downto 8); -- Digit 3
when others => digit_o <= digits_i(15 downto 12); -- Digit 3
end case;
end process;
end rtl; | mit | fd8bea2fe50cf4326625c74c9caf3d08 | 0.417945 | 4.811808 | false | false | false | false |
chastell/art-decomp | kiss/s8_rnd.vhd | 1 | 2,612 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s8_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s8_rnd;
architecture behaviour of s8_rnd is
constant s1: std_logic_vector(2 downto 0) := "101";
constant s2: std_logic_vector(2 downto 0) := "010";
constant s3: std_logic_vector(2 downto 0) := "011";
constant s5: std_logic_vector(2 downto 0) := "110";
constant s4: std_logic_vector(2 downto 0) := "111";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s1 =>
if std_match(input, "1000") then next_state <= s1; output <= "1";
elsif std_match(input, "0100") then next_state <= s1; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s2; output <= "1";
end if;
when s2 =>
if std_match(input, "1000") then next_state <= s2; output <= "1";
elsif std_match(input, "0100") then next_state <= s3; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s1; output <= "1";
end if;
when s3 =>
if std_match(input, "1000") then next_state <= s3; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s5; output <= "1";
end if;
when s4 =>
if std_match(input, "1000") then next_state <= s4; output <= "1";
elsif std_match(input, "0100") then next_state <= s2; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s3; output <= "1";
end if;
when s5 =>
if std_match(input, "1000") then next_state <= s5; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s1; output <= "1";
elsif std_match(input, "0001") then next_state <= s4; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | c2bdeb770cd4ed73f555491029e92ae1 | 0.582695 | 3.20098 | false | false | false | false |
chastell/art-decomp | kiss/bbtas_rnd.vhd | 1 | 3,027 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbtas_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbtas_rnd;
architecture behaviour of bbtas_rnd is
constant st0: std_logic_vector(2 downto 0) := "101";
constant st1: std_logic_vector(2 downto 0) := "010";
constant st2: std_logic_vector(2 downto 0) := "011";
constant st3: std_logic_vector(2 downto 0) := "110";
constant st4: std_logic_vector(2 downto 0) := "111";
constant st5: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st1; output <= "00";
elsif std_match(input, "10") then next_state <= st1; output <= "00";
elsif std_match(input, "11") then next_state <= st1; output <= "00";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st2; output <= "00";
elsif std_match(input, "10") then next_state <= st2; output <= "00";
elsif std_match(input, "11") then next_state <= st2; output <= "00";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st1; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "00";
elsif std_match(input, "10") then next_state <= st3; output <= "00";
elsif std_match(input, "11") then next_state <= st3; output <= "00";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st4; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "01";
elsif std_match(input, "10") then next_state <= st3; output <= "10";
elsif std_match(input, "11") then next_state <= st3; output <= "11";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st5; output <= "00";
elsif std_match(input, "01") then next_state <= st4; output <= "00";
elsif std_match(input, "10") then next_state <= st4; output <= "00";
elsif std_match(input, "11") then next_state <= st4; output <= "00";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st5; output <= "00";
elsif std_match(input, "10") then next_state <= st5; output <= "00";
elsif std_match(input, "11") then next_state <= st5; output <= "00";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | d35499b40d1a8cb0140f8d0fd2343ab1 | 0.582094 | 3.230523 | false | false | false | false |
chastell/art-decomp | kiss/train4_jed.vhd | 1 | 2,066 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_jed;
architecture behaviour of train4_jed is
constant st0: std_logic_vector(1 downto 0) := "11";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "00";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | e172cbc0265879d2601bce0769623359 | 0.587609 | 3.238245 | false | false | false | false |
chastell/art-decomp | kiss/sand_nov.vhd | 1 | 20,706 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sand_nov is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(8 downto 0)
);
end sand_nov;
architecture behaviour of sand_nov is
constant st0: std_logic_vector(4 downto 0) := "00111";
constant st1: std_logic_vector(4 downto 0) := "11011";
constant st2: std_logic_vector(4 downto 0) := "11010";
constant st3: std_logic_vector(4 downto 0) := "11000";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00011";
constant st6: std_logic_vector(4 downto 0) := "11100";
constant st7: std_logic_vector(4 downto 0) := "01111";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "10111";
constant st10: std_logic_vector(4 downto 0) := "10100";
constant st11: std_logic_vector(4 downto 0) := "01000";
constant st12: std_logic_vector(4 downto 0) := "00100";
constant st13: std_logic_vector(4 downto 0) := "00101";
constant st14: std_logic_vector(4 downto 0) := "11110";
constant st15: std_logic_vector(4 downto 0) := "10011";
constant st16: std_logic_vector(4 downto 0) := "01001";
constant st17: std_logic_vector(4 downto 0) := "00110";
constant st18: std_logic_vector(4 downto 0) := "11101";
constant st19: std_logic_vector(4 downto 0) := "00010";
constant st20: std_logic_vector(4 downto 0) := "11111";
constant st21: std_logic_vector(4 downto 0) := "10000";
constant st22: std_logic_vector(4 downto 0) := "01010";
constant st23: std_logic_vector(4 downto 0) := "10101";
constant st24: std_logic_vector(4 downto 0) := "01011";
constant st25: std_logic_vector(4 downto 0) := "01100";
constant st26: std_logic_vector(4 downto 0) := "10001";
constant st27: std_logic_vector(4 downto 0) := "10110";
constant st28: std_logic_vector(4 downto 0) := "01101";
constant st29: std_logic_vector(4 downto 0) := "10010";
constant st30: std_logic_vector(4 downto 0) := "01110";
constant st31: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---------";
case current_state is
when st0 =>
if std_match(input, "---------0-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----0----1-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----1---11-") then next_state <= st5; output <= "011001000";
elsif std_match(input, "----1---01-") then next_state <= st1; output <= "11-001000";
end if;
when st1 =>
if std_match(input, "0000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0100---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0100---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0101---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0101---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0110---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0110---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0111---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0111---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1100---0---") then next_state <= st4; output <= "1010-0100";
elsif std_match(input, "1101---0---") then next_state <= st3; output <= "0000-0110";
elsif std_match(input, "1111--10---") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "1111--00---") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st2 =>
if std_match(input, "-------0-0-") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "-------0-10") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----0-00-11") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "----1-00-11") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "------10-11") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st3 =>
if std_match(input, "------10--1") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-----010--0") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "-----110--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "------00--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st4 =>
if std_match(input, "------10-00") then next_state <= st4; output <= "0000-0000";
elsif std_match(input, "------10-01") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "------00-00") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st4; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st3; output <= "11-0-0000";
elsif std_match(input, "------10-1-") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0---00";
end if;
when st5 =>
if std_match(input, "0000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0000-----1-") then next_state <= st31; output <= "010110100";
elsif std_match(input, "0001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0001-----1-") then next_state <= st25; output <= "010110100";
elsif std_match(input, "0010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0010-----1-") then next_state <= st19; output <= "010110100";
elsif std_match(input, "0011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "0100-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0100-----1-") then next_state <= st29; output <= "010110100";
elsif std_match(input, "0101-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0101-----1-") then next_state <= st23; output <= "010110100";
elsif std_match(input, "0110-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0110-----1-") then next_state <= st17; output <= "010110100";
elsif std_match(input, "0111-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0111-----1-") then next_state <= st13; output <= "010110100";
elsif std_match(input, "1000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1000-----1-") then next_state <= st27; output <= "010110100";
elsif std_match(input, "1001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1001-----1-") then next_state <= st21; output <= "010110100";
elsif std_match(input, "1010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1010-----1-") then next_state <= st15; output <= "010110100";
elsif std_match(input, "1011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "1100-------") then next_state <= st12; output <= "101100100";
elsif std_match(input, "1101-------") then next_state <= st10; output <= "011100110";
elsif std_match(input, "1111-------") then next_state <= st7; output <= "011100000";
end if;
when st6 =>
if std_match(input, "----------0") then next_state <= st5; output <= "000100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "000101000";
elsif std_match(input, "----1-0---1") then next_state <= st7; output <= "011101000";
end if;
when st7 =>
if std_match(input, "-----1---1-") then next_state <= st8; output <= "100000000";
elsif std_match(input, "-----0---1-") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "---------0-") then next_state <= st7; output <= "000100000";
end if;
when st8 =>
if std_match(input, "0000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "00111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0110-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0111-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01110----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "10111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11000----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11010----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1111-------") then next_state <= st8; output <= "000000000";
end if;
when st9 =>
if std_match(input, "----------1") then next_state <= st8; output <= "001001000";
elsif std_match(input, "----------0") then next_state <= st8; output <= "000000000";
end if;
when st10 =>
if std_match(input, "------1--10") then next_state <= st11; output <= "---000010";
elsif std_match(input, "------1--00") then next_state <= st10; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st10; output <= "---101000";
end if;
when st11 =>
if std_match(input, "-----0-----") then next_state <= st11; output <= "---000000";
elsif std_match(input, "-----1-----") then next_state <= st5; output <= "011100000";
end if;
when st12 =>
if std_match(input, "------1--10") then next_state <= st5; output <= "001100000";
elsif std_match(input, "------1--00") then next_state <= st12; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st12; output <= "---101000";
end if;
when st13 =>
if std_match(input, "---------0-") then next_state <= st13; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st14; output <= "001100000";
end if;
when st14 =>
if std_match(input, "---------0-") then next_state <= st14; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st15; output <= "010110000";
end if;
when st15 =>
if std_match(input, "---------0-") then next_state <= st15; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st16; output <= "001100000";
end if;
when st16 =>
if std_match(input, "---------0-") then next_state <= st16; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st17; output <= "010110000";
end if;
when st17 =>
if std_match(input, "---------0-") then next_state <= st17; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st18; output <= "001100000";
end if;
when st18 =>
if std_match(input, "---------0-") then next_state <= st18; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st19; output <= "010110000";
end if;
when st19 =>
if std_match(input, "---------0-") then next_state <= st19; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st20; output <= "001100000";
end if;
when st20 =>
if std_match(input, "---------0-") then next_state <= st20; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st21; output <= "010110000";
end if;
when st21 =>
if std_match(input, "---------0-") then next_state <= st21; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st22; output <= "001100000";
end if;
when st22 =>
if std_match(input, "---------0-") then next_state <= st22; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st23; output <= "010110000";
end if;
when st23 =>
if std_match(input, "---------0-") then next_state <= st23; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st24; output <= "001100000";
end if;
when st24 =>
if std_match(input, "---------0-") then next_state <= st24; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st25; output <= "010110000";
end if;
when st25 =>
if std_match(input, "---------0-") then next_state <= st25; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st26; output <= "001100000";
end if;
when st26 =>
if std_match(input, "---------0-") then next_state <= st26; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st27; output <= "010110000";
end if;
when st27 =>
if std_match(input, "---------0-") then next_state <= st27; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st28; output <= "001100000";
end if;
when st28 =>
if std_match(input, "---------0-") then next_state <= st28; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st29; output <= "010110000";
end if;
when st29 =>
if std_match(input, "---------0-") then next_state <= st29; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st30; output <= "001100000";
end if;
when st30 =>
if std_match(input, "---------0-") then next_state <= st30; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st31; output <= "010110000";
end if;
when st31 =>
if std_match(input, "---------0-") then next_state <= st31; output <= "000110000";
elsif std_match(input, "---------10") then next_state <= st5; output <= "100100000";
elsif std_match(input, "------1--11") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "----0-0--11") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0--11") then next_state <= st7; output <= "011101000";
end if;
when others => next_state <= "-----"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 4a1af3dff7e199752d42263f3dff6c89 | 0.56061 | 3.451575 | false | false | false | false |
ibm2030/IBM2030 | ibm2030-switches.vhd | 1 | 22,125 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-switches.vhd
-- Creation Date: 21:49:37 20/01/2010
-- Description:
-- 360/30 Front Panel switch handling
-- Some switches are provided by the pushbuttons and sliders on the S3BOARD
-- Rotary switches are connected externally with a mixture of scanning and
-- discrete inputs. In all cases the "Process" position is not connected so
-- omitting the switches entirely allows the system to run normally.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.01 2010-07-20
-- [LJW] Add Switch connection information, no functional change
--
--
-- Func Port Pin Conn A2 A B C D E F G H J AC E' ROS Rate Check
-- Ground 1 - - - - - - - - - - - - - -
-- +5V 2 - - - - - - - - - - - - - -
-- +3.3V Vcco 3 - - - - - - - - - - C C C C
-- Hex0 pa_io1 E6 4 * * * * * * * * * # - - - -
-- Hex1 pa_io2 D5 5 * * * * * * * * * # - - - -
-- Hex2 pa_io3 C5 6 * * * * * * * * * # - - - -
-- Hex3 pa_io4 D6 7 * * * * * * * * * # - - - -
-- ScanA pa_io5 C6 8 S - - - - - - - - - - - - -
-- ScanB pa_io6 E7 9 - S - - - - - - - - - - - -
-- ScanC pa_io7 C7 10 - - S - - - - - - - - - - -
-- ScanD pa_io8 D7 11 - - - S - - - - - - - - - -
-- ScanE pa_io9 C8 12 - - - - S - - - - - - - - -
-- ScanF pa_io10 D8 13 - - - - - S - - - - - - - -
-- ScanG pa_io11 C9 14 - - - - - - S - - - - - - -
-- ScanH pa_io12 D10 15 - - - - - - - S - - - - - -
-- ScanJ pa_io13 A3 16 - - - - - - - - S - - - - -
-- ScanAC pa_io14 B4 17 - - - - - - - - - S - - - -
-- E_Inner pa_io15 A4 18 - - - - - - - - - - * - - -
-- E_Outer pa_io16 B5 19 - - - - - - - - - - * - - -
-- ROS InhCFStop pa_io17 A5 20 - - - - - - - - - - - * - -
-- ROS Scan pa_io18 B6 21 - - - - - - - - - - - * - -
-- Rate_InstrStep ma2_db0 B7 22 - - - - - - - - - - - - * -
-- Rate_SingleCyc ma2_db1 A7 23 - - - - - - - - - - - - * -
-- Check_Diag ma2_db2 B8 24 - - - - - - - - - - - - - *
-- Check_Disable ma2_db3 A8 25 - - - - - - - - - - - - - *
-- Check_Stop ma2_db4 A9 26 - - - - - - - - - - - - - *
-- Check_Restart ma2_db5 B10 27 - - - - - - - - - - - - - *
--
-- * = Hex0,1,2,3 inputs have diodes from each of the 9 hex-encoded switches A-J (A to switch, K to FPGA, total 36 diodes)
-- # = The Address Compare switch (AC) is 10-position, unencoded, with diodes to perform the 0-9 encoding (total 15 diodes)
-- S = Scan output to switch common (one output at a time goes high to scan)
-- C = Common connection for non-scanned switches
-- Switch E' is the selector switch which is part of switch E and selects the inner, middle or outer rings
-- The "Proc" positions of the ROS, Rate and Check switches are not connected - if no switches are present then these 3 and the AC switch default to "Proc"
-- The "Middle" position of the E selector switch is not connected - the default is therefore the MS/LS ring
-- Pulldowns are provided by the FPGA input
--
-- Most of the remaining switches are connected to the on-board pushbuttons and slide switches:
-- Reset
-- Start
-- Stop
-- Load
-- Lamp Test
-- ROAR Reset
-- Display
-- Store
-- Check Reset
-- Set IC
-- Interrupt
-- Fast/Slow clock control
-- Two switches are not used:
-- Power Off
-- Timer Interrupt
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity switches is
Port ( -- Raw switch inputs: (These can be modified to suit the board being used)
SwA_scan : out STD_LOGIC;
SwB_scan : out STD_LOGIC;
SwC_scan : out STD_LOGIC;
SwD_scan : out STD_LOGIC;
SwE_scan : out STD_LOGIC;
SwF_scan : out STD_LOGIC;
SwG_scan : out STD_LOGIC;
SwH_scan : out STD_LOGIC;
SwJ_scan : out STD_LOGIC;
SwAC_scan : out STD_LOGIC; -- Address Compare
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
SW_E_Inner, SW_E_Outer : in STD_LOGIC;
RawSw_Proc_Inh_CF_Stop, RawSw_Proc_Scan : in STD_LOGIC; -- ROS Control
RawSw_Rate_Single_Cycle, RawSw_Rate_Instruction_Step : in STD_LOGIC; -- Rate
RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control
pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons
sw : in std_logic_vector(7 downto 0); -- On-board slide switches
-- Scanned switch inputs - MAX7318 connections
SCL : out STD_LOGIC;
SDA : inout STD_LOGIC;
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
status_lamps : in STD_LOGIC_VECTOR(4 downto 0);
-- Conditioned switch outputs:
SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0);
SwAP,SwBP,SwCP,SwDP,SwFP,SwGP,SwHP,SwJP : out STD_LOGIC;
SwE : out E_SW_BUS_Type;
Sw_PowerOff, Sw_Interrupt, Sw_Load : out STD_LOGIC; -- Right-hand pushbuttons
Sw_SystemReset, Sw_RoarReset, Sw_Start, Sw_SetIC, Sw_CheckReset,
Sw_Stop, Sw_IntTmr, Sw_Store, Sw_LampTest, Sw_Display : out STD_LOGIC; -- Left-hand pushbuttons
Sw_Proc_Inh_CF_Stop, Sw_Proc_Proc, Sw_Proc_Scan : out STD_LOGIC; -- ROS Control
Sw_Rate_Single_Cycle, Sw_Rate_Instruction_Step, Sw_Rate_Process : out STD_LOGIC; -- Rate
Sw_Chk_Chk_Restart, Sw_Chk_Diagnostic, Sw_Chk_Stop, Sw_Chk_Process, Sw_Chk_Disable : out STD_LOGIC; -- Check Control
Sw_ROAR_RESTT,Sw_ROAR_RESTT_WITHOUT_RST,Sw_EARLY_ROAR_STOP,Sw_ROAR_STOP, Sw_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_SYNC,Sw_ADDR_COMP_PROC,Sw_SAR_DLYD_STOP,Sw_SAR_STOP,Sw_SAR_RESTART : out STD_LOGIC; -- Address Compare
-- 1kHz clock signal
Clock1ms : out STD_LOGIC;
-- 50Hz Timer signal
Timer : out STD_LOGIC
);
end switches;
architecture Behavioral of switches is
subtype debounce is std_logic_vector(0 to 3);
signal scan : std_logic_vector(3 downto 0) := "0000";
signal counter : std_logic_vector(14 downto 0) := (others=>'0');
signal counter1k : std_logic_vector(15 downto 0) := (others=>'0');
signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0');
signal SwE_raw,SwE_combined : std_logic_vector(3 downto 0) := "0000";
signal UseInner,UseMid,UseOuter : Boolean;
signal SwAC,SwAC_combined : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch
signal Parity_in : std_logic;
signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start,
RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest,
RawSw_Display : STD_LOGIC; -- Right-hand pushbuttons
signal debouncePowerOff, debounceInterrupt, debounceLoad,
debounceSystemReset, debounceRoarReset, debounceStart, debounceSetIC, debounceCheckReset,
debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce;
signal timerOut : std_logic := '0';
signal sClock1ms : std_logic := '0';
signal max7318_switches : std_logic_vector(0 to 63);
constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz
constant divider2000 : std_logic_vector(14 downto 0) := "110000110101000"; -- 25,000 gives 2kHz
constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999
constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer
begin
max7318 : entity panel_Switches port map (
clk => clk,
SCL => SCL,
SDA => SDA,
LEDs => status_lamps,
Switches => max7318_switches -- If the MAX7318 is not present, this vector should be all zero
);
Parity_in <= EvenParity(Hex_in);
scan_counter: process(clk)
begin
if (rising_edge(clk)) then
if counter=sample then
if scan="0000" then SwA <= Hex_in or max7318_switches(12 to 15); SwAP <= Parity_in; end if;
if scan="0001" then SwB <= Hex_in or max7318_switches(16 to 19); SwBP <= Parity_in; end if;
if scan="0010" then SwC <= Hex_in or max7318_switches(20 to 23); SwCP <= Parity_in; end if;
if scan="0011" then SwD <= Hex_in or max7318_switches(24 to 27); SwDP <= Parity_in; end if;
if scan="0100" then SwE_raw <= Hex_in or max7318_switches(36 to 39); end if;
if scan="0101" then SwF <= Hex_in or max7318_switches(28 to 31); SwFP <= Parity_in; end if;
if scan="0110" then SwG <= Hex_in or max7318_switches(40 to 43); SwGP <= Parity_in; end if;
if scan="0111" then SwH <= Hex_in or max7318_switches(44 to 47); SwHP <= Parity_in; end if;
if scan="1000" then SwJ <= Hex_in or max7318_switches(48 to 51); SwJP <= Parity_in; end if;
if scan="1001" then SwAC <= Hex_in or max7318_switches(4 to 7); end if;
end if;
if counter=divider then
counter<=(others=>'0');
if scan="1001" then
scan <= "0000";
else
scan <= scan + 1;
end if;
debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff;
debounceInterrupt <= debounceInterrupt(1 to 3) & (rawSw_Interrupt or max7318_switches(53));
debounceLoad <= debounceLoad(1 to 3) & (rawSw_Load or max7318_switches(52));
debounceSystemReset <= debounceSystemReset(1 to 3) & (rawSw_SystemReset or max7318_switches(63));
debounceRoarReset <= debounceRoarReset(1 to 3) & (rawSw_RoarReset or max7318_switches(61));
debounceStart <= debounceStart(1 to 3) & (rawSw_Start or max7318_switches(56));
debounceSetIC <= debounceSetIC(1 to 3) & (rawSw_SetIC or max7318_switches(60));
debounceCheckReset <= debounceCheckReset(1 to 3) & (rawSw_CheckReset or max7318_switches(58));
debounceStop <= debounceStop(1 to 3) & (rawSw_Stop or max7318_switches(55));
debounceIntTmr <= debounceIntTmr(1 to 3) & (rawSw_IntTmr or max7318_switches(62));
debounceStore <= debounceStore(1 to 3) & (rawSw_Store or max7318_switches(59));
debounceLampTest <= debounceLampTest(1 to 3) & (rawSw_LampTest or max7318_switches(57));
debounceDisplay <= debounceDisplay(1 to 3) & (rawSw_Display or max7318_switches(54));
if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if;
if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if;
if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if;
if (debounceSystemReset = "0000") then Sw_SystemReset <= '0'; else if (debounceSystemReset = "1111") then Sw_SystemReset <= '1'; end if; end if;
if (debounceRoarReset = "0000") then Sw_RoarReset <= '0'; else if (debounceRoarReset = "1111") then Sw_RoarReset <= '1'; end if; end if;
if (debounceStart = "0000") then Sw_Start <= '0'; else if (debounceStart = "1111") then Sw_Start <= '1'; end if; end if;
if (debounceSetIC = "0000") then Sw_SetIC <= '0'; else if (debounceSetIC = "1111") then Sw_SetIC <= '1'; end if; end if;
if (debounceCheckReset = "0000") then Sw_CheckReset <= '0'; else if (debounceCheckReset = "1111") then Sw_CheckReset <= '1'; end if; end if;
if (debounceStop = "0000") then Sw_Stop <= '0'; else if (debounceStop = "1111") then Sw_Stop <= '1'; end if; end if;
if (debounceIntTmr = "0000") then Sw_IntTmr <= '0'; else if (debounceIntTmr = "1111") then Sw_IntTmr <= '1'; end if; end if;
if (debounceStore = "0000") then Sw_Store <= '0'; else if (debounceStore = "1111") then Sw_Store <= '1'; end if; end if;
if (debounceLampTest = "0000") then Sw_LampTest <= '0'; else if (debounceLampTest = "1111") then Sw_LampTest <= '1'; end if; end if;
if (debounceDisplay = "0000") then Sw_Display <= '0'; else if (debounceDisplay = "1111") then Sw_Display <= '1'; end if; end if;
if (timerCounter = divider100) then
timerOut <= not timerOut;
Timer <= timerOut;
timerCounter <= (others=>'0');
else
timerCounter <= timerCounter + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
Clock1kHz : process(clk)
begin
if (rising_edge(clk)) then
if counter1k = divider2000 then
counter1k <= (others => '0');
sClock1ms <= not sClock1ms;
else
counter1k <= counter1k + 1;
end if;
end if;
end process;
Clock1ms <= sClock1ms;
SwA_scan <= '1' when scan="0000" else '0';
SwB_scan <= '1' when scan="0001" else '0';
SwC_scan <= '1' when scan="0010" else '0';
SwD_scan <= '1' when scan="0011" else '0';
SwE_scan <= '1' when scan="0100" else '0';
SwF_scan <= '1' when scan="0101" else '0';
SwG_scan <= '1' when scan="0110" else '0';
SwH_scan <= '1' when scan="0111" else '0';
SwJ_scan <= '1' when scan="1000" else '0';
SwAC_scan <= '1' when scan="1001" else '0';
-- Inner ring
UseInner <= (SW_E_INNER='1' or max7318_switches(34)='1');
UseMid <= SW_E_INNER='0' and max7318_switches(34)='0' and SW_E_OUTER='0' and max7318_switches(35)='0';
UseOuter <= (SW_E_OUTER='1' or max7318_switches(35)='1');
SwE_combined <= SwE_raw or max7318_switches(36 to 39);
SwE.I_SEL <= '1' when SwE_combined="0000" and UseInner else '0';
SwE.J_SEL <= '1' when SwE_combined="0001" and UseInner else '0';
SwE.U_SEL <= '1' when SwE_combined="0010" and UseInner else '0';
SwE.V_SEL <= '1' when SwE_combined="0011" and UseInner else '0';
SwE.L_SEL <= '1' when SwE_combined="0100" and UseInner else '0';
SwE.T_SEL <= '1' when SwE_combined="0101" and UseInner else '0';
SwE.D_SEL <= '1' when SwE_combined="0110" and UseInner else '0';
SwE.R_SEL <= '1' when SwE_combined="0111" and UseInner else '0';
SwE.S_SEL <= '1' when SwE_combined="1000" and UseInner else '0';
SwE.G_SEL <= '1' when SwE_combined="1001" and UseInner else '0';
SwE.H_SEL <= '1' when SwE_combined="1010" and UseInner else '0';
SwE.FI_SEL <= '1' when SwE_combined="1011" and UseInner else '0';
SwE.FT_SEL <= '1' when SwE_combined="1100" and UseInner else '0';
-- Mid ring
SwE.MS_SEL <= '1' when SwE_combined="0000" and UseMid else '0';
SwE.LS_SEL <= '1' when SwE_combined="0001" and UseMid else '0';
-- Outer ring
SwE.E_SEL_SW_GS <= '1' when SwE_combined="0000" and UseOuter else '0';
SwE.E_SEL_SW_GT <= '1' when SwE_combined="0001" and UseOuter else '0';
SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_combined="0010" and UseOuter else '0';
SwE.E_SEL_SW_HS <= '1' when SwE_combined="0011" and UseOuter else '0';
SwE.E_SEL_SW_HT <= '1' when SwE_combined="0100" and UseOuter else '0';
SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_combined="0101" and UseOuter else '0';
SwE.Q_SEL <= '1' when SwE_combined="0110" and UseOuter else '0';
SwE.C_SEL <= '1' when SwE_combined="0111" and UseOuter else '0';
SwE.F_SEL <= '1' when SwE_combined="1000" and UseOuter else '0';
SwE.TT_SEL <= '1' when SwE_combined="1001" and UseOuter else '0';
SwE.TI_SEL <= '1' when SwE_combined="1010" and UseOuter else '0';
SwE.JI_SEL <= '1' when SwE_combined="1011" and UseOuter else '0';
-- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- Address Compare
SwAC_combined <= SwAC or max7318_switches(4 to 7);
Sw_ADDR_COMP_PROC <= '1' when SwAC_combined="0000" else '0';
Sw_SAR_DLYD_STOP <= '1' when SwAC_combined="0001" else '0';
Sw_SAR_STOP <= '1' when SwAC_combined="0010" else '0';
Sw_SAR_RESTART <= '1' when SwAC_combined="0011" else '0';
Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC_combined="0100" else '0';
Sw_ROAR_RESTT <= '1' when SwAC_combined="0101" else '0';
Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC_combined="0110" else '0';
Sw_EARLY_ROAR_STOP <= '1' when SwAC_combined="0111" else '0';
Sw_ROAR_STOP <= '1' when SwAC_combined="1000" else '0';
Sw_ROAR_SYNC <= '1' when SwAC_combined="1001" else '0';
-- ROS Control
Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' or max7318_switches(0)='1' else '0';
Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' and max7318_switches(0 to 1)="00" else '0';
Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' or max7318_switches(1)='1' else '0';
-- Rate
Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' or max7318_switches(3)='1' else '0';
Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' and max7318_switches(2 to 3)="00" else '0';
Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' or max7318_switches(2)='1' else '0';
-- Check Control
Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' or max7318_switches(11)='1' else '0';
Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' or max7318_switches(8)='1' else '0';
Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' or max7318_switches(10)='1' else '0';
Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' and max7318_switches(8 to 11)="0000"else '0';
Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' or max7318_switches(9)='1' else '0';
-- Unimplemented switches
RawSw_PowerOff <= '0';
-- Pushbuttons
RawSw_SystemReset <= pb(0);
RawSw_Start <= pb(1);
RawSw_Load <= pb(2);
RawSw_Stop <= pb(3);
-- Slide switches
RawSw_IntTmr <= sw(0);
RawSw_Display <= sw(1);
RawSw_Store <= sw(2);
RawSw_Interrupt <= sw(3);
RawSw_RoarReset <= sw(4);
RawSw_SetIC <= sw(5);
RawSw_CheckReset <= sw(6);
RawSw_LampTest <= sw(7);
end behavioral;
| gpl-3.0 | 8d9e3652cd07506e6692462929723c49 | 0.540475 | 3.198641 | false | false | false | false |
chastell/art-decomp | kiss/s386_rnd.vhd | 1 | 7,731 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s386_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s386_rnd;
architecture behaviour of s386_rnd is
constant s000000: std_logic_vector(3 downto 0) := "1101";
constant s001100: std_logic_vector(3 downto 0) := "0010";
constant s010010: std_logic_vector(3 downto 0) := "1011";
constant s010000: std_logic_vector(3 downto 0) := "1110";
constant s001000: std_logic_vector(3 downto 0) := "1111";
constant s000100: std_logic_vector(3 downto 0) := "0001";
constant s000011: std_logic_vector(3 downto 0) := "0110";
constant s010001: std_logic_vector(3 downto 0) := "0000";
constant s010011: std_logic_vector(3 downto 0) := "1010";
constant s110000: std_logic_vector(3 downto 0) := "1000";
constant s100000: std_logic_vector(3 downto 0) := "0100";
constant s000010: std_logic_vector(3 downto 0) := "1001";
constant s000001: std_logic_vector(3 downto 0) := "1100";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "----11-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----100") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1-101") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0-101") then next_state <= s010000; output <= "0000001";
elsif std_match(input, "----0-0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----011") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "----001") then next_state <= s000000; output <= "0000000";
end if;
when s001100 =>
if std_match(input, "-1---00") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---00") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
elsif std_match(input, "-0---10") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---10") then next_state <= s001000; output <= "1000000";
elsif std_match(input, "-0---11") then next_state <= s001100; output <= "0000000";
elsif std_match(input, "-1---11") then next_state <= s000100; output <= "0010000";
end if;
when s001000 =>
if std_match(input, "-----00") then next_state <= s001000; output <= "0000000";
elsif std_match(input, "0----01") then next_state <= s000000; output <= "0101100";
elsif std_match(input, "1----01") then next_state <= s000000; output <= "0101000";
elsif std_match(input, "0----11") then next_state <= s001100; output <= "0101100";
elsif std_match(input, "1----11") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "-----10") then next_state <= s001000; output <= "0000000";
end if;
when s000100 =>
if std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----10") then next_state <= s001100; output <= "0110000";
elsif std_match(input, "-----11") then next_state <= s000100; output <= "0010000";
elsif std_match(input, "-----01") then next_state <= s000000; output <= "0000000";
end if;
when s010010 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000011; output <= "0000000";
end if;
when s000011 =>
if std_match(input, "--01-01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--00-01") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s010001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-1---01") then next_state <= s010011; output <= "0000010";
elsif std_match(input, "-0---01") then next_state <= s010001; output <= "0000010";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s010011 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s110000; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
end if;
when s110000 =>
if std_match(input, "-1---01") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "-0---01") then next_state <= s110000; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "------0") then next_state <= s001100; output <= "0100000";
end if;
when s100000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000010; output <= "0000000";
end if;
when s000010 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--10-00") then next_state <= s001100; output <= "0101000";
elsif std_match(input, "--00-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1-00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "---1101") then next_state <= s100000; output <= "0000001";
elsif std_match(input, "--10101") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--00101") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--10001") then next_state <= s000000; output <= "0001000";
elsif std_match(input, "--11001") then next_state <= s000010; output <= "0000000";
elsif std_match(input, "--00001") then next_state <= s010001; output <= "0100010";
elsif std_match(input, "--01001") then next_state <= s000010; output <= "0000000";
end if;
when s010000 =>
if std_match(input, "------0") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----01") then next_state <= s000001; output <= "0000000";
elsif std_match(input, "-----11") then next_state <= s001100; output <= "0100000";
end if;
when s000001 =>
if std_match(input, "-----1-") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "-----00") then next_state <= s001100; output <= "0100000";
elsif std_match(input, "--1--01") then next_state <= s010010; output <= "0000001";
elsif std_match(input, "--0--01") then next_state <= s010000; output <= "0000001";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | 1d13ad57be05fd2cbd3b613773324cab | 0.591256 | 3.602516 | false | false | false | false |
TheMassController/VHDL_experimenting | project/SPI/spi_slave_static.vhd | 1 | 3,777 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- A static SPI slave. It is static in the sense that all settings (frame size, polarity, ..)
-- are set before synthesis and cannot be changed afterwards.
-- The MSB is transmitted and received first, so if the word is 0101 (5), then we receive or send 0-1-0-1.
-- Two important properties are SPO (Clock polarity) and SPH (Phase Control)
-- Polarity is about the default or idle clock.
-- SPO = 0 means that if there is no data transfer, the clock is 0
-- SPO = 1 means that if there is no data transfer, the clock is 1
-- Phase control is about the edge on which data is read and set by both master and slave
-- SPH = 0 means read on rising edge and set on falling edge
-- SPH = 1 means read on falling edge and set on rising edge
entity spi_slave is
generic (
FRAME_SIZE_BIT_L2 : natural := 4;
POLARITY : std_logic := '0';
PHASE : std_logic := '0'
);
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
sclk : in STD_LOGIC; -- Serial clock
mosi : in STD_LOGIC; -- Master output slave input
miso : out STD_LOGIC; -- Master input slave output
ss : in STD_LOGIC; -- Slave Select
trans_data : in std_logic_vector(2**FRAME_SIZE_BIT_L2 - 1 downto 0);
receiv_data : out std_logic_vector(2**FRAME_SIZE_BIT_L2 - 1 downto 0);
done : out boolean
);
end spi_slave;
architecture Behavioral of spi_slave is
constant FRAME_SIZE_BIT : natural := 2**FRAME_SIZE_BIT_L2;
signal transceiver_active : boolean;
signal miso_int : std_logic;
signal sclk_int : std_logic;
signal cursor_ex : unsigned(FRAME_SIZE_BIT_L2 - 1 downto 0);
begin
slave_selected : process(ss, miso_int, sclk)
begin
if ss = '1' then
miso <= 'Z';
sclk_int <= POLARITY;
else
miso <= miso_int;
sclk_int <= sclk;
end if;
end process;
finish_generator : process(clk, transceiver_active)
variable lastVal : boolean := true;
begin
if rising_edge(clk) then
lastVal := not transceiver_active;
end if;
done <= not (transceiver_active or lastVal);
end process;
transceiver : process(clk, trans_data)
variable cursor : unsigned(FRAME_SIZE_BIT_L2 - 1 downto 0) := (others => '0');
variable data_out : std_logic_vector(receiv_data'RANGE) := (others => '0');
variable last_sclk : std_logic := '0';
begin
if rising_edge(clk) then
if rst = '1' then
if POLARITY = PHASE then
cursor := (others => '1');
else
cursor := (others => '0');
end if;
last_sclk := sclk;
elsif sclk_int /= last_sclk then
last_sclk := sclk_int;
if (PHASE = '0' and sclk_int = '0') or (PHASE = '1' and sclk_int = '1') then
cursor := cursor - 1;
elsif (PHASE = '0' and sclk_int = '1') or (PHASE = '1' and sclk_int = '0') then
data_out(to_integer(cursor)) := mosi;
end if;
end if;
end if;
if (last_sclk = '0' and POLARITY = '0') or (last_sclk = '1' and POLARITY = '1') then
if POLARITY = PHASE then
transceiver_active <= not(cursor = 2**FRAME_SIZE_BIT_L2 - 1);
else
transceiver_active <= not(cursor = 0);
end if;
end if;
receiv_data <= data_out;
miso_int <= trans_data(to_integer(cursor));
cursor_ex <= cursor;
end process;
end Behavioral;
| mit | f302edd4007f89969c783ab7d8be6959 | 0.552555 | 3.788365 | false | false | false | false |
chastell/art-decomp | kiss/s298_nov.vhd | 1 | 128,772 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s298_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s298_nov;
architecture behaviour of s298_nov is
constant s00000000000000: std_logic_vector(7 downto 0) := "00000100";
constant s00000001100000: std_logic_vector(7 downto 0) := "00001100";
constant s10000001100000: std_logic_vector(7 downto 0) := "00001010";
constant s01000001100001: std_logic_vector(7 downto 0) := "00001110";
constant s11001001100011: std_logic_vector(7 downto 0) := "00000010";
constant s00100001100011: std_logic_vector(7 downto 0) := "00000110";
constant s10101001100010: std_logic_vector(7 downto 0) := "00011010";
constant s01101001100010: std_logic_vector(7 downto 0) := "00011110";
constant s11101001100011: std_logic_vector(7 downto 0) := "00010010";
constant s00010001100010: std_logic_vector(7 downto 0) := "01101101";
constant s10010100011010: std_logic_vector(7 downto 0) := "11010011";
constant s00001100000001: std_logic_vector(7 downto 0) := "01111000";
constant s00000000011000: std_logic_vector(7 downto 0) := "00000000";
constant s10000001100010: std_logic_vector(7 downto 0) := "00010110";
constant s01000001100011: std_logic_vector(7 downto 0) := "00011000";
constant s11001001100001: std_logic_vector(7 downto 0) := "00010000";
constant s00100001100000: std_logic_vector(7 downto 0) := "00001011";
constant s10100001100010: std_logic_vector(7 downto 0) := "00000011";
constant s01100001100001: std_logic_vector(7 downto 0) := "00101101";
constant s11101000100110: std_logic_vector(7 downto 0) := "00111001";
constant s00011000100110: std_logic_vector(7 downto 0) := "00111000";
constant s10011000100100: std_logic_vector(7 downto 0) := "00111101";
constant s00000000100100: std_logic_vector(7 downto 0) := "00100100";
constant s10000001100011: std_logic_vector(7 downto 0) := "00001111";
constant s01001001100011: std_logic_vector(7 downto 0) := "00000111";
constant s11000001100000: std_logic_vector(7 downto 0) := "00001001";
constant s00100001100010: std_logic_vector(7 downto 0) := "00000001";
constant s10100001100011: std_logic_vector(7 downto 0) := "00001101";
constant s01101001100000: std_logic_vector(7 downto 0) := "00000101";
constant s11101001100010: std_logic_vector(7 downto 0) := "00011011";
constant s00011001100001: std_logic_vector(7 downto 0) := "00010011";
constant s10010001100010: std_logic_vector(7 downto 0) := "01111011";
constant s00001100000010: std_logic_vector(7 downto 0) := "01111110";
constant s10001100011000: std_logic_vector(7 downto 0) := "11011011";
constant s01001100000001: std_logic_vector(7 downto 0) := "01110000";
constant s11000100011001: std_logic_vector(7 downto 0) := "11010010";
constant s00101100000000: std_logic_vector(7 downto 0) := "01110110";
constant s00101100000001: std_logic_vector(7 downto 0) := "01100100";
constant s00101100000010: std_logic_vector(7 downto 0) := "01110010";
constant s00101100000011: std_logic_vector(7 downto 0) := "11110100";
constant s11000100011000: std_logic_vector(7 downto 0) := "11011010";
constant s00100100000011: std_logic_vector(7 downto 0) := "11111100";
constant s00100100000010: std_logic_vector(7 downto 0) := "11110000";
constant s00100100000001: std_logic_vector(7 downto 0) := "11111000";
constant s00100100000000: std_logic_vector(7 downto 0) := "11110110";
constant s11000100011010: std_logic_vector(7 downto 0) := "11010111";
constant s11000100011011: std_logic_vector(7 downto 0) := "11011111";
constant s01001100000000: std_logic_vector(7 downto 0) := "11111110";
constant s11001100011000: std_logic_vector(7 downto 0) := "11010110";
constant s11001100011001: std_logic_vector(7 downto 0) := "11011110";
constant s11001100011010: std_logic_vector(7 downto 0) := "11000011";
constant s11001100011011: std_logic_vector(7 downto 0) := "11001011";
constant s01001100000010: std_logic_vector(7 downto 0) := "11110101";
constant s01001100000011: std_logic_vector(7 downto 0) := "11111101";
constant s10001100011001: std_logic_vector(7 downto 0) := "11000010";
constant s01000100000000: std_logic_vector(7 downto 0) := "11100100";
constant s01000100000001: std_logic_vector(7 downto 0) := "11101100";
constant s01000100000010: std_logic_vector(7 downto 0) := "10111100";
constant s01000100000011: std_logic_vector(7 downto 0) := "11111010";
constant s10001100011011: std_logic_vector(7 downto 0) := "11001010";
constant s10001100011010: std_logic_vector(7 downto 0) := "11000111";
constant s00001100000011: std_logic_vector(7 downto 0) := "11110010";
constant s10000100011000: std_logic_vector(7 downto 0) := "11001111";
constant s10000100011001: std_logic_vector(7 downto 0) := "11000110";
constant s10000100011010: std_logic_vector(7 downto 0) := "11001110";
constant s10000100011011: std_logic_vector(7 downto 0) := "11010001";
constant s00001100000000: std_logic_vector(7 downto 0) := "11111001";
constant s10010001100011: std_logic_vector(7 downto 0) := "01100101";
constant s10010001100001: std_logic_vector(7 downto 0) := "01111001";
constant s00001010010001: std_logic_vector(7 downto 0) := "11110001";
constant s10000000011010: std_logic_vector(7 downto 0) := "00011111";
constant s01000001100010: std_logic_vector(7 downto 0) := "00010111";
constant s11000001100010: std_logic_vector(7 downto 0) := "00011001";
constant s00100001100001: std_logic_vector(7 downto 0) := "00010001";
constant s11000001100011: std_logic_vector(7 downto 0) := "00011101";
constant s00101001100010: std_logic_vector(7 downto 0) := "00010101";
constant s00101001100011: std_logic_vector(7 downto 0) := "01001010";
constant s00101001100000: std_logic_vector(7 downto 0) := "01000010";
constant s00101001100001: std_logic_vector(7 downto 0) := "01001011";
constant s11000001100001: std_logic_vector(7 downto 0) := "01000011";
constant s01000001100000: std_logic_vector(7 downto 0) := "01001110";
constant s10000000011011: std_logic_vector(7 downto 0) := "01000110";
constant s01001001100001: std_logic_vector(7 downto 0) := "01001111";
constant s01001001100000: std_logic_vector(7 downto 0) := "01000111";
constant s11001001100000: std_logic_vector(7 downto 0) := "01001000";
constant s11001001100010: std_logic_vector(7 downto 0) := "01000000";
constant s01001001100010: std_logic_vector(7 downto 0) := "01001001";
constant s10000000011001: std_logic_vector(7 downto 0) := "01000001";
constant s10000000011000: std_logic_vector(7 downto 0) := "01001100";
constant s00001010010000: std_logic_vector(7 downto 0) := "11111111";
constant s10001000011000: std_logic_vector(7 downto 0) := "11110111";
constant s01001000011011: std_logic_vector(7 downto 0) := "01000100";
constant s01001000011010: std_logic_vector(7 downto 0) := "01001101";
constant s01001000011001: std_logic_vector(7 downto 0) := "01000101";
constant s01001000011000: std_logic_vector(7 downto 0) := "01011010";
constant s10001000011001: std_logic_vector(7 downto 0) := "11111011";
constant s01000000011011: std_logic_vector(7 downto 0) := "01010010";
constant s01000000011010: std_logic_vector(7 downto 0) := "01011011";
constant s01000000011001: std_logic_vector(7 downto 0) := "01010011";
constant s01000000011000: std_logic_vector(7 downto 0) := "01011110";
constant s10001000011011: std_logic_vector(7 downto 0) := "11110011";
constant s10001000011010: std_logic_vector(7 downto 0) := "11101000";
constant s00001010010011: std_logic_vector(7 downto 0) := "11100000";
constant s00001010010010: std_logic_vector(7 downto 0) := "11101110";
constant s00000010010000: std_logic_vector(7 downto 0) := "00001000";
constant s10000001100001: std_logic_vector(7 downto 0) := "01010110";
constant s10010001100000: std_logic_vector(7 downto 0) := "01111111";
constant s00011001100000: std_logic_vector(7 downto 0) := "01011111";
constant s10011001100001: std_logic_vector(7 downto 0) := "01010111";
constant s00000001100001: std_logic_vector(7 downto 0) := "01011000";
constant s10001001100000: std_logic_vector(7 downto 0) := "01110011";
constant s10001001100001: std_logic_vector(7 downto 0) := "01111101";
constant s10001001100010: std_logic_vector(7 downto 0) := "01110001";
constant s10001001100011: std_logic_vector(7 downto 0) := "01110111";
constant s00000001100010: std_logic_vector(7 downto 0) := "01010000";
constant s00000001100011: std_logic_vector(7 downto 0) := "01011001";
constant s10011001100000: std_logic_vector(7 downto 0) := "01010001";
constant s10011001100011: std_logic_vector(7 downto 0) := "01011100";
constant s10011001100010: std_logic_vector(7 downto 0) := "01010100";
constant s00011001100011: std_logic_vector(7 downto 0) := "01011101";
constant s00011001100010: std_logic_vector(7 downto 0) := "01010101";
constant s11101001100001: std_logic_vector(7 downto 0) := "01101010";
constant s00010001100001: std_logic_vector(7 downto 0) := "01110101";
constant s10011010010000: std_logic_vector(7 downto 0) := "10101011";
constant s00000010010011: std_logic_vector(7 downto 0) := "01100010";
constant s00000010010010: std_logic_vector(7 downto 0) := "01101011";
constant s00000010010001: std_logic_vector(7 downto 0) := "01100011";
constant s10011010010001: std_logic_vector(7 downto 0) := "10101010";
constant s10011010010010: std_logic_vector(7 downto 0) := "10101001";
constant s10011010010011: std_logic_vector(7 downto 0) := "10101111";
constant s00010001100000: std_logic_vector(7 downto 0) := "01111010";
constant s10010010010011: std_logic_vector(7 downto 0) := "10101101";
constant s10010010010010: std_logic_vector(7 downto 0) := "10001111";
constant s10010010010000: std_logic_vector(7 downto 0) := "10100011";
constant s10010010010001: std_logic_vector(7 downto 0) := "10101000";
constant s00010001100011: std_logic_vector(7 downto 0) := "01101100";
constant s10011100011000: std_logic_vector(7 downto 0) := "11011001";
constant s00000100000010: std_logic_vector(7 downto 0) := "11100110";
constant s00000100000011: std_logic_vector(7 downto 0) := "11101101";
constant s00000100000000: std_logic_vector(7 downto 0) := "11100101";
constant s00000100000001: std_logic_vector(7 downto 0) := "11101010";
constant s10011100011001: std_logic_vector(7 downto 0) := "11010000";
constant s10011100011011: std_logic_vector(7 downto 0) := "11011000";
constant s10011100011010: std_logic_vector(7 downto 0) := "11010101";
constant s11101001100000: std_logic_vector(7 downto 0) := "01101110";
constant s01101001100001: std_logic_vector(7 downto 0) := "01100110";
constant s11100001100001: std_logic_vector(7 downto 0) := "00111010";
constant s00011000100111: std_logic_vector(7 downto 0) := "00111111";
constant s10010000100111: std_logic_vector(7 downto 0) := "00101100";
constant s10010000100110: std_logic_vector(7 downto 0) := "00100000";
constant s10010000100101: std_logic_vector(7 downto 0) := "00100110";
constant s10010000100100: std_logic_vector(7 downto 0) := "00101000";
constant s00011000100100: std_logic_vector(7 downto 0) := "00111100";
constant s10011000100110: std_logic_vector(7 downto 0) := "00111110";
constant s00000000100101: std_logic_vector(7 downto 0) := "00101110";
constant s00000000100110: std_logic_vector(7 downto 0) := "00100010";
constant s00000000100111: std_logic_vector(7 downto 0) := "00101010";
constant s10011000100111: std_logic_vector(7 downto 0) := "00110101";
constant s10011000100101: std_logic_vector(7 downto 0) := "00110001";
constant s00011000100101: std_logic_vector(7 downto 0) := "00110111";
constant s11100001100000: std_logic_vector(7 downto 0) := "00101001";
constant s00010000100100: std_logic_vector(7 downto 0) := "00010100";
constant s00010000100101: std_logic_vector(7 downto 0) := "01110100";
constant s00010000100110: std_logic_vector(7 downto 0) := "10110100";
constant s10010100011000: std_logic_vector(7 downto 0) := "11011101";
constant s10010100011001: std_logic_vector(7 downto 0) := "11000001";
constant s10010100011011: std_logic_vector(7 downto 0) := "11001001";
constant s00010000100111: std_logic_vector(7 downto 0) := "00011100";
constant s11100001100010: std_logic_vector(7 downto 0) := "00100001";
constant s11100001100011: std_logic_vector(7 downto 0) := "00101011";
constant s01101001100011: std_logic_vector(7 downto 0) := "01101111";
constant s10100001100000: std_logic_vector(7 downto 0) := "01100111";
constant s01100001100011: std_logic_vector(7 downto 0) := "00101111";
constant s11101000100111: std_logic_vector(7 downto 0) := "00110011";
constant s11101000100100: std_logic_vector(7 downto 0) := "00110100";
constant s11101000100101: std_logic_vector(7 downto 0) := "00110000";
constant s01100001100010: std_logic_vector(7 downto 0) := "00100011";
constant s11100000100111: std_logic_vector(7 downto 0) := "00110110";
constant s11100000100110: std_logic_vector(7 downto 0) := "00110010";
constant s11100000100100: std_logic_vector(7 downto 0) := "00100101";
constant s11100000100101: std_logic_vector(7 downto 0) := "00111011";
constant s01100001100000: std_logic_vector(7 downto 0) := "00100111";
constant s10100001100001: std_logic_vector(7 downto 0) := "01101000";
constant s10101001100011: std_logic_vector(7 downto 0) := "01100000";
constant s10101001100000: std_logic_vector(7 downto 0) := "01101001";
constant s10101001100001: std_logic_vector(7 downto 0) := "01100001";
constant s10100100011000: std_logic_vector(7 downto 0) := "11000000";
constant s01100100000010: std_logic_vector(7 downto 0) := "11100010";
constant s11100100011011: std_logic_vector(7 downto 0) := "11001000";
constant s00011100000001: std_logic_vector(7 downto 0) := "11101001";
constant s00011100000000: std_logic_vector(7 downto 0) := "11100001";
constant s00011100000010: std_logic_vector(7 downto 0) := "11101111";
constant s00011100000011: std_logic_vector(7 downto 0) := "11100111";
constant s11100100011010: std_logic_vector(7 downto 0) := "11000101";
constant s00010100000000: std_logic_vector(7 downto 0) := "11101011";
constant s00010100000001: std_logic_vector(7 downto 0) := "11100011";
constant s00010100000010: std_logic_vector(7 downto 0) := "01111100";
constant s00010100000011: std_logic_vector(7 downto 0) := "11011100";
constant s11100100011001: std_logic_vector(7 downto 0) := "11001101";
constant s11100100011000: std_logic_vector(7 downto 0) := "11000100";
constant s01100100000011: std_logic_vector(7 downto 0) := "11010100";
constant s11101100011001: std_logic_vector(7 downto 0) := "11001100";
constant s11101100011000: std_logic_vector(7 downto 0) := "10000011";
constant s11101100011010: std_logic_vector(7 downto 0) := "10010011";
constant s11101100011011: std_logic_vector(7 downto 0) := "10001011";
constant s01100100000001: std_logic_vector(7 downto 0) := "10111000";
constant s01100100000000: std_logic_vector(7 downto 0) := "10110000";
constant s10100100011001: std_logic_vector(7 downto 0) := "10011011";
constant s01101100000000: std_logic_vector(7 downto 0) := "10111110";
constant s01101100000001: std_logic_vector(7 downto 0) := "10110110";
constant s01101100000011: std_logic_vector(7 downto 0) := "10111101";
constant s01101100000010: std_logic_vector(7 downto 0) := "10110101";
constant s10100100011011: std_logic_vector(7 downto 0) := "10000010";
constant s10100100011010: std_logic_vector(7 downto 0) := "10010010";
constant s10101100011000: std_logic_vector(7 downto 0) := "10001010";
constant s10101100011001: std_logic_vector(7 downto 0) := "10011010";
constant s10101100011010: std_logic_vector(7 downto 0) := "10000111";
constant s10101100011011: std_logic_vector(7 downto 0) := "10010111";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "------";
case current_state is
when s00000000000000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "000000";
end if;
when s00000001100000 =>
if std_match(input, "000") then next_state <= s10000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10000001100000 =>
if std_match(input, "010") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100001 =>
if std_match(input, "001") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100011 =>
if std_match(input, "000") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100011 =>
if std_match(input, "010") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100010 =>
if std_match(input, "000") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100001; output <= "100001";
end if;
when s11101001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100001; output <= "100001";
end if;
when s00010001100010 =>
if std_match(input, "000") then next_state <= s10010100011010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10010100011010 =>
if std_match(input, "011") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011011; output <= "000000";
end if;
when s00000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "010100";
end if;
when s10000001100010 =>
if std_match(input, "010") then next_state <= s01000001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "100001";
end if;
when s11001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100010; output <= "100001";
end if;
when s00100001100000 =>
if std_match(input, "001") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100010 =>
if std_match(input, "011") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100001 =>
if std_match(input, "011") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100110 =>
if std_match(input, "000") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100110 =>
if std_match(input, "001") then next_state <= s10011000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100100; output <= "100010";
end if;
when s00000000100100 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "100010";
end if;
when s10000001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100001; output <= "100001";
end if;
when s01001001100011 =>
if std_match(input, "011") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00100001100000; output <= "100001";
end if;
when s00100001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100001; output <= "100001";
end if;
when s10100001100011 =>
if std_match(input, "011") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101001100000; output <= "100001";
end if;
when s11101001100010 =>
if std_match(input, "011") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100001 =>
if std_match(input, "011") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10010001100010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100001";
end if;
when s00001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011010; output <= "000000";
end if;
when s10001100011000 =>
if std_match(input, "010") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011011; output <= "000000";
end if;
when s11000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000011; output <= "010100";
end if;
when s00101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000001 =>
if std_match(input, "001") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011011; output <= "000000";
end if;
when s00101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011010; output <= "000000";
end if;
when s11000100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000000; output <= "010100";
end if;
when s00100100000011 =>
if std_match(input, "011") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10100100011010; output <= "000000";
end if;
when s00100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10101100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10101100011011; output <= "000000";
end if;
when s00100100000000 =>
if std_match(input, "000") then next_state <= s10100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11000100011010 =>
if std_match(input, "011") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11000100011011 =>
if std_match(input, "010") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000000 =>
if std_match(input, "000") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11001100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000011; output <= "010100";
end if;
when s11001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000010; output <= "010100";
end if;
when s11001100011010 =>
if std_match(input, "000") then next_state <= s00101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00101100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11001100011011 =>
if std_match(input, "001") then next_state <= s00100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00100100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00100100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01001100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011001; output <= "000000";
end if;
when s01001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011010; output <= "000000";
end if;
when s10001100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000011; output <= "010100";
end if;
when s01000100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011001; output <= "000000";
end if;
when s01000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011001; output <= "000000";
end if;
when s01000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11000100011010; output <= "000000";
end if;
when s01000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11001100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11001100011010; output <= "000000";
end if;
when s10001100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000000; output <= "010100";
end if;
when s10001100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000011; output <= "010100";
end if;
when s00001100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011011; output <= "000000";
end if;
when s10000100011000 =>
if std_match(input, "001") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10000100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000000; output <= "010100";
end if;
when s10000100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000100000011; output <= "010100";
end if;
when s10000100011011 =>
if std_match(input, "011") then next_state <= s01001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00001100000000 =>
if std_match(input, "011") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10010001100011 =>
if std_match(input, "001") then next_state <= s00001100000001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100001";
end if;
when s10010001100001 =>
if std_match(input, "000") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00001010010001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000000011000; output <= "001100";
end if;
when s10000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100001; output <= "010100";
end if;
when s01000001100010 =>
if std_match(input, "000") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11000001100010 =>
if std_match(input, "000") then next_state <= s00100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100000; output <= "100001";
end if;
when s11000001100011 =>
if std_match(input, "010") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100010 =>
if std_match(input, "001") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100011 =>
if std_match(input, "011") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100000 =>
if std_match(input, "001") then next_state <= s10101001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s10101001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10101001100000; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10100001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10100001100001; output <= "100001";
end if;
when s11000001100001 =>
if std_match(input, "001") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01000001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "100001";
end if;
when s10000000011011 =>
if std_match(input, "001") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "100001";
end if;
when s01001001100000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11001001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100001; output <= "100001";
end if;
when s11001001100010 =>
if std_match(input, "001") then next_state <= s00101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s00101001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01001001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "100001";
end if;
when s10000000011001 =>
if std_match(input, "010") then next_state <= s01001001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10000000011000 =>
if std_match(input, "000") then next_state <= s01000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s00001010010000 =>
if std_match(input, "000") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s10001000011000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "010100";
end if;
when s01001000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100000; output <= "010100";
end if;
when s01001000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100001; output <= "010100";
end if;
when s01001000011001 =>
if std_match(input, "001") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s01001000011000 =>
if std_match(input, "010") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
end if;
when s10001000011001 =>
if std_match(input, "001") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s01000000011011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100011; output <= "010100";
end if;
when s01000000011010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100011; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100001; output <= "010100";
end if;
when s01000000011001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "001") then next_state <= s11001001100011; output <= "010100";
elsif std_match(input, "011") then next_state <= s11001001100010; output <= "010100";
elsif std_match(input, "000") then next_state <= s11001001100001; output <= "010100";
elsif std_match(input, "010") then next_state <= s11001001100000; output <= "010100";
end if;
when s01000000011000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "010100";
elsif std_match(input, "000") then next_state <= s11000001100000; output <= "010100";
elsif std_match(input, "010") then next_state <= s11000001100001; output <= "010100";
elsif std_match(input, "001") then next_state <= s11000001100010; output <= "010100";
elsif std_match(input, "011") then next_state <= s11000001100011; output <= "010100";
end if;
when s10001000011011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "010100";
end if;
when s10001000011010 =>
if std_match(input, "000") then next_state <= s01001000011010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01001000011011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "010100";
end if;
when s00001010010011 =>
if std_match(input, "010") then next_state <= s10000000011010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000000011011; output <= "001100";
elsif std_match(input, "011") then next_state <= s10000000011000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00001010010010 =>
if std_match(input, "000") then next_state <= s10001000011010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001000011011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001000011000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001000011001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "001100";
end if;
when s00000010010000 =>
if std_match(input, "011") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s10000001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001001100000; output <= "100001";
end if;
when s10010001100000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "100001";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s00011001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100010; output <= "100001";
end if;
when s10011001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100011; output <= "100001";
end if;
when s00000001100001 =>
if std_match(input, "010") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10001001100000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011000; output <= "100001";
end if;
when s10001001100001 =>
if std_match(input, "000") then next_state <= s01000000011001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100010 =>
if std_match(input, "010") then next_state <= s01001000011011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01001000011010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01001000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01001000011001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
end if;
when s10001001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01000000011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01000000011010; output <= "100001";
elsif std_match(input, "011") then next_state <= s01000000011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s01000000011001; output <= "100001";
end if;
when s00000001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100001";
end if;
when s00000001100011 =>
if std_match(input, "011") then next_state <= s10001001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100000 =>
if std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "110") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "-00") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100000; output <= "100001";
end if;
when s10011001100010 =>
if std_match(input, "000") then next_state <= s00000001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s00000001100011; output <= "100001";
elsif std_match(input, "1-0") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "1-1") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s00000001100001; output <= "100001";
end if;
when s00011001100011 =>
if std_match(input, "011") then next_state <= s10010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00011001100010 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011001100010; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011001100011; output <= "100001";
end if;
when s11101001100001 =>
if std_match(input, "000") then next_state <= s00010001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s00010001100001 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100001";
end if;
when s10011010010000 =>
if std_match(input, "011") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010000; output <= "001100";
end if;
when s00000010010011 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "001100";
end if;
when s00000010010010 =>
if std_match(input, "011") then next_state <= s10000001100001; output <= "001100";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "001100";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
end if;
when s00000010010001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "001100";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "001100";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "001100";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "001100";
elsif std_match(input, "001") then next_state <= s10001001100011; output <= "001100";
end if;
when s10011010010001 =>
if std_match(input, "001") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "1-1") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "100") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "-10") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010010 =>
if std_match(input, "000") then next_state <= s00000010010010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "1-0") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "111") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "-01") then next_state <= s00000010010000; output <= "001100";
end if;
when s10011010010011 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00000010010000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00000010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00000010010011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00000010010010; output <= "001100";
end if;
when s00010001100000 =>
if std_match(input, "011") then next_state <= s10010010010011; output <= "100001";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100001";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100001";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100001";
end if;
when s10010010010011 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
end if;
when s10010010010010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "001100";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "001100";
end if;
when s10010010010000 =>
if std_match(input, "010") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s10010010010001 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "001100";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "001100";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "001100";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "001100";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "001100";
end if;
when s00010001100011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100001";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "100001";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100001";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100001";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100001";
end if;
when s10011100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000001; output <= "010100";
end if;
when s00000100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10000100011000; output <= "000000";
end if;
when s00000100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011010; output <= "000000";
end if;
when s00000100000000 =>
if std_match(input, "001") then next_state <= s10000100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10000100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10000100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10000100011001; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00000100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10001100011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s10001100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10001100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10001100011010; output <= "000000";
end if;
when s10011100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000001; output <= "010100";
end if;
when s10011100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000011; output <= "010100";
end if;
when s10011100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00000100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00000100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00000100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00000100000001; output <= "010100";
end if;
when s11101001100000 =>
if std_match(input, "011") then next_state <= s00011001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01101001100001 =>
if std_match(input, "000") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s11100001100001 =>
if std_match(input, "001") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s00011000100111 =>
if std_match(input, "000") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s10010000100111 =>
if std_match(input, "000") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
end if;
when s10010000100110 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001100000010; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001100000011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001100000000; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001100000001; output <= "100010";
end if;
when s10010000100101 =>
if std_match(input, "010") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010010; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
end if;
when s10010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s00001010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s00001010010001; output <= "100010";
elsif std_match(input, "011") then next_state <= s00001010010011; output <= "100010";
elsif std_match(input, "001") then next_state <= s00001010010010; output <= "100010";
end if;
when s00011000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011000100110; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011000100100; output <= "100010";
end if;
when s10011000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100111; output <= "100010";
end if;
when s00000000100101 =>
if std_match(input, "001") then next_state <= s10001001100011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
end if;
when s00000000100110 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10000001100011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10000001100010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10000001100001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10000001100000; output <= "100010";
end if;
when s00000000100111 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10001001100001; output <= "100010";
elsif std_match(input, "011") then next_state <= s10001001100000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10001001100010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10001001100011; output <= "100010";
end if;
when s10011000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00000000100100; output <= "100010";
end if;
when s10011000100101 =>
if std_match(input, "011") then next_state <= s00000000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00000000100111; output <= "100010";
elsif std_match(input, "1-1") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "1-0") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00000000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00000000100100; output <= "100010";
end if;
when s00011000100101 =>
if std_match(input, "000") then next_state <= s10010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100001100000 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100111; output <= "100001";
end if;
when s00010000100100 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010010010010; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010010010011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010010010001; output <= "100010";
end if;
when s00010000100101 =>
if std_match(input, "1--") then next_state <= s00000010010000; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011010010000; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011010010001; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011010010011; output <= "100010";
elsif std_match(input, "011") then next_state <= s10011010010010; output <= "100010";
end if;
when s00010000100110 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10010100011000; output <= "100010";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "100010";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "100010";
end if;
when s10010100011000 =>
if std_match(input, "010") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011001 =>
if std_match(input, "010") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10010100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00001100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00001100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00001100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00001100000001; output <= "010100";
end if;
when s00010000100111 =>
if std_match(input, "011") then next_state <= s10011100011000; output <= "100010";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "100010";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "100010";
elsif std_match(input, "000") then next_state <= s10011100011011; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "100010";
end if;
when s11100001100010 =>
if std_match(input, "001") then next_state <= s00010000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100001";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100001100011 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100001";
elsif std_match(input, "011") then next_state <= s00011000100100; output <= "100001";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100001";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100001";
end if;
when s01101001100011 =>
if std_match(input, "000") then next_state <= s11100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100001100010; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100001100000; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10100001100000 =>
if std_match(input, "011") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s01100001100011 =>
if std_match(input, "010") then next_state <= s11101000100110; output <= "100001";
elsif std_match(input, "000") then next_state <= s11101000100111; output <= "100001";
elsif std_match(input, "011") then next_state <= s11101000100100; output <= "100001";
elsif std_match(input, "001") then next_state <= s11101000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11101000100111 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100100; output <= "100010";
end if;
when s11101000100100 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100110; output <= "100010";
end if;
when s11101000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100100; output <= "100010";
end if;
when s01100001100010 =>
if std_match(input, "010") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "001") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s11100000100111 =>
if std_match(input, "011") then next_state <= s00011000100100; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100110 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00010000100101; output <= "100010";
end if;
when s11100000100100 =>
if std_match(input, "011") then next_state <= s00010000100111; output <= "100010";
elsif std_match(input, "001") then next_state <= s00010000100110; output <= "100010";
elsif std_match(input, "000") then next_state <= s00010000100100; output <= "100010";
elsif std_match(input, "010") then next_state <= s00010000100101; output <= "100010";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
end if;
when s11100000100101 =>
if std_match(input, "1--") then next_state <= s00000000100100; output <= "100010";
elsif std_match(input, "011") then next_state <= s00011000100110; output <= "100010";
elsif std_match(input, "001") then next_state <= s00011000100111; output <= "100010";
elsif std_match(input, "000") then next_state <= s00011000100101; output <= "100010";
elsif std_match(input, "010") then next_state <= s00011000100100; output <= "100010";
end if;
when s01100001100000 =>
if std_match(input, "001") then next_state <= s11100000100110; output <= "100001";
elsif std_match(input, "011") then next_state <= s11100000100111; output <= "100001";
elsif std_match(input, "000") then next_state <= s11100000100100; output <= "100001";
elsif std_match(input, "010") then next_state <= s11100000100101; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000000100100; output <= "100001";
end if;
when s10100001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100010; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100000; output <= "100001";
end if;
when s10101001100011 =>
if std_match(input, "001") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100010; output <= "100001";
elsif std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
end if;
when s10101001100000 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01101001100001; output <= "100001";
elsif std_match(input, "000") then next_state <= s01101001100000; output <= "100001";
elsif std_match(input, "011") then next_state <= s01101001100011; output <= "100001";
elsif std_match(input, "001") then next_state <= s01101001100010; output <= "100001";
end if;
when s10101001100001 =>
if std_match(input, "1--") then next_state <= s00000001100000; output <= "100001";
elsif std_match(input, "010") then next_state <= s01100001100000; output <= "100001";
elsif std_match(input, "000") then next_state <= s01100001100001; output <= "100001";
elsif std_match(input, "001") then next_state <= s01100001100011; output <= "100001";
elsif std_match(input, "011") then next_state <= s01100001100010; output <= "100001";
end if;
when s10100100011000 =>
if std_match(input, "001") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011000; output <= "000000";
end if;
when s11100100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000011; output <= "010100";
end if;
when s00011100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011000; output <= "000000";
end if;
when s00011100000000 =>
if std_match(input, "000") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00011100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011001; output <= "000000";
end if;
when s00011100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011010; output <= "000000";
end if;
when s11100100011010 =>
if std_match(input, "001") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s00010100000000 =>
if std_match(input, "010") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011000; output <= "000000";
end if;
when s00010100000010 =>
if std_match(input, "001") then next_state <= s10010100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s10010100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s10010100011010; output <= "000000";
elsif std_match(input, "010") then next_state <= s10010100011011; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s00010100000011 =>
if std_match(input, "000") then next_state <= s10011100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s10011100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s10011100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s10011100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s11100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000010; output <= "010100";
end if;
when s11100100011000 =>
if std_match(input, "010") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s01100100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011011; output <= "000000";
end if;
when s11101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000001; output <= "010100";
end if;
when s11101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "011") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000001; output <= "010100";
end if;
when s11101100011010 =>
if std_match(input, "011") then next_state <= s00011100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s00011100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s00011100000011; output <= "010100";
elsif std_match(input, "000") then next_state <= s00011100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s11101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s00010100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s00010100000010; output <= "010100";
elsif std_match(input, "001") then next_state <= s00010100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s00010100000000; output <= "010100";
end if;
when s01100100000001 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011011; output <= "000000";
end if;
when s01100100000000 =>
if std_match(input, "000") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s10100100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000010; output <= "010100";
end if;
when s01101100000000 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011000; output <= "000000";
end if;
when s01101100000001 =>
if std_match(input, "011") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
end if;
when s01101100000011 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "000") then next_state <= s11100100011011; output <= "000000";
elsif std_match(input, "010") then next_state <= s11100100011010; output <= "000000";
elsif std_match(input, "011") then next_state <= s11100100011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11100100011001; output <= "000000";
end if;
when s01101100000010 =>
if std_match(input, "1--") then next_state <= s00000000011000; output <= "000000";
elsif std_match(input, "001") then next_state <= s11101100011000; output <= "000000";
elsif std_match(input, "011") then next_state <= s11101100011001; output <= "000000";
elsif std_match(input, "010") then next_state <= s11101100011011; output <= "000000";
elsif std_match(input, "000") then next_state <= s11101100011010; output <= "000000";
end if;
when s10100100011011 =>
if std_match(input, "011") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10100100011010 =>
if std_match(input, "001") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
end if;
when s10101100011000 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000010; output <= "010100";
end if;
when s10101100011001 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000010; output <= "010100";
end if;
when s10101100011010 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "000") then next_state <= s01101100000010; output <= "010100";
elsif std_match(input, "010") then next_state <= s01101100000011; output <= "010100";
elsif std_match(input, "011") then next_state <= s01101100000001; output <= "010100";
elsif std_match(input, "001") then next_state <= s01101100000000; output <= "010100";
end if;
when s10101100011011 =>
if std_match(input, "1--") then next_state <= s00000000000000; output <= "010100";
elsif std_match(input, "001") then next_state <= s01100100000001; output <= "010100";
elsif std_match(input, "011") then next_state <= s01100100000000; output <= "010100";
elsif std_match(input, "010") then next_state <= s01100100000010; output <= "010100";
elsif std_match(input, "000") then next_state <= s01100100000011; output <= "010100";
end if;
when others => next_state <= "--------"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | fd2500f0fc22aad6958955e6704d434c | 0.644434 | 3.947397 | false | false | false | false |
chastell/art-decomp | kiss/modulo12_jed.vhd | 1 | 3,524 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity modulo12_jed is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(0 downto 0)
);
end modulo12_jed;
architecture behaviour of modulo12_jed is
constant st0: std_logic_vector(3 downto 0) := "1001";
constant st1: std_logic_vector(3 downto 0) := "1101";
constant st2: std_logic_vector(3 downto 0) := "1111";
constant st3: std_logic_vector(3 downto 0) := "1011";
constant st4: std_logic_vector(3 downto 0) := "1010";
constant st5: std_logic_vector(3 downto 0) := "1110";
constant st6: std_logic_vector(3 downto 0) := "0010";
constant st7: std_logic_vector(3 downto 0) := "0001";
constant st8: std_logic_vector(3 downto 0) := "0000";
constant st9: std_logic_vector(3 downto 0) := "0100";
constant st10: std_logic_vector(3 downto 0) := "1100";
constant st11: std_logic_vector(3 downto 0) := "1000";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "0") then next_state <= st0; output <= "0";
elsif std_match(input, "1") then next_state <= st1; output <= "0";
end if;
when st1 =>
if std_match(input, "0") then next_state <= st1; output <= "0";
elsif std_match(input, "1") then next_state <= st2; output <= "0";
end if;
when st2 =>
if std_match(input, "0") then next_state <= st2; output <= "0";
elsif std_match(input, "1") then next_state <= st3; output <= "0";
end if;
when st3 =>
if std_match(input, "0") then next_state <= st3; output <= "0";
elsif std_match(input, "1") then next_state <= st4; output <= "0";
end if;
when st4 =>
if std_match(input, "0") then next_state <= st4; output <= "0";
elsif std_match(input, "1") then next_state <= st5; output <= "0";
end if;
when st5 =>
if std_match(input, "0") then next_state <= st5; output <= "0";
elsif std_match(input, "1") then next_state <= st6; output <= "0";
end if;
when st6 =>
if std_match(input, "0") then next_state <= st6; output <= "0";
elsif std_match(input, "1") then next_state <= st7; output <= "0";
end if;
when st7 =>
if std_match(input, "0") then next_state <= st7; output <= "0";
elsif std_match(input, "1") then next_state <= st8; output <= "0";
end if;
when st8 =>
if std_match(input, "0") then next_state <= st8; output <= "0";
elsif std_match(input, "1") then next_state <= st9; output <= "0";
end if;
when st9 =>
if std_match(input, "0") then next_state <= st9; output <= "0";
elsif std_match(input, "1") then next_state <= st10; output <= "0";
end if;
when st10 =>
if std_match(input, "0") then next_state <= st10; output <= "0";
elsif std_match(input, "1") then next_state <= st11; output <= "0";
end if;
when st11 =>
if std_match(input, "0") then next_state <= st11; output <= "0";
elsif std_match(input, "1") then next_state <= st0; output <= "0";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 0b6c4e5cec7c93cfc094c898f6781e1d | 0.571226 | 3.180505 | false | false | false | false |
chastell/art-decomp | kiss/ex5_rnd.vhd | 1 | 3,826 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_rnd;
architecture behaviour of ex5_rnd is
constant s1: std_logic_vector(3 downto 0) := "1101";
constant s0: std_logic_vector(3 downto 0) := "0010";
constant s7: std_logic_vector(3 downto 0) := "1011";
constant s5: std_logic_vector(3 downto 0) := "1110";
constant s4: std_logic_vector(3 downto 0) := "1111";
constant s2: std_logic_vector(3 downto 0) := "0001";
constant s3: std_logic_vector(3 downto 0) := "0110";
constant s6: std_logic_vector(3 downto 0) := "0000";
constant s8: std_logic_vector(3 downto 0) := "1010";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s7; output <= "00";
elsif std_match(input, "10") then next_state <= s5; output <= "11";
elsif std_match(input, "11") then next_state <= s4; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s1; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "00";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "11";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s5; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 3fbbdd7e3cb35ff9e4aef400bef0085e | 0.564036 | 3.267293 | false | false | false | false |
chastell/art-decomp | kiss/opus_jed.vhd | 1 | 3,496 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_jed is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_jed;
architecture behaviour of opus_jed is
constant init0: std_logic_vector(3 downto 0) := "1011";
constant init1: std_logic_vector(3 downto 0) := "1111";
constant init2: std_logic_vector(3 downto 0) := "1110";
constant init4: std_logic_vector(3 downto 0) := "0110";
constant IOwait: std_logic_vector(3 downto 0) := "0111";
constant read0: std_logic_vector(3 downto 0) := "0100";
constant write0: std_logic_vector(3 downto 0) := "1101";
constant RMACK: std_logic_vector(3 downto 0) := "0101";
constant WMACK: std_logic_vector(3 downto 0) := "1100";
constant read1: std_logic_vector(3 downto 0) := "0011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----"; output <= "------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | bac51c3579adc7b7d88e666df7b7f0c3 | 0.588673 | 3.492507 | false | false | false | false |
chastell/art-decomp | kiss/train4_nov.vhd | 1 | 2,066 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_nov is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_nov;
architecture behaviour of train4_nov is
constant st0: std_logic_vector(1 downto 0) := "00";
constant st1: std_logic_vector(1 downto 0) := "10";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | eb37e875e0402549c824a358f0d738a1 | 0.587609 | 3.238245 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/dataunit_ddr.vhd | 2 | 6,942 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- DataUnit: this entity contains the actual encryption datapath (the control
-- and the key-related logic are in separate entities). It instantiate:
-- + the four columns making the AES states,
-- + the barrel shifter implementing the ShiftRows operation,
-- + a DDR register layer after the barrel shifter to balance the critical path
-----------------------------------------------------------------------
-- Component Declaration
entity dataunit_ddr is port (
inH : in std_logic_vector( 127 downto 0 );
key : in std_logic_vector( 127 downto 0 );
aux_sbox_in : in std_logic_vector(31 downto 0);
ctrl_dec : in T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
enable_SBox_sharing : T_ENABLE;
ctrl_barrel : in std_logic_vector( 1 downto 0 );
enable_main, enable_dual, select_dual1, select_dual2 : in T_ENABLE;
check_dual : in T_ENABLE;
clock, reset : in std_logic;
broken: out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
outH : out std_logic_vector( 127 downto 0 );
outKey : out std_logic_vector(31 downto 0);
fault_data_unit_port : in std_logic_vector( 7 downto 0 )
);
end dataunit_ddr;
-- Architecture of the Component
architecture a_dataunit of dataunit_ddr is
component column is port (
in_hi, in_lo : in std_logic_vector (7 downto 0);
side_in : in std_logic_vector( 31 downto 0 ); -- horizontal input for I/O
roundkey : in std_logic_vector( 31 downto 0 );
aux_sbox_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
enable_key_pre_add, enable_key_add, enable_MixCol, enable_H_in : T_ENABLE;
enable_SBox_sharing : T_ENABLE;
--ctrl_sub : in T_CTRL_SUB;
enable_main, enable_dual, select_dual1, select_dual2 : in T_ENABLE;
check_dual : in T_ENABLE;
clock, reset : in std_logic;
broken: out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
side_out : out std_logic_vector( 31 downto 0 );
aux_sbox_out : out std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0);
fault_injection : in std_logic_vector( 7 downto 0)
);
end component;
component DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component L_barrel is
generic ( SIZE : integer := 32 );
port (
d_in : in std_logic_vector (SIZE-1 downto 0);
amount : in std_logic_vector (1 downto 0); -- 0 to 3
d_out : out std_logic_vector (SIZE-1 downto 0) ) ;
end component;
component pos_trigger is port (
switch : in std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
clock, reset : in std_logic;
value : out std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 ) );
end component;
signal column_out, barrel_out, sbox_regs_hi, sbox_regs_lo : std_logic_vector(31 downto 0);
signal side_data_in, side_data_out : std_logic_vector( 127 downto 0 );
signal broken_col : std_logic_vector( 4*C_ERR_SIGNAL_SIZE-1 downto 0 );
signal broken_du : std_logic_vector( C_ERR_SIGNAL_SIZE-1 downto 0 );
-- Fort fault injection
signal fault_sig : std_logic_vector( 7 downto 0 );
signal no_fault_sig : std_logic_vector( 7 downto 0 ) := "00000000";
begin
side_data_in <= inH; --*
fault_sig <= fault_data_unit_port;
-- for_col : for I in 0 to 3 generate
col0 : column port map(
sbox_regs_hi( 7 downto 0 ), sbox_regs_lo( 7 downto 0 ),
side_data_in( 31 downto 0 ), --*
key( 31 downto 0 ),
aux_sbox_in( 7 downto 0 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE-1 downto 0 ),
side_data_out( 31 downto 0 ), --*
outKey( 7 downto 0 ),
column_out( 7 downto 0 ),
fault_sig(7 downto 0)
);
col1 : column port map(
sbox_regs_hi( 15 downto 8 ), sbox_regs_lo( 15 downto 8 ),
side_data_in( 63 downto 32 ), --*
key( 63 downto 32 ),
aux_sbox_in( 15 downto 8 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE*1+C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE ),
side_data_out( 63 downto 32 ), --*
outKey( 15 downto 8 ),
column_out( 15 downto 8 ),
no_fault_sig(7 downto 0) );
col2 : column port map(
sbox_regs_hi( 23 downto 16 ), sbox_regs_lo( 23 downto 16 ),
side_data_in( 95 downto 64 ), --*
key( 95 downto 64 ),
aux_sbox_in( 23 downto 16 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE*2+C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE*2 ),
side_data_out( 95 downto 64 ), --*
outKey( 23 downto 16 ),
column_out( 23 downto 16 ),
no_fault_sig(7 downto 0) );
col3 : column port map(
sbox_regs_hi( 31 downto 24 ), sbox_regs_lo( 31 downto 24 ),
side_data_in( 127 downto 96 ), --*
key( 127 downto 96 ),
aux_sbox_in( 31 downto 24 ),
ctrl_dec,
enable_key_pre_add, enable_key_add, enable_MixCol,
enable_H_in, enable_SBox_sharing,
enable_main, enable_dual, select_dual1, select_dual2, check_dual,
clock, reset,
broken_col( C_ERR_SIGNAL_SIZE*3+C_ERR_SIGNAL_SIZE-1 downto C_ERR_SIGNAL_SIZE*3 ),
side_data_out( 127 downto 96 ), --*
outKey( 31 downto 24 ),
column_out( 31 downto 24 ),
no_fault_sig(7 downto 0) );
-- end generate;
barrel_shifter : L_barrel port map( column_out, ctrl_barrel, barrel_out );
sbox_regs_layer : for I in 0 to 3 generate
sbox_DDR : DDR_register port map( din_hi=>barrel_out(8*I+7 downto 8*I),
din_lo=>barrel_out(8*I+7 downto 8*I),
dout_hi=>sbox_regs_hi(8*I+7 downto 8*I),
dout_lo=>sbox_regs_lo(8*I+7 downto 8*I),
rst=>reset, clk=>clock );
end generate; -- for I sbox_regs_layer
outH <= side_data_out; --*
broken_du <= not C_BROKEN
when ( broken_col = not( C_BROKEN & C_BROKEN & C_BROKEN & C_BROKEN ) )
else C_BROKEN;
broken <= broken_du;
end a_dataunit;
| mit | b7026223df3369a84e3fab12b2ebc211 | 0.598675 | 3.3375 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/PreMcRot.vhd | 2 | 1,375 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- This entity is used to rotate the inputs to the MixColumns component
-- in order to use the same basic entity (which computes MixCol for the
-- the first row) for any other row of the AES (the coefficients are in
-- fact the same, but rotated.
-----------------------------------------------------------------------
-- Component Declaration
entity PreMcRot is
generic( G_ROW : integer range 0 to 3 );
port (
in_0, in_1, in_2, in_3 : in std_logic_vector (7 downto 0);
out_0, out_1, out_2, out_3 : out std_logic_vector (7 downto 0) ) ;
end PreMcRot;
-- Architecture of the Component
architecture a_PreMcRot of PreMcRot is
begin
i0 : if ( G_ROW=0 ) generate
out_0 <= in_0;
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
end generate; -- 0
i1 : if ( G_ROW=1 ) generate
out_0 <= in_0;
out_1 <= in_2;
out_2 <= in_3;
out_3 <= in_1;
end generate; -- 1
i2 : if ( G_ROW=2 ) generate
out_0 <= in_0;
out_1 <= in_3;
out_2 <= in_1;
out_3 <= in_2;
end generate; -- 2
i3 : if ( G_ROW=3 ) generate
out_0 <= in_0;
out_1 <= in_1;
out_2 <= in_2;
out_3 <= in_3;
end generate; -- 3
end a_PreMcRot;
| mit | a15c98b07e4f39fcb438f5dff215fb3b | 0.526545 | 3.16092 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-03C.vhd | 1 | 13,264 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-03C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Clock Start & Stop control
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change PROC_STOP_LOOP condition to make STOP/START buttons happier
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ClockStartStop IS
port
(
-- Switches
SW_START,SW_LOAD,SW_SET_IC,SW_STOP : IN std_logic;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN std_logic;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN std_logic;
SW_PWR_OFF : IN std_logic;
-- Other inputs
ALLOW_MAN_OPER : IN std_logic;
FT3_MPX_SHARE_REQ : IN std_logic;
M_CONV_OSC : IN std_logic;
SEL_ROS_REQ : IN std_logic;
MACH_RST_3 : IN std_logic;
CLOCK_ON : IN std_logic;
SAR_DLYD_STOP_SW : IN std_logic;
MATCH : IN std_logic;
SALS : IN SALS_Bus;
FORCE_IJ_REQ : IN std_logic;
MACH_START_RST : IN std_logic;
MACH_RST_SW : IN std_logic;
USE_BASIC_CA_DECO : IN std_logic;
S_REG_1_DLYD : IN std_logic;
INTERRUPT : IN std_logic;
END_OF_E_CY_LCH : IN std_logic;
ANY_PRIORITY_PULSE : IN std_logic;
FORCE_IJ_REQ_LCH : IN std_logic;
P_CONV_OSC : IN std_logic;
MAN_OPERATION : IN std_logic;
ALLOW_WRITE : IN std_logic;
MACH_CHK_PULSE : IN std_logic;
MACH_CHK_RST : IN std_logic;
HZ_DEST_RST : IN std_logic;
FIRST_MACH_CHK : IN std_logic;
CHK_OR_DIAG_STOP_SW : IN std_logic;
ANY_MACH_CHK : IN std_logic;
MATCH_LCH : IN std_logic;
EARLY_ROAR_STOP_SW : IN std_logic;
ALU_CHK : IN std_logic;
DIAGNOSTIC_SW : IN std_logic;
CS_DECODE_X001 : IN std_logic;
BASIC_CS0 : IN std_logic;
SUPPR_MACH_CHK_TRAP : IN std_logic;
Z_BUS_0 : IN std_logic;
SAR_STOP_SW : IN std_logic;
ROAR_STOP_SW : IN std_logic;
ANY_PRIORITY_PULSE_PWR : IN std_logic;
GT_CK_DECODE : IN std_logic;
SX1_SHARE_CYCLE,SX2_SHARE_CYCLE : IN std_logic;
SEL_T4 : IN std_logic;
SEL_SHARE_HOLD : IN std_logic;
SEL_CONV_OSC : IN std_logic;
SEL_BASIC_CLOCK_OFF : IN std_logic;
GT_J_REG_TO_A_BUS : IN std_logic;
M_CONV_OSC_2 : IN std_logic;
MPX_SHARE_REQ : IN std_logic;
SYSTEM_RESET_SW : IN std_logic;
-- Outputs
START_SW_RST : OUT std_logic;
E_CY_STOP_SAMPLE : OUT std_logic;
LOAD_KEY_SW : OUT std_logic;
LOAD_KEY_INLK : OUT std_logic;
SET_IC_ALLOWED : OUT std_logic;
INH_ROSAR_SET : OUT std_logic;
STOP_REQ : OUT std_logic;
ROS_SCAN : OUT std_logic;
ROS_CTRL_PROC_SW : OUT std_logic;
FT_4_LD_IND : OUT std_logic;
LOAD_REQ_LCH : OUT std_logic;
LOAD_IND : OUT std_logic;
RST_SEL_CHNL_DIAG_LCHS : OUT std_logic;
RST_LOAD : OUT std_logic;
CLOCK_START_LCH : OUT std_logic;
PWR_OFF_SW : OUT std_logic;
N2ND_ERROR_STOP : OUT std_logic;
SEL_CHNL_CPU_CLOCK_STOP : OUT std_logic;
CLOCK_START : OUT std_logic;
EARLY_ROAR_STOP : OUT std_logic;
HARD_STOP_LCH : OUT std_logic;
-- CLOCK_RST : OUT std_logic;
-- CLOCK_STOP : OUT std_logic;
DEBUG : OUT std_logic;
-- Clocks
T2,T3,T4 : IN std_logic;
P1 : IN std_logic;
clk : IN std_logic
);
END ClockStartStop;
ARCHITECTURE slt OF ClockStartStop IS
signal STT_RST_INLK : std_logic := '1';
signal CLK_STT_CTRL : std_logic := '0';
signal SET_IC_START : std_logic;
signal SET_IC_INLK : std_logic := '1';
signal PROCESS_STOP : std_logic := '0';
signal PROC_STOP_LOOP_ACTIVE : std_logic;
signal LOAD_KEY : std_logic := '0';
signal CF100T4 : std_logic;
signal CF_STOP : std_logic := '0';
signal INSTRUCTION_STEP_SW : std_logic;
signal SINGLE_CYCLE_SW : std_logic;
signal HS_MACH_CHK, HS_ALU_CHK, HS_DIAG, HS_MATCH, HS_INSTR : std_logic;
signal LOAD_REQ : std_logic;
signal PWR_OFF : std_logic := '0';
signal sSTART_SW_RST : std_logic := '0';
signal sE_CY_STOP_SAMPLE : std_logic := '0';
signal sLOAD_KEY_SW : std_logic;
signal sLOAD_KEY_INLK : std_logic := '1';
signal sSET_IC_ALLOWED : std_logic := '0';
signal sROS_SCAN : std_logic;
signal sLOAD_IND : std_logic := '0';
signal sRST_SEL_CHNL_DIAG_LCHS : std_logic;
signal sRST_LOAD : std_logic;
signal sCLOCK_START_LCH : std_logic := '0';
signal sPWR_OFF_SW : std_logic;
signal sN2ND_ERROR_STOP : std_logic := '0';
signal sSEL_CHNL_CPU_CLOCK_STOP : std_logic;
signal sCLOCK_START : std_logic;
signal sEARLY_ROAR_STOP : std_logic;
signal sHARD_STOP_LCH : std_logic := '0';
signal sCLOCK_RST : std_logic;
signal sCLOCK_STOP : std_logic;
signal HS_DIAG_DEGLITCHED : std_logic;
-- The following signals are required to allow the FL components to instantiate
signal CSC_LCH_Set,SSR_LCH_Set,SSR_LCH_Reset,ECS_LCH_Set,ECS_LCH_Reset,LKI_LCH_Set,
LK_LCH_Set,LK_LCH_Reset,SI_LCH_Set,SI_LCH_Reset,SIA_LCH_Set,SIA_LCH_Reset,
PS_LCH_Set,PS_LCH_Reset,CFS_LCH_Reset,CS_LCH_Set,CS_LCH_Reset,N2E_LCH_Set,N2E_LCH_Reset,
PO_LCH_Set,HS_LCH_Set : std_logic;
BEGIN
-- Fig 5-03C
-- STT RST INLK
SRI_LCH: entity work.FLL port map(R=>sSTART_SW_RST,S=>SW_START,Q=>STT_RST_INLK); -- AC1G7 - Note inputs reversed to make inverted output
-- STT RST
SSR_LCH_Set <= ALLOW_MAN_OPER and STT_RST_INLK and not SW_START;
SSR_LCH_Reset <= T2 or MACH_RST_SW;
SSR_LCH: entity work.FLL port map(S=>SSR_LCH_Set,R=>SSR_LCH_Reset,Q=>sSTART_SW_RST); -- AC1G7
START_SW_RST <= sSTART_SW_RST;
-- CLK STT CTRL
CSC_LCH_Set <= sCLOCK_RST or sE_CY_STOP_SAMPLE;
CSC_LCH: entity work.FLL port map(S=>CSC_LCH_Set,R=>sSTART_SW_RST,Q=>CLK_STT_CTRL); -- AC1F5
-- E CY STOP SAMPLE
ECS_LCH_Set <= SET_IC_START or (FT3_MPX_SHARE_REQ and M_CONV_OSC and PROC_STOP_LOOP_ACTIVE) or
(M_CONV_OSC and PROC_STOP_LOOP_ACTIVE and SEL_ROS_REQ) or
(not SW_START and M_CONV_OSC and not CLK_STT_CTRL); -- "not CLK_STT_CTRL" ?? is CLK_STT_CTRL meant to be inverted?
ECS_LCH_Reset <= MACH_RST_SW or T4;
ECS_LCH: entity work.FLL port map(S=>ECS_LCH_Set, R=>ECS_LCH_Reset, Q=>sE_CY_STOP_SAMPLE); -- AC1F7
E_CY_STOP_SAMPLE <= sE_CY_STOP_SAMPLE;
-- LOAD KEY INLK
LKI_LCH_Set <= (not SW_LOAD and MACH_RST_3) or LOAD_KEY;
LKI_LCH: entity work.FLL port map(R=>LKI_LCH_Set, S=>SW_LOAD, Q=>sLOAD_KEY_INLK); -- AC1F7 - Note inputs reversed to make inverted output
LOAD_KEY_INLK <= sLOAD_KEY_INLK;
-- LOAD KEY
LK_LCH_Set <= not sLOAD_KEY_SW and sLOAD_KEY_INLK;
LK_LCH_Reset <= T4 or sCLOCK_RST;
LK_LCH: entity work.FLL port map(S=>LK_LCH_Set, R=>LK_LCH_Reset, Q=>LOAD_KEY); -- AC1F7
sLOAD_KEY_SW <= SW_LOAD;
LOAD_KEY_SW <= sLOAD_KEY_SW;
-- SET IC INLK
SI_LCH_Set <= (CLOCK_ON and SW_SET_IC) or MACH_RST_3 or sSET_IC_ALLOWED; -- MACH_RST_3 inverted??
SI_LCH_Reset <= not SW_SET_IC; -- FMD is missing invert on switch output??
SI_LCH: entity work.FLL port map(S=>SI_LCH_Set, R=>SI_LCH_Reset, Q=>SET_IC_INLK); -- AC1G7
-- SET IC
SIA_LCH_Set <= ALLOW_MAN_OPER and not SET_IC_INLK and SW_SET_IC;
SIA_LCH_Reset <= T2 or MACH_RST_SW;
SIA_LCH: entity work.FLL port map(S=>SIA_LCH_Set, R=>SIA_LCH_Reset, Q=>sSET_IC_ALLOWED); -- AC1G7
SET_IC_ALLOWED <= sSET_IC_ALLOWED;
SET_IC_START <= not FORCE_IJ_REQ_LCH and M_CONV_OSC and sSET_IC_ALLOWED; -- AC1D6
-- PROCESS STOP
PS_LCH_Set <= sSET_IC_ALLOWED or SW_STOP or (SAR_DLYD_STOP_SW and MATCH) or (INSTRUCTION_STEP_SW and T4);
PS_LCH_Reset <= sSTART_SW_RST or '0'; -- ?? What is second reset input?
PS_LCH: entity work.FLL port map(S=>PS_LCH_Set, R=>PS_LCH_Reset, Q=>PROCESS_STOP); -- AC1E5
DEBUG <= PROCESS_STOP; -- ?? DEBUG ??
-- PROC_STOP_LOOP_ACTIVE <= (not (USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed??
PROC_STOP_LOOP_ACTIVE <= ((USE_BASIC_CA_DECO and SALS.SALS_CA(0) and SALS.SALS_CA(1) and SALS.SALS_CA(2) and not SALS.SALS_CA(3)) and PROCESS_STOP and CF_STOP); -- AA2G5,AC1D5,AC1F5-removed?? and inverter on AA2G5 removed??
INH_ROSAR_SET <= PROC_STOP_LOOP_ACTIVE and not ANY_PRIORITY_PULSE; -- AC1D5
STOP_REQ <= PROCESS_STOP and not S_REG_1_DLYD and not INTERRUPT and END_OF_E_CY_LCH; -- AC1H7
-- CF STOP
CF100T4 <= SALS.SALS_CF(0) and not SALS.SALS_CF(1) and not SALS.SALS_CF(2) and T4; -- AA2G5
CFS_LCH_Reset <= (not CF100T4 and T4) or (not FORCE_IJ_REQ and not sROS_SCAN and not SW_PROC) or MACH_START_RST; -- AC1G5 AC1K6 AC1M5 AC1F2 ?? SW_INH_CF_STOP instead of SW_PROC ??
CFS_LCH: entity work.FLL port map(S=>CF100T4, R=>CFS_LCH_Reset, Q=>CF_STOP); -- AC1D5
sROS_SCAN <= SW_SCAN;
ROS_SCAN <= sROS_SCAN;
ROS_CTRL_PROC_SW <= SW_PROC;
SINGLE_CYCLE_SW <= SW_SINGLE_CYCLE;
INSTRUCTION_STEP_SW <= SW_INSTRUCTION_STEP;
-- LOAD REQ
sRST_LOAD <= GT_CK_DECODE and SALS.SALS_CK(0) and SALS.SALS_CK(1) and not SALS.SALS_CK(2) and SALS.SALS_CK(3); -- AB3F7
RST_LOAD <= sRST_LOAD;
sRST_SEL_CHNL_DIAG_LCHS <= MACH_RST_3 or sRST_LOAD; -- AC1F5,AC1H6
LOAD_REQ_FL: entity work.FLL port map(LOAD_KEY, sRST_SEL_CHNL_DIAG_LCHS, sLOAD_IND); -- AC1E5
RST_SEL_CHNL_DIAG_LCHS <= sRST_SEL_CHNL_DIAG_LCHS;
LOAD_IND <= sLOAD_IND;
LOAD_REQ <= sLOAD_IND;
LOAD_REQ_LCH <= sLOAD_IND; -- AC1F2
FT_4_LD_IND <= sLOAD_IND;
-- CLOCK START
CS_LCH_Set <= (LOAD_KEY and P_CONV_OSC) or (P_CONV_OSC and sE_CY_STOP_SAMPLE and not MAN_OPERATION);
CS_LCH_Reset <= sCLOCK_RST or sCLOCK_STOP;
CS_LCH: entity work.FLL port map(S=>CS_LCH_Set, R=>CS_LCH_Reset, Q=>sCLOCK_START_LCH); -- AC1K6
CLOCK_START_LCH <= sCLOCK_START_LCH;
sSEL_CHNL_CPU_CLOCK_STOP <= not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and T4) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_T4) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and not SEL_SHARE_HOLD) and
not (not SX1_SHARE_CYCLE and not SX2_SHARE_CYCLE and SEL_CONV_OSC and SEL_BASIC_CLOCK_OFF); -- AD1D2,AD1C4
SEL_CHNL_CPU_CLOCK_STOP <= sSEL_CHNL_CPU_CLOCK_STOP;
sCLOCK_START <= (not sSEL_CHNL_CPU_CLOCK_STOP and sCLOCK_START_LCH and not PWR_OFF) and ((GT_J_REG_TO_A_BUS or not CF_STOP) and sCLOCK_START_LCH); -- AC1E4,AC1G6 ?? CLOCK_START_LCH twice?
CLOCK_START <= sCLOCK_START;
-- 2ND ERR STP
N2E_LCH_Set <= MACH_CHK_PULSE and P1;
N2E_LCH_Reset <= MACH_CHK_RST or HZ_DEST_RST;
N2E_LCH: entity work.FLL port map(S=>N2E_LCH_Set, R=>N2E_LCH_Reset, Q=>sN2ND_ERROR_STOP); -- AB3F4
N2ND_ERROR_STOP <= sN2ND_ERROR_STOP;
--PWR OFF
sPWR_OFF_SW <= SW_PWR_OFF;
PWR_OFF_SW <= sPWR_OFF_SW;
PO_LCH_Set <= sPWR_OFF_SW and T3 and not ALLOW_WRITE;
PO_LCH: entity work.FLL port map(S=>PO_LCH_Set, R=>MACH_START_RST, Q=>PWR_OFF); -- AC1F4
-- HARD STOP
HS_MACH_CHK <= (sN2ND_ERROR_STOP and T4 and FIRST_MACH_CHK) or (CHK_OR_DIAG_STOP_SW and ANY_MACH_CHK); -- AB3F4
sEARLY_ROAR_STOP <= MATCH_LCH and EARLY_ROAR_STOP_SW; -- AC1K5
EARLY_ROAR_STOP <= sEARLY_ROAR_STOP;
HS_ALU_CHK <= CHK_OR_DIAG_STOP_SW and ALU_CHK and T4; -- AB3H3
-- Z0_DELAY: entity AR port map(Z_BUS_0,clk,Z_BUS_0_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
-- T4_DELAY: entity AR port map(T4,clk,T4_DLYD); -- Delay to ensure Z0 signal is there at the end of T4
HS_DIAG <= T4 and DIAGNOSTIC_SW and CS_DECODE_X001 and BASIC_CS0 and SUPPR_MACH_CHK_TRAP and not Z_BUS_0; -- AC1J6
-- DEGLITCH: entity DEGLITCH2 port map(HS_DIAG,clk,HS_DIAG_DEGLITCHED);
HS_MATCH <= (SAR_STOP_SW and MATCH_LCH and T4) or (ROAR_STOP_SW and T4 and MATCH_LCH) or (T4 and SINGLE_CYCLE_SW);
HS_INSTR <= T4 and INSTRUCTION_STEP_SW and ANY_PRIORITY_PULSE_PWR and sROS_SCAN; -- AB3H2
HS_LCH_Set <= HS_MACH_CHK or sEARLY_ROAR_STOP or HS_ALU_CHK or HS_DIAG or HS_MATCH or HS_INSTR;
HS_LCH: entity work.FLL port map(S=>HS_LCH_Set, R=>MACH_START_RST, Q=>sHARD_STOP_LCH); -- AB3H6
HARD_STOP_LCH <= sHARD_STOP_LCH;
sCLOCK_RST <= MACH_RST_3 or (sHARD_STOP_LCH and M_CONV_OSC_2) or (M_CONV_OSC_2 and not GT_J_REG_TO_A_BUS and CF_STOP); -- AC1F6,AC1G5
-- CLOCK_RST <= sCLOCK_RST;
sCLOCK_STOP <= (PROC_STOP_LOOP_ACTIVE and not SEL_ROS_REQ and not MPX_SHARE_REQ and T2) or (not LOAD_REQ and sLOAD_KEY_SW) or SYSTEM_RESET_SW; -- AC1H7,AC1J6,AC1J7
-- CLOCK_STOP <= sCLOCK_STOP;
END slt;
| gpl-3.0 | 01c788efa98d8f0ab5ff2a24a3e7f042 | 0.671668 | 2.601805 | false | false | false | false |
ibm2030/IBM2030 | shift_compare_serial.vhd | 1 | 5,918 | --*****************************************************************************************
--**
--** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
--** provided to you "as is". Xilinx and its licensors make and you
--** receive no warranties or conditions, express, implied, statutory
--** or otherwise, and Xilinx specifically disclaims any implied
--** warranties of merchantability, non-infringement, or fitness for a
--** particular purpose. Xilinx does not warrant that the functions
--** contained in these designs will meet your requirements, or that the
--** operation of these designs will be uninterrupted or error free, or
--** that defects in the Designs will be corrected. Furthermore, Xilinx
--** does not warrant or make any representations regarding use or the
--** results of the use of the designs in terms of correctness, accuracy,
--** reliability, or otherwise.
--**
--** LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be
--** liable for any loss of data, lost profits, cost or procurement of
--** substitute goods or services, or for any special, incidental,
--** consequential, or indirect damages arising from the use or operation
--** of the designs or accompanying documentation, however caused and on
--** any theory of liability. This limitation will apply even if Xilinx
--** has been advised of the possibility of such damage. This limitation
--** shall apply not-withstanding the failure of the essential purpose of
--** any limited remedies herein.
--**
--*****************************************************************************************
-- MODULE : shift_compare_serial.vhd
-- AUTHOR : Stephan Neuhold
-- VERSION : v1.00
--
--
-- REVISION HISTORY:
-- -----------------
-- No revisions
--
--
-- FUNCTION DESCRIPTION:
-- ---------------------
-- This module provides the shifting in of data
-- and comparing that data to the synchronisation
-- pattern. Once the synchronisation pattern has
-- been found, the last eight bits of data
-- shifted in are presented.
--
-- The shift register and comparator are
-- automatically scaled to the correct length
-- using the "length" generic.
--***************************
--* Library declarations
--***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--***********************
--* Entity declaration
--***********************
entity shift_compare_serial is
generic(
length : integer := 5
);
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
din : in std_logic;
b : in std_logic_vector((2**length) - 1 downto 0);
eq : out std_logic;
din_shifted : out std_logic_vector(7 downto 0)
);
end shift_compare_serial;
architecture Behavioral of shift_compare_serial is
signal q : std_logic_vector((2**length) - 1 downto 0);
signal r : std_logic_vector((2**length) downto 0);
signal a : std_logic_vector((2**length) - 1 downto 0);
signal b_swapped : std_logic_vector((2**length) - 1 downto 0);
signal GND : std_logic;
begin
--***************************************************
--* This process swaps the bits in the data byte.
--* This is done to present the data in the format
--* that it is entered in the PROM file.
--***************************************************
process (clock, a)
begin
for i in 0 to 7 loop
din_shifted(i) <= a(((2**length) - 1) - i);
end loop;
end process;
--*******************************************************
--* This process swaps the bits of every byte of the
--* synchronisation pattern. This is done so that
--* data read in from the PROM can be directly
--* compared. Data from the PROM is read with all
--* bits of every byte swapped.
--* e.g.
--* If the data in the PROM is 28h then this is read in
--* the following way:
--* 00010100
--*******************************************************
process (clock, b)
begin
for i in 0 to (((2**length) / 8) - 1) loop
for j in 0 to 7 loop
b_swapped((8 * i) + j) <= b(7 + (8 * i) - j);
end loop;
end loop;
end process;
--***********************************************
--* This is the first FF of the shift register.
--* It needs to be seperated from the rest
--* since it has a different input.
--***********************************************
GND <= '0';
r(0) <= '1';
Data_Shifter_0_Serial: FDRE
port map(
C => clock,
D => din,
CE => enable,
R => reset,
Q => a(0)
);
--***************************************************
--* This loop generates as many registers needed
--* based on the length of the synchronisation
--* word.
--***************************************************
Shifter_Serial:
for i in 1 to (2**length) - 1 generate
Data_Shifter_Serial: FDRE
port map(
C => clock,
D => a(i - 1),
CE => enable,
R => reset,
Q => a(i)
);
end generate;
--***********************************************
--* This loop generates as many LUTs and MUXCYs
--* as needed based on the length of the
--* synchronisation word.
--***********************************************
Comparator_Serial:
for i in 0 to (2**length) - 1 generate
Comparator_LUTs_Serial: LUT2
generic map(
INIT => X"9"
)
port map(
I0 => a(i),
I1 => b_swapped(i),
O => q(i)
);
Comparator_MUXs_Serial: MUXCY
port map(
DI => GND,
CI => r(i),
S => q(i),
O => r(i + 1)
);
end generate;
eq <= r(2**length);
end Behavioral;
| gpl-3.0 | bdea1be640aca498ed041cabc5549d68 | 0.527881 | 3.883202 | false | false | false | false |
chastell/art-decomp | kiss/keyb_hot.vhd | 1 | 16,633 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_hot;
architecture behaviour of keyb_hot is
constant st0: std_logic_vector(18 downto 0) := "1000000000000000000";
constant st1: std_logic_vector(18 downto 0) := "0100000000000000000";
constant st2: std_logic_vector(18 downto 0) := "0010000000000000000";
constant st3: std_logic_vector(18 downto 0) := "0001000000000000000";
constant st4: std_logic_vector(18 downto 0) := "0000100000000000000";
constant st5: std_logic_vector(18 downto 0) := "0000010000000000000";
constant st6: std_logic_vector(18 downto 0) := "0000001000000000000";
constant st7: std_logic_vector(18 downto 0) := "0000000100000000000";
constant st8: std_logic_vector(18 downto 0) := "0000000010000000000";
constant st9: std_logic_vector(18 downto 0) := "0000000001000000000";
constant st10: std_logic_vector(18 downto 0) := "0000000000100000000";
constant st11: std_logic_vector(18 downto 0) := "0000000000010000000";
constant st12: std_logic_vector(18 downto 0) := "0000000000001000000";
constant st13: std_logic_vector(18 downto 0) := "0000000000000100000";
constant st14: std_logic_vector(18 downto 0) := "0000000000000010000";
constant st15: std_logic_vector(18 downto 0) := "0000000000000001000";
constant st16: std_logic_vector(18 downto 0) := "0000000000000000100";
constant st17: std_logic_vector(18 downto 0) := "0000000000000000010";
constant st18: std_logic_vector(18 downto 0) := "0000000000000000001";
signal current_state, next_state: std_logic_vector(18 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-------------------"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 9a6489f6a4dcfe67b230f7a51845a2ad | 0.548007 | 3.40352 | false | false | false | false |
chastell/art-decomp | kiss/planet_rnd.vhd | 1 | 16,521 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity planet_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(18 downto 0)
);
end planet_rnd;
architecture behaviour of planet_rnd is
constant st0: std_logic_vector(5 downto 0) := "111101";
constant st1: std_logic_vector(5 downto 0) := "000010";
constant st2: std_logic_vector(5 downto 0) := "011011";
constant st3: std_logic_vector(5 downto 0) := "111110";
constant st4: std_logic_vector(5 downto 0) := "111111";
constant st42: std_logic_vector(5 downto 0) := "010001";
constant st5: std_logic_vector(5 downto 0) := "010110";
constant st6: std_logic_vector(5 downto 0) := "001011";
constant st7: std_logic_vector(5 downto 0) := "001111";
constant st41: std_logic_vector(5 downto 0) := "011110";
constant st38: std_logic_vector(5 downto 0) := "101011";
constant st8: std_logic_vector(5 downto 0) := "100001";
constant st10: std_logic_vector(5 downto 0) := "110000";
constant st9: std_logic_vector(5 downto 0) := "101111";
constant st11: std_logic_vector(5 downto 0) := "011010";
constant st12: std_logic_vector(5 downto 0) := "111000";
constant st13: std_logic_vector(5 downto 0) := "110110";
constant st14: std_logic_vector(5 downto 0) := "001000";
constant st15: std_logic_vector(5 downto 0) := "000001";
constant st16: std_logic_vector(5 downto 0) := "100100";
constant st17: std_logic_vector(5 downto 0) := "001001";
constant st18: std_logic_vector(5 downto 0) := "101001";
constant st19: std_logic_vector(5 downto 0) := "100110";
constant st46: std_logic_vector(5 downto 0) := "111011";
constant st24: std_logic_vector(5 downto 0) := "011100";
constant st20: std_logic_vector(5 downto 0) := "100011";
constant st25: std_logic_vector(5 downto 0) := "100010";
constant st21: std_logic_vector(5 downto 0) := "011000";
constant st22: std_logic_vector(5 downto 0) := "000011";
constant st23: std_logic_vector(5 downto 0) := "110111";
constant st26: std_logic_vector(5 downto 0) := "010011";
constant st28: std_logic_vector(5 downto 0) := "110010";
constant st30: std_logic_vector(5 downto 0) := "000111";
constant st27: std_logic_vector(5 downto 0) := "001100";
constant st29: std_logic_vector(5 downto 0) := "110101";
constant st31: std_logic_vector(5 downto 0) := "010100";
constant st32: std_logic_vector(5 downto 0) := "000000";
constant st33: std_logic_vector(5 downto 0) := "100111";
constant st35: std_logic_vector(5 downto 0) := "011101";
constant st34: std_logic_vector(5 downto 0) := "101101";
constant st36: std_logic_vector(5 downto 0) := "100101";
constant st37: std_logic_vector(5 downto 0) := "100000";
constant st39: std_logic_vector(5 downto 0) := "111100";
constant st40: std_logic_vector(5 downto 0) := "000100";
constant st43: std_logic_vector(5 downto 0) := "110011";
constant st44: std_logic_vector(5 downto 0) := "010111";
constant st45: std_logic_vector(5 downto 0) := "111010";
constant st47: std_logic_vector(5 downto 0) := "111001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when st0 =>
if std_match(input, "-------") then next_state <= st1; output <= "001011101000000---0";
end if;
when st1 =>
if std_match(input, "----01-") then next_state <= st1; output <= "--------0000000---0";
elsif std_match(input, "----10-") then next_state <= st1; output <= "--------0100000---1";
elsif std_match(input, "----00-") then next_state <= st1; output <= "1000----1000000---1";
elsif std_match(input, "----11-") then next_state <= st2; output <= "1000111110011001000";
end if;
when st2 =>
if std_match(input, "------0") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---0---") then next_state <= st3; output <= "1010010010000000000";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "1010----1010010---1";
end if;
when st3 =>
if std_match(input, "11-----") then next_state <= st4; output <= "001111101000000-010";
elsif std_match(input, "10-----") then next_state <= st4; output <= "0011111110000000-10";
elsif std_match(input, "0-0-01-") then next_state <= st4; output <= "--------000010000-0";
elsif std_match(input, "0-0-10-") then next_state <= st4; output <= "--------010010000-1";
elsif std_match(input, "0-0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "0-0-00-") then next_state <= st4; output <= "0110----100000000-1";
elsif std_match(input, "0-1-01-") then next_state <= st4; output <= "--------00011000000";
elsif std_match(input, "0-1-10-") then next_state <= st4; output <= "--------01011000001";
elsif std_match(input, "0-1-11-") then next_state <= st42; output <= "011011011001100--00";
elsif std_match(input, "0-1-00-") then next_state <= st4; output <= "0110----10010000001";
end if;
when st4 =>
if std_match(input, "-------") then next_state <= st5; output <= "1010010010000000000";
end if;
when st5 =>
if std_match(input, "--0----") then next_state <= st6; output <= "1000011110000000001";
elsif std_match(input, "--1----") then next_state <= st6; output <= "1000011110010000001";
end if;
when st6 =>
if std_match(input, "-1----0") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-110--1") then next_state <= st7; output <= "101001001000000-000";
elsif std_match(input, "-10---1") then next_state <= st41; output <= "101001001000000--00";
elsif std_match(input, "-111--1") then next_state <= st38; output <= "101001001000000--00";
elsif std_match(input, "-0-----") then next_state <= st7; output <= "1010010010000000-00";
end if;
when st7 =>
if std_match(input, "--1----") then next_state <= st8; output <= "0001101010010000000";
elsif std_match(input, "--0----") then next_state <= st8; output <= "0001101010000000000";
end if;
when st8 =>
if std_match(input, "--0----") then next_state <= st10; output <= "1010010010000000000";
elsif std_match(input, "--1----") then next_state <= st9; output <= "1010010010000000000";
end if;
when st9 =>
if std_match(input, "-11----") then next_state <= st11; output <= "001011101001000-000";
elsif std_match(input, "-01----") then next_state <= st11; output <= "0010111110010000-00";
elsif std_match(input, "-10----") then next_state <= st11; output <= "001011101000000-000";
elsif std_match(input, "-00----") then next_state <= st11; output <= "0010111110000000-00";
end if;
when st10 =>
if std_match(input, "--1----") then next_state <= st12; output <= "0010----10010000001";
elsif std_match(input, "--0----") then next_state <= st12; output <= "0010----10000000001";
end if;
when st11 =>
if std_match(input, "-------") then next_state <= st13; output <= "1010010010000000000";
end if;
when st12 =>
if std_match(input, "-------") then next_state <= st14; output <= "1010010010000000000";
end if;
when st13 =>
if std_match(input, "-11----") then next_state <= st15; output <= "010110011001000-000";
elsif std_match(input, "-10----") then next_state <= st15; output <= "010110011000000-000";
elsif std_match(input, "-01----") then next_state <= st15; output <= "0101100010010000-00";
elsif std_match(input, "-00----") then next_state <= st15; output <= "0101100010000000-00";
end if;
when st14 =>
if std_match(input, "--1----") then next_state <= st15; output <= "0101----10010000001";
elsif std_match(input, "--0----") then next_state <= st15; output <= "0101----10000000001";
end if;
when st15 =>
if std_match(input, "-------") then next_state <= st16; output <= "1010010010000000000";
end if;
when st16 =>
if std_match(input, "--1----") then next_state <= st17; output <= "0110010110010000001";
elsif std_match(input, "--0----") then next_state <= st17; output <= "0110010110000000001";
end if;
when st17 =>
if std_match(input, "---0---") then next_state <= st18; output <= "1010010010000000000";
elsif std_match(input, "01-1---") then next_state <= st19; output <= "101001001000001-0-0";
elsif std_match(input, "00-1--0") then next_state <= st19; output <= "1010010010000010--0";
elsif std_match(input, "00-1--1") then next_state <= st46; output <= "101001001000000---0";
elsif std_match(input, "11-1---") then next_state <= st24; output <= "101001001000001-000";
elsif std_match(input, "10-1--0") then next_state <= st24; output <= "1010010010000010-00";
elsif std_match(input, "10-1--1") then next_state <= st18; output <= "1010010010000000-00";
end if;
when st18 =>
if std_match(input, "--1----") then next_state <= st2; output <= "1000111110010000000";
elsif std_match(input, "0-0----") then next_state <= st2; output <= "1000----10000000001";
elsif std_match(input, "1-0----") then next_state <= st2; output <= "1000111110000000000";
end if;
when st19 =>
if std_match(input, "-10----") then next_state <= st20; output <= "100101001000000-0-0";
elsif std_match(input, "-00----") then next_state <= st20; output <= "1001010110000000--0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st20 =>
if std_match(input, "-10----") then next_state <= st19; output <= "101001001000000-0-0";
elsif std_match(input, "-11----") then next_state <= st21; output <= "101001001000000-0-0";
elsif std_match(input, "-01----") then next_state <= st19; output <= "1010010010000000--0";
elsif std_match(input, "-00----") then next_state <= st21; output <= "1010010010000000--0";
end if;
when st21 =>
if std_match(input, "-10----") then next_state <= st22; output <= "001111111000000-0-0";
elsif std_match(input, "-11----") then next_state <= st23; output <= "001111111001000--00";
elsif std_match(input, "-00----") then next_state <= st22; output <= "0011111010000000--0";
elsif std_match(input, "-01----") then next_state <= st23; output <= "001111101001000--00";
end if;
when st22 =>
if std_match(input, "-------") then next_state <= st19; output <= "10100100100000000-0";
end if;
when st23 =>
if std_match(input, "-------") then next_state <= st24; output <= "101001001000000--00";
end if;
when st24 =>
if std_match(input, "-------") then next_state <= st25; output <= "100011111000000--00";
end if;
when st25 =>
if std_match(input, "---0--0") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1--0") then next_state <= st28; output <= "101001001000010--00";
elsif std_match(input, "------1") then next_state <= st30; output <= "101001001000000--10";
end if;
when st26 =>
if std_match(input, "--0-01-") then next_state <= st27; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st27; output <= "--------0100100---1";
elsif std_match(input, "--0-00-") then next_state <= st27; output <= "0110----1000000---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--1----") then next_state <= st25; output <= "100011111001000--00";
end if;
when st27 =>
if std_match(input, "-------") then next_state <= st26; output <= "101001001000000---0";
end if;
when st28 =>
if std_match(input, "-------") then next_state <= st29; output <= "011001011000000--01";
end if;
when st29 =>
if std_match(input, "---1---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "--10---") then next_state <= st3; output <= "1010010010000001000";
elsif std_match(input, "--00---") then next_state <= st3; output <= "1010010010000000100";
end if;
when st30 =>
if std_match(input, "-------") then next_state <= st31; output <= "100001111000000---1";
end if;
when st31 =>
if std_match(input, "---0---") then next_state <= st26; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st32; output <= "101001001000000---0";
end if;
when st32 =>
if std_match(input, "--0----") then next_state <= st33; output <= "100101011000000---0";
elsif std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
end if;
when st33 =>
if std_match(input, "--10---") then next_state <= st32; output <= "101001001000000---0";
elsif std_match(input, "--0----") then next_state <= st34; output <= "101001001000000---0";
elsif std_match(input, "---1---") then next_state <= st34; output <= "101001001000000---0";
end if;
when st34 =>
if std_match(input, "--1----") then next_state <= st35; output <= "011011011001000--00";
elsif std_match(input, "--0----") then next_state <= st35; output <= "011011011000000---0";
end if;
when st35 =>
if std_match(input, "-------") then next_state <= st36; output <= "101001001000000--00";
end if;
when st36 =>
if std_match(input, "--0----") then next_state <= st37; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st37; output <= "011011101001000--00";
end if;
when st37 =>
if std_match(input, "-------") then next_state <= st9; output <= "1010010010000000100";
end if;
when st38 =>
if std_match(input, "--0-01-") then next_state <= st39; output <= "--------0000100---0";
elsif std_match(input, "--0-10-") then next_state <= st39; output <= "--------0100100---1";
elsif std_match(input, "--0-11-") then next_state <= st42; output <= "011011011000100---0";
elsif std_match(input, "--0-00-") then next_state <= st39; output <= "0110----1000000---1";
elsif std_match(input, "--1----") then next_state <= st40; output <= "100011111001000--00";
end if;
when st39 =>
if std_match(input, "-------") then next_state <= st38; output <= "101001001000000---0";
end if;
when st40 =>
if std_match(input, "-------") then next_state <= st41; output <= "101001001000000--10";
end if;
when st41 =>
if std_match(input, "-------") then next_state <= st42; output <= "011011011000000---0";
end if;
when st42 =>
if std_match(input, "-------") then next_state <= st43; output <= "101001001000000--00";
end if;
when st43 =>
if std_match(input, "--0----") then next_state <= st44; output <= "011011101000000--00";
elsif std_match(input, "--1----") then next_state <= st44; output <= "011011101001000--00";
end if;
when st44 =>
if std_match(input, "-------") then next_state <= st45; output <= "101001001000000--00";
end if;
when st45 =>
if std_match(input, "--0----") then next_state <= st6; output <= "0111001110000000100";
elsif std_match(input, "--1----") then next_state <= st6; output <= "0111001110010000100";
end if;
when st46 =>
if std_match(input, "--0----") then next_state <= st47; output <= "1000----1000000---1";
elsif std_match(input, "--1----") then next_state <= st0; output <= "100011111011010---0";
end if;
when st47 =>
if std_match(input, "-------") then next_state <= st46; output <= "101001001000000---0";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 4f94be2f9da319705daf4ecb3ce3bd3f | 0.579384 | 3.597779 | false | false | false | false |
ibm2030/IBM2030 | ccros.vhd | 1 | 218,587 | -- CCROS library
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE std.textio.all;
package CCROS is
subtype CCROS_Address_Type is integer range 0 to 4095;
subtype CCROS_Word_Type is std_logic_vector(0 to 54);
type CCROS_Type is array(CCROS_Address_Type) of CCROS_Word_Type;
impure function readCCROS return CCROS_Type;
constant Package_CCROS : CCROS_Type :=
(
-- Replace below these comments, to the next comment
-- PCCCCCCPPCCCCCCCCCCCCCCCCCCCCCCCPPCCCCCCCCCCCCCCCCCCAAA
-- NNNNNNNSAHHHHLLLLMMMUUAAAABBKKKKKCDDDDFFFGGVVCCCSSSSASK
16#102# => "1111100110001000111001000000001011011000000000000000000",
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16#107# => "0011010111000000111001010011010000011001110010100000000",
16#181# => "0000001000001000100000011100000001111101100000000000000",
16#105# => "0100000100000000111001000000000111100100000000000000000",
16#1f3# => "0000001100000000100000011100000000111001100000000000000",
16#103# => "1111100000001000111001000000001011011000000000000000000",
16#1b6# => "1100010010001000011001000000000001000000000000000000000",
16#123# => "1101101011011000000100111100000001111101100001101010000",
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16#116# => "0001000111000000100100111001000000111001111001010000000",
16#10b# => "1000101110001000000000000000000001101000000000000000000",
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16#2ec# => "1010001010001000100010000000000100100100000000011010000",
16#2e8# => "0111011001111111011001100000101110110011000000010000000",
16#2e4# => "1111010001110110100000100100010101100001111000110001001",
16#2e0# => "1111001011101110001100111000000000111001100001010110000",
16#2ed# => "0111000100000000100000100011001100101101001000000000000",
16#2e2# => "1111001100000000101100111000000001111001100001011011000",
16#2ee# => "1010001100001000100010000000000100100100000000011010000",
16#2ef# => "1110110010000100000000100000000000100101010000101001000",
16#200# => "1111010001110110100100111100000000111101100000010000000",
16#128# => "0000001000001000010001110011001101110001001000000000000",
16#2e9# => "1001010111111111000110100000000100110011000011010000000",
16#12a# => "1010100110001100000100110011001100110001001000000100000",
16#129# => "0111011010000000110001100000000001101101000000000000000",
16#12b# => "0111011100000000110001100000000001101101000000000000000",
16#131# => "0001011010001000000000111000000000111001100001010000000",
16#134# => "0001011010001101000100100111001100101111001000000111000",
16#133# => "0001101001100000000000111000000000111001100001010000000",
16#12c# => "1001100011010000101100011100000001110100100000000110000",
16#117# => "1000101100000000100100111100000000111101100000010000000",
16#2e5# => "1000101110110000100010100100000100100101111000110001000",
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16#10a# => "1001111101011000010101110000000000110001111001000000000",
16#138# => "0000010010001000000000101100000001101101100010000000000",
16#12e# => "0001110100000100110101011100000001110001100000000000000",
16#141# => "1010010001101110100000011100000000100001100001101001000",
16#13f# => "0010000000000000110101110100000001110101111001100100000",
16#139# => "0001110000000000000100111100000000111101100000010000000",
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16#144# => "1010001000000000110101110100000001110101111001100100000",
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16#12f# => "0001110110001100100100011100000000110001100000000100000",
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16#2ea# => "1110110010001111011001100000110000110011000000010000000",
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16#9f7# => "1101110001011000100100000000000000011100000000000000000",
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16#9a6# => "0010101010000000100100000000100101000000000000001110010",
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16#9a3# => "0101001110000101100100000000000101011100000000001111010",
16#9a4# => "1001001000000000100100000011010001101100010000000000000",
16#9a2# => "0101001100000000000100000000000101011100000000001111010",
16#9b7# => "1001010010001000000100000011010100011100010000000100000",
16#9af# => "0000111010001000100100111011100000000001110000100010100",
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16#9b8# => "0101111010000011100001000000000001110000000001001010010",
16#9df# => "1101110000111000010000111011010001000001101000100000100",
16#9f4# => "0110111100001100100001110000000000110001100010001011010",
16#993# => "0111101010000000010000010000101000011000100011011111010",
16#9b1# => "1100100110001011100001110011001101110001101000001001010",
16#9b2# => "0101100110000000110000110000000000000001111001111101110",
16#9ba# => "0101111000001000000001110111000100000001101000101010110",
16#9f5# => "0111101010000000010000110011111100000001111001100110110",
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16#9c3# => "0010101010000011100100000000000001000000000000000000000",
16#9bf# => "1110000100001000100100000011100001000001101000101110010",
16#9be# => "1100100110000011100100000000100001000000000000001110010",
16#9c1# => "0101111100001101100100110111000100000001101000101111110",
16#9a1# => "1110000100000011100100000000101001000000000000001110010",
16#9e4# => "1010100010000000000100010000000000011000100000000000000",
16#9c0# => "1111001110000000000100000011011000011100010000000100000",
16#971# => "1001111110001000000100000000000100000000000000001111010",
16#93d# => "0011100000000000100100110000000000011001111000101101110",
16#9c7# => "1001111000000011100100000000110100000000000000001100010",
16#9c6# => "0110001010001000100100110111100001000001101000100000100",
16#990# => "0110001110001000000100000011010000011100010000001100010",
16#9c4# => "1100100100000101000100000000101101000000000000001110010",
16#9c2# => "0110001000000101100100110111000100000001111000100011100",
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16#954# => "0010101000000000000100000000000001000000000000000000000",
16#9ca# => "0010101110000011100100000000101101000000000000001110010",
16#9c5# => "0110010011010000000100000011100000000011010000100010000",
16#983# => "1111010000001000000100000011010000101100011000000110000",
16#9c8# => "0100000001010000100100000000110011000000000000001110010",
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16#9d3# => "0110010000001000100100010000010000011000100011011111010",
16#9cc# => "0110100010001101000100000000000001000000000000000000000",
16#9d4# => "1110011111010100100100110000000001110001100010010000000",
16#9ce# => "1110101100110000000100111011001000000001111000100011100",
16#91a# => "1110011000001000000100000000111000110000000001001110010",
16#9c9# => "1110110010000000000100111011000101000011101000100001100",
16#9d1# => "0110010010000000100100000000010011000000000000001110010",
16#9cf# => "0110100110000000100100010011011000011001110000111110010",
16#9cd# => "1110101100110000000100111011000101000011110000100010100",
16#9d0# => "1100100100000000100100000000010011000000000000001110010",
16#9f2# => "0110100100000000000100000000101101000000000000001110010",
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16#93f# => "0100101110001000011001110100111010011101100000001100000",
16#994# => "1001111000001000101000110011010001011001110000100000100",
16#98b# => "0100101010111000011001110000111101011101100000001101000",
16#0fd# => "1100010000001001001000100100000110011000000000001111010",
16#00c# => "1111111110000011111001010000110111011101100000001100010",
16#0b7# => "1000011010000000001000110111100001000001101000101101110",
16#00b# => "1101101000001000111001010111010010010101101000110000000",
16#0fc# => "1100010110001001001000100100000110011000000000000111000",
16#998# => "0100110000001000011001011100111101110101100000001101000",
16#99a# => "0100110011011101100000000000000001000000000000000000000",
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16#999# => "0100110110001000011001011100110110110001100000001011000",
16#9f1# => "1000000000000000000011010111010000010101101010100000000",
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16#a03# => "0000100110000000101000000000001000000000000000001111010",
16#a00# => "1000000110001000111001110000010110011101100000000000100",
16#a08# => "1000000000000011100100111011110010000001011010101110110",
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16#008# => "1110000000001000111001010111010010010101101000110000000",
16#a10# => "1000101100000011000100110000000001011101100000000100100",
16#a0b# => "0000100100000011100100011100000101000001100010001111010",
16#a02# => "0000010100001000100100000011100001000001101000100000000",
16#a01# => "1000000000001011100100111111010000011101100000001110110",
16#009# => "0000010110000000001010111011101011000001101000101101110",
16#a17# => "1111111111001001000100011000100111000000011000001110010",
16#a16# => "1000101100001000100100011111110001110101101010101001000",
16#a14# => "1000101011010000000100111011110101011011110000100010100",
16#a15# => "1000101100000000100100000000000000000010000000000000000",
16#9d9# => "1000000100001000000100000000000000110000000000001011000",
16#9db# => "1110110010000101000100111011001001011001101000100000100",
16#91b# => "1110110010001000100100111011000101000011101000100001100",
16#9d8# => "1001001011001101000100000011010001101100010000000000000",
16#970# => "1110110100000000000000110000000000000001111001111001000",
16#906# => "0011100010000000011001000000010111011000000000011011000",
16#926# => "1100001100000000111001000000101111000000000000000000000",
16#9d5# => "1001001000110000101000101100000001101101100000010000000",
16#925# => "1110101100000000110100101111100101110111010000000000000",
16#9e9# => "1100010000000000101000000011001000011000001000000000000",
16#9ef# => "1111010100000101110100000000100110011000000000011110010",
16#9eb# => "0111011110001000100100111111010000011101100000000000100",
16#9e3# => "1111010100001000101000101100000001101101100000010000000",
16#9ea# => "0111000000111000110100110000000000011101100000000000100",
16#927# => "1111010110001000000100000011010001101100011000000111000",
16#9f3# => "1001001110001000100100000000000001000000000000000000000",
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16#907# => "0011010001010000101000101100000001101101100000010000000",
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16#968# => "1011000100000000010100000000000001000000000000000011000",
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16#962# => "1011000100000000101000101111011100101101001000110000000",
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16#9ee# => "1111010110001000001000000011010001101100011010000000000",
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16#96a# => "1011101110001000000100110111010001000001110000100000100",
16#9da# => "0011010100001000011001011100011011110001100000000000000",
16#967# => "1110110000001000000000111111001000111001100000000000100",
16#966# => "0011001110001000100100111111000101111101100000000000100",
16#969# => "0011001110001000011001000000011101110100000000001100010",
16#92b# => "0000100010001000100100000000100111000000000000001110010",
16#928# => "1001010110001101100100000011100101011100010000000000000",
16#91f# => "1001010001010000000100000011001100011100010000000100000",
16#901# => "1010111100110000000100000011100000110100010000010000000",
16#950# => "1000000110000000100100000011100001000011110000000000000",
16#973# => "1010100000000000000100000000011001000000000000001110010",
16#92a# => "0011100100001000100100010000111100011000100000001110010",
16#959# => "1001010110001000000100000000010000000000000000001111010",
16#958# => "0010110100000000100100000000110001000000000000001110010",
16#082# => "0011100010001001000100100111010110011000010000001110010",
16#96e# => "1011011000001000100100101111010001101101101010010000000",
16#9d7# => "1011011010001011100100000011100000101100011000011000000",
16#96d# => "1110101100001000100100110111010001000001101000100000100",
16#977# => "1011011010000000100100001000000000011101100000000000100",
16#95c# => "1011101011000000100100000000110011000000000000001110010",
16#96c# => "1011011110000000100100101100000001110001100000000000000",
16#975# => "1011011100000101100100110111010001110101110000000000000",
16#a07# => "1000110000000000100100011100000001011101100000010000000",
16#a0e# => "0000010000000000100100000000101010110100000000001110010",
16#a0a# => "1000011011001101000100110100000000011111100000000111000",
16#974# => "0000010110001000001010101100101011101101100000010000000",
16#96f# => "1011101010000000010100111011010101000001101000101001100",
16#a19# => "1000011100000000000000000000000001000000000000000000000",
16#a05# => "1000110110000011100100110100000001110101100000010000000",
16#a18# => "0000001010110000100100111011010101000001101000100000100",
16#a09# => "1000110110000000000100011111001001011101101000001110010",
16#a0f# => "0000010110000000100100000000101010110100000000001110010",
16#a0d# => "1000011100000000000100011100000001011101100000010000000",
16#a1a# => "1000110000000000111001000000010111000000000000000000000",
16#a1b# => "1000110110001000001000101100000001101101100000010000000",
16#a06# => "1000110010001000100100110100000001011101110000000110000",
16#a0c# => "0000001010111000010100011100000001110101100000001000000",
16#a04# => "0010110100001100101010000000100111110100000000000001000",
16#95b# => "1000011000000001000100000000100111000000000000001110010",
16#9e7# => "1110110110000000000100000000000000011100000000000000000",
16#95a# => "1111001110001101100100101011010100000000101001111001000",
16#9e5# => "1100100000000000100100110000010000101101100000001110010",
16#9e6# => "1111001001011000100100000000000000000000000000001000000",
16#9e2# => "1100100110000000100100000000101101000000000000001110010",
16#95e# => "1010111100001000000100000000000000000010000000000000000",
16#97c# => "1100111000000000000100000000000001000000000000000000000",
16#9e0# => "0011111100000000011001000000010111110000000000000000000",
16#98e# => "0111000110111000000100000011000100011000010000000000000",
16#95f# => "0100011010001101100100000000011011000000000000001110010",
16#95d# => "1010111000001011100100000000000001000000000000001110010",
16#98f# => "1111010000001000000100000011010001101100011000000111000",
-- Replace above this line
others => (others => '0')
);
end package;
package body CCROS is
impure function readCCROS return CCROS_Type is
variable fileCCROS : CCROS_Type := (others => (others => '0'));
variable Cline : line;
variable addr : natural;
variable CCROSaddr : CCROS_Address_Type;
file CCROS_lines : text open read_mode is "ccros20120318.txt";
function fmHex(c : in character) return integer is
begin
if (c>='0') and (c<='9') then return character'pos(c)-character'pos('0');
elsif (c>='A') and (c<='F') then return character'pos(c)-character'pos('A')+10;
elsif (c>='a') and (c<='f') then return character'pos(c)-character'pos('a')+10;
else
report "Invalid hex address:" & c severity note;
return 0;
end if;
end;
function fmBin(c : in character) return STD_LOGIC is
begin
if c='0' then return '0';
elsif c='1' then return '1';
elsif c='?' then return '0';
else
report "Invalid bit:" & c severity note;
return '0';
end if;
end;
-- parity() function returns 1 if the vector has even parity
function parity(v : STD_LOGIC_VECTOR) return STD_LOGIC is
variable p : STD_LOGIC;
begin
p := '1';
for i in v'range loop
p := p xor v(i);
end loop;
return p;
end;
function toString(v : STD_LOGIC_VECTOR) return string is
variable s : string(1 to 55);
begin
for i in v'range loop
if v(i)='1' then s(i+1):='1';
else s(i+1):='0'; end if;
end loop;
return s;
end;
variable char : character;
variable field : integer;
variable newC : CCROS_Word_Type;
variable version : string(1 to 3);
variable eol : boolean;
variable cstr3 : string(1 to 3);
variable cstr8 : string(1 to 8);
variable cstr55 : string(1 to 55);
begin
for i in 1 to 8192 loop
exit when endfile(CCROS_lines);
readline(CCROS_lines,Cline);
exit when endfile(CCROS_lines);
-- 1-3 = address (hex)
-- 5-6 = CN hex (ignore 2 lower bits)
-- 8-11 = CH
-- 13-16 = CL
-- 18-20 = CM
-- 22-23 = CU
-- 25-28 = CA
-- 30-31 = CB
-- 33-36 = CK
-- 38-41 = CD
-- 43-45 = CF
-- 47-48 = CG
-- 50-51 = CV
-- 53-55 = CC
-- 57-60 = CS
-- 62 = AA
-- 64 = AS
-- 66 = AK
-- 68 = PK
-- File layout:
-- #AAA CN CH CL CM CU CA CB CK CD CF CG CV CC CS AAASAKPK
read(Cline,char);
if char='#' then next; end if;
addr := fmHex(char);
cstr3(1) := char;
read(Cline,char); addr := addr*16+fmhex(char);
cstr3(2) := char;
read(Cline,char); addr := addr*16+fmhex(char);
cstr3(3) := char;
CCROSaddr := CCROS_Address_Type(addr);
-- report "Addr: " & cstr3 severity note;
-- PN (0) omitted for now
-- CN
-- read(Cline,char); -- 4
read(Cline,char); field := fmHex(char);
read(Cline,char); field := field*16+fmhex(char);
field := field / 4;
newC(1 to 6) := conv_std_logic_vector(field,6);
-- PS (7) and PA (8) omitted for now
-- CH
-- read(Cline,char);
read(Cline,char); newc( 9) := fmBin(char);
read(Cline,char); newc(10) := fmBin(char);
read(Cline,char); newc(11) := fmBin(char);
read(Cline,char); newc(12) := fmBin(char);
-- CL
-- read(Cline,char);
read(Cline,char); newc(13) := fmBin(char);
read(Cline,char); newc(14) := fmBin(char);
read(Cline,char); newc(15) := fmBin(char);
read(Cline,char); newc(16) := fmBin(char);
-- CM
-- read(Cline,char);
read(Cline,char); newc(17) := fmBin(char);
read(Cline,char); newc(18) := fmBin(char);
read(Cline,char); newc(19) := fmBin(char);
-- CU
-- read(Cline,char);
read(Cline,char); newc(20) := fmBin(char);
read(Cline,char); newc(21) := fmBin(char);
-- CA
-- read(Cline,char);
read(Cline,char); newc(22) := fmBin(char);
read(Cline,char); newc(23) := fmBin(char);
read(Cline,char); newc(24) := fmBin(char);
read(Cline,char); newc(25) := fmBin(char);
-- CB
-- read(Cline,char);
read(Cline,char); newc(26) := fmBin(char);
read(Cline,char); newc(27) := fmBin(char);
-- CK
-- read(Cline,char);
read(Cline,char); newc(28) := fmBin(char);
read(Cline,char); newc(29) := fmBin(char);
read(Cline,char); newc(30) := fmBin(char);
read(Cline,char); newc(31) := fmBin(char);
-- PK (32) and PC (33) omitted for now
-- CD
-- read(Cline,char);
read(Cline,char); newc(34) := fmBin(char);
read(Cline,char); newc(35) := fmBin(char);
read(Cline,char); newc(36) := fmBin(char);
read(Cline,char); newc(37) := fmBin(char);
-- CF
-- read(Cline,char);
read(Cline,char); newc(38) := fmBin(char);
read(Cline,char); newc(39) := fmBin(char);
read(Cline,char); newc(40) := fmBin(char);
-- CG
-- read(Cline,char);
read(Cline,char); newc(41) := fmBin(char);
read(Cline,char); newc(42) := fmBin(char);
-- CV
-- read(Cline,char);
read(Cline,char); newc(43) := fmBin(char);
read(Cline,char); newc(44) := fmBin(char);
-- CC
-- read(Cline,char);
read(Cline,char); newc(45) := fmBin(char);
read(Cline,char); newc(46) := fmBin(char);
read(Cline,char); newc(47) := fmBin(char);
-- CS
-- read(Cline,char);
read(Cline,char); newc(48) := fmBin(char);
read(Cline,char); newc(49) := fmBin(char);
read(Cline,char); newc(50) := fmBin(char);
read(Cline,char); newc(51) := fmBin(char);
-- AA
-- read(Cline,char);
read(Cline,char); newc(52) := fmBin(char);
-- AS
-- read(Cline,char);
read(Cline,char); newc(53) := fmBin(char);
-- AK
-- read(Cline,char);
read(Cline,char); newc(54) := fmBin(char);
-- PK
-- read(Cline,char);
read(Cline,char); newc(32) := fmBin(char);
-- Now fill in PN,PA,PS,PC
newc(0) := parity(newc(1 to 6)); -- PN = CN
newc(8) := parity(CONV_STD_LOGIC_VECTOR(CCROSAddr,13)); -- PA = ADDR
-- if (newc(13 to 16)="0010") then
-- newc(32) := parity(newc(22 to 25)); -- PK = CA
-- else
-- newc(32) := parity(newc(28 to 31)); -- PK = CK
-- end if;
newc(7) := parity(newc(8 to 32) & newc(52) & newc(54)); -- PS = PA CH CL CM CU CA CB CK PK AA AK
newc(33) := parity(newc(34 to 51) & newc(53)); -- PC = CD CF CG CV CC CS AS
-- Bodge to generate incorrect parity for some locations
if addr=unsigned'(x"BA0") then -- BA0 has parity change "7" = PS PA PC
-- newc(7) := not newc(7); -- Already doing PA so no need to flip PS
newc(8) := not newc(8); -- PA
newc(33) := not newc(33); -- PC
end if;
if addr=unsigned'(x"B60") then -- B60 has parity change "B" = PN PA PC
newc(0) := not newc(0); -- PN
newc(7) := not newc(7); -- Need to flip PS to keep it correct when PA is flipped
newc(8) := not newc(8); -- PA
newc(33) := not newc(33); -- PC
end if;
-- Skip over page/location
read(Cline,char);read(Cline,cstr8);
-- report "Loc: " & cstr8 severity note;
-- for i in newC'range loop
-- if newC(i)='1' then
-- report "1" severity note;
-- else
-- report "0" severity note;
-- end if;
-- end loop;
-- See if there is a version
read(Cline,char,eol);
read(Cline,version,eol);
if char='-' then
-- report "Version: "&version severity note;
else
version := " ";
end if;
-- Check for acceptable versions
-- 000/Blank = Basic
-- 004 = 64k
-- 005 = 224UCWs
-- 006 = Storage Protect
-- 007 = Decimal Option
-- 010 = 1050 Console
-- 014 = Selector Channel #1
-- 025 = 50Hz timer
-- A20 = 64k + Storage Protect
-- Omitted:
-- 015 = Selector Channel 2
-- 031 = ??
-- 906 = Storage Protect Diagnostic
-- 914 = Selector Channel Diagnostic
-- 994 = ??
-- 995 = Local Storage Dump
-- 996 = Storage Diagnostic
-- 997 = Mpx Diagnostic
if version=" " or version="000" or version="004" or version="005" or version="006" or
version="007" or version="010" or version="014" or version="025" or version="A20" then
if fileCCROS(CCROSaddr) = (newC'range => '0') then
fileCCROS(CCROSaddr) := newC;
else
report "Duplicate CCROS " & integer'image(CCROSAddr) & " Ver " & version severity note;
end if;
else
report "CCROS " & integer'image(CCROSAddr) & " Ver " & version & " skipped" severity note;
end if;
-- report "CCROS " & integer'image(CCROSAddr) & ": " & toString(newC);
end loop;
return fileCCROS;
end;
end package body; | gpl-3.0 | cf52bb9578ab948406547ed3cfdbbe34 | 0.847379 | 4.658916 | false | false | false | false |
thommyj/slotcar | de0/uart_halfduplex.vhd | 1 | 4,765 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity uart_halfduplex is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : out std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
rts : out std_logic
);
end entity uart_halfduplex;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of uart_halfduplex is
component txuart is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
busy : out std_logic
);
end component;
component rxuart is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : out std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in_ext : in std_logic
);
end component;
begin
inst_txuart : txuart
port map(
clk => clk,
rst => rst,
parallell_data_in => parallell_data_in,
parallell_data_in_valid => parallell_data_in_valid,
parallell_data_in_sent => parallell_data_in_sent,
uart_data_out => uart_data_out,
busy => rts
);
inst_rxuart : rxuart
port map(
clk => clk,
rst => rst,
parallell_data_out => parallell_data_out,
parallell_data_out_valid => parallell_data_out_valid,
uart_data_in_ext => uart_data_in
);
end architecture syn;
-- *** EOF ***
| mit | fe891888796a977eb887196efa6b47a8 | 0.504302 | 4.46161 | false | false | false | false |
LucasMahieu/TP_secu | code/edk_support/aes_ddr.vhd | 1 | 21,624 | ------------------------------------------------------------------------------
-- aes_ddr.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: aes_ddr.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Sep 29 13:35:32 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library aes_ddr_v1_00_a;
use aes_ddr_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity aes_ddr is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
aes_clk : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity aes_ddr;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of aes_ddr is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 14;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity aes_ddr_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
aes_clk => aes_clk,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| mit | e398dcf37d498848284a4b42ec6e3204 | 0.446402 | 4.485376 | false | false | false | false |
chastell/art-decomp | kiss/s832_jed.vhd | 1 | 30,735 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_jed is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_jed;
architecture behaviour of s832_jed is
constant s00000: std_logic_vector(4 downto 0) := "01010";
constant s10000: std_logic_vector(4 downto 0) := "10000";
constant s01110: std_logic_vector(4 downto 0) := "11100";
constant s10001: std_logic_vector(4 downto 0) := "00001";
constant s01111: std_logic_vector(4 downto 0) := "10111";
constant s00010: std_logic_vector(4 downto 0) := "01110";
constant s00001: std_logic_vector(4 downto 0) := "00010";
constant s00100: std_logic_vector(4 downto 0) := "00110";
constant s00011: std_logic_vector(4 downto 0) := "00100";
constant s00101: std_logic_vector(4 downto 0) := "10110";
constant s00110: std_logic_vector(4 downto 0) := "01100";
constant s11111: std_logic_vector(4 downto 0) := "01000";
constant s00111: std_logic_vector(4 downto 0) := "01111";
constant s10111: std_logic_vector(4 downto 0) := "01001";
constant s01011: std_logic_vector(4 downto 0) := "01011";
constant s01000: std_logic_vector(4 downto 0) := "00111";
constant s01100: std_logic_vector(4 downto 0) := "11110";
constant s01101: std_logic_vector(4 downto 0) := "11111";
constant s01001: std_logic_vector(4 downto 0) := "00011";
constant s01010: std_logic_vector(4 downto 0) := "10011";
constant s11000: std_logic_vector(4 downto 0) := "11011";
constant s11011: std_logic_vector(4 downto 0) := "11010";
constant s11001: std_logic_vector(4 downto 0) := "00000";
constant s11010: std_logic_vector(4 downto 0) := "11000";
constant s11100: std_logic_vector(4 downto 0) := "10010";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0001000000000010000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0001000000000010000";
elsif std_match(input, "-001------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-011------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000010000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000010001";
end if;
when s10000 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000001000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000000001000000000";
end if;
when s01111 =>
if std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000010000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000010000000010000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000010000000010000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000001000000000100";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000001000001000100";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000001000000000100";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000001000001000100";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000001000000000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000001000000000000";
end if;
when s00100 =>
if std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0-0001-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0--101-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0---11-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s00001 =>
if std_match(input, "------0--------0-1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------0--------000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------101") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------111") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10---------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-10--------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10--------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------110--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-110-------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------110-------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------111--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------1110-----010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1110-----110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----101--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0------11--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----1-----1------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----11---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----10---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1-----0------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----0----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----0----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0-----01---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---110") then next_state <= s01011; output <= "0000000100000000000";
end if;
when s11111 =>
if std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s00111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s01011 =>
if std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
end if;
when s01100 =>
if std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0000000010000100000";
elsif std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0000000010000100000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0000000000000101000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0000000000000101000";
end if;
when s01101 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0101000000000000010";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0101000000000000010";
elsif std_match(input, "-0---------------1") then next_state <= s00000; output <= "0100000000000000010";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0100000000000000010";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0100000000000000010";
elsif std_match(input, "-0-1-------------0") then next_state <= s00000; output <= "0100000000000000010";
end if;
when s01000 =>
if std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "0000000100100000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000100100000001";
end if;
when s01001 =>
if std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "1000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
end if;
when s01010 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s11000 =>
if std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
end if;
when s11001 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "1000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000100000000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11010 =>
if std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11011 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-0--------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----111") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1--0-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-0--1-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
end if;
when s11100 =>
if std_match(input, "----0------------1") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00011 =>
if std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000100000000000";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 7e70c3801ca933a0e16577537a601a88 | 0.582723 | 4.181633 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-07B_2.vhd | 1 | 5,714 | ---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-07B_2.vhd
-- Creation Date: 01/11/09
-- Description:
-- S Register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY SReg IS
port
(
SA : IN STD_LOGIC; -- 01C
CS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
CD : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
N_Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS0, CARRY_0, Z_BUS_HI_0, Z_BUS_LO_0 : IN STD_LOGIC; -- 06B
GT_CARRY_TO_S3 : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(0 to 7);
GT_Z_BUS_TO_S : OUT STD_LOGIC;
S_REG_RST : OUT STD_LOGIC;
CTRL_REG_RST : IN STD_LOGIC; -- 01C
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
STORE_S_REG_RST : IN STD_LOGIC; -- 03D
E_SW_SEL_S : IN STD_LOGIC; -- 04C
MACH_RST_2C : IN STD_LOGIC; -- 06B
T_REQUEST : IN STD_LOGIC; -- 10BC6
FB_K_T2_PULSE : OUT STD_LOGIC;
CS_DECODE_X001 : OUT STD_LOGIC; -- 03C
BASIC_CS_0 : OUT STD_LOGIC; -- 03C
P1, T1, T2, T3, T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END SReg;
ARCHITECTURE FMD OF SReg IS
signal SETS, RESETS : STD_LOGIC_VECTOR(0 to 7);
signal CS_X000,CS_X001,CS_X010,CS_X011,CS_X100,CS_X101,CS_X110,CS_X111,CS_X01X,CS_X0X1,CS_0XXX,CS_1XXX : STD_LOGIC;
signal CD_0110 : STD_LOGIC;
signal GT_CS_OPT_DECODER, GT_CS_BASIC_DECODER : STD_LOGIC;
signal BASIC_NOT_CS_0, sBASIC_CS_0 : STD_LOGIC;
signal sGT_Z_BUS_TO_S : STD_LOGIC;
signal sS_REG_RST : STD_LOGIC;
signal GT_CS_OPT_Set,GT_CS_OPT_Reset : STD_LOGIC;
signal S_REG_Set,S_REG_Reset : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-07B
CS_X000 <= '1' when CS(1 to 3)="000" else '0';
CS_X001 <= '1' when CS(1 to 3)="001" else '0';
CS_DECODE_X001 <= CS_X001;
CS_X010 <= '1' when CS(1 to 3)="010" else '0';
CS_X011 <= '1' when CS(1 to 3)="011" else '0';
CS_X100 <= '1' when CS(1 to 3)="100" else '0';
CS_X101 <= '1' when CS(1 to 3)="101" else '0';
CS_X110 <= '1' when CS(1 to 3)="110" else '0';
CS_X111 <= '1' when CS(1 to 3)="111" else '0';
CS_X01X <= '1' when CS(1 to 2)="01" else '0';
CS_X0X1 <= '1' when CS(1)='0' and CS(3)='1' else '0';
CS_0XXX <= '1' when CS(0)='0' else '0';
CS_1XXX <= '1' when CS(0)='1' else '0';
GT_CS_OPT_Set <= SA and P1;
GT_CS_OPT_Reset <= CTRL_REG_RST or T1;
GT_CS_OPT: FLE port map(GT_CS_OPT_Set, GT_CS_OPT_Reset, clk, GT_CS_OPT_DECODER); -- AB3E5
GT_CS_BASIC_DECODER <= not GT_CS_OPT_DECODER; -- AB3E5
BASIC_NOT_CS_0 <= GT_CS_BASIC_DECODER and CS_0XXX; -- AA3L5 Could be" GT_CS_BASIC_DECODER and not CS(0)"
sBASIC_CS_0 <= GT_CS_BASIC_DECODER and CS_1XXX; -- AA3L5 Could be "GT_CS_BASIC_DECODER and CS(0)"
BASIC_CS_0 <= sBASIC_CS_0;
FB_K_T2_PULSE <= sBASIC_CS_0 and T2 and CS_X110; -- AA3F7, AA3E3
CD_0110 <= '1' when CD="0110" else '0'; -- AA3B7, AA3J6
sGT_Z_BUS_TO_S <= (CD_0110 and T4) or (MAN_STOR_PWR and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
GT_Z_BUS_TO_S <= sGT_Z_BUS_TO_S;
sS_REG_RST <= (CD_0110 and T3) or (STORE_S_REG_RST and E_SW_SEL_S) or MACH_RST_2C; -- AA3J6
S_REG_RST <= sS_REG_RST;
SETS(0) <= CS_X111 and BASIC_NOT_CS_0; -- AA3G7
SETS(1) <= T_REQUEST and CS_X101 and BASIC_NOT_CS_0; -- AA3G7
SETS(2) <= CS_X001 and not Z_BUS0 and sBASIC_CS_0; -- AA3H7
SETS(3) <= GT_CARRY_TO_S3 and CARRY_0; -- AA3H7
SETS(4) <= BASIC_NOT_CS_0 and CS_X01X and Z_BUS_HI_0; -- AA3J7
SETS(5) <= BASIC_NOT_CS_0 and CS_X0X1 and Z_BUS_LO_0; -- AA3J7
SETS(6) <= CS_X011 and sBASIC_CS_0; -- AA3K7
SETS(7) <= CS_X101 and sBASIC_CS_0; -- AA3K7
RESETS(0) <= CS_X110 and BASIC_NOT_CS_0; -- AA3G7
RESETS(1) <= CS_X101 and not T_REQUEST and BASIC_NOT_CS_0; -- AA3G7
RESETS(2) <= CS_X000 and sBASIC_CS_0; -- AA3H7
RESETS(3) <= not CARRY_0 and GT_CARRY_TO_S3; -- AA3H7
RESETS(4) <= (BASIC_NOT_CS_0 and not Z_BUS_HI_0 and CS_X01X) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(5) <= (BASIC_NOT_CS_0 and not Z_BUS_LO_0 and CS_X0X1) or (BASIC_NOT_CS_0 and CS_X100); -- AA3J7
RESETS(6) <= sBASIC_CS_0 and CS_X010; -- AA3K7
RESETS(7) <= sBASIC_CS_0 and CS_X100; -- AA3K7
S_REG_Set <= mux(sGT_Z_BUS_TO_S,not N_Z_BUS) or mux(T4,SETS);
S_REG_Reset <= (S'range=>sS_REG_RST) or mux(T4,RESETS);
S_REG: FLVL port map(S_REG_Set, S_REG_Reset, S); -- AA3G7, AA3H7, AA3J7, AA3K7
END FMD;
| gpl-3.0 | eee745f834ed091de31721507f7d4226 | 0.612356 | 2.448158 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_UDC1.vhd | 1 | 40,366 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: fmd2030_udc1.vhd
-- Creation Date:
-- Description:
-- First section of the 360/30, corresponding to Unit Data & Control Diagram 1
-- in the MDM.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Minor changes, and add DEBUG facility
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
USE work.Gates_package.all;
USE work.Buses_package.all;
USE work.all;
entity UDC1 is
port(
-- Buses
SALS : OUT SALS_Bus;
CTRL : OUT CTRL_REG;
Z_BUS : IN STD_LOGIC_VECTOR(0 to 8);
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
B_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
M_ASSM_BUS,N_ASSM_BUS : OUT STD_LOGIC_VECTOR(0 to 8);
MN : IN STD_LOGIC_VECTOR(0 to 15);
MPX_BUS : IN STD_LOGIC_VECTOR(0 to 8);
R : IN STD_LOGIC_VECTOR(0 to 8);
S : IN STD_LOGIC_VECTOR(0 to 7);
-- Indicators
W_IND_P : OUT STD_LOGIC;
X_IND_P : OUT STD_LOGIC;
WX_IND : OUT STD_LOGIC_VECTOR(0 to 12);
IND_LOAD : OUT STD_LOGIC;
IND_SYST,IND_MAN,IND_WAIT,IND_TEST,IND_EX,IND_CY_MATCH,IND_ALLOW_WR : OUT STD_LOGIC;
IND_1050_INTRV,IND_1050_REQ,IND_MPX,IND_SEL_CHNL : OUT STD_LOGIC;
IND_MSDR : OUT STD_LOGIC_VECTOR(0 to 7);
IND_MSDR_P : OUT STD_LOGIC;
-- Hardware Switches
-- ABCD FGHJ
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
-- E
E_SW : IN E_SW_BUS_Type;
SW_START,SW_LOAD,SW_SET_IC,SW_STOP : IN STD_LOGIC;
SW_PWR_OFF,SW_LAMP_TEST : IN STD_LOGIC;
SW_CONS_INTRP,SW_INTRP_TIMER : STD_LOGIC;
SW_INH_CF_STOP,SW_PROC,SW_SCAN : IN STD_LOGIC;
SW_SINGLE_CYCLE,SW_INSTRUCTION_STEP,SW_RATE_SW_PROCESS : IN STD_LOGIC;
SW_DSPLY,SW_STORE,SW_SYS_RST : IN STD_LOGIC;
SW_CHK_RST,SW_ROAR_RST,SW_CHK_RESTART,SW_DIAGNOSTIC : IN STD_LOGIC;
SW_CHK_STOP,SW_CHK_SW_PROCESS,SW_CHK_SW_DISABLE,SW_ROAR_RESTT_STOR_BYPASS : IN STD_LOGIC;
SW_ROAR_RESTT,SW_ROAR_RESTT_WITHOUT_RST,SW_EARLY_ROAR_STOP,SW_ROAR_STOP : IN STD_LOGIC;
SW_ROAR_SYNC,SW_ADDR_COMP_PROC,SW_SAR_DLYD_STOP,SW_SAR_STOP,SW_SAR_RESTART : IN STD_LOGIC;
-- Other hard I/O
MPX_METERING_IN : IN STD_LOGIC;
METER_IN_SX1,METER_IN_SX2 : IN STD_LOGIC;
KEY_SW : IN STD_LOGIC;
TO_KEY_SW : OUT STD_LOGIC;
METERING_OUT : OUT STD_LOGIC;
N60_CY_TIMER_PULSE : IN STD_LOGIC;
-- Signals to UDC2,UDC3
CARRY_0 : IN STD_LOGIC;
COMPLEMENT : IN STD_LOGIC;
NTRUE : IN STD_LOGIC;
CLOCK_ON : IN STD_LOGIC;
N1050_INTRV_REQ : IN STD_LOGIC;
TT6_POS_ATTN : IN STD_LOGIC;
FT2_MPX_OPNL : IN STD_LOGIC;
EXT_TRAP_MASK_ON : IN STD_LOGIC;
GT_1050_TAGS : OUT STD_LOGIC;
GT_1050_BUS : OUT STD_LOGIC;
SYS_RST_PRIORITY_LCH : OUT STD_LOGIC;
STORE_R : OUT STD_LOGIC;
MACH_RST_3 : OUT STD_LOGIC;
FT0,FT1,FT2,FT3,FT5,FT6,FT7 : IN STD_LOGIC;
MANUAL_STORE : OUT STD_LOGIC;
CARRY_0_LCHD : IN STD_LOGIC;
CARRY_1_LCHD : IN STD_LOGIC;
RECYCLE_RST : OUT STD_LOGIC;
ALU_CHK : IN STD_LOGIC;
N_CTRL_LM : IN STD_LOGIC;
CTRL_N : IN STD_LOGIC;
N_CTRL_N : IN STD_LOGIC;
STORE_S_REG_RST : OUT STD_LOGIC;
MAIN_STORAGE_CP : OUT STD_LOGIC;
LOCAL_STORAGE_CP : OUT STD_LOGIC;
SET_IND_ROSAR : OUT STD_LOGIC;
N_STACK_MEM_SELECT : OUT STD_LOGIC;
STACK_RD_WR_CONTROL : OUT STD_LOGIC;
H_REG_5_PWR : OUT STD_LOGIC;
FORCE_M_REG_123 : OUT STD_LOGIC;
GT_T_TO_MN_REG : OUT STD_LOGIC;
GT_CK_TO_MN_REG : OUT STD_LOGIC;
WX_CHK : OUT STD_LOGIC;
SAL_PC : OUT STD_LOGIC;
R_REG_PC : OUT STD_LOGIC;
RST_LOAD : OUT STD_LOGIC;
N2ND_ERROR_STOP : OUT STD_LOGIC;
MEM_WRAP : OUT STD_LOGIC;
LOAD_IND : OUT STD_LOGIC;
DIAGNOSTIC_SW : OUT STD_LOGIC;
-- Signals from UDC2
PROT_LOC_CPU_OR_MPX : IN STD_LOGIC;
ODD : IN STD_LOGIC;
EARLY_M_REG_0 : IN STD_LOGIC;
XH,XXH,XL : IN STD_LOGIC;
SUPPR_A_REG_CHK : IN STD_LOGIC;
STATUS_IN_LCHD : IN STD_LOGIC;
M_REG_0 : IN STD_LOGIC;
MACH_RST_PROT : IN STD_LOGIC;
MACH_RST_MPX : IN STD_LOGIC;
MACH_RST_2A,MACH_RST_2B : IN STD_LOGIC;
GM_WM_DETECTED : IN STD_LOGIC; -- 06CE4 to 05AB5
FIRST_MACH_CHK_REQ : IN STD_LOGIC;
FIRST_MACH_CHK : IN STD_LOGIC;
DECIMAL : IN STD_LOGIC;
INTRODUCE_ALU_CHK : IN STD_LOGIC;
SERV_IN_LCHD, ADDR_IN_LCHD, OPNL_IN_LCHD : IN STD_LOGIC;
MPX_SHARE_REQ : IN STD_LOGIC;
MPX_INTERRUPT : IN STD_LOGIC;
CS_DECODE_X001 : IN STD_LOGIC;
CLOCK_OFF : IN STD_LOGIC;
CONNECT : IN STD_LOGIC;
P_8F_DETECTED : IN STD_LOGIC;
BASIC_CS0 : IN STD_LOGIC;
ANY_MACH_CHK : IN STD_LOGIC;
ALU_CHK_LCH : IN STD_LOGIC;
ALLOW_PROTECT : IN STD_LOGIC;
ALLOW_PC_SALS : IN STD_LOGIC;
Z0_BUS_0 : IN STD_LOGIC;
Z_0 : IN STD_LOGIC;
SELECT_CPU_BUMP : IN STD_LOGIC;
-- Signals to UDC2
GT_MAN_SET_MN : OUT STD_LOGIC;
MPX_ROS_LCH : OUT STD_LOGIC;
SET_FW : OUT STD_LOGIC;
MANUAL_DISPLAY : OUT STD_LOGIC;
CTRL_REG_RST : OUT STD_LOGIC;
CTRL_REG_CHK : OUT STD_LOGIC;
CPU_WRITE_IN_R_REG : OUT STD_LOGIC; -- to 07A
CK_SAL_P_BIT_TO_MPX : OUT STD_LOGIC;
CHANNEL_RD_CALL : OUT STD_LOGIC; -- to 07B
USE_R : OUT STD_LOGIC;
USE_BASIC_CA_DECODER : OUT STD_LOGIC; -- 02A
USE_ALT_CA_DECODER : OUT STD_LOGIC; -- 02B
SUPPR_MACH_CHK_TRAP : OUT STD_LOGIC; -- 03A
N1401_MODE : OUT STD_LOGIC; -- 05A
MEM_PROT_REQUEST : OUT STD_LOGIC; -- 03A
MAIN_STORAGE : OUT STD_LOGIC; -- 04D
MACH_RST_SW : OUT STD_LOGIC; -- 03D
MACH_RST_SET_LCH : OUT STD_LOGIC;
MACH_RST_SET_LCH_DLY : OUT STD_LOGIC; -- 04B
MACH_CHK_RST : OUT STD_LOGIC; -- 04A
MACH_CHK_PULSE : OUT STD_LOGIC; -- 03A
GT_LOCAL_STORAGE : OUT STD_LOGIC; -- 04D
GT_D_REG_TO_A_BUS : OUT STD_LOGIC; -- 05C
GT_CA_TO_W_REG : OUT STD_LOGIC; -- 02B
DATA_READY : OUT STD_LOGIC; -- 03A
CPU_SET_ALLOW_WR_LCH : OUT STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : OUT STD_LOGIC; -- 03A
ALLOW_WRITE : OUT STD_LOGIC; -- 03D
ALLOW_WRITE_DLYD : OUT STD_LOGIC; -- 03D
USE_MANUAL_DECODER : OUT STD_LOGIC;
GTD_CA_BITS : OUT STD_LOGIC_VECTOR(0 to 3);
USE_MAIN_MEMORY, USE_LOC_MAIN_MEM : OUT STD_LOGIC;
MAN_STOR_OR_DSPLY : OUT STD_LOGIC;
MACH_RST_6 : OUT STD_LOGIC;
GT_SWS_TO_WX_PWR : OUT STD_LOGIC;
CPU_RD_PWR : OUT STD_LOGIC;
READ_ECHO_1,READ_ECHO_2,WRITE_ECHO_1,WRITE_ECHO_2 : OUT STD_LOGIC;
-- Signals from UDC3
SX1_SHARE_CYCLE, SX2_SHARE_CYCLE : IN STD_LOGIC := '0';
SEL_WR_CALL, SEL_AUX_WR_CALL, SEL_AUX_RD_CALL : IN STD_LOGIC := '0';
SEL_T1, SEL_T4, SEL_CONV_OSC,SEL_BASIC_CLOCK_OFF : IN STD_LOGIC := '0';
SEL_SHARE_HOLD, SEL_SHARE_CYCLE, SEL_CHNL_DATA_XFER : IN STD_LOGIC := '0';
SEL_ROS_REQ, SEL_READ_CALL, SEL_RD_WR_CTRL, SEL_RD_CALL_TO_STP : IN STD_LOGIC := '0';
SEL_CC_ROS_REQ : IN STD_LOGIC := '0';
MAN_DSPLY_GUV_HUV : IN STD_LOGIC := '0';
HSMPX_TRAP : IN STD_LOGIC := '0';
SX1_INTERRUPT, SX2_INTERRUPT : IN STD_LOGIC := '0';
SX_1_GATE, SX_1_R_W_CTRL : IN STD_LOGIC := '0';
SX_2_GATE, SX_2_R_W_CTRL : IN STD_LOGIC := '0';
SX_2_BUMP_SW_GT : IN STD_LOGIC := '0';
-- Signals to UDC3
SEL_DATA_READY, SEL_CHNL_CPU_CLOCK_STOP, RST_SEL_CHNL_DIAG_LCHS : OUT STD_LOGIC;
LOAD_REQ_LCH : OUT STD_LOGIC;
USE_GR_OR_HR : OUT STD_LOGIC;
SX_CHAIN_PULSE_1 : OUT STD_LOGIC;
CLOCK_START_LCH : OUT STD_LOGIC;
CLOCK_OUT : OUT STD_LOGIC;
CHK_RST_SW : OUT STD_LOGIC;
STG_MEM_SEL : OUT STD_LOGIC; -- to 08D
-- Debug
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1,P4 : IN STD_LOGIC;
M_CONV_OSC,P_CONV_OSC,M_CONV_OSC_2 : IN STD_LOGIC;
CLOCK_START : OUT STD_LOGIC;
USE_MAN_DECODER_PWR : OUT STD_LOGIC;
CLK : IN STD_LOGIC -- 50MHz
);
end entity UDC1;
architecture FMD of UDC1 is
-- Timing
signal CROS_STROBE : STD_LOGIC;
signal CROS_GO_PULSE : STD_LOGIC;
-- Registers
signal WX : STD_LOGIC_VECTOR(0 to 12);
signal H : STD_LOGIC_VECTOR(0 to 8);
signal sH_REG_5_PWR : STD_LOGIC;
signal H_REG_6 : STD_LOGIC;
signal I : STD_LOGIC_VECTOR(0 to 8);
signal J : STD_LOGIC_VECTOR(0 to 8);
signal U : STD_LOGIC_VECTOR(0 to 8);
signal V : STD_LOGIC_VECTOR(0 to 8);
signal T : STD_LOGIC_VECTOR(0 to 8);
signal G : STD_LOGIC_VECTOR(0 to 8);
signal L : STD_LOGIC_VECTOR(0 to 8);
signal HU,HV,GU,GV : STD_LOGIC_VECTOR(0 to 8) := "000000000";
signal sCTRL : CTRL_REG;
-- Switch buses
signal FGHJ_SW_BUS,ABCD_SW_BUS : STD_LOGIC_VECTOR(0 to 15);
signal SW_ABP,SW_CDP,SW_FGP,SW_HJP : STD_LOGIC;
-- Other logic
signal ALLOW_MAN_OPERATION : STD_LOGIC;
signal sALLOW_WRITE : STD_LOGIC;
signal sALLOW_WRITE_DLYD : STD_LOGIC;
signal sANY_PRIORITY_LCH : STD_LOGIC;
signal ANY_PRIORITY_PULSE : STD_LOGIC;
signal ANY_PRIORITY_PULSE_2 : STD_LOGIC;
signal ANY_PRIORITY_PULSE_PWR : STD_LOGIC;
signal AUX_WRITE_CALL : STD_LOGIC;
signal A_BUS1,A_BUS2 : STD_LOGIC_VECTOR(0 to 8);
signal CD_REG_2 : STD_LOGIC;
signal CHK_OR_DIAG_STOP_SW : STD_LOGIC;
signal COMPUTE : STD_LOGIC;
signal sCPU_READ_PWR : STD_LOGIC;
signal CPU_WR_PWR : STD_LOGIC;
signal CU_DECODE_UCW : STD_LOGIC;
signal DATA_READY_1 : STD_LOGIC;
signal DATA_READY_2 : STD_LOGIC;
signal sDIAGNOSTIC_SW : STD_LOGIC;
signal EARLY_LOCAL_STG : STD_LOGIC;
signal EARLY_ROAR_STOP : STD_LOGIC;
signal END_OF_E_CY_LCH : STD_LOGIC;
signal EXTERNAL_INT : STD_LOGIC;
signal E_CY_STOP_SAMPLE : STD_LOGIC;
signal FORCE_DEAD_CY_LCH : STD_LOGIC;
signal FORCE_IJ_PULSE : STD_LOGIC;
signal FORCE_IJ_REQ : STD_LOGIC;
signal FORCE_IJ_REQ_LCH : STD_LOGIC;
signal sFORCE_M_REG_123 : STD_LOGIC;
signal sGTD_CA_BITS : STD_LOGIC_VECTOR(0 to 3);
signal FT_4_LD_IND : STD_LOGIC;
signal sGT_SWS_TO_WX_PWR : STD_LOGIC;
signal GT_BU_ROSAR_TO_WX_REG : STD_LOGIC;
signal sGT_CA_TO_W_REG : STD_LOGIC;
signal GT_CK_DECO : STD_LOGIC;
signal GT_FWX_TO_WX_REG,GT_GWX_TO_WX_REG : STD_LOGIC;
signal GT_J_REG_TO_A_BUS : STD_LOGIC;
signal GT_J_TO_N_REG,GT_V_TO_N_REG : STD_LOGIC;
signal GT_SW_TO_WX_LCH,GT_SWS_TO_WX_LCH : STD_LOGIC;
signal GT_SW_MACH_RST : STD_LOGIC;
signal GT_UV_TO_WX_REG : STD_LOGIC;
signal G_REG_1_OR_R_REG_3 : STD_LOGIC;
signal HARD_STOP_LCH : STD_LOGIC;
signal HZ_DEST_RST : STD_LOGIC;
signal INH_ROSAR_SET : STD_LOGIC;
signal INTERRUPT : STD_LOGIC;
signal I_WRAPPED_CPU : STD_LOGIC;
signal LAMP_TEST : STD_LOGIC;
signal sLOAD_IND : STD_LOGIC;
signal LOAD_KEY_SW,LOAD_KEY_INLK : STD_LOGIC;
signal sMACH_CHK_PULSE : STD_LOGIC;
signal sMACH_CHK_RST : STD_LOGIC;
signal MACH_RST_1,sMACH_RST_3,MACH_RST_4,MACH_RST_5,sMACH_RST_6 : STD_LOGIC;
signal MACH_RST_LCH : STD_LOGIC;
signal sMACH_RST_SET_LCH : STD_LOGIC;
signal sMACH_RST_SW : STD_LOGIC;
signal sMACH_RST_SET_LCH_DLY : STD_LOGIC;
signal MACH_START_RST : STD_LOGIC;
signal sMAIN_STORAGE : STD_LOGIC;
signal sMAIN_STORAGE_CP : STD_LOGIC;
signal MANUAL_OPERATION : STD_LOGIC;
signal MANUAL_READ_CALL : STD_LOGIC;
signal sMANUAL_STORE : STD_LOGIC;
signal MANUAL_STORE_PWR : STD_LOGIC;
signal sMAN_STOR_OR_DSPLY : STD_LOGIC;
signal MANUAL_WRITE_CALL : STD_LOGIC;
signal MATCH,MATCH_LCH : STD_LOGIC;
signal sSTG_MEM_SEL : STD_LOGIC;
signal MEM_WRAP_REQ : STD_LOGIC;
signal sN1401_MODE : STD_LOGIC;
signal N1BC_OR_R1 : STD_LOGIC;
signal POWER_OFF_SW : STD_LOGIC := '0';
signal POWER_ON_RESET : STD_LOGIC := '0';
signal PRIORITY_BUS : STD_LOGIC_VECTOR(0 to 7);
signal PRIORITY_BUS_P : STD_LOGIC;
signal READ_CALL : STD_LOGIC;
signal sREAD_ECHO_1,sREAD_ECHO_2 : STD_LOGIC;
signal sRECYCLE_RST : STD_LOGIC;
signal ROS_CTRL_PROC_SW : STD_LOGIC;
signal ROS_SCAN : STD_LOGIC;
signal DIAG_LATCH_RST : STD_LOGIC;
signal R_REG_VAL_DEC_DIG : STD_LOGIC;
signal sSALS : SALS_Bus;
signal SET_IC_ALLOWED : STD_LOGIC;
signal START_SW_RST : STD_LOGIC;
signal STOP_REQ : STD_LOGIC;
signal sSUPPR_MACH_CHK_TRAP : STD_LOGIC;
signal SYSTEM_RESET_SW : STD_LOGIC;
signal S_REG_1_DLYD : STD_LOGIC;
signal S_REG_1_OR_R_REG_2 : STD_LOGIC;
signal TIMER_UPDATE : STD_LOGIC;
signal TIMER_UPDATE_OR_EXT_INT : STD_LOGIC;
signal sUSE_ALT_CA_DECODER : STD_LOGIC;
signal USE_ALT_CU_DECODER : STD_LOGIC;
signal sUSE_BASIC_CA_DECODER : STD_LOGIC;
signal USE_CPU_DECODER : STD_LOGIC;
signal sUSE_MANUAL_DECODER : STD_LOGIC;
signal sUSE_R : STD_LOGIC;
signal sUSE_MAN_DECODER_PWR : STD_LOGIC;
signal U_WRAPPED_MPX : STD_LOGIC;
signal V67_00_OR_GM_WM : STD_LOGIC;
signal sWRITE_ECHO_1,sWRITE_ECHO_2 : STD_LOGIC;
signal X6,X7 : STD_LOGIC;
signal XOR_OR_OR : STD_LOGIC;
signal IJ_SEL, UV_SEL : STD_LOGIC;
begin
-- Microcode sequencer
wx_sect: entity WX_Regs (FMD) port map (
W_IND_P => W_IND_P,
X_IND_P => X_IND_P,
WX_IND => WX_IND,
WX => WX,
CROS_STROBE => CROS_STROBE,
CROS_GO_PULSE => CROS_GO_PULSE,
SALS => sSALS,
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
CLK => clk,
SWS_FGP => SW_FGP,
SWS_HJP => SW_HJP,
SWS_F3 => SW_F(3),
SWS_G => SW_G,
SWS_H => SW_H,
SWS_J => SW_J,
U_P => U(8),
V_P => V(8),
U3_7 => U(3 to 7),
V => V(0 to 7),
PRIORITY_BUS_P => PRIORITY_BUS_P,
PRIORITY_BUS => PRIORITY_BUS,
SX_CHAIN_PULSE => PRIORITY_BUS(4),
MPX_SHARE_PULSE => PRIORITY_BUS(3),
X6 => X6,
X7 => X7,
ANY_MACH_CHK => ANY_MACH_CHK,
CHK_OR_DIAG_STOP_SW => CHK_OR_DIAG_STOP_SW,
EARLY_ROAR_STOP => EARLY_ROAR_STOP,
MACH_START_RST => MACH_START_RST,
ALU_CHK => ALU_CHK,
ALU_CHK_LCH => ALU_CHK_LCH,
MACH_RST_SET_LCH => sMACH_RST_SET_LCH,
MACH_RST_SET_LCH_DLY => sMACH_RST_SET_LCH_DLY,
USE_ALT_CU_DECODER => USE_ALT_CU_DECODER,
USE_BASIC_CA_DECODER => sUSE_BASIC_CA_DECODER,
GT_UV_TO_WX_REG => GT_UV_TO_WX_REG,
GT_CA_TO_W_REG => sGT_CA_TO_W_REG,
GT_FWX_TO_WX_REG => GT_FWX_TO_WX_REG,
GT_GWX_TO_WX_REG => GT_GWX_TO_WX_REG,
GT_SWS_TO_WX_PWR => sGT_SWS_TO_WX_PWR,
GT_SWS_TO_WX_LCH => GT_SWS_TO_WX_LCH,
ANY_PRIORITY_PULSE => ANY_PRIORITY_PULSE,
ANY_PRIORITY_PULSE_PWR => ANY_PRIORITY_PULSE_PWR,
INH_ROSAR_SET => INH_ROSAR_SET,
CHK_SW_PROC_SW => SW_CHK_SW_PROCESS,
ROS_SCAN => ROS_SCAN,
MACH_RST_2A => MACH_RST_2A,
MACH_RST_4 => MACH_RST_4,
MACH_RST_5 => MACH_RST_5,
N1401_MODE => sN1401_MODE,
CARRY_0_LCHD => CARRY_0_LCHD,
HSMPX_TRAP => HSMPX_TRAP,
SEL_CC_ROS_REQ => SEL_CC_ROS_REQ,
ALLOW_PC_SALS => ALLOW_PC_SALS,
TEST_LAMP => LAMP_TEST,
-- Outputs
CTRL_REG_CHK => CTRL_REG_CHK,
WX_CHK => WX_CHK,
SAL_PC => SAL_PC,
SET_IND_ROSAR => SET_IND_ROSAR,
GT_BU_ROSAR_TO_WX_REG => GT_BU_ROSAR_TO_WX_REG,
SET_FW => SET_FW,
DEBUG => DEBUG
);
-- CCROS microcode storage
ccros_sect: entity CCROS (FMD) port map (
-- Inputs
WX => WX,
MACH_RST_SW => sMACH_RST_SW,
MANUAL_STORE => sMANUAL_STORE,
ANY_PRIORITY_LCH => sANY_PRIORITY_LCH,
COMPUTE => COMPUTE,
MACH_RST_MPX => MACH_RST_MPX,
CROS_STROBE => CROS_STROBE,
CROS_GO_PULSE => CROS_GO_PULSE,
-- Outputs
SALS => sSALS,
CTRL => sCTRL,
CTRL_REG_RST => CTRL_REG_RST,
CK_SAL_P_BIT_TO_MPX => CK_SAL_P_BIT_TO_MPX,
-- Clocks
T1 => T1,
P1 => P1,
Clk => Clk );
SALS <= sSALS;
CTRL <= sCTRL;
-- X6,X7 computation
x6x7_sect: entity X6X7 (FMD) port map (
SALS => sSALS,
DECIMAL => DECIMAL,
CONNECT => CONNECT,
N_CTRL_LM => N_CTRL_LM,
CTRL_N => CTRL_N,
R_REG_0_BIT => R(0),
V67_00_OR_GM_WM => V67_00_OR_GM_WM,
STATUS_IN_LCHD => STATUS_IN_LCHD,
OPNL_IN_LCHD => OPNL_IN_LCHD,
CARRY_0_LCHD => CARRY_0_LCHD,
S_REG_1_OR_R_REG_2 => S_REG_1_OR_R_REG_2,
S => S,
G => G(0 to 7),
TIMER_UPDATE => TIMER_UPDATE,
EXTERNAL_INT => EXTERNAL_INT,
MPX_INTERRUPT => MPX_INTERRUPT,
SX1_INTERRUPT => SX1_INTERRUPT,
SX2_INTERRUPT => SX2_INTERRUPT,
I_WRAPPED_CPU => I_WRAPPED_CPU,
TIMER_UPDATE_OR_EXT_INT => TIMER_UPDATE_OR_EXT_INT,
U_WRAPPED_MPX => U_WRAPPED_MPX,
H_REG_6_BIT => H_REG_6,
ADDR_IN_LCHD => ADDR_IN_LCHD,
SERV_IN_LCHD => SERV_IN_LCHD,
R_REG_VAL_DEC_DIG => R_REG_VAL_DEC_DIG,
N1BC_OR_R1 => N1BC_OR_R1,
Z_BUS_0 => Z0_BUS_0, -- Different to MDM - see 06AE3
G_REG_1_OR_R_REG_3 => G_REG_1_OR_R_REG_3,
GT_BU_ROSAR_TO_WX_REG => GT_BU_ROSAR_TO_WX_REG,
H_REG_5_PWR => sH_REG_5_PWR,
MPX_SHARE_PULSE => PRIORITY_BUS(3),
SX_CHAIN_PULSE => PRIORITY_BUS(4),
MACH_RST_SW => sMACH_RST_SW,
R_REG_4_BIT => R(4),
ANY_PRIORITY_PULSE => ANY_PRIORITY_PULSE,
-- Outputs
XOR_OR_OR => XOR_OR_OR,
INTERRUPT => INTERRUPT,
GT_GWX_TO_WX_REG => GT_GWX_TO_WX_REG,
GT_FWX_TO_WX_REG => GT_FWX_TO_WX_REG,
MPX_ROS_LCH => MPX_ROS_LCH,
X6 => X6,
X7 => X7,
USE_ALT_CA_DECODER => sUSE_ALT_CA_DECODER,
USE_CA_BASIC_DECODER => sUSE_BASIC_CA_DECODER,
GT_CA_TO_W_REG => sGT_CA_TO_W_REG,
GT_UV_TO_WX_REG => GT_UV_TO_WX_REG,
DIAG_LATCH_RST => DIAG_LATCH_RST,
-- Debug
DEBUG => open,
-- Clocks
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
CLK => CLK );
USE_BASIC_CA_DECODER <= sUSE_BASIC_CA_DECODER;
USE_ALT_CA_DECODER <= sUSE_ALT_CA_DECODER;
GT_CA_TO_W_REG <= sGT_CA_TO_W_REG;
-- Priority control (microcode interrupts)
priority_sect: entity Priority (FMD) port map (
-- Inputs
RECYCLE_RST => sRECYCLE_RST,
S_REG_1_BIT => S(1),
SALS_CDREG => sCTRL.CTRL_CD,
MACH_RST_SW => sMACH_RST_SW,
DATA_READY_1 => DATA_READY_1,
DATA_READY_2 => DATA_READY_2,
MEM_WRAP_REQ => MEM_WRAP_REQ,
ALLOW_PROTECT => ALLOW_PROTECT,
PROT_LOC_CPU_OR_MPX => PROT_LOC_CPU_OR_MPX,
READ_CALL => READ_CALL,
XOR_OR_OR => XOR_OR_OR,
CTRL_N => CTRL_N,
STOP_REQ => STOP_REQ,
SUPPR_A_REG_CHK => SUPPR_A_REG_CHK,
H_REG_5_PWR => sH_REG_5_PWR,
SEL_ROS_REQ => SEL_ROS_REQ,
FT_3_MPX_SHARE_REQ => FT3,
H_REG_6 => H_REG_6,
P_8F_DETECTED => P_8F_DETECTED,
LOAD_IND => sLOAD_IND,
FORCE_IJ_REQ => FORCE_IJ_REQ,
FIRST_MACH_CHK_REQ => FIRST_MACH_CHK_REQ,
MACH_RST_6 => sMACH_RST_6,
ALLOW_WRITE => sALLOW_WRITE_DLYD,
GT_SWS_TO_WX_PWR => sGT_SWS_TO_WX_PWR,
DIAGNOSTIC_SW => sDIAGNOSTIC_SW,
MACH_RST_LCH => MACH_RST_LCH,
HARD_STOP_LCH => HARD_STOP_LCH,
R_REG_5 => R(5),
H => H(0 to 7),
FORCE_DEAD_CY_LCH => FORCE_DEAD_CY_LCH,
-- Outputs
SUPPR_MACH_CHK_TRAP => sSUPPR_MACH_CHK_TRAP,
ANY_PRIORITY_PULSE_2 => ANY_PRIORITY_PULSE_2,
ANY_PRIORITY_LCH => sANY_PRIORITY_LCH,
S_REG_1_DLYD => S_REG_1_DLYD,
GT_SW_TO_WX_LCH => GT_SW_TO_WX_LCH, -- to 04A
DATA_READY => DATA_READY,
MEM_PROTECT_REQ => MEM_PROT_REQUEST,
HZ_DEST_RST => HZ_DEST_RST,
GT_SW_MACH_RST => GT_SW_MACH_RST,
GT_SWS_TO_WX_LCH => GT_SWS_TO_WX_LCH, -- to 01B
FORCE_IJ_REQ_LCH => FORCE_IJ_REQ_LCH,
SYS_RST_PRIORITY_LCH => SYS_RST_PRIORITY_LCH,
MACH_CHK_PULSE => sMACH_CHK_PULSE,
FORCE_IJ_PULSE => FORCE_IJ_PULSE,
SX_CHAIN_PULSE_1 => SX_CHAIN_PULSE_1,
ANY_PRIORITY_PULSE => ANY_PRIORITY_PULSE,
ANY_PRIORITY_PULSE_PWR => ANY_PRIORITY_PULSE_PWR,
PRIORITY_BUS => PRIORITY_BUS,
PRIORITY_BUS_P => PRIORITY_BUS_P,
-- Clocks
T1 => T1,
T3 => T3,
T4 => T4,
P4 => P4,
CLK => CLK
);
ANY_PRIORITY_LCH <= sANY_PRIORITY_LCH;
SUPPR_MACH_CHK_TRAP <= sSUPPR_MACH_CHK_TRAP;
MACH_CHK_PULSE <= sMACH_CHK_PULSE;
wrap_sect: entity StorageWrap port map (
-- Inputs
SALS => sSALS,
CTRL => sCTRL,
ANY_PRIORITY_PULSE_2 => ANY_PRIORITY_PULSE_2,
H_REG_5_PWR => sH_REG_5_PWR,
H_REG_6 => H_REG_6,
NTRUE => NTRUE,
CARRY_0 => CARRY_0,
COMPLEMENT => COMPLEMENT,
GT_J_TO_N_REG => GT_J_TO_N_REG,
GT_V_TO_N_REG => GT_V_TO_N_REG,
M012 => MN(0 to 2),
RECYCLE_RST => sRECYCLE_RST,
ALLOW_WRITE => sALLOW_WRITE,
READ_CALL => READ_CALL,
MAIN_STORAGE => sMAIN_STORAGE,
DATA_READY_1 => DATA_READY_1,
DATA_READY_2 => DATA_READY_2,
-- Outputs
GT_CK_DECO => GT_CK_DECO,
SEL_DATA_READY => SEL_DATA_READY,
MEM_WRAP_REQ => MEM_WRAP_REQ,
MEM_WRAP => MEM_WRAP,
I_WRAPPED_CPU => I_WRAPPED_CPU,
U_WRAPPED_MPX => U_WRAPPED_MPX,
-- Clocks
T1 => T1,
T2 => T2,
T4 => T4,
P1 => P1,
CLK => CLK
);
css_sect: entity ClockStartStop port map (
-- Switches
SW_START => SW_START,
SW_LOAD => SW_LOAD,
SW_SET_IC => SW_SET_IC,
SW_STOP => SW_STOP,
SW_INH_CF_STOP => SW_INH_CF_STOP,
SW_PROC => SW_PROC,
SW_SCAN => SW_SCAN,
SW_SINGLE_CYCLE => SW_SINGLE_CYCLE,
SW_INSTRUCTION_STEP => SW_INSTRUCTION_STEP,
SW_RATE_SW_PROCESS => SW_RATE_SW_PROCESS,
SW_PWR_OFF => SW_PWR_OFF,
-- Other inputs
ALLOW_MAN_OPER => ALLOW_MAN_OPERATION,
FT3_MPX_SHARE_REQ => FT3,
M_CONV_OSC => M_CONV_OSC,
SEL_ROS_REQ => SEL_ROS_REQ,
MACH_RST_3 => sMACH_RST_3,
CLOCK_ON => CLOCK_ON,
SAR_DLYD_STOP_SW => SW_SAR_DLYD_STOP,
MATCH => MATCH,
SALS => sSALS,
FORCE_IJ_REQ => FORCE_IJ_REQ,
MACH_START_RST => MACH_START_RST,
MACH_RST_SW => sMACH_RST_SW,
USE_BASIC_CA_DECO => sUSE_BASIC_CA_DECODER,
S_REG_1_DLYD => S_REG_1_DLYD,
INTERRUPT => INTERRUPT,
END_OF_E_CY_LCH => END_OF_E_CY_LCH,
ANY_PRIORITY_PULSE => ANY_PRIORITY_PULSE,
FORCE_IJ_REQ_LCH => FORCE_IJ_REQ_LCH,
P_CONV_OSC => P_CONV_OSC,
MAN_OPERATION => MANUAL_OPERATION,
ALLOW_WRITE => sALLOW_WRITE_DLYD,
MACH_CHK_PULSE => sMACH_CHK_PULSE,
MACH_CHK_RST => sMACH_CHK_RST,
HZ_DEST_RST => HZ_DEST_RST,
FIRST_MACH_CHK => FIRST_MACH_CHK,
CHK_OR_DIAG_STOP_SW => CHK_OR_DIAG_STOP_SW,
ANY_MACH_CHK => ANY_MACH_CHK,
MATCH_LCH => MATCH_LCH,
EARLY_ROAR_STOP_SW => SW_EARLY_ROAR_STOP,
ALU_CHK => ALU_CHK,
DIAGNOSTIC_SW => sDIAGNOSTIC_SW,
CS_DECODE_X001 => CS_DECODE_X001,
BASIC_CS0 => BASIC_CS0,
SUPPR_MACH_CHK_TRAP => sSUPPR_MACH_CHK_TRAP,
Z_BUS_0 => Z_0, -- Not quite sure which signal this needs to be
SAR_STOP_SW => SW_SAR_STOP,
ROAR_STOP_SW => SW_ROAR_STOP,
ANY_PRIORITY_PULSE_PWR => ANY_PRIORITY_PULSE_PWR,
GT_CK_DECODE => GT_CK_DECO,
SX1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX2_SHARE_CYCLE => SX2_SHARE_CYCLE,
SEL_T4 => SEL_T4,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
SEL_CONV_OSC => SEL_CONV_OSC,
SEL_BASIC_CLOCK_OFF => SEL_BASIC_CLOCK_OFF,
GT_J_REG_TO_A_BUS => GT_J_REG_TO_A_BUS,
M_CONV_OSC_2 => M_CONV_OSC_2,
MPX_SHARE_REQ => MPX_SHARE_REQ,
SYSTEM_RESET_SW => SYSTEM_RESET_SW,
-- Outputs
START_SW_RST => START_SW_RST,
E_CY_STOP_SAMPLE => E_CY_STOP_SAMPLE,
LOAD_KEY_SW => LOAD_KEY_SW,
LOAD_KEY_INLK => LOAD_KEY_INLK,
SET_IC_ALLOWED => SET_IC_ALLOWED,
INH_ROSAR_SET => INH_ROSAR_SET,
STOP_REQ => STOP_REQ,
ROS_SCAN => ROS_SCAN,
ROS_CTRL_PROC_SW => ROS_CTRL_PROC_SW,
FT_4_LD_IND => FT_4_LD_IND,
LOAD_REQ_LCH => LOAD_REQ_LCH,
LOAD_IND => sLOAD_IND,
RST_SEL_CHNL_DIAG_LCHS => RST_SEL_CHNL_DIAG_LCHS,
RST_LOAD => RST_LOAD,
CLOCK_START_LCH => CLOCK_START_LCH,
PWR_OFF_SW => POWER_OFF_SW,
N2ND_ERROR_STOP => N2ND_ERROR_STOP,
SEL_CHNL_CPU_CLOCK_STOP => SEL_CHNL_CPU_CLOCK_STOP,
CLOCK_START => CLOCK_START,
EARLY_ROAR_STOP => EARLY_ROAR_STOP,
HARD_STOP_LCH => HARD_STOP_LCH,
DEBUG => open,
-- Clocks
T2 => T2,
T3 => T3,
T4 => T4,
P1 => P1,
clk => clk
);
LOAD_IND <= sLOAD_IND;
manctrl : entity ManualControls port map (
E_SW_SEL_MAIN_STG => E_SW.MS_SEL,
E_SW_SEL_AUX_STG => E_SW.LS_SEL,
E_CY_STOP_SMPL => E_CY_STOP_SAMPLE,
SEL_CHNL_DATA_XFER => SEL_CHNL_DATA_XFER,
POWER_ON_RESET => POWER_ON_RESET,
LOAD_KEY_SW => LOAD_KEY_SW,
CLOCK_OFF => CLOCK_OFF,
CLOCK_ON => CLOCK_ON,
WRITE_ECHO_1 => sWRITE_ECHO_1,
WRITE_ECHO_2 => sWRITE_ECHO_2,
READ_ECHO_1 => sREAD_ECHO_1,
READ_ECHO_2 => sREAD_ECHO_2,
CPU_READ_PWR => sCPU_READ_PWR,
SEL_AUX_RD_CALL => SEL_AUX_RD_CALL,
SEL_WR_CALL => SEL_WR_CALL,
ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
RECYCLE_RST => sRECYCLE_RST,
MAN_DSPLY_GUV_HUV => MAN_DSPLY_GUV_HUV,
CPU_WR_PWR => CPU_WR_PWR,
LOAD_KEY_INLK => LOAD_KEY_INLK,
POWER_OFF_SW => POWER_OFF_SW,
IJ_SEL_SW => IJ_SEL,
UV_SEL_SW => UV_SEL,
SEL_AUX_WR_CALL => SEL_AUX_WR_CALL,
USE_R => sUSE_R,
SEL_T1 => SEL_T1,
CU_SALS => sSALS.SALS_CU,
-- Switches
SW_DSPLY => SW_DSPLY,
SW_STORE => SW_STORE,
SW_SYS_RST => SW_SYS_RST,
-- Outputs
MACH_RST_SW => sMACH_RST_SW,
MACH_RST_1 => MACH_RST_1,
MACH_RST_3 => sMACH_RST_3,
MACH_RST_4 => MACH_RST_4,
MACH_RST_5 => MACH_RST_5,
MACH_RST_6 => sMACH_RST_6,
SYSTEM_RST_SW => SYSTEM_RESET_SW,
STG_MEM_SEL => sSTG_MEM_SEL,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
USE_MANUAL_DECODER => sUSE_MANUAL_DECODER,
ALLOW_MAN_OPERATION => ALLOW_MAN_OPERATION,
MANUAL_DISPLAY => MANUAL_DISPLAY,
MAN_STOR_OR_DSPLY => sMAN_STOR_OR_DSPLY,
MAN_STORE => sMANUAL_STORE,
MAN_STORE_PWR => MANUAL_STORE_PWR,
STORE_S_REG_RST => STORE_S_REG_RST,
CPU_SET_ALLOW_WR_LCH => CPU_SET_ALLOW_WR_LCH,
MAN_RD_CALL => MANUAL_READ_CALL,
GT_MAN_SET_MN => GT_MAN_SET_MN,
AUX_WRITE_CALL => AUX_WRITE_CALL,
ALLOW_WRITE => sALLOW_WRITE,
ALLOW_WR_DLYD => sALLOW_WRITE_DLYD,
MANUAL_OPERATION => MANUAL_OPERATION,
MAN_WRITE_CALL => MANUAL_WRITE_CALL,
STORE_R => STORE_R,
-- Clocks
CONV_OSC => P_CONV_OSC,
T1 => T1,T2 => T2,
Clk => CLK
);
USE_MAN_DECODER_PWR <= sUSE_MAN_DECODER_PWR;
USE_MANUAL_DECODER <= sUSE_MANUAL_DECODER;
MANUAL_STORE <= sMANUAL_STORE;
MACH_RST_SW <= sMACH_RST_SW;
ALLOW_WRITE <= sALLOW_WRITE;
ALLOW_WRITE_DLYD <= sALLOW_WRITE_DLYD;
STG_MEM_SEL <= sSTG_MEM_SEL;
MAN_STOR_OR_DSPLY <= sMAN_STOR_OR_DSPLY;
MACH_RST_6 <= sMACH_RST_6;
MACH_RST_3 <= sMACH_RST_3;
recycsect: entity RecycleCtrlsMatch port map (
-- Inputs
N_CTRL_N => N_CTRL_N,
XOR_OR_OR => XOR_OR_OR,
S_REG_7_BIT => S(7),
CLOCK_ON => CLOCK_ON,
CLOCK_OFF => CLOCK_OFF,
MAN_STOR_OR_DSPLY => sMAN_STOR_OR_DSPLY,
HARD_STOP_LCH => HARD_STOP_LCH,
MPX_METERING_IN => MPX_METERING_IN,
METER_IN_SX1 => METER_IN_SX1,
METER_IN_SX2 => METER_IN_SX2,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
KEY_SW => KEY_SW,
MACH_RST_SW => sMACH_RST_SW,
LOAD_KEY_SW => LOAD_KEY_SW,
SYSTEM_RESET_SW => SYSTEM_RESET_SW,
CL_SALS => sSALS.SALS_CL,
INH_ROSAR_SET => INH_ROSAR_SET,
ALLOW_WRITE => sALLOW_WRITE,
ALLOW_WRITE_DLYD => sALLOW_WRITE_DLYD,
SET_IC_LCH => SET_IC_ALLOWED,
MACH_RST_3 => sMACH_RST_3,
FORCE_IJ_PULSE => FORCE_IJ_PULSE,
FORCE_IJ_REQ_LCH => FORCE_IJ_REQ_LCH,
START_SW_RST => START_SW_RST,
MACH_RST_6 => sMACH_RST_6,
ANY_MACH_CHK => ANY_MACH_CHK,
ANY_PRIORITY_LCH => sANY_PRIORITY_LCH,
SUPPR_MACH_CHK_TRAP => sSUPPR_MACH_CHK_TRAP,
ALLOW_MAN_OPERATION => ALLOW_MAN_OPERATION,
N1050_INTRV_REQ => N1050_INTRV_REQ,
TT6_POS_ATTN => TT6_POS_ATTN,
FT2_MPX_OPNL => FT2_MPX_OPNL,
H_REG_5_PWR => sH_REG_5_PWR,
ROS_CTRL_PROC_SW => ROS_CTRL_PROC_SW,
RATE_SW_PROC_SW => SW_RATE_SW_PROCESS,
ODD => ODD,
INTRODUCE_ALU_CHK => INTRODUCE_ALU_CHK,
GT_SW_TO_WX_LCH => GT_SW_TO_WX_LCH,
HZ_DEST_RST => HZ_DEST_RST,
MAIN_STORAGE => sMAIN_STORAGE,
WX_REG_BUS => WX,
ABCD_SW_BUS => ABCD_SW_BUS,
MN_REGS_BUS => MN,
AUX_WRITE_CALL => AUX_WRITE_CALL,
LOAD_IND => sLOAD_IND,
DIAG_LATCH_RST => DIAG_LATCH_RST,
-- Switches
SW_LAMP_TEST => SW_LAMP_TEST,
SW_CHK_RST => SW_CHK_RST,
SW_ROAR_RST => SW_ROAR_RST,
SW_CHK_RESTART => SW_CHK_RESTART,
SW_DIAGNOSTIC => SW_DIAGNOSTIC,
SW_CHK_STOP => SW_CHK_STOP,
SW_CHK_SW_PROCESS => SW_CHK_SW_PROCESS,
SW_CHK_SW_DISABLE => SW_CHK_SW_DISABLE,
SW_ROAR_RESTT_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SW_ROAR_RESTT => SW_ROAR_RESTT,
SW_ROAR_RESTT_WITHOUT_RST => SW_ROAR_RESTT_WITHOUT_RST,
SW_EARLY_ROAR_STOP => SW_EARLY_ROAR_STOP,
SW_ROAR_STOP => SW_ROAR_STOP,
SW_ROAR_SYNC => SW_ROAR_SYNC,
SW_ADDR_COMP_PROC => SW_ADDR_COMP_PROC,
SW_SAR_DLYD_STOP => SW_SAR_DLYD_STOP,
SW_SAR_STOP => SW_SAR_STOP,
SW_SAR_RESTART => SW_SAR_RESTART,
-- Outputs
LAMP_TEST => LAMP_TEST,
CLOCK_OUT => CLOCK_OUT,
TO_KEY_SW => TO_KEY_SW,
METERING_OUT => METERING_OUT,
MACH_RST_SET_LCH => sMACH_RST_SET_LCH,
MACH_RST_SET_LCH_DLYD => sMACH_RST_SET_LCH_DLY,
FORCE_DEAD_CY_LCH => FORCE_DEAD_CY_LCH,
END_OF_E_CY_LCH => END_OF_E_CY_LCH,
FORCE_IJ_REQ => FORCE_IJ_REQ,
MACH_START_RST => MACH_START_RST,
DIAGNOSTIC_SW => sDIAGNOSTIC_SW,
CHK_OR_DIAG_STOP_SW => CHK_OR_DIAG_STOP_SW,
RECYCLE_RST => sRECYCLE_RST,
MACH_CHK_RST => sMACH_CHK_RST,
CHK_RST_SW => CHK_RST_SW,
MACH_RST_LCH => MACH_RST_LCH,
GT_SWS_TO_WX_PWR => sGT_SWS_TO_WX_PWR,
MATCH_LCH => MATCH_LCH,
MATCH => MATCH,
-- Indicators
IND_SYST => IND_SYST,
IND_MAN => IND_MAN,
IND_WAIT => IND_WAIT,
IND_TEST => IND_TEST,
IND_LOAD => IND_LOAD,
IND_EX => IND_EX,
IND_CY_MATCH => IND_CY_MATCH,
IND_ALLOW_WR => IND_ALLOW_WR,
IND_1050_INTRV => IND_1050_INTRV,
IND_1050_REQ => IND_1050_REQ,
IND_MPX => IND_MPX,
IND_SEL_CHNL => IND_SEL_CHNL,
-- Clocks
T1 => T1,T2 => T2,T3 => T3,T4 => T4,
Clk => CLK
);
RECYCLE_RST <= sRECYCLE_RST;
MACH_RST_SET_LCH <= sMACH_RST_SET_LCH;
MACH_RST_SET_LCH_DLY <= sMACH_RST_SET_LCH_DLY;
MACH_CHK_RST <= sMACH_CHK_RST;
GT_SWS_TO_WX_PWR <= sGT_SWS_TO_WX_PWR;
DIAGNOSTIC_SW <= sDIAGNOSTIC_SW;
manual: entity ManualDataCFH port map
(
-- Inputs
MACH_RST_PROT => MACH_RST_PROT,
USE_MAN_DECO_PWR => sUSE_MAN_DECODER_PWR,
N60_CY_TIMER_PULSE => N60_CY_TIMER_PULSE,
L_REGISTER => L(0 to 7),
MACH_RST_SW => sMACH_RST_SW,
EXT_TRAP_MASK_ON => EXT_TRAP_MASK_ON,
USE_MAN_DECODER => sUSE_MANUAL_DECODER,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
USE_ALT_CA_DECODER => sUSE_ALT_CA_DECODER,
USE_BASIC_CA_DECODER => sUSE_BASIC_CA_DECODER,
GTD_CA_BITS => sGTD_CA_BITS,
CK_SALS => sSALS.SALS_CK,
GT_CK_DECO => GT_CK_DECO,
Z_BUS => Z_BUS(0 to 7),
Z_BUS_P => Z_BUS(8),
MAN_STOR_PWR => MANUAL_STORE_PWR,
CD_CTRL_REG => sCTRL.CTRL_CD,
RECYCLE_RST => sRECYCLE_RST,
MACH_RST_2B => MACH_RST_2B,
-- Switches
SW_INTRP_TIMER => SW_INTRP_TIMER,
SW_CONS_INTRP => SW_CONS_INTRP,
SW_A => SW_A,SW_B => SW_B,SW_C => SW_C,SW_D => SW_D,
SW_F => SW_F,SW_G => SW_G,SW_H => SW_H,SW_J => SW_J,
SW_AP => SW_AP,SW_BP => SW_BP,SW_CP => SW_CP,SW_DP => SW_DP,
SW_FP => SW_FP,SW_GP => SW_GP,SW_HP => SW_HP,SW_JP => SW_JP,
IJ_SEL => IJ_SEL, UV_SEL => UV_SEL,
-- Outputs
ABCD_SW_BUS => ABCD_SW_BUS,
FGHJ_SW_BUS => FGHJ_SW_BUS,
AB_SW_P => SW_ABP,CD_SW_P => SW_CDP,
FG_SW_P => SW_FGP,HJ_SW_P => SW_HJP,
TIMER_UPDATE => TIMER_UPDATE,
TIMER_UPDATE_OR_EXT_INT => TIMER_UPDATE_OR_EXT_INT,
EXT_INTRP => EXTERNAL_INT,
A_BUS => A_BUS2,
H_REG_BITS => H(0 to 7),
H_REG_P => H(8),
H_REG_6 => H_REG_6,
H_REG_5_PWR => sH_REG_5_PWR,
GT_1050_TAGS => GT_1050_TAGS,
GT_1050_BUS => GT_1050_BUS,
CD_REG_2 => CD_REG_2,
-- E switch
E_SW => E_SW,
-- Clocks
T1 => T1,T2 => T2,T3 => T3,T4 => T4,
clk => clk
);
H_REG_5_PWR <= sH_REG_5_PWR;
A_BUS <= A_BUS1 and A_BUS2;
rwstg: entity RWStgCntl port map(
-- Inputs
SALS => sSALS,
ANY_PRIORITY_PULSE => ANY_PRIORITY_PULSE,
ANY_PRIORITY_PULSE_2 => ANY_PRIORITY_PULSE_2,
G_REG_0_BIT => G(0),
G_REG_1_BIT => G(1),
N1401_MODE => sN1401_MODE,
USE_CPU_DECODER => USE_CPU_DECODER,
USE_MAN_DECODER => sUSE_MANUAL_DECODER,
E_SW_SEL_AUX_STG => E_SW.LS_SEL,
MEM_SEL => sSTG_MEM_SEL,
ALLOW_WRITE => sALLOW_WRITE_DLYD,
ALLOW_WRITE_2 => sALLOW_WRITE,
SEL_RD_WR_CTRL => SEL_RD_WR_CTRL,
MAN_STOR_OR_DISPLAY => sMAN_STOR_OR_DSPLY,
MACH_RST_1 => MACH_RST_1,
MANUAL_RD_CALL => MANUAL_READ_CALL,
MANUAL_WR_CALL => MANUAL_WRITE_CALL,
HSMPX_READ_CALL => '0',
SEL_RD_CALL_TO_STP => SEL_RD_CALL_TO_STP,
SEL_SHARE_HOLD => SEL_SHARE_HOLD,
SELECT_CPU_BUMP => SELECT_CPU_BUMP,
-- Outputs
USE_ALT_CU_DECODE => USE_ALT_CU_DECODER,
USE_GR_OR_HR => USE_GR_OR_HR,
USE_R => sUSE_R,
CPU_WRITE_IN_R_REG => CPU_WRITE_IN_R_REG,
CPU_WRITE_PWR => CPU_WR_PWR,
COMPUTE => COMPUTE,
CPU_READ_PWR => sCPU_READ_PWR,
FORCE_M_REG_123 => sFORCE_M_REG_123,
CU_DECODE_UCW => CU_DECODE_UCW,
MAIN_STORAGE_CP => sMAIN_STORAGE_CP,
LOCAL_STORAGE_CP => LOCAL_STORAGE_CP,
MAIN_STORAGE => sMAIN_STORAGE,
EARLY_LOCAL_STG => EARLY_LOCAL_STG,
GT_LOCAL_STG => GT_LOCAL_STORAGE,
CHANNEL_RD_CALL => CHANNEL_RD_CALL,
N_MEM_SELECT => N_STACK_MEM_SELECT,
RW_CTRL_STACK => STACK_RD_WR_CONTROL,
-- Clocks
T1 => T1,
SEL_T1 => SEL_T1,
clk => clk
);
MAIN_STORAGE <= sMAIN_STORAGE;
MAIN_STORAGE_CP <= sMAIN_STORAGE_CP;
FORCE_M_REG_123 <= sFORCE_M_REG_123;
USE_R <= sUSE_R;
CPU_RD_PWR <= sCPU_READ_PWR;
rind: entity RIndsChks port map(
-- Inputs
TEST_LAMP => LAMP_TEST,
R_REG_BUS => R(0 to 7),
R_REG_BUS_P => R(8),
G_REG_1 => G(1),
V_REG_6 => V(6),
V_REG_7 => V(7),
GM_WM_DETECTED => GM_WM_DETECTED,
CARRY_1_LCHD => CARRY_1_LCHD,
S_REG_1 => S(1),
W3_TO_MATCH => WX(0),
ROS_SCAN => ROS_SCAN,
GT_SW_MACH_RST => GT_SW_MACH_RST,
-- Outputs
IND_MSDR => IND_MSDR,
IND_MSDR_P => IND_MSDR_P,
R_REG_PC => R_REG_PC,
R_REG_VALID_DEC_DIGIT => R_REG_VAL_DEC_DIG,
N1BC_OR_R1 => N1BC_OR_R1,
S_REG_1_OR_R_REG_2 => S_REG_1_OR_R_REG_2,
G_REG_1_OR_R_REG_3 => G_REG_1_OR_R_REG_3,
V67_00_OR_GM_WM => V67_00_OR_GM_WM,
N1401_MODE => sN1401_MODE,
-- Clocks
T2 => T2,
CLK => CLK
);
N1401_MODE <= sN1401_MODE;
mnassm: entity MNAssem port map(
-- Inputs
MAIN_STORAGE_CP => sMAIN_STORAGE_CP,
SX_2_BUMP_SW_GT => SX_2_BUMP_SW_GT,
USE_CPU_DECODER => USE_CPU_DECODER,
E_SEL_SW_BUS => E_SW,
SALS => sSALS,
MEM_SEL => sSTG_MEM_SEL,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
N1401_MODE => sN1401_MODE,
USE_MANUAL_DECODER => sUSE_MANUAL_DECODER,
SX_2_R_W_CTRL => SX_2_R_W_CTRL,
SX_2_SHARE_CYCLE => SX2_SHARE_CYCLE,
SX_2_GATE => SX_2_GATE,
SX_1_R_W_CTRL => SX_1_R_W_CTRL,
SX_1_SHARE_CYCLE => SX1_SHARE_CYCLE,
SX_1_GATE => SX_1_GATE,
XXH => XXH,
CU_DECODE_UCW => CU_DECODE_UCW,
FORCE_M_REG_123 => sFORCE_M_REG_123,
XH => XH, XL => XL,
CU_SAL_0_BIT => sSALS.SALS_CU(0),
MACH_RST_2A => MACH_RST_2A,
ABCD_SW_BUS => ABCD_SW_BUS,
AB_SW_P => SW_ABP,
CD_SW_P => SW_CDP,
IJ_SEL => IJ_SEL,
UV_SEL => UV_SEL,
I => I(0 to 7),
U => U(0 to 7),
T => T(0 to 7),
V => V(0 to 7),
J => J(0 to 7),
L => L(0 to 7),
GU => GU(0 to 7),
GV => GV(0 to 7),
HU => HU(0 to 7),
HV => HV(0 to 7),
I_P => I(8),
U_P => U(8),
T_P => T(8),
V_P => V(8),
J_P => J(8),
L_P => L(8),
GU_P => GU(8),
GV_P => GV(8),
HU_P => HU(8),
HV_P => HV(8),
-- Outputs
GT_T_TO_MN_REG => GT_T_TO_MN_REG,
GT_CK_TO_MN_REG => GT_CK_TO_MN_REG,
GT_V_TO_N_REG => GT_V_TO_N_REG,
GT_J_TO_N_REG => GT_J_TO_N_REG,
M_BUS => M_ASSM_BUS(0 to 7),
N_BUS => N_ASSM_BUS(0 to 7),
M_BUS_P => M_ASSM_BUS(8),
N_BUS_P => N_ASSM_BUS(8)
);
Regs: entity RegsABAssm port map(
-- Inputs
SALS => sSALS,
MACH_RST_SET_LCH => sMACH_RST_SET_LCH,
SEL_SHARE_CYCLE => SEL_SHARE_CYCLE,
USE_MAN_DECODER => sUSE_MANUAL_DECODER,
MAN_STOR_PWR => MANUAL_STORE_PWR,
USE_MAN_DECODER_PWR => sUSE_MAN_DECODER_PWR,
FG_SWS => FGHJ_SW_BUS(0 to 7),
FG_SW_P => SW_FGP,
USE_BASIC_CA_DECODER => sUSE_BASIC_CA_DECODER,
USE_ALT_CA_DECODER => sUSE_ALT_CA_DECODER,
MPX_BUS => MPX_BUS,
FT0 => FT0,
FT3 => FT3,
FT5 => FT5,
FT6 => FT6,
FT1 => FT1,
FT2 => FT2,
FT7 => FT7,
FT4 => FT_4_LD_IND,
E_SW_SEL_BUS => E_SW,
CD_CTRL_REG => sCTRL.CTRL_CD,
CD_REG_2 => CD_REG_2,
MACH_RST_2A_B => MACH_RST_2A,
HJ_SWS => FGHJ_SW_BUS(8 to 15),
HJ_SW_P => SW_HJP,
Z_BUS => Z_BUS,
R_REG => R,
-- Outputs
USE_CPU_DECODER => USE_CPU_DECODER,
GATED_CA_BITS => sGTD_CA_BITS,
GT_J_TO_A => GT_J_REG_TO_A_BUS,
GT_D_TO_A => GT_D_REG_TO_A_BUS,
I => I,
J => J,
U => U,
V => V,
T => T,
G => G,
L => L,
A_BUS => A_BUS1,
B_BUS_OUT => B_BUS,
-- Clocks
T4 => T4
);
GTD_CA_BITS <= sGTD_CA_BITS;
RW1st32k: entity RWStgClk1st32k port map(
-- Inputs
ALLOW_WRITE => sALLOW_WRITE_DLYD,
CPU_READ_PWR => sCPU_READ_PWR,
SEL_RD_CALL => SEL_READ_CALL,
MAN_RD_CALL => MANUAL_READ_CALL,
ROAR_RESTT_AND_STOR_BYPASS => SW_ROAR_RESTT_STOR_BYPASS,
SEL_WR_CALL => SEL_WR_CALL,
MAN_WR_CALL => MANUAL_WRITE_CALL,
CPU_WRITE_PWR => CPU_WR_PWR,
EARLY_LOCAL_STG => EARLY_LOCAL_STG,
EARLY_M_REG_0 => EARLY_M_REG_0,
M_REG_0 => M_REG_0,
MACH_RST_SW => sMACH_RST_SW,
-- Outputs
READ_CALL => READ_CALL,
USE_LOCAL_MAIN_MEM => USE_LOC_MAIN_MEM,
USE_MAIN_MEMORY => USE_MAIN_MEMORY,
READ_ECHO_1 => sREAD_ECHO_1,
READ_ECHO_2 => sREAD_ECHO_2,
WRITE_ECHO_1 => sWRITE_ECHO_1,
WRITE_ECHO_2 => sWRITE_ECHO_2,
DATA_READY_1 => DATA_READY_1,
DATA_READY_2 => DATA_READY_2,
DEBUG => open,
-- Clocks
T1 => T1,T2 => T2,T3 => T3,T4 => T4,
CLK => CLK
);
READ_ECHO_1 <= sREAD_ECHO_1;
READ_ECHO_2 <= sREAD_ECHO_2;
WRITE_ECHO_1 <= sWRITE_ECHO_1;
WRITE_ECHO_2 <= sWRITE_ECHO_2;
end FMD;
| gpl-3.0 | e91ff2bc175da450a833c6f6c3415c4c | 0.579646 | 2.534598 | false | false | false | false |
chastell/art-decomp | kiss/beecount_rnd.vhd | 1 | 3,518 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity beecount_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(3 downto 0)
);
end beecount_rnd;
architecture behaviour of beecount_rnd is
constant st0: std_logic_vector(2 downto 0) := "101";
constant st1: std_logic_vector(2 downto 0) := "010";
constant st4: std_logic_vector(2 downto 0) := "011";
constant st2: std_logic_vector(2 downto 0) := "110";
constant st3: std_logic_vector(2 downto 0) := "111";
constant st5: std_logic_vector(2 downto 0) := "001";
constant st6: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "000") then next_state <= st0; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st1 =>
if std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "0-0") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st2 =>
if std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st3 =>
if std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "0110";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st4 =>
if std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "-00") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st5 =>
if std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st6 =>
if std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "1001";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when others => next_state <= "---"; output <= "----";
end case;
end process;
end behaviour;
| agpl-3.0 | 661c2159bc32460f53a6116e8aafacc3 | 0.58556 | 3.309501 | false | false | false | false |
chastell/art-decomp | kiss/tma_jed.vhd | 1 | 6,129 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_jed;
architecture behaviour of tma_jed is
constant I0: std_logic_vector(4 downto 0) := "11100";
constant T1: std_logic_vector(4 downto 0) := "11111";
constant R1: std_logic_vector(4 downto 0) := "00111";
constant T3: std_logic_vector(4 downto 0) := "10010";
constant T9: std_logic_vector(4 downto 0) := "01010";
constant T4: std_logic_vector(4 downto 0) := "11000";
constant T5: std_logic_vector(4 downto 0) := "11011";
constant T6: std_logic_vector(4 downto 0) := "11110";
constant T7: std_logic_vector(4 downto 0) := "00110";
constant T8: std_logic_vector(4 downto 0) := "00010";
constant I2: std_logic_vector(4 downto 0) := "01110";
constant T2: std_logic_vector(4 downto 0) := "11010";
constant R2: std_logic_vector(4 downto 0) := "00000";
constant I1: std_logic_vector(4 downto 0) := "01000";
constant R3: std_logic_vector(4 downto 0) := "01001";
constant R4: std_logic_vector(4 downto 0) := "01101";
constant R6: std_logic_vector(4 downto 0) := "01111";
constant R8: std_logic_vector(4 downto 0) := "01100";
constant R5: std_logic_vector(4 downto 0) := "01011";
constant R7: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when I0 =>
if std_match(input, "11110--") then next_state <= T1; output <= "000000";
elsif std_match(input, "101-1--") then next_state <= R1; output <= "000000";
end if;
when T1 =>
if std_match(input, "1110---") then next_state <= T3; output <= "100000";
elsif std_match(input, "100----") then next_state <= T9; output <= "100000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "100000";
end if;
when T3 =>
if std_match(input, "111----") then next_state <= T4; output <= "110000";
elsif std_match(input, "100----") then next_state <= T9; output <= "110000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "110000";
end if;
when T4 =>
if std_match(input, "111----") then next_state <= T5; output <= "001000";
elsif std_match(input, "100----") then next_state <= T9; output <= "001000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "001000";
end if;
when T5 =>
if std_match(input, "111-0--") then next_state <= T6; output <= "101000";
elsif std_match(input, "100----") then next_state <= T9; output <= "101000";
elsif std_match(input, "101-1--") then next_state <= T9; output <= "101000";
end if;
when T6 =>
if std_match(input, "101-0--") then next_state <= T7; output <= "011000";
elsif std_match(input, "101-1--") then next_state <= T8; output <= "011000";
elsif std_match(input, "100----") then next_state <= T9; output <= "011000";
end if;
when T7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111000";
end if;
when T8 =>
if std_match(input, "10-----") then next_state <= I2; output <= "000100";
end if;
when T9 =>
if std_match(input, "101-0--") then next_state <= T2; output <= "100100";
elsif std_match(input, "100----") then next_state <= T2; output <= "100100";
end if;
when T2 =>
if std_match(input, "10-----") then next_state <= T8; output <= "010100";
end if;
when R1 =>
if std_match(input, "101-1--") then next_state <= R2; output <= "100010";
elsif std_match(input, "100----") then next_state <= I1; output <= "100010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "100010";
end if;
when R2 =>
if std_match(input, "101-1--") then next_state <= R3; output <= "010010";
elsif std_match(input, "100----") then next_state <= I1; output <= "010010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "010010";
end if;
when R3 =>
if std_match(input, "101-1--") then next_state <= R4; output <= "110010";
elsif std_match(input, "101-0-0") then next_state <= R6; output <= "110010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "110010";
elsif std_match(input, "100----") then next_state <= R5; output <= "110010";
end if;
when R4 =>
if std_match(input, "101-0-0") then next_state <= R6; output <= "001010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "001010";
elsif std_match(input, "100----") then next_state <= R5; output <= "001010";
end if;
when R6 =>
if std_match(input, "101-0--") then next_state <= R7; output <= "011010";
elsif std_match(input, "101-1--") then next_state <= R5; output <= "011010";
elsif std_match(input, "100----") then next_state <= R5; output <= "011010";
end if;
when R7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111010";
end if;
when R8 =>
if std_match(input, "10-----") then next_state <= R5; output <= "000110";
end if;
when R5 =>
if std_match(input, "101----") then next_state <= I2; output <= "100110";
elsif std_match(input, "100----") then next_state <= I1; output <= "100110";
end if;
when I2 =>
if std_match(input, "-------") then next_state <= I0; output <= "000001";
end if;
when I1 =>
if std_match(input, "111-0--") then next_state <= I0; output <= "010111";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
| agpl-3.0 | 20dd392987c0a908eb8ab73149c62664 | 0.564856 | 3.300485 | false | false | false | false |
chastell/art-decomp | kiss/s420_jed.vhd | 1 | 17,549 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_jed is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_jed;
architecture behaviour of s420_jed is
constant s1111111111111111: std_logic_vector(4 downto 0) := "11000";
constant s0000000000000000: std_logic_vector(4 downto 0) := "00001";
constant s0001000000000000: std_logic_vector(4 downto 0) := "01001";
constant s0010000000000000: std_logic_vector(4 downto 0) := "11001";
constant s0011000000000000: std_logic_vector(4 downto 0) := "01101";
constant s0100000000000000: std_logic_vector(4 downto 0) := "10000";
constant s0101000000000000: std_logic_vector(4 downto 0) := "10001";
constant s0110000000000000: std_logic_vector(4 downto 0) := "10101";
constant s0111000000000000: std_logic_vector(4 downto 0) := "01111";
constant s1000000000000000: std_logic_vector(4 downto 0) := "00010";
constant s1001000000000000: std_logic_vector(4 downto 0) := "00011";
constant s1010000000000000: std_logic_vector(4 downto 0) := "01000";
constant s1011000000000000: std_logic_vector(4 downto 0) := "00111";
constant s1100000000000000: std_logic_vector(4 downto 0) := "00000";
constant s1101000000000000: std_logic_vector(4 downto 0) := "10011";
constant s1110000000000000: std_logic_vector(4 downto 0) := "00100";
constant s1111000000000000: std_logic_vector(4 downto 0) := "01011";
constant s0000000100000000: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 085e5bc32cf7d5e0c3248192a669713c | 0.564192 | 4.094494 | false | false | false | false |
chastell/art-decomp | kiss/dk16_rnd.vhd | 1 | 12,212 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk16_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk16_rnd;
architecture behaviour of dk16_rnd is
constant state_1: std_logic_vector(4 downto 0) := "11101";
constant state_3: std_logic_vector(4 downto 0) := "00010";
constant state_2: std_logic_vector(4 downto 0) := "11011";
constant state_4: std_logic_vector(4 downto 0) := "11110";
constant state_5: std_logic_vector(4 downto 0) := "11111";
constant state_6: std_logic_vector(4 downto 0) := "10001";
constant state_7: std_logic_vector(4 downto 0) := "10110";
constant state_9: std_logic_vector(4 downto 0) := "01011";
constant state_8: std_logic_vector(4 downto 0) := "01111";
constant state_15: std_logic_vector(4 downto 0) := "00001";
constant state_10: std_logic_vector(4 downto 0) := "10000";
constant state_14: std_logic_vector(4 downto 0) := "11010";
constant state_11: std_logic_vector(4 downto 0) := "11000";
constant state_12: std_logic_vector(4 downto 0) := "01000";
constant state_20: std_logic_vector(4 downto 0) := "00100";
constant state_13: std_logic_vector(4 downto 0) := "01001";
constant state_16: std_logic_vector(4 downto 0) := "00110";
constant state_17: std_logic_vector(4 downto 0) := "11100";
constant state_18: std_logic_vector(4 downto 0) := "00011";
constant state_19: std_logic_vector(4 downto 0) := "10111";
constant state_21: std_logic_vector(4 downto 0) := "10011";
constant state_22: std_logic_vector(4 downto 0) := "10010";
constant state_23: std_logic_vector(4 downto 0) := "00111";
constant state_24: std_logic_vector(4 downto 0) := "01100";
constant state_25: std_logic_vector(4 downto 0) := "10101";
constant state_26: std_logic_vector(4 downto 0) := "10100";
constant state_27: std_logic_vector(4 downto 0) := "00000";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "00") then next_state <= state_3; output <= "001";
elsif std_match(input, "01") then next_state <= state_10; output <= "001";
elsif std_match(input, "10") then next_state <= state_11; output <= "001";
elsif std_match(input, "11") then next_state <= state_12; output <= "001";
end if;
when state_2 =>
if std_match(input, "00") then next_state <= state_1; output <= "001";
elsif std_match(input, "01") then next_state <= state_2; output <= "001";
elsif std_match(input, "10") then next_state <= state_8; output <= "001";
elsif std_match(input, "11") then next_state <= state_9; output <= "001";
end if;
when state_3 =>
if std_match(input, "00") then next_state <= state_4; output <= "001";
elsif std_match(input, "01") then next_state <= state_5; output <= "001";
elsif std_match(input, "10") then next_state <= state_6; output <= "001";
elsif std_match(input, "11") then next_state <= state_7; output <= "001";
end if;
when state_4 =>
if std_match(input, "00") then next_state <= state_4; output <= "010";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "010";
elsif std_match(input, "11") then next_state <= state_7; output <= "010";
end if;
when state_5 =>
if std_match(input, "00") then next_state <= state_1; output <= "010";
elsif std_match(input, "01") then next_state <= state_2; output <= "010";
elsif std_match(input, "10") then next_state <= state_16; output <= "010";
elsif std_match(input, "11") then next_state <= state_17; output <= "010";
end if;
when state_6 =>
if std_match(input, "00") then next_state <= state_3; output <= "010";
elsif std_match(input, "01") then next_state <= state_21; output <= "010";
elsif std_match(input, "10") then next_state <= state_10; output <= "010";
elsif std_match(input, "11") then next_state <= state_22; output <= "010";
end if;
when state_7 =>
if std_match(input, "00") then next_state <= state_9; output <= "010";
elsif std_match(input, "01") then next_state <= state_18; output <= "010";
elsif std_match(input, "10") then next_state <= state_19; output <= "010";
elsif std_match(input, "11") then next_state <= state_20; output <= "010";
end if;
when state_8 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_26; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_9 =>
if std_match(input, "00") then next_state <= state_1; output <= "000";
elsif std_match(input, "01") then next_state <= state_5; output <= "000";
elsif std_match(input, "10") then next_state <= state_6; output <= "000";
elsif std_match(input, "11") then next_state <= state_7; output <= "000";
end if;
when state_10 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_1; output <= "000";
elsif std_match(input, "11") then next_state <= state_2; output <= "000";
end if;
when state_11 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_24; output <= "000";
elsif std_match(input, "11") then next_state <= state_25; output <= "000";
end if;
when state_12 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_13 =>
if std_match(input, "00") then next_state <= state_3; output <= "101";
elsif std_match(input, "01") then next_state <= state_10; output <= "101";
elsif std_match(input, "10") then next_state <= state_11; output <= "101";
elsif std_match(input, "11") then next_state <= state_12; output <= "101";
end if;
when state_14 =>
if std_match(input, "00") then next_state <= state_1; output <= "101";
elsif std_match(input, "01") then next_state <= state_2; output <= "101";
elsif std_match(input, "10") then next_state <= state_8; output <= "101";
elsif std_match(input, "11") then next_state <= state_9; output <= "101";
end if;
when state_15 =>
if std_match(input, "00") then next_state <= state_4; output <= "101";
elsif std_match(input, "01") then next_state <= state_5; output <= "101";
elsif std_match(input, "10") then next_state <= state_6; output <= "101";
elsif std_match(input, "11") then next_state <= state_7; output <= "101";
end if;
when state_16 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_17 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_23; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_27; output <= "000";
end if;
when state_18 =>
if std_match(input, "00") then next_state <= state_4; output <= "100";
elsif std_match(input, "01") then next_state <= state_5; output <= "010";
elsif std_match(input, "10") then next_state <= state_6; output <= "100";
elsif std_match(input, "11") then next_state <= state_7; output <= "100";
end if;
when state_19 =>
if std_match(input, "00") then next_state <= state_18; output <= "100";
elsif std_match(input, "01") then next_state <= state_23; output <= "010";
elsif std_match(input, "10") then next_state <= state_24; output <= "100";
elsif std_match(input, "11") then next_state <= state_25; output <= "100";
end if;
when state_20 =>
if std_match(input, "00") then next_state <= state_19; output <= "100";
elsif std_match(input, "01") then next_state <= state_20; output <= "010";
elsif std_match(input, "10") then next_state <= state_9; output <= "100";
elsif std_match(input, "11") then next_state <= state_26; output <= "100";
end if;
when state_21 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_22 =>
if std_match(input, "00") then next_state <= state_3; output <= "000";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "100";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_23 =>
if std_match(input, "00") then next_state <= state_2; output <= "100";
elsif std_match(input, "01") then next_state <= state_1; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "010";
elsif std_match(input, "11") then next_state <= state_14; output <= "010";
end if;
when state_24 =>
if std_match(input, "00") then next_state <= state_14; output <= "000";
elsif std_match(input, "01") then next_state <= state_13; output <= "000";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when state_25 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_15; output <= "000";
elsif std_match(input, "11") then next_state <= state_15; output <= "000";
end if;
when state_26 =>
if std_match(input, "00") then next_state <= state_20; output <= "000";
elsif std_match(input, "01") then next_state <= state_19; output <= "000";
elsif std_match(input, "10") then next_state <= state_18; output <= "000";
elsif std_match(input, "11") then next_state <= state_21; output <= "000";
end if;
when state_27 =>
if std_match(input, "00") then next_state <= state_15; output <= "010";
elsif std_match(input, "01") then next_state <= state_3; output <= "010";
elsif std_match(input, "10") then next_state <= state_13; output <= "100";
elsif std_match(input, "11") then next_state <= state_14; output <= "100";
end if;
when others => next_state <= "-----"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | 97003fb56ad7ddb8fac7aef33b081227 | 0.585162 | 3.295197 | false | false | false | false |
thommyj/slotcar | de0/uart_tx.vhd | 1 | 5,535 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity txuart is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
busy : out std_logic
);
end entity txuart;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of txuart is
type sendstate_type is (TXSTATE_IDLE, TXSTATE_START, TXSTATE_DATA, TXSTATE_STOP);
signal send_state : sendstate_type;
type clkstate_type is (CLKSTATE_IDLE, CLKSTATE_COUNTING);
signal clk_state : clkstate_type;
signal send_data : std_logic_vector(7 downto 0);
signal uart_clk_re : std_logic;
begin
process(clk, rst)
variable uart_clk_cnt : integer := 0;
begin
if rst = '1' then
uart_clk_cnt := 0;
uart_clk_re <= '0';
elsif rising_edge(clk) then
case clk_state is
when CLKSTATE_IDLE =>
uart_clk_cnt := 0;
uart_clk_re <= '0';
when CLKSTATE_COUNTING =>
--TODO: fix average frequency
if uart_clk_cnt = 2604 then
uart_clk_re <= '1';
uart_clk_cnt := 0;
else
uart_clk_re <= '0';
uart_clk_cnt := uart_clk_cnt + 1;
end if;
end case;
end if;
end process;
--
-- when data_in_valid goes high, start sending out data
--
process(clk,rst)
variable send_cnt : integer := 0;
begin
if rst = '1' then
send_state <= TXSTATE_IDLE;
clk_state <= CLKSTATE_IDLE;
send_cnt := 0;
uart_data_out <= '1';
parallell_data_in_sent <= '0';
busy <= '0';
elsif rising_edge(clk) then
parallell_data_in_sent <= '0';
case send_state is
when TXSTATE_IDLE =>
uart_data_out <= '1'; --high during idle
busy <= '0';
clk_state <= CLKSTATE_IDLE;
send_cnt := 0;
if(parallell_data_in_valid = '1') then
send_state <= TXSTATE_START;
clk_state <= CLKSTATE_COUNTING; --restart UART clock
busy <= '1';
send_data <= parallell_data_in;
end if;
when TXSTATE_START =>
uart_data_out <= '0'; --start bit low
if uart_clk_re = '1' then
send_state <= TXSTATE_DATA;
end if;
when TXSTATE_DATA =>
uart_data_out <= send_data(send_cnt);
if uart_clk_re = '1' then
send_cnt := send_cnt + 1;
if(send_cnt > 7) then
send_state <= TXSTATE_STOP;
end if;
end if;
when TXSTATE_STOP =>
uart_data_out <= '1'; --stop bit high
if uart_clk_re = '1' then
parallell_data_in_sent <= '1'; --transmit done
send_state <= TXSTATE_IDLE;
busy <= '0';
end if;
end case;
end if;
end process;
end architecture syn;
-- *** EOF ***
| mit | 7da4aa25db21296a0aef3f68a7c2665b | 0.526468 | 3.9367 | false | false | false | false |
chastell/art-decomp | kiss/s510_nov.vhd | 1 | 13,167 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_nov is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_nov;
architecture behaviour of s510_nov is
constant s000000: std_logic_vector(5 downto 0) := "111101";
constant s010010: std_logic_vector(5 downto 0) := "000010";
constant s010011: std_logic_vector(5 downto 0) := "111100";
constant s000100: std_logic_vector(5 downto 0) := "000011";
constant s000001: std_logic_vector(5 downto 0) := "111111";
constant s100101: std_logic_vector(5 downto 0) := "000000";
constant s100100: std_logic_vector(5 downto 0) := "111110";
constant s000010: std_logic_vector(5 downto 0) := "000001";
constant s000011: std_logic_vector(5 downto 0) := "111001";
constant s011100: std_logic_vector(5 downto 0) := "000110";
constant s011101: std_logic_vector(5 downto 0) := "111000";
constant s000111: std_logic_vector(5 downto 0) := "000111";
constant s000101: std_logic_vector(5 downto 0) := "111011";
constant s010000: std_logic_vector(5 downto 0) := "000100";
constant s010001: std_logic_vector(5 downto 0) := "111010";
constant s001000: std_logic_vector(5 downto 0) := "000101";
constant s001001: std_logic_vector(5 downto 0) := "110101";
constant s010100: std_logic_vector(5 downto 0) := "001010";
constant s010101: std_logic_vector(5 downto 0) := "110100";
constant s001010: std_logic_vector(5 downto 0) := "001011";
constant s001011: std_logic_vector(5 downto 0) := "110111";
constant s011000: std_logic_vector(5 downto 0) := "001000";
constant s011001: std_logic_vector(5 downto 0) := "110110";
constant s011010: std_logic_vector(5 downto 0) := "001001";
constant s011011: std_logic_vector(5 downto 0) := "110001";
constant s001100: std_logic_vector(5 downto 0) := "001110";
constant s001101: std_logic_vector(5 downto 0) := "110000";
constant s011110: std_logic_vector(5 downto 0) := "001111";
constant s011111: std_logic_vector(5 downto 0) := "110011";
constant s100000: std_logic_vector(5 downto 0) := "001100";
constant s100001: std_logic_vector(5 downto 0) := "110010";
constant s100010: std_logic_vector(5 downto 0) := "001101";
constant s100011: std_logic_vector(5 downto 0) := "101101";
constant s001110: std_logic_vector(5 downto 0) := "010010";
constant s001111: std_logic_vector(5 downto 0) := "101100";
constant s100110: std_logic_vector(5 downto 0) := "010011";
constant s100111: std_logic_vector(5 downto 0) := "101111";
constant s101000: std_logic_vector(5 downto 0) := "010000";
constant s101001: std_logic_vector(5 downto 0) := "101110";
constant s101010: std_logic_vector(5 downto 0) := "010001";
constant s101011: std_logic_vector(5 downto 0) := "101001";
constant s101100: std_logic_vector(5 downto 0) := "010110";
constant s101101: std_logic_vector(5 downto 0) := "101000";
constant s101110: std_logic_vector(5 downto 0) := "010111";
constant s010110: std_logic_vector(5 downto 0) := "101011";
constant s010111: std_logic_vector(5 downto 0) := "010100";
constant s000110: std_logic_vector(5 downto 0) := "101010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | fae7375ff17c1f0ed174849961ac1903 | 0.536189 | 3.970748 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-02A-B.vhd | 1 | 9,958 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-02A-B.vhd
-- Creation Date:
-- Description:
-- X6,X7 assembly, ASCII latch, X6,X7 backup (5-02A), WX reg gating (5-02B)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Enable MPX interruptions
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY X6X7 IS
port
(
SALS : IN SALS_Bus; -- 01C
DECIMAL : IN STD_LOGIC; -- 06B
CONNECT : IN STD_LOGIC; -- 06B
N_CTRL_LM : IN STD_LOGIC; -- 06B
CTRL_N : IN STD_LOGIC; -- 06B
R_REG_0_BIT : IN STD_LOGIC; -- 06C
V67_00_OR_GM_WM : IN STD_LOGIC; -- 05A
STATUS_IN_LCHD : IN STD_LOGIC; -- 06A
OPNL_IN_LCHD : IN STD_LOGIC; -- 06A
CARRY_0_LCHD : IN STD_LOGIC; -- 06A
S_REG_1_OR_R_REG_2 : IN STD_LOGIC; -- 05A
S : IN STD_LOGIC_VECTOR(0 to 7); -- 07B
G : IN STD_LOGIC_VECTOR(0 to 7); -- 05C
TIMER_UPDATE : IN STD_LOGIC; -- 04C
EXTERNAL_INT : IN STD_LOGIC; -- 04C
MPX_INTERRUPT : IN STD_LOGIC; -- 08C
SX1_INTERRUPT : IN STD_LOGIC; -- 12D
SX2_INTERRUPT : IN STD_LOGIC; -- 14D
-- HSMPX : IN STD_LOGIC; -- XXXXX
I_WRAPPED_CPU : IN STD_LOGIC; -- 03B
TIMER_UPDATE_OR_EXT_INT : IN STD_LOGIC; -- 04C
U_WRAPPED_MPX : IN STD_LOGIC; -- 03B
H_REG_6_BIT : IN STD_LOGIC; -- 04C
ADDR_IN_LCHD : IN STD_LOGIC; -- 06A
SERV_IN_LCHD : IN STD_LOGIC; -- 06A
R_REG_VAL_DEC_DIG : IN STD_LOGIC; -- 05A
N1BC_OR_R1 : IN STD_LOGIC; -- 05A
Z_BUS_0 : IN STD_LOGIC; -- 06B
G_REG_1_OR_R_REG_3 : IN STD_LOGIC; -- 05A
GT_BU_ROSAR_TO_WX_REG : IN STD_LOGIC; -- 01B
H_REG_5_PWR : IN STD_LOGIC; -- 04C
MPX_SHARE_PULSE : IN STD_LOGIC; -- 03A
SX_CHAIN_PULSE : IN STD_LOGIC; -- 03A
MACH_RST_SW : IN STD_LOGIC; -- 03D
R_REG_4_BIT : IN STD_LOGIC; -- 06C
ANY_PRIORITY_PULSE : IN STD_LOGIC; -- 03A
-- Outputs
XOR_OR_OR : OUT STD_LOGIC; -- 03A,04A
INTERRUPT : OUT STD_LOGIC; -- 01B
GT_GWX_TO_WX_REG : OUT STD_LOGIC; -- 01B
GT_FWX_TO_WX_REG : OUT STD_LOGIC; -- 01B
USE_CA_BASIC_DECODER : OUT STD_LOGIC; -- 02B,01A,03C,04C,05C,07A,07C,10C
MPX_ROS_LCH : OUT STD_LOGIC; -- 08C
X6 : OUT STD_LOGIC;
X7 : OUT STD_LOGIC;
USE_ALT_CA_DECODER : OUT STD_LOGIC; -- 07C,04C,10C,07A,11C
GT_CA_TO_W_REG : OUT STD_LOGIC; -- 01B,07A
GT_UV_TO_WX_REG : OUT STD_LOGIC; -- 01B
DIAG_LATCH_RST : OUT STD_LOGIC; -- NEW
-- Debug
DEBUG : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END X6X7;
ARCHITECTURE FMD OF X6X7 IS
signal TEST_ASCII : STD_LOGIC;
signal TEST_INTRP : STD_LOGIC;
signal TEST_WRAP : STD_LOGIC;
signal GT_ASCII_LCH : STD_LOGIC;
signal GT_MPX_LCH : STD_LOGIC; -- Output of AA3E3
signal GT_SX_LCH : STD_LOGIC; -- Output of AA3L6
signal X6_MUX,X7_MUX : STD_LOGIC;
signal CA_TO_X7_DECO : STD_LOGIC;
signal X6_BRANCH,X7_BRANCH : STD_LOGIC;
signal SX_CH_ROAR_RESTORE : STD_LOGIC;
signal MPX_CH_ROAR_RESTORE : STD_LOGIC;
signal RESTORE_0 : STD_LOGIC; -- Output of AA3K5,FL0
signal ASCII_LCH : STD_LOGIC;
signal MPX_CH_X6,MPX_CH_X7 : STD_LOGIC;
signal SX_CH_X6,SX_CH_X7 : STD_LOGIC;
signal X6_DATA,X7_DATA : STD_LOGIC;
signal STORED_X6,STORED_X7 : STD_LOGIC;
signal sXOR_OR_OR : STD_LOGIC;
signal sINTERRUPT : STD_LOGIC;
signal sGT_GWX_TO_WX_REG : STD_LOGIC;
signal sGT_FWX_TO_WX_REG : STD_LOGIC;
signal sUSE_CA_BASIC_DECODER : STD_LOGIC;
signal sMPX_ROS_LCH : STD_LOGIC;
signal REST0_LCH_Set,REST0_LCH_Reset,SXREST_LCH_Set,SXREST_LCH_Reset,
MPXROS_LCH_Reset,MPXROS_LCH_Set,MPXREST_LCH_Set,MPXREST_LCH_Reset : STD_LOGIC;
BEGIN
-- Fig 5-02A
TEST_ASCII <= '1' when SALS.SALS_CK="1001" and SALS.SALS_AK='1' else '0'; -- AB3E7
TEST_INTRP <= '1' when SALS.SALS_CK="1010" and SALS.SALS_AK='1' else '0'; -- AB3E7
TEST_WRAP <= '1' when SALS.SALS_CK="0011" and SALS.SALS_AK='1' else '0'; -- AB3E6
DIAG_LATCH_RST <= '1' when SALS.SALS_CK="0000" and SALS.SALS_AK='1' and T1='1' else '0'; -- NEW!
sXOR_OR_OR <= DECIMAL and CONNECT and N_CTRL_LM; -- AB3D2
XOR_OR_OR <= sXOR_OR_OR;
GT_ASCII_LCH <= sXOR_OR_OR and CTRL_N and T2; -- AB3D2
DEBUG <= ASCII_LCH;
-- ?? Debug remove other interrupt sources
-- sINTERRUPT <= TIMER_UPDATE or EXTERNAL_INT or MPX_INTERRUPT or SX1_INTERRUPT or SX2_INTERRUPT; -- AA3K4
sINTERRUPT <= EXTERNAL_INT or MPX_INTERRUPT;
INTERRUPT <= sINTERRUPT;
with (SALS.SALS_CH) select X6_MUX <= -- AA3G5
'1' when "0001",
R_REG_0_BIT when "0010",
V67_00_OR_GM_WM when "0011",
STATUS_IN_LCHD when "0100",
OPNL_IN_LCHD when "0101",
CARRY_0_LCHD when "0110",
S(0) when "0111",
S_REG_1_OR_R_REG_2 when "1000",
S(2) when "1001",
S(4) when "1010",
S(6) when "1011",
G(0) when "1100",
G(2) when "1101",
G(4) when "1110",
G(6) when "1111",
'0' when others; -- 0000
with (SALS.SALS_CL) select X7_MUX <= -- AA3H5
'1' when "0001",
'1' when "0010", -- CL=0010 is CA>W ?? Needed otherwise CA>W always forces X7 to 0 ??
ADDR_IN_LCHD when "0011",
SERV_IN_LCHD when "0100",
R_REG_VAL_DEC_DIG when "0101",
N1BC_OR_R1 when "0110",
Z_BUS_0 when "0111",
G(7) when "1000",
S(3) when "1001",
S(5) when "1010",
S(7) when "1011",
G_REG_1_OR_R_REG_3 when "1100",
G(3) when "1101",
G(5) when "1110",
sINTERRUPT when "1111",
'0' when others; -- 0000
X6_BRANCH <= (not ASCII_LCH or not TEST_ASCII) and -- AA3K3
(not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3
(not SX2_INTERRUPT or SX1_INTERRUPT or not TEST_INTRP) and -- AA3K4
(not I_WRAPPED_CPU or not TEST_WRAP) and -- AA3K3
X6_MUX;
X7_BRANCH <= (not TIMER_UPDATE_OR_EXT_INT or not TEST_INTRP) and -- AA3K3
(not SX1_INTERRUPT or not TEST_INTRP) and -- AA3B7
(not TEST_WRAP or not U_WRAPPED_MPX or not H_REG_6_BIT) and -- AA3J5
X7_MUX ;
-- and CA_TO_X7_DECO; ?? Removed as it forced X7 to 0 on CA>W ??
sGT_GWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and H_REG_5_PWR; -- AA3L5
GT_GWX_TO_WX_REG <= sGT_GWX_TO_WX_REG;
sGT_FWX_TO_WX_REG <= GT_BU_ROSAR_TO_WX_REG and not H_REG_5_PWR; -- AA3C2
GT_FWX_TO_WX_REG <= sGT_FWX_TO_WX_REG;
sUSE_CA_BASIC_DECODER <= not SALS.SALS_AA;
USE_CA_BASIC_DECODER <= sUSE_CA_BASIC_DECODER;
REST0_LCH_Set <= T2 and sGT_GWX_TO_WX_REG;
REST0_LCH_Reset <= MACH_RST_SW or T1;
REST0_LCH: entity work.FLL port map(REST0_LCH_Set,REST0_LCH_Reset,RESTORE_0); -- AA3K5 Bit 0
SXREST_LCH_Set <= T4 and RESTORE_0;
SXREST_LCH_Reset <= MACH_RST_SW or T3;
SXREST_LCH: entity work.FLL port map(SXREST_LCH_Set,SXREST_LCH_Reset,SX_CH_ROAR_RESTORE); -- AA3K5 Bit 1
MPXROS_LCH_Set <= T2 and sGT_FWX_TO_WX_REG;
MPXROS_LCH_Reset <= MACH_RST_SW or T1;
MPXROS_LCH: entity work.FLL port map(MPXROS_LCH_Set,MPXROS_LCH_Reset,sMPX_ROS_LCH); -- AA3L2 Bit 2
MPX_ROS_LCH <= sMPX_ROS_LCH;
MPXREST_LCH_Set <= T4 and sMPX_ROS_LCH;
MPXREST_LCH_Reset <= MACH_RST_SW or T3;
MPXREST_LCH: entity work.FLL port map(MPXREST_LCH_Set,MPXREST_LCH_Reset,MPX_CH_ROAR_RESTORE); -- AA3L2 Bit 3
X6_DATA <= X6_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
X7_DATA <= X7_BRANCH and not SX_CH_ROAR_RESTORE and not MPX_CH_ROAR_RESTORE; -- AA3L6
GT_MPX_LCH <= (MPX_SHARE_PULSE and T1) or MACH_RST_SW; -- AA3L4,AA3E3
GT_SX_LCH <= (SX_CHAIN_PULSE and T1) or MACH_RST_SW; -- AA3F3,AA3L6
-- ASCII latch plus X6,X7 storage for
ASC_LCH: entity work.PH port map(R_REG_4_BIT,GT_ASCII_LCH,ASCII_LCH); -- AA3L3
M7_LCH: entity work.PH port map(X7_DATA,GT_MPX_LCH,MPX_CH_X7); -- AA3L3
S7_LCH: entity work.PH port map(X7_DATA,GT_SX_LCH,SX_CH_X7); -- AA3L3
M6_LCH: entity work.PH port map(X6_DATA,GT_MPX_LCH,MPX_CH_X6); -- AA3L3
S6_LCH: entity work.PH port map(X6_DATA,GT_SX_LCH,SX_CH_X6); -- AA3L3
STORED_X6 <= (SX_CH_ROAR_RESTORE and SX_CH_X6) or (MPX_CH_ROAR_RESTORE and MPX_CH_X6); -- AA3K6
STORED_X7 <= (SX_CH_ROAR_RESTORE and SX_CH_X7) or (MPX_CH_ROAR_RESTORE and MPX_CH_X7); -- AA3K6
X6 <= X6_DATA or STORED_X6; -- Wire-AND of negated signals
X7 <= X7_DATA or STORED_X7; -- Wire-AND of negated signals
-- Page 5-02B
USE_ALT_CA_DECODER <= not sUSE_CA_BASIC_DECODER and not ANY_PRIORITY_PULSE; -- AB2F7 ??
CA_TO_X7_DECO <= '0' when SALS.SALS_CL="0010" else '1'; -- AA3H5
GT_CA_TO_W_REG <= not CA_TO_X7_DECO and not ANY_PRIORITY_PULSE; -- AA3L4,AA3G4
GT_UV_TO_WX_REG <= '1' when SALS.SALS_CK="0001" and SALS.SALS_AK='1' and ANY_PRIORITY_PULSE='0' else '0'; -- AB3E6,AB3B3
END FMD;
| gpl-3.0 | df2abd5f1fb3a68597f8c9949ae0a9ba | 0.62864 | 2.549411 | false | true | false | false |
ibm2030/IBM2030 | FMD2030_5-01C-D.vhd | 1 | 8,593 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-01C-D.vhd
-- Creation Date:
-- Description:
-- CCROS storage, SALS (Sense Amplifier Latches), CTRL register
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.1 2012-04-07
-- Change CCROS initialisation
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE std.textio.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
library CCROS;
use CCROS.CCROS.all;
ENTITY CCROS IS
port
(
-- Inputs
WX : IN STD_LOGIC_VECTOR(0 to 12); -- 01B
MACH_RST_SW : IN STD_LOGIC; -- 03D
MANUAL_STORE : IN STD_LOGIC; -- 03D
ANY_PRIORITY_LCH : IN STD_LOGIC; -- 03A
COMPUTE : IN STD_LOGIC; -- 04D
MACH_RST_MPX : IN STD_LOGIC; -- 08C
CROS_STROBE : IN STD_LOGIC; -- 01B
CROS_GO_PULSE : IN STD_LOGIC; -- 01B
-- Outputs
SALS: OUT SALS_Bus;
CTRL : OUT CTRL_REG;
CTRL_REG_RST : OUT STD_LOGIC; -- 07B
CK_SAL_P_BIT_TO_MPX : OUT STD_LOGIC; -- ?
-- Clocks
T1 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END CCROS;
ARCHITECTURE FMD OF CCROS IS
signal SALS_Word : STD_LOGIC_VECTOR(0 to 54) := (others=>'1');
alias SALS_PN : STD_LOGIC is SALS_Word(0);
alias SALS_CN : STD_LOGIC_VECTOR(0 to 5) is SALS_Word(1 to 6);
alias SALS_PS : STD_LOGIC is SALS_Word(7);
alias SALS_PA : STD_LOGIC is SALS_Word(8);
alias SALS_CH : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(9 to 12);
alias SALS_CL : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(13 to 16);
alias SALS_CM : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(17 to 19);
alias SALS_CU : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(20 to 21);
alias SALS_CA : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(22 to 25);
alias SALS_CB : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(26 to 27);
alias SALS_CK : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(28 to 31);
alias SALS_PK : STD_LOGIC is SALS_Word(32);
alias SALS_PC : STD_LOGIC is SALS_Word(33);
alias SALS_CD : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(34 to 37);
alias SALS_CF : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(38 to 40);
alias SALS_CG : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(41 to 42);
alias SALS_CV : STD_LOGIC_VECTOR(0 to 1) is SALS_Word(43 to 44);
alias SALS_CC : STD_LOGIC_VECTOR(0 to 2) is SALS_Word(45 to 47);
alias SALS_CS : STD_LOGIC_VECTOR(0 to 3) is SALS_Word(48 to 51);
alias SALS_AA : STD_LOGIC is SALS_Word(52);
alias SALS_SA : STD_LOGIC is SALS_Word(53);
alias SALS_AK : STD_LOGIC is SALS_Word(54);
constant CCROS : CCROS_Type := Package_CCROS;
-- constant CCROS : CCROS_Type := readCCROS;
signal AUX_CTRL_REG_RST : STD_LOGIC;
signal SET_CTRL_REG : STD_LOGIC;
signal sCTRL : CTRL_REG;
signal sCTRL_REG_RST : STD_LOGIC;
signal CD_LCH_Set,CD_LCH_Reset,CS_LCH_Set,CS_LCH_Reset : STD_LOGIC_VECTOR(0 to 3);
signal STRAIGHT_LCH_Set,CROSSED_LCH_Set,CC2_LCH_Set,CC2_LCH_Reset,GTAHI_LCH_Set,GTAHI_LCH_Reset,
GTALO_LCH_Set,GTALO_LCH_Reset,COMPCY_LCH_Set,COMPCY_LCH_Reset,CG0_Set,CG1_Set,CG_Reset : STD_LOGIC;
signal CV_LCH_Set,CV_LCH_Reset,CC01_LCH_Set,CC01_LCH_Reset : STD_LOGIC_VECTOR(0 to 1);
signal CROS_STROBE_DELAY : STD_LOGIC_VECTOR(1 to 6) := "000000";
BEGIN
-- Page 5-01C
sCTRL_REG_RST <= MACH_RST_SW or MANUAL_STORE or ANY_PRIORITY_LCH;
CTRL_REG_RST <= sCTRL_REG_RST;
AUX_CTRL_REG_RST <= T1 or sCTRL_REG_RST;
SET_CTRL_REG <= not ANY_PRIORITY_LCH and P1;
CD_LCH_Set <= SALS_CD and (0 to 3 => SET_CTRL_REG);
CD_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST);
CD_LCH: FLVL port map(CD_LCH_Set,CD_LCH_Reset,sCTRL.CTRL_CD); -- AA2C6
STRAIGHT_LCH_Set <= sCTRL_REG_RST or (SET_CTRL_REG and not SALS_CF(0));
STRAIGHT_LCH: entity work.FLL port map(STRAIGHT_LCH_Set, T1, sCTRL.STRAIGHT);
CROSSED_LCH_Set <= SET_CTRL_REG and SALS_CF(0);
CROSSED_LCH: entity work.FLL port map(CROSSED_LCH_Set, AUX_CTRL_REG_RST, sCTRL.CROSSED);
CC2_LCH_Set <= SET_CTRL_REG and SALS_CC(2);
CC2_LCH_Reset <= T1 or sCTRL_REG_RST;
CC2_LCH: entity work.FLL port map(CC2_LCH_Set, CC2_LCH_Reset, sCTRL.CTRL_CC(2));
GTAHI_LCH_Set <= SET_CTRL_REG and SALS_CF(1);
GTAHI_LCH_Reset <= T1 or sCTRL_REG_RST;
GTAHI_LCH: entity work.FLL port map(GTAHI_LCH_Set, GTAHI_LCH_Reset, sCTRL.GT_A_REG_HI);
GTALO_LCH_Set <= SET_CTRL_REG and SALS_CF(2);
GTALO_LCH_Reset <= T1 or sCTRL_REG_RST;
GTALO_LCH: entity work.FLL port map(GTALO_LCH_Set, GTALO_LCH_Reset, sCTRL.GT_A_REG_LO);
COMPCY_LCH_Set <= SET_CTRL_REG and COMPUTE;
COMPCY_LCH_Reset <= T1 or sCTRL_REG_RST;
COMPCY_LCH: entity work.FLL port map(COMPCY_LCH_Set, COMPCY_LCH_Reset, sCTRL.COMPUTE_CY_LCH);
CG0_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(0));
CG_Reset <= T1 or (MACH_RST_SW or ANY_PRIORITY_LCH); -- ?? Required to prevent simultaneous Set & Reset of CG by MANUAL_STORE
CG0: entity work.FLL port map(CG0_Set, CG_Reset, sCTRL.CTRL_CG(0)); sCTRL.GT_B_REG_HI <= sCTRL.CTRL_CG(0);
CG1_Set <= MANUAL_STORE or (SET_CTRL_REG and SALS_CG(1));
CG1: entity work.FLL port map(CG1_Set, CG_Reset, sCTRL.CTRL_CG(1)); sCTRL.GT_B_REG_LO <= sCTRL.CTRL_CG(1);
CV_LCH_Set <= SALS_CV and (0 to 1 => SET_CTRL_REG);
CV_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST);
CV_LCH: entity work.FLVL port map(CV_LCH_Set,CV_LCH_Reset,sCTRL.CTRL_CV); -- AA2D6
CC01_LCH_Set <= SALS_CC(0 to 1) and (0 to 1 => SET_CTRL_REG);
CC01_LCH_Reset <= (0 to 1 => T1 or sCTRL_REG_RST);
CC01_LCH: entity work.FLVL port map(CC01_LCH_Set,CC01_LCH_Reset,sCTRL.CTRL_CC(0 to 1)); -- AA2D6
CS_LCH_Set <= SALS_CS and (0 to 3 => SET_CTRL_REG);
CS_LCH_Reset <= (0 to 3 => T1 or sCTRL_REG_RST);
CS_LCH: entity work.FLVL port map(CS_LCH_Set,CS_LCH_Reset,sCTRL.CTRL_CS); -- AA2D7
CTRL <= sCTRL;
CK_SAL_P_BIT_TO_MPX <= SALS_PK and not MACH_RST_MPX;
-- Page 5-01D
-- CCROS microcode storage
-- Start of read is CROS_GO_PULSE
-- End of read is CCROS_STROBE
-- Should use falling edge of CCROS_STROBE to gate data from CCROS into SALS (actually happens earlier)
CCROS_RESET_SET: process (Clk,CROS_STROBE,CROS_GO_PULSE,WX)
begin
-- Reset SALS when CROS_GO_PULSE goes Low
-- Set SALS 100ns after CROS_STROBE goes High (start of T3)
-- ROAR should have been set during T1 so we have a 1.5 minor cycle (~280ns) access time
if (Clk'Event and Clk='1') then
-- if (CROS_STROBE='1' and CROS_STROBE_DELAY="10000") then
--SALS_Word <= (others => '0');
-- else
if (CROS_STROBE='1' and CROS_STROBE_DELAY="111100") then
SALS_Word <= CCROS(CCROS_Address_Type(conv_integer(unsigned(WX(1 to 12)))));
-- end if;
end if;
CROS_STROBE_DELAY <= CROS_STROBE & CROS_STROBE_DELAY(1 to 5);
end if;
end process;
SALS.SALS_PN <= SALS_PN;
SALS.SALS_CN <= SALS_CN;
SALS.SALS_PS <= SALS_PS;
SALS.SALS_PA <= SALS_PA;
SALS.SALS_CH <= SALS_CH;
SALS.SALS_CL <= SALS_CL;
SALS.SALS_CM <= SALS_CM;
SALS.SALS_CU <= SALS_CU;
SALS.SALS_CA <= SALS_CA;
SALS.SALS_CB <= SALS_CB;
SALS.SALS_CK <= SALS_CK;
SALS.SALS_PK <= SALS_PK;
SALS.SALS_PC <= SALS_PC;
SALS.SALS_CD <= SALS_CD;
SALS.SALS_CF <= SALS_CF;
SALS.SALS_CG <= SALS_CG;
SALS.SALS_CV <= SALS_CV;
SALS.SALS_CC <= SALS_CC;
SALS.SALS_CS <= SALS_CS;
SALS.SALS_AA <= SALS_AA;
SALS.SALS_SA <= SALS_SA;
SALS.SALS_AK <= SALS_AK;
END FMD;
| gpl-3.0 | f8139207c69b2abed4b7f333d5e87462 | 0.652275 | 2.725341 | false | false | false | false |
chastell/art-decomp | kiss/ex5_jed.vhd | 1 | 3,826 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_jed;
architecture behaviour of ex5_jed is
constant s1: std_logic_vector(3 downto 0) := "0100";
constant s0: std_logic_vector(3 downto 0) := "0101";
constant s7: std_logic_vector(3 downto 0) := "1001";
constant s5: std_logic_vector(3 downto 0) := "1101";
constant s4: std_logic_vector(3 downto 0) := "0001";
constant s2: std_logic_vector(3 downto 0) := "0110";
constant s3: std_logic_vector(3 downto 0) := "1100";
constant s6: std_logic_vector(3 downto 0) := "0111";
constant s8: std_logic_vector(3 downto 0) := "0011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s7; output <= "00";
elsif std_match(input, "10") then next_state <= s5; output <= "11";
elsif std_match(input, "11") then next_state <= s4; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s1; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "00";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "11";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s5; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 8cf34b8bfe5598505e290050eef1f5e1 | 0.564036 | 3.267293 | false | false | false | false |
caiopo/battleship-vhdl | src/contador_pontos.vhd | 1 | 1,002 | library IEEE;
use IEEE.Std_Logic_1164.all;
entity contador_pontos is
port (compara, user, cont_match, clock, reset: in std_logic;
ledred, ledgrn: out std_logic_vector(7 downto 0)
);
end contador_pontos;
architecture behv of contador_pontos is
signal tempLedRed, tempLedGrn: std_logic_vector(7 downto 0);
begin
process(clock, reset)
begin
if (reset = '0') then
-- reset assincrono
tempLedRed <= "00000000";
tempLedGrn <= "00000000";
elsif rising_edge(clock) and (cont_match = '1') and (compara = '1') then
-- se o match e o enable do comparador estiverem em 1, desloca os pontos do jogador para a esquerda e adiciona um ponto no final
if user = '0' then
tempLedRed(7 downto 1) <= tempLedRed(6 downto 0);
tempLedRed(0) <= '1';
else
tempLedGrn(7 downto 1) <= tempLedGrn(6 downto 0);
tempLedGrn(0) <= '1';
end if;
end if;
ledred <= tempLedRed;
ledgrn <= tempLedGrn;
end process;
end behv; | mit | b5eeaa69da9a627b8b027c48f4e34cd6 | 0.641717 | 3.02719 | false | false | false | false |
chastell/art-decomp | kiss/bbsse_hot.vhd | 1 | 7,216 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_hot;
architecture behaviour of bbsse_hot is
constant st0: std_logic_vector(15 downto 0) := "1000000000000000";
constant st1: std_logic_vector(15 downto 0) := "0100000000000000";
constant st11: std_logic_vector(15 downto 0) := "0010000000000000";
constant st4: std_logic_vector(15 downto 0) := "0001000000000000";
constant st2: std_logic_vector(15 downto 0) := "0000100000000000";
constant st3: std_logic_vector(15 downto 0) := "0000010000000000";
constant st5: std_logic_vector(15 downto 0) := "0000001000000000";
constant st6: std_logic_vector(15 downto 0) := "0000000100000000";
constant st7: std_logic_vector(15 downto 0) := "0000000010000000";
constant st8: std_logic_vector(15 downto 0) := "0000000001000000";
constant st9: std_logic_vector(15 downto 0) := "0000000000100000";
constant st10: std_logic_vector(15 downto 0) := "0000000000010000";
constant st12: std_logic_vector(15 downto 0) := "0000000000001000";
constant st13: std_logic_vector(15 downto 0) := "0000000000000100";
constant st14: std_logic_vector(15 downto 0) := "0000000000000010";
constant st15: std_logic_vector(15 downto 0) := "0000000000000001";
signal current_state, next_state: std_logic_vector(15 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------------"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "0------") then next_state <= st0; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010";
end if;
when st1 =>
if std_match(input, "100----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st2 =>
if std_match(input, "10-----") then next_state <= st3; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st4 =>
if std_match(input, "10-----") then next_state <= st5; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10---0-") then next_state <= st6; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st8; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10---0-") then next_state <= st8; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st10 =>
if std_match(input, "1001---") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st11 =>
if std_match(input, "0----0-") then next_state <= st11; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0";
end if;
when st12 =>
if std_match(input, "11-----") then next_state <= st12; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when others => next_state <= "----------------"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | ca244589a80a80ad2917d859630136d6 | 0.572201 | 3.434555 | false | false | false | false |
chastell/art-decomp | kiss/bbsse_jed.vhd | 1 | 6,983 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_jed;
architecture behaviour of bbsse_jed is
constant st0: std_logic_vector(3 downto 0) := "0010";
constant st1: std_logic_vector(3 downto 0) := "0011";
constant st11: std_logic_vector(3 downto 0) := "1011";
constant st4: std_logic_vector(3 downto 0) := "1001";
constant st2: std_logic_vector(3 downto 0) := "0001";
constant st3: std_logic_vector(3 downto 0) := "0000";
constant st5: std_logic_vector(3 downto 0) := "1000";
constant st6: std_logic_vector(3 downto 0) := "1111";
constant st7: std_logic_vector(3 downto 0) := "1110";
constant st8: std_logic_vector(3 downto 0) := "1101";
constant st9: std_logic_vector(3 downto 0) := "0101";
constant st10: std_logic_vector(3 downto 0) := "0111";
constant st12: std_logic_vector(3 downto 0) := "1010";
constant st13: std_logic_vector(3 downto 0) := "1100";
constant st14: std_logic_vector(3 downto 0) := "0100";
constant st15: std_logic_vector(3 downto 0) := "0110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "0------") then next_state <= st0; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010";
end if;
when st1 =>
if std_match(input, "100----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st2 =>
if std_match(input, "10-----") then next_state <= st3; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st4 =>
if std_match(input, "10-----") then next_state <= st5; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10---0-") then next_state <= st6; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st8; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10---0-") then next_state <= st8; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st10 =>
if std_match(input, "1001---") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st11 =>
if std_match(input, "0----0-") then next_state <= st11; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0";
end if;
when st12 =>
if std_match(input, "11-----") then next_state <= st12; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
| agpl-3.0 | e791d8f12ee17a8714c7c492a55ca99d | 0.561363 | 3.323655 | false | false | false | false |
chastell/art-decomp | kiss/s820_rnd.vhd | 1 | 29,266 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s820_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s820_rnd;
architecture behaviour of s820_rnd is
constant s00000: std_logic_vector(4 downto 0) := "11101";
constant s01110: std_logic_vector(4 downto 0) := "00010";
constant s10000: std_logic_vector(4 downto 0) := "11011";
constant s10001: std_logic_vector(4 downto 0) := "11110";
constant s01111: std_logic_vector(4 downto 0) := "11111";
constant s00010: std_logic_vector(4 downto 0) := "10001";
constant s00001: std_logic_vector(4 downto 0) := "10110";
constant s00100: std_logic_vector(4 downto 0) := "01011";
constant s00011: std_logic_vector(4 downto 0) := "01111";
constant s00101: std_logic_vector(4 downto 0) := "00001";
constant s00110: std_logic_vector(4 downto 0) := "10000";
constant s11111: std_logic_vector(4 downto 0) := "11010";
constant s10111: std_logic_vector(4 downto 0) := "11000";
constant s01011: std_logic_vector(4 downto 0) := "01000";
constant s00111: std_logic_vector(4 downto 0) := "00100";
constant s11000: std_logic_vector(4 downto 0) := "01001";
constant s11011: std_logic_vector(4 downto 0) := "00110";
constant s11001: std_logic_vector(4 downto 0) := "11100";
constant s11010: std_logic_vector(4 downto 0) := "00011";
constant s11100: std_logic_vector(4 downto 0) := "10111";
constant s01100: std_logic_vector(4 downto 0) := "10011";
constant s01101: std_logic_vector(4 downto 0) := "10010";
constant s01000: std_logic_vector(4 downto 0) := "00111";
constant s01001: std_logic_vector(4 downto 0) := "01100";
constant s01010: std_logic_vector(4 downto 0) := "10101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000000000000110000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000100001";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000100000";
elsif std_match(input, "-0-1------------00") then next_state <= s00000; output <= "0000000001000100000";
elsif std_match(input, "-1--------------00") then next_state <= s10000; output <= "0000000000000110000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000100001";
elsif std_match(input, "-1--------------10") then next_state <= s10000; output <= "0000000000000110000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000010000000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000010000000000000";
end if;
when s01111 =>
if std_match(input, "----------------11") then next_state <= s00000; output <= "0000000100000100000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000100000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000100000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000100000100000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000000000110000000";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000000000111000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000000000010000000";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000000000110000000";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000000000111000000";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000000000010000000";
end if;
when s00100 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------10") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-11-1-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1011-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0-1--0-----110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----0-1--------010") then next_state <= s00100; output <= "0000000000000001000";
end if;
when s00001 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----1----111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----1-1--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----1-----0-1--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----011--111") then next_state <= s00000; output <= "0000000000000001100";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----0-0--111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------1----10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------1---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0------1----00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1------1----00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1------0-----0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0------0---010") then next_state <= s00110; output <= "0000000000000001000";
elsif std_match(input, "----0------0---000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0------01--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----001--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000000000000001100";
elsif std_match(input, "----0-----000--110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----000--100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----0-----100--100") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11111 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000000000001000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11000 =>
if std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "1000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000000000001000";
end if;
when s11001 =>
if std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "0100000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000000000001000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11010 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s11011 =>
if std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-0---------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-0---------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-10--------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-110-------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1110------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----001") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-1111-----011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----1-1") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-0--------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-0--------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-10-------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-110------110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1110-----110") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000000000001010";
elsif std_match(input, "----0-11-------010") then next_state <= s11011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s11100 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01100 =>
if std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0010100000000000000";
elsif std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0010100000000000000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0001100000000000000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0001100000000000000";
end if;
when s01101 =>
if std_match(input, "-1---------------0") then next_state <= s10000; output <= "0000001010000010000";
elsif std_match(input, "-1---------------1") then next_state <= s00000; output <= "0000001010000010000";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0000001010000000000";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0000001010000000000";
elsif std_match(input, "-0-0-------------1") then next_state <= s00000; output <= "0000001010000000000";
elsif std_match(input, "-0-1--------------") then next_state <= s00000; output <= "0000001010000000000";
end if;
when s10000 =>
if std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
elsif std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s01011 =>
if std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001010";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000000000001010";
elsif std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
end if;
when s00111 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000000000001000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01000 =>
if std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "1000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "1000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000000000001001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s01001 =>
if std_match(input, "----0----------101") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0100000000000001000";
elsif std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0100000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "0100000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0100000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0100000000000001001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000000000001001";
end if;
when s01010 =>
if std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000000000001000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000000000001000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000000000001001";
end if;
when s00011 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000000000001000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000000000001001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000000000001000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000000000001001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000000000001001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000000000001000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000000000001001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
| agpl-3.0 | 81eb59765b1054e7dcff6268372840e4 | 0.582075 | 4.157102 | false | false | false | false |
thommyj/slotcar | de0/spi.vhd | 1 | 5,069 | --*****************************************************************************
--* Copyright (c) 2012 by Michael Fischer. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity spi is
port(
clk : in std_logic;
rst : in std_logic;
SS_async : in std_logic;
SCLK_async : in std_logic;
MOSI_async : in std_logic;
MISO_async : out std_logic;
data_out : buffer std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out_valid : buffer std_logic
-- data_in_valid : in std_logic
);
end entity spi;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of spi is
--
-- Define all local signals (like static data) here
--
signal data_to_send : std_logic_vector(7 downto 0) := (others => '0');
signal SCLK_saved : std_logic;
signal SCLK_delayed : std_logic := '0';
signal SCLK : std_logic := '0';
signal receive_cnt : integer := 0;
begin
--
-- remove metastabilty on SCLK
--
process(clk,rst)
begin
if rst = '1' then
SCLK <= '0';
SCLK_delayed <= '0';
elsif rising_edge(clk) then
SCLK <= SCLK_delayed;
SCLK_delayed <= SCLK_async;
end if;
end process;
--
-- shift in values from RPI when up flank is detected on SCLK
-- shift out values to RPI when down flank is detected on SCLK
--
process(clk,rst)
begin
if rst = '1' then
SCLK_saved <= '0';
receive_cnt <= 0;
elsif rising_edge(clk) then
if(receive_cnt = 8) then
receive_cnt <= 0;
end if;
if(SCLK_saved = '0' and SCLK = '1') then -- Sample Time (Up Flank)
if(SS_async = '0') then
data_out(0) <= MOSI_async;
data_out(7 downto 1) <= data_out(6 downto 0);
receive_cnt <= receive_cnt + 1;
end if;
elsif(SCLK_saved = '1' and SCLK = '0') then -- (Down Flank)
if(SS_async = '0') then
MISO_async <= data_to_send(7-receive_cnt);
end if;
elsif(receive_cnt = 0) then
MISO_async <= data_to_send(7);
end if;
SCLK_saved <= SCLK;
end if;
end process;
--
-- clock new data in from decoder when valid is high
--
--process(clk,rst)
--begin
--if rst='1' then
--data_to_send <= x"F0";
--elsif rising_edge(clk) then
-- if(data_out_valid = '1') then
data_to_send <= data_in;
--end if;
--end if;
--end process;
data_out_valid <= '1' when receive_cnt=8 else
'0';
end architecture syn;
-- *** EOF ***
| mit | 5eb15b5e701932e61e8869f556d9fe4f | 0.526337 | 4.000789 | false | false | false | false |
LucasMahieu/TP_secu | code/AES/vhd/vhd/Sbox.vhd | 2 | 4,859 | -- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-- Component Declaration
entity sbox is port (
b_in : in std_logic_vector (7 downto 0);
ctrl_dec : T_ENCDEC;
clock, reset : in std_logic;
b_out : out std_logic_vector (7 downto 0) );
end sbox;
-- Architecture of the Component
architecture a_sbox of sbox is
component DDR_register is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 ); --
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end component;
component aff_trans port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end component;
component aff_trans_inv port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end component;
component gfmap port (
a : in std_logic_vector (7 downto 0);
ah, al : out std_logic_vector (3 downto 0));
end component;
component quadrato port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end component;
component x_e is port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0) );
end component;
component gf_molt is port (
a, b: in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end component;
component gf_inv is port (
a_in : std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end component;
component gfmapinv is port (
ah, al : in std_logic_vector (3 downto 0);
a : out std_logic_vector (7 downto 0) );
end component;
-- Internal Signal (4 std_logic)
signal ah, a1h, al, a1l, o, n, m, l, i, g, f,
p, p_hi, p_lo, q, d, d_hi, d_lo, r, r_hi, r_lo : std_logic_vector (3 downto 0);
-- Internal Signal (8 bit)
signal s, t, v, z : std_logic_vector (7 downto 0);
signal s_enc_buffer : T_ENCDEC;
begin
-- Affine Trasnformation
gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
v <= b_in;
end generate;
gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate
ati:aff_trans_inv port map (b_in, s);
v <= s when (ctrl_dec = C_DEC) else b_in;
end generate;
-- Map
mp:gfmap port map (v, ah, al);
-- First Square
qua1:quadrato port map (ah, o);
-- Second Square
qua2:quadrato port map (al, n);
-- X [e]
xe:x_e port map (o, m);
-- First Moltiplicator
molt1:gf_molt port map (ah, al, l);
f <= ah xor al;
i <= m xor n;
g <= i xor l;
-- Inverter
--inv:gf_inv port map (q, d);
inv:gf_inv port map (g, q);
temp_reg_p : DDR_register generic map ( SIZE=>4 )
port map( din_hi=>ah, din_lo=>ah, --dout=>p,
dout_hi=>p_hi, dout_lo=>p_lo,
rst=>reset, clk=>clock );
p <= p_hi when ( clock = '1' ) else p_lo;
--temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( g, q, reset, clock );
temp_reg_q : DDR_register generic map ( SIZE=>4 )
port map( din_hi=>q, din_lo=>q, --dout=>d,
dout_hi=>d_hi, dout_lo=>d_lo,
rst=>reset, clk=>clock );
d <= d_hi when ( clock = '1' ) else d_lo;
temp_reg_r : DDR_register generic map ( SIZE=>4 )
port map( din_hi=>f, din_lo=>f, --dout=>r,
dout_hi=>r_hi, dout_lo=>r_lo,
rst=>reset, clk=>clock );
r <= r_hi when ( clock = '1' ) else r_lo;
gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
s_enc_buffer <= C_ENC;
end generate; -- gen002e : if ( not C_INCLUDE_DECODING_LOGIC )
gen002d : if ( C_INCLUDE_DECODING_LOGIC ) generate
S_ENC_PROC : process( reset, clock )
begin
if ( reset=RESET_ACTIVE ) then
s_enc_buffer <= C_ENC;
elsif ( clock'event and clock='1' ) then
s_enc_buffer <= ctrl_dec;
end if;
end process S_ENC_PROC;
end generate; -- gen002d : if ( C_INCLUDE_DECODING_LOGIC )
-- Second Moltiplicator
molt2:gf_molt port map (p, d, a1h);
-- Third Moltiplicator
molt3:gf_molt port map (d, r, a1l);
-- Inverse Map
mapinv:gfmapinv port map (a1h, a1l, z);
-- Inverse Affine Transformation
at:aff_trans port map (z, t);
gen001e : if ( not C_INCLUDE_DECODING_LOGIC ) generate
b_out <= t;
end generate;
gen001d : if ( C_INCLUDE_DECODING_LOGIC ) generate
b_out <= z when ( s_enc_buffer=C_DEC ) else t;
end generate;
end a_sbox;
| mit | dc33cbc060dfae97d054cc59985ec774 | 0.547644 | 3.258887 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-01A-B.vhd | 1 | 11,838 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-01A-B.vhd
-- Creation Date:
-- Description:
-- WX register & indicators, CCROS parity check (5-01A), WX assembly (5-01B)
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.1 2012-04-07
-- Changes to PA check latch
-- Use T1 rather than P1 to latch WX
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
LIBRARY work;
USE work.Gates_package.all;
USE work.Buses_package.all;
-- This package implements the WX register and associated logic
-- Fig 5-01A, 5-01B
entity WX_Regs is
port (
-- Indicators
W_IND_P : OUT STD_LOGIC;
X_IND_P : OUT STD_LOGIC;
WX_IND : OUT STD_LOGIC_VECTOR(0 to 12);
-- CCROS interface
WX : OUT STD_LOGIC_VECTOR(0 to 12); -- 01BA5 01BA6 to 01CC1 04BD3
CROS_STROBE : OUT STD_LOGIC; -- 01BD2 to 01CC1
CROS_GO_PULSE : OUT STD_LOGIC; -- 01BD2 to 01CC1
SALS : IN SALS_Bus; -- 01C
-- Clock inputs
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
clk : IN STD_LOGIC;
-- Switch inputs
SWS_FGP,SWS_HJP : IN STD_LOGIC; -- 04CA3
SWS_F3: IN STD_LOGIC; -- 04CA3
SWS_G,SWS_H,SWS_J : IN STD_LOGIC_VECTOR(0 to 3); -- 04CA3
-- UV bus input
U_P : IN STD_LOGIC; -- 05CC3
U3_7: IN STD_LOGIC_VECTOR(3 to 7); -- 05CC3
V_P : IN STD_LOGIC; -- 05CC4
V : IN STD_LOGIC_VECTOR(0 to 7); -- 05CC4
-- Priority bus input
PRIORITY_BUS_P : IN STD_LOGIC; -- 03AE6
PRIORITY_BUS : IN STD_LOGIC_VECTOR(0 to 7); -- 03AE6
-- X6,7 inputs
X6,X7 : IN STD_LOGIC; -- 02AE6
-- Status inputs
ANY_MACH_CHK : IN STD_LOGIC; -- 07AD6
CHK_OR_DIAG_STOP_SW : IN STD_LOGIC; -- 04AE3
EARLY_ROAR_STOP : IN STD_LOGIC; -- 03CC6
MACH_START_RST : IN STD_LOGIC; -- 04AD3
ALU_CHK : IN STD_LOGIC; -- 06AE6
ALU_CHK_LCH : IN STD_LOGIC; -- 06BE6
MACH_RST_SET_LCH : IN STD_LOGIC; -- 04BB2
MACH_RST_SET_LCH_DLY : IN STD_LOGIC; -- 04BB2
USE_ALT_CU_DECODER : IN STD_LOGIC; -- 04DC2
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02AE6
GT_UV_TO_WX_REG : IN STD_LOGIC; -- 02BA2
GT_CA_TO_W_REG : IN STD_LOGIC; -- 02BA2
GT_FWX_TO_WX_REG,GT_GWX_TO_WX_REG : IN STD_LOGIC; -- 02AE4
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04AD6
GT_SWS_TO_WX_LCH : IN STD_LOGIC; -- 03AB2
ANY_PRIORITY_PULSE : IN STD_LOGIC; -- 03AD6
ANY_PRIORITY_PULSE_PWR : IN STD_LOGIC; -- 03AD6
INH_ROSAR_SET : IN STD_LOGIC; -- 03CD3
CHK_SW_PROC_SW : IN STD_LOGIC; -- 04AE2
ROS_SCAN : IN STD_LOGIC; -- 03CE2
MACH_RST_2A : IN STD_LOGIC; -- 06BC6
MACH_RST_4,MACH_RST_5 : IN STD_LOGIC; -- 03DD2
N1401_MODE : IN STD_LOGIC; -- 05AD5
CARRY_0_LCHD : IN STD_LOGIC; -- 06AE3
HSMPX_TRAP : IN STD_LOGIC; -- XXXXX
SX_CHAIN_PULSE : IN STD_LOGIC; -- 03AC6
SEL_CC_ROS_REQ : IN STD_LOGIC; -- 12CA6
MPX_SHARE_PULSE : IN STD_LOGIC; -- 03AC6
ALLOW_PC_SALS : IN STD_LOGIC; -- 07AC4
TEST_LAMP : IN STD_LOGIC; -- ?????
-- Debug
DEBUG : INOUT DEBUG_BUS;
-- Outputs
SET_IND_ROSAR : OUT STD_LOGIC; --- 01AB2 to 07AB3
CTRL_REG_CHK : OUT STD_LOGIC; -- 01AD5 to 01BD1,07AC4
WX_CHK : OUT STD_LOGIC; -- 01AB5 to 07AC3
SAL_PC : OUT STD_LOGIC; -- 01AC5 to 01BD1,07AC4
GT_BU_ROSAR_TO_WX_REG : OUT STD_LOGIC; -- 01BA2 to 02AE2
SET_FW : OUT STD_LOGIC -- 01BE3 to 08CA1
);
end WX_Regs;
architecture FMD of WX_Regs is
signal SET_IND : STD_LOGIC;
signal FL_ROSAR_IND : STD_LOGIC;
signal GT_CK_TO_W_REG : STD_LOGIC;
signal sGT_BU_ROSAR_TO_WX_REG : STD_LOGIC;
signal NORMAL_ENTRY : STD_LOGIC;
signal SET_W2,SET_W2A,SET_W2B,SET_W_REG : STD_LOGIC;
signal SET_X_REG : STD_LOGIC;
signal W_P : STD_LOGIC;
signal X_P : STD_LOGIC;
signal sSET_IND_ROSAR : STD_LOGIC;
signal sWX : STD_LOGIC_VECTOR(0 to 12);
signal sINH_NORM_ENTRY : STD_LOGIC;
signal sCTRL_REG_CHK : STD_LOGIC;
signal sSAL_PC : STD_LOGIC;
signal PA_LCH : STD_LOGIC;
-- WX display
signal WX_IND_X : STD_LOGIC_VECTOR(0 to 12);
signal W_IND_P_X, X_IND_P_X : STD_LOGIC;
-- New WX value
signal W_ASSM : STD_LOGIC_VECTOR(3 to 8); -- 8 is P
signal X_ASSM : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
-- Multiplexor backup ROSAR
signal FWX : STD_LOGIC_VECTOR(0 to 12);
alias FW : STD_LOGIC_VECTOR(3 to 7) is FWX(0 to 4);
alias FX : STD_LOGIC_VECTOR(0 to 7) is FWX(5 to 12);
signal FW_P : STD_LOGIC;
signal FX_P : STD_LOGIC;
signal SET_F : STD_LOGIC;
-- Selector backup ROSAR
signal GWX : STD_LOGIC_VECTOR(0 to 12);
alias GW : STD_LOGIC_VECTOR(3 to 7) is GWX(0 to 4);
alias GX : STD_LOGIC_VECTOR(0 to 7) is GWX(5 to 12);
signal GW_P : STD_LOGIC;
signal GX_P : STD_LOGIC;
signal SET_G : STD_LOGIC;
signal ROSAR_IND_LATCH_Set : STD_LOGIC;
signal PRIORITY_PARITY : STD_LOGIC;
BEGIN
-- Fig 5-01A
-- ROS Indicator register
ROSAR_IND_LATCH_Set <= (ANY_MACH_CHK and CHK_OR_DIAG_STOP_SW) or EARLY_ROAR_STOP;
ROSAR_IND_LATCH: entity work.FLL port map(ROSAR_IND_LATCH_Set,MACH_START_RST,FL_ROSAR_IND); -- AA3G4,AA3H4
sSET_IND_ROSAR <= (not ALU_CHK or not CHK_OR_DIAG_STOP_SW) and not FL_ROSAR_IND; -- AA3H4
-- sSET_IND_ROSAR <= '1'; -- Debug
SET_IND_ROSAR <= sSET_IND_ROSAR;
SET_IND <= (T4 and sSET_IND_ROSAR) or MACH_RST_SET_LCH; -- AA3J4
WINDP: entity work.PH port map(W_P,SET_IND,W_IND_P_X); -- AA3J2
W_IND_P <= W_IND_P_X or TEST_LAMP;
XINDP: entity work.PH port map(X_P,SET_IND,X_IND_P_X); -- AA3J3
X_IND_P <= X_IND_P_X or TEST_LAMP;
WXIND: entity work.PHV13 port map(sWX,SET_IND,WX_IND_X); -- AA3J2,AA3J3
WX_IND <= WX_IND_X or (WX_IND'range=>TEST_LAMP);
-- SALS parity checking
-- ?? I have added a latch (FL) on PA to hold it at T4, as are W_IND_P and X_IND_P
-- This keeps WX_CHK valid during T1, T2 and T3 - it is checked during T2 of the following cycle
-- Without this, spurious ROS_ADDR checks are generated because PA is not always valid at the next T2
PA_PH: entity work.PH port map(SALS.SALS_PA,T4,PA_LCH);
WX_CHK <= not(PA_LCH xor W_IND_P_X xor X_IND_P_X); -- AA2J4 ?? Inverted ??
sSAL_PC <= not EvenParity(USE_BASIC_CA_DECODER & SALS.SALS_AK & SALS.SALS_PK & SALS.SALS_CH & SALS.SALS_CL &
SALS.SALS_CM & SALS.SALS_CU & SALS.SALS_CA & SALS.SALS_CB & SALS.SALS_CK & SALS.SALS_PA & SALS.SALS_PS)
or
EvenParity(SALS.SALS_PN & SALS.SALS_CN);
SAL_PC <= sSAL_PC;
sCTRL_REG_CHK <= EvenParity(SALS.SALS_CD & SALS.SALS_SA & SALS.SALS_CS & SALS.SALS_CV & SALS.SALS_CC & SALS.SALS_CF & SALS.SALS_CG & SALS.SALS_PC);
CTRL_REG_CHK <= sCTRL_REG_CHK;
-- Fig 5-01B
-- W Reg assembly
PRIORITY_PARITY <= not N1401_MODE and not GT_SWS_TO_WX_LCH;
W_ASSM <= (
mux(GT_GWX_TO_WX_REG, GW & GW_P) or -- AA2G2
-- mux(ANY_PRIORITY_PULSE_PWR, (N1401_MODE & ROS_SCAN & '0' & (not GT_SWS_TO_WX_LCH and not N1401_MODE) & '0' & ROS_SCAN)) or -- AA2J2,AA2E3 ?? Sets W6 on restart ??
mux(ANY_PRIORITY_PULSE_PWR, (N1401_MODE & '0' & '0' & ROS_SCAN & ROS_SCAN & PRIORITY_PARITY)) or -- AA2J2,AA2E3 ?? See above for original version
mux(MACH_RST_2A,"00000" & not GT_SWS_TO_WX_LCH) or -- AA2F2,AA2E7 ?? See above
mux(GT_SWS_TO_WX_PWR, (SWS_F3 & SWS_G & SWS_FGP)) or -- AA2J2,AA2F2,AA2E3,AA2E2
mux(GT_UV_TO_WX_REG, U3_7 & U_P) or -- AA2J2,AA2F2,AA2E3,AA2E2
mux(GT_CK_TO_W_REG, (N1401_MODE & SALS.SALS_CK & SALS.SALS_PK)) or -- AA2J2,AA2F2,AA2E3,AA2E2
mux(GT_CA_TO_W_REG, (SALS.SALS_AA & SALS.SALS_CA & SALS.SALS_PK)) or -- AA2H2,AA2J2,AA2F2
mux(GT_FWX_TO_WX_REG, FW & FW_P)); -- AA2H2,AA2J2,AA2F2
-- X Reg assembly
sINH_NORM_ENTRY <= '1' when SALS.SALS_CK="0101" and SALS.SALS_AK='1' and CARRY_0_LCHD='1' else '0'; -- AB3H7,AA2F5 CK=0101 AK=1 ACFORCE
X_ASSM <= (
mux(GT_FWX_TO_WX_REG, FX & FX_P) or -- AA2G3
mux(ANY_PRIORITY_PULSE_PWR, PRIORITY_BUS & PRIORITY_BUS_P) or -- AA2G3
mux(GT_GWX_TO_WX_REG, GX & GX_P) or -- AA2G3
mux(GT_SWS_TO_WX_PWR, SWS_H & SWS_J & SWS_HJP) or -- AA2F3
mux(GT_UV_TO_WX_REG, V & V_P) or -- AA2F3
mux(NORMAL_ENTRY and not sINH_NORM_ENTRY, (SALS.SALS_CN & X6 & X7 & (SALS.SALS_PN xor X6 xor X7))) or -- AA2F3
mux(sINH_NORM_ENTRY, "000000001") or -- AA2H5 XP=1 for ACFORCE
mux(ANY_PRIORITY_PULSE_PWR and SEL_CC_ROS_REQ and SX_CHAIN_PULSE, "000000110") or -- AA2H3
mux(HSMPX_TRAP and SX_CHAIN_PULSE, "000001001") -- AA2E7
);
-- WX Reg loading
GT_CK_TO_W_REG <= '1' when USE_ALT_CU_DECODER='1' and SALS.SALS_CU="10" else '0'; -- AB3D6
sGT_BU_ROSAR_TO_WX_REG <= '1' when USE_ALT_CU_DECODER='1' and SALS.SALS_CU="11" else '0'; -- AB3D6
GT_BU_ROSAR_TO_WX_REG <= sGT_BU_ROSAR_TO_WX_REG;
NORMAL_ENTRY <= not sGT_BU_ROSAR_TO_WX_REG and not GT_UV_TO_WX_REG and not ANY_PRIORITY_PULSE; -- AA2C7
-- W_LATCH:
SET_W2A <= not ANY_PRIORITY_PULSE_PWR or not ALU_CHK_LCH or not CHK_SW_PROC_SW; -- AA2H5 ?? What does this do?
-- SET_W2A <= '1';
SET_W2B <= sGT_BU_ROSAR_TO_WX_REG or not NORMAL_ENTRY; -- AA2F2
SET_W2 <= SET_W2A and SET_W2B; -- AA2H5,AA2F2 Wired-AND
SET_W_REG <= ((GT_CA_TO_W_REG or GT_CK_TO_W_REG or SET_W2) and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ??
REG_W: entity work.PHV5 port map(W_ASSM(3 to 7),SET_W_REG,sWX(0 to 4)); -- AA2D2
REG_WP: entity work.PH port map(W_ASSM(8),SET_W_REG,W_P); -- AA2D2
-- X_LATCH:
SET_X_REG <= (not INH_ROSAR_SET and T1) or MACH_RST_SET_LCH_DLY; -- AA2D2 ?? P1 or T1 ??
REG_X: entity work.PHV8 port map(X_ASSM(0 to 7),SET_X_REG,sWX(5 to 12)); -- AA2D3
REG_XP: entity work.PH port map(X_ASSM(8),SET_X_REG,X_P); -- AA2D3
WX <= sWX;
-- Backup ROSAR regs
SET_F <= (MPX_SHARE_PULSE and T4) or MACH_RST_4; -- AA3G3
SET_FW <= SET_F;
FWX_LCH: entity work.PHV13 port map(sWX,SET_F,FWX); -- AA3H2,AA3H3
FWP_LCH: entity work.PH port map(W_P,SET_F,FW_P); -- AA3H2
FXP_LCH: entity work.PH port map(X_P,SET_F,FX_P); -- AA3H3
SET_G <= (SX_CHAIN_PULSE and T4) or MACH_RST_5; -- AA3K2
GWX_LCH: entity work.PHV13 port map(sWX,SET_G,GWX); -- AA2K5,AA2L2
GWP_LCH: entity work.PH port map(W_P,SET_G,GW_P); -- AA2K5
GXP_LCH: entity work.PH port map(X_P,SET_G,GX_P); -- AA2L2
-- CROS triggering
-- This is what the ALD shows:
-- CROS_GO_PULSE <= not (T2 and CHK_OR_DIAG_STOP_SW and ALLOW_PC_SALS and (sSAL_PC or sCTRL_REG_CHK)); -- AA2E7,AA2E2,AA2C2
-- This is what I think it should be
CROS_GO_PULSE <= T2 and not (CHK_OR_DIAG_STOP_SW and ALLOW_PC_SALS and (sSAL_PC or sCTRL_REG_CHK)); -- AA2E7,AA2E2,AA2C2 ??
CROS_STROBE <= T3; -- AA3L6
with DEBUG.SELECTION select
DEBUG.PROBE <=
FWX(0) when 0,
FWX(1) when 1,
FWX(2) when 2,
FWX(3) when 3,
FWX(4) when 4,
FWX(5) when 5,
FWX(6) when 6,
FWX(7) when 7,
FWX(8) when 8,
FWX(9) when 9,
FWX(10) when 10,
FWX(11) when 11,
FWX(12) when 12,
FW_P when 13,
FX_P when 14,
MPX_SHARE_PULSE when 15;
end FMD;
| gpl-3.0 | 5bd900097bd5eb6b53a0dac8cc10922b | 0.641409 | 2.450932 | false | false | false | false |
chastell/art-decomp | spec/fixtures/fsm.vhd | 1 | 2,612 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity fsm is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end fsm;
architecture behaviour of fsm is
type state is (init0, init1, init2, init4, IOwait, RMACK, WMACK, read0, read1, write0);
signal current_state, next_state: state;
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= init0; output <= "--";
case current_state is
when init0 =>
if std_match(input, "--00") then next_state <= init1; output <= "00";
end if;
when init1 =>
if std_match(input, "0100") then next_state <= init1; output <= "00";
elsif std_match(input, "--1-") then next_state <= init2; output <= "10";
end if;
when init2 =>
if std_match(input, "1-10") then next_state <= init4; output <= "10";
end if;
when init4 =>
if std_match(input, "-111") then next_state <= init4; output <= "10";
elsif std_match(input, "--01") then next_state <= IOwait; output <= "01";
end if;
when IOwait =>
if std_match(input, "000-") then next_state <= IOwait; output <= "01";
elsif std_match(input, "100-") then next_state <= init1; output <= "01";
elsif std_match(input, "0110") then next_state <= read0; output <= "00";
elsif std_match(input, "1100") then next_state <= write0; output <= "11";
elsif std_match(input, "0111") then next_state <= RMACK; output <= "11";
elsif std_match(input, "1101") then next_state <= WMACK; output <= "00";
elsif std_match(input, "-01-") then next_state <= init2; output <= "01";
end if;
when RMACK =>
if std_match(input, "0010") then next_state <= RMACK; output <= "11";
elsif std_match(input, "0111") then next_state <= read0; output <= "00";
end if;
when WMACK =>
if std_match(input, "1100") then next_state <= WMACK; output <= "00";
elsif std_match(input, "1001") then next_state <= write0; output <= "01";
end if;
when read0 =>
if std_match(input, "0001") then next_state <= read1; output <= "11";
end if;
when read1 =>
if std_match(input, "0010") then next_state <= IOwait; output <= "01";
end if;
when write0 =>
if std_match(input, "0100") then next_state <= IOwait; output <= "01";
end if;
end case;
end process;
end behaviour;
| agpl-3.0 | b2b50cc4a9bcb4863db20fbfcc9c2909 | 0.578867 | 3.427822 | false | false | false | false |
es17m014/vhdl-counter | src/vhdl/gen_debouncer.vhd | 1 | 1,546 | -- --------------------------------------------------------------
-- Title : Debounce Logic
-- Project : Counter
-- -------- ------------------------------------------------------
-- File : gen_debouncer.vhd
-- Author : Martin Angermair
-- Company : FH Technikum Wien
-- Last update : 31.10.2017
-- Standard : VHDL'87
-- --------------------------------------------------------------
-- Description : Debounce input signals from switches and buttons
-- --------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 31.10.2017 1.0 Martin Angermair
-- --------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture rtl of gen_debouncer is
signal s_delay1 : std_logic_vector(N-1 downto 0); -- delay signal between ff1 and ff2
signal s_delay2 : std_logic_vector(N-1 downto 0); -- delay signal between ff2 and ff2
signal s_delay3 : std_logic_vector(N-1 downto 0); -- delay signal between ff3 and and gatter
begin
process(clk_i, reset_i)
begin
if reset_i = '1' then
s_delay1 <= (others => '0');
s_delay2 <= (others => '0');
s_delay3 <= (others => '0');
elsif rising_edge(clk_i) then
s_delay1 <= data_i;
s_delay2 <= s_delay1;
s_delay3 <= s_delay2;
end if;
end process;
q_o <= s_delay1 and s_delay2 and s_delay3;
end rtl;
| mit | defa5e01cf57139649e7ebee0a388824 | 0.466365 | 3.90404 | false | false | false | false |
mike7c2/befunge_processor | befunge_pc_v2.vhd | 1 | 2,764 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_pc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
--PC outputs x and y coordinates to read from grid
--dir input affects PC incrementing, it denotes the direction of execution in befunge_pc
--skip increments the pc twice to avoid a cell
--en, so that the operation of the pc can be clocked
entity befunge_pc_v2 is
generic(
grid_power : integer
);
port(
clk : in std_logic;
reset : in std_logic;
pc_address : out std_logic_vector((grid_power * 2)-1 downto 0);
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end befunge_pc_v2;
--dir:
--0 = right
--1 = down
--2 = left
--3 = up
architecture pc_v1 of befunge_pc_v2 is
signal pc_address_int : std_logic_vector((grid_power * 2)-1 downto 0);
signal pc_row : std_logic_vector(grid_power-1 downto 0);
signal pc_col : std_logic_vector(grid_power-1 downto 0);
begin
pc_address((grid_power * 2)-1 downto ((grid_power*2)/2)) <= pc_col;
pc_address(((grid_power * 2)/2)-1 downto 0) <= pc_row;
process(reset,clk)
variable increment : integer range 1 to 2;
begin
if(reset = '1') then
pc_address_int <= (others => '0');
pc_row <= (others => '0');
pc_col <= (others => '0');
increment := 1;
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( skip = '1' ) then
increment := 2;
else
increment := 1;
end if;
if ( dir = "00" ) then --move right: add 1
pc_row <= std_logic_vector((unsigned(pc_row) + increment));
elsif ( dir = "01" ) then --move up: subtract grid_width
pc_col <= std_logic_vector((unsigned(pc_col) - increment));
elsif ( dir = "10" ) then --move left: subtract 1
pc_row <= std_logic_vector((unsigned(pc_row) - increment));
elsif (dir = "11") then --move down: add grid_width
pc_col <= std_logic_vector((unsigned(pc_col) + increment));
else --do nothing, laaaatchhh!!!!
end if;
end if;
end if;
end if;
end process;
end pc_v1;
| unlicense | f88b4161c317bef8dd5a327107ece579 | 0.512301 | 3.534527 | false | false | false | false |
chastell/art-decomp | spec/fixtures/mark1_nov.vhd | 2 | 4,356 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_nov;
architecture behaviour of mark1_nov is
constant state1: std_logic_vector(3 downto 0) := "0100";
constant state2: std_logic_vector(3 downto 0) := "1000";
constant state3: std_logic_vector(3 downto 0) := "1011";
constant state4: std_logic_vector(3 downto 0) := "1100";
constant state5: std_logic_vector(3 downto 0) := "0001";
constant state6: std_logic_vector(3 downto 0) := "0011";
constant state7: std_logic_vector(3 downto 0) := "0000";
constant state8: std_logic_vector(3 downto 0) := "0010";
constant state9: std_logic_vector(3 downto 0) := "1101";
constant state10: std_logic_vector(3 downto 0) := "1010";
constant state11: std_logic_vector(3 downto 0) := "0111";
constant state12: std_logic_vector(3 downto 0) := "1001";
constant state13: std_logic_vector(3 downto 0) := "0101";
constant state14: std_logic_vector(3 downto 0) := "0110";
constant state0: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "----------------";
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
else
case current_state is
when state1 =>
if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
end if;
when state2 =>
if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
end if;
when state3 =>
if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
end if;
when state4 =>
if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
end if;
when state5 =>
if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
end if;
when state6 =>
if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
end if;
when state7 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
end if;
when state8 =>
if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
end if;
when state9 =>
if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
end if;
when state10 =>
if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
end if;
when state11 =>
if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
end if;
when state12 =>
if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
end if;
when state13 =>
if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
end if;
when state14 =>
if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
end if;
when state0 =>
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
end if;
when others => next_state <= "----"; output <= "----------------";
end case;
end if;
end process;
end behaviour;
| agpl-3.0 | 3390a9a74cde66b2f89d11265b4b8de2 | 0.557622 | 3.424528 | false | false | false | false |
chastell/art-decomp | kiss/dk512_hot.vhd | 1 | 4,742 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk512_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk512_hot;
architecture behaviour of dk512_hot is
constant state_1: std_logic_vector(14 downto 0) := "100000000000000";
constant state_8: std_logic_vector(14 downto 0) := "010000000000000";
constant state_2: std_logic_vector(14 downto 0) := "001000000000000";
constant state_4: std_logic_vector(14 downto 0) := "000100000000000";
constant state_3: std_logic_vector(14 downto 0) := "000010000000000";
constant state_5: std_logic_vector(14 downto 0) := "000001000000000";
constant state_6: std_logic_vector(14 downto 0) := "000000100000000";
constant state_13: std_logic_vector(14 downto 0) := "000000010000000";
constant state_7: std_logic_vector(14 downto 0) := "000000001000000";
constant state_9: std_logic_vector(14 downto 0) := "000000000100000";
constant state_10: std_logic_vector(14 downto 0) := "000000000010000";
constant state_11: std_logic_vector(14 downto 0) := "000000000001000";
constant state_12: std_logic_vector(14 downto 0) := "000000000000100";
constant state_14: std_logic_vector(14 downto 0) := "000000000000010";
constant state_15: std_logic_vector(14 downto 0) := "000000000000001";
signal current_state, next_state: std_logic_vector(14 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---------------"; output <= "---";
case current_state is
when state_1 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_9; output <= "000";
end if;
when state_2 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "000";
end if;
when state_3 =>
if std_match(input, "0") then next_state <= state_5; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when state_4 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_11; output <= "000";
end if;
when state_5 =>
if std_match(input, "0") then next_state <= state_8; output <= "000";
elsif std_match(input, "1") then next_state <= state_12; output <= "000";
end if;
when state_6 =>
if std_match(input, "0") then next_state <= state_13; output <= "000";
elsif std_match(input, "1") then next_state <= state_14; output <= "000";
end if;
when state_7 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_15; output <= "000";
end if;
when state_8 =>
if std_match(input, "0") then next_state <= state_1; output <= "001";
elsif std_match(input, "1") then next_state <= state_2; output <= "001";
end if;
when state_9 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_10 =>
if std_match(input, "0") then next_state <= state_1; output <= "010";
elsif std_match(input, "1") then next_state <= state_2; output <= "010";
end if;
when state_11 =>
if std_match(input, "0") then next_state <= state_3; output <= "010";
elsif std_match(input, "1") then next_state <= state_4; output <= "010";
end if;
when state_12 =>
if std_match(input, "0") then next_state <= state_4; output <= "100";
elsif std_match(input, "1") then next_state <= state_3; output <= "001";
end if;
when state_13 =>
if std_match(input, "0") then next_state <= state_5; output <= "100";
elsif std_match(input, "1") then next_state <= state_6; output <= "100";
end if;
when state_14 =>
if std_match(input, "0") then next_state <= state_3; output <= "100";
elsif std_match(input, "1") then next_state <= state_7; output <= "100";
end if;
when state_15 =>
if std_match(input, "0") then next_state <= state_4; output <= "000";
elsif std_match(input, "1") then next_state <= state_6; output <= "000";
end if;
when others => next_state <= "---------------"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | ec6cbcc67a169a8feebc8ccb639dd3c5 | 0.595529 | 3.391989 | false | false | false | false |
TheMassController/VHDL_experimenting | project/bus/bus_singleport_ram.vhd | 1 | 3,136 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
entity bus_singleport_ram is
generic (
DEPTH_LOG2B : natural range bus_bytes_per_word_log2b to 11
);
port (
rst : in std_logic;
clk : in std_logic;
mst2mem : in bus_mst2slv_type;
mem2mst : out bus_slv2mst_type
);
end bus_singleport_ram;
architecture Behavioral of bus_singleport_ram is
constant word_count : natural := 2**(DEPTH_LOG2B - bus_bytes_per_word_log2b);
constant byte_count : natural := 2**DEPTH_LOG2B;
signal ram : bus_byte_array(0 to byte_count - 1);
signal mem2mst_out : bus_slv2mst_type := BUS_SLV2MST_IDLE;
begin
sequential: process(clk, rst, mst2mem) is
variable b : natural range 0 to bus_bytes_per_word - 1 := 0;
variable wait_for_completion : boolean := false;
variable active : boolean := false;
variable ramb_addr : std_logic_vector(DEPTH_LOG2B - 1 downto 0) := (others => '0');
variable ramb_data_out : std_logic_vector(7 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
wait_for_completion := false;
b := 0;
mem2mst_out <= BUS_SLV2MST_IDLE;
elsif wait_for_completion then
if bus_requesting(mst2mem) = '0' then
b := 0;
mem2mst_out.ack <= '0';
mem2mst_out.fault <= '0';
wait_for_completion := false;
end if;
elsif active then
mem2mst_out.readData((b+1)*bus_byte_size - 1 downto b*bus_byte_size) <= ramb_data_out;
if b = bus_bytes_per_word - 1 then
mem2mst_out.ack <= '1';
wait_for_completion := true;
active := false;
else
b := b + 1;
end if;
elsif bus_requesting(mst2mem) = '1' then
if unsigned(mst2mem.address(bus_bytes_per_word_log2b - 1 downto 0)) /= 0 then
mem2mst_out.fault <= '1';
wait_for_completion := true;
else
active := true;
end if;
end if;
ramb_addr(bus_bytes_per_word_log2b - 1 downto 0) := std_logic_vector(to_unsigned(b, bus_bytes_per_word_log2b));
ramb_addr(DEPTH_LOG2B - 1 downto bus_bytes_per_word_log2b) := mst2mem.address(DEPTH_LOG2B - 1 downto bus_bytes_per_word_log2b);
if active then
if (mst2mem.writeEnable and mst2mem.writeMask(b)) = '1' then
ram(to_integer(unsigned(ramb_addr))) <= mst2mem.writeData(b*bus_byte_size + (bus_byte_size - 1) downto b*bus_byte_size);
end if;
ramb_data_out := ram(to_integer(unsigned(ramb_addr)));
end if;
end if;
end process;
concurrent: process(mem2mst_out) is
begin
mem2mst <= mem2mst_out;
end process;
end Behavioral;
| mit | 2a115c41037153eb4576f11f90038078 | 0.52838 | 3.625434 | false | false | false | false |
chastell/art-decomp | kiss/dk17_hot.vhd | 1 | 4,184 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk17_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk17_hot;
architecture behaviour of dk17_hot is
constant s10000000: std_logic_vector(7 downto 0) := "10000000";
constant s01000000: std_logic_vector(7 downto 0) := "01000000";
constant s00100000: std_logic_vector(7 downto 0) := "00100000";
constant s00010000: std_logic_vector(7 downto 0) := "00010000";
constant s00001000: std_logic_vector(7 downto 0) := "00001000";
constant s00000100: std_logic_vector(7 downto 0) := "00000100";
constant s00000010: std_logic_vector(7 downto 0) := "00000010";
constant s00000001: std_logic_vector(7 downto 0) := "00000001";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "---";
case current_state is
when s10000000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s00010000; output <= "010";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s00001000; output <= "010";
end if;
when s01000000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00000100; output <= "000";
end if;
when s00100000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00010000 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "101";
elsif std_match(input, "10") then next_state <= s00010000; output <= "010";
elsif std_match(input, "11") then next_state <= s00001000; output <= "101";
end if;
when s00001000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000100 =>
if std_match(input, "00") then next_state <= s00000010; output <= "000";
elsif std_match(input, "01") then next_state <= s00000001; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000010 =>
if std_match(input, "00") then next_state <= s00010000; output <= "010";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s00001000; output <= "010";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00000001 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when others => next_state <= "--------"; output <= "---";
end case;
end process;
end behaviour;
| agpl-3.0 | b54ff2a2bc618f06b2f7fa5672622320 | 0.612094 | 3.521886 | false | false | false | false |
chastell/art-decomp | kiss/sand_hot.vhd | 1 | 21,657 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sand_hot is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(8 downto 0)
);
end sand_hot;
architecture behaviour of sand_hot is
constant st0: std_logic_vector(31 downto 0) := "10000000000000000000000000000000";
constant st5: std_logic_vector(31 downto 0) := "01000000000000000000000000000000";
constant st1: std_logic_vector(31 downto 0) := "00100000000000000000000000000000";
constant st2: std_logic_vector(31 downto 0) := "00010000000000000000000000000000";
constant st4: std_logic_vector(31 downto 0) := "00001000000000000000000000000000";
constant st3: std_logic_vector(31 downto 0) := "00000100000000000000000000000000";
constant st31: std_logic_vector(31 downto 0) := "00000010000000000000000000000000";
constant st25: std_logic_vector(31 downto 0) := "00000001000000000000000000000000";
constant st19: std_logic_vector(31 downto 0) := "00000000100000000000000000000000";
constant st6: std_logic_vector(31 downto 0) := "00000000010000000000000000000000";
constant st29: std_logic_vector(31 downto 0) := "00000000001000000000000000000000";
constant st23: std_logic_vector(31 downto 0) := "00000000000100000000000000000000";
constant st17: std_logic_vector(31 downto 0) := "00000000000010000000000000000000";
constant st13: std_logic_vector(31 downto 0) := "00000000000001000000000000000000";
constant st27: std_logic_vector(31 downto 0) := "00000000000000100000000000000000";
constant st21: std_logic_vector(31 downto 0) := "00000000000000010000000000000000";
constant st15: std_logic_vector(31 downto 0) := "00000000000000001000000000000000";
constant st12: std_logic_vector(31 downto 0) := "00000000000000000100000000000000";
constant st10: std_logic_vector(31 downto 0) := "00000000000000000010000000000000";
constant st7: std_logic_vector(31 downto 0) := "00000000000000000001000000000000";
constant st8: std_logic_vector(31 downto 0) := "00000000000000000000100000000000";
constant st9: std_logic_vector(31 downto 0) := "00000000000000000000010000000000";
constant st11: std_logic_vector(31 downto 0) := "00000000000000000000001000000000";
constant st14: std_logic_vector(31 downto 0) := "00000000000000000000000100000000";
constant st16: std_logic_vector(31 downto 0) := "00000000000000000000000010000000";
constant st18: std_logic_vector(31 downto 0) := "00000000000000000000000001000000";
constant st20: std_logic_vector(31 downto 0) := "00000000000000000000000000100000";
constant st22: std_logic_vector(31 downto 0) := "00000000000000000000000000010000";
constant st24: std_logic_vector(31 downto 0) := "00000000000000000000000000001000";
constant st26: std_logic_vector(31 downto 0) := "00000000000000000000000000000100";
constant st28: std_logic_vector(31 downto 0) := "00000000000000000000000000000010";
constant st30: std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(31 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------------------"; output <= "---------";
case current_state is
when st0 =>
if std_match(input, "---------0-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----0----1-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----1---11-") then next_state <= st5; output <= "011001000";
elsif std_match(input, "----1---01-") then next_state <= st1; output <= "11-001000";
end if;
when st1 =>
if std_match(input, "0000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0100---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0100---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0101---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0101---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0110---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0110---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0111---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0111---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1100---0---") then next_state <= st4; output <= "1010-0100";
elsif std_match(input, "1101---0---") then next_state <= st3; output <= "0000-0110";
elsif std_match(input, "1111--10---") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "1111--00---") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st2 =>
if std_match(input, "-------0-0-") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "-------0-10") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----0-00-11") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "----1-00-11") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "------10-11") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st3 =>
if std_match(input, "------10--1") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-----010--0") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "-----110--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "------00--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st4 =>
if std_match(input, "------10-00") then next_state <= st4; output <= "0000-0000";
elsif std_match(input, "------10-01") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "------00-00") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st4; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st3; output <= "11-0-0000";
elsif std_match(input, "------10-1-") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0---00";
end if;
when st5 =>
if std_match(input, "0000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0000-----1-") then next_state <= st31; output <= "010110100";
elsif std_match(input, "0001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0001-----1-") then next_state <= st25; output <= "010110100";
elsif std_match(input, "0010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0010-----1-") then next_state <= st19; output <= "010110100";
elsif std_match(input, "0011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "0100-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0100-----1-") then next_state <= st29; output <= "010110100";
elsif std_match(input, "0101-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0101-----1-") then next_state <= st23; output <= "010110100";
elsif std_match(input, "0110-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0110-----1-") then next_state <= st17; output <= "010110100";
elsif std_match(input, "0111-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0111-----1-") then next_state <= st13; output <= "010110100";
elsif std_match(input, "1000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1000-----1-") then next_state <= st27; output <= "010110100";
elsif std_match(input, "1001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1001-----1-") then next_state <= st21; output <= "010110100";
elsif std_match(input, "1010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1010-----1-") then next_state <= st15; output <= "010110100";
elsif std_match(input, "1011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "1100-------") then next_state <= st12; output <= "101100100";
elsif std_match(input, "1101-------") then next_state <= st10; output <= "011100110";
elsif std_match(input, "1111-------") then next_state <= st7; output <= "011100000";
end if;
when st6 =>
if std_match(input, "----------0") then next_state <= st5; output <= "000100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "000101000";
elsif std_match(input, "----1-0---1") then next_state <= st7; output <= "011101000";
end if;
when st7 =>
if std_match(input, "-----1---1-") then next_state <= st8; output <= "100000000";
elsif std_match(input, "-----0---1-") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "---------0-") then next_state <= st7; output <= "000100000";
end if;
when st8 =>
if std_match(input, "0000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "00111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0110-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0111-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01110----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "10111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11000----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11010----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1111-------") then next_state <= st8; output <= "000000000";
end if;
when st9 =>
if std_match(input, "----------1") then next_state <= st8; output <= "001001000";
elsif std_match(input, "----------0") then next_state <= st8; output <= "000000000";
end if;
when st10 =>
if std_match(input, "------1--10") then next_state <= st11; output <= "---000010";
elsif std_match(input, "------1--00") then next_state <= st10; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st10; output <= "---101000";
end if;
when st11 =>
if std_match(input, "-----0-----") then next_state <= st11; output <= "---000000";
elsif std_match(input, "-----1-----") then next_state <= st5; output <= "011100000";
end if;
when st12 =>
if std_match(input, "------1--10") then next_state <= st5; output <= "001100000";
elsif std_match(input, "------1--00") then next_state <= st12; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st12; output <= "---101000";
end if;
when st13 =>
if std_match(input, "---------0-") then next_state <= st13; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st14; output <= "001100000";
end if;
when st14 =>
if std_match(input, "---------0-") then next_state <= st14; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st15; output <= "010110000";
end if;
when st15 =>
if std_match(input, "---------0-") then next_state <= st15; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st16; output <= "001100000";
end if;
when st16 =>
if std_match(input, "---------0-") then next_state <= st16; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st17; output <= "010110000";
end if;
when st17 =>
if std_match(input, "---------0-") then next_state <= st17; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st18; output <= "001100000";
end if;
when st18 =>
if std_match(input, "---------0-") then next_state <= st18; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st19; output <= "010110000";
end if;
when st19 =>
if std_match(input, "---------0-") then next_state <= st19; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st20; output <= "001100000";
end if;
when st20 =>
if std_match(input, "---------0-") then next_state <= st20; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st21; output <= "010110000";
end if;
when st21 =>
if std_match(input, "---------0-") then next_state <= st21; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st22; output <= "001100000";
end if;
when st22 =>
if std_match(input, "---------0-") then next_state <= st22; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st23; output <= "010110000";
end if;
when st23 =>
if std_match(input, "---------0-") then next_state <= st23; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st24; output <= "001100000";
end if;
when st24 =>
if std_match(input, "---------0-") then next_state <= st24; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st25; output <= "010110000";
end if;
when st25 =>
if std_match(input, "---------0-") then next_state <= st25; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st26; output <= "001100000";
end if;
when st26 =>
if std_match(input, "---------0-") then next_state <= st26; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st27; output <= "010110000";
end if;
when st27 =>
if std_match(input, "---------0-") then next_state <= st27; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st28; output <= "001100000";
end if;
when st28 =>
if std_match(input, "---------0-") then next_state <= st28; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st29; output <= "010110000";
end if;
when st29 =>
if std_match(input, "---------0-") then next_state <= st29; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st30; output <= "001100000";
end if;
when st30 =>
if std_match(input, "---------0-") then next_state <= st30; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st31; output <= "010110000";
end if;
when st31 =>
if std_match(input, "---------0-") then next_state <= st31; output <= "000110000";
elsif std_match(input, "---------10") then next_state <= st5; output <= "100100000";
elsif std_match(input, "------1--11") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "----0-0--11") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0--11") then next_state <= st7; output <= "011101000";
end if;
when others => next_state <= "--------------------------------"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | 9f5011d1019189823a62658a656ff0b8 | 0.577411 | 3.610102 | false | false | false | false |
ibm2030/IBM2030 | FMD2030_5-04C.vhd | 1 | 9,879 | ---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-04C.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- Manual Data (E switch) & C,F,H registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
-- Revision 1.01 2012-04-07
-- Fix typo in comment
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
ENTITY ManualDataCFH IS
port
(
-- Inputs
MACH_RST_PROT : IN STD_LOGIC; -- 07B
USE_MAN_DECO_PWR : IN STD_LOGIC; -- 03D
N60_CY_TIMER_PULSE : IN STD_LOGIC; -- 14A
L_REGISTER : IN STD_LOGIC_VECTOR(0 to 7); -- 05C
MACH_RST_SW : IN STD_LOGIC; -- 03D
EXT_TRAP_MASK_ON : IN STD_LOGIC; -- 08C
USE_MAN_DECODER, USE_MAN_DECODER_PWR : IN STD_LOGIC; -- 03D
USE_ALT_CA_DECODER : IN STD_LOGIC; -- 02B
USE_BASIC_CA_DECODER : IN STD_LOGIC; -- 02A
GTD_CA_BITS : IN STD_LOGIC_VECTOR(0 to 3); -- 05C
CK_SALS : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
GT_CK_DECO : IN STD_LOGIC; -- 03B
Z_BUS : IN STD_LOGIC_VECTOR(0 to 7);
Z_BUS_P : IN STD_LOGIC;
MACH_RST_2B : IN STD_LOGIC; -- 06B
MAN_STOR_PWR : IN STD_LOGIC; -- 03D
CD_CTRL_REG : IN STD_LOGIC_VECTOR(0 to 3); -- 01C
RECYCLE_RST : IN STD_LOGIC; -- 04A
-- Switches
SW_INTRP_TIMER : IN STD_LOGIC;
SW_CONS_INTRP : IN STD_LOGIC;
SW_A,SW_B,SW_C,SW_D,SW_F,SW_G,SW_H,SW_J : IN STD_LOGIC_VECTOR(0 to 3);
SW_AP,SW_BP,SW_CP,SW_DP,SW_FP,SW_GP,SW_HP,SW_JP : IN STD_LOGIC;
-- Outputs
ABCD_SW_BUS,FGHJ_SW_BUS : OUT STD_LOGIC_VECTOR(0 to 15);
AB_SW_P,CD_SW_P,FG_SW_P,HJ_SW_P : OUT STD_LOGIC;
IJ_SEL,UV_SEL : OUT STD_LOGIC;
TIMER_UPDATE : OUT STD_LOGIC; -- 02A
TIMER_UPDATE_OR_EXT_INT : OUT STD_LOGIC; -- 02A
EXT_INTRP : OUT STD_LOGIC; -- 02A
A_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
H_REG_BITS : OUT STD_LOGIC_VECTOR(0 to 7); -- 03B,03A
H_REG_P : OUT STD_LOGIC; -- 03B,03A
H_REG_6 : OUT STD_LOGIC;
H_REG_5_PWR : OUT STD_LOGIC; -- 02A,08B
GT_1050_TAGS : OUT STD_LOGIC; -- 10C
GT_1050_BUS : OUT STD_LOGIC; -- 10C
CD_REG_2 : OUT STD_LOGIC; -- 05C
-- E switch
E_SW : IN E_SW_BUS_Type;
DEBUG : INOUT DEBUG_BUS;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
clk : IN STD_LOGIC
);
END ManualDataCFH;
ARCHITECTURE FMD OF ManualDataCFH IS
signal RST_COUNTER : STD_LOGIC;
signal N10MSPULSE : STD_LOGIC;
signal BIN_DRIVE : STD_LOGIC;
signal CTRL_TRG : STD_LOGIC;
signal CTRL_LCH : STD_LOGIC;
signal CNTR_FULL : STD_LOGIC;
signal C_BINARY_CNTR : STD_LOGIC_VECTOR(4 to 7);
signal EXT_INT : STD_LOGIC;
signal RESET_F_REG : STD_LOGIC;
signal F_REGISTER : STD_LOGIC_VECTOR(0 to 7);
signal F_REGISTER_1A : STD_LOGIC;
signal SET_F_REG_0 : STD_LOGIC;
signal GT_C_TO_A_BUS : STD_LOGIC;
signal GT_F_TO_A : STD_LOGIC;
signal GT_H_TO_A : STD_LOGIC;
signal C_EXT_INT : STD_LOGIC_VECTOR(2 to 7);
signal H_SET : STD_LOGIC;
signal sTIMER_UPDATE : STD_LOGIC;
signal sH_REG_BITS : STD_LOGIC_VECTOR(0 to 7);
signal sH_REG_P : STD_LOGIC;
signal CTL_LCH_Set,CTL_LCH_Reset,CT_FF_Set,BD_FF_Set,EI_LCH_Set,EI_LCH_Reset,F0_LCH_Reset,F1_LCH_Set,F1A_LCH_Reset : STD_LOGIC;
signal F07_LCH_Reset,F07_LCH_Set : STD_LOGIC_VECTOR(0 to 7);
BEGIN
-- Fig 5-04C
-- Rotary switches ABCD and FGHJ
ABCD_SW_BUS <= SW_A & SW_B & SW_C & SW_D;
AB_SW_P <= SW_AP xnor SW_BP; -- AC1D2,AC1E3
CD_SW_P <= SW_CP xnor SW_DP; -- AC1D4,AC1E3,AC1D2
FGHJ_SW_BUS <= SW_F & SW_G & SW_H & SW_J;
FG_SW_P <= SW_FP xnor SW_GP; -- AC1D4,AC1E3,AC1D2
HJ_SW_P <= SW_HP xnor SW_JP; -- AC1D4,AC1E3,AC1D2
IJ_SEL <= '1' when (E_SW.I_SEL='1' or E_SW.J_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
UV_SEL <= '1' when (E_SW.U_SEL='1' or E_SW.V_SEL='1') and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
RST_COUNTER <= MACH_RST_PROT; -- BE3G5
CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (not sTIMER_UPDATE and SW_INTRP_TIMER);
-- CTL_LCH_Set <= (GT_C_TO_A_BUS and T1) or (sTIMER_UPDATE and SW_INTRP_TIMER);
CTL_LCH_Reset <= CTRL_TRG and T3;
CTL_LCH: entity work.FLL port map(CTL_LCH_Set,CTL_LCH_Reset,CTRL_LCH); -- BE3G6,BE3F5
N10MSPULSE <= not(N60_CY_TIMER_PULSE and not T3); -- 10ms monostable here
CT_FF_Set <= CTRL_LCH and T4;
CT_FF: entity work.FLL port map(CT_FF_Set,not CTRL_LCH,CTRL_TRG); -- BE3F6
BD_FF_Set <= not CTRL_LCH and T3 and N10MSPULSE and not CNTR_FULL; -- Not T2 as per MDM (refer FETOM)
BD_FF: entity work.FLL port map(BD_FF_Set,not N10MSPULSE,BIN_DRIVE); -- BE3F6
process(BIN_DRIVE,RST_COUNTER,CTRL_TRG) -- BE3G7,BE3F7
begin
if RST_COUNTER='1' or CTRL_TRG='1' then
C_BINARY_CNTR <= "0000";
else if BIN_DRIVE'event and BIN_DRIVE='0' then
C_BINARY_CNTR <= C_BINARY_CNTR + "0001";
end if;
end if;
end process;
CNTR_FULL <= C_BINARY_CNTR(4) and C_BINARY_CNTR(5) and C_BINARY_CNTR(6) and C_BINARY_CNTR(7); -- BE3G6
-- Interrupt generation
sTIMER_UPDATE <= C_BINARY_CNTR(4) or C_BINARY_CNTR(5) or C_BINARY_CNTR(6) or C_BINARY_CNTR(7); -- BE3G6,BE3G5
TIMER_UPDATE <= sTIMER_UPDATE and EXT_TRAP_MASK_ON; -- Modified to include EXT_TRAP_MASK_ON for timer as well
-- TIMER_UPDATE <= sTIMER_UPDATE;
TIMER_UPDATE_OR_EXT_INT <= (sTIMER_UPDATE and EXT_TRAP_MASK_ON) or EXT_INT; -- AC1D5 Modified to include EXT_TRAP_MASK_ON for timer as well
-- TIMER_UPDATE_OR_EXT_INT <= EXT_INT; -- AC1D5 ?? Temporarily prevent Timer
EXT_INT <= (F_REGISTER(0) or F_REGISTER(1) or F_REGISTER(2) or F_REGISTER(3) or
F_REGISTER(4) or F_REGISTER(5) or F_REGISTER(6) or F_REGISTER(7)) and EXT_TRAP_MASK_ON; -- AC1G2 ?? Should this include EXT_TRAP_MASK_ON ?
EI_LCH_Reset <= MACH_RST_SW or RESET_F_REG;
EI_LCH_Set <= EXT_INT and T3; -- ?? Seems to be needed, not as per MDM
EI_LCH: entity work.FLL port map(EI_LCH_Set,EI_LCH_Reset,EXT_INTRP); -- AC1K6,AC1C2
-- F register - here it is held in True polarity, in the 2030 it is inverted
C_EXT_INT <= "000000";
SET_F_REG_0 <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1111
RESET_F_REG <= CK_SALS(0) and CK_SALS(1) and CK_SALS(2) and not CK_SALS(3) and GT_CK_DECO; -- AB3F7 CK=1110
F1A_LCH_Reset <= (L_REGISTER(1) and RESET_F_REG) or RECYCLE_RST;
F1_LCH_Set <= F_REGISTER_1A and SW_CONS_INTRP;
F1A_LCH: entity work.FLL port map(not SW_CONS_INTRP, F1A_LCH_Reset, F_REGISTER_1A); -- AC1L2
F07_LCH_Set <= SET_F_REG_0 & F1_LCH_Set & C_EXT_INT(2 to 7);
F07_LCH_Reset <= (0 to 7 => RECYCLE_RST) or ((0 to 7 => RESET_F_REG) and ('1' & L_REGISTER(1 to 7)));
F07_LCH: entity work.FLVL port map(F07_LCH_Set, F07_LCH_Reset, F_REGISTER(0 to 7)); -- AC1L2
-- H register
H_SET <= MACH_RST_2B or (E_SW.H_SEL and MAN_STOR_PWR) or
(T4 and not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3)); -- AB1J2 CD=0101
GT_1050_TAGS <= not CD_CTRL_REG(0) and CD_CTRL_REG(1) and not CD_CTRL_REG(2) and not CD_CTRL_REG(3); -- AB1B3 CD=0100
GT_1050_BUS <= not CD_CTRL_REG(0) and not CD_CTRL_REG(1) and not CD_CTRL_REG(2) and CD_CTRL_REG(3); -- AB1B3 CD=0001
CD_REG_2 <= CD_CTRL_REG(2); -- AB1B3
H_LCH: entity work.PHV8 port map(Z_BUS,H_SET,sH_REG_BITS); -- AB1L3
H_REG_BITS <= sH_REG_BITS;
HP_LCH: entity work.PH port map(Z_BUS_P,H_SET,sH_REG_P); -- AB1L3
H_REG_P <= sH_REG_P;
H_REG_6 <= sH_REG_BITS(6); -- AB1C6,AB1G2
H_REG_5_PWR <= sH_REG_BITS(5); -- AB1L2
-- A bus drive
GT_C_TO_A_BUS <= (E_SW.C_SEL and USE_MAN_DECODER) or
(not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0100
GT_F_TO_A <= (E_SW.F_SEL and USE_MAN_DECO_PWR) or
(not GTD_CA_BITS(0) and not GTD_CA_BITS(1) and not GTD_CA_BITS(2) and not GTD_CA_BITS(3) and USE_ALT_CA_DECODER); -- AB3C7 CA=0000
GT_H_TO_A <= (E_SW.H_SEL and USE_MAN_DECODER) or
(not GTD_CA_BITS(0) and GTD_CA_BITS(1) and not GTD_CA_BITS(2) and GTD_CA_BITS(3) and USE_BASIC_CA_DECODER); -- AB3C7 CA=0101
A_BUS <= not ("0000" & C_BINARY_CNTR & '0') when GT_C_TO_A_BUS='1'
else (F_REGISTER & '0') when GT_F_TO_A='1' -- ?? F_REGISTER should be inverted?
else not (sH_REG_BITS & sH_REG_P) when GT_H_TO_A='1'
else "111111111"; -- AB1F6
with DEBUG.Selection select
DEBUG.Probe <=
C_BINARY_CNTR(7) when 0,
C_BINARY_CNTR(6) when 1,
C_BINARY_CNTR(5) when 2,
C_BINARY_CNTR(4) when 3,
N10MSPULSE when 4,
CNTR_FULL when 5,
CTRL_LCH when 6,
CTRL_TRG when 7,
BIN_DRIVE when 8,
RST_COUNTER when 9,
N60_CY_TIMER_PULSE when 10,
CTL_LCH_Set when 11,
CTL_LCH_Reset when 12,
BD_FF_Set when 13,
EXT_INT when 14,
sTIMER_UPDATE when 15;
END FMD;
| gpl-3.0 | d49099c21abeb532d8ba35b328c628b4 | 0.642575 | 2.466667 | false | false | false | false |
chastell/art-decomp | kiss/ex3_jed.vhd | 1 | 4,215 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex3_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex3_jed;
architecture behaviour of ex3_jed is
constant s1: std_logic_vector(3 downto 0) := "0011";
constant s2: std_logic_vector(3 downto 0) := "0000";
constant s4: std_logic_vector(3 downto 0) := "0010";
constant s3: std_logic_vector(3 downto 0) := "1000";
constant s0: std_logic_vector(3 downto 0) := "0001";
constant s7: std_logic_vector(3 downto 0) := "0111";
constant s8: std_logic_vector(3 downto 0) := "1101";
constant s6: std_logic_vector(3 downto 0) := "0101";
constant s5: std_logic_vector(3 downto 0) := "1001";
constant s9: std_logic_vector(3 downto 0) := "0100";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "01";
elsif std_match(input, "10") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "10";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "--";
elsif std_match(input, "10") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s2; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 326a5c7b3788052fc461ccb36ef73cb0 | 0.557533 | 3.316286 | false | false | false | false |
chastell/art-decomp | kiss/train4_hot.vhd | 1 | 2,078 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_hot;
architecture behaviour of train4_hot is
constant st0: std_logic_vector(3 downto 0) := "1000";
constant st1: std_logic_vector(3 downto 0) := "0100";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st3: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | 8e8e78546b74be1285146080d8e048b9 | 0.588065 | 3.257053 | false | false | false | false |
chastell/art-decomp | spec/fixtures/ex4_hot.vhd | 2 | 3,881 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex4_hot is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(8 downto 0)
);
end ex4_hot;
architecture behaviour of ex4_hot is
constant s1: std_logic_vector(13 downto 0) := "10000000000000";
constant s3: std_logic_vector(13 downto 0) := "01000000000000";
constant s2: std_logic_vector(13 downto 0) := "00100000000000";
constant s5: std_logic_vector(13 downto 0) := "00010000000000";
constant s7: std_logic_vector(13 downto 0) := "00001000000000";
constant s11: std_logic_vector(13 downto 0) := "00000100000000";
constant s12: std_logic_vector(13 downto 0) := "00000010000000";
constant s8: std_logic_vector(13 downto 0) := "00000001000000";
constant s4: std_logic_vector(13 downto 0) := "00000000100000";
constant s13: std_logic_vector(13 downto 0) := "00000000010000";
constant s14: std_logic_vector(13 downto 0) := "00000000001000";
constant s6: std_logic_vector(13 downto 0) := "00000000000100";
constant s9: std_logic_vector(13 downto 0) := "00000000000010";
constant s10: std_logic_vector(13 downto 0) := "00000000000001";
signal current_state, next_state: std_logic_vector(13 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------"; output <= "---------";
case current_state is
when s1 =>
if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
end if;
when s3 =>
if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
end if;
when s2 =>
if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
end if;
when s5 =>
if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
end if;
when s7 =>
if std_match(input, "10----") then next_state <= s7; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
end if;
when s11 =>
if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
end if;
when s12 =>
if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
end if;
when s8 =>
if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
end if;
when s4 =>
if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
end if;
when s13 =>
if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
end if;
when s14 =>
if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
end if;
when s6 =>
if std_match(input, "10----") then next_state <= s6; output <= "000000000";
elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
end if;
when s9 =>
if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
end if;
when s10 =>
if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
end if;
when others => next_state <= "--------------"; output <= "---------";
end case;
end process;
end behaviour;
| agpl-3.0 | c892612bd64bb32039216ed27aa3a5ec | 0.582582 | 3.486972 | false | false | false | false |
chastell/art-decomp | kiss/lion_jed.vhd | 1 | 1,832 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity lion_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end lion_jed;
architecture behaviour of lion_jed is
constant st0: std_logic_vector(1 downto 0) := "10";
constant st1: std_logic_vector(1 downto 0) := "00";
constant st2: std_logic_vector(1 downto 0) := "11";
constant st3: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "-0") then next_state <= st0; output <= "0";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "0-") then next_state <= st1; output <= "1";
elsif std_match(input, "11") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "1-") then next_state <= st2; output <= "1";
elsif std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "0-") then next_state <= st3; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when others => next_state <= "--"; output <= "-";
end case;
end process;
end behaviour;
| agpl-3.0 | eef2b17064e8ea6b0cce6468c0d5736f | 0.587882 | 3.231041 | false | false | false | false |
chastell/art-decomp | kiss/styr_nov.vhd | 1 | 18,712 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_nov is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_nov;
architecture behaviour of styr_nov is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st1: std_logic_vector(4 downto 0) := "11111";
constant st2: std_logic_vector(4 downto 0) := "00111";
constant st3: std_logic_vector(4 downto 0) := "00110";
constant st4: std_logic_vector(4 downto 0) := "11011";
constant st5: std_logic_vector(4 downto 0) := "11100";
constant st6: std_logic_vector(4 downto 0) := "00101";
constant st7: std_logic_vector(4 downto 0) := "00100";
constant st29: std_logic_vector(4 downto 0) := "01011";
constant st8: std_logic_vector(4 downto 0) := "10010";
constant st9: std_logic_vector(4 downto 0) := "10100";
constant st28: std_logic_vector(4 downto 0) := "10000";
constant st10: std_logic_vector(4 downto 0) := "01010";
constant st11: std_logic_vector(4 downto 0) := "01001";
constant st12: std_logic_vector(4 downto 0) := "01000";
constant st13: std_logic_vector(4 downto 0) := "01111";
constant st14: std_logic_vector(4 downto 0) := "01110";
constant st15: std_logic_vector(4 downto 0) := "11101";
constant st16: std_logic_vector(4 downto 0) := "01101";
constant st17: std_logic_vector(4 downto 0) := "01100";
constant st18: std_logic_vector(4 downto 0) := "10001";
constant st19: std_logic_vector(4 downto 0) := "11110";
constant st20: std_logic_vector(4 downto 0) := "10111";
constant st21: std_logic_vector(4 downto 0) := "10011";
constant st22: std_logic_vector(4 downto 0) := "00001";
constant st23: std_logic_vector(4 downto 0) := "00010";
constant st24: std_logic_vector(4 downto 0) := "11000";
constant st25: std_logic_vector(4 downto 0) := "10110";
constant st26: std_logic_vector(4 downto 0) := "11001";
constant st27: std_logic_vector(4 downto 0) := "00011";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "----------";
case current_state is
when st0 =>
if std_match(input, "1-0000---") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-10-----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-1-0----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0010---") then next_state <= st10; output <= "1000----10";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "1010100110";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st1 =>
if std_match(input, "------0--") then next_state <= st2; output <= "0110010000";
elsif std_match(input, "------1--") then next_state <= st8; output <= "0110100100";
end if;
when st2 =>
if std_match(input, "1-00000--") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0011---") then next_state <= st2; output <= "010100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st7; output <= "010000--00";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st3 =>
if std_match(input, "1-0000---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st3; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st5; output <= "0110001100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st4 =>
if std_match(input, "---------") then next_state <= st6; output <= "0110010000";
end if;
when st5 =>
if std_match(input, "---------") then next_state <= st1; output <= "0110010100";
end if;
when st6 =>
if std_match(input, "1-00000--") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st6; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st7 =>
if std_match(input, "1-0000---") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st7; output <= "110100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0010------";
elsif std_match(input, "1-010----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st29 =>
if std_match(input, "1-0000---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st29; output <= "110100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st8 =>
if std_match(input, "---------") then next_state <= st9; output <= "0110010000";
end if;
when st9 =>
if std_match(input, "1-00000--") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-001----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-00001--") then next_state <= st28; output <= "010010--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st28 =>
if std_match(input, "1-0000---") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-001----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st10 =>
if std_match(input, "1--0---00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1---0--00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1--0---10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0----1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0---1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st11 =>
if std_match(input, "1--011-0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0--0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--010-0-") then next_state <= st10; output <= "0100----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0---1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st12 =>
if std_match(input, "1--011---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--10----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--000---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0001---") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1--010---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st13 =>
if std_match(input, "1--000---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--01----") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--001---") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st14 =>
if std_match(input, "1--000---") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--01----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--001---") then next_state <= st15; output <= "0010100100";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st15 =>
if std_match(input, "--1------") then next_state <= st16; output <= "0010010000";
elsif std_match(input, "--0------") then next_state <= st22; output <= "0010010000";
end if;
when st16 =>
if std_match(input, "1--000---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--011---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st17 =>
if std_match(input, "1--000---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st18; output <= "0010001100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st18 =>
if std_match(input, "---------") then next_state <= st19; output <= "0010010100";
end if;
when st19 =>
if std_match(input, "---------") then next_state <= st16; output <= "0010010000";
end if;
when st20 =>
if std_match(input, "---------") then next_state <= st21; output <= "0010010000";
end if;
when st21 =>
if std_match(input, "1--000---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st22 =>
if std_match(input, "1-0000---") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st23 =>
if std_match(input, "1-0000---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st24; output <= "0010001100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st24 =>
if std_match(input, "---------") then next_state <= st25; output <= "0010010100";
end if;
when st25 =>
if std_match(input, "---------") then next_state <= st22; output <= "0010010000";
end if;
when st26 =>
if std_match(input, "---------") then next_state <= st27; output <= "0010010000";
end if;
when st27 =>
if std_match(input, "1-0000---") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when others => next_state <= "-----"; output <= "----------";
end case;
end process;
end behaviour;
| agpl-3.0 | 346ddfa4a7abeea3ff9490d661f642c7 | 0.553068 | 3.430247 | false | false | false | false |
chastell/art-decomp | kiss/dk15_nov.vhd | 1 | 3,716 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk15_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk15_nov;
architecture behaviour of dk15_nov is
constant state1: std_logic_vector(1 downto 0) := "10";
constant state2: std_logic_vector(1 downto 0) := "00";
constant state3: std_logic_vector(1 downto 0) := "11";
constant state4: std_logic_vector(1 downto 0) := "01";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when state1 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state2 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state2; output <= "10001";
elsif std_match(input, "111") then next_state <= state3; output <= "10101";
elsif std_match(input, "100") then next_state <= state3; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "01010";
end if;
when state3 =>
if std_match(input, "000") then next_state <= state1; output <= "00101";
elsif std_match(input, "001") then next_state <= state2; output <= "00010";
elsif std_match(input, "010") then next_state <= state3; output <= "00010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "10100";
elsif std_match(input, "101") then next_state <= state2; output <= "01000";
elsif std_match(input, "110") then next_state <= state4; output <= "01010";
end if;
when state4 =>
if std_match(input, "000") then next_state <= state2; output <= "10010";
elsif std_match(input, "001") then next_state <= state2; output <= "10100";
elsif std_match(input, "010") then next_state <= state3; output <= "10010";
elsif std_match(input, "011") then next_state <= state1; output <= "00100";
elsif std_match(input, "111") then next_state <= state1; output <= "00100";
elsif std_match(input, "100") then next_state <= state1; output <= "01001";
elsif std_match(input, "101") then next_state <= state2; output <= "01010";
elsif std_match(input, "110") then next_state <= state3; output <= "10000";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
| agpl-3.0 | 3020043273dd8306053142002b8579f8 | 0.609526 | 3.453532 | false | false | false | false |
TheMassController/VHDL_experimenting | project/UART/uart_tb.vhd | 1 | 20,021 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.txt_util.all;
use IEEE.numeric_std.ALL;
use IEEE.math_real.ALL;
entity uart_tb is
generic (
clock_period : time;
randVal : natural
);
port (
clk : in STD_LOGIC;
done : out boolean;
success : out boolean
);
end uart_tb;
architecture Behavioral of uart_tb is
signal uart_receiv_1_rst : STD_LOGIC := '1';
signal uart_receiv_1_rx : STD_LOGIC := '1';
signal uart_receiv_1 : STD_LOGIC_VECTOR(8 DOWNTO 0);
signal uart_receiv_1_ready : STD_LOGIC;
signal uart_receiv_1_par_err : STD_LOGIC;
signal uart_receiv_1_dat_err : STD_LOGIC;
signal uart_receiv_2_rst : STD_LOGIC := '1';
signal uart_receiv_2_rx : STD_LOGIC := '1';
signal uart_receiv_2 : STD_LOGIC_VECTOR(8 DOWNTO 0);
signal uart_receiv_2_ready : STD_LOGIC;
signal uart_receiv_2_par_err : STD_LOGIC;
signal uart_receiv_2_dat_err : STD_LOGIC;
signal uart_send_1_rst : STD_LOGIC := '1';
signal uart_send_1_in : STD_LOGIC_VECTOR(8 DOWNTO 0) := (others => '0');
signal uart_send_1_start : STD_LOGIC := '0';
signal uart_send_1_tx : STD_LOGIC;
signal uart_send_1_ready : STD_LOGIC;
signal uart_send_2_rst : STD_LOGIC := '1';
signal uart_send_2_in : STD_LOGIC_VECTOR(8 DOWNTO 0) := (others => '0');
signal uart_send_2_start : STD_LOGIC := '0';
signal uart_send_2_tx : STD_LOGIC;
signal uart_send_2_ready : STD_LOGIC;
signal uart_main_rst : STD_LOGIC := '1';
signal uart_main_rx : STD_LOGIC := '1';
signal uart_main_tx : STD_LOGIC;
signal uart_main_send_start : STD_LOGIC := '0';
signal uart_main_data_in : STD_LOGIC_VECTOR(8 DOWNTO 0) := (others => '0');
signal uart_main_data_out : STD_LOGIC_VECTOR(8 DOWNTO 0);
signal uart_main_data_ready : STD_LOGIC;
signal uart_main_data_error : STD_LOGIC;
signal uart_main_parity_error : STD_LOGIC;
signal uart_main_send_ready : STD_LOGIC;
signal uart_receiv_1_done : boolean := false;
signal uart_receiv_2_done : boolean := false;
signal uart_send_1_done : boolean := false;
signal uart_send_2_done : boolean := false;
signal uart_main_done : boolean := false;
signal uart_receiv_1_success : boolean := false;
signal uart_receiv_2_success : boolean := false;
signal uart_send_1_success : boolean := false;
signal uart_send_2_success : boolean := false;
signal uart_main_success : boolean := false;
constant clk_freq : natural := (1000 ms / clock_period);
constant baudrate : natural := 236400;
constant baud_period : time := (1000 ms / baudrate);
constant clk_ticks_per_baud : natural := (natural(ceil(real(clk_freq)/real(baudrate))));
begin
done <= uart_receiv_1_done and uart_receiv_2_done and uart_send_1_done and uart_send_2_done and uart_main_done;
success <= uart_receiv_1_success and uart_receiv_2_success and uart_send_1_success and uart_send_2_success and uart_main_success;
uart_receiver_1 : entity work.uart_receiv
generic map (
baudrate => baudrate,
clk_freq => clk_freq,
parity_bit_in => false,
parity_bit_in_type => 0,
bit_count_in => 8,
stop_bits_in => 1
)
port map (
rst => uart_receiv_1_rst,
clk => clk,
uart_rx => uart_receiv_1_rx,
received_data => uart_receiv_1,
data_ready => uart_receiv_1_ready,
parity_error => uart_receiv_1_par_err,
data_error => uart_receiv_1_dat_err
);
uart_receiver_2 : entity work.uart_receiv
generic map (
baudrate => baudrate,
clk_freq => clk_freq,
parity_bit_in => true,
parity_bit_in_type => 0,
bit_count_in => 8,
stop_bits_in => 2
)
port map (
rst => uart_receiv_2_rst,
clk => clk,
uart_rx => uart_receiv_2_rx,
received_data => uart_receiv_2,
data_ready => uart_receiv_2_ready,
parity_error => uart_receiv_2_par_err,
data_error => uart_receiv_2_dat_err
);
uart_send_1 : entity work.uart_transmit
generic map (
baudrate => baudrate,
clk_freq => clk_freq,
parity_bit_en => false,
parity_bit_type => 0,
bit_count => 8,
stop_bits => 1
)
port map (
rst => uart_send_1_rst,
clk => clk,
uart_tx => uart_send_1_tx,
data_in => uart_send_1_in,
data_send_start => uart_send_1_start,
ready => uart_send_1_ready
);
uart_send_2 : entity work.uart_transmit
generic map (
baudrate => baudrate,
clk_freq => clk_freq,
parity_bit_en => true,
parity_bit_type => 1,
bit_count => 8,
stop_bits => 2
)
port map (
rst => uart_send_2_rst,
clk => clk,
uart_tx => uart_send_2_tx,
data_in => uart_send_2_in,
data_send_start => uart_send_2_start,
ready => uart_send_2_ready
);
uart_total : entity work.uart_main
generic map (
clk_freq => clk_freq,
baudrate => baudrate,
parity_bit_en => true,
parity_bit_type => 3,
bit_count => 6,
stop_bits_count => 2
)
port map (
rst => uart_main_rst,
clk => clk,
uart_rx => uart_main_rx,
uart_tx => uart_main_tx,
send_start => uart_main_send_start,
data_in => uart_main_data_in,
data_out => uart_main_data_out,
data_ready => uart_main_data_ready,
data_error => uart_main_data_error,
parity_error => uart_main_parity_error,
send_ready => uart_main_send_ready
);
uart_main_rx <= uart_main_tx;
uart_main_tester : process
variable suc : boolean := true;
variable test_data : STD_LOGIC_VECTOR(5 DOWNTO 0) := "101000";
begin
uart_main_rst <= '0';
wait for clock_period;
report "clk_period " & time'image(clock_period) & " clk_ticks_per_baud " & natural'image(clk_ticks_per_baud) & " baud_period " & time'image(baud_period) severity note;
for D in 32 to 43 loop
uart_main_data_in(5 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(D, 6));
uart_main_send_start <= '1';
wait for clock_period;
uart_main_send_start <= '0';
wait for 10 * baud_period; -- Wait for 10 baud ticks, which is about 2120 cycles on a 50 MHz clock
wait for 5 * clock_period;
if uart_main_data_ready /= '1' then
report "uart_main had not received on D = " & integer'image(D) severity error;
suc := false;
end if;
if uart_main_send_ready /= '1' then
report "uart main is not ready to send on D = " & integer'image(D) severity error;
suc := false;
end if;
if uart_main_data_error /= '0' then
report "UART main reports unexpected data error on D = " & integer'image(D) severity error;
suc := false;
end if;
if uart_main_parity_error /= '0' then
report "UART main reports unexpected parity error on D = " & integer'image(D) severity error;
suc := false;
end if;
if uart_main_data_out(5 DOWNTO 0) /= STD_LOGIC_VECTOR(to_unsigned(D, 6)) then
report "uart main send/receive error on D = " & integer'image(D) severity error;
suc := false;
end if;
end loop;
report "Uart main test done" severity note;
uart_main_success <= suc;
uart_main_done <= true;
wait;
end process;
uart_receiver_1_tester : process
variable data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
variable suc : boolean := true;
begin
uart_receiv_1_rst <= '0';
wait for baud_period;
for D in 230 to 255 loop
data_buffer := STD_LOGIC_VECTOR(to_unsigned(D, data_buffer'length));
uart_receiv_1_rx <= '0';
for I in 0 TO 7 loop
wait for baud_period;
uart_receiv_1_rx <= data_buffer(I);
end loop;
wait for baud_period;
uart_receiv_1_rx <= '1';
wait for baud_period;
if uart_receiv_1_ready /= '1' then
suc := false;
report "Uart_receiv_1 was not ready, while it was expected to be" severity error;
end if;
if uart_receiv_1(7 DOWNTO 0) /= data_buffer then
report "uart_receiv_1 unexpected value" severity error;
suc := false;
end if;
if uart_receiv_1_dat_err /= '0' then
report "uart_receiv_1_dat_err unexpected value" severity error;
suc := false;
end if;
if uart_receiv_1_par_err /= '0' then
report "uart_receiv_1_par_err unexpected value" severity error;
suc := false;
end if;
end loop;
uart_receiv_1_rst <= '1';
report "UART_receiv_1 test done" severity note;
uart_receiv_1_done <= true;
uart_receiv_1_success <= suc;
wait;
end process;
uart_receive_2_tester : process
variable data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
variable odd : STD_LOGIC := '0';
variable suc : boolean := true;
begin
uart_receiv_2_rx <= '1';
uart_receiv_2_rst <= '0';
wait for baud_period;
for D in 230 to 255 loop
data_buffer := STD_LOGIC_VECTOR(to_unsigned(D, data_buffer'length));
uart_receiv_2_rx <= '0';
for I in 0 to 7 loop
wait for baud_period;
uart_receiv_2_rx <= data_buffer(I);
if data_buffer(I) = '1' then
odd := not odd;
end if;
end loop;
wait for baud_period;
-- Send the parity bit
uart_receiv_2_rx <= odd;
wait for baud_period;
uart_receiv_2_rx <= '1';
wait for baud_period;
wait for baud_period;
if uart_receiv_2_ready /= '1' then
suc := false;
report "Uart receiv 2 was not ready while it was expected to be ready" severity error;
end if;
if uart_receiv_2(7 DOWNTO 0) /= data_buffer then
report "uart_receiv_2 unexpected value" severity error;
suc := false;
end if;
if uart_receiv_2_dat_err /= '0' then
report "uart_receiv_2_dat_err unexpected value" severity error;
suc := false;
end if;
if uart_receiv_2_par_err /= '0' then
report "uart_receiv_2_par_err unexpected value" severity error;
suc := false;
end if;
odd := '0';
end loop;
uart_receiv_2_rst <= '1';
-- Test if the parity error happens when expected
wait for clock_period;
uart_receiv_2_rst <= '0';
-- Test for parity error
data_buffer := STD_LOGIC_VECTOR(to_unsigned(randVal, data_buffer'length));
odd := '0';
-- Start bit
uart_receiv_2_rx <= '0';
-- Send data
for I in 0 to 7 loop
wait for baud_period;
uart_receiv_2_rx <= data_buffer(I);
if data_buffer(I) = '1' then
odd := not odd;
end if;
end loop;
-- Send the wrong parity bit
wait for baud_period;
uart_receiv_2_rx <= not odd;
wait for baud_period;
-- Double stop bit
uart_receiv_2_rx <= '1';
wait for baud_period;
wait for baud_period;
if uart_receiv_2_ready /= '1' then
suc := false;
report "Uart receiv 2 was not ready while it was expected to be ready" severity error;
end if;
if uart_receiv_2(7 DOWNTO 0) /= data_buffer then
suc := false;
report "uart_receiv_2 unexpected value" severity error;
end if;
if uart_receiv_2_dat_err /= '0' then
suc := false;
report "uart_receiv_2_dat_err unexpected value" severity error;
end if;
if uart_receiv_2_par_err /= '1' then
suc := false;
report "uart_receiv_2_par_err unexpected value, expected to fail, but passed, randval was " & integer'image(randVal) severity error;
end if;
uart_receiv_2_rst <= '1';
report "UART_receiv_2 test done" severity note;
uart_receiv_2_done <= true;
uart_receiv_2_success <= suc;
wait;
end process;
uart_send_1_test : process
variable data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
variable suc : boolean := true;
begin
uart_send_1_rst <= '0';
wait for clock_period;
if uart_send_1_tx /= '1' then
suc := false;
report "uart_send_1_rx does not default to 1" severity error;
end if;
if uart_send_1_ready /= '1' then
report "uart_send_1_ready does not default to 1" severity error;
suc := false;
end if;
for D in 230 to 255 loop
data_buffer := STD_LOGIC_VECTOR(to_unsigned(D, data_buffer'length));
uart_send_1_in(7 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(D, data_buffer'length));
uart_send_1_start <= '1';
wait for baud_period/2; -- We want to poll halfway trough
uart_send_1_start <= '0';
if uart_send_1_tx /= '0' then
report "uart_send_1_tx start bit incorrect" severity error;
suc := false;
end if;
if uart_send_1_ready /= '0' then
report "uart_send_1_ready is one where it should have been zero" severity error;
suc := false;
end if;
for I in 0 to 7 loop
wait for baud_period;
if data_buffer(I) /= uart_send_1_tx then
report "UART 1 tx unexpected value" severity error;
suc := false;
end if;
end loop;
wait for baud_period;
if uart_send_1_tx /= '1' then
report "uart_send_1_tx stop bit incorrect" severity error;
suc := false;
end if;
if uart_send_1_ready /= '0' then
report "uart_send_1_ready is one where it should have been zero" severity error;
suc := false;
end if;
wait for baud_period;
if uart_send_1_tx /= '1' then
report "uart_send_1_tx stop bit incorrect" severity error;
suc := false;
end if;
if uart_send_1_ready /= '1' then
report "uart_send_1_ready is not one in time" severity error;
suc := false;
end if;
end loop;
report "data_send_1 tests done" severity note;
uart_send_1_done <= true;
uart_send_1_success <= suc;
wait;
end process;
uart_send_2_test : process
variable data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
variable even : STD_LOGIC := '1';
variable suc : boolean := true;
begin
uart_send_2_rst <= '0';
-- Test the start situation
if uart_send_2_tx = '1' then
report "uart_send_2_tx does not default to 1" severity error;
suc := false;
end if;
if uart_send_2_ready = '1' then
report "uart_send_2_ready does not default to 1" severity error;
suc := false;
end if;
wait for clock_period;
for D in 230 to 255 loop
even := '1';
data_buffer := STD_LOGIC_VECTOR(to_unsigned(D, data_buffer'length));
uart_send_2_in(7 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(D, data_buffer'length));
uart_send_2_start <= '1';
-- Jump to halfway trough start bit
wait for baud_period/2;
uart_send_2_start <= '0';
if uart_send_2_tx /= '0' then
report "uart_send_2_tx start bit incorrect" severity error;
suc := false;
end if;
if uart_send_2_ready /= '0' then
report "uart_send_2_ready is one where it should have been zero" severity error;
suc := false;
end if;
for I in 0 to 7 loop
-- Jump to halfway trough the Ith bit
wait for baud_period;
if data_buffer(I) /= uart_send_2_tx then
report "UART_2_send_tx unexpected value" severity error;
suc := false;
end if;
if data_buffer(I) = '1' then
even := not even;
end if;
end loop;
-- Parity bit
wait for baud_period;
if uart_send_2_tx /= even then
report "uart_send_2_tx parity bit incorrect, even = " & std_logic'image(even) & " uart_send_2_tx = " & std_logic'image(uart_send_2_tx) & " D = " & integer'image(D) severity error;
suc := false;
end if;
if uart_send_2_ready /= '0' then
report "uart_send_2_ready is one where it should have been zero" severity error;
suc := false;
end if;
-- stop bit 1
wait for baud_period;
if uart_send_2_tx /= '1' then
report "uart_send_2_tx stop bit incorrect" severity error;
suc := false;
end if;
if uart_send_2_ready /= '0' then
report "uart_send_2_ready is one where it should have been zero" severity error;
suc := false;
end if;
-- stop bit 2
wait for baud_period;
if uart_send_2_tx /= '1' then
report "uart_send_2_tx stop bit incorrect" severity error;
suc := false;
end if;
if uart_send_2_ready /= '0' then
report "uart_send_2_ready is one where it should have been zero" severity error;
suc := false;
end if;
-- Back to start situation
wait for baud_period;
end loop;
wait for baud_period;
-- At this point we would test for abnormal situations, but there are none: there is no input for which an error is expected.
report "data_send_2 tests done" severity note;
uart_send_2_done <= true;
uart_send_2_success <= suc;
wait;
end process;
end Behavioral;
| mit | 5b3ac5d550e2f085cd05de1a9e3b27f5 | 0.501523 | 3.92261 | false | false | false | false |
chastell/art-decomp | kiss/s208_rnd.vhd | 1 | 16,541 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s208_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s208_rnd;
architecture behaviour of s208_rnd is
constant s11111111: std_logic_vector(4 downto 0) := "11101";
constant s00000000: std_logic_vector(4 downto 0) := "00010";
constant s00010000: std_logic_vector(4 downto 0) := "11011";
constant s00100000: std_logic_vector(4 downto 0) := "11110";
constant s00110000: std_logic_vector(4 downto 0) := "11111";
constant s01000000: std_logic_vector(4 downto 0) := "10001";
constant s01010000: std_logic_vector(4 downto 0) := "10110";
constant s01100000: std_logic_vector(4 downto 0) := "01011";
constant s01110000: std_logic_vector(4 downto 0) := "01111";
constant s10000000: std_logic_vector(4 downto 0) := "00001";
constant s10010000: std_logic_vector(4 downto 0) := "10000";
constant s10100000: std_logic_vector(4 downto 0) := "11010";
constant s10110000: std_logic_vector(4 downto 0) := "11000";
constant s11000000: std_logic_vector(4 downto 0) := "01000";
constant s11010000: std_logic_vector(4 downto 0) := "00100";
constant s11100000: std_logic_vector(4 downto 0) := "01001";
constant s11110000: std_logic_vector(4 downto 0) := "00110";
constant s00000001: std_logic_vector(4 downto 0) := "11100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s11111111 =>
if std_match(input, "0--------01") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------01") then next_state <= s00000000; output <= "11";
elsif std_match(input, "0--------11") then next_state <= s00000000; output <= "10";
elsif std_match(input, "1--------11") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------10") then next_state <= s00000000; output <= "11";
elsif std_match(input, "1--------00") then next_state <= s00000000; output <= "10";
elsif std_match(input, "0---------0") then next_state <= s00000000; output <= "10";
end if;
when s00000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10--------0") then next_state <= s00010000; output <= "00";
end if;
when s00010000 =>
if std_match(input, "10-------00") then next_state <= s00100000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s00100000; output <= "01";
elsif std_match(input, "10-------1-") then next_state <= s00100000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
end if;
when s00100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s00110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s00110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s00110000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s00110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s01000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01000000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s01000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-----1--0") then next_state <= s01010000; output <= "01";
elsif std_match(input, "10-----0--0") then next_state <= s01010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01010000; output <= "01";
end if;
when s01010000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s01100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s01100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s01100000; output <= "01";
end if;
when s01100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1-0") then next_state <= s01110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s01110000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s01110000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s01110000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s10000000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10----0---0") then next_state <= s10010000; output <= "00";
elsif std_match(input, "10----1---0") then next_state <= s10010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s10010000; output <= "01";
elsif std_match(input, "11----1---0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11----0---0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s10010000 =>
if std_match(input, "10--------1") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------10") then next_state <= s10100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s10100000; output <= "00";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s10100000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10------1--") then next_state <= s10110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s10110000; output <= "00";
elsif std_match(input, "10------0-1") then next_state <= s10110000; output <= "01";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when s10110000 =>
if std_match(input, "10--------1") then next_state <= s11000000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11000000; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s11000000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------0-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------1-") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------1-") then next_state <= s00000000; output <= "01";
end if;
when s11000000 =>
if std_match(input, "10-----0--0") then next_state <= s11010000; output <= "00";
elsif std_match(input, "10-----1--0") then next_state <= s11010000; output <= "01";
elsif std_match(input, "10--------1") then next_state <= s11010000; output <= "01";
elsif std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-----1--0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11-----0--0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
end if;
when s11010000 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10-------01") then next_state <= s11100000; output <= "01";
elsif std_match(input, "10-------00") then next_state <= s11100000; output <= "00";
elsif std_match(input, "10-------1-") then next_state <= s11100000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01--------1") then next_state <= s00000000; output <= "00";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
end if;
when s11100000 =>
if std_match(input, "0----------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------0-0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11------1-0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10------1--") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-1") then next_state <= s11110000; output <= "01";
elsif std_match(input, "10------0-0") then next_state <= s11110000; output <= "00";
end if;
when s11110000 =>
if std_match(input, "01-------01") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------01") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01-------11") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------11") then next_state <= s00000000; output <= "01";
elsif std_match(input, "-1-------00") then next_state <= s00000000; output <= "00";
elsif std_match(input, "01-------10") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11-------10") then next_state <= s00000000; output <= "01";
elsif std_match(input, "10-------01") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------01") then next_state <= s00000001; output <= "00";
elsif std_match(input, "-0-------00") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------11") then next_state <= s00000001; output <= "01";
elsif std_match(input, "00-------11") then next_state <= s00000001; output <= "00";
elsif std_match(input, "00-------10") then next_state <= s00000001; output <= "00";
elsif std_match(input, "10-------10") then next_state <= s00000001; output <= "01";
end if;
when s00000001 =>
if std_match(input, "00---------") then next_state <= s00000000; output <= "00";
elsif std_match(input, "10---1----0") then next_state <= s00010000; output <= "01";
elsif std_match(input, "10---0----0") then next_state <= s00010000; output <= "00";
elsif std_match(input, "10--------1") then next_state <= s00010000; output <= "01";
elsif std_match(input, "11---0----0") then next_state <= s00000000; output <= "00";
elsif std_match(input, "11---1----0") then next_state <= s00000000; output <= "01";
elsif std_match(input, "11--------1") then next_state <= s00000000; output <= "01";
elsif std_match(input, "01---------") then next_state <= s00000000; output <= "00";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
| agpl-3.0 | 0414669768bea9b1cf96528c9fdb9f23 | 0.565625 | 3.517865 | false | false | false | false |
Diego-HR/HL-Object-Oriented | QAMDemodulator/src/solution1/syn/vhdl/qam_dem_top_mounstrito.vhd | 4 | 63,258 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity qam_dem_top_mounstrito is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
din_i_V : IN STD_LOGIC_VECTOR (15 downto 0);
din_q_V : IN STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_i_V_ap_vld : OUT STD_LOGIC;
dout_mix_q_V : OUT STD_LOGIC_VECTOR (15 downto 0);
dout_mix_q_V_ap_vld : OUT STD_LOGIC;
ph_in_i_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_in_q_V : IN STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_i_V_ap_vld : OUT STD_LOGIC;
ph_out_q_V : OUT STD_LOGIC_VECTOR (11 downto 0);
ph_out_q_V_ap_vld : OUT STD_LOGIC;
loop_integ_V : OUT STD_LOGIC_VECTOR (27 downto 0);
loop_integ_V_ap_vld : OUT STD_LOGIC;
control_lf_p : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_i : IN STD_LOGIC_VECTOR (7 downto 0);
control_lf_out_gain : IN STD_LOGIC_VECTOR (7 downto 0);
control_reg_clr : IN STD_LOGIC_VECTOR (0 downto 0);
control_reg_init_V : IN STD_LOGIC_VECTOR (27 downto 0) );
end;
architecture behav of qam_dem_top_mounstrito is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv28_0 : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv14_1FFF : STD_LOGIC_VECTOR (13 downto 0) := "01111111111111";
constant ap_const_lv14_2000 : STD_LOGIC_VECTOR (13 downto 0) := "10000000000000";
constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv9_9 : STD_LOGIC_VECTOR (8 downto 0) := "000001001";
constant ap_const_lv9_1F7 : STD_LOGIC_VECTOR (8 downto 0) := "111110111";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv28_7FFFFFF : STD_LOGIC_VECTOR (27 downto 0) := "0111111111111111111111111111";
constant ap_const_lv28_8000000 : STD_LOGIC_VECTOR (27 downto 0) := "1000000000000000000000000000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv10_3FF : STD_LOGIC_VECTOR (9 downto 0) := "1111111111";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_34 : BOOLEAN;
signal i_reg_V : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
signal phase_angle_V : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal cos_lut_address0 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_lut_ce0 : STD_LOGIC;
signal cos_lut_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal cos_lut_address1 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_lut_ce1 : STD_LOGIC;
signal cos_lut_q1 : STD_LOGIC_VECTOR (14 downto 0);
signal reg_312 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_82 : BOOLEAN;
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_89 : BOOLEAN;
signal grp_fu_276_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal reg_316 : STD_LOGIC_VECTOR (26 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_99 : BOOLEAN;
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_106 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_114 : BOOLEAN;
signal OP1_V_i_cast_fu_320_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP1_V_i_cast_reg_1471 : STD_LOGIC_VECTOR (26 downto 0);
signal ap_sig_bdd_122 : BOOLEAN;
signal OP2_V_i_cast_fu_325_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_i_cast_reg_1476 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_1_i_cast_fu_330_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal OP2_V_1_i_cast_reg_1481 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_1_fu_335_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_1_reg_1486 : STD_LOGIC_VECTOR (26 downto 0);
signal sd_out_i_V_reg_1491 : STD_LOGIC_VECTOR (15 downto 0);
signal newsignbit_fu_372_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_reg_1497 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_fu_408_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_reg_1503 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_fu_432_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_reg_1509 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_fu_467_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_1516 : STD_LOGIC_VECTOR (0 downto 0);
signal sd_out_q_V_reg_1521 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_148 : BOOLEAN;
signal isneg_1_reg_1527 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_1_reg_1533 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_1_i_reg_1541 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_6_fu_620_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_6_reg_1547 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_163 : BOOLEAN;
signal OP1_V_fu_628_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal OP2_V_fu_633_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal isneg_2_reg_1562 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_176 : BOOLEAN;
signal p_Val2_9_reg_1568 : STD_LOGIC_VECTOR (13 downto 0);
signal newsignbit_2_reg_1574 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_i8_reg_1580 : STD_LOGIC_VECTOR (1 downto 0);
signal OP1_V_1_fu_692_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal OP2_V_1_fu_697_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal tmp_9_fu_775_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_9_reg_1596 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_24_reg_1601 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_197 : BOOLEAN;
signal overflow_3_fu_854_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_3_reg_1607 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_3_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_3_reg_1613 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_26_fu_977_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_26_reg_1620 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_210 : BOOLEAN;
signal p_Val2_4_fu_1041_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_4_reg_1625 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_16_i_fu_1137_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_16_i_reg_1630 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_221 : BOOLEAN;
signal isNeg_2_fu_1160_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal isNeg_2_reg_1636 : STD_LOGIC_VECTOR (0 downto 0);
signal sh_assign_3_fu_1174_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sh_assign_3_reg_1641 : STD_LOGIC_VECTOR (7 downto 0);
signal msb_V_reg_1647 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_234 : BOOLEAN;
signal tmp_26_reg_1654 : STD_LOGIC_VECTOR (0 downto 0);
signal sin_adr_V_reg_1660 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_247 : BOOLEAN;
signal tmp_23_i_fu_1300_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_i_fu_1305_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Val2_41_fu_1145_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal loop_integ_V_preg : STD_LOGIC_VECTOR (27 downto 0) := "0000000000000000000000000000";
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_275 : BOOLEAN;
signal grp_fu_276_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_276_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_6_i_fu_340_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_1_fu_348_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Result_i_fu_380_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal p_not_i1_i_fu_390_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_fu_364_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i1_i_fu_396_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_i_fu_402_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i1_i_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i1_i_fu_414_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i1_i_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_not_i_fu_442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_i_fu_438_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_brmerge_i_i1_i_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge8_i_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_458_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_463_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_i_fu_475_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_3_fu_483_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_not_i_i_fu_525_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_fu_530_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_i_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i_fu_546_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_1_fu_540_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_1_not_i_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i2_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal brmerge_i_i_i_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_brmerge_i_i_i_fu_604_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge9_i_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_615_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_s_fu_592_p5 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_i3_fu_637_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal isneg_2_fu_656_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_9_fu_664_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal newsignbit_2_fu_674_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Result_i8_fu_682_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Result_2_fu_644_p5 : STD_LOGIC_VECTOR (4 downto 0);
signal p_not_i_i9_fu_701_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i1_fu_706_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i_fu_711_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i1_fu_727_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i1_fu_722_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i1_fu_732_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_2_fu_738_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_2_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_not_i1_fu_749_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i1_fu_743_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_fu_755_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_21_mux_i_fu_761_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_i1_fu_768_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_1_i1_fu_783_p3 : STD_LOGIC_VECTOR (18 downto 0);
signal tmp_10_cast_i_fu_790_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_23_fu_794_p1 : STD_LOGIC_VECTOR (20 downto 0);
signal p_Val2_23_fu_794_p2 : STD_LOGIC_VECTOR (20 downto 0);
signal tmp_7_fu_826_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal newsignbit_3_fu_818_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not_i_i_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_3_fu_800_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i4_i_fu_842_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_i1_fu_848_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_not38_i_i_i_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal newsignbit_0_not_i_i_i_fu_860_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge39_i_i_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal underflow_4_not_i_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i_i_fu_884_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge1_i_fu_893_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ssdm_int_V_write_assign_fu_898_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_Val2_1_i_fu_905_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_10_fu_911_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal isNeg_fu_927_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_i_fu_935_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal sh_assign_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_i1_fu_919_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_5_i1_fu_957_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast_i_fu_953_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_1_cast6_i_fu_949_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_6_i2_fu_961_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_fu_973_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_7_i1_fu_967_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_cast_i_fu_985_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_1_fu_989_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal isNeg_1_fu_995_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_i1_fu_1003_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_2_fu_1009_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal sh_assign_3_cast_i_fu_1021_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_3_cast5_i_fu_1017_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_10_i_fu_1025_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_1037_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_11_i_fu_1031_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_5_fu_1053_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_12_i_fu_1058_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_13_i_fu_1062_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_27_fu_1065_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal newsignbit_4_fu_1083_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_4_fu_1071_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_15_i_fu_1091_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal isneg_not_i_fu_1109_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i2_fu_1103_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_29_fu_1079_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal underflow_4_fu_1097_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i1_fu_1115_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_28_mux_i_fu_1121_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_i2_fu_1129_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_17_i_fu_1168_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_i_fu_1188_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_5_cast_i_fu_1185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sh_assign_5_cast3_i_fu_1182_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_i_fu_1191_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_1202_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_20_i_fu_1197_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_i2_15_fu_1217_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_33_fu_1206_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_35_cast_i_fu_1225_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_21_i_fu_1229_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_34_fu_1233_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal cos_adr_V_3_fu_1283_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal cos_adr_V_fu_1288_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal sin_adr_V_1_fu_1294_p3 : STD_LOGIC_VECTOR (9 downto 0);
signal p_Val2_31_cast_i_fu_1314_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal p_Val2_32_cast_i_fu_1310_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_25_i_fu_1318_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_i_fu_1323_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_demorgan_i_fu_1345_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_27_i_fu_1328_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_i_fu_1351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_i_fu_1363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_i_fu_1369_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_i_fu_1357_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_1381_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal sel_tmp_i_fu_1339_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_12_fu_1391_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_27_fu_1395_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_28_fu_1405_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_29_fu_1422_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal sin_out_V_fu_1333_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_30_fu_1432_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_31_fu_1436_p4 : STD_LOGIC_VECTOR (11 downto 0);
signal or_cond_fu_1375_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_1446_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_33_fu_1454_p3 : STD_LOGIC_VECTOR (11 downto 0);
signal grp_fu_276_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component qam_dem_top_mul_16s_12s_27_2 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (11 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (26 downto 0) );
end component;
component qam_dem_top_mounstrito_cos_lut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (9 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0);
address1 : IN STD_LOGIC_VECTOR (9 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
begin
cos_lut_U : component qam_dem_top_mounstrito_cos_lut
generic map (
DataWidth => 15,
AddressRange => 1024,
AddressWidth => 10)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => cos_lut_address0,
ce0 => cos_lut_ce0,
q0 => cos_lut_q0,
address1 => cos_lut_address1,
ce1 => cos_lut_ce1,
q1 => cos_lut_q1);
qam_dem_top_mul_16s_12s_27_2_U1 : component qam_dem_top_mul_16s_12s_27_2
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 16,
din1_WIDTH => 12,
dout_WIDTH => 27)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_276_p0,
din1 => grp_fu_276_p1,
ce => grp_fu_276_ce,
dout => grp_fu_276_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- loop_integ_V_preg assign process. --
loop_integ_V_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
loop_integ_V_preg <= ap_const_lv28_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V_preg <= p_Val2_41_fu_1145_p3;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_122))) then
OP1_V_i_cast_reg_1471 <= OP1_V_i_cast_fu_320_p1;
OP2_V_i_cast_reg_1476 <= OP2_V_i_cast_fu_325_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
OP2_V_1_i_cast_reg_1481 <= OP2_V_1_i_cast_fu_330_p1;
tmp_1_reg_1486 <= tmp_1_fu_335_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
i_reg_V <= p_Val2_41_fu_1145_p3;
isNeg_2_reg_1636 <= control_lf_out_gain(7 downto 7);
sh_assign_3_reg_1641 <= sh_assign_3_fu_1174_p3;
tmp_16_i_reg_1630 <= tmp_16_i_fu_1137_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
isneg_1_reg_1527 <= p_Val2_3_fu_483_p2(26 downto 26);
newsignbit_1_reg_1533 <= p_Val2_3_fu_483_p2(24 downto 24);
p_Result_1_i_reg_1541 <= p_Val2_3_fu_483_p2(26 downto 25);
sd_out_q_V_reg_1521 <= p_Val2_3_fu_483_p2(26 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
isneg_2_reg_1562 <= isneg_2_fu_656_p1(20 downto 20);
newsignbit_2_reg_1574 <= newsignbit_2_fu_674_p1(18 downto 18);
p_Result_i8_reg_1580 <= p_Result_i8_fu_682_p1(20 downto 19);
p_Val2_9_reg_1568 <= p_Val2_9_fu_664_p1(18 downto 5);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
msb_V_reg_1647 <= p_Val2_34_fu_1233_p2(26 downto 25);
phase_angle_V <= p_Val2_34_fu_1233_p2(26 downto 11);
sin_adr_V_reg_1660 <= p_Val2_34_fu_1233_p2(24 downto 15);
tmp_26_reg_1654 <= p_Val2_34_fu_1233_p2(25 downto 25);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
newsignbit_reg_1497 <= p_Val2_1_fu_348_p2(24 downto 24);
overflow_reg_1503 <= overflow_fu_408_p2;
sd_out_i_V_reg_1491 <= p_Val2_1_fu_348_p2(26 downto 11);
underflow_reg_1509 <= underflow_fu_432_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
overflow_3_reg_1607 <= overflow_3_fu_854_p2;
p_Val2_24_reg_1601 <= p_Val2_23_fu_794_p2(18 downto 5);
underflow_3_reg_1613 <= underflow_3_fu_878_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
p_Val2_26_reg_1620 <= p_Val2_26_fu_977_p3;
p_Val2_4_reg_1625 <= p_Val2_4_fu_1041_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
reg_312 <= grp_fu_276_p2(26 downto 11);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8))) then
reg_316 <= grp_fu_276_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
tmp_3_reg_1516 <= tmp_3_fu_467_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
tmp_6_reg_1547 <= tmp_6_fu_620_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_9_reg_1596 <= tmp_9_fu_775_p3;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_122)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_122)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
OP1_V_1_fu_692_p1 <= std_logic_vector(resize(signed(p_Result_2_fu_644_p5),21));
OP1_V_fu_628_p1 <= std_logic_vector(resize(signed(p_Result_s_fu_592_p5),21));
OP1_V_i_cast_fu_320_p1 <= std_logic_vector(resize(signed(din_i_V),27));
OP2_V_1_fu_697_p1 <= std_logic_vector(resize(signed(sd_out_i_V_reg_1491),21));
OP2_V_1_i_cast_fu_330_p1 <= std_logic_vector(resize(signed(ph_in_q_V),27));
OP2_V_fu_633_p1 <= std_logic_vector(resize(signed(sd_out_q_V_reg_1521),21));
OP2_V_i_cast_fu_325_p1 <= std_logic_vector(resize(signed(ph_in_i_V),27));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st15_fsm_14)
begin
if (((ap_const_logic_1 = ap_done_reg) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_106 assign process. --
ap_sig_bdd_106_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_106 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_114 assign process. --
ap_sig_bdd_114_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_114 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_122 assign process. --
ap_sig_bdd_122_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_122 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_148 assign process. --
ap_sig_bdd_148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_148 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_163 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_176 assign process. --
ap_sig_bdd_176_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_176 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_197 assign process. --
ap_sig_bdd_197_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_197 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_210 assign process. --
ap_sig_bdd_210_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_210 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_221 assign process. --
ap_sig_bdd_221_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_221 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_234 assign process. --
ap_sig_bdd_234_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_234 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_247 assign process. --
ap_sig_bdd_247_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_247 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_275 assign process. --
ap_sig_bdd_275_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_275 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_34 assign process. --
ap_sig_bdd_34_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_34 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_82 assign process. --
ap_sig_bdd_82_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_82 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_89 assign process. --
ap_sig_bdd_89_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_99 assign process. --
ap_sig_bdd_99_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_99 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_197)
begin
if (ap_sig_bdd_197) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_210)
begin
if (ap_sig_bdd_210) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_221)
begin
if (ap_sig_bdd_221) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_234)
begin
if (ap_sig_bdd_234) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_247)
begin
if (ap_sig_bdd_247) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_34)
begin
if (ap_sig_bdd_34) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_82)
begin
if (ap_sig_bdd_82) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_99)
begin
if (ap_sig_bdd_99) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_89)
begin
if (ap_sig_bdd_89) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_106)
begin
if (ap_sig_bdd_106) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_148)
begin
if (ap_sig_bdd_148) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_163)
begin
if (ap_sig_bdd_163) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_176)
begin
if (ap_sig_bdd_176) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_114)
begin
if (ap_sig_bdd_114) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
brmerge1_i_fu_893_p2 <= (overflow_3_reg_1607 or underflow_4_not_i_fu_888_p2);
brmerge39_i1_i_fu_426_p2 <= (p_not38_i1_i_fu_420_p2 or newsignbit_0_not_i1_i_fu_414_p2);
brmerge39_i_i1_fu_732_p2 <= (p_not38_i_i1_fu_727_p2 or newsignbit_0_not_i_i1_fu_722_p2);
brmerge39_i_i_fu_556_p2 <= (p_not38_i_i_fu_551_p2 or newsignbit_0_not_i_i_fu_546_p2);
brmerge39_i_i_i_fu_872_p2 <= (p_not38_i_i_i_fu_866_p2 or newsignbit_0_not_i_i_i_fu_860_p2);
brmerge8_i_fu_447_p2 <= (overflow_reg_1503 or underflow_not_i_fu_442_p2);
brmerge9_i_fu_579_p2 <= (overflow_1_fu_540_p2 or underflow_1_not_i_fu_573_p2);
brmerge_i1_fu_1115_p2 <= (newsignbit_4_fu_1083_p3 or isneg_not_i_fu_1109_p2);
brmerge_i1_i_fu_396_p2 <= (newsignbit_fu_372_p3 or p_not_i1_i_fu_390_p2);
brmerge_i_fu_755_p2 <= (overflow_2_fu_716_p2 or underflow_not_i1_fu_749_p2);
brmerge_i_i1_fu_706_p2 <= (newsignbit_2_reg_1574 or p_not_i_i9_fu_701_p2);
brmerge_i_i1_i_fu_438_p2 <= (underflow_reg_1509 or overflow_reg_1503);
brmerge_i_i4_i_fu_842_p2 <= (newsignbit_3_fu_818_p3 or p_not_i_i_i_fu_836_p2);
brmerge_i_i_fu_530_p2 <= (newsignbit_1_reg_1533 or p_not_i_i_fu_525_p2);
brmerge_i_i_i1_fu_743_p2 <= (underflow_2_fu_738_p2 or overflow_2_fu_716_p2);
brmerge_i_i_i2_fu_1103_p2 <= (isneg_4_fu_1071_p3 xor newsignbit_4_fu_1083_p3);
brmerge_i_i_i_fu_567_p2 <= (underflow_1_fu_562_p2 or overflow_1_fu_540_p2);
brmerge_i_i_i_i_fu_884_p2 <= (underflow_3_reg_1613 or overflow_3_reg_1607);
cos_adr_V_3_fu_1283_p2 <= (sin_adr_V_reg_1660 xor ap_const_lv10_3FF);
cos_adr_V_fu_1288_p3 <=
cos_adr_V_3_fu_1283_p2 when (tmp_26_reg_1654(0) = '1') else
sin_adr_V_reg_1660;
cos_lut_address0 <= tmp_23_i_fu_1300_p1(10 - 1 downto 0);
cos_lut_address1 <= tmp_24_i_fu_1305_p1(10 - 1 downto 0);
-- cos_lut_ce0 assign process. --
cos_lut_ce0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
cos_lut_ce0 <= ap_const_logic_1;
else
cos_lut_ce0 <= ap_const_logic_0;
end if;
end process;
-- cos_lut_ce1 assign process. --
cos_lut_ce1_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
cos_lut_ce1 <= ap_const_logic_1;
else
cos_lut_ce1 <= ap_const_logic_0;
end if;
end process;
dout_mix_i_V <= sd_out_i_V_reg_1491;
-- dout_mix_i_V_ap_vld assign process. --
dout_mix_i_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
dout_mix_i_V_ap_vld <= ap_const_logic_1;
else
dout_mix_i_V_ap_vld <= ap_const_logic_0;
end if;
end process;
dout_mix_q_V <= sd_out_q_V_reg_1521;
-- dout_mix_q_V_ap_vld assign process. --
dout_mix_q_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st7_fsm_6)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
dout_mix_q_V_ap_vld <= ap_const_logic_1;
else
dout_mix_q_V_ap_vld <= ap_const_logic_0;
end if;
end process;
-- grp_fu_276_ce assign process. --
grp_fu_276_ce_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st5_fsm_4, ap_sig_cseq_ST_st9_fsm_8, ap_sig_bdd_122, ap_sig_cseq_ST_st7_fsm_6, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) or (ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_122)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7))) then
grp_fu_276_ce <= ap_const_logic_1;
else
grp_fu_276_ce <= ap_const_logic_0;
end if;
end process;
-- grp_fu_276_p0 assign process. --
grp_fu_276_p0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, OP1_V_i_cast_fu_320_p1, OP1_V_i_cast_reg_1471, tmp_1_fu_335_p1, tmp_1_reg_1486, ap_sig_cseq_ST_st7_fsm_6, OP2_V_fu_633_p1, ap_sig_cseq_ST_st8_fsm_7, OP2_V_1_fu_697_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
grp_fu_276_p0 <= OP2_V_1_fu_697_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
grp_fu_276_p0 <= OP2_V_fu_633_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
grp_fu_276_p0 <= tmp_1_reg_1486(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
grp_fu_276_p0 <= OP1_V_i_cast_reg_1471(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_276_p0 <= tmp_1_fu_335_p1(16 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_276_p0 <= OP1_V_i_cast_fu_320_p1(16 - 1 downto 0);
else
grp_fu_276_p0 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_276_p1 assign process. --
grp_fu_276_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st3_fsm_2, OP2_V_i_cast_fu_325_p1, OP2_V_i_cast_reg_1476, OP2_V_1_i_cast_fu_330_p1, OP2_V_1_i_cast_reg_1481, ap_sig_cseq_ST_st7_fsm_6, OP1_V_fu_628_p1, ap_sig_cseq_ST_st8_fsm_7, OP1_V_1_fu_692_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
grp_fu_276_p1 <= OP1_V_1_fu_692_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
grp_fu_276_p1 <= OP1_V_fu_628_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
grp_fu_276_p1 <= OP2_V_i_cast_reg_1476(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
grp_fu_276_p1 <= OP2_V_1_i_cast_reg_1481(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
grp_fu_276_p1 <= OP2_V_1_i_cast_fu_330_p1(12 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_276_p1 <= OP2_V_i_cast_fu_325_p1(12 - 1 downto 0);
else
grp_fu_276_p1 <= "XXXXXXXXXXXX";
end if;
end process;
isNeg_1_fu_995_p3 <= sh_assign_1_fu_989_p2(8 downto 8);
isNeg_2_fu_1160_p3 <= control_lf_out_gain(7 downto 7);
isNeg_fu_927_p3 <= control_lf_p(7 downto 7);
isneg_2_fu_656_p1 <= grp_fu_276_p2(21 - 1 downto 0);
isneg_3_fu_800_p3 <= p_Val2_23_fu_794_p2(20 downto 20);
isneg_4_fu_1071_p3 <= p_Val2_27_fu_1065_p2(28 downto 28);
isneg_fu_364_p3 <= p_Val2_1_fu_348_p2(26 downto 26);
isneg_not_i_fu_1109_p2 <= (isneg_4_fu_1071_p3 xor ap_const_lv1_1);
-- loop_integ_V assign process. --
loop_integ_V_assign_proc : process(ap_sig_cseq_ST_st12_fsm_11, p_Val2_41_fu_1145_p3, loop_integ_V_preg)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V <= p_Val2_41_fu_1145_p3;
else
loop_integ_V <= loop_integ_V_preg;
end if;
end process;
-- loop_integ_V_ap_vld assign process. --
loop_integ_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st12_fsm_11)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
loop_integ_V_ap_vld <= ap_const_logic_1;
else
loop_integ_V_ap_vld <= ap_const_logic_0;
end if;
end process;
newsignbit_0_not_i1_i_fu_414_p2 <= (newsignbit_fu_372_p3 xor ap_const_lv1_1);
newsignbit_0_not_i_i1_fu_722_p2 <= (newsignbit_2_reg_1574 xor ap_const_lv1_1);
newsignbit_0_not_i_i_fu_546_p2 <= (newsignbit_1_reg_1533 xor ap_const_lv1_1);
newsignbit_0_not_i_i_i_fu_860_p2 <= (newsignbit_3_fu_818_p3 xor ap_const_lv1_1);
newsignbit_2_fu_674_p1 <= grp_fu_276_p2(21 - 1 downto 0);
newsignbit_3_fu_818_p3 <= p_Val2_23_fu_794_p2(18 downto 18);
newsignbit_4_fu_1083_p3 <= p_Val2_27_fu_1065_p2(27 downto 27);
newsignbit_fu_372_p3 <= p_Val2_1_fu_348_p2(24 downto 24);
not_brmerge_i_i1_i_fu_452_p2 <= (brmerge_i_i1_i_fu_438_p2 xor ap_const_lv1_1);
not_brmerge_i_i_i_fu_604_p2 <= (brmerge_i_i_i_fu_567_p2 xor ap_const_lv1_1);
or_cond_fu_1375_p2 <= (sel_tmp7_i_fu_1369_p2 or sel_tmp4_i_fu_1357_p2);
overflow_1_fu_540_p2 <= (brmerge_i_i_fu_530_p2 and tmp_7_i_fu_535_p2);
overflow_2_fu_716_p2 <= (brmerge_i_i1_fu_706_p2 and tmp_8_i_fu_711_p2);
overflow_3_fu_854_p2 <= (brmerge_i_i4_i_fu_842_p2 and tmp_3_i1_fu_848_p2);
overflow_fu_408_p2 <= (brmerge_i1_i_fu_396_p2 and tmp_5_i_fu_402_p2);
p_Result_2_fu_644_p5 <= (tmp_1_i3_fu_637_p3 & ap_const_lv5_0(2 downto 0));
p_Result_i8_fu_682_p1 <= grp_fu_276_p2(21 - 1 downto 0);
p_Result_i_fu_380_p4 <= p_Val2_1_fu_348_p2(26 downto 25);
p_Result_s_fu_592_p5 <= (tmp_i2_fu_585_p3 & ap_const_lv5_0(2 downto 0));
p_Val2_1_fu_348_p2 <= std_logic_vector(unsigned(tmp_6_i_fu_340_p3) - unsigned(reg_316));
p_Val2_1_i_fu_905_p3 <=
ap_const_lv14_2000 when (underflow_3_reg_1613(0) = '1') else
p_Val2_24_reg_1601;
p_Val2_21_mux_i_fu_761_p3 <=
ap_const_lv14_1FFF when (brmerge_i_i_i1_fu_743_p2(0) = '1') else
p_Val2_9_reg_1568;
p_Val2_23_fu_794_p1 <= reg_316(21 - 1 downto 0);
p_Val2_23_fu_794_p2 <= std_logic_vector(signed(tmp_10_cast_i_fu_790_p1) - signed(p_Val2_23_fu_794_p1));
p_Val2_26_fu_977_p3 <=
tmp_16_fu_973_p1 when (isNeg_fu_927_p3(0) = '1') else
tmp_7_i1_fu_967_p2;
p_Val2_27_fu_1065_p2 <= std_logic_vector(signed(tmp_12_i_fu_1058_p1) + signed(tmp_13_i_fu_1062_p1));
p_Val2_28_mux_i_fu_1121_p3 <=
ap_const_lv28_7FFFFFF when (brmerge_i_i_i2_fu_1103_p2(0) = '1') else
p_Val2_29_fu_1079_p1;
p_Val2_29_fu_1079_p1 <= p_Val2_27_fu_1065_p2(28 - 1 downto 0);
p_Val2_31_cast_i_fu_1314_p1 <= std_logic_vector(resize(unsigned(cos_lut_q1),16));
p_Val2_32_cast_i_fu_1310_p1 <= std_logic_vector(resize(unsigned(cos_lut_q0),16));
p_Val2_33_fu_1206_p3 <=
tmp_25_fu_1202_p1 when (isNeg_2_reg_1636(0) = '1') else
tmp_20_i_fu_1197_p2;
p_Val2_34_fu_1233_p2 <= std_logic_vector(signed(tmp_35_cast_i_fu_1225_p1) - signed(tmp_21_i_fu_1229_p1));
p_Val2_3_fu_483_p2 <= std_logic_vector(unsigned(tmp_3_i_fu_475_p3) + unsigned(reg_316));
p_Val2_41_fu_1145_p3 <=
control_reg_init_V when (control_reg_clr(0) = '1') else
p_Val2_5_fu_1053_p2;
p_Val2_4_fu_1041_p3 <=
tmp_18_fu_1037_p1 when (isNeg_1_fu_995_p3(0) = '1') else
tmp_11_i_fu_1031_p2;
p_Val2_5_fu_1053_p2 <= std_logic_vector(unsigned(i_reg_V) + unsigned(p_Val2_4_reg_1625));
p_Val2_9_fu_664_p1 <= grp_fu_276_p2(21 - 1 downto 0);
p_Val2_i1_fu_768_p3 <=
ap_const_lv14_2000 when (underflow_2_fu_738_p2(0) = '1') else
p_Val2_9_reg_1568;
p_Val2_i2_fu_1129_p3 <=
ap_const_lv28_8000000 when (underflow_4_fu_1097_p2(0) = '1') else
p_Val2_29_fu_1079_p1;
p_not38_i1_i_fu_420_p2 <= "0" when (p_Result_i_fu_380_p4 = ap_const_lv2_3) else "1";
p_not38_i_i1_fu_727_p2 <= "0" when (p_Result_i8_reg_1580 = ap_const_lv2_3) else "1";
p_not38_i_i_fu_551_p2 <= "0" when (p_Result_1_i_reg_1541 = ap_const_lv2_3) else "1";
p_not38_i_i_i_fu_866_p2 <= "0" when (tmp_7_fu_826_p4 = ap_const_lv2_3) else "1";
p_not_i1_i_fu_390_p2 <= "0" when (p_Result_i_fu_380_p4 = ap_const_lv2_0) else "1";
p_not_i_i9_fu_701_p2 <= "0" when (p_Result_i8_reg_1580 = ap_const_lv2_0) else "1";
p_not_i_i_fu_525_p2 <= "0" when (p_Result_1_i_reg_1541 = ap_const_lv2_0) else "1";
p_not_i_i_i_fu_836_p2 <= "0" when (tmp_7_fu_826_p4 = ap_const_lv2_0) else "1";
ph_out_i_V <=
tmp_12_fu_1391_p1 when (sel_tmp7_i_fu_1369_p2(0) = '1') else
tmp_28_fu_1405_p3;
-- ph_out_i_V_ap_vld assign process. --
ph_out_i_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ph_out_i_V_ap_vld <= ap_const_logic_1;
else
ph_out_i_V_ap_vld <= ap_const_logic_0;
end if;
end process;
ph_out_q_V <=
tmp_32_fu_1446_p3 when (or_cond_fu_1375_p2(0) = '1') else
tmp_33_fu_1454_p3;
-- ph_out_q_V_ap_vld assign process. --
ph_out_q_V_ap_vld_assign_proc : process(ap_sig_cseq_ST_st15_fsm_14)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
ph_out_q_V_ap_vld <= ap_const_logic_1;
else
ph_out_q_V_ap_vld <= ap_const_logic_0;
end if;
end process;
sel_tmp3_demorgan_i_fu_1345_p2 <= (tmp_25_i_fu_1318_p2 or tmp_26_i_fu_1323_p2);
sel_tmp3_i_fu_1351_p2 <= (sel_tmp3_demorgan_i_fu_1345_p2 xor ap_const_lv1_1);
sel_tmp4_i_fu_1357_p2 <= (tmp_27_i_fu_1328_p2 and sel_tmp3_i_fu_1351_p2);
sel_tmp6_i_fu_1363_p2 <= (tmp_25_i_fu_1318_p2 xor ap_const_lv1_1);
sel_tmp7_i_fu_1369_p2 <= (tmp_26_i_fu_1323_p2 and sel_tmp6_i_fu_1363_p2);
sel_tmp_i_fu_1339_p2 <= std_logic_vector(unsigned(ap_const_lv16_0) - unsigned(p_Val2_32_cast_i_fu_1310_p1));
sh_assign_1_cast6_i_fu_949_p1 <= std_logic_vector(resize(unsigned(sh_assign_fu_941_p3),28));
sh_assign_1_cast_i_fu_953_p1 <= std_logic_vector(resize(unsigned(sh_assign_fu_941_p3),32));
sh_assign_1_fu_989_p2 <= std_logic_vector(signed(tmp_19_cast_i_fu_985_p1) + signed(ap_const_lv9_9));
sh_assign_2_fu_1009_p3 <=
tmp_8_i1_fu_1003_p2 when (isNeg_1_fu_995_p3(0) = '1') else
sh_assign_1_fu_989_p2;
sh_assign_3_cast5_i_fu_1017_p1 <= std_logic_vector(resize(signed(sh_assign_2_fu_1009_p3),28));
sh_assign_3_cast_i_fu_1021_p1 <= std_logic_vector(resize(signed(sh_assign_2_fu_1009_p3),32));
sh_assign_3_fu_1174_p3 <=
tmp_17_i_fu_1168_p2 when (isNeg_2_fu_1160_p3(0) = '1') else
control_lf_out_gain;
sh_assign_5_cast3_i_fu_1182_p1 <= std_logic_vector(resize(unsigned(sh_assign_3_reg_1641),28));
sh_assign_5_cast_i_fu_1185_p1 <= std_logic_vector(resize(unsigned(sh_assign_3_reg_1641),32));
sh_assign_fu_941_p3 <=
tmp_4_i_fu_935_p2 when (isNeg_fu_927_p3(0) = '1') else
control_lf_p;
sin_adr_V_1_fu_1294_p3 <=
sin_adr_V_reg_1660 when (tmp_26_reg_1654(0) = '1') else
cos_adr_V_3_fu_1283_p2;
sin_out_V_fu_1333_p2 <= std_logic_vector(unsigned(ap_const_lv16_0) - unsigned(p_Val2_31_cast_i_fu_1314_p1));
ssdm_int_V_write_assign_fu_898_p3 <=
ap_const_lv14_1FFF when (brmerge_i_i_i_i_fu_884_p2(0) = '1') else
p_Val2_24_reg_1601;
tmp_10_cast_i_fu_790_p1 <= std_logic_vector(resize(signed(tmp_1_i1_fu_783_p3),21));
tmp_10_fu_911_p3 <=
ssdm_int_V_write_assign_fu_898_p3 when (brmerge1_i_fu_893_p2(0) = '1') else
p_Val2_1_i_fu_905_p3;
tmp_10_i_fu_1025_p2 <= std_logic_vector(shift_left(unsigned(tmp_5_i1_fu_957_p1),to_integer(unsigned('0' & sh_assign_3_cast_i_fu_1021_p1(31-1 downto 0)))));
tmp_11_fu_1381_p4 <= cos_lut_q0(14 downto 4);
tmp_11_i_fu_1031_p2 <= std_logic_vector(shift_right(signed(tmp_i1_fu_919_p3),to_integer(unsigned('0' & sh_assign_3_cast5_i_fu_1017_p1(28-1 downto 0)))));
tmp_12_fu_1391_p1 <= std_logic_vector(resize(unsigned(tmp_11_fu_1381_p4),12));
tmp_12_i_fu_1058_p1 <= std_logic_vector(resize(signed(p_Val2_5_fu_1053_p2),29));
tmp_13_i_fu_1062_p1 <= std_logic_vector(resize(signed(p_Val2_26_reg_1620),29));
tmp_15_i_fu_1091_p2 <= (newsignbit_4_fu_1083_p3 xor ap_const_lv1_1);
tmp_16_fu_973_p1 <= tmp_6_i2_fu_961_p2(28 - 1 downto 0);
tmp_16_i_fu_1137_p3 <=
p_Val2_28_mux_i_fu_1121_p3 when (brmerge_i1_fu_1115_p2(0) = '1') else
p_Val2_i2_fu_1129_p3;
tmp_17_i_fu_1168_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(control_lf_out_gain));
tmp_18_fu_1037_p1 <= tmp_10_i_fu_1025_p2(28 - 1 downto 0);
tmp_18_i_fu_1188_p1 <= std_logic_vector(resize(signed(tmp_16_i_reg_1630),32));
tmp_19_cast_i_fu_985_p1 <= std_logic_vector(resize(signed(control_lf_i),9));
tmp_19_i_fu_1191_p2 <= std_logic_vector(shift_left(unsigned(tmp_18_i_fu_1188_p1),to_integer(unsigned('0' & sh_assign_5_cast_i_fu_1185_p1(31-1 downto 0)))));
tmp_1_fu_335_p1 <= std_logic_vector(resize(signed(din_q_V),27));
tmp_1_i1_fu_783_p3 <= (tmp_9_reg_1596 & ap_const_lv5_0);
tmp_1_i3_fu_637_p3 <= (tmp_6_reg_1547 & ap_const_lv1_1);
tmp_20_i_fu_1197_p2 <= std_logic_vector(shift_right(signed(tmp_16_i_reg_1630),to_integer(unsigned('0' & sh_assign_5_cast3_i_fu_1182_p1(28-1 downto 0)))));
tmp_21_i_fu_1229_p1 <= std_logic_vector(resize(unsigned(p_Val2_33_fu_1206_p3),29));
tmp_23_i_fu_1300_p1 <= std_logic_vector(resize(unsigned(cos_adr_V_fu_1288_p3),64));
tmp_24_i_fu_1305_p1 <= std_logic_vector(resize(unsigned(sin_adr_V_1_fu_1294_p3),64));
tmp_25_fu_1202_p1 <= tmp_19_i_fu_1191_p2(28 - 1 downto 0);
tmp_25_i_fu_1318_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_1) else "0";
tmp_26_i_fu_1323_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_0) else "0";
tmp_27_fu_1395_p4 <= sel_tmp_i_fu_1339_p2(15 downto 4);
tmp_27_i_fu_1328_p2 <= "1" when (msb_V_reg_1647 = ap_const_lv2_3) else "0";
tmp_28_fu_1405_p3 <=
tmp_12_fu_1391_p1 when (sel_tmp4_i_fu_1357_p2(0) = '1') else
tmp_27_fu_1395_p4;
tmp_29_fu_1422_p4 <= cos_lut_q1(14 downto 4);
tmp_30_fu_1432_p1 <= std_logic_vector(resize(unsigned(tmp_29_fu_1422_p4),12));
tmp_31_fu_1436_p4 <= sin_out_V_fu_1333_p2(15 downto 4);
tmp_32_fu_1446_p3 <=
tmp_30_fu_1432_p1 when (sel_tmp7_i_fu_1369_p2(0) = '1') else
tmp_31_fu_1436_p4;
tmp_33_fu_1454_p3 <=
tmp_30_fu_1432_p1 when (tmp_25_i_fu_1318_p2(0) = '1') else
tmp_31_fu_1436_p4;
tmp_35_cast_i_fu_1225_p1 <= std_logic_vector(resize(signed(tmp_i2_15_fu_1217_p3),29));
tmp_3_fu_467_p3 <=
tmp_5_fu_458_p2 when (brmerge8_i_fu_447_p2(0) = '1') else
tmp_s_fu_463_p2;
tmp_3_i1_fu_848_p2 <= (isneg_3_fu_800_p3 xor ap_const_lv1_1);
tmp_3_i_fu_475_p3 <= (reg_312 & ap_const_lv11_0);
tmp_4_fu_610_p2 <= (newsignbit_1_reg_1533 and not_brmerge_i_i_i_fu_604_p2);
tmp_4_i_fu_935_p2 <= std_logic_vector(unsigned(ap_const_lv8_0) - unsigned(control_lf_p));
tmp_5_fu_458_p2 <= (newsignbit_reg_1497 and not_brmerge_i_i1_i_fu_452_p2);
tmp_5_i1_fu_957_p1 <= std_logic_vector(resize(signed(tmp_i1_fu_919_p3),32));
tmp_5_i_fu_402_p2 <= (isneg_fu_364_p3 xor ap_const_lv1_1);
tmp_6_fu_620_p3 <=
tmp_4_fu_610_p2 when (brmerge9_i_fu_579_p2(0) = '1') else
tmp_8_fu_615_p2;
tmp_6_i2_fu_961_p2 <= std_logic_vector(shift_left(unsigned(tmp_5_i1_fu_957_p1),to_integer(unsigned('0' & sh_assign_1_cast_i_fu_953_p1(31-1 downto 0)))));
tmp_6_i_fu_340_p3 <= (reg_312 & ap_const_lv11_0);
tmp_7_fu_826_p4 <= p_Val2_23_fu_794_p2(20 downto 19);
tmp_7_i1_fu_967_p2 <= std_logic_vector(shift_right(signed(tmp_i1_fu_919_p3),to_integer(unsigned('0' & sh_assign_1_cast6_i_fu_949_p1(28-1 downto 0)))));
tmp_7_i_fu_535_p2 <= (isneg_1_reg_1527 xor ap_const_lv1_1);
tmp_8_fu_615_p2 <= (underflow_1_fu_562_p2 or newsignbit_1_reg_1533);
tmp_8_i1_fu_1003_p2 <= std_logic_vector(signed(ap_const_lv9_1F7) - signed(tmp_19_cast_i_fu_985_p1));
tmp_8_i_fu_711_p2 <= (isneg_2_reg_1562 xor ap_const_lv1_1);
tmp_9_fu_775_p3 <=
p_Val2_21_mux_i_fu_761_p3 when (brmerge_i_fu_755_p2(0) = '1') else
p_Val2_i1_fu_768_p3;
tmp_i1_fu_919_p3 <= (tmp_10_fu_911_p3 & ap_const_lv14_0);
tmp_i2_15_fu_1217_p3 <= (phase_angle_V & ap_const_lv11_0);
tmp_i2_fu_585_p3 <= (tmp_3_reg_1516 & ap_const_lv1_1);
tmp_s_fu_463_p2 <= (underflow_reg_1509 or newsignbit_reg_1497);
underflow_1_fu_562_p2 <= (brmerge39_i_i_fu_556_p2 and isneg_1_reg_1527);
underflow_1_not_i_fu_573_p2 <= (underflow_1_fu_562_p2 xor ap_const_lv1_1);
underflow_2_fu_738_p2 <= (brmerge39_i_i1_fu_732_p2 and isneg_2_reg_1562);
underflow_3_fu_878_p2 <= (brmerge39_i_i_i_fu_872_p2 and isneg_3_fu_800_p3);
underflow_4_fu_1097_p2 <= (isneg_4_fu_1071_p3 and tmp_15_i_fu_1091_p2);
underflow_4_not_i_fu_888_p2 <= (underflow_3_reg_1613 xor ap_const_lv1_1);
underflow_fu_432_p2 <= (brmerge39_i1_i_fu_426_p2 and isneg_fu_364_p3);
underflow_not_i1_fu_749_p2 <= (underflow_2_fu_738_p2 xor ap_const_lv1_1);
underflow_not_i_fu_442_p2 <= (underflow_reg_1509 xor ap_const_lv1_1);
end behav;
| gpl-2.0 | 7be0e306f74973e23566eed1e63b6fcd | 0.600936 | 2.598825 | false | false | false | false |
Subsets and Splits