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545/Atari7800 | core/cpu6502_true_cycle/tags/arelease/rtl/vhdl/fsm_execution_unit.vhd | 2 | 189,939 | -- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:53 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity FSM_Execution_Unit is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
sel_pc_as_o : out std_logic;
sel_pc_in_o : out std_logic;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic;
sel_sp_in_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end FSM_Execution_Unit ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: FSM Execution Unit for all op codes
-- Path: R6502_TC/FSM_Execution_Unit/fsm
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:55 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of FSM_Execution_Unit is
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal reg_sel_pc_as : std_logic;
signal reg_sel_pc_in : std_logic;
signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
signal reg_sel_sp_as : std_logic;
signal reg_sel_sp_in : std_logic;
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_so : std_logic;
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
constant FETCH : state_type := "00000000";
constant s1 : state_type := "00000001";
constant s2 : state_type := "00000011";
constant s5 : state_type := "00000010";
constant s3 : state_type := "00000110";
constant s4 : state_type := "00000111";
constant s12 : state_type := "00000101";
constant s16 : state_type := "00000100";
constant s17 : state_type := "00001100";
constant s24 : state_type := "00001101";
constant s25 : state_type := "00001111";
constant s271 : state_type := "00001110";
constant s273 : state_type := "00001010";
constant s304 : state_type := "00001011";
constant s307 : state_type := "00001001";
constant s177 : state_type := "00001000";
constant s180 : state_type := "00011000";
constant s181 : state_type := "00011001";
constant s182 : state_type := "00011011";
constant s183 : state_type := "00011010";
constant s184 : state_type := "00011110";
constant s185 : state_type := "00011111";
constant s186 : state_type := "00011101";
constant s187 : state_type := "00011100";
constant s188 : state_type := "00010100";
constant s189 : state_type := "00010101";
constant s190 : state_type := "00010111";
constant s191 : state_type := "00010110";
constant s192 : state_type := "00010010";
constant s193 : state_type := "00010011";
constant s377 : state_type := "00010001";
constant s381 : state_type := "00010000";
constant s378 : state_type := "00110000";
constant s382 : state_type := "00110001";
constant s379 : state_type := "00110011";
constant s383 : state_type := "00110010";
constant s384 : state_type := "00110110";
constant s380 : state_type := "00110111";
constant s385 : state_type := "00110101";
constant s386 : state_type := "00110100";
constant s387 : state_type := "00111100";
constant s388 : state_type := "00111101";
constant s389 : state_type := "00111111";
constant s391 : state_type := "00111110";
constant s392 : state_type := "00111010";
constant s390 : state_type := "00111011";
constant s393 : state_type := "00111001";
constant s394 : state_type := "00111000";
constant s395 : state_type := "00101000";
constant s396 : state_type := "00101001";
constant s397 : state_type := "00101011";
constant s398 : state_type := "00101010";
constant s399 : state_type := "00101110";
constant s400 : state_type := "00101111";
constant s401 : state_type := "00101101";
constant s526 : state_type := "00101100";
constant s527 : state_type := "00100100";
constant s528 : state_type := "00100101";
constant s529 : state_type := "00100111";
constant s530 : state_type := "00100110";
constant s531 : state_type := "00100010";
constant s544 : state_type := "00100011";
constant s545 : state_type := "00100001";
constant s546 : state_type := "00100000";
constant s547 : state_type := "01100000";
constant s549 : state_type := "01100001";
constant s550 : state_type := "01100011";
constant s404 : state_type := "01100010";
constant s556 : state_type := "01100110";
constant s557 : state_type := "01100111";
constant s579 : state_type := "01100101";
constant s201 : state_type := "01100100";
constant s202 : state_type := "01101100";
constant s210 : state_type := "01101101";
constant s211 : state_type := "01101111";
constant s215 : state_type := "01101110";
constant s217 : state_type := "01101010";
constant s218 : state_type := "01101011";
constant s222 : state_type := "01101001";
constant s223 : state_type := "01101000";
constant s224 : state_type := "01111000";
constant s225 : state_type := "01111001";
constant s226 : state_type := "01111011";
constant s243 : state_type := "01111010";
constant s244 : state_type := "01111110";
constant s247 : state_type := "01111111";
constant s344 : state_type := "01111101";
constant s343 : state_type := "01111100";
constant s250 : state_type := "01110100";
constant s251 : state_type := "01110101";
constant s351 : state_type := "01110111";
constant s361 : state_type := "01110110";
constant s360 : state_type := "01110010";
constant s403 : state_type := "01110011";
constant s406 : state_type := "01110001";
constant s407 : state_type := "01110000";
constant s409 : state_type := "01010000";
constant s412 : state_type := "01010001";
constant s413 : state_type := "01010011";
constant s416 : state_type := "01010010";
constant s418 : state_type := "01010110";
constant s510 : state_type := "01010111";
constant s553 : state_type := "01010101";
constant s555 : state_type := "01010100";
constant s558 : state_type := "01011100";
constant s560 : state_type := "01011101";
constant s561 : state_type := "01011111";
constant s563 : state_type := "01011110";
constant s564 : state_type := "01011010";
constant s565 : state_type := "01011011";
constant s566 : state_type := "01011001";
constant s266 : state_type := "01011000";
constant s301 : state_type := "01001000";
constant s302 : state_type := "01001001";
constant RES : state_type := "01001011";
constant s511 : state_type := "01001010";
constant s559 : state_type := "01001110";
constant s562 : state_type := "01001111";
constant s567 : state_type := "01001101";
constant s568 : state_type := "01001100";
constant s569 : state_type := "01000100";
constant s570 : state_type := "01000101";
constant s571 : state_type := "01000111";
constant s572 : state_type := "01000110";
constant s573 : state_type := "01000010";
constant s574 : state_type := "01000011";
constant s548 : state_type := "01000001";
constant s551 : state_type := "01000000";
constant s552 : state_type := "11000000";
constant s575 : state_type := "11000001";
constant s576 : state_type := "11000011";
constant s577 : state_type := "11000010";
constant s532 : state_type := "11000110";
constant s533 : state_type := "11000111";
constant s534 : state_type := "11000101";
constant s535 : state_type := "11000100";
constant s536 : state_type := "11001100";
constant s537 : state_type := "11001101";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00000100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
reg_sel_pc_as <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_sp_as <= '0';
reg_sel_sp_in <= '0';
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_NMI <= '0';
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
reg_sel_pc_as <= reg_sel_pc_as;
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
reg_sel_rb_out <= reg_sel_rb_out;
reg_sel_reg <= reg_sel_reg;
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_NMI <= zw_REG_NMI or nmi_i;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
-- Combined Actions
case current_state is
when FETCH =>
zw_REG_OP <= d_i;
if ((nmi_i = '1') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_REG_NMI <= '0';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"88") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"C8") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"28") and (rdy_i = '1')) then
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"4A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"2A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"6A") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
elsif ((d_i = X"A8") and (rdy_i = '1')) then
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"98") and (rdy_i = '1')) then
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
end if;
when s1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s5 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s3 =>
sig_PC <= adr_pc_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s12 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s16 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s17 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s24 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s25 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
end if;
when s273 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
end if;
when s304 =>
if (rdy_i = '1') then
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s307 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s180 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s181 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s182 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s183 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s185 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s186 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s188 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s189 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s190 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s191 =>
sig_PC <= zw_b3 & zw_b1;
when s192 =>
sig_PC <= d_i & zw_b1;
when s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s377 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s378 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s383 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s384 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s385 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s386 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s387 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s388 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s389 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
end if;
when s391 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s392 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s390 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s393 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s394 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
end if;
when s395 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s396 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s397 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s399 =>
sig_PC <= adr_sp_i;
when s400 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
when s401 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s526 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s527 =>
sig_PC <= adr_sp_i;
when s528 =>
sig_PC <= adr_sp_i;
when s529 =>
sig_PC <= X"FFFE";
when s530 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s531 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s544 =>
sig_PC <= adr_sp_i;
when s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
when s546 =>
sig_PC <= adr_pc_i;
when s547 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_w1 (7 downto 0) <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
end if;
when s549 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
when s404 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s556 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s557 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s579 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s202 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s210 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s211 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s215 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s217 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s218 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s222 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s223 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s243 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s244 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s247 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s344 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s343 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s361 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s360 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s406 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s407 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s409 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s412 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s553 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s555 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s558 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s560 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s561 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s563 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s566 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s302 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_pc_as <= '0';
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s559 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s562 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s567 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s568 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s569 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s570 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s571 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s572 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s548 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s551 =>
sig_PC <= adr_sp_i;
when s552 =>
sig_PC <= adr_sp_i;
when s575 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s576 =>
sig_PC <= X"FFFE";
when s577 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when s532 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s533 =>
sig_PC <= adr_sp_i;
when s534 =>
sig_PC <= adr_sp_i;
when s535 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
end if;
when s536 =>
sig_PC <= X"FFFA";
when s537 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_as <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
nmi_i,
rdy_i,
reg_F,
zw_REG_OP,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when FETCH =>
if ((nmi_i = '1') and (rdy_i = '1')) then
next_state <= s532;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= s548;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
next_state <= s510;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
next_state <= s266;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
next_state <= s351;
elsif ((d_i = X"00") and (rdy_i = '1')) then
next_state <= s526;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s12;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s16;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s17;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s24;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
next_state <= s271;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s397;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s1;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s377;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s378;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s379;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s380;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s387;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s390;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
next_state <= s511;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s2;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s5;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s3;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s404;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s556;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s557;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s579;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s4;
elsif (rdy_i = '1') then
next_state <= s1;
else
next_state <= FETCH;
end if;
when s1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s1;
end if;
when s2 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s2;
end if;
when s5 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s5;
end if;
when s3 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s3;
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s4;
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s12;
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s16;
end if;
when s17 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s17;
end if;
when s24 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s24;
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s25;
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= s307;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= s273;
else
next_state <= s271;
end if;
when s273 =>
if (rdy_i = '1') then
next_state <= s304;
else
next_state <= s273;
end if;
when s304 =>
if (rdy_i = '1') then
next_state <= s307;
else
next_state <= s304;
end if;
when s307 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s307;
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
next_state <= s184;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
next_state <= s185;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
next_state <= s183;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
next_state <= s182;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s180;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s181;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s186;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s185;
else
next_state <= s177;
end if;
when s180 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s180;
end if;
when s181 =>
if (rdy_i = '1') then
next_state <= s189;
else
next_state <= s181;
end if;
when s182 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s182;
end if;
when s183 =>
if (rdy_i = '1') then
next_state <= s187;
else
next_state <= s183;
end if;
when s184 =>
next_state <= FETCH;
when s185 =>
if (rdy_i = '1') then
next_state <= s190;
else
next_state <= s185;
end if;
when s186 =>
if (rdy_i = '1') then
next_state <= s188;
else
next_state <= s186;
end if;
when s187 =>
next_state <= FETCH;
when s188 =>
if (rdy_i = '1') then
next_state <= s192;
else
next_state <= s188;
end if;
when s189 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s189;
end if;
when s190 =>
next_state <= FETCH;
when s191 =>
next_state <= s193;
when s192 =>
next_state <= s193;
when s193 =>
next_state <= FETCH;
when s377 =>
if (rdy_i = '1') then
next_state <= s381;
else
next_state <= s377;
end if;
when s381 =>
next_state <= FETCH;
when s378 =>
if (rdy_i = '1') then
next_state <= s382;
else
next_state <= s378;
end if;
when s382 =>
next_state <= FETCH;
when s379 =>
if (rdy_i = '1') then
next_state <= s383;
else
next_state <= s379;
end if;
when s383 =>
if (rdy_i = '1') then
next_state <= s384;
else
next_state <= s383;
end if;
when s384 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s384;
end if;
when s380 =>
if (rdy_i = '1') then
next_state <= s385;
else
next_state <= s380;
end if;
when s385 =>
if (rdy_i = '1') then
next_state <= s386;
else
next_state <= s385;
end if;
when s386 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s386;
end if;
when s387 =>
if (rdy_i = '1') then
next_state <= s388;
else
next_state <= s387;
end if;
when s388 =>
if (rdy_i = '1') then
next_state <= s389;
else
next_state <= s388;
end if;
when s389 =>
if (rdy_i = '1') then
next_state <= s391;
else
next_state <= s389;
end if;
when s391 =>
if (rdy_i = '1') then
next_state <= s392;
else
next_state <= s391;
end if;
when s392 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s392;
end if;
when s390 =>
if (rdy_i = '1') then
next_state <= s393;
else
next_state <= s390;
end if;
when s393 =>
if (rdy_i = '1') then
next_state <= s394;
else
next_state <= s393;
end if;
when s394 =>
if (rdy_i = '1') then
next_state <= s395;
else
next_state <= s394;
end if;
when s395 =>
if (rdy_i = '1') then
next_state <= s396;
else
next_state <= s395;
end if;
when s396 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s396;
end if;
when s397 =>
if (rdy_i = '1') then
next_state <= s398;
else
next_state <= s397;
end if;
when s398 =>
if (rdy_i = '1') then
next_state <= s399;
else
next_state <= s398;
end if;
when s399 =>
next_state <= s400;
when s400 =>
next_state <= s401;
when s401 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s401;
end if;
when s526 =>
if (rdy_i = '1') then
next_state <= s527;
else
next_state <= s526;
end if;
when s527 =>
next_state <= s528;
when s528 =>
next_state <= s529;
when s529 =>
next_state <= s531;
when s530 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s530;
end if;
when s531 =>
if (rdy_i = '1') then
next_state <= s530;
else
next_state <= s531;
end if;
when s544 =>
next_state <= s550;
when s545 =>
next_state <= s546;
when s546 =>
next_state <= s547;
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
else
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s549;
end if;
when s550 =>
next_state <= s545;
when s404 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s404;
end if;
when s556 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s556;
end if;
when s557 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s557;
end if;
when s579 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s579;
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s224;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
next_state <= s217;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
next_state <= s202;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
next_state <= s210;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
next_state <= s211;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
next_state <= s215;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
next_state <= s218;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s217;
else
next_state <= s201;
end if;
when s202 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s202;
end if;
when s210 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s210;
end if;
when s211 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s211;
end if;
when s215 =>
if (rdy_i = '1') then
next_state <= s223;
else
next_state <= s215;
end if;
when s217 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s217;
end if;
when s218 =>
if (rdy_i = '1') then
next_state <= s222;
else
next_state <= s218;
end if;
when s222 =>
if (rdy_i = '1') then
next_state <= s202;
else
next_state <= s222;
end if;
when s223 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s223;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s224;
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s224;
else
next_state <= s225;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= s343;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= s247;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= s243;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= s244;
else
next_state <= s226;
end if;
when s243 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s243;
end if;
when s244 =>
if (rdy_i = '1') then
next_state <= s344;
else
next_state <= s244;
end if;
when s247 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s247;
end if;
when s344 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s344;
end if;
when s343 =>
if (rdy_i = '1') then
next_state <= s250;
else
next_state <= s343;
end if;
when s250 =>
if (rdy_i = '1') then
next_state <= s251;
else
next_state <= s250;
end if;
when s251 =>
next_state <= FETCH;
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s361;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s360;
else
next_state <= s351;
end if;
when s361 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s361;
end if;
when s360 =>
if (rdy_i = '1') then
next_state <= s361;
else
next_state <= s360;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= s407;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
next_state <= s413;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= s409;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
next_state <= s406;
else
next_state <= s403;
end if;
when s406 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s406;
end if;
when s407 =>
if (rdy_i = '1') then
next_state <= s412;
else
next_state <= s407;
end if;
when s409 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s409;
end if;
when s412 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s412;
end if;
when s413 =>
if (rdy_i = '1') then
next_state <= s416;
else
next_state <= s413;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
next_state <= s418;
else
next_state <= s416;
end if;
when s418 =>
next_state <= FETCH;
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s565;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s560;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s553;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s558;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s561;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s510;
end if;
when s553 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s553;
end if;
when s555 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s555;
end if;
when s558 =>
if (rdy_i = '1') then
next_state <= s566;
else
next_state <= s558;
end if;
when s560 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s560;
end if;
when s561 =>
if (rdy_i = '1') then
next_state <= s563;
else
next_state <= s561;
end if;
when s563 =>
if (rdy_i = '1') then
next_state <= s553;
else
next_state <= s563;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s565;
else
next_state <= s564;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s565;
end if;
when s566 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s566;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s301;
else
next_state <= s266;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s302;
else
next_state <= s301;
end if;
when s302 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s302;
end if;
when RES =>
next_state <= s544;
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s574;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s569;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s559;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s562;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s567;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s568;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s570;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s511;
end if;
when s559 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s559;
end if;
when s562 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s562;
end if;
when s567 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s567;
end if;
when s568 =>
if (rdy_i = '1') then
next_state <= s571;
else
next_state <= s568;
end if;
when s569 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s569;
end if;
when s570 =>
if (rdy_i = '1') then
next_state <= s572;
else
next_state <= s570;
end if;
when s571 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s571;
end if;
when s572 =>
if (rdy_i = '1') then
next_state <= s559;
else
next_state <= s572;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s574;
else
next_state <= s573;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s574;
end if;
when s548 =>
if (rdy_i = '1') then
next_state <= s551;
else
next_state <= s548;
end if;
when s551 =>
next_state <= s552;
when s552 =>
next_state <= s576;
when s575 =>
if (rdy_i = '1') then
next_state <= s577;
else
next_state <= s575;
end if;
when s576 =>
next_state <= s575;
when s577 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s577;
end if;
when s532 =>
if (rdy_i = '1') then
next_state <= s533;
else
next_state <= s532;
end if;
when s533 =>
next_state <= s534;
when s534 =>
next_state <= s536;
when s535 =>
if (rdy_i = '1') then
next_state <= s537;
else
next_state <= s535;
end if;
when s536 =>
next_state <= s535;
when s537 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s537;
end if;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_i,
d_regs_out_i,
irq_n_i,
nmi_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
reg_sel_pc_as,
reg_sel_pc_in,
reg_sel_pc_val,
reg_sel_rb_in,
reg_sel_rb_out,
reg_sel_reg,
reg_sel_sp_as,
reg_sel_sp_in,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1
)
-----------------------------------------------------------------
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
fetch_o <= '0';
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
sel_pc_as_o <= reg_sel_pc_as;
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
sel_rb_out_o <= reg_sel_rb_out;
sel_reg_o <= reg_sel_reg;
sel_sp_as_o <= reg_sel_sp_as;
sel_sp_in_o <= reg_sel_sp_in;
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '1';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"00";
zw_ALU2 <= '0' & X"00";
zw_ALU3 <= '0' & X"00";
zw_ALU4 <= '0' & X"00";
zw_ALU5 <= '0' & X"00";
zw_ALU6 <= '0' & X"00";
-- Combined Actions
case current_state is
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
if ((nmi_i = '1') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s1 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s2 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s5 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s3 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s12 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s16 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s17 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s24 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s25 =>
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s273 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s307 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s180 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s181 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s182 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s183 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s184 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s185 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s187 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s188 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s189 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s190 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
when s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
when s193 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s377 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s381 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s378 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s382 =>
sig_SYNC <= '1';
fetch_o <= '1';
when s379 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s384 =>
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s380 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s386 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s387 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s388 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s389 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s392 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s390 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s393 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s395 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s396 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s397 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s398 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s401 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s526 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
when s530 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s544 =>
ld_o <= "11";
ld_sp_o <= '1';
when s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
when s546 =>
ld_o <= "11";
ld_pc_o <= '1';
when s549 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s550 =>
ld_o <= "11";
ld_sp_o <= '1';
when s404 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s556 =>
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s557 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s579 =>
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s202 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s210 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s211 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s215 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s217 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s222 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s223 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s243 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s244 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s247 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s343 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s250 =>
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s361 =>
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s360 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s406 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s407 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s409 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
fetch_o <= '1';
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s553 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s555 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s558 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s560 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s563 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s566 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s302 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s559 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s562 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s567 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s568 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s569 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s571 =>
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s572 =>
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s548 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s551 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s552 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s577 =>
if (rdy_i = '1') then
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when s532 =>
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s533 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s534 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s537 =>
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
fetch_o <= '1';
end if;
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
end fsm;
| gpl-2.0 | 0a753016d6bf60cb77eb09e439bf3674 | 0.329443 | 3.285573 | false | false | false | false |
545/Atari7800 | tia/sound_interface/clocking.vhd | 3 | 7,963 | -- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
| gpl-2.0 | d6df68fcfb4b47f650ebee6fd2716033 | 0.570639 | 4.195469 | false | false | false | false |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM_1/synth/BIOS_ROM.vhd | 2 | 14,010 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY BIOS_ROM IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END BIOS_ROM;
ARCHITECTURE BIOS_ROM_arch OF BIOS_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF BIOS_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF BIOS_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF BIOS_ROM_arch : ARCHITECTURE IS "BIOS_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF BIOS_ROM_arch: ARCHITECTURE IS "BIOS_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=BIOS_ROM.mif,C_INIT_FILE=BIOS_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "BIOS_ROM.mif",
C_INIT_FILE => "BIOS_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END BIOS_ROM_arch;
| gpl-2.0 | 57b30e57d574fc07ab01231847ad82f6 | 0.625054 | 3.022654 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_1/synth/DIGDUG_ROM.vhd | 1 | 13,930 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DIGDUG_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DIGDUG_ROM;
ARCHITECTURE DIGDUG_ROM_arch OF DIGDUG_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DIGDUG_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DIGDUG_ROM_arch : ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=DIGDUG_ROM.mif,C_INIT_FILE=DIGDUG_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "DIGDUG_ROM.mif",
C_INIT_FILE => "DIGDUG_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DIGDUG_ROM_arch;
| gpl-2.0 | da570878d2df18a698eac8508c58b6f1 | 0.625197 | 3.028919 | false | false | false | false |
aurabindo/altersync | synchro_tb.vhd | 1 | 2,702 | --------------------------------------------------------------------------------
--Author: Jay Aurabind
--Email : [email protected]
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT synchro
PORT(
x1 : IN std_logic;
x2 : IN std_logic;
x3 : IN std_logic;
y1 : IN std_logic;
y2 : IN std_logic;
y3 : IN std_logic;
vcomp : IN std_logic;
rst : IN std_logic;
clock : IN std_logic;
phase : INOUT std_logic;
freq : INOUT std_logic;
voltage : INOUT std_logic;
inst : OUT std_logic
);
END COMPONENT;
--signals
signal x1 : std_logic;
signal x2 : std_logic;
signal x3 : std_logic;
signal y1 : std_logic;
signal y2 : std_logic;
signal y3 : std_logic;
signal vcomp : std_logic;
signal rst : std_logic;
signal CLK_I : std_logic;
signal phase : std_logic;
signal freq : std_logic;
signal voltage : std_logic;
signal inst : std_logic;
--constants
constant CLK_I_period : time := 10 ns;
BEGIN
-- Component Instantiation
Inst_synchro: synchro PORT MAP(
x1 => x1,
x2 => x2,
x3 => x3,
y1 => y1,
y2 => y2,
y3 => y3,
vcomp => vcomp,
rst => rst,
phase => phase ,
freq => freq ,
voltage => voltage,
inst => inst,
clock => CLK_I);
-- Test Bench Statements
CLK_I_process :process
begin
CLK_I <= '0';
wait for CLK_I_period/2;
CLK_I <= '1';
wait for CLK_I_period/2;
end process;
-- Stimulus process
process
begin
x1 <= '0';
wait for CLK_I_period*30;
x1 <= '1';
wait for CLK_I_period*30;
end process;
process
begin
wait for 20 ns;
x2 <= '0';
wait for CLK_I_period*30;
x2 <= '1';
wait for CLK_I_period*30;
end process;
process
begin
wait for 40 ns;
x3 <= '0';
wait for CLK_I_period*30;
x3 <= '1';
wait for CLK_I_period*30;
end process;
--for y's
process
begin
y1 <= '0';
wait for (CLK_I_period*30);
wait for 25 ns;
y1 <= '1';
wait for (CLK_I_period*30) + 25 ns;
end process;
process
begin
wait for 20 ns;
y2 <= '0';
wait for (CLK_I_period*30) + 25 ns;
y2 <= '1';
wait for (CLK_I_period*30) + 25 ns;
end process;
process
begin
wait for 40 ns;
y3 <= '0';
wait for (CLK_I_period*30) + 25 ns;
y3 <= '1';
wait for (CLK_I_period*30) + 25 ns;
end process;
-- break
process
begin
vcomp <= '1';
wait for 100 ns;
rst <= '1';
wait for 100 ns;
rst <= '0';
wait;
end process;
END;
| lgpl-3.0 | 5fb3a765907255d22d3f5952e7302bda | 0.541821 | 2.850211 | false | false | false | false |
jhladky/ratload | RAT_CPU/flag_reg.vhd | 1 | 1,510 | --
-- A flip-flop to store the the zero, carry, and interrupt flags.
-- To be used in the RAT CPU.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity flag_reg is
Port ( IN_FLAG : in STD_LOGIC; --flag input
LD : in STD_LOGIC; --load the out_flag with the in_flag value
SET : in STD_LOGIC; --set the flag to '1'
CLR : in STD_LOGIC; --clear the flag to '0'
RESTORE : in STD_LOGIC; --interrupt complete; restore flag from shadow
SAVE : in STD_LOGIC; --interrupt received; store flag into shadow
CLK : in STD_LOGIC; --system clock
OUT_FLAG : out STD_LOGIC); --flag output
end flag_reg;
architecture flag_reg_a of flag_reg is
signal out_flag_i : std_logic := '0';
signal shadow_flag_i : std_logic := '0';
begin
process(CLK) begin
if( rising_edge(CLK) ) then
if( LD = '1' ) then
out_flag_i <= IN_FLAG;
elsif( SET = '1' ) then
out_flag_i <= '1';
elsif( CLR = '1' ) then
out_flag_i <= '0';
elsif(RESTORE = '1') then
out_flag_i <= shadow_flag_i;
end if;
end if;
end process;
process(CLK) begin
if( rising_edge(CLK) ) then
if SAVE = '1' then
shadow_flag_i <= out_flag_i;
end if;
end if;
end process;
OUT_FLAG <= out_flag_i;
end flag_reg_a;
| mit | 76ab44dc2b12db73a9a3bfaa08079f46 | 0.503974 | 3.431818 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/JOUST_ROM/synth/JOUST_ROM.vhd | 1 | 13,915 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY JOUST_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END JOUST_ROM;
ARCHITECTURE JOUST_ROM_arch OF JOUST_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF JOUST_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF JOUST_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF JOUST_ROM_arch : ARCHITECTURE IS "JOUST_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF JOUST_ROM_arch: ARCHITECTURE IS "JOUST_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=JOUST_ROM.mif,C_INIT_FILE=JOUST_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "JOUST_ROM.mif",
C_INIT_FILE => "JOUST_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END JOUST_ROM_arch;
| gpl-2.0 | e98054df46f29369247f53423be6aa79 | 0.624793 | 3.021716 | false | false | false | false |
jhladky/ratload | RAT_CPU/cu.vhd | 1 | 22,232 | ----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer: Jacob Hladky and Curtis Jonaitis
-- -------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity control_unit is
port( CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RST : in STD_LOGIC;
--From the instruction register:
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
--Program counter
PC_LD : out STD_LOGIC; --Load program counter
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0); --Program counter mux
PC_OE : out STD_LOGIC; --Program counter output enable
--Stack Pointer
SP_LD : out STD_LOGIC; --stack pointer load
INC_DEC : out STD_LOGIC_VECTOR (1 downto 0); --SP input mux
--Reset to program counter and stack pointer
RESET : out STD_LOGIC; --Reset program counter and stack pointer
--Register File
RF_WR : out STD_LOGIC; --Reg File Write Enable
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0); --Reg File Mux
RF_OE : out STD_LOGIC; --Register File Tristate Ooutput
--ALU
ALU_MUX_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
--Scratchpad RAM
SCR_WR : out STD_LOGIC; --scratchpad write enable
SCR_OE : out STD_LOGIC; --sp output enable
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0); --sp mux sel
--C Flag
C_FLAG_RESTORE: out STD_LOGIC;
C_FLAG_SAVE : out STD_LOGIC;
C_FLAG_LD : out STD_LOGIC;
C_FLAG_SET : out STD_LOGIC;
C_FLAG_CLR : out STD_LOGIC;
--Z Flag
Z_FLAG_RESTORE: out STD_LOGIC;
Z_FLAG_SAVE : out STD_LOGIC;
Z_FLAG_LD : out STD_LOGIC; --Load Z
Z_FLAG_SET : out STD_LOGIC; --Set Z
Z_FLAG_CLR : out STD_LOGIC; --Clear Z
--Interrupt Flag
I_FLAG_SET : out STD_LOGIC; --Set Interrupt
I_FLAG_CLR : out STD_LOGIC; --Clear Interrupt
--I/O Output Enable
IO_OE : out STD_LOGIC);
end control_unit;
architecture control_unit_a of control_unit is
type state_type is (ST_init, ST_fet, ST_exec, ST_int);
signal PS,NS : state_type;
signal int_ast_i : std_logic := '0';
signal int_set_i : std_logic := '0';
signal int_clr_i : std_logic := '0';
begin
--synchronous process of statemachine
--intializes present state to ST_init
--on clock edge, PS updates to NS
sync_p: process (CLK, RST) begin
if (RST = '1') then
PS <= ST_init;
elsif (rising_edge(CLK)) then
PS <= NS;
if(int_set_i = '1') then
int_ast_i <= '1';
elsif(int_clr_i = '1') then
int_ast_i <= '0';
end if;
end if;
end process sync_p;
-- asynchronous process to determine NS and set all output signals
comb_p: process (opcode_hi_5, opcode_lo_2, PS, NS, z, c, int, int_set_i, int_clr_i, int_ast_i) begin
int_set_i <= '0';
int_clr_i <= '0';
case PS is
-- STATE: the init cycle ------------------------------------
-- Initialize all control outputs to non-active states and reset the PC and SP to all zeros.
when ST_init =>
NS <= ST_fet;
int_clr_i <= '1';
RESET <= '1';
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_OE <= '0';
SP_LD <= '0'; INC_DEC <= "00";
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
ALU_MUX_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00"; C_FLAG_SAVE <= '0';
C_FLAG_RESTORE <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '1';
Z_FLAG_RESTORE <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '1';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '1'; Z_FLAG_SAVE <= '0'; IO_OE <= '0';
-- STATE: the fetch cycle -----------------------------------
-- Set all control outputs to the values needed for fetch
when ST_fet =>
NS <= ST_exec;
if(INT = '1') then
int_set_i <= '1';
end if;
RESET <= '0';
PC_LD <= '1'; PC_MUX_SEL <= "00"; PC_OE <= '0';
SP_LD <= '0'; INC_DEC <= "00";
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
ALU_MUX_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00"; C_FLAG_SAVE <= '0';
C_FLAG_RESTORE <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0';
Z_FLAG_RESTORE <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; Z_FLAG_SAVE <= '0'; IO_OE <= '0';
-- STATE: the execute cycle ---------------------------------
when ST_exec =>
if(INT = '1' or int_ast_i = '1') then
NS <= ST_int;
int_clr_i <= '1';
else
NS <= ST_fet;
end if;
-- Repeat the init block for all variables here, noting that any output values desired to be different
-- from init values shown below will be assigned in the following case statements for each opcode.
RESET <= '0';
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_OE <= '0';
SP_LD <= '0'; INC_DEC <= "00";
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
ALU_MUX_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00"; C_FLAG_SAVE <= '0';
C_FLAG_RESTORE <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0';
Z_FLAG_RESTORE <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; Z_FLAG_SAVE <= '0'; IO_OE <= '0';
case OPCODE_HI_5 is
-- Could be AND, OR, EXOR, or TEST
when "00000" =>
-- AND (reg/reg)
if(OPCODE_LO_2 = "00") then
ALU_SEL <= x"5"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- OR (reg/reg)
elsif(OPCODE_LO_2 = "01") then
ALU_SEL <= x"a"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- EXOR (reg/reg)
elsif(OPCODE_LO_2 = "10") then
ALU_SEL <= x"7"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- TEST (reg/reg)
else
ALU_SEL <= x"d"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
end if;
-- Could be ADD, ADDC, SUB, or SUBC
when "00001" =>
-- ADD (reg/reg)
if(OPCODE_LO_2 = "00") then
ALU_SEL <= x"0"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- ADDC (reg/reg)
elsif(OPCODE_LO_2 = "01") then
ALU_SEL <= x"1"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- SUB (reg/reg)
elsif(OPCODE_LO_2 = "10") then
ALU_SEL <= x"3"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- SUBC (reg/reg)
else
ALU_SEL <= x"4"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
end if;
-- Could be CMP, MOV, LD, or ST (all reg/reg)
when "00010" =>
-- CMP (reg/reg)
if(OPCODE_LO_2 = "00") then
ALU_SEL <= x"2"; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_OE <= '1'; --RF_WR <= '1'; --do NOT write back to REG!!!!!!
C_FLAG_LD <= '1';
-- MOV (reg/reg)
elsif(OPCODE_LO_2 = "01") then
ALU_SEL <= x"e";
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- LD (reg/reg)
elsif(OPCODE_LO_2 = "10") then
SCR_ADDR_SEL <= "11"; SCR_OE <= '1'; RF_WR <= '1';
RF_WR_SEL <= "01";
-- ST (reg/reg)
else
SCR_ADDR_SEL <= "11"; SCR_WR <= '1'; RF_OE <= '1';
end if;
-- Could be BRN, CALL, BREQ, or BRNE
when "00100" =>
-- BRN (no other form)
-- Unditional branch. Add only the signals that will change FROM THE INIT BLOCK
if(OPCODE_LO_2 = "00") then
PC_MUX_SEL <= "01"; PC_LD <= '1';
-- CALL (no other form)
-- Call a function
elsif(OPCODE_LO_2 = "01") then
PC_MUX_SEL <= "01"; PC_OE <= '1'; SCR_WR <= '1';
SCR_ADDR_SEL <= "10"; INC_DEC <= "01"; PC_LD <= '1';
-- BREQ (no other form)
-- Branch if zero set
elsif(OPCODE_LO_2 = "10") then
if(z = '1') then
PC_MUX_SEL <= "01";
PC_LD <= '1';
end if;
-- BRNE (no other form)
-- Branch if zero cleared
else
if(z = '0') then
PC_MUX_SEL <= "01";
PC_LD <= '1';
end if;
end if;
-- Could be BRCS or BRCC
when "00101" =>
-- BRCS (no other form)
-- Branch if carry set
if(OPCODE_LO_2 = "00") then
if(c = '1') then
PC_MUX_SEL <= "01";
PC_LD <= '1';
end if;
-- BRCC (no other form)
-- Branch if carry cleared
else
if(c = '0') then
PC_MUX_SEL <= "01";
PC_LD <= '1';
end if;
end if;
-- Could be LSL, LSR, ROL, or ROR
when "01000" =>
-- LSL (no other form)
if(OPCODE_LO_2 = "00") then
ALU_SEL <= x"8"; C_FLAG_LD <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- LSR (no other form)
elsif(OPCODE_LO_2 = "01") then
ALU_SEL <= x"9"; C_FLAG_LD <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- ROL (no other form)
elsif(OPCODE_LO_2 = "10") then
ALU_SEL <= x"b"; C_FLAG_LD <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- ROR (no other form)
else
ALU_SEL <= x"c"; C_FLAG_LD <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
end if;
-- Could be ASR, PUSH, or POP
when "01001" =>
-- ASR (no other form)
-- Arithmetic shift right
if(OPCODE_LO_2 = "00") then
ALU_SEL <= x"6"; C_FLAG_LD <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- PUSH (no other form)
-- Push a value onto the stack
elsif(OPCODE_LO_2 = "01") then
RF_OE <= '1'; SCR_ADDR_SEL <= "10"; SCR_WR <= '1';
INC_DEC <= "01";
-- POP (no other form)
-- Pop a value from the stack
elsif(OPCODE_LO_2 = "10") then
SCR_OE <= '1'; RF_WR <= '1'; RF_WR_SEL <= "01";
INC_DEC <= "10"; SCR_ADDR_SEL <= "01";
end if;
-- Could be CLC, SEC, RET, or RETI
when "01100" =>
-- CLC (no other form)
-- Clear the carry flag
if(OPCODE_LO_2 = "00") then
C_FLAG_CLR <= '1';
-- SEC (no other form)
-- Set the carry flag
elsif(OPCODE_LO_2 = "01") then
C_FLAG_SET <= '1';
-- RET (no other form)
-- Return from a function
elsif(OPCODE_LO_2 = "10") then
SCR_OE <= '1'; PC_MUX_SEL <= "10"; PC_LD <= '1';
INC_DEC <= "10"; SCR_ADDR_SEL <= "01";
-- RETI (no other form)
else
-- unclear if this is actually a command being used
end if;
-- Could be SEI, CLI, RETID, or RETIE
when "01101" =>
-- SEI (no other form)
-- Set the interrupt flag
if(OPCODE_LO_2 = "00") then
I_FLAG_SET <= '1';
-- CLI (no other form)
-- Clear the interrupt clag
elsif(OPCODE_LO_2 = "01") then
I_FLAG_CLR <= '1';
-- RETID (no other form)
-- Return with interrupts disabled
elsif(OPCODE_LO_2 = "10") then
SCR_OE <= '1'; PC_MUX_SEL <= "10"; PC_LD <= '1';
INC_DEC <= "10"; SCR_ADDR_SEL <= "01"; I_FLAG_CLR <= '1';
C_FLAG_RESTORE <= '1'; Z_FLAG_RESTORE <= '1';
-- RETIE (no other form)
-- Return with interrupts enabled
else
SCR_OE <= '1'; PC_MUX_SEL <= "10"; PC_LD <= '1';
INC_DEC <= "10"; SCR_ADDR_SEL <= "01"; I_FLAG_SET <= '1';
C_FLAG_RESTORE <= '1'; Z_FLAG_RESTORE <= '1';
end if;
-- AND (reg/immed)
when "10000" =>
ALU_SEL <= x"5"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- OR (reg/immed)
when "10001" =>
ALU_SEL <= x"a"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- EXOR (reg/immed)
when "10010" =>
ALU_SEL <= x"7"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- TEST (reg/immed)
when "10011" =>
ALU_SEL <= x"d"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
-- ADD (reg/immed)
when "10100" =>
ALU_SEL <= x"0"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- ADDC (reg/immed)
when "10101" =>
ALU_SEL <= x"1"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- SUB (reg/immed)
when "10110" =>
ALU_SEL <= x"3"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- SUBC (reg/immed)
when "10111" =>
ALU_SEL <= x"4"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_WR <= '1'; RF_OE <= '1';
C_FLAG_LD <= '1';
-- CMP (reg/immed)
when "11000" =>
ALU_SEL <= x"2"; ALU_MUX_SEL <= '1'; Z_FLAG_LD <= '1';
RF_WR_SEL <= "10"; RF_OE <= '1'; -- RF_WR<= '1'; DO NOT WRITE BACK TO REG!!!
C_FLAG_LD <= '1';
-- IN (no other form)
when "11001" =>
RF_WR <= '1';
-- OUT (no other form)
when "11010" =>
RF_OE <= '1'; IO_OE <= '1';
-- MOV (reg/immed)
when "11011" =>
RF_WR <= '1'; RF_WR_SEL <= "10"; RF_OE <= '1';
ALU_MUX_SEL <= '1'; ALU_SEL <= x"e";
-- LD (reg/immed)
when "11100" =>
SCR_ADDR_SEL <= "00"; SCR_OE <= '1'; RF_WR <= '1';
RF_WR_SEL <= "01";
-- ST (reg/immed)
when "11101" =>
SCR_ADDR_SEL <= "00"; SCR_WR <= '1'; RF_OE <= '1';
-- WSP (no other form)
when "01010" =>
RF_OE <= '1'; SP_LD <= '1';
when others =>
-- repeat the init block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
RESET <= '0';
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_OE <= '0';
SP_LD <= '0'; INC_DEC <= "00";
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
ALU_MUX_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00"; C_FLAG_SAVE <= '0';
C_FLAG_RESTORE <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0';
Z_FLAG_RESTORE <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; Z_FLAG_SAVE <= '0'; IO_OE <= '0';
end case;
-- STATE: the interrupt cycle -----------------------------------
-- Do interrupt shit here @ the 3FF, yo
when ST_int =>
NS <= ST_fet;
RESET <= '0';
PC_LD <= '1'; PC_MUX_SEL <= "11"; PC_OE <= '1'; -- ok
SP_LD <= '0'; INC_DEC <= "01"; -- ok
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0'; -- ok
ALU_MUX_SEL <= '0'; ALU_SEL <= "0000"; -- ok
SCR_WR <= '1'; SCR_OE <= '0'; SCR_ADDR_SEL <= "10"; C_FLAG_SAVE <= '1'; -- ok
C_FLAG_RESTORE <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0'; -- ok
Z_FLAG_RESTORE <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0'; -- ok
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; Z_FLAG_SAVE <= '1'; IO_OE <= '0'; -- ok
when others =>
NS <= ST_fet;
-- repeat the init block here to avoid incompletely specified outputs and hence avoid
-- the problem of inadvertently created latches within the synthesized system.
RESET <= '0';
PC_LD <= '0'; PC_MUX_SEL <= "00"; PC_OE <= '0';
SP_LD <= '0'; INC_DEC <= "00";
RF_WR <= '0'; RF_WR_SEL <= "00"; RF_OE <= '0';
ALU_MUX_SEL <= '0'; ALU_SEL <= "0000";
SCR_WR <= '0'; SCR_OE <= '0'; SCR_ADDR_SEL <= "00"; C_FLAG_SAVE <= '0';
C_FLAG_RESTORE <= '0'; C_FLAG_LD <= '0'; C_FLAG_SET <= '0'; C_FLAG_CLR <= '0';
Z_FLAG_RESTORE <= '0'; Z_FLAG_LD <= '0'; Z_FLAG_SET <= '0'; Z_FLAG_CLR <= '0';
I_FLAG_SET <= '0'; I_FLAG_CLR <= '0'; Z_FLAG_SAVE <= '0'; IO_OE <= '0';
end case;
end process comb_p;
end control_unit_a;
| mit | db6a75c68d16406f6d696d429ac68646 | 0.345358 | 3.591599 | false | false | false | false |
MonsieurOenologue/Paprotto | shiftreg.vhd | 1 | 447 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY shiftreg IS
PORT(
clk, din, rst : IN std_logic;
dout : OUT std_logic
);
END ENTITY shiftreg;
ARCHITECTURE behavior OF shiftreg IS
SIGNAL sint: std_logic;
BEGIN
PROCESS (clk, rst)
BEGIN
if rst='1' THEN
dout <= (others => '0');
elsif clk = '1' AND clk'EVENT THEN
sint <= din;
dout <= sint;
end if;
END PROCESS;
END behavior;
| gpl-3.0 | 62ac1bd7234d9f3a27a5c3177c96a5c8 | 0.588367 | 3.262774 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/MARIO_ROM/synth/MARIO_ROM.vhd | 1 | 13,913 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY MARIO_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MARIO_ROM;
ARCHITECTURE MARIO_ROM_arch OF MARIO_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MARIO_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF MARIO_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF MARIO_ROM_arch : ARCHITECTURE IS "MARIO_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF MARIO_ROM_arch: ARCHITECTURE IS "MARIO_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=MARIO_ROM.mif,C_INIT_FILE=MARIO_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=65536,C_READ_DEPTH_A=65536,C_ADDRA_WIDTH=16,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=65536,C_READ_DEPTH_B=65536,C_ADDRB_WIDTH=16,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 17.198 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "MARIO_ROM.mif",
C_INIT_FILE => "MARIO_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 65536,
C_READ_DEPTH_A => 65536,
C_ADDRA_WIDTH => 16,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 65536,
C_READ_DEPTH_B => 65536,
C_ADDRB_WIDTH => 16,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "16",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 17.198 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END MARIO_ROM_arch;
| gpl-2.0 | bfde39f8b154dca82884fee1cdc41663 | 0.624739 | 3.021281 | false | false | false | false |
id101010/vhdl-irdecoder | hex2seg_tb.vhd | 1 | 2,270 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hex2seg_tb IS
END hex2seg_tb;
ARCHITECTURE behavior OF hex2seg_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hex2seg
PORT(
clk : IN std_logic;
en : in std_logic;
hex : IN std_logic_vector(3 downto 0);
seg : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal en: std_logic := '0';
signal hex : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal seg : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hex2seg PORT MAP (
clk => clk,
en => en,
hex => hex,
seg => seg
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
--Test if nothing happens if enabled is on '0'
en <= '0';
hex <= "0001";
wait for clk_period*10;
-- Test decoding of hex numbers 0-F
en <= '1';
hex <= "0000";
wait for clk_period*10;
hex <= "0001";
wait for clk_period*10;
hex <= "0010";
wait for clk_period*10;
hex <= "0011";
wait for clk_period*10;
hex <= "0100";
wait for clk_period*10;
hex <= "0101";
wait for clk_period*10;
hex <= "0110";
wait for clk_period*10;
hex <= "0111";
wait for clk_period*10;
hex <= "1000";
wait for clk_period*10;
hex <= "1001";
wait for clk_period*10;
hex <= "1010";
wait for clk_period*10;
hex <= "1011";
wait for clk_period*10;
hex <= "1100";
wait for clk_period*10;
hex <= "1101";
wait for clk_period*10;
hex <= "1110";
wait for clk_period*10;
hex <= "1111";
wait;
end process;
END;
| lgpl-3.0 | 37750d72eb702d64ac4fe7a866faff41 | 0.537445 | 3.649518 | false | false | false | false |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/ip/ram0/synth/ram0.vhd | 1 | 14,182 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY ram0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram0;
ARCHITECTURE ram0_arch OF ram0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ram0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ram0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ram0_arch : ARCHITECTURE IS "ram0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ram0_arch: ARCHITECTURE IS "ram0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=ram0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=bf,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 1.3396 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "ram0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "bf",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 1.3396 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ram0_arch;
| gpl-2.0 | c527debc62ed857ca9aa1f9f11b6d5d2 | 0.626146 | 3.025171 | false | false | false | false |
545/Atari7800 | core/cpu6502_true_cycle/trunk/rtl/vhdl/fsm_execution_unit.vhd | 1 | 185,772 | -- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 15:57:20 20.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY FSM_Execution_Unit IS
PORT(
adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_pc_i : IN std_logic_vector (15 DOWNTO 0);
adr_sp_i : IN std_logic_vector (15 DOWNTO 0);
clk_clk_i : IN std_logic;
d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_i : IN std_logic_vector ( 7 DOWNTO 0 );
d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );
irq_n_i : IN std_logic;
nmi_i : IN std_logic;
q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );
q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );
rdy_i : IN std_logic;
reg_0flag_i : IN std_logic;
reg_1flag_i : IN std_logic;
reg_7flag_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
adr_o : OUT std_logic_vector (15 DOWNTO 0);
ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_o : OUT std_logic_vector ( 7 DOWNTO 0 );
d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );
ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );
ld_pc_o : OUT std_logic;
ld_sp_o : OUT std_logic;
load_regs_o : OUT std_logic;
offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );
rd_o : OUT std_logic;
rst_nmi_o : OUT std_logic;
sel_pc_in_o : OUT std_logic;
sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );
sel_sp_as_o : OUT std_logic;
sel_sp_in_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
-- Declarations
END FSM_Execution_Unit ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: fsm.sm,v $
-- <<-- more -->>
-- Title: FSM Execution Unit for all op codes
-- Path: R6502_TC/FSM_Execution_Unit/fsm
-- Edited: by eda on 20 Feb 2010
--
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 15:57:21 20.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE fsm OF FSM_Execution_Unit IS
-- Architecture Declarations
SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
SIGNAL reg_sel_pc_in : std_logic;
SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
SIGNAL reg_sel_sp_as : std_logic;
SIGNAL reg_sel_sp_in : std_logic;
SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
SIGNAL sig_RD : std_logic;
SIGNAL sig_RWn : std_logic;
SIGNAL sig_SYNC : std_logic;
SIGNAL sig_WR : std_logic;
SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL zw_so : std_logic;
SUBTYPE STATE_TYPE IS
std_logic_vector(7 DOWNTO 0);
-- Hard encoding
CONSTANT FETCH : STATE_TYPE := "00000000";
CONSTANT s1 : STATE_TYPE := "00000001";
CONSTANT s2 : STATE_TYPE := "00000011";
CONSTANT s5 : STATE_TYPE := "00000010";
CONSTANT s3 : STATE_TYPE := "00000110";
CONSTANT s4 : STATE_TYPE := "00000111";
CONSTANT s12 : STATE_TYPE := "00000101";
CONSTANT s16 : STATE_TYPE := "00000100";
CONSTANT s17 : STATE_TYPE := "00001100";
CONSTANT s24 : STATE_TYPE := "00001101";
CONSTANT s25 : STATE_TYPE := "00001111";
CONSTANT s271 : STATE_TYPE := "00001110";
CONSTANT s273 : STATE_TYPE := "00001010";
CONSTANT s304 : STATE_TYPE := "00001011";
CONSTANT s307 : STATE_TYPE := "00001001";
CONSTANT s177 : STATE_TYPE := "00001000";
CONSTANT s180 : STATE_TYPE := "00011000";
CONSTANT s181 : STATE_TYPE := "00011001";
CONSTANT s182 : STATE_TYPE := "00011011";
CONSTANT s183 : STATE_TYPE := "00011010";
CONSTANT s184 : STATE_TYPE := "00011110";
CONSTANT s185 : STATE_TYPE := "00011111";
CONSTANT s186 : STATE_TYPE := "00011101";
CONSTANT s187 : STATE_TYPE := "00011100";
CONSTANT s188 : STATE_TYPE := "00010100";
CONSTANT s189 : STATE_TYPE := "00010101";
CONSTANT s190 : STATE_TYPE := "00010111";
CONSTANT s191 : STATE_TYPE := "00010110";
CONSTANT s192 : STATE_TYPE := "00010010";
CONSTANT s193 : STATE_TYPE := "00010011";
CONSTANT s377 : STATE_TYPE := "00010001";
CONSTANT s381 : STATE_TYPE := "00010000";
CONSTANT s378 : STATE_TYPE := "00110000";
CONSTANT s382 : STATE_TYPE := "00110001";
CONSTANT s379 : STATE_TYPE := "00110011";
CONSTANT s383 : STATE_TYPE := "00110010";
CONSTANT s384 : STATE_TYPE := "00110110";
CONSTANT s380 : STATE_TYPE := "00110111";
CONSTANT s385 : STATE_TYPE := "00110101";
CONSTANT s386 : STATE_TYPE := "00110100";
CONSTANT s387 : STATE_TYPE := "00111100";
CONSTANT s388 : STATE_TYPE := "00111101";
CONSTANT s389 : STATE_TYPE := "00111111";
CONSTANT s391 : STATE_TYPE := "00111110";
CONSTANT s392 : STATE_TYPE := "00111010";
CONSTANT s390 : STATE_TYPE := "00111011";
CONSTANT s393 : STATE_TYPE := "00111001";
CONSTANT s394 : STATE_TYPE := "00111000";
CONSTANT s395 : STATE_TYPE := "00101000";
CONSTANT s396 : STATE_TYPE := "00101001";
CONSTANT s397 : STATE_TYPE := "00101011";
CONSTANT s398 : STATE_TYPE := "00101010";
CONSTANT s399 : STATE_TYPE := "00101110";
CONSTANT s400 : STATE_TYPE := "00101111";
CONSTANT s401 : STATE_TYPE := "00101101";
CONSTANT s526 : STATE_TYPE := "00101100";
CONSTANT s527 : STATE_TYPE := "00100100";
CONSTANT s528 : STATE_TYPE := "00100101";
CONSTANT s529 : STATE_TYPE := "00100111";
CONSTANT s530 : STATE_TYPE := "00100110";
CONSTANT s531 : STATE_TYPE := "00100010";
CONSTANT s544 : STATE_TYPE := "00100011";
CONSTANT s545 : STATE_TYPE := "00100001";
CONSTANT s546 : STATE_TYPE := "00100000";
CONSTANT s547 : STATE_TYPE := "01100000";
CONSTANT s549 : STATE_TYPE := "01100001";
CONSTANT s550 : STATE_TYPE := "01100011";
CONSTANT s404 : STATE_TYPE := "01100010";
CONSTANT s556 : STATE_TYPE := "01100110";
CONSTANT s557 : STATE_TYPE := "01100111";
CONSTANT s579 : STATE_TYPE := "01100101";
CONSTANT s201 : STATE_TYPE := "01100100";
CONSTANT s202 : STATE_TYPE := "01101100";
CONSTANT s210 : STATE_TYPE := "01101101";
CONSTANT s211 : STATE_TYPE := "01101111";
CONSTANT s215 : STATE_TYPE := "01101110";
CONSTANT s217 : STATE_TYPE := "01101010";
CONSTANT s218 : STATE_TYPE := "01101011";
CONSTANT s222 : STATE_TYPE := "01101001";
CONSTANT s223 : STATE_TYPE := "01101000";
CONSTANT s224 : STATE_TYPE := "01111000";
CONSTANT s225 : STATE_TYPE := "01111001";
CONSTANT s226 : STATE_TYPE := "01111011";
CONSTANT s243 : STATE_TYPE := "01111010";
CONSTANT s244 : STATE_TYPE := "01111110";
CONSTANT s247 : STATE_TYPE := "01111111";
CONSTANT s344 : STATE_TYPE := "01111101";
CONSTANT s343 : STATE_TYPE := "01111100";
CONSTANT s250 : STATE_TYPE := "01110100";
CONSTANT s251 : STATE_TYPE := "01110101";
CONSTANT s351 : STATE_TYPE := "01110111";
CONSTANT s361 : STATE_TYPE := "01110110";
CONSTANT s360 : STATE_TYPE := "01110010";
CONSTANT s403 : STATE_TYPE := "01110011";
CONSTANT s406 : STATE_TYPE := "01110001";
CONSTANT s407 : STATE_TYPE := "01110000";
CONSTANT s409 : STATE_TYPE := "01010000";
CONSTANT s412 : STATE_TYPE := "01010001";
CONSTANT s413 : STATE_TYPE := "01010011";
CONSTANT s416 : STATE_TYPE := "01010010";
CONSTANT s418 : STATE_TYPE := "01010110";
CONSTANT s510 : STATE_TYPE := "01010111";
CONSTANT s553 : STATE_TYPE := "01010101";
CONSTANT s555 : STATE_TYPE := "01010100";
CONSTANT s558 : STATE_TYPE := "01011100";
CONSTANT s560 : STATE_TYPE := "01011101";
CONSTANT s561 : STATE_TYPE := "01011111";
CONSTANT s563 : STATE_TYPE := "01011110";
CONSTANT s564 : STATE_TYPE := "01011010";
CONSTANT s565 : STATE_TYPE := "01011011";
CONSTANT s566 : STATE_TYPE := "01011001";
CONSTANT s266 : STATE_TYPE := "01011000";
CONSTANT s301 : STATE_TYPE := "01001000";
CONSTANT s302 : STATE_TYPE := "01001001";
CONSTANT RES : STATE_TYPE := "01001011";
CONSTANT s511 : STATE_TYPE := "01001010";
CONSTANT s559 : STATE_TYPE := "01001110";
CONSTANT s562 : STATE_TYPE := "01001111";
CONSTANT s567 : STATE_TYPE := "01001101";
CONSTANT s568 : STATE_TYPE := "01001100";
CONSTANT s569 : STATE_TYPE := "01000100";
CONSTANT s570 : STATE_TYPE := "01000101";
CONSTANT s571 : STATE_TYPE := "01000111";
CONSTANT s572 : STATE_TYPE := "01000110";
CONSTANT s573 : STATE_TYPE := "01000010";
CONSTANT s574 : STATE_TYPE := "01000011";
CONSTANT s548 : STATE_TYPE := "01000001";
CONSTANT s551 : STATE_TYPE := "01000000";
CONSTANT s552 : STATE_TYPE := "11000000";
CONSTANT s575 : STATE_TYPE := "11000001";
CONSTANT s576 : STATE_TYPE := "11000011";
CONSTANT s577 : STATE_TYPE := "11000010";
CONSTANT s578 : STATE_TYPE := "11000110";
-- Declare current and next state signals
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
-- Declare any pre-registered internal signals
SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
SIGNAL rd_o_cld : std_logic ;
SIGNAL sync_o_cld : std_logic ;
SIGNAL wr_n_o_cld : std_logic ;
SIGNAL wr_o_cld : std_logic ;
BEGIN
-----------------------------------------------------------------
clocked_proc : PROCESS (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
BEGIN
IF (rst_rst_n_i = '0') THEN
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
reg_F <= "00000100";
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_rb_in <= "00";
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_sp_as <= '0';
reg_sel_sp_in <= '0';
sig_PC <= X"0000";
zw_REG_OP <= X"00";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_so <= '0';
ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
reg_sel_pc_in <= reg_sel_pc_in;
reg_sel_pc_val <= reg_sel_pc_val;
reg_sel_rb_in <= reg_sel_rb_in;
reg_sel_rb_out <= reg_sel_rb_out;
reg_sel_reg <= reg_sel_reg;
reg_sel_sp_as <= reg_sel_sp_as;
reg_sel_sp_in <= reg_sel_sp_in;
sig_PC <= sig_PC;
zw_REG_OP <= zw_REG_OP;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
-- Combined Actions
CASE current_state IS
WHEN FETCH =>
zw_REG_OP <= d_i;
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
sig_PC <= adr_sp_i;
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
sig_PC <= adr_sp_i;
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"FF";
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
zw_b4 <= X"01";
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
reg_sel_reg <= "10";
reg_sel_rb_in <= "11";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
zw_b1(0) <= reg_F(7);
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
sig_PC <= adr_nxt_pc_i;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "01";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "00";
reg_sel_rb_in <= "11";
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "00";
reg_sel_reg <= "10";
reg_sel_rb_in <= "00";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "10";
reg_sel_reg <= "00";
reg_sel_rb_in <= "01";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "01";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "00";
reg_sel_rb_in <= "10";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
reg_sel_rb_out <= "01";
reg_sel_reg <= "11";
reg_sel_rb_in <= "11";
reg_sel_sp_in <= '1';
reg_sel_sp_as <= '0';
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s3 =>
sig_PC <= adr_pc_i;
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
zw_b1 <= d_i;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
zw_b2 <= d_i;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s184 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s187 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s190 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s191 =>
sig_PC <= zw_b3 & zw_b1;
WHEN s192 =>
sig_PC <= d_i & zw_b1;
WHEN s193 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s381 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s382 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s383 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F <= d_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
reg_F <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
END IF;
WHEN s399 =>
sig_PC <= adr_sp_i;
WHEN s400 =>
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
WHEN s401 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1 (7 downto 0);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s527 =>
sig_PC <= adr_sp_i;
WHEN s528 =>
sig_PC <= adr_sp_i;
WHEN s529 =>
sig_PC <= X"FFFE";
WHEN s530 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
zw_b1 <= d_i;
END IF;
WHEN s544 =>
sig_PC <= adr_sp_i;
WHEN s545 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
WHEN s546 =>
sig_PC <= adr_pc_i;
WHEN s547 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
zw_b1 <= d_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s550 =>
sig_PC <= adr_sp_i;
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "00";
WHEN s404 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
sig_PC <= X"00" & d_i;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
zw_b1 <= d_alu_i;
END IF;
WHEN s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
END IF;
WHEN s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "10";
zw_b2 <= d_i;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN RES =>
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
sig_PC <= adr_nxt_pc_i;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
sig_PC <= X"00" & d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & zw_b1;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1') THEN
sig_PC <= zw_b3 & zw_b1;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
sig_PC <= adr_sp_i;
END IF;
WHEN s551 =>
sig_PC <= adr_sp_i;
WHEN s552 =>
sig_PC <= adr_sp_i;
WHEN s575 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFF";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
reg_F(2) <= '1';
zw_b1 <= d_i;
END IF;
WHEN s576 =>
IF (NMI_i = '1') THEN
sig_PC <= X"FFFA";
ELSE
sig_PC <= X"FFFE";
END IF;
WHEN s577 =>
IF (rdy_i = '1') THEN
sig_PC <= d_i & zw_b1;
reg_sel_pc_in <= '0';
reg_sel_pc_val <= "00";
reg_sel_sp_in <= '0';
reg_sel_sp_as <= '1';
END IF;
WHEN s578 =>
IF (rdy_i = '1') THEN
sig_PC <= X"FFFB";
reg_sel_pc_in <= '1';
reg_sel_pc_val <= "11";
reg_F(2) <= '1';
zw_b1 <= d_i;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
nmi_i,
rdy_i,
reg_F,
zw_REG_OP,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
BEGIN
CASE current_state IS
WHEN FETCH =>
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
next_state <= s548;
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
next_state <= s548;
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
next_state <= s510;
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
next_state <= s266;
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
next_state <= s351;
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
next_state <= s526;
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
next_state <= s12;
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
next_state <= s16;
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
next_state <= s17;
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
next_state <= s24;
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
next_state <= s226;
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
next_state <= s226;
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
next_state <= s25;
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
next_state <= s271;
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
next_state <= s397;
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
next_state <= s201;
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
next_state <= s1;
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
next_state <= s377;
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
next_state <= s378;
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
next_state <= s379;
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
next_state <= s380;
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
next_state <= s403;
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
next_state <= s387;
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
next_state <= s390;
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
next_state <= s511;
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
next_state <= s2;
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
next_state <= s5;
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
next_state <= s3;
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
next_state <= s177;
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
next_state <= s404;
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
next_state <= s556;
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
next_state <= s557;
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
next_state <= s579;
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
next_state <= s4;
ELSIF (rdy_i = '1') THEN
next_state <= s1;
ELSE
next_state <= FETCH;
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s1;
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s2;
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s5;
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s3;
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s4;
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s12;
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s16;
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s17;
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s24;
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s25;
END IF;
WHEN s271 =>
IF (rdy_i = '1' and
zw_REG_OP = X"4C") THEN
next_state <= s307;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6C") THEN
next_state <= s273;
ELSE
next_state <= s271;
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
next_state <= s304;
ELSE
next_state <= s273;
END IF;
WHEN s304 =>
IF (rdy_i = '1') THEN
next_state <= s307;
ELSE
next_state <= s304;
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s307;
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
next_state <= s184;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
next_state <= s185;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
next_state <= s183;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
next_state <= s182;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
next_state <= s180;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
next_state <= s181;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
next_state <= s186;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
next_state <= s185;
ELSE
next_state <= s177;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s180;
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
next_state <= s189;
ELSE
next_state <= s181;
END IF;
WHEN s182 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s182;
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
next_state <= s187;
ELSE
next_state <= s183;
END IF;
WHEN s184 =>
next_state <= FETCH;
WHEN s185 =>
IF (rdy_i = '1') THEN
next_state <= s190;
ELSE
next_state <= s185;
END IF;
WHEN s186 =>
IF (rdy_i = '1') THEN
next_state <= s188;
ELSE
next_state <= s186;
END IF;
WHEN s187 =>
next_state <= FETCH;
WHEN s188 =>
IF (rdy_i = '1') THEN
next_state <= s192;
ELSE
next_state <= s188;
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
next_state <= s191;
ELSE
next_state <= s189;
END IF;
WHEN s190 =>
next_state <= FETCH;
WHEN s191 =>
next_state <= s193;
WHEN s192 =>
next_state <= s193;
WHEN s193 =>
next_state <= FETCH;
WHEN s377 =>
IF (rdy_i = '1') THEN
next_state <= s381;
ELSE
next_state <= s377;
END IF;
WHEN s381 =>
next_state <= FETCH;
WHEN s378 =>
IF (rdy_i = '1') THEN
next_state <= s382;
ELSE
next_state <= s378;
END IF;
WHEN s382 =>
next_state <= FETCH;
WHEN s379 =>
IF (rdy_i = '1') THEN
next_state <= s383;
ELSE
next_state <= s379;
END IF;
WHEN s383 =>
IF (rdy_i = '1') THEN
next_state <= s384;
ELSE
next_state <= s383;
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s384;
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
next_state <= s385;
ELSE
next_state <= s380;
END IF;
WHEN s385 =>
IF (rdy_i = '1') THEN
next_state <= s386;
ELSE
next_state <= s385;
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s386;
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
next_state <= s388;
ELSE
next_state <= s387;
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
next_state <= s389;
ELSE
next_state <= s388;
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
next_state <= s391;
ELSE
next_state <= s389;
END IF;
WHEN s391 =>
IF (rdy_i = '1') THEN
next_state <= s392;
ELSE
next_state <= s391;
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s392;
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
next_state <= s393;
ELSE
next_state <= s390;
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
next_state <= s394;
ELSE
next_state <= s393;
END IF;
WHEN s394 =>
IF (rdy_i = '1') THEN
next_state <= s395;
ELSE
next_state <= s394;
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
next_state <= s396;
ELSE
next_state <= s395;
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s396;
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
next_state <= s398;
ELSE
next_state <= s397;
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
next_state <= s399;
ELSE
next_state <= s398;
END IF;
WHEN s399 =>
next_state <= s400;
WHEN s400 =>
next_state <= s401;
WHEN s401 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s401;
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
next_state <= s527;
ELSE
next_state <= s526;
END IF;
WHEN s527 =>
next_state <= s528;
WHEN s528 =>
next_state <= s529;
WHEN s529 =>
next_state <= s531;
WHEN s530 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s530;
END IF;
WHEN s531 =>
IF (rdy_i = '1') THEN
next_state <= s530;
ELSE
next_state <= s531;
END IF;
WHEN s544 =>
next_state <= s550;
WHEN s545 =>
next_state <= s546;
WHEN s546 =>
next_state <= s547;
WHEN s547 =>
IF (rdy_i = '1') THEN
next_state <= s549;
ELSE
next_state <= s547;
END IF;
WHEN s549 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s549;
END IF;
WHEN s550 =>
next_state <= s545;
WHEN s404 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s404;
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s556;
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s557;
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s579;
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
next_state <= s224;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
next_state <= s217;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
next_state <= s202;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
next_state <= s210;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
next_state <= s211;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
next_state <= s215;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
next_state <= s218;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
next_state <= s217;
ELSE
next_state <= s201;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s202;
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s210;
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s211;
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
next_state <= s223;
ELSE
next_state <= s215;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s217;
END IF;
WHEN s218 =>
IF (rdy_i = '1') THEN
next_state <= s222;
ELSE
next_state <= s218;
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
next_state <= s202;
ELSE
next_state <= s222;
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
next_state <= s225;
ELSE
next_state <= s223;
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s224;
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
next_state <= FETCH;
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s224;
ELSE
next_state <= s225;
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
next_state <= s343;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
next_state <= s247;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
next_state <= s243;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
next_state <= s244;
ELSE
next_state <= s226;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s243;
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
next_state <= s344;
ELSE
next_state <= s244;
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s247;
END IF;
WHEN s344 =>
IF (rdy_i = '1') THEN
next_state <= s343;
ELSE
next_state <= s344;
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
next_state <= s250;
ELSE
next_state <= s343;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
next_state <= s251;
ELSE
next_state <= s250;
END IF;
WHEN s251 =>
next_state <= FETCH;
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
next_state <= s361;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
next_state <= s360;
ELSE
next_state <= s351;
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s361;
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
next_state <= s361;
ELSE
next_state <= s360;
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
next_state <= s407;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
next_state <= s413;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
next_state <= s409;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
next_state <= s406;
ELSE
next_state <= s403;
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s406;
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
next_state <= s412;
ELSE
next_state <= s407;
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s409;
END IF;
WHEN s412 =>
IF (rdy_i = '1') THEN
next_state <= s413;
ELSE
next_state <= s412;
END IF;
WHEN s413 =>
IF (rdy_i = '1') THEN
next_state <= s416;
ELSE
next_state <= s413;
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
next_state <= s418;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
next_state <= s418;
ELSE
next_state <= s416;
END IF;
WHEN s418 =>
next_state <= FETCH;
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
next_state <= s565;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
next_state <= s560;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
next_state <= s553;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
next_state <= s555;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
next_state <= s558;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
next_state <= s561;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s510;
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s553;
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
next_state <= s564;
ELSE
next_state <= s555;
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
next_state <= s566;
ELSE
next_state <= s558;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s560;
END IF;
WHEN s561 =>
IF (rdy_i = '1') THEN
next_state <= s563;
ELSE
next_state <= s561;
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
next_state <= s553;
ELSE
next_state <= s563;
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s565;
ELSE
next_state <= s564;
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s565;
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
next_state <= s564;
ELSE
next_state <= s566;
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s301;
ELSE
next_state <= s266;
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s302;
ELSE
next_state <= s301;
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s302;
END IF;
WHEN RES =>
next_state <= s544;
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
next_state <= s574;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
next_state <= s569;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
next_state <= s559;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
next_state <= s562;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
next_state <= s567;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
next_state <= s568;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
next_state <= s570;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s511;
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s559;
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s562;
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s567;
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
next_state <= s571;
ELSE
next_state <= s568;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s569;
END IF;
WHEN s570 =>
IF (rdy_i = '1') THEN
next_state <= s572;
ELSE
next_state <= s570;
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
next_state <= s573;
ELSE
next_state <= s571;
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
next_state <= s559;
ELSE
next_state <= s572;
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1') THEN
next_state <= s574;
ELSE
next_state <= s573;
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
next_state <= FETCH;
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s574;
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
next_state <= s551;
ELSE
next_state <= s548;
END IF;
WHEN s551 =>
next_state <= s552;
WHEN s552 =>
next_state <= s576;
WHEN s575 =>
IF (rdy_i = '1') THEN
next_state <= s577;
ELSE
next_state <= s575;
END IF;
WHEN s576 =>
IF (NMI_i = '1') THEN
next_state <= s578;
ELSE
next_state <= s575;
END IF;
WHEN s577 =>
IF (rdy_i = '1') THEN
next_state <= FETCH;
ELSE
next_state <= s577;
END IF;
WHEN s578 =>
IF (rdy_i = '1') THEN
next_state <= s577;
ELSE
next_state <= s578;
END IF;
WHEN OTHERS =>
next_state <= RES;
END CASE;
END PROCESS nextstate_proc;
-----------------------------------------------------------------
output_proc : PROCESS (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_i,
d_regs_out_i,
irq_n_i,
nmi_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
reg_sel_pc_in,
reg_sel_pc_val,
reg_sel_rb_in,
reg_sel_rb_out,
reg_sel_reg,
reg_sel_sp_as,
reg_sel_sp_in,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
rst_nmi_o <= '0';
sel_pc_in_o <= reg_sel_pc_in;
sel_pc_val_o <= reg_sel_pc_val;
sel_rb_in_o <= reg_sel_rb_in;
sel_rb_out_o <= reg_sel_rb_out;
sel_reg_o <= reg_sel_reg;
sel_sp_as_o <= reg_sel_sp_as;
sel_sp_in_o <= reg_sel_sp_in;
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '1';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"0";
zw_ALU2 <= '0' & X"0";
zw_ALU3 <= '0' & X"0";
zw_ALU4 <= '0' & X"0";
zw_ALU5 <= X"0";
zw_ALU6 <= X"0";
-- Combined Actions
CASE current_state IS
WHEN FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
ELSIF ((irq_n_i = '0' and
reg_F(2) = '0') AND (rdy_i = '1')) THEN
ELSIF ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"24" or
d_i = X"2C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"4C" or
d_i = X"6C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s1 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s2 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s5 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s3 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s4 =>
IF (rdy_i = '1' and
zw_REG_OP = X"9A") THEN
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"BA") THEN
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
ELSIF (rdy_i = '1') THEN
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s12 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s16 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s17 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s24 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s25 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s273 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s307 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s177 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"9D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"99") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"91") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"81") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"96") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s180 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s181 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s182 =>
sig_RWn <= '1';
sig_RD <= '1';
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s183 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s184 =>
sig_SYNC <= '1';
WHEN s185 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s187 =>
sig_SYNC <= '1';
WHEN s188 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s189 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s190 =>
sig_SYNC <= '1';
WHEN s191 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
WHEN s192 =>
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
WHEN s193 =>
sig_SYNC <= '1';
WHEN s377 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s381 =>
sig_SYNC <= '1';
WHEN s378 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s382 =>
sig_SYNC <= '1';
WHEN s379 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s384 =>
IF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
END IF;
WHEN s380 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s386 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s387 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s388 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s389 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s392 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s390 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s393 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
END IF;
WHEN s395 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s396 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN s397 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
END IF;
WHEN s398 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s399 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s401 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s526 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s527 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s528 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F OR X"10";
WHEN s530 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s544 =>
ld_o <= "11";
ld_sp_o <= '1';
WHEN s545 =>
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
WHEN s546 =>
ld_o <= "11";
ld_pc_o <= '1';
WHEN s549 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s550 =>
ld_o <= "11";
ld_sp_o <= '1';
WHEN s404 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s556 =>
IF (rdy_i = '1') THEN
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s557 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s579 =>
IF (rdy_i = '1') THEN
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN s201 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"B6") THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s202 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s210 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s211 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s215 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s217 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s222 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s223 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s224 =>
IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
ELSIF (rdy_i = '1') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
END IF;
WHEN s225 =>
IF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
ELSIF ((rdy_i = '1' AND
zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0') THEN
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
END IF;
WHEN s226 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
END IF;
WHEN s243 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s244 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s247 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s343 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= zw_b4;
END IF;
WHEN s250 =>
IF (rdy_i = '1') THEN
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
END IF;
WHEN s251 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
WHEN s351 =>
IF (rdy_i = '1' and
zw_REG_OP = X"24") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"2C") THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s361 =>
IF (rdy_i = '1') THEN
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
END IF;
WHEN s360 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s403 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s406 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s407 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s409 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s416 =>
IF (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) THEN
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) THEN
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) THEN
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
ELSIF (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) THEN
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
END IF;
WHEN s418 =>
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
WHEN s510 =>
IF (rdy_i = '1' and
zw_REG_OP = X"65") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"75") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"6D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"7D") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"79") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"71") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"61") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
END IF;
WHEN s553 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s555 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s558 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s560 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s563 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s564 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
END IF;
WHEN s565 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
zw_ALU6(2 downto 0) <= (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
zw_ALU5(2 downto 0) <= (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
END IF;
WHEN s566 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s266 =>
IF (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
ELSIF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s301 =>
IF (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
ELSIF (rdy_i = '1') THEN
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s302 =>
IF (rdy_i = '1') THEN
sig_SYNC <= '1';
END IF;
WHEN RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
WHEN s511 =>
IF (rdy_i = '1' and
zw_REG_OP = X"E5") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F5") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"ED") THEN
ld_o <= "11";
ld_pc_o <= '1';
ELSIF (rdy_i = '1' and
zw_REG_OP = X"FD") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F9") THEN
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"F1") THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E1") THEN
ch_a_o <= d_i;
ch_b_o <= q_x_i;
ELSIF (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
END IF;
WHEN s559 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s562 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s567 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s568 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= q_y_i;
END IF;
WHEN s569 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s571 =>
IF (rdy_i = '1') THEN
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
END IF;
WHEN s572 =>
IF (rdy_i = '1') THEN
ch_a_o <= zw_b1;
ch_b_o <= X"01";
END IF;
WHEN s573 =>
IF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
ELSIF (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
END IF;
WHEN s574 =>
IF (rdy_i = '1' and
reg_F(3) = '0') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
ELSIF (rdy_i = '1' and
reg_F(3) = '1') THEN
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
END IF;
WHEN s548 =>
IF (rdy_i = '1') THEN
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
END IF;
WHEN s551 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
WHEN s552 =>
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
WHEN s576 =>
IF (NMI_i = '1') THEN
rst_nmi_o <= '1';
END IF;
WHEN s577 =>
IF (rdy_i = '1') THEN
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
END fsm;
| gpl-2.0 | 3304f9596f1412efe6a46ddb3c25972c | 0.3207 | 3.366411 | false | false | false | false |
MonsieurOenologue/Paprotto | composants_fonctionnels/testALU.vhd | 1 | 1,106 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY testALU IS
END ENTITY testALU;
Architecture Test OF testALU IS
COMPONENT alu IS
GENERIC(N: POSITIVE := 16);
PORT(
sel : IN std_logic_vector(3 DOWNTO 0);
A, B : IN std_logic_vector(N-1 DOWNTO 0);
Q : OUT std_logic_vector(N-1 DOWNTO 0);
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL s_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s_A, s_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_Q : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
SIGNAL s_Cout : STD_LOGIC;
BEGIN
aluTest : alu GENERIC MAP(16) PORT MAP(s_sel, s_A, s_B, s_Q, s_Cout);
ProcessSimulation : PROCESS
BEGIN
s_sel <= "0010";
s_A <= "1000000000000011";
s_B <= "1000000000000010";
WAIT FOR 10 ns;
s_sel <= "0100";
WAIT FOR 10 ns;
s_sel <= "0101";
WAIT FOR 10 ns;
s_sel <= "0110";
WAIT FOR 10 ns;
s_sel <= "0111";
WAIT FOR 10 ns;
s_A <= "0011110000110000";
WAIT FOR 10 ns;
s_sel <= "0010";
WAIT FOR 10 ns;
WAIT;
END PROCESS ProcessSimulation;
END Test;
| gpl-3.0 | 678339df487e0e64415025d5ff4e4c1a | 0.597649 | 3.038462 | false | true | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/MSPAC_DROM/synth/MSPAC_DROM.vhd | 1 | 6,789 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY MSPAC_DROM IS
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MSPAC_DROM;
ARCHITECTURE MSPAC_DROM_arch OF MSPAC_DROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MSPAC_DROM_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF MSPAC_DROM_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF MSPAC_DROM_arch : ARCHITECTURE IS "MSPAC_DROM,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF MSPAC_DROM_arch: ARCHITECTURE IS "MSPAC_DROM,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_ADDR_WIDTH=14,C_DEFAULT_DATA=0,C_DEPTH=16384,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=MSPAC_DROM.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=8,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "zynq",
C_ADDR_WIDTH => 14,
C_DEFAULT_DATA => "0",
C_DEPTH => 16384,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "MSPAC_DROM.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 8,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END MSPAC_DROM_arch;
| gpl-2.0 | 662fca748ff8eb534d05ea7ecf82177d | 0.64413 | 3.19032 | false | false | false | false |
freecores/spi_boot | rtl/vhdl/spi_boot.vhd | 1 | 30,394 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot.vhd,v 1.11 2007-08-08 00:39:10 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_boot is
generic (
-- width of bit counter: minimum 6, maximum 12
width_bit_cnt_g : integer := 6;
-- width of image counter: minimum 0, maximum n
width_img_cnt_g : integer := 2;
-- number of bits required to address one image
num_bits_per_img_g : integer := 18;
-- SD specific initialization
sd_init_g : integer := 0;
-- clock divider to reach 400 kHz for MMC compatibility
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
-- active level of reset_i
reset_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g
downto 0);
-- Card Interface ---------------------------------------------------------
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
-- FPGA Configuration Interface -------------------------------------------
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end spi_boot;
library ieee;
use ieee.numeric_std.all;
use work.spi_boot_pack.all;
architecture rtl of spi_boot is
component spi_counter
generic (
cnt_width_g : integer := 4;
cnt_max_g : integer := 15
);
port (
clk_i : in std_logic;
reset_i : in boolean;
cnt_en_i : in boolean;
cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
cnt_ovfl_o : out boolean
);
end component;
-----------------------------------------------------------------------------
-- States of the controller FSM
--
type ctrl_states_t is (POWER_UP1, POWER_UP2,
CMD0,
CMD1,
CMD55, ACMD41,
CMD16,
WAIT_START,
WAIT_INIT_LOW, WAIT_INIT_HIGH,
CMD18, CMD18_DATA,
CMD12,
INC_IMG_CNT);
--
signal ctrl_fsm_q,
ctrl_fsm_s : ctrl_states_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- States of the command FSM
--
type cmd_states_t is (CMD, START, R1, PAUSE);
--
signal cmd_fsm_q,
cmd_fsm_s : cmd_states_t;
--
-----------------------------------------------------------------------------
subtype op_r is integer range 5 downto 0;
type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0);
signal res_bc_s : res_bc_t;
signal upper_bitcnt_zero_s : boolean;
signal cfg_dat_q : std_logic;
signal spi_clk_q : std_logic;
signal spi_clk_rising_q : boolean;
signal spi_clk_falling_q : boolean;
signal spi_dat_q,
spi_dat_s : std_logic;
signal spi_cs_n_q,
spi_cs_n_s : std_logic;
signal cfg_clk_q : std_logic;
signal start_q : std_logic;
signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0);
signal cnt_en_img_s : boolean;
signal mmc_cnt_ovfl_s : boolean;
signal mmc_compat_s : boolean;
signal cmd_finished_s : boolean;
signal r1_illcmd_q,
r1_idle_q : std_logic;
signal done_q,
send_cmd12_q : boolean;
signal en_outs_s,
en_outs_q : boolean;
signal reset_s : boolean;
signal true_s : boolean;
begin
true_s <= true;
reset_s <= true
when (reset_level_g = 1 and reset_i = '1') or
(reset_level_g = 0 and reset_i = '0') else
false;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements several sequential elements.
--
seq: process (clk_i, reset_s)
variable bit_cnt_v : unsigned(1 downto 0);
begin
if reset_s then
-- reset bit counter to 63 for power up
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "111111";
spi_dat_q <= '1';
spi_cs_n_q <= '1';
cfg_dat_q <= '1';
start_q <= '0';
done_q <= false;
send_cmd12_q <= false;
ctrl_fsm_q <= POWER_UP1;
cmd_fsm_q <= CMD;
r1_illcmd_q <= '0';
r1_idle_q <= '0';
en_outs_q <= false;
elsif clk_i'event and clk_i = '1' then
-- bit counter control
if spi_clk_rising_q then
case res_bc_s is
when NONE =>
bit_cnt_q <= bit_cnt_q - 1;
when RES_MAX =>
bit_cnt_q <= (others => '1');
when RES_47 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "101111";
when RES_15 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "001111";
when RES_7 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "000111";
when others =>
bit_cnt_q <= (others => '0');
end case;
end if;
-- Card data output register
-- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
-- As soon as this mode is left, the register must start latching.
-- There is no explicit relation to spi_clk_q anymore in normal mode.
-- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
-- value after the rising edge of spi_clk_q.
-- -> spi_dat_q changes upon falling edge of spi_clk_q
if spi_clk_falling_q or not mmc_compat_s then
spi_dat_q <= spi_dat_s;
end if;
-- config data output register
-- a new value is loaded when config clock is high,
-- i.e. input data is sampled with rising spi_clk
-- while output value changes on falling edge of cfg_clk
if cfg_clk_q = '1' and spi_clk_rising_q then
cfg_dat_q <= spi_data_in_i;
end if;
-- Controller FSM state
ctrl_fsm_q <= ctrl_fsm_s;
-- Command FSM state
cmd_fsm_q <= cmd_fsm_s;
-- CS signal for SPI card
if spi_clk_q = '1' then
spi_cs_n_q <= spi_cs_n_s;
end if;
-- Extract flags from R1 response
if cmd_fsm_q = R1 then
bit_cnt_v := bit_cnt_q(1 downto 0);
case bit_cnt_v(1 downto 0) is
when "10" =>
-- save "Illegal Command" flag
r1_illcmd_q <= to_X01(spi_data_in_i);
when "00" =>
-- save "Idle State" flag
r1_idle_q <= to_X01(spi_data_in_i);
when others =>
null;
end case;
end if;
-- Start trigger register for rising edge detection
-- the reset value is '0' thus a rising edge will always be detected
-- after reset even though start_i is tied to '1'
if start_i = '0' then
start_q <= '0';
elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
start_q <= start_i;
end if;
-- Marker for cfg_done and dat_done
if ctrl_fsm_q = CMD18_DATA then
if cfg_done_i = '1' and dat_done_i = '1' then
done_q <= true;
end if;
if done_q and
(not upper_bitcnt_zero_s or cmd_fsm_q = START) then
-- activate sending of CMD12 when it is safe:
-- * upper bits of bit counter are not zero
-- -> transmission of CMD12 is not running
-- * cmd FSM is in START state
-- -> also no transmission running
send_cmd12_q <= true;
end if;
elsif ctrl_fsm_q = WAIT_START then
-- reset done_q when WAIT_START has been reached
-- this is necessary to let the stop transmission process come to
-- an end without interruption or generation of unwanted cfg_clk_q
done_q <= false;
send_cmd12_q <= false;
end if;
-- output enable
if spi_clk_rising_q then
en_outs_q <= en_outs_s;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process upper_bits
--
-- Purpose:
-- Detects that the upper bits of the bit counter are zero.
-- Upper bits = n downto 6, i.e. the optional part that is not required for
-- commands but for extension of data blocks.
--
upper_bits: process (bit_cnt_q)
variable zero_v : boolean;
begin
zero_v := true;
for i in bit_cnt_q'high downto 6 loop
if bit_cnt_q(i) = '1' then
zero_v := false;
end if;
end loop;
upper_bitcnt_zero_s <= zero_v;
end process upper_bits;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process clk_gen
--
-- Purpose:
-- Generates clocks for card and FPGA configuration.
-- The card clock is free running with a divide by two of clk_i.
-- The clock for FPGA config has an enable and is stopped on high level.
-- There is a phase shift of half a period between spi_clk and cfg_clk.
--
clk_gen: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_q <= '0';
cfg_clk_q <= '1';
elsif clk_i'event and clk_i = '1' then
-- spi_clk_q rises according to the flag
-- it falls with overflow indication
-- the resulting duty cycle is not exactly 50:50,
-- high time is a bit longer
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_q rises when flagged by spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
elsif mmc_cnt_ovfl_s then
-- upon counter overflow spi_clk_q falls in case it does not rise
spi_clk_q <= '0';
end if;
else
-- normal mode
-- spi_clk_q follows spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
else
spi_clk_q <= '0';
end if;
end if;
-- clock for FPGA config must be enabled and follows spi_clk
if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
not done_q then
cfg_clk_q <= spi_clk_q;
else
cfg_clk_q <= '1';
end if;
end if;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Indication flags for rising and falling spi_clk_q.
-- Essential for MMC clock compatibility mode.
-----------------------------------------------------------------------------
mmc_comap: if mmc_compat_clk_div_g > 0 generate
mmc_compat_sig: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
elsif clk_i'event and clk_i = '1' then
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
-- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
if mmc_cnt_ovfl_s then
spi_clk_rising_q <= spi_clk_q = '0';
spi_clk_falling_q <= spi_clk_q = '1';
else
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
end if;
else
-- normal mode
spi_clk_rising_q <= not spi_clk_rising_q;
spi_clk_falling_q <= true;
end if;
end if;
end process mmc_compat_sig;
end generate;
no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
-- SPI clock rising whenever spi_clk_q is '0'
spi_clk_rising_q <= spi_clk_q = '0';
-- SPI clock falling whenever spi_clk_q is '1'
spi_clk_falling_q <= spi_clk_q = '1';
end generate;
-----------------------------------------------------------------------------
-- Process ctrl_fsm
--
-- Purpose:
-- Implements the controller FSM.
--
ctrl_fsm: process (ctrl_fsm_q,
cmd_finished_s, r1_illcmd_q, r1_idle_q,
start_i, start_q, mode_i,
cfg_init_n_i)
variable mmc_compat_v : boolean;
begin
-- default assignments
ctrl_fsm_s <= POWER_UP1;
config_n_o <= '1';
cnt_en_img_s <= false;
spi_cs_n_s <= '0';
mmc_compat_v := false;
en_outs_s <= true;
case ctrl_fsm_q is
-- Let card finish power up, step 1 -------------------------------------
when POWER_UP1 =>
mmc_compat_v := true;
spi_cs_n_s <= '1';
if cmd_finished_s then
ctrl_fsm_s <= POWER_UP2;
else
ctrl_fsm_s <= POWER_UP1;
end if;
-- Let card finish power up, step 2 -------------------------------------
when POWER_UP2 =>
mmc_compat_v := true;
if cmd_finished_s then
ctrl_fsm_s <= CMD0;
else
spi_cs_n_s <= '1';
ctrl_fsm_s <= POWER_UP2;
end if;
-- Issue CMD0: GO_IDLE_STATE --------------------------------------------
when CMD0 =>
mmc_compat_v := true;
if cmd_finished_s then
if sd_init_g = 1 then
ctrl_fsm_s <= CMD55;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD0;
end if;
-- Issue CMD55: APP_CMD -------------------------------------------------
when CMD55 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_illcmd_q = '0' then
-- command accepted, continue with ACMD41
ctrl_fsm_s <= ACMD41;
else
-- command rejected, it's an MMC card
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD55;
end if;
end if;
-- Issue ACMD41: SEND_OP_COND -------------------------------------------
when ACMD41 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_illcmd_q = '0' then
-- ok, that's an SD card
if r1_idle_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD55;
end if;
else
-- command rejected, though it accepted CMD55 -> it's an MMC
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= ACMD41;
end if;
end if;
-- Issue CMD1: SEND_OP_COND ---------------------------------------------
when CMD1 =>
mmc_compat_v := true;
if cmd_finished_s then
if r1_idle_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD1;
end if;
-- Issue CMD16: SET_BLOCKLEN --------------------------------------------
when CMD16 =>
if cmd_finished_s then
ctrl_fsm_s <= WAIT_START;
else
ctrl_fsm_s <= CMD16;
end if;
-- Wait for configuration start request ---------------------------------
when WAIT_START =>
spi_cs_n_s <= '1';
-- detect rising edge of start_i
if start_i = '1' and start_q = '0' then
-- decide which mode is requested
if cmd_finished_s then
if mode_i = '0' then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
-- Wait for INIT to become low ------------------------------------------
when WAIT_INIT_LOW =>
spi_cs_n_s <= '1';
-- activate FPGA configuration
config_n_o <= '0';
if cfg_init_n_i = '0' then
ctrl_fsm_s <= WAIT_INIT_HIGH;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
-- Wait for INIT to become high -----------------------------------------
when WAIT_INIT_HIGH =>
spi_cs_n_s <= '1';
if cfg_init_n_i = '1' and cmd_finished_s then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_HIGH;
end if;
-- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
when CMD18 =>
if cmd_finished_s then
ctrl_fsm_s <= CMD18_DATA;
else
ctrl_fsm_s <= CMD18;
end if;
--
-- receive a data block
when CMD18_DATA =>
if cmd_finished_s then
ctrl_fsm_s <= CMD12;
else
ctrl_fsm_s <= CMD18_DATA;
end if;
-- Issued CMD12: STOP_TRANSMISSION -------------------------------------
when CMD12 =>
if cmd_finished_s then
ctrl_fsm_s <= INC_IMG_CNT;
else
ctrl_fsm_s <= CMD12;
end if;
-- Increment Image Counter ----------------------------------------------
when INC_IMG_CNT =>
spi_cs_n_s <= '1';
ctrl_fsm_s <= WAIT_START;
cnt_en_img_s <= true;
when others =>
null;
end case;
-- mmc_compat_s is suppressed if MMC clock compatibility is not required
if mmc_compat_clk_div_g > 0 then
mmc_compat_s <= mmc_compat_v;
else
mmc_compat_s <= false;
end if;
end process ctrl_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process cmd_fsm
--
-- Purpose:
-- Implements the command FSM.
--
cmd_fsm: process (spi_clk_rising_q,
spi_data_in_i,
bit_cnt_q,
ctrl_fsm_q,
cmd_fsm_q,
send_cmd12_q)
variable cnt_zero_v : boolean;
variable spi_data_low_v : boolean;
variable no_startbit_v : boolean;
begin
-- default assignments
cmd_finished_s <= false;
cmd_fsm_s <= CMD;
res_bc_s <= NONE;
cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0;
spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
-- these are no real commands thus there will be no startbit
case ctrl_fsm_q is
when POWER_UP1 | POWER_UP2 |
WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
no_startbit_v := true;
when others =>
no_startbit_v := false;
end case;
case cmd_fsm_q is
-- Send the command -----------------------------------------------------
when CMD =>
if cnt_zero_v then
if ctrl_fsm_q /= CMD18_DATA then
-- normal commands including CMD12 require startbit of R1 response
cmd_fsm_s <= START;
else
if not send_cmd12_q then
-- CMD18_DATA needs to read CRC
cmd_fsm_s <= R1;
res_bc_s <= RES_15;
else
-- CMD18_DATA finished, scan for startbit of response
cmd_finished_s <= true;
cmd_fsm_s <= START;
end if;
end if;
else
cmd_fsm_s <= CMD;
end if;
-- Wait for startbit of response ----------------------------------------
when START =>
-- startbit detection or skip of this check
if no_startbit_v and spi_clk_rising_q then
cmd_fsm_s <= R1;
res_bc_s <= RES_7;
elsif spi_data_low_v then
if ctrl_fsm_q /= CMD18_DATA then
cmd_fsm_s <= R1;
else
-- CMD18_DATA startbit detected, read payload
cmd_fsm_s <= CMD;
res_bc_s <= RES_MAX;
end if;
else
cmd_fsm_s <= START;
res_bc_s <= RES_7;
end if;
-- Read R1 response -----------------------------------------------------
when R1 =>
if cnt_zero_v then
res_bc_s <= RES_7;
if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
cmd_fsm_s <= PAUSE;
else
-- CMD18 needs another startbit detection for the data token.
-- CMD18_DATA needs a startbit after having received the CRC, either
-- * next data token
-- * R1 response of CMD12
cmd_fsm_s <= START;
if ctrl_fsm_q = CMD18 then
-- CMD18 response received -> advance to CMD18_DATA
cmd_finished_s <= true;
end if;
end if;
else
cmd_fsm_s <= R1;
end if;
-- PAUSE state -> required for Nrc, card response to host command -------
when PAUSE =>
if cnt_zero_v then
cmd_fsm_s <= CMD;
res_bc_s <= RES_47;
cmd_finished_s <= true;
else
cmd_fsm_s <= PAUSE;
end if;
when others =>
null;
end case;
end process cmd_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process transmit
--
-- Purpose:
-- Generates the serial data output values based on the current FSM state
--
-- The local variable cmd_v is 64 bits wide in contrast to an SPI command
-- with 48 bits. There are two reasons for this:
-- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
-- counter will start from 3F on its lowest 6 bits. Therefore, it is
-- necessary to provide all 64 positions in cmd_v.
-- * Reduces logic.
--
transmit: process (ctrl_fsm_q,
cmd_fsm_q,
bit_cnt_q,
img_cnt_s,
send_cmd12_q,
set_sel_i,
upper_bitcnt_zero_s)
subtype cmd_r is natural range 47 downto 0;
subtype cmd_t is std_logic_vector(cmd_r);
subtype ext_cmd_t is std_logic_vector(63 downto 0);
-- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101";
constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1";
constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1";
constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1";
constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1";
constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1";
constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
variable cmd_v : ext_cmd_t;
variable tx_v : boolean;
begin
-- default assignments
spi_dat_s <= '1';
cmd_v := (others => '1');
tx_v := false;
if cmd_fsm_q = CMD then
case ctrl_fsm_q is
when CMD0 =>
cmd_v(cmd_r) := cmd0_c;
tx_v := true;
when CMD1 =>
cmd_v(cmd_r) := cmd1_c;
tx_v := true;
when CMD16 =>
cmd_v(cmd_r) := cmd16_c;
cmd_v(8 + width_bit_cnt_g-3) := '1';
tx_v := true;
when CMD18 =>
cmd_v(cmd_r) := cmd18_c;
-- insert image counter
cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
downto 8 + num_bits_per_img_g) := img_cnt_s;
-- insert set selection
cmd_v(8 + 31
downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
tx_v := true;
when CMD18_DATA =>
cmd_v(cmd_r) := cmd12_c;
if send_cmd12_q and upper_bitcnt_zero_s then
tx_v := true;
end if;
when CMD55 =>
cmd_v(cmd_r) := cmd55_c;
tx_v := true;
when ACMD41 =>
cmd_v(cmd_r) := acmd41_c;
tx_v := true;
when others =>
null;
end case;
end if;
if tx_v then
spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
end if;
end process transmit;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Optional Image Counter
-----------------------------------------------------------------------------
img_cnt: if width_img_cnt_g > 0 generate
img_cnt_b : spi_counter
generic map (
cnt_width_g => width_img_cnt_g,
cnt_max_g => 2**width_img_cnt_g - 1
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => cnt_en_img_s,
cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0),
cnt_ovfl_o => open
);
img_cnt_s(width_img_cnt_g) <= '0';
end generate;
no_img_cnt: if width_img_cnt_g = 0 generate
img_cnt_s <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- Optional MMC compatibility counter
-----------------------------------------------------------------------------
mmc_cnt: if mmc_compat_clk_div_g > 0 generate
mmc_cnt_b : spi_counter
generic map (
cnt_width_g => width_mmc_clk_div_g,
cnt_max_g => mmc_compat_clk_div_g
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => true_s,
cnt_o => open,
cnt_ovfl_o => mmc_cnt_ovfl_s
);
end generate;
no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
mmc_cnt_ovfl_s <= true;
end generate;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_q;
spi_cs_n_o <= spi_cs_n_q;
spi_data_out_o <= spi_dat_q;
spi_en_outs_o <= '1'
when en_outs_q else
'0';
cfg_clk_o <= cfg_clk_q;
cfg_dat_o <= cfg_dat_q;
detached_o <= '0'
when en_outs_q else
'1';
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.10 2007/08/06 23:31:05 arniml
-- enlarge set_sel_i input to fill all upper bits of the 32 bit address vector
--
-- Revision 1.9 2007/02/25 18:24:12 arniml
-- fix type handling of resets
--
-- Revision 1.8 2006/09/11 23:03:36 arniml
-- disable outputs with reset
--
-- Revision 1.7 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.6 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.5 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.4 2005/02/18 06:42:08 arniml
-- clarify wording for images
--
-- Revision 1.3 2005/02/16 18:59:10 arniml
-- include output enable control for SPI outputs
--
-- Revision 1.2 2005/02/13 17:25:51 arniml
-- major update to fix several problems
-- configuration/data download of multiple sets works now
--
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 7ed704c3e7250ac86dd0f89662a06eaf | 0.476541 | 3.856617 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_2/synth/DIGDUG_ROM.vhd | 1 | 14,048 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DIGDUG_ROM IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DIGDUG_ROM;
ARCHITECTURE DIGDUG_ROM_arch OF DIGDUG_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DIGDUG_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DIGDUG_ROM_arch : ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=DIGDUG_ROM.mif,C_INIT_FILE=DIGDUG_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "DIGDUG_ROM.mif",
C_INIT_FILE => "DIGDUG_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DIGDUG_ROM_arch;
| gpl-2.0 | 326f57bdf5e955b57d215fe022361ec0 | 0.626068 | 3.030852 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM/synth/DIGDUG_ROM.vhd | 1 | 14,076 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DIGDUG_ROM IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DIGDUG_ROM;
ARCHITECTURE DIGDUG_ROM_arch OF DIGDUG_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DIGDUG_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DIGDUG_ROM_arch : ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DIGDUG_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.264701 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DIGDUG_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.264701 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DIGDUG_ROM_arch;
| gpl-2.0 | a718b4c1689673c8011fd2701e811333 | 0.62667 | 3.032967 | false | false | false | false |
id101010/vhdl-irdecoder | serparbuf.vhd | 1 | 3,207 | ----------------------------------------------------------------------------------
-- Licence:
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Engineer: Aaron Schmocker
-- Create Date: 00:01:55 21.01.2016
-- Module Name: SerParLatch
-- Project Name: irdecoder
-- Description: A serial to parallel shiftregister with latched output
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serparbuf is
generic ( nbits : natural := 19);
port ( clk : in std_logic; -- input clock frequency
shift_out : in std_logic; -- push internal data (latched) to output
shift_down : in std_logic; -- shift all internal bits (latched) one bit down, and set the highest bit to serial_in
clear : in std_logic; -- asynchronous, high active clear
serial_in : in std_logic; -- serial input (synchronous on clk, enabled by shift_down)
parallel_output : out std_logic_vector(nbits downto 0)); -- parallel output
end serparbuf;
architecture Behavioral of serparbuf is
signal parallel_output_latch : std_logic_vector(nbits downto 0) := (others => '0'); -- this signal acts as a latch
begin
-- purpose : serial-in/parallel-out shift register with output latch and clear
-- type : sequential (on clk)
-- inputs : clk, clear, shift_down, shift_out, serial_in
-- outputs : parallel_out
process(clk,clear)
begin
if (clear = '1') then -- if a clear signal gets detected, clear everything
parallel_output_latch <= (others => '0');
parallel_output <= (others => '0');
elsif(rising_edge(clk)) then -- positive edge on clk
if (shift_down = '1') then -- shift down all bits and read a new one into the latch
parallel_output_latch((nbits-1) downto 0) <= parallel_output_latch(nbits downto 1);
parallel_output_latch(nbits) <= serial_in;
end if;
if (shift_out = '1') then -- make the contents of the latch visible
parallel_output(nbits downto 0) <= parallel_output_latch(nbits downto 0);
end if;
end if;
end process;
end Behavioral;
| lgpl-3.0 | da46025b362bc053b319525c2e7717a5 | 0.556595 | 4.723122 | false | false | false | false |
545/Atari7800 | core/cpu6502_true_cycle/trunk/rtl/vhdl/regbank_axy.vhd | 1 | 7,813 | -- VHDL Entity R6502_TC.RegBank_AXY.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:49 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY RegBank_AXY IS
PORT(
clk_clk_i : IN std_logic;
d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);
load_regs_i : IN std_logic;
rst_rst_n_i : IN std_logic;
sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);
sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);
sel_reg_i : IN std_logic_vector (1 DOWNTO 0);
d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);
q_a_o : OUT std_logic_vector (7 DOWNTO 0);
q_x_o : OUT std_logic_vector (7 DOWNTO 0);
q_y_o : OUT std_logic_vector (7 DOWNTO 0)
);
-- Declarations
END RegBank_AXY ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Register Bank for register A, X and Y
-- Path: R6502_TC/RegBank_AXY/struct
-- Edited: by eda on 08 Feb 2010
--
-- VHDL Architecture R6502_TC.RegBank_AXY.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 18:39:49 08.02.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ARCHITECTURE struct OF RegBank_AXY IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL ld : std_logic_vector(2 DOWNTO 0);
SIGNAL load1_o_i : std_logic;
SIGNAL load2_o_i : std_logic;
SIGNAL load_o_i : std_logic;
SIGNAL q_mux_o_i : std_logic_vector(7 DOWNTO 0);
SIGNAL val_zero : std_logic_vector(7 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL q_a_o_internal : std_logic_vector (7 DOWNTO 0);
SIGNAL q_x_o_internal : std_logic_vector (7 DOWNTO 0);
SIGNAL q_y_o_internal : std_logic_vector (7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);
-- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'
SIGNAL mw_U_5reg_cval : std_logic_vector(7 DOWNTO 0);
BEGIN
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
q_a_o_internal <= mw_U_0reg_cval;
u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_0reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load_o_i = '1') THEN
mw_U_0reg_cval <= q_mux_o_i;
END IF;
END IF;
END PROCESS u_0seq_proc;
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
q_x_o_internal <= mw_U_4reg_cval;
u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_4reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load1_o_i = '1') THEN
mw_U_4reg_cval <= q_mux_o_i;
END IF;
END IF;
END PROCESS u_4seq_proc;
-- ModuleWare code(v1.9) for instance 'U_5' of 'adff'
q_y_o_internal <= mw_U_5reg_cval;
u_5seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)
BEGIN
IF (rst_rst_n_i = '0') THEN
mw_U_5reg_cval <= "00000000";
ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN
IF (load2_o_i = '1') THEN
mw_U_5reg_cval <= q_mux_o_i;
END IF;
END IF;
END PROCESS u_5seq_proc;
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= load_regs_i AND ld(0);
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load1_o_i <= load_regs_i AND ld(1);
-- ModuleWare code(v1.9) for instance 'U_8' of 'and'
load2_o_i <= load_regs_i AND ld(2);
-- ModuleWare code(v1.9) for instance 'U_11' of 'constval'
val_zero <= "00000000";
-- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'
u_1combo_proc: PROCESS (sel_reg_i)
BEGIN
ld <= (OTHERS => '0');
CASE sel_reg_i IS
WHEN "00" => ld(0) <= '1';
WHEN "01" => ld(1) <= '1';
WHEN "10" => ld(2) <= '1';
WHEN OTHERS => ld <= (OTHERS => '0');
END CASE;
END PROCESS u_1combo_proc;
-- ModuleWare code(v1.9) for instance 'U_2' of 'mux'
u_2combo_proc: PROCESS(q_a_o_internal, q_x_o_internal, q_y_o_internal,
val_zero, sel_rb_out_i)
BEGIN
CASE sel_rb_out_i IS
WHEN "00" => d_regs_out_o <= q_a_o_internal;
WHEN "01" => d_regs_out_o <= q_x_o_internal;
WHEN "10" => d_regs_out_o <= q_y_o_internal;
WHEN "11" => d_regs_out_o <= val_zero;
WHEN OTHERS => d_regs_out_o <= (OTHERS => 'X');
END CASE;
END PROCESS u_2combo_proc;
-- ModuleWare code(v1.9) for instance 'U_3' of 'mux'
u_3combo_proc: PROCESS(q_a_o_internal, q_y_o_internal, q_x_o_internal,
d_regs_in_i, sel_rb_in_i)
BEGIN
CASE sel_rb_in_i IS
WHEN "00" => q_mux_o_i <= q_a_o_internal;
WHEN "01" => q_mux_o_i <= q_y_o_internal;
WHEN "10" => q_mux_o_i <= q_x_o_internal;
WHEN "11" => q_mux_o_i <= d_regs_in_i;
WHEN OTHERS => q_mux_o_i <= (OTHERS => 'X');
END CASE;
END PROCESS u_3combo_proc;
-- Instance port mappings.
-- Implicit buffered output assignments
q_a_o <= q_a_o_internal;
q_x_o <= q_x_o_internal;
q_y_o <= q_y_o_internal;
END struct;
| gpl-2.0 | 382b3d3965370abd6f5cc1299e62644d | 0.480993 | 3.478629 | false | false | false | false |
id101010/vhdl-irdecoder | decoder_tb.vhd | 1 | 5,564 | ----------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company: BFH
-- Engineer: Aaron Schmocker
--
-- Create Date: 18:57:27 01/08/2016
-- Design Name:
-- Module Name: decoder_tb.vhd
-- Project Name: irdecoder
-- Target Device:
-- Tool versions:
-- Description:
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity decoder_tb is
generic ( input_freq : time := 32768 us; -- frequency of clk in hz
start_time : time := 2500 us; -- time for the start signal/leader in us
one_time : time := 1300 us; -- time for a '1' signal in us
zero_time : time := 655 us; -- time for a '0' signal in us
pause_time : time := 574 us; -- time for a pause signal in us
tolerance_time : time := 130 us); -- allowed tolerance +- in us
end decoder_tb;
architecture behavior of decoder_tb is
-- Component Declaration for the Unit Under Test (UUT)
component decoder
port( clk : in std_logic;
data_in : in std_logic;
reset : in std_logic;
data_out : out std_logic;
frame_detect : out std_logic;
latch_enable : out std_logic);
end component;
--Inputs
signal clk : std_logic := '0';
signal data_in : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal data_out : std_logic;
signal frame_detect : std_logic;
signal latch_enable : std_logic;
-- Clock period definitions
constant clk_period : time := (1000 ms) / 32768; -- clock period
begin
-- Instantiate the Unit Under Test (UUT)
uut: decoder PORT MAP (
clk => clk,
data_in => data_in,
reset => reset,
data_out => data_out,
frame_detect => frame_detect,
latch_enable => latch_enable);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable seed1, seed2: positive; -- will be updated by random generator, after each retrival of a random number
--procedure that waits for t(argument) +- tolerance_time (generic parameter)
procedure wait_rand(constant t : in time) is
variable rand: real;
variable rand_num : integer;
variable wait_time : time;
begin
uniform(seed1, seed2, rand); --calc rand value 0.00 ... 1.00
rand_num := integer(rand*2.0*real(tolerance_time/1 us))-integer(tolerance_time/1 us); --scale to -tolerance ... + tolerance
wait_time := t + (rand_num * 1 us);
wait for wait_time;
end procedure;
--prodecure that sends out a sequence (passed by parameter)
--TODO: Find out why the function behaves wrongly if we make the 'dat' argument a 'constant' instead of a 'variable'
procedure sendData(variable dat : in std_logic_vector(19 downto 0)) is
begin
data_in <= '0';
wait_rand(start_time); -- Start bit
data_in <= '1';
for i in 0 to 19 loop -- once per bit
wait_rand(pause_time);
data_in <= '0';
if(dat(i)='0') then
wait_rand(zero_time);
elsif(dat(i)='1') then
wait_rand(one_time);
end if;
data_in <= '1';
end loop;
wait for 50*clk_period;
end procedure;
--temporiaries
variable data : std_logic_vector(19 downto 0);
begin
-- hold neutral state for 100 ns.
wait for 100 ns;
data_in <= '1';
reset <= '1'; -- push reset
wait for 10 ns;
reset <= '0'; -- release reset
wait for clk_period*10;
--Send only zeros
data := (others=>'0');
sendData(data);
--Send only ones
data := (others=>'1');
sendData(data);
--Send 10101...
data := ("10101010101010101010");
sendData(data);
--Send 01010...
data := ("01010101010101010101");
sendData(data);
--Send "Random"
data := ("11000101011100110101");
sendData(data);
wait;
end process;
end;
| lgpl-3.0 | 5e3d032cd0621096f4dba22ae8c3072e | 0.508986 | 4.408875 | false | false | false | false |
jhladky/ratload | RAT_CPU/prog_rom.vhd | 1 | 2,504 | ----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prog_rom is
Port( address : in STD_LOGIC_VECTOR(9 downto 0);
clk : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR(17 downto 0);
tristate_in : in STD_LOGIC_VECTOR(7 downto 0));
end prog_rom;
architecture prog_rom_a of prog_rom is
component real_prog_rom is
Port( address : in STD_LOGIC_VECTOR(9 downto 0);
clk : in STD_LOGIC;
instruction : out STD_LOGIC_VECTOR(17 downto 0));
end component;
component prog_ram is
Port( address : in STD_LOGIC_VECTOR(9 downto 0);
clk, we, oe : in STD_LOGIC;
ins_prog : in STD_LOGIC_VECTOR(17 downto 0);
instruction : out STD_LOGIC_VECTOR(17 downto 0));
end component;
component interceptor is
Port( ins_rom_in : in STD_LOGIC_VECTOR(17 downto 0);
ins_ram_in : in STD_LOGIC_VECTOR(17 downto 0);
clk : in STD_LOGIC;
address_in : in STD_LOGIC_VECTOR(9 downto 0);
data_in : in STD_LOGIC_VECTOR(7 downto 0);
address_out : out STD_LOGIC_VECTOR(9 downto 0);
ins_ram_prog: out STD_LOGIC_VECTOR(17 downto 0);
ins_out : out STD_LOGIC_VECTOR(17 downto 0);
ram_we : out STD_LOGIC;
ram_oe : out STD_LOGIC);
end component;
signal ram_we_i : STD_LOGIC;
signal ram_oe_i : STD_LOGIC;
signal address_out_i : STD_LOGIC_VECTOR(9 downto 0);
signal ins_ram_i : STD_LOGIC_VECTOR(17 downto 0);
signal ins_rom_i : STD_LOGIC_VECTOR(17 downto 0);
signal ins_prog_i : STD_LOGIC_VECTOR(17 downto 0);
begin
rpr1 : real_prog_rom port map(
address => address,
clk => clk,
instruction => ins_rom_i);
prog_ram1 : prog_ram port map(
address => address_out_i,
clk => clk,
we => ram_we_i,
oe => ram_oe_i,
instruction => ins_ram_i,
ins_prog => ins_prog_i);
int1 : interceptor port map(
ins_rom_in => ins_rom_i,
ins_ram_in => ins_ram_i,
ins_ram_prog => ins_prog_i,
clk => clk,
address_in => address,
address_out => address_out_i,
data_in => tristate_in,
ins_out => instruction,
ram_we => ram_we_i,
ram_oe => ram_oe_i);
end prog_rom_a;
| mit | 7e475ce9529a3e52b86698af1cc787ab | 0.539936 | 3.334221 | false | false | false | false |
545/Atari7800 | new_atari/project_1/project_1.srcs/sources_1/ip/ram1/synth/ram1.vhd | 1 | 14,179 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY ram1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram1;
ARCHITECTURE ram1_arch OF ram1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ram1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ram1_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ram1_arch : ARCHITECTURE IS "ram1,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ram1_arch: ARCHITECTURE IS "ram1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=ram1.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=ae,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 1.3396 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "ram1.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "ae",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 1.3396 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ram1_arch;
| gpl-2.0 | 341bf033da125b27a0ef3f97b7470e80 | 0.626067 | 3.024531 | false | false | false | false |
jhladky/ratload | RAT_CPU/ascii_to_int.vhd | 1 | 810 | ----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ascii_to_int is
Port( ascii_in : in STD_LOGIC_VECTOR (7 downto 0);
int_out : out STD_LOGIC_VECTOR (7 downto 0));
end ascii_to_int;
architecture ascii_to_int_a of ascii_to_int is begin
process(ascii_in) begin
if(ascii_in >= x"30" and ascii_in <= x"39") then
int_out <= ascii_in - x"30";
elsif(ascii_in >= x"41" and ascii_in <= x"46") then
int_out <= ascii_in - x"41" + 10;
else
int_out <= ascii_in;
end if;
end process;
end ascii_to_int_a;
| mit | ab9eec2f752ee59f1de2d9b357429bd1 | 0.509877 | 3.446809 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/Frame_Buf/synth/Frame_Buf.vhd | 1 | 14,604 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY Frame_Buf IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Frame_Buf;
ARCHITECTURE Frame_Buf_arch OF Frame_Buf IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Frame_Buf_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Frame_Buf_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Frame_Buf_arch : ARCHITECTURE IS "Frame_Buf,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Frame_Buf_arch: ARCHITECTURE IS "Frame_Buf,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=Frame_Buf.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.53475 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "Frame_Buf.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.53475 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Frame_Buf_arch;
| gpl-2.0 | 69c3ab19060eea021e1354e527263ca6 | 0.629622 | 3.039967 | false | false | false | false |
freecores/spi_boot | rtl/vhdl/spi_boot_pack-p.vhd | 1 | 1,068 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot_pack-p.vhd,v 1.1 2005-02-08 20:41:33 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spi_boot_pack is
function "=" (a : std_logic; b : integer) return boolean;
end spi_boot_pack;
package body spi_boot_pack is
function "=" (a : std_logic; b : integer) return boolean is
variable result_v : boolean;
begin
result_v := false;
case a is
when '0' =>
if b = 0 then
result_v := true;
end if;
when '1' =>
if b = 1 then
result_v := true;
end if;
when others =>
null;
end case;
return result_v;
end;
end spi_boot_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 8edb11eb9acd1418575f75f8b2f632fc | 0.390449 | 4.323887 | false | false | false | false |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/imports/dsp_base_project/low_pass_moving_sum.vhd | 1 | 1,616 | ------------------------------------------------------
-- low_pass : A generic DSP low pass filter.
--
-- It is a moving sum, as it doesn't divide by the
-- number of samples. Make sure that data_width is wide
-- enough that no overflows occur - you might have to
-- add leading zeros to sample_in!
--
-- PS. Also note that sample_in is unsigned.
--
-- Author : Mike Field <[email protected]>
--
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity low_pass_moving_sum is
generic ( data_width : natural := 16;
window_width : natural := 5);
Port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
sample_in : in STD_LOGIC_VECTOR (data_width-1 downto 0);
sample_out : out STD_LOGIC_VECTOR (data_width-1 downto 0));
end low_pass_moving_sum;
architecture Behavioral of low_pass_moving_sum is
signal total : unsigned( data_width-1 downto 0) := (others =>'0');
signal end_sample : STD_LOGIC_VECTOR ( data_width-1 downto 0);
signal delay_line : STD_LOGIC_VECTOR (window_width * data_width-1 downto 0) := (others => '0');
begin
end_sample <= Delay_line(Delay_line'high downto Delay_line'high-data_width+1);
sample_out <= std_logic_vector(total);
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
total <= total + unsigned(sample_in) - unsigned(end_sample);
delay_line <= Delay_line(Delay_line'high-data_width downto 0) & sample_in;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | e4b00fc7675619f6065781f0fdd9c2f5 | 0.593441 | 3.567329 | false | false | false | false |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/ip/CART_ROM/synth/CART_ROM.vhd | 1 | 13,900 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY CART_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CART_ROM;
ARCHITECTURE CART_ROM_arch OF CART_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF CART_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF CART_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF CART_ROM_arch : ARCHITECTURE IS "CART_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF CART_ROM_arch: ARCHITECTURE IS "CART_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=CART_ROM.mif,C_INIT_FILE=CART_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "CART_ROM.mif",
C_INIT_FILE => "CART_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END CART_ROM_arch;
| gpl-2.0 | 8b5bb6d075b96c4ee269a8bcd4610195 | 0.624388 | 3.022396 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/CHOPLIFTER_DROM/synth/CHOPLIFTER_DROM.vhd | 1 | 6,854 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY CHOPLIFTER_DROM IS
PORT (
a : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CHOPLIFTER_DROM;
ARCHITECTURE CHOPLIFTER_DROM_arch OF CHOPLIFTER_DROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF CHOPLIFTER_DROM_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF CHOPLIFTER_DROM_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF CHOPLIFTER_DROM_arch : ARCHITECTURE IS "CHOPLIFTER_DROM,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF CHOPLIFTER_DROM_arch: ARCHITECTURE IS "CHOPLIFTER_DROM,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_ADDR_WIDTH=15,C_DEFAULT_DATA=0,C_DEPTH=32768,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=CHOPLIFTER_DROM.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=8,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "zynq",
C_ADDR_WIDTH => 15,
C_DEFAULT_DATA => "0",
C_DEPTH => 32768,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "CHOPLIFTER_DROM.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 8,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END CHOPLIFTER_DROM_arch;
| gpl-2.0 | 25ab1d413ff1d80ec6ede8c7ac6647ac | 0.647505 | 3.220865 | false | false | false | false |
MonsieurOenologue/Paprotto | mux.vhd | 1 | 641 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END ENTITY mux;
ARCHITECTURE Behavior OF mux IS
SIGNAL Qs : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
mux : PROCESS(sel)
BEGIN
CASE sel IS
when "0100" =>
Qs <= a;
when "0011" =>
when "0101" =>
Qs <= c;
when "0110" =>
Qs <= d;
when "0111" =>
Qs <= e;
when "1000" =>
Qs <= f;
when others =>
NULL;
END CASE;
S <= Qs;
END PROCESS mux;
END ARCHITECTURE Behavior;
| gpl-3.0 | cb92c823d3fe5be4eb4757c9b9f86703 | 0.583463 | 2.627049 | false | false | false | false |
545/Atari7800 | core/cpu6502_true_cycle/trunk/rtl/vhdl/r6502_tc.vhd | 1 | 4,891 | -- VHDL Entity R6502_TC.R6502_TC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:53 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY R6502_TC IS
PORT(
clk_clk_i : IN std_logic;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic;
nmi_n_i : IN std_logic;
rdy_i : IN std_logic;
rst_rst_n_i : IN std_logic;
so_n_i : IN std_logic;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic;
sync_o : OUT std_logic;
wr_n_o : OUT std_logic;
wr_o : OUT std_logic
);
-- Declarations
END R6502_TC ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: struct.bd,v $
-- <<-- more -->>
-- Title: Top Level
-- Path: R6502_TC/R6502_TC/struct
-- Edited: by eda on 08 Feb 2010
--
-- VHDL Architecture R6502_TC.R6502_TC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW1)
-- at - 14:13:53 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY R6502_TC;
ARCHITECTURE struct OF R6502_TC IS
-- Architecture declarations
-- Internal signal declarations
-- Component Declarations
COMPONENT Core
PORT (
clk_clk_i : IN std_logic ;
d_i : IN std_logic_vector (7 DOWNTO 0);
irq_n_i : IN std_logic ;
nmi_n_i : IN std_logic ;
rdy_i : IN std_logic ;
rst_rst_n_i : IN std_logic ;
so_n_i : IN std_logic ;
a_o : OUT std_logic_vector (15 DOWNTO 0);
d_o : OUT std_logic_vector (7 DOWNTO 0);
rd_o : OUT std_logic ;
sync_o : OUT std_logic ;
wr_n_o : OUT std_logic ;
wr_o : OUT std_logic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : Core USE ENTITY R6502_TC.Core;
-- pragma synthesis_on
BEGIN
-- Instance port mappings.
U_0 : Core
PORT MAP (
clk_clk_i => clk_clk_i,
d_i => d_i,
irq_n_i => irq_n_i,
nmi_n_i => nmi_n_i,
rdy_i => rdy_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
d_o => d_o,
rd_o => rd_o,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
END struct;
| gpl-2.0 | cd8189c6268772a9f2231b08b5959277 | 0.388264 | 4.35918 | false | false | false | false |
545/Atari7800 | core/t65/trunk/rtl/vhdl/T65_Pack.vhd | 1 | 4,479 | --
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Res_n : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end component;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;
| gpl-2.0 | 9237a007d6b6568e20be9fb29efc43d3 | 0.67649 | 3.010081 | false | false | false | false |
aysteph3/MiniMIPS_Testing | src/testbench.vhd | 1 | 4,851 | library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use ieee.math_real.all;
use std.textio.all;
use work.pack_mips.all;
USE work.my_package.ALL;
entity testbench is
end testbench;
architecture behaviour of testbench is
-- component declaration
component alu is
port(
clock : in bus1;
reset : in bus1;
op1 : in bus32; -- Operand 1
op2 : in bus32; -- Operand 2
ctrl : in alu_ctrl_type; -- Opearator control
res : out bus32; -- The result is 32 bit long
overflow : out bus1 -- Overflow of the result
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '1';
signal op1 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal op2 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal ctrl : std_logic_vector(27 downto 0) := "0000000000000000000000000000";
--signal c : std_logic_vector(27 downto 0) := "1000000000000000000000000000";
signal res : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal overflow : std_logic := '0';
constant clk_period : time := 10 ns;
begin
uut: alu port map(
clock => clock,
reset => reset,
op1 => op1,
op2 => op2,
ctrl => ctrl,
res => res,
overflow => overflow
);
reset <= '0' after 10 ns;
clk_process:
process
begin
clock <= '0';
wait for clk_period/2; --for 5 ns signal is '0'.
clock <= '1';
wait for clk_period/2; --for next 5 ns signal is '1'.
end process;
monitor:
process
variable count_value : integer := 0;
file out_file : text open write_mode is "sim_generated_file/out.txt";
file input_file : text; --declare input file
variable line_v : line;
variable line_num : line;
variable char : character:='0';
variable a, b : string(1 to 32);
variable num_1 : std_logic_vector (31 downto 0); -- num_1 and num_2 are declared as variable
variable num_2 : std_logic_vector (31 downto 0);
variable c : std_logic_vector(27 downto 0) := "1000000000000000000000000000";
begin
--while (count_value < c'length) loop
file_open(input_file, "sim_input/input.txt", read_mode);
wait for 5 ns;
--f: loop
while not endfile(input_file) loop
c := "1000000000000000000000000000";
count_value := 0;
readline(input_file, line_num);
read(line_num, a);
read(line_num, b);
for idx in 1 to 32 loop
char := a(idx);
if(char = '0') then
num_1(32-idx) := '0';
else
num_1(32-idx) := '1';
end if;
end loop;
for id in 1 to 32 loop
char := b(id);
if(char = '0') then
num_2(32-id) := '0';
else
num_2(32-id) := '1';
end if;
end loop;
op1 <= num_1;
op2 <= num_2;
wait for 1 ns;
write(line_v, to_bstring(op1)& " " & to_bstring(op2));
while (count_value < c'length) loop
ctrl <= std_logic_vector(signed(c) srl count_value);
wait for 10 ns;
--wait until rising_edge(clock);
--write(line_v, to_bstring(ctrl)& " " & to_bstring(op1)& " " & to_bstring(op2)& " " & to_bstring(res));
write(line_v, " " & to_bstring(res));
--writeline(out_file, line_v);
wait for 3 ns;
count_value := count_value + 1;
end loop; -- end of while loop
wait for 1 ns;
--exit f when endfile(input_file);
write(line_v, string'(""));
writeline(out_file, line_v);
end loop; -- end of file while loop end of f loop
--write(line_v, string'(""));
--writeline(out_file, line_v);
wait for 1 ns;
file_close(input_file);
--count_value := count_value + 1;
--end loop; -- end of while loop
file_close(out_file);
wait;
end process;
end;
| gpl-3.0 | 9c7f3a4a6f2df5fb8a5a50a0665aee1d | 0.473923 | 4.142613 | false | false | false | false |
freecores/gamepads | snespad/rtl/vhdl/snespad_pack-p.vhd | 1 | 2,481 | -------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- $Id: snespad_pack-p.vhd,v 1.1 2004-10-05 17:01:27 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package snespad_pack is
constant num_buttons_c : natural := 12;
subtype buttons_t is std_logic_vector(num_buttons_c-1 downto 0);
subtype num_buttons_read_t is natural range 0 to num_buttons_c-1;
function button_active_f(state : in std_logic; ref : in natural) return std_logic;
function button_reset_f(ref : in natural) return std_logic;
function "=" (a : std_logic; b : integer) return boolean;
-----------------------------------------------------------------------------
-- The button positions inside the SNES packet
-----------------------------------------------------------------------------
constant but_pos_b_c : natural := 11;
constant but_pos_y_c : natural := 10;
constant but_pos_sel_c : natural := 9;
constant but_pos_start_c : natural := 8;
constant but_pos_up_c : natural := 7;
constant but_pos_down_c : natural := 6;
constant but_pos_left_c : natural := 5;
constant but_pos_right_c : natural := 4;
constant but_pos_a_c : natural := 3;
constant but_pos_x_c : natural := 2;
constant but_pos_tl_c : natural := 1;
constant but_pos_tr_c : natural := 0;
end snespad_pack;
package body snespad_pack is
function button_active_f(state : in std_logic; ref : in natural) return std_logic is
variable result_v : std_logic;
begin
if ref = 0 then
result_v := state;
else
result_v := not state;
end if;
return result_v;
end button_active_f;
function button_reset_f(ref : in natural) return std_logic is
variable result_v : std_logic;
begin
if ref = 0 then
result_v := '1';
else
result_v := '0';
end if;
return result_v;
end button_reset_f;
function "=" (a : std_logic; b : integer) return boolean is
variable result_v : boolean;
begin
result_v := false;
case a is
when '0' =>
if b = 0 then
result_v := true;
end if;
when '1' =>
if b = 1 then
result_v := true;
end if;
when others =>
null;
end case;
return result_v;
end;
end snespad_pack;
| gpl-2.0 | 22eb24d2f8274ea8fb05c1f9d20edf5a | 0.532447 | 3.686478 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/CTRL_CRLF/CTRL_CRLF_VHDL.vhd | 2 | 3,095 | -- CTRL_CRLF
-- Carriage Return Line Fed bei Telegrammende in den zu sendenen Datenstrom einfügen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_CRLF_VHDL is
Port(BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
BYTE_OK : in std_logic; --Eingangsvariable, Byte OK
T_CMPLT : in std_logic; --Eingangsvariabel, Telegramm vollständig
BYTE_SEND : out std_logic_vector (7 downto 0); --Ausgangsvariable, zu sendene Daten, 8 bit
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_CRLF_VHDL;
architecture Behavioral of CTRL_CRLF_VHDL is
type TYPE_STATE is
(ST_CRLF_00, --Zustaende CTRL_CRLF
ST_CRLF_01,
ST_CRLF_02,
ST_CRLF_03);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
--signal not_CLK : std_logic; --negierte Taktvariable
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CRLF_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CRLF_00;
else
if falling_edge(CLK)
then SV <= SV_M;
end if;
end if;
end process;
CTRL_CRLF_PROC:process (BYTE_IN, BYTE_OK, T_CMPLT, SV) --Wenn Byte ok dann Output=Input, wenn Byte ok und Telegramm komplett dann OUTPUT=CRLF
begin
case SV is
when ST_CRLF_00 =>
if (BYTE_OK = '1')
then
--CR01
BYTE_SEND <= BYTE_IN; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
else
--CR00
BYTE_SEND <= BYTE_IN; --Output=Input
n_sv <= ST_CRLF_00; --bleibt im Zustand
end if;
when ST_CRLF_01 =>
if (T_CMPLT = '1')
then
--CR02
BYTE_SEND <= x"0D"; --Carriage Return
n_SV <= ST_CRLF_02; --Zustandsübergang
else
--CR01
BYTE_SEND <= BYTE_IN; --Output=Input
n_sv <= ST_CRLF_01; --Zustandsübergang
end if;
when ST_CRLF_02 =>
--CR03
BYTE_SEND <= x"0A"; --Line Feed
n_SV <= ST_CRLF_00; --Zustandsübergang
when others =>
-- CR00
BYTE_SEND <= BYTE_IN; --Output=Input
n_SV <= ST_CRLF_00; --Zustandsübergang
end case;
end process;
end Behavioral;
| gpl-2.0 | 4071eb32586136e20f72076a53c3fdd7 | 0.601616 | 3.247639 | false | false | false | false |
freecores/gamepads | gcpad/bench/vhdl/tb.vhd | 1 | 28,127 | -------------------------------------------------------------------------------
--
-- Testbench for the
-- GCpad controller core
--
-- $Id: tb.vhd,v 1.4 2004-10-10 20:19:49 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end tb;
use work.gcpad_pack.all;
use work.gcpad_comp.gcpad_basic;
use work.gcpad_comp.gcpad_full;
architecture behav of tb is
-----------------------------------------------------------------------------
-- Some known commands for the GC controller
-----------------------------------------------------------------------------
constant cmd_get_id_c : std_logic_vector(7 downto 0) := "00000000";
constant cmd_poll_c : std_logic_vector(7 downto 0) := "01000000";
component gcpad_mod
generic (
clocks_per_1us_g : natural := 2
);
port (
clk_i : in std_logic;
pad_data_io : inout std_logic;
rx_data_i : in std_logic_vector(63 downto 0)
);
end component;
constant period_c : time := 100 ns;
constant reset_level_c : natural := 0;
constant clocks_per_1us_c : natural := 10;
signal clk_s : std_logic;
signal reset_s : std_logic;
-- signals for basic gcpad
signal stimuli_1_end_s : boolean;
signal pad_data_1_s : std_logic;
signal buttons_1_s : std_logic_vector(64 downto 0);
signal pad_request_1_s : std_logic;
signal pad_avail_1_s : std_logic;
signal pad_model_data_1_s : std_logic_vector(63 downto 0);
-- signals for full gcpad
signal stimuli_2_end_s : boolean;
signal pad_data_2_s : std_logic;
signal pad_request_2_s : std_logic;
signal pad_avail_2_s : std_logic;
signal pad_timeout_2_s : std_logic;
signal tx_size_2_s : std_logic_vector( 1 downto 0);
signal tx_command_2_s : std_logic_vector(23 downto 0);
signal rx_size_2_s : std_logic_vector( 3 downto 0);
signal rx_data_2_s : std_logic_vector(63 downto 0);
signal pad_model_data_2_s : std_logic_vector(63 downto 0);
begin
basic_b : gcpad_basic
generic map (
reset_level_g => reset_level_c,
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_request_i => pad_request_1_s,
pad_avail_o => pad_avail_1_s,
pad_data_io => pad_data_1_s,
but_a_o => buttons_1_s(56),
but_b_o => buttons_1_s(57),
but_x_o => buttons_1_s(58),
but_y_o => buttons_1_s(59),
but_z_o => buttons_1_s(52),
but_start_o => buttons_1_s(60),
but_tl_o => buttons_1_s(54),
but_tr_o => buttons_1_s(53),
but_left_o => buttons_1_s(48),
but_right_o => buttons_1_s(49),
but_up_o => buttons_1_s(51),
but_down_o => buttons_1_s(50),
ana_joy_x_o => buttons_1_s(47 downto 40),
ana_joy_y_o => buttons_1_s(39 downto 32),
ana_c_x_o => buttons_1_s(31 downto 24),
ana_c_y_o => buttons_1_s(23 downto 16),
ana_l_o => buttons_1_s(15 downto 8),
ana_r_o => buttons_1_s( 7 downto 0)
);
buttons_1_s(64) <= '0';
buttons_1_s(63 downto 61) <= (others => '0');
buttons_1_s(55) <= '1';
full_b: gcpad_full
generic map (
reset_level_g => reset_level_c,
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_request_i => pad_request_2_s,
pad_avail_o => pad_avail_2_s,
pad_timeout_o => pad_timeout_2_s,
tx_size_i => tx_size_2_s,
tx_command_i => tx_command_2_s,
rx_size_i => rx_size_2_s,
rx_data_o => rx_data_2_s,
pad_data_io => pad_data_2_s
);
pad_1 : gcpad_mod
generic map (
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
pad_data_io => pad_data_1_s,
rx_data_i => pad_model_data_1_s
);
-----------------------------------------------------------------------------
-- Process stimuli_pad_1
--
-- Executes test stimuli with Pad 1, the gcpad_basic flavour.
--
stimuli_pad_1: process
---------------------------------------------------------------------------
-- Procedure poll_pad
--
-- Requests the status of Pad 1 and checks the received data.
--
procedure poll_pad(packet : in std_logic_vector(63 downto 0)) is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
pad_model_data_1_s <= packet;
-- send request;
pad_request_1_s <= '1';
wait for 1 * period_c;
pad_request_1_s <= '0';
wait for 10 * 40 * period_c;
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
-- check result
for i in 0 to packet'high loop
assert packet(i) = buttons_1_s(i)
report "Button mismatch on Pad 1!"
severity error;
end loop;
end poll_pad;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure timeout_gcpad
--
-- Generates a timeout in gcpad_basic by disturbing the communication.
--
procedure timeout_gcpad is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
-- send request;
pad_request_1_s <= '1';
wait for 1 * period_c;
pad_request_1_s <= '0';
wait for 2 * period_c;
-- disturb communication
pad_data_1_s <= 'X';
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
pad_data_1_s <= 'H';
wait for 10 * period_c;
end timeout_gcpad;
--
---------------------------------------------------------------------------
begin
stimuli_1_end_s <= false;
pad_data_1_s <= 'H';
pad_request_1_s <= '0';
pad_model_data_1_s <= (others => '0');
wait until reset_s = '1';
wait for period_c * 4;
timeout_gcpad;
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
wait for clocks_per_1us_c * 100 * period_c;
poll_pad(packet => "0001111111111111111111111111111111111111111111111111111111111111");
poll_pad(packet => "0001000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000100010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000010010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000001010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000110000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000101010101010101010101010101010101010101010101010101010101010");
poll_pad(packet => "0001010111010101010101010101010101010101010101010101010101010101");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000011000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010100000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010010000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010001000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000100000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000010000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000001000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000100000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000010000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000001000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000100000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000010000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000001000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000100000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000010000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000001000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000100000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000010000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000001000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000100000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000010000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000001000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000100000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000010000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000001000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000100000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000010000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000001000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000100000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000010000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000001000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000100000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000010000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000001000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000100000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000010000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000001000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000100000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000010000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000001000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000100000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000010000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000001000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000100000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000010000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000001000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000100000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000010000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000001000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000100000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000010000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000001000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000100");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000010");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000001");
wait for period_c * 2*40;
stimuli_1_end_s <= true;
wait;
end process stimuli_pad_1;
--
-----------------------------------------------------------------------------
pad_2 : gcpad_mod
generic map (
clocks_per_1us_g => clocks_per_1us_c
)
port map (
clk_i => clk_s,
pad_data_io => pad_data_2_s,
rx_data_i => pad_model_data_2_s
);
-----------------------------------------------------------------------------
-- Process stimuli_pad_2
--
-- Executes test stimuli with Pad 2, the gcpad_full flavour.
--
stimuli_pad_2: process
---------------------------------------------------------------------------
-- Procedure issue_command
--
-- Sets the transmitter command for Pad 2 and starts the request.
--
procedure issue_command(cmd : in std_logic_vector(23 downto 0);
size : in std_logic_vector( 1 downto 0)) is
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
tx_command_2_s <= cmd;
tx_size_2_s <= size;
-- send request;
pad_request_2_s <= '1';
wait for 1 * period_c;
pad_request_2_s <= '0';
end issue_command;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure poll_pad
--
-- Requests the status of Pad 2 and checks the received data.
--
procedure poll_pad(packet : in std_logic_vector(63 downto 0)) is
variable cmd_v : std_logic_vector(23 downto 0);
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
-- set up model answer
pad_model_data_2_s <= packet;
-- set expected number of bytes for gcpad_full
rx_size_2_s <= "1000";
cmd_v(23 downto 16) := cmd_poll_c;
cmd_v(15 downto 0) := "0000001100000010";
issue_command(cmd => cmd_v,
size => "11");
wait until pad_avail_2_s = '1';
assert pad_timeout_2_s = '0'
report "Timout signalled on Pad 2 during status polling!"
severity error;
-- check result
for i in 0 to packet'high loop
assert packet(i) = rx_data_2_s(i)
report "Data mismatch on Pad 2!"
severity error;
end loop;
end poll_pad;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure timeout_gcpad_x
--
-- Generates a timeout in gcpad_full by disturbing the communication.
--
procedure timeout_gcpad_x is
variable cmd_v : std_logic_vector(23 downto 0);
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
pad_model_data_2_s <= (others => '0');
rx_size_2_s <= "1000";
cmd_v(23 downto 16) := cmd_poll_c;
cmd_v(15 downto 0) := "0000001100000010";
issue_command(cmd => cmd_v,
size => "11");
-- disturb communication
pad_data_2_s <= 'X';
wait until pad_avail_1_s = '1';
wait for 10 * period_c;
pad_data_2_s <= 'H';
wait for 10 * period_c;
assert pad_timeout_2_s = '1'
report "No timeout indicated on Pad 2 when communication has been disturbed!"
severity error;
end timeout_gcpad_x;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure timeout_gcpad_short
--
-- Generates a timeout in gcpad_full by requesting too many bytes for
-- a "get id" command.
--
procedure timeout_gcpad_short is
variable cmd_v : std_logic_vector(23 downto 0);
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
-- expect too many number of bytes
-- command is "get id", will yield 3 bytes, but 8 bytes are requested
rx_size_2_s <= "1000";
cmd_v(23 downto 16) := cmd_get_id_c;
cmd_v(15 downto 0) := (others => '1');
issue_command(cmd => cmd_v,
size => "01");
wait until pad_avail_2_s = '1';
assert pad_timeout_2_s = '1'
report "No timout indicated on Pad 2 when too many bytes requested!"
severity error;
end timeout_gcpad_short;
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Procedure get_id
--
-- Requests the ID information from the GC controller model.
--
procedure get_id is
variable cmd_v : std_logic_vector(23 downto 0);
constant id_c : std_logic_vector(23 downto 0) := "000010010000000000000000";
begin
wait until clk_s'event and clk_s = '1';
wait for 1 ns;
rx_size_2_s <= "0011";
cmd_v(23 downto 16) := cmd_get_id_c;
cmd_v(15 downto 0) := (others => '1');
issue_command(cmd => cmd_v,
size => "01");
wait until pad_avail_2_s = '1';
assert pad_timeout_2_s = '0'
report "Timout signalled on Pad 2 during get id!"
severity error;
-- check result
for i in 0 to id_c'high loop
assert id_c(i) = rx_data_2_s(i)
report "ID mismatch on Pad 2!"
severity error;
end loop;
end get_id;
--
---------------------------------------------------------------------------
begin
stimuli_2_end_s <= false;
pad_data_2_s <= 'H';
pad_request_2_s <= '0';
tx_size_2_s <= (others => '0');
tx_command_2_s <= (others => '0');
rx_size_2_s <= (others => '0');
pad_model_data_2_s <= (others => '0');
wait until reset_s = '1';
wait for period_c * 4;
get_id;
timeout_gcpad_x;
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
wait for clocks_per_1us_c * 100 * period_c;
poll_pad(packet => "0001111111111111111111111111111111111111111111111111111111111111");
timeout_gcpad_short;
poll_pad(packet => "0001000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000100010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000010010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000001010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000110000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000101010101010101010101010101010101010101010101010101010101010");
poll_pad(packet => "0001010111010101010101010101010101010101010101010101010101010101");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000011000000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010100000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010010000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010001000000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000100000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000010000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000001000000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000100000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000010000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000001000000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000100000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000010000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000001000000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000100000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000010000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000001000000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000100000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000010000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000001000000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000100000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000010000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000001000000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000100000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000010000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000001000000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000100000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000010000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000001000000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000100000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000010000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000001000000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000100000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000010000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000001000000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000100000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000010000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000001000000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000100000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000010000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000001000000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000100000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000010000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000001000000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000100000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000010000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000001000000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000100000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000010000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000001000000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000100000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000010000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000001000");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000100");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000010");
poll_pad(packet => "0000000010000000000000000000000000000000000000000000000000000001");
wait for period_c * 2*40;
stimuli_2_end_s <= true;
wait;
end process stimuli_pad_2;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
-----------------------------------------------------------------------------
-- End of simulation detection
-----------------------------------------------------------------------------
eos: process (stimuli_1_end_s, stimuli_2_end_s)
begin
if stimuli_1_end_s and stimuli_2_end_s then
assert false
report "End of simulation reached."
severity failure;
end if;
end process eos;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/10/10 17:27:44 arniml
-- added second pad
-- introduced testbench model for GC controller
--
-- Revision 1.2 2004/10/09 17:05:59 arniml
-- delay assertion of request signal by real time (instead of delta cycles)
--
-- Revision 1.1 2004/10/07 21:24:06 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 16ce7eff7bc5f8c2900fc80c4114e32c | 0.63711 | 4.911297 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_9P6_50MHZ_SCH/CTRL_9P6_50MHZ_VHDL.vhd | 6 | 21,554 | -- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
| gpl-2.0 | 43a795d2c52f998e6cf13a21b3281c71 | 0.466364 | 2.614508 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_19_12_2012/TEST_CTRL_9P6_50MHZ_SCH/CTRL_9P6_50MHZ.vhd | 4 | 44,911 | -- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
STOP : in std_logic; --Eingangsvariable, Stopp nach einem Byte
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
CTRL_STOP : out std_logic; --Ausgangsvariable, Stopp anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (8 downto 0); --Ausgangsvariable, Vektor >> Normal:(7 downto 0); TEST:(8 downto 0)
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, STOP, ERROR_QUIT, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (STOP = '1')
then
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; -- Stopp nach einem Byte
else --STOP_S = '0'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
BYTE_OUT(8) <= BYTE_VEC(8); --Bit 8 Test, nach Test entfernen
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
| gpl-2.0 | 2e06ce1abc8bb8d60c8087ca1cb7e459 | 0.514262 | 2.544388 | false | false | false | false |
freecores/gamepads | snespad/rtl/vhdl/snespad_pad.vhd | 1 | 5,661 | -------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad_pad.vhd,v 1.2 2005-09-15 17:28:02 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity snespad_pad is
generic (
reset_level_g : natural := 0;
button_level_g : natural := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_i : in boolean;
-- Control Interface ------------------------------------------------------
shift_buttons_i : in boolean;
save_buttons_i : in boolean;
-- Pad Interface ----------------------------------------------------------
pad_data_i : in std_logic;
-- Buttons Interface ------------------------------------------------------
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_start_o : out std_logic;
but_sel_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic
);
end snespad_pad;
use work.snespad_pack.all;
architecture rtl of snespad_pad is
signal buttons_q,
shift_buttons_q : buttons_t;
begin
-- pragma translate_off
-----------------------------------------------------------------------------
-- Check generics
-----------------------------------------------------------------------------
assert (reset_level_g = 0) or (reset_level_g = 1)
report "reset_level_g must be either 0 or 1!"
severity failure;
assert (button_level_g = 0) or (button_level_g = 1)
report "button_level_g must be either 0 or 1!"
severity failure;
-- pragma translate_on
seq: process (reset_i, clk_i)
begin
if reset_i = reset_level_g then
for i in buttons_t'range loop
buttons_q(i) <= button_reset_f(button_level_g);
shift_buttons_q(i) <= button_reset_f(button_level_g);
end loop;
elsif clk_i'event and clk_i = '1' then
if save_buttons_i then
buttons_q <= shift_buttons_q;
end if;
if clk_en_i and shift_buttons_i then
shift_buttons_q(buttons_t'high downto 1) <= shift_buttons_q(buttons_t'high-1 downto 0);
shift_buttons_q(0) <= button_active_f(pad_data_i, button_level_g);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
but_a_o <= buttons_q(but_pos_a_c);
but_b_o <= buttons_q(but_pos_b_c);
but_x_o <= buttons_q(but_pos_x_c);
but_y_o <= buttons_q(but_pos_y_c);
but_start_o <= buttons_q(but_pos_start_c);
but_sel_o <= buttons_q(but_pos_sel_c);
but_tl_o <= buttons_q(but_pos_tl_c);
but_tr_o <= buttons_q(but_pos_tr_c);
but_up_o <= buttons_q(but_pos_up_c);
but_down_o <= buttons_q(but_pos_down_c);
but_left_o <= buttons_q(but_pos_left_c);
but_right_o <= buttons_q(but_pos_right_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/10/05 17:01:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | adde36a42cd6b1bcca015e06d4ca5839 | 0.551316 | 3.933982 | false | false | false | false |
akshayp/college-projects | vhdl/pong/display.vhd | 1 | 27,821 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY display IS
PORT(Clock : IN STD_LOGIC;
ROW, COLUMN : IN INTEGER RANGE 0 TO 64;
PADDLE1,PADDLE2 : IN INTEGER RANGE 0 TO 48;
OUT1,OUT2 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
Horiz_sync, Vert_sync : OUT STD_LOGIC;
RED, GREEN, BLUE : OUT STD_LOGIC);
END display;
ARCHITECTURE NEW1 OF display IS
-- Video Display Signals
signal Horiz_Count,Vert_Count: std_logic_vector(9 Downto 0);
signal R, G, B : std_logic;
-- Signals for Video Memory for Pixel Data
signal col_address, row_address: std_logic_vector(7 Downto 0);
signal col_count, row_count: std_logic_vector(2 Downto 0);
constant H_max : std_logic_vector(9 Downto 0) := CONV_STD_LOGIC_VECTOR(799,10);
-- 799 is max horiz count
constant V_max : std_logic_vector(9 Downto 0) := CONV_STD_LOGIC_VECTOR(524,10);
-- 524 is max vert count
begin
Red <= R ;
Green <= G;
Blue <= B;
-----------------------------------------------------
--Generate Horizontal and Vertical Timing Signals for Video Signal
VIDEO_DISPLAY: Process
Begin
Wait until(Clock'Event and Clock='1');
-- Horiz_Count counts pixels (640 + extra time for sync signals)
If (Horiz_Count >= H_max) then
Horiz_Count <= To_Stdlogicvector(B"0000000000");
Else
Horiz_Count <= Horiz_Count + To_Stdlogicvector(B"0000000001");
End if;
--Generate Horizontal Sync Signal
If (Horiz_Count <= CONV_STD_LOGIC_VECTOR(755,10)) and (Horiz_Count >= CONV_STD_LOGIC_VECTOR(659,10)) Then
Horiz_Sync <= '0';
ELSE
Horiz_Sync <= '1';
End if;
--Vert_Count counts rows of pixels (480 + extra time for sync signals)
If (Vert_Count >= V_max) and (Horiz_Count >= CONV_STD_LOGIC_VECTOR(699,10)) then
Vert_Count <= To_Stdlogicvector(B"0000000000");
Else If (Horiz_Count = CONV_STD_LOGIC_VECTOR(699,10)) Then
Vert_Count <= Vert_Count + To_Stdlogicvector(B"0000000001");
End if;
-- Generate Vertical Sync Signal
If (Vert_Count <= CONV_STD_LOGIC_VECTOR(494,10)) and (Vert_Count >= CONV_STD_LOGIC_VECTOR(493,10)) Then
Vert_Sync <= '0';
ELSE
Vert_Sync <= '1';
End if;
-- Generate row and col address for 7 by 5 superpixel to map into 64 by 64 video memory
if (Horiz_Count <= CONV_STD_LOGIC_VECTOR(639,10)) Then
If col_count < CONV_STD_LOGIC_VECTOR(7,3) Then
col_count <= col_count + '1';
Else
col_count <= "000";
col_address <= col_address + '1';
End if;
ELSE
col_count <= "000";
col_address <= "00000000";
End if;
IF(HORIZ_COUNT = CONV_STD_LOGIC_VECTOR(641,10)) Then
row_count <= row_count + '1';
If (row_count = CONV_STD_LOGIC_VECTOR(5,3)) THEN
row_count <= "000";
row_address <= row_address + '1';
End if;
End if;
If (Vert_Count >= CONV_STD_LOGIC_VECTOR(479,10)) Then
row_count <= "000";
row_address <= "00000000";
End if;
end if;
end process VIDEO_DISPLAY;
RGB:PROCESS(PADDLE1, PADDLE2, ROW, COLUMN, OUT1, OUT2)
BEGIN
--BOUNDARY
IF row_address = CONV_STD_LOGIC_VECTOR(15,8) AND col_address >= CONV_STD_LOGIC_VECTOR(15,8) AND col_address <= CONV_STD_LOGIC_VECTOR(89,8) THEN
R <= '1';
G <= '0';
B <= '0';
ELSIF row_address = CONV_STD_LOGIC_VECTOR(49,8) AND col_address >= CONV_STD_LOGIC_VECTOR(15,8) AND col_address <= CONV_STD_LOGIC_VECTOR(89,8) THEN
R <= '1';
G <= '0';
B <= '0';
--ELSIF col_address = CONV_STD_LOGIC_VECTOR(15,8) AND row_address >= CONV_STD_LOGIC_VECTOR(15,8) AND row_address <= CONV_STD_LOGIC_VECTOR(89,8) THEN
-- R <= '1';
-- G <= '0';
-- B <= '0';
--ELSIF col_address = CONV_STD_LOGIC_VECTOR(49,8) AND row_address >= CONV_STD_LOGIC_VECTOR(15,8) AND row_address <= CONV_STD_LOGIC_VECTOR(89,8) THEN
-- R <= '1';
-- G <= '0';
-- B <= '0';
END IF;
--PADDLE1
FOR i IN 0 TO 32 LOOP
IF col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(15+i,8) OR row_address = CONV_STD_LOGIC_VECTOR(16+i,8) OR row_address = CONV_STD_LOGIC_VECTOR(17+i,8) OR row_address = CONV_STD_LOGIC_VECTOR(18+i,8)) THEN
R <= '1';
G <= '0';
B <= '1';
END IF;
END loop;
--PADDLE2
FOR i IN 0 TO 32 LOOP
IF col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(15+i,8) OR row_address = CONV_STD_LOGIC_VECTOR(16+i,8) OR row_address = CONV_STD_LOGIC_VECTOR(17+i,8) OR row_address = CONV_STD_LOGIC_VECTOR(18+i,8)) THEN
R <= '1';
G <= '0';
B <= '1';
END IF;
END LOOP;
--BALL
IF row_address = CONV_STD_LOGIC_VECTOR(ROW,8) AND col_address = CONV_STD_LOGIC_VECTOR(COLUMN,8) THEN
R <= '1';
G <= '1';
B <= '0';
END IF;
--SCORES
--SCORE OF PLAYER 1
IF OUT1(6) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(29,8) AND (col_address = CONV_STD_LOGIC_VECTOR(8,8) OR col_address = CONV_STD_LOGIC_VECTOR(9,8) OR col_address = CONV_STD_LOGIC_VECTOR(10,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT1(5) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(10,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT1(4) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(10,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT1(3) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(33,8) AND (col_address = CONV_STD_LOGIC_VECTOR(8,8) OR col_address = CONV_STD_LOGIC_VECTOR(9,8) OR col_address = CONV_STD_LOGIC_VECTOR(10,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT1(2) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(8,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT1(1) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(8,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT1(0) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(31,8) AND (col_address = CONV_STD_LOGIC_VECTOR(8,8) OR col_address = CONV_STD_LOGIC_VECTOR(9,8) OR col_address = CONV_STD_LOGIC_VECTOR(10,8)) THEN
R <= '1';
G <='1';
B <= '1';
END IF;
--SCORE OF PLAYER 2
IF OUT2(6) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(29,8) AND (col_address = CONV_STD_LOGIC_VECTOR(54,8) OR col_address = CONV_STD_LOGIC_VECTOR(55,8) OR col_address = CONV_STD_LOGIC_VECTOR(56,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT2(5) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(56,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT2(4) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(56,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT2(3) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(33,8) AND (col_address = CONV_STD_LOGIC_VECTOR(54,8) OR col_address = CONV_STD_LOGIC_VECTOR(55,8) OR col_address = CONV_STD_LOGIC_VECTOR(56,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT2(2) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(54,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT2(1) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(54,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)) THEN
R <= '1';
G <='1';
B <= '1';
ELSIF OUT2(0) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(31,8) AND (col_address = CONV_STD_LOGIC_VECTOR(54,8) OR col_address = CONV_STD_LOGIC_VECTOR(55,8) OR col_address = CONV_STD_LOGIC_VECTOR(56,8)) THEN
R <= '1';
G <='1';
B <= '1';
END IF;
--REST OF THE SCREEN IS BLACKENED SO THAT THERE IS LESS POWER CONSUMPTION FROM THE SCREEN
IF (NOT(row_address = CONV_STD_LOGIC_VECTOR(15,8) AND col_address >= CONV_STD_LOGIC_VECTOR(15,8) AND col_address <= CONV_STD_LOGIC_VECTOR(49,8))AND
NOT(row_address = CONV_STD_LOGIC_VECTOR(49,8) AND col_address >= CONV_STD_LOGIC_VECTOR(15,8) AND col_address <= CONV_STD_LOGIC_VECTOR(49,8))AND
--NOT(col_address = CONV_STD_LOGIC_VECTOR(15,8) AND row_address >= CONV_STD_LOGIC_VECTOR(15,8) AND row_address <= CONV_STD_LOGIC_VECTOR(49,8))AND
--NOT(col_address = CONV_STD_LOGIC_VECTOR(49,8) AND row_address >= CONV_STD_LOGIC_VECTOR(15,8) AND row_address <= CONV_STD_LOGIC_VECTOR(49,8))AND
NOT(PADDLE1=17 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(15,8) OR row_address = CONV_STD_LOGIC_VECTOR(16,8) OR row_address = CONV_STD_LOGIC_VECTOR(17,8) OR row_address = CONV_STD_LOGIC_VECTOR(18,8)))AND
NOT(PADDLE1=18 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(16,8) OR row_address = CONV_STD_LOGIC_VECTOR(17,8) OR row_address = CONV_STD_LOGIC_VECTOR(18,8) OR row_address = CONV_STD_LOGIC_VECTOR(19,8)))AND
NOT(PADDLE1=19 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(17,8) OR row_address = CONV_STD_LOGIC_VECTOR(18,8) OR row_address = CONV_STD_LOGIC_VECTOR(19,8) OR row_address = CONV_STD_LOGIC_VECTOR(20,8)))AND
NOT(PADDLE1=20 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(18,8) OR row_address = CONV_STD_LOGIC_VECTOR(19,8) OR row_address = CONV_STD_LOGIC_VECTOR(20,8) OR row_address = CONV_STD_LOGIC_VECTOR(21,8)))AND
NOT(PADDLE1=21 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(19,8) OR row_address = CONV_STD_LOGIC_VECTOR(20,8) OR row_address = CONV_STD_LOGIC_VECTOR(21,8) OR row_address = CONV_STD_LOGIC_VECTOR(22,8)))AND
NOT(PADDLE1=22 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(20,8) OR row_address = CONV_STD_LOGIC_VECTOR(21,8) OR row_address = CONV_STD_LOGIC_VECTOR(22,8) OR row_address = CONV_STD_LOGIC_VECTOR(23,8)))AND
NOT(PADDLE1=23 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(21,8) OR row_address = CONV_STD_LOGIC_VECTOR(22,8) OR row_address = CONV_STD_LOGIC_VECTOR(23,8) OR row_address = CONV_STD_LOGIC_VECTOR(24,8)))AND
NOT(PADDLE1=24 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(22,8) OR row_address = CONV_STD_LOGIC_VECTOR(23,8) OR row_address = CONV_STD_LOGIC_VECTOR(24,8) OR row_address = CONV_STD_LOGIC_VECTOR(25,8)))AND
NOT(PADDLE1=25 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(23,8) OR row_address = CONV_STD_LOGIC_VECTOR(24,8) OR row_address = CONV_STD_LOGIC_VECTOR(25,8) OR row_address = CONV_STD_LOGIC_VECTOR(26,8)))AND
NOT(PADDLE1=26 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(24,8) OR row_address = CONV_STD_LOGIC_VECTOR(25,8) OR row_address = CONV_STD_LOGIC_VECTOR(26,8) OR row_address = CONV_STD_LOGIC_VECTOR(27,8)))AND
NOT(PADDLE1=27 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(25,8) OR row_address = CONV_STD_LOGIC_VECTOR(26,8) OR row_address = CONV_STD_LOGIC_VECTOR(27,8) OR row_address = CONV_STD_LOGIC_VECTOR(28,8)))AND
NOT(PADDLE1=28 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(26,8) OR row_address = CONV_STD_LOGIC_VECTOR(27,8) OR row_address = CONV_STD_LOGIC_VECTOR(28,8) OR row_address = CONV_STD_LOGIC_VECTOR(29,8)))AND
NOT(PADDLE1=29 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(27,8) OR row_address = CONV_STD_LOGIC_VECTOR(28,8) OR row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8)))AND
NOT(PADDLE1=30 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(28,8) OR row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)))AND
NOT(PADDLE1=31 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8)))AND
NOT(PADDLE1=32 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)))AND
NOT(PADDLE1=33 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8) OR row_address = CONV_STD_LOGIC_VECTOR(34,8)))AND
NOT(PADDLE1=34 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8) OR row_address = CONV_STD_LOGIC_VECTOR(34,8) OR row_address = CONV_STD_LOGIC_VECTOR(35,8)))AND
NOT(PADDLE1=35 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(33,8) OR row_address = CONV_STD_LOGIC_VECTOR(34,8) OR row_address = CONV_STD_LOGIC_VECTOR(35,8) OR row_address = CONV_STD_LOGIC_VECTOR(36,8)))AND
NOT(PADDLE1=36 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(34,8) OR row_address = CONV_STD_LOGIC_VECTOR(35,8) OR row_address = CONV_STD_LOGIC_VECTOR(36,8) OR row_address = CONV_STD_LOGIC_VECTOR(37,8)))AND
NOT(PADDLE1=37 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(35,8) OR row_address = CONV_STD_LOGIC_VECTOR(36,8) OR row_address = CONV_STD_LOGIC_VECTOR(37,8) OR row_address = CONV_STD_LOGIC_VECTOR(38,8)))AND
NOT(PADDLE1=38 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(36,8) OR row_address = CONV_STD_LOGIC_VECTOR(37,8) OR row_address = CONV_STD_LOGIC_VECTOR(38,8) OR row_address = CONV_STD_LOGIC_VECTOR(39,8)))AND
NOT(PADDLE1=39 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(37,8) OR row_address = CONV_STD_LOGIC_VECTOR(38,8) OR row_address = CONV_STD_LOGIC_VECTOR(39,8) OR row_address = CONV_STD_LOGIC_VECTOR(40,8)))AND
NOT(PADDLE1=40 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(38,8) OR row_address = CONV_STD_LOGIC_VECTOR(39,8) OR row_address = CONV_STD_LOGIC_VECTOR(40,8) OR row_address = CONV_STD_LOGIC_VECTOR(41,8)))AND
NOT(PADDLE1=41 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(39,8) OR row_address = CONV_STD_LOGIC_VECTOR(40,8) OR row_address = CONV_STD_LOGIC_VECTOR(41,8) OR row_address = CONV_STD_LOGIC_VECTOR(42,8)))AND
NOT(PADDLE1=42 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(40,8) OR row_address = CONV_STD_LOGIC_VECTOR(41,8) OR row_address = CONV_STD_LOGIC_VECTOR(42,8) OR row_address = CONV_STD_LOGIC_VECTOR(43,8)))AND
NOT(PADDLE1=43 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(41,8) OR row_address = CONV_STD_LOGIC_VECTOR(42,8) OR row_address = CONV_STD_LOGIC_VECTOR(43,8) OR row_address = CONV_STD_LOGIC_VECTOR(44,8)))AND
NOT(PADDLE1=44 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(42,8) OR row_address = CONV_STD_LOGIC_VECTOR(43,8) OR row_address = CONV_STD_LOGIC_VECTOR(44,8) OR row_address = CONV_STD_LOGIC_VECTOR(45,8)))AND
NOT(PADDLE1=45 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(43,8) OR row_address = CONV_STD_LOGIC_VECTOR(44,8) OR row_address = CONV_STD_LOGIC_VECTOR(45,8) OR row_address = CONV_STD_LOGIC_VECTOR(46,8)))AND
NOT(PADDLE1=46 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(44,8) OR row_address = CONV_STD_LOGIC_VECTOR(45,8) OR row_address = CONV_STD_LOGIC_VECTOR(46,8) OR row_address = CONV_STD_LOGIC_VECTOR(47,8)))AND
NOT(PADDLE1=47 AND col_address = CONV_STD_LOGIC_VECTOR(15,8) AND (row_address = CONV_STD_LOGIC_VECTOR(45,8) OR row_address = CONV_STD_LOGIC_VECTOR(46,8) OR row_address = CONV_STD_LOGIC_VECTOR(47,8) OR row_address = CONV_STD_LOGIC_VECTOR(48,8)))AND
NOT(PADDLE2=17 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(15,8) OR row_address = CONV_STD_LOGIC_VECTOR(16,8) OR row_address = CONV_STD_LOGIC_VECTOR(17,8) OR row_address = CONV_STD_LOGIC_VECTOR(18,8)))AND
NOT(PADDLE2=18 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(16,8) OR row_address = CONV_STD_LOGIC_VECTOR(17,8) OR row_address = CONV_STD_LOGIC_VECTOR(18,8) OR row_address = CONV_STD_LOGIC_VECTOR(19,8)))AND
NOT(PADDLE2=19 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(17,8) OR row_address = CONV_STD_LOGIC_VECTOR(18,8) OR row_address = CONV_STD_LOGIC_VECTOR(19,8) OR row_address = CONV_STD_LOGIC_VECTOR(20,8)))AND
NOT(PADDLE2=20 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(18,8) OR row_address = CONV_STD_LOGIC_VECTOR(19,8) OR row_address = CONV_STD_LOGIC_VECTOR(20,8) OR row_address = CONV_STD_LOGIC_VECTOR(21,8)))AND
NOT(PADDLE2=21 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(19,8) OR row_address = CONV_STD_LOGIC_VECTOR(20,8) OR row_address = CONV_STD_LOGIC_VECTOR(21,8) OR row_address = CONV_STD_LOGIC_VECTOR(22,8)))AND
NOT(PADDLE2=22 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(20,8) OR row_address = CONV_STD_LOGIC_VECTOR(21,8) OR row_address = CONV_STD_LOGIC_VECTOR(22,8) OR row_address = CONV_STD_LOGIC_VECTOR(23,8)))AND
NOT(PADDLE2=23 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(21,8) OR row_address = CONV_STD_LOGIC_VECTOR(22,8) OR row_address = CONV_STD_LOGIC_VECTOR(23,8) OR row_address = CONV_STD_LOGIC_VECTOR(24,8)))AND
NOT(PADDLE2=24 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(22,8) OR row_address = CONV_STD_LOGIC_VECTOR(23,8) OR row_address = CONV_STD_LOGIC_VECTOR(24,8) OR row_address = CONV_STD_LOGIC_VECTOR(25,8)))AND
NOT(PADDLE2=25 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(23,8) OR row_address = CONV_STD_LOGIC_VECTOR(24,8) OR row_address = CONV_STD_LOGIC_VECTOR(25,8) OR row_address = CONV_STD_LOGIC_VECTOR(26,8)))AND
NOT(PADDLE2=26 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(24,8) OR row_address = CONV_STD_LOGIC_VECTOR(25,8) OR row_address = CONV_STD_LOGIC_VECTOR(26,8) OR row_address = CONV_STD_LOGIC_VECTOR(27,8)))AND
NOT(PADDLE2=27 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(25,8) OR row_address = CONV_STD_LOGIC_VECTOR(26,8) OR row_address = CONV_STD_LOGIC_VECTOR(27,8) OR row_address = CONV_STD_LOGIC_VECTOR(28,8)))AND
NOT(PADDLE2=28 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(26,8) OR row_address = CONV_STD_LOGIC_VECTOR(27,8) OR row_address = CONV_STD_LOGIC_VECTOR(28,8) OR row_address = CONV_STD_LOGIC_VECTOR(29,8)))AND
NOT(PADDLE2=29 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(27,8) OR row_address = CONV_STD_LOGIC_VECTOR(28,8) OR row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8)))AND
NOT(PADDLE2=30 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(28,8) OR row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)))AND
NOT(PADDLE2=31 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8)))AND
NOT(PADDLE2=32 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)))AND
NOT(PADDLE2=33 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8) OR row_address = CONV_STD_LOGIC_VECTOR(34,8)))AND
NOT(PADDLE2=34 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8) OR row_address = CONV_STD_LOGIC_VECTOR(34,8) OR row_address = CONV_STD_LOGIC_VECTOR(35,8)))AND
NOT(PADDLE2=35 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(33,8) OR row_address = CONV_STD_LOGIC_VECTOR(34,8) OR row_address = CONV_STD_LOGIC_VECTOR(35,8) OR row_address = CONV_STD_LOGIC_VECTOR(36,8)))AND
NOT(PADDLE2=36 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(34,8) OR row_address = CONV_STD_LOGIC_VECTOR(35,8) OR row_address = CONV_STD_LOGIC_VECTOR(36,8) OR row_address = CONV_STD_LOGIC_VECTOR(37,8)))AND
NOT(PADDLE2=37 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(35,8) OR row_address = CONV_STD_LOGIC_VECTOR(36,8) OR row_address = CONV_STD_LOGIC_VECTOR(37,8) OR row_address = CONV_STD_LOGIC_VECTOR(38,8)))AND
NOT(PADDLE2=38 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(36,8) OR row_address = CONV_STD_LOGIC_VECTOR(37,8) OR row_address = CONV_STD_LOGIC_VECTOR(38,8) OR row_address = CONV_STD_LOGIC_VECTOR(39,8)))AND
NOT(PADDLE2=39 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(37,8) OR row_address = CONV_STD_LOGIC_VECTOR(38,8) OR row_address = CONV_STD_LOGIC_VECTOR(39,8) OR row_address = CONV_STD_LOGIC_VECTOR(40,8)))AND
NOT(PADDLE2=40 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(38,8) OR row_address = CONV_STD_LOGIC_VECTOR(39,8) OR row_address = CONV_STD_LOGIC_VECTOR(40,8) OR row_address = CONV_STD_LOGIC_VECTOR(41,8)))AND
NOT(PADDLE2=41 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(39,8) OR row_address = CONV_STD_LOGIC_VECTOR(40,8) OR row_address = CONV_STD_LOGIC_VECTOR(41,8) OR row_address = CONV_STD_LOGIC_VECTOR(42,8)))AND
NOT(PADDLE2=42 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(40,8) OR row_address = CONV_STD_LOGIC_VECTOR(41,8) OR row_address = CONV_STD_LOGIC_VECTOR(42,8) OR row_address = CONV_STD_LOGIC_VECTOR(43,8)))AND
NOT(PADDLE2=43 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(41,8) OR row_address = CONV_STD_LOGIC_VECTOR(42,8) OR row_address = CONV_STD_LOGIC_VECTOR(43,8) OR row_address = CONV_STD_LOGIC_VECTOR(44,8)))AND
NOT(PADDLE2=44 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(42,8) OR row_address = CONV_STD_LOGIC_VECTOR(43,8) OR row_address = CONV_STD_LOGIC_VECTOR(44,8) OR row_address = CONV_STD_LOGIC_VECTOR(45,8)))AND
NOT(PADDLE2=45 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(43,8) OR row_address = CONV_STD_LOGIC_VECTOR(44,8) OR row_address = CONV_STD_LOGIC_VECTOR(45,8) OR row_address = CONV_STD_LOGIC_VECTOR(46,8)))AND
NOT(PADDLE2=46 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(44,8) OR row_address = CONV_STD_LOGIC_VECTOR(45,8) OR row_address = CONV_STD_LOGIC_VECTOR(46,8) OR row_address = CONV_STD_LOGIC_VECTOR(47,8)))AND
NOT(PADDLE2=47 AND col_address = CONV_STD_LOGIC_VECTOR(49,8) AND (row_address = CONV_STD_LOGIC_VECTOR(45,8) OR row_address = CONV_STD_LOGIC_VECTOR(46,8) OR row_address = CONV_STD_LOGIC_VECTOR(47,8) OR row_address = CONV_STD_LOGIC_VECTOR(48,8)))AND
NOT(row_address = CONV_STD_LOGIC_VECTOR(ROW,8) AND col_address = CONV_STD_LOGIC_VECTOR(COLUMN,8)) AND
NOT(OUT1(6) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(29,8) AND (col_address = CONV_STD_LOGIC_VECTOR(8,8) OR col_address = CONV_STD_LOGIC_VECTOR(9,8) OR col_address = CONV_STD_LOGIC_VECTOR(10,8)))AND
NOT(OUT1(5) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(10,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)))AND
NOT(OUT1(4) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(10,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)))AND
NOT(OUT1(3) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(33,8) AND (col_address = CONV_STD_LOGIC_VECTOR(8,8) OR col_address = CONV_STD_LOGIC_VECTOR(9,8) OR col_address = CONV_STD_LOGIC_VECTOR(10,8)))AND
NOT(OUT1(2) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(8,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)))AND
NOT(OUT1(1) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(8,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)))AND
NOT(OUT1(0) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(31,8) AND (col_address = CONV_STD_LOGIC_VECTOR(8,8) OR col_address = CONV_STD_LOGIC_VECTOR(9,8) OR col_address = CONV_STD_LOGIC_VECTOR(10,8)))AND
NOT(OUT2(6) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(29,8) AND (col_address = CONV_STD_LOGIC_VECTOR(54,8) OR col_address = CONV_STD_LOGIC_VECTOR(55,8) OR col_address = CONV_STD_LOGIC_VECTOR(56,8)))AND
NOT(OUT2(5) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(56,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)))AND
NOT(OUT2(4) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(56,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)))AND
NOT(OUT2(3) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(33,8) AND (col_address = CONV_STD_LOGIC_VECTOR(54,8) OR col_address = CONV_STD_LOGIC_VECTOR(55,8) OR col_address = CONV_STD_LOGIC_VECTOR(56,8)))AND
NOT(OUT2(2) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(54,8) AND (row_address = CONV_STD_LOGIC_VECTOR(31,8) OR row_address = CONV_STD_LOGIC_VECTOR(32,8) OR row_address = CONV_STD_LOGIC_VECTOR(33,8)))AND
NOT(OUT2(1) = '0' AND col_address = CONV_STD_LOGIC_VECTOR(54,8) AND (row_address = CONV_STD_LOGIC_VECTOR(29,8) OR row_address = CONV_STD_LOGIC_VECTOR(30,8) OR row_address = CONV_STD_LOGIC_VECTOR(31,8)))AND
NOT(OUT2(0) = '0' AND row_address = CONV_STD_LOGIC_VECTOR(31,8) AND (col_address = CONV_STD_LOGIC_VECTOR(54,8) OR col_address = CONV_STD_LOGIC_VECTOR(55,8) OR col_address = CONV_STD_LOGIC_VECTOR(56,8)))) THEN
R <= '0';
G <= '0';
B <= '0';
END IF;
END PROCESS RGB;
END NEW1; | mit | 7e00a60a7b679ca44ca052d84742d1fd | 0.685022 | 2.63033 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/bufg/ibuf_tech.vhd | 2 | 1,073 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple input buffer.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ibuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of ibuf_tech is
component ibuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component ibuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = micron180 generate
bufm : ibuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= micron180 generate
bufinf : ibuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
| bsd-2-clause | ec1c9582fdb8bbcebdd9e4a018515f43 | 0.512582 | 3.887681 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/bufg/types_buf.vhd | 2 | 3,587 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_buf package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Technology constants definition.
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' Buffers components.
package types_buf is
--! @brief Clock signals multiplexer.
--! @param[in] tech Technology selector.
--! @param[out] O Output clock signal.
--! @param[in] I1 Input clock signal 1.
--! @param[in] I2 Input clock signal 2.
--! @param[in] S Input signals switcher:
--! 0 = I1; 1 = I2.
component bufgmux_tech is
generic (
tech : integer := 0;
tmode_always_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic);
end component;
--! @brief Input PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered signal.
--! @param[in] i Input unbuffered signal.
component ibuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Output PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal directly connected to the ASIC output pin.
--! @param[in] i Input signal.
component obuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input/Output PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal
--! @param[inout] io Bi-directional signal.
--! @param[in] i Input signal
--! @param[in] t Controlling signal: 0 = in; 1=out
--!
--! Example:
--! @code
--! entity foo is port (
--! io_gpio : inout std_logic
--! )
--! end foo;
--! architecture rtl of foo is
--! signal ob_gpio_direction : std_logic;
--! signal ob_gpio_opins : std_logic;
--! signal ib_gpio_ipins : std_logic;
--! ...
--! begin
--! ob_gpio_direction <= '1';
--!
--! iob : iobuf_tech generic map(kintex7)
--! port map (ib_gpio_ipins, io_gpio, ob_gpio_opins, ob_gpio_direction);
--!
--! reg : process(clk, nrst) begin
--! if rising_edge(clk) then
--! reg1 <= ib_gpio_ipins;
--! ob_gpio_opins <= reg2;
--! end;
--! end process;
--! end;
--! @endcode
component iobuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
--! @brief Gigabit buffer with differential inputs.
--! @param[in] gclk_p Differential clock input.
--! @param[in] gclk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
end;
| bsd-2-clause | 883aba9e86a577c1976f4603da779aaf | 0.553666 | 3.72869 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/misc/nasti_irqctrl.vhd | 2 | 8,666 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Interrupt controller with the AXI4 interface
--! @details This module generates CPU interrupt emitting write message into
--! CSR register 'send_ipi' via HostIO bus interface.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! RISCV specific funcionality.
library rocketlib;
use rocketlib.types_rocket.all;
entity nasti_irqctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type
);
end;
architecture nasti_irqctrl_rtl of nasti_irqctrl is
constant CSR_MIPI : std_logic_vector(11 downto 0) := X"783";
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_IRQCTRL,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type state_type is (idle, wait_grant, wait_resp);
type registers is record
bank_axi : nasti_slave_bank_type;
host_reset : std_logic_vector(1 downto 0);
--! Message multiplexer to form 128 request message of writting into CSR
state : state_type;
--! interrupt signal delay signal to detect interrupt positive edge
irqs_z : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
irqs_zz : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
--! mask irq disabled: 1=disabled; 0=enabled
irqs_mask : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
--! irq pending bit mask
irqs_pending : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
--! interrupt handler address initialized by FW:
isr_table : std_logic_vector(63 downto 0);
--! hold-on generation of interrupt.
irq_lock : std_logic;
--! delayed interrupt
irq_wait_unlock : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
irq_cause_idx : std_logic_vector(31 downto 0);
--! Function trap_entry copies the values of CSRs into these two regs:
dbg_cause : std_logic_vector(63 downto 0);
dbg_epc : std_logic_vector(63 downto 0);
end record;
signal r, rin: registers;
begin
comblogic : process(i_irqs, i_axi, i_host, r)
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable w_generate_ipi : std_logic;
begin
v := r;
w_generate_ipi := '0';
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp(CFG_IRQ_TOTAL-1 downto 0) := r.irqs_mask; --! [RW]: 1=irq disable; 0=enable
when 1 => tmp(CFG_IRQ_TOTAL-1 downto 0) := r.irqs_pending; --! [RO]: Rised interrupts.
when 2 => tmp := (others => '0'); --! [WO]: Clear interrupts mask.
when 3 => tmp := (others => '0'); --! [WO]: Rise interrupts mask.
when 4 => tmp := r.isr_table(31 downto 0); --! [RW]: LSB of the function address
when 5 => tmp := r.isr_table(63 downto 32); --! [RW]: MSB of the function address
when 6 => tmp := r.dbg_cause(31 downto 0); --! [RW]: Cause of the interrupt
when 7 => tmp := r.dbg_cause(63 downto 32); --! [RW]:
when 8 => tmp := r.dbg_epc(31 downto 0); --! [RW]: Instruction pointer
when 9 => tmp := r.dbg_epc(63 downto 32); --! [RW]:
when 10 => tmp(0) := r.irq_lock;
when 11 => tmp := r.irq_cause_idx;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i_axi.w_data(32*(n+1)-1 downto 32*n);
wstrb := i_axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 0 => v.irqs_mask := tmp(CFG_IRQ_TOTAL-1 downto 0);
when 1 => --! Read only
when 2 =>
v.irqs_pending := r.irqs_pending and (not tmp(CFG_IRQ_TOTAL-1 downto 0));
when 3 =>
w_generate_ipi := '1';
v.irqs_pending := (not r.irqs_mask) and tmp(CFG_IRQ_TOTAL-1 downto 0);
when 4 => v.isr_table(31 downto 0) := tmp;
when 5 => v.isr_table(63 downto 32) := tmp;
when 6 => v.dbg_cause(31 downto 0) := tmp;
when 7 => v.dbg_cause(63 downto 32) := tmp;
when 8 => v.dbg_epc(31 downto 0) := tmp;
when 9 => v.dbg_epc(63 downto 32) := tmp;
when 10 => v.irq_lock := tmp(0);
when 11 => v.irq_cause_idx := tmp;
when others =>
end case;
end if;
end loop;
end if;
v.irqs_z := i_irqs;
v.irqs_zz := r.irqs_z;
for n in 0 to CFG_IRQ_TOTAL-1 loop
if (r.irqs_z(n) = '1' and r.irqs_zz(n) = '0') or r.irq_wait_unlock(n) = '1' then
if r.irq_lock = '0' then
v.irq_wait_unlock(n) := '0';
v.irqs_pending(n) := not r.irqs_mask(n);
w_generate_ipi := w_generate_ipi or (not r.irqs_mask(n));
else
v.irq_wait_unlock(n) := '1';
end if;
end if;
end loop;
case r.state is
when idle =>
if w_generate_ipi = '1' then
v.state := wait_grant;
end if;
when wait_grant =>
if (i_host.grant(htif_index) and i_host.csr_req_ready) = '1' then
v.state := wait_resp;
end if;
when wait_resp =>
if i_host.csr_resp_valid = '1' then
v.state := idle;
end if;
when others =>
end case;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
if r.state = wait_grant then
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= CSR_MIPI;
o_host.csr_req_bits_data <= X"0000000000000001";
else
o_host.csr_req_valid <= '0';
o_host.csr_req_bits_rw <= '0';
o_host.csr_req_bits_addr <= (others => '0');
o_host.csr_req_bits_data <= (others => '0');
end if;
-- delayed reset (!!!previously accidentaly was ='1' check with L2)
v.host_reset := r.host_reset(0) & '0';
rin <= v;
end process;
o_cfg <= xconfig;
o_host.reset <= '0';--r.host_reset(1);
o_host.id <= '0';
o_host.csr_resp_ready <= '1';
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
r.host_reset <= (others => '1');
r.state <= idle;
r.irqs_mask <= (others => '1'); -- all interrupts disabled
r.irqs_pending <= (others => '0');
r.irqs_z <= (others => '0');
r.irqs_zz <= (others => '0');
r.isr_table <= (others => '0');
r.irq_lock <= '0';
r.irq_wait_unlock <= (others => '0');
r.irq_cause_idx <= (others => '0');
r.dbg_cause <= (others => '0');
r.dbg_epc <= (others => '0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 95ce5d0cf7af05a09e2d63594a44bbaf | 0.54385 | 3.340786 | false | false | false | false |
freecores/gamepads | gcpad/rtl/vhdl/gcpad_ctrl.vhd | 1 | 7,037 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_ctrl.vhd,v 1.2 2004-10-09 17:04:36 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gcpad_ctrl is
generic (
reset_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
rx_timeout_o : out std_logic;
-- Control Interface ------------------------------------------------------
tx_start_o : out boolean;
tx_finished_i : in boolean;
rx_en_o : out boolean;
rx_done_i : in boolean;
rx_data_ok_i : in boolean
);
end gcpad_ctrl;
use work.gcpad_pack.all;
architecture rtl of gcpad_ctrl is
type state_t is (IDLE,
TX,
RX1_START,
RX1_WAIT,
RX2_START,
RX2_WAIT,
RX3_START,
RX3_WAIT,
RX4_START,
RX4_WAIT);
signal state_s,
state_q : state_t;
signal set_txrx_finished_s : boolean;
signal enable_txrx_finished_s : boolean;
signal txrx_finished_q : std_logic;
signal timeout_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (reset_i, clk_i)
begin
if reset_i = reset_level_g then
state_q <= IDLE;
txrx_finished_q <= '0';
timeout_q <= '1';
elsif clk_i'event and clk_i = '1' then
state_q <= state_s;
-- transmit/receive finished flag
if set_txrx_finished_s then
txrx_finished_q <= '1';
elsif pad_request_i = '1' then
txrx_finished_q <= '0';
end if;
if pad_request_i = '1' then
timeout_q <= '1';
elsif rx_data_ok_i then
timeout_q <= '0';
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process fsm
--
-- Purpose:
-- Models the controlling state machine.
--
fsm: process (state_q,
tx_finished_i,
rx_done_i,
pad_request_i)
begin
rx_en_o <= false;
state_s <= IDLE;
tx_start_o <= false;
set_txrx_finished_s <= false;
enable_txrx_finished_s <= false;
case state_q is
when IDLE =>
-- enable output of txrx_finished flag
-- the flag has to be suppressed while the FSM probes four times
enable_txrx_finished_s <= true;
if pad_request_i = '1' then
state_s <= TX;
tx_start_o <= true;
else
state_s <= IDLE;
end if;
when TX =>
if not tx_finished_i then
state_s <= TX;
else
state_s <= RX1_START;
end if;
when RX1_START =>
rx_en_o <= true;
state_s <= RX1_WAIT;
when RX1_WAIT =>
if rx_done_i then
state_s <= RX2_START;
else
state_s <= RX1_WAIT;
end if;
when RX2_START =>
rx_en_o <= true;
state_s <= RX2_WAIT;
when RX2_WAIT =>
if rx_done_i then
state_s <= RX3_START;
else
state_s <= RX2_WAIT;
end if;
when RX3_START =>
rx_en_o <= true;
state_s <= RX3_WAIT;
when RX3_WAIT =>
if rx_done_i then
state_s <= RX4_START;
else
state_s <= RX3_WAIT;
end if;
when RX4_START =>
rx_en_o <= true;
state_s <= RX4_WAIT;
when RX4_WAIT =>
if rx_done_i then
state_s <= IDLE;
set_txrx_finished_s <= true;
else
state_s <= RX4_WAIT;
end if;
when others =>
null;
end case;
end process fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pad_avail_o <= txrx_finished_q
when enable_txrx_finished_s else
'0';
rx_timeout_o <= timeout_q
when enable_txrx_finished_s else
'0';
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/10/07 21:23:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 21c9d9d132102babd68cd1c95bc84a02 | 0.498366 | 4.246832 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/mem/ram32_inferred.vhd | 2 | 1,361 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief 32-bits RAM implementation based on registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity Ram32_inferred is
generic (
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_inferred is
constant RAM32_ADR_WIDTH : integer := 10+log2(generic_kWords);
type ram_type is array ((2**RAM32_ADR_WIDTH)-1 downto 0) of std_logic_vector (31 downto 0);
signal RAM : ram_type;
signal adr : std_logic_vector(10+log2(generic_kWords)-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if(i_wr_ena='1') then
RAM(conv_integer(i_address)) <= i_data;
end if;
adr <= i_address;
end if;
end process;
o_data <= RAM(conv_integer(adr));
end;
| bsd-2-clause | 223432bae6ec9185e3b5521a33145e9b | 0.56576 | 3.562827 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/CTRL_9P6_50MHZ/CTRL_9P6_50MHZ.vhd | 2 | 44,163 | -- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Vektor
BYTE_NUM : out std_logic_vector (7 downto 0); --Ausgangswariable, Bytenummer
NEXT_BYTE : in std_logic; --Eingangsvariable, naechstes Byte
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
type TYPE_STATE_BYTE_CHECK is
(ST_BC_00, --Zustaende BYTE_CHECK
ST_BC_01,
ST_BC_02);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK
signal n_SV_BYTE_CHECK : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, neuer Wert
signal SV_BYTE_CHECK_M : TYPE_STATE_BYTE_CHECK; --Zustandsvariable BYTE_CHECK, Ausgang Master
signal PARITY_OK : std_logic; --Signal, Parität in Ordnung
signal BYTE_CMPLT : std_logic; -- Signal, Byte vollständig
signal BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit
signal n_BYTE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, neuer Wert
signal BYTE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Bytenummer, 8bit, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
--NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
SV_BYTE_CHECK_M <= ST_BC_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
SV_BYTE_CHECK_M <= n_SV_BYTE_CHECK;
BYTE_COUNT_M <= n_BYTE_COUNT;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
SV_BYTE_CHECK_M <= SV_BYTE_CHECK_M;
BYTE_COUNT_M <= BYTE_COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
SV_BYTE_CHECK <= ST_BC_00;
else
if falling_edge(CLK)
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
SV_BYTE_CHECK <= SV_BYTE_CHECK_M;
BYTE_COUNT <= BYTE_COUNT_M;
end if;
end if;
end process;
BYTE_CHECK_PROC:process (NEXT_BYTE, BYTE_CMPLT, PARITY_OK, SV_BYTE_CHECK, BYTE_COUNT) --Bytes zählen und prüfen
begin
case SV_BYTE_CHECK is
when ST_BC_00 =>
if (NEXT_BYTE = '1')
then
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --kein Zustandsübergang
end if;
when ST_BC_01 =>
if (BYTE_CMPLT = '1')
then
--BC02
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_02; --Zustandsübergang
else
-- BC01
BYTE_OK <= '0';
n_BYTE_COUNT <= BYTE_COUNT; --bleibt gleich
n_SV_BYTE_CHECK <= ST_BC_01; --kein Zustandsübergang
end if;
when ST_BC_02 =>
if (PARITY_OK = '1')
then
--BC03
BYTE_OK <= '1';
n_BYTE_COUNT <= BYTE_COUNT+1; --wird erhoeht
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
else
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end if;
when others =>
-- BC00
BYTE_OK <= '0';
n_BYTE_COUNT <= x"00"; --wird Null (hex)
n_SV_BYTE_CHECK <= ST_BC_00; --Zustandsübergang
end case;
end process;
BYTE_NUM_PROC:process (BYTE_COUNT) --Ausgabe BYTE_NUM aus BYTE_COUNT
begin
BYTE_NUM <= BYTE_COUNT;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_12; --Stoppbit erkannt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
| gpl-2.0 | 960b54de4b009550253fa5443992fd78 | 0.526957 | 2.561659 | false | false | false | false |
jrrk2/greth_library | greth_library/work/config_a7.vhd | 2 | 666 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief FPGA artix7 specific constants definition.
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_JTAGTECH : integer := artix7;
constant CFG_RMII : integer := 1;
end;
| bsd-2-clause | 556d8d6b097de885fbf03e3c3771eadb | 0.555556 | 5.083969 | false | true | false | false |
jrrk2/greth_library | greth_library/techmap/mem/syncram_2p_inferred.vhd | 2 | 2,030 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Synchronous 2-port ram, common clock
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture arch_syncram_2p_inferred of syncram_2p_inferred is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
--! This fuinction just to check with C++ reference model. Can be removed.
impure function init_ram(file_name : in string) return dregtype is
variable temp_mem : dregtype;
begin
for i in 0 to (2**abits - 1) loop
if dbits = 32 then
temp_mem(i) := X"00000000";--X"CCCCCCCC";
else
temp_mem(i) := X"0000";--X"CCCC";
end if;
end loop;
return temp_mem;
end function;
signal rfd : dregtype := init_ram("");
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then
q <= rfd(conv_integer(rdaddress));
end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
| bsd-2-clause | d8c36775925aea96d2471a96a9323e76 | 0.582759 | 3.773234 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/CTRL_TELEGRAM_CHECK/CTRL_TELEGRAM_CHECK.vhd | 4 | 24,503 | -- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"05")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"05"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"05"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FE") --254
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FE"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FE"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0D") --13
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0D"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0D"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"02") --bei Byte 3
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"02"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"02"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC19
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC19
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC19
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral; | gpl-2.0 | 809a94aa99dcb6453668f96268fc30e0 | 0.431417 | 3.366259 | false | false | false | false |
freecores/gamepads | snespad/rtl/vhdl/snespad.vhd | 1 | 7,061 | -------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad.vhd,v 1.2 2004-10-05 18:22:40 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity snespad is
generic (
-- number of pads connected to this core
num_pads_g : natural := 1;
-- active level of reset_i
reset_level_g : natural := 0;
-- active level of the button outputs
button_level_g : natural := 0;
-- number of clk_i periods during 6us
clocks_per_6us_g : natural := 6
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Gamepad Interface ------------------------------------------------------
pad_clk_o : out std_logic;
pad_latch_o : out std_logic;
pad_data_i : in std_logic_vector(num_pads_g-1 downto 0);
-- Buttons Interface ------------------------------------------------------
but_a_o : out std_logic_vector(num_pads_g-1 downto 0);
but_b_o : out std_logic_vector(num_pads_g-1 downto 0);
but_x_o : out std_logic_vector(num_pads_g-1 downto 0);
but_y_o : out std_logic_vector(num_pads_g-1 downto 0);
but_start_o : out std_logic_vector(num_pads_g-1 downto 0);
but_sel_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tl_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tr_o : out std_logic_vector(num_pads_g-1 downto 0);
but_up_o : out std_logic_vector(num_pads_g-1 downto 0);
but_down_o : out std_logic_vector(num_pads_g-1 downto 0);
but_left_o : out std_logic_vector(num_pads_g-1 downto 0);
but_right_o : out std_logic_vector(num_pads_g-1 downto 0)
);
end snespad;
architecture struct of snespad is
component snespad_ctrl
generic (
reset_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_o : out boolean;
shift_buttons_o : out boolean;
save_buttons_o : out boolean;
pad_clk_o : out std_logic;
pad_latch_o : out std_logic
);
end component snespad_ctrl;
component snespad_pad
generic (
reset_level_g : natural := 0;
button_level_g : natural := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_i : in boolean;
shift_buttons_i : in boolean;
save_buttons_i : in boolean;
pad_data_i : in std_logic;
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_start_o : out std_logic;
but_sel_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic
);
end component snespad_pad;
signal clk_en_s : boolean;
signal shift_buttons_s : boolean;
signal save_buttons_s : boolean;
begin
ctrl_b : snespad_ctrl
generic map (
reset_level_g => reset_level_g,
clocks_per_6us_g => clocks_per_6us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_en_o => clk_en_s,
shift_buttons_o => shift_buttons_s,
save_buttons_o => save_buttons_s,
pad_clk_o => pad_clk_o,
pad_latch_o => pad_latch_o
);
pads: for i in 0 to num_pads_g-1 generate
pad_b : snespad_pad
generic map (
reset_level_g => reset_level_g,
button_level_g => button_level_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
clk_en_i => clk_en_s,
shift_buttons_i => shift_buttons_s,
save_buttons_i => save_buttons_s,
pad_data_i => pad_data_i(i),
but_a_o => but_a_o(i),
but_b_o => but_b_o(i),
but_x_o => but_x_o(i),
but_y_o => but_y_o(i),
but_start_o => but_start_o(i),
but_sel_o => but_sel_o(i),
but_tl_o => but_tl_o(i),
but_tr_o => but_tr_o(i),
but_up_o => but_up_o(i),
but_down_o => but_down_o(i),
but_left_o => but_left_o(i),
but_right_o => but_right_o(i)
);
end generate;
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/10/05 17:01:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 42d3a0f837b875b44b989a3b7dbc2894 | 0.544824 | 3.587907 | false | false | false | false |
aysteph3/MiniMIPS_Testing | src/pack_mips.vhd | 1 | 14,955 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation; either version 2 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Enumerations and components declarations --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pack_mips is
-- Type signal on n bits
subtype bus64 is std_logic_vector(63 downto 0);
subtype bus33 is std_logic_vector(32 downto 0);
subtype bus32 is std_logic_vector(31 downto 0);
subtype bus31 is std_logic_vector(30 downto 0);
subtype bus26 is std_logic_vector(25 downto 0);
subtype bus24 is std_logic_vector(23 downto 0);
subtype bus16 is std_logic_vector(15 downto 0);
subtype bus8 is std_logic_vector(7 downto 0);
subtype bus6 is std_logic_vector(5 downto 0);
subtype bus5 is std_logic_vector(4 downto 0);
subtype bus4 is std_logic_vector(3 downto 0);
subtype bus2 is std_logic_vector(1 downto 0);
subtype bus1 is std_logic;
-- Address of a register type
subtype adr_reg_type is std_logic_vector(5 downto 0);
-- Coding of the level of data availability for UR
subtype level_type is std_logic_vector(1 downto 0);
constant LVL_DI : level_type := "11"; -- Data available from the op2 of DI stage
constant LVL_EX : level_type := "10"; -- Data available from the data_ual register of EX stage
constant LVL_MEM : level_type := "01"; -- Data available from the data_ecr register of MEM stage
constant LVL_REG : level_type := "00"; -- Data available only in the register bank
-- Different values of cause exceptions
constant IT_NOEXC : bus32 := X"00000000";
constant IT_ITMAT : bus32 := X"00000001";
constant IT_OVERF : bus32 := X"00000002";
constant IT_ERINS : bus32 := X"00000004";
constant IT_BREAK : bus32 := X"00000008";
constant IT_SCALL : bus32 := X"00000010";
-- Operation type of the coprocessor system (only the low 16 bits are valid)
constant SYS_NOP : bus32 := X"0000_0000";
constant SYS_MASK : bus32 := X"0000_0001";
constant SYS_UNMASK : bus32 := X"0000_0002";
constant SYS_ITRET : bus32 := X"0000_0004";
-- Type for the alu control
subtype alu_ctrl_type is std_logic_vector(27 downto 0);
-- Arithmetical operations
constant OP_ADD : alu_ctrl_type := "1000000000000000000000000000"; -- op1 + op2 sign
constant OP_ADDU : alu_ctrl_type := "0100000000000000000000000000"; -- op1 + op2 non sign
constant OP_SUB : alu_ctrl_type := "0010000000000000000000000000"; -- op1 - op2 sign
constant OP_SUBU : alu_ctrl_type := "0001000000000000000000000000"; -- op1 - op2 non signe
-- Logical operations
constant OP_AND : alu_ctrl_type := "0000100000000000000000000000"; -- et logique
constant OP_OR : alu_ctrl_type := "0000010000000000000000000000"; -- ou logique
constant OP_XOR : alu_ctrl_type := "0000001000000000000000000000"; -- ou exclusif logique
constant OP_NOR : alu_ctrl_type := "0000000100000000000000000000"; -- non ou logique
-- Tests : result to one if ok
constant OP_SLT : alu_ctrl_type := "0000000010000000000000000000"; -- op1 < op2 (sign)
constant OP_SLTU : alu_ctrl_type := "0000000001000000000000000000"; -- op1 < op2 (non sign)
constant OP_EQU : alu_ctrl_type := "0000000000100000000000000000"; -- op1 = op2
constant OP_NEQU : alu_ctrl_type := "0000000000010000000000000000"; -- op1 /= op2
constant OP_SNEG : alu_ctrl_type := "0000000000001000000000000000"; -- op1 < 0
constant OP_SPOS : alu_ctrl_type := "0000000000000100000000000000"; -- op1 > 0
constant OP_LNEG : alu_ctrl_type := "0000000000000010000000000000"; -- op1 <= 0
constant OP_LPOS : alu_ctrl_type := "0000000000000001000000000000"; -- op1 >= 0
-- Multiplications
constant OP_MULT : alu_ctrl_type := "0000000000000000100000000000"; -- op1 * op2 sign (chargement des poids faibles)
constant OP_MULTU : alu_ctrl_type := "0000000000000000010000000000"; -- op1 * op2 non sign (chargement des poids faibles)
-- Shifts
constant OP_SLL : alu_ctrl_type := "0000000000000000001000000000"; -- decallage logique a gauche
constant OP_SRL : alu_ctrl_type := "0000000000000000000100000000"; -- decallage logique a droite
constant OP_SRA : alu_ctrl_type := "0000000000000000000010000000"; -- decallage arithmetique a droite
constant OP_LUI : alu_ctrl_type := "0000000000000000000001000000"; -- met en poids fort la valeur immediate
-- Access to internal registers
constant OP_MFHI : alu_ctrl_type := "0000000000000000000000100000"; -- lecture des poids forts
constant OP_MFLO : alu_ctrl_type := "0000000000000000000000010000"; -- lecture des poids faibles
constant OP_MTHI : alu_ctrl_type := "0000000000000000000000001000"; -- ecriture des poids forts
constant OP_MTLO : alu_ctrl_type := "0000000000000000000000000100"; -- ecriture des poids faibles
-- Operations which do nothing but are useful
constant OP_OUI : alu_ctrl_type := "0000000000000000000000000010"; -- met a 1 le bit de poids faible en sortie
constant OP_OP2 : alu_ctrl_type := "0000000000000000000000000001"; -- recopie l'operande 2 en sortie
-- Starting boot address (after reset)
constant ADR_INIT : bus32 := X"00000000";
constant INS_NOP : bus32 := X"00000000";
-- Internal component of the pipeline stage
component alu
port (
clock : in bus1;
reset : in bus1;
op1 : in bus32;
op2 : in bus32;
ctrl : in alu_ctrl_type;
res : out bus32;
overflow : out bus1
);
end component;
-- Pipeline stage components
component pps_pf
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
bra_cmd : in bus1;
bra_adr : in bus32;
exch_cmd : in bus1;
exch_adr : in bus32;
stop_pf : in bus1;
PF_pc : out bus32
);
end component;
component pps_ei
port (
clock : in bus1;
reset : in bus1;
clear : in bus1;
stop_all : in bus1;
stop_ei : in bus1;
genop : in bus1;
CTE_instr : in bus32;
ETC_adr : out bus32;
PF_pc : in bus32;
EI_instr : out bus32;
EI_adr : out bus32;
EI_it_ok : out bus1
);
end component;
component pps_di
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
bra_detect : out bus1;
adr_reg1 : out adr_reg_type;
adr_reg2 : out adr_reg_type;
use1 : out bus1;
use2 : out bus1;
stop_di : in bus1;
data1 : in bus32;
data2 : in bus32;
EI_adr : in bus32;
EI_instr : in bus32;
EI_it_ok : in bus1;
DI_bra : out bus1;
DI_link : out bus1;
DI_op1 : out bus32;
DI_op2 : out bus32;
DI_code_ual : out alu_ctrl_type;
DI_offset : out bus32;
DI_adr_reg_dest : out adr_reg_type;
DI_ecr_reg : out bus1;
DI_mode : out bus1;
DI_op_mem : out bus1;
DI_r_w : out bus1;
DI_adr : out bus32;
DI_exc_cause : out bus32;
DI_level : out level_type;
DI_it_ok : out bus1
);
end component;
component pps_ex
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
DI_bra : in bus1;
DI_link : in bus1;
DI_op1 : in bus32;
DI_op2 : in bus32;
DI_code_ual : in alu_ctrl_type;
DI_offset : in bus32;
DI_adr_reg_dest : in adr_reg_type;
DI_ecr_reg : in bus1;
DI_mode : in bus1;
DI_op_mem : in bus1;
DI_r_w : in bus1;
DI_adr : in bus32;
DI_exc_cause : in bus32;
DI_level : in level_type;
DI_it_ok : in bus1;
EX_adr : out bus32;
EX_bra_confirm : out bus1;
EX_data_ual : out bus32;
EX_adresse : out bus32;
EX_adr_reg_dest : out adr_reg_type;
EX_ecr_reg : out bus1;
EX_op_mem : out bus1;
EX_r_w : out bus1;
EX_exc_cause : out bus32;
EX_level : out level_type;
EX_it_ok : out bus1
);
end component;
component pps_mem
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
MTC_data : out bus32;
MTC_adr : out bus32;
MTC_r_w : out bus1;
MTC_req : out bus1;
CTM_data : in bus32;
EX_adr : in bus32;
EX_data_ual : in bus32;
EX_adresse : in bus32;
EX_adr_reg_dest : in adr_reg_type;
EX_ecr_reg : in bus1;
EX_op_mem : in bus1;
EX_r_w : in bus1;
EX_exc_cause : in bus32;
EX_level : in level_type;
EX_it_ok : in bus1;
MEM_adr : out bus32;
MEM_adr_reg_dest : out adr_reg_type;
MEM_ecr_reg : out bus1;
MEM_data_ecr : out bus32;
MEM_exc_cause : out bus32;
MEM_level : out level_type;
MEM_it_ok : out bus1
);
end component;
component renvoi
port (
adr1 : in adr_reg_type;
adr2 : in adr_reg_type;
use1 : in bus1;
use2 : in bus1;
data1 : out bus32;
data2 : out bus32;
alea : out bus1;
DI_level : in level_type;
DI_adr : in adr_reg_type;
DI_ecr : in bus1;
DI_data : in bus32;
EX_level : in level_type;
EX_adr : in adr_reg_type;
EX_ecr : in bus1;
EX_data : in bus32;
MEM_level : in level_type;
MEM_adr : in adr_reg_type;
MEM_ecr : in bus1;
MEM_data : in bus32;
interrupt : in bus1;
write_data : out bus32;
write_adr : out bus5;
write_GPR : out bus1;
write_SCP : out bus1;
read_adr1 : out bus5;
read_adr2 : out bus5;
read_data1_GPR : in bus32;
read_data1_SCP : in bus32;
read_data2_GPR : in bus32;
read_data2_SCP : in bus32
);
end component;
component banc
port (
clock : in bus1;
reset : bus1;
reg_src1 : in bus5;
reg_src2 : in bus5;
reg_dest : in bus5;
donnee : in bus32;
cmd_ecr : in bus1;
data_src1 : out bus32;
data_src2 : out bus32
);
end component;
component bus_ctrl
port
(
clock : bus1;
reset : bus1;
interrupt : in std_logic;
adr_from_ei : in bus32;
instr_to_ei : out bus32;
req_from_mem : in bus1;
r_w_from_mem : in bus1;
adr_from_mem : in bus32;
data_from_mem : in bus32;
data_to_mem : out bus32;
req_to_ram : out std_logic;
adr_to_ram : out bus32;
r_w_to_ram : out bus1;
ack_from_ram : in bus1;
data_inout_ram : inout bus32;
stop_all : out bus1
);
end component;
component syscop
port
(
clock : in bus1;
reset : in bus1;
MEM_adr : in bus32;
MEM_exc_cause : in bus32;
MEM_it_ok : in bus1;
it_mat : in bus1;
interrupt : out bus1;
vecteur_it : out bus32;
write_data : in bus32;
write_adr : in bus5;
write_SCP : in bus1;
read_adr1 : in bus5;
read_adr2 : in bus5;
read_data1 : out bus32;
read_data2 : out bus32
);
end component;
component minimips
port (
clock : in bus1;
reset : in bus1;
ram_req : out bus1;
ram_adr : out bus32;
ram_r_w : out bus1;
ram_data : inout bus32;
ram_ack : in bus1;
it_mat : in bus1
);
end component;
end pack_mips;
| gpl-3.0 | ba7d2f61de5b53cfc9bef5db1cb40def | 0.503845 | 3.958444 | false | false | false | false |
siavooshpayandehazad/TTU_ElevatorLab | VHDL_FILES/LIFT_TB.vhd | 1 | 10,389 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY lift_tb IS
END lift_tb;
RCHITECTURE behavior OF lift_tb IS
-- Component Declaration for the Unit Under Test (UUT)
-- fix this component for your design
COMPONENT lift
PORT(
clk : IN std_logic;
sensors : IN std_logic_vector(4 downto 0);
calls : IN std_logic_vector(4 downto 0);
menu : IN std_logic_vector(4 downto 0);
motor : OUT std_logic_vector (1 downto 0);
sleep : OUT std_logic;
ss : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal sensor : std_logic_vector(4 downto 0) := (others => '0');
signal call : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal motor : std_logic_vector(1 downto 0);
signal menu : std_logic_vector(4 downto 0);
signal sleep : std_logic;
signal ss : std_logic_vector(6 downto 0);
-- internal signals and types
signal counter : integer:=0 ;
type state is (f1,f12,f2,f23,f3,f34,f4);
signal current_floor : state;
-- Clock period definitions
constant clk_period : time := 2 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lift PORT MAP (
clk => clk,
sensors => sensor,
calls => call,
menu => menu,
motor => motor,
sleep => sleep,
ss => ss
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
call <= "00000";
menu <= "00000";
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
call <= "00001";
wait for clk_period;
call <= "00000";
wait for clk_period*50;
call <= "00010";
wait for clk_period;
call <= "00000";
wait for clk_period*50;
call <= "00100";
wait for clk_period;
call <= "00000";
wait until sensor(2)= '1';
wait for clk_period*40;
call <= "01000";
wait for clk_period;
call <= "00000";
wait until sensor(3)= '1';
wait for clk_period*40;
call <= "00010";
wait for clk_period;
call <= "00000";
wait until sensor(1)= '1';
wait for clk_period*40;
call <= "00001";
wait for clk_period;
call <= "00000";
wait until sensor(0) = '1';
wait for clk_period*40;
wait;
end process;
-- simple/stupid lift emulator
process (motor(1)) begin
if rising_edge(motor(1)) then
if sleep = '1' then
if motor(0) = '0' then
counter <= counter +1;
elsif motor(0) = '1' then
counter <= counter -1;
else
assert false report "The motor feels lonely and ignored why are you not driving it properly" severity warning;
end if;
end if; -- sleep
end if;-- motor)1)
end process;
-- Assert based on state on lift
process (counter) begin
if counter < 2 and counter >=0 then -- floor 1 ( last chance to stop for 1st floor)
sensor <="00001";
assert false report " 1st Floor "severity note;
elsif counter < 3 and counter >=2 then -- between floor 1 and 2 sensors ( good place to stop either way for 1nd floor)
sensor <="00000";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " BLIND SPOT "severity note;
assert motor(0) /= '0' report " BLIND SPOT "severity note;
end if;
elsif counter < 4 and counter >=3 then -- between floor 1 and 2 sensors ( good place to stop either way for 1nd floor)
sensor <="00011";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " Just cut the bottom sensor for 1st floor, this is a good place to stop "severity note;
assert motor(0) /= '0' report " Just cut the bottom sensor for 2nd floor, keep going up "severity note;
end if;
elsif counter < 9 and counter >=4 then -- floor 2: for up : 1st cut of bottom
-- floor 2: for down: stop
assert motor(0) /= '1' report " 2nd Floor "severity note;
assert motor(0) /= '0' report " floor 2: for up : 1st cut of sensor 1"severity note;
sensor <="00010";
elsif counter < 10 and counter >=9 then -- between the 2 and 3 sensors ( good place to stop either way for 2nd floor)
sensor <="00000";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " BLIND SPOT "severity note;
assert motor(0) /= '0' report " BLIND SPOT "severity note;
end if;
elsif counter < 11 and counter >=10 then -- between the 2 and 3 sensors ( good place to stop either way for 2nd floor)
sensor <="00110";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " Just cut the bottom sensor for 2nd floor, this is a good place to stop "severity note;
assert motor(0) /= '0' report " Just cut the bottom sensor for 3rd floor, keep going up "severity note;
end if;
elsif counter < 16 and counter >=11 then -- floor 3: for up : 1st cut of bottom
-- floor 3: for down: stop
assert motor(0) /= '1' report " 3nd Floor "severity note;
assert motor(0) /= '0' report " floor 3: for up : 1st cut of sensor 2"severity note;
sensor <="00100";
elsif counter < 17 and counter >=16 then -- between the 3 and 4 sensors ( good place to stop either way for 3nd floor)
sensor <="00000";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " BLIND SPOT "severity note;
assert motor(0) /= '0' report " BLIND SPOT "severity note;
end if;
elsif counter < 18 and counter >=17 then -- between the 3 and 4 sensors ( good place to stop either way for 3nd floor)
sensor <="01100";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " Just cut the bottom sensor for 3rd floor, this is a good place to stop "severity note;
assert motor(0) /= '0' report " Just cut the bottom sensor for 4th floor, keep going up "severity note;
end if;
elsif counter < 23 and counter >=18 then -- floor 4: for up : 1st cut of bottom
-- floor 4: for down: stop
assert motor(0) /= '1' report " 4nd Floor "severity note;
assert motor(0) /= '0' report " floor 4: for up : 1st cut of sensor 3"severity note;
sensor <="01000";
elsif counter < 24 and counter >=23 then -- between the 4 and 5 sensors ( good place to stop either way for 4nd floor)
sensor <="00000";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " BLIND SPOT "severity note;
assert motor(0) /= '0' report " BLIND SPOT "severity note;
end if;
elsif counter < 25 and counter >=24 then -- between the 4 and 5 sensors ( good place to stop either way for 4nd floor)
sensor <="11000";
if sleep = '1' then --check if we are awake
assert motor(0) /= '1' report " Just cut the bottom sensor for 4th floor, this is a good place to stop "severity note;
assert motor(0) /= '0' report " Getting too close to the roof, 5th sensor is cut "severity warning;
end if;
elsif counter < 30 and counter >=25 then -- floor 5: for up : 1st cut of bottom
-- floor 5: for down: stop
assert motor(0) /= '1' report " 5nd Floor "severity note;
assert motor(0) /= '0' report " ITS THE 5TH FLOOR ALREADY!!! STOP GOING UP "severity warning;
sensor <="10000";
elsif counter >33 then
assert false report "Hold on mi lord! this is an elevator not a Nazgûl, Elevators cant fly P.s. by now your passenger will be halfway through the roof saying hi to the seagulls " severity error;
elsif counter < 0 then
assert false report "Trying to go below 1st floor P.S. leave the Journey to the center of the earth to Jules Verne" severity error;
end if;
end process;
END; | gpl-2.0 | be4f63f0f980872a9b19f285daa80cb4 | 0.47449 | 4.677172 | false | false | false | false |
jrrk2/greth_library | greth_library/gnsslib/sync/afifo.vhd | 2 | 5,115 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity afifo is
generic (
abits : integer := 4;
dbits : integer := 8
);
port (
i_nrst : in std_logic;
-- Reading port.
i_rclk : in std_logic;
i_rd_ena : in std_logic;
o_data : out std_logic_vector (dbits-1 downto 0);
o_empty : out std_logic;
-- Writing port.
i_wclk : in std_logic;
i_wr_ena : in std_logic;
i_data : in std_logic_vector (dbits-1 downto 0);
o_full : out std_logic
);
end entity;
architecture rtl of afifo is
----/Internal connections & variables------
constant FIFO_DEPTH :integer := 2**abits;
type RAM is array (integer range <>)of std_logic_vector (dbits-1 downto 0);
signal Mem : RAM (0 to FIFO_DEPTH-1);
signal pNextWordToWrite :std_logic_vector (abits-1 downto 0);
signal pNextWordToRead :std_logic_vector (abits-1 downto 0);
signal EqualAddresses :std_logic;
signal NextWriteAddressEn :std_logic;
signal NextReadAddressEn :std_logic;
signal Set_Status :std_logic;
signal Rst_Status :std_logic;
signal Status :std_logic;
signal PresetFull :std_logic;
signal PresetEmpty :std_logic;
signal empty,full :std_logic;
signal r_stat :std_logic;
component GrayCounter is
generic (
generic_width : integer := 4
);
port ( --'Gray' code count output.
i_nrst : in std_logic; -- Count reset.
i_clk : in std_logic; -- Input clock
i_ena : in std_logic; -- Count enable.
o_cnt : out std_logic_vector (generic_width-1 downto 0)
);
end component;
begin
process (i_rclk) begin
if (rising_edge(i_rclk)) then
if (i_rd_ena = '1' and empty = '0') then
o_data <= Mem(conv_integer(pNextWordToRead));
end if;
end if;
end process;
--'Data_in' logic:
process (i_wclk) begin
if (rising_edge(i_wclk)) then
if (i_wr_ena = '1' and full = '0') then
Mem(conv_integer(pNextWordToWrite)) <= i_data;
end if;
end if;
end process;
--Fifo addresses support logic:
NextWriteAddressEn <= i_wr_ena and (not full);
NextReadAddressEn <= i_rd_ena and (not empty);
--Addreses (Gray counters) logic:
GrayCounter_pWr : GrayCounter
generic map (
generic_width => abits
) port map (
i_nrst => i_nrst,
i_clk => i_wclk,
i_ena => NextWriteAddressEn,
o_cnt => pNextWordToWrite
);
GrayCounter_pRd : GrayCounter
generic map (
generic_width => abits
) port map (
i_nrst => i_nrst,
i_clk => i_rclk,
i_ena => NextReadAddressEn,
o_cnt => pNextWordToRead
);
--'EqualAddresses' logic:
EqualAddresses <= '1' when (pNextWordToWrite = pNextWordToRead) else '0';
--'Quadrant selectors' logic:
process (pNextWordToWrite, pNextWordToRead)
variable set_status_bit0 :std_logic;
variable set_status_bit1 :std_logic;
variable rst_status_bit0 :std_logic;
variable rst_status_bit1 :std_logic;
begin
set_status_bit0 := pNextWordToWrite(abits-2) xnor pNextWordToRead(abits-1);
set_status_bit1 := pNextWordToWrite(abits-1) xor pNextWordToRead(abits-2);
Set_Status <= set_status_bit0 and set_status_bit1;
rst_status_bit0 := pNextWordToWrite(abits-2) xor pNextWordToRead(abits-1);
rst_status_bit1 := pNextWordToWrite(abits-1) xnor pNextWordToRead(abits-2);
Rst_Status <= rst_status_bit0 and rst_status_bit1;
end process;
--'Status' latch logic:
r_stat <= Rst_Status or (not i_nrst);
process (i_rclk, Set_Status, r_stat) begin--D Latch w/ Asynchronous Clear & Preset.
if r_stat = '1' then
Status <= '0';
elsif (Set_Status = '1') then
Status <= '1'; --Going 'Full'.
elsif rising_edge(i_rclk) then
Status <= Status;
end if;
end process;
--'Full_out' logic for the writing port:
PresetFull <= Status and EqualAddresses; --'Full' Fifo.
process (i_wclk, PresetFull) begin --D Flip-Flop w/ Asynchronous Preset.
if (PresetFull = '1') then
full <= '1';
elsif (rising_edge(i_wclk)) then
full <= '0';
end if;
end process;
o_full <= full;
--'Empty_out' logic for the reading port:
PresetEmpty <= not Status and EqualAddresses; --'Empty' Fifo.
process (i_rclk, PresetEmpty) begin --D Flip-Flop w/ Asynchronous Preset.
if (PresetEmpty = '1') then
empty <= '1';
elsif (rising_edge(i_rclk)) then
empty <= '0';
end if;
end process;
o_empty <= empty;
end architecture;
| bsd-2-clause | 6bd9752766ec70c4503c6199f30a50b7 | 0.554643 | 3.733577 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/PROFIBUS_MONITOR/CTRL_TELEGRAM_FILTER_SD1_VHDL.vhd | 4 | 6,433 | -- CTRL_TELEGRAM_FILTER_SD1
-- Profibus Telegramtyp SD1 ermitteln und Bytes ausgeben, alternativ alle Bytes durchlassen
-- Ersteller: Martin Harndt
-- Erstellt: 23.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_FILTER_SD1_VHDL is
Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
FILTER_ON : in std_logic; --Eingangsvariable, Filter einschalten
PARITY_OK : in std_logic; --Eingangsvariable, Parität i.O.
FILTER_BYTE_OUT : out std_logic_vector (7 downto 0);--Ausgangsvariable, gefilterte Telegramme
SEND_OUT : out std_logic; --Ausgangsvariable, Byte senden
T_CMPLT: out std_logic; --Ausgangsvariable, Telegramm komplett
DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_FILTER_SD1_VHDL;
architecture Behavioral of CTRL_TELEGRAM_FILTER_SD1_VHDL is
type TYPE_STATE is
(ST_FI_00, --Zustaende TELEGRAM_CHECK
ST_FI_01,
ST_FI_02,
ST_FI_03);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (11 downto 0); -- Vektor, Zaehler, 8bit
signal n_COUNT : std_logic_vector (11 downto 0); -- Vektor, Zaehler, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (11 downto 0); -- Vektor, Zaehler, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
--signal not_CLK : std_logic; --negierte Taktvariable
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_FI_00;
COUNT_M <= X"000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_FI_00;
COUNT <= X"000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_FILTER_PROC:process (FILTER_ON, PARITY_OK, BYTE_IN, SV, COUNT) --Telegramm SD1 Filtern und ausgeben
begin
case SV is
when ST_FI_00 =>
if (FILTER_ON = '1')
then
--FI02
FILTER_BYTE_OUT <= X"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= COUNT;
n_SV <= ST_FI_01;
else
--FI01
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= X"000";
n_SV <= ST_FI_00;
end if;
when ST_FI_01 =>
if (PARITY_OK = '1' AND BYTE_IN = X"68") --SD2
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_02;
else
--FI00
FILTER_BYTE_OUT <= X"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= X"000";
n_SV <= ST_FI_00;
end if;
when ST_FI_02 =>
if (PARITY_OK = '1')
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_03;
else
--FI02
FILTER_BYTE_OUT <= X"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= COUNT;
n_SV <= ST_FI_02;
end if;
when ST_FI_03 =>
if (COUNT = X"126" OR BYTE_IN = X"16")
then
--FI04
FILTER_BYTE_OUT <= X"00";
T_CMPLT <= '1';
SEND_OUT <= '0';
n_COUNT <= X"000";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= X"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= COUNT;
n_SV <= ST_FI_02;
end if;
when others =>
-- FI00
FILTER_BYTE_OUT <= X"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"000";
n_SV <= ST_FI_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--anktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT ='0') --Original
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
else --Telegrammzaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
end if;
end process;
end Behavioral;
| gpl-2.0 | d7694110345f4a409df98b629e833256 | 0.56319 | 2.964516 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/pll/SysPLL_tech.vhd | 2 | 2,894 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the SysPLL_tech entity
--! @details This module file be included in all projects.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
--! "Virtual" components declarations library.
library techmap;
use techmap.gencomp.all;
use techmap.types_pll.all;
use techmap.types_buf.all;
--! @brief SysPLL_tech entity declaration ("Virtual" PLL).
--! @details This module instantiates the certain PLL implementation
--! depending generic technology argument.
entity SysPLL_tech is
generic (
tech : integer range 0 to NTECH := 0; --! PLL implementation selector
tmode_always_ena : boolean := false
);
port
(
--! Reset value. Active high.
i_reset : in std_logic;
--! Differential clock input positive
i_clkp : in std_logic;
--! Differential clock input negative
i_clkn : in std_logic;
--! System Bus clock 100MHz/40MHz (Virtex6/Spartan6)
o_clk_bus : out std_logic;
--! PLL locked status.
o_locked : out std_logic;
--rmii clocks
o_clk_50 : out std_logic;
o_clk_50_quad : out std_logic
);
end SysPLL_tech;
--! SysPLL_tech architecture declaration.
architecture rtl of SysPLL_tech is
--! Clock bus (default 60 MHz).
signal pll_clk_bus : std_logic;
--! Clock bus Fsys / 4 (unbuffered).
signal adc_clk_unbuf : std_logic;
begin
xv6 : if tech = virtex6 generate
pll0 : SysPLL_v6 port map (i_clkp, i_clkn, pll_clk_bus, adc_clk_unbuf, i_reset, o_locked);
end generate;
xv7 : if tech = kintex7 generate
pll0 : SysPLL_k7 port map (i_clkp, i_clkn, pll_clk_bus, adc_clk_unbuf, i_reset, o_locked);
end generate;
xa7 : if tech = artix7 generate
pll0 : SysPLL_a7
port map (
-- Clock in ports
clk_in1 => i_clkp,
-- Clock out ports
clk_out1 => pll_clk_bus,
clk_out2 => adc_clk_unbuf,
clk_out3 => o_clk_50,
clk_out4 => o_clk_50_quad,
-- Status and control signals
reset => i_reset,
locked => o_locked
);
end generate;
inf : if tech = inferred generate
pll0 : SysPLL_inferred port map (i_clkp, i_clkn, pll_clk_bus, adc_clk_unbuf, i_reset, o_locked);
end generate;
m180 : if tech = micron180 generate
pll0 : SysPLL_micron180 port map (i_clkp, i_clkn, pll_clk_bus, adc_clk_unbuf, i_reset, o_locked);
end generate;
o_clk_bus <= pll_clk_bus;
end;
| bsd-2-clause | 639b7a8e0f2c8ecc51e0025bba40a197 | 0.588459 | 3.677255 | false | false | false | false |
akshayp/college-projects | vhdl/mips/MIPS.vhd | 1 | 11,160 | -- Top Level Structural Model for MIPS Processor Core
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MIPS IS
PORT( reset, clock : IN STD_LOGIC;
-- Output important signals to pins for easy display in Simulator
PC : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
Stall_out : OUT STD_LOGIC;
Address_V_out : OUT STD_LOGIC;
Data_Ready_out : OUT STD_LOGIC;
Memory_Addr_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Mem_Inst_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
D_ALU_result_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_result_out, read_data_1_out, read_data_2_out, write_data_out,
Instruction_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Branch_out, Zero_out, Memwrite_out,
D_RegisterWriteOut : OUT STD_LOGIC;
DD_RegisterWriteOut : OUT STD_LOGIC;
Regwrite_out : OUT STD_LOGIC ;
WriteRegOut : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
D_WriteRegOut : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
Add_Result_Out :OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
DD_WriteRegOut : OUT STD_LOGIC_VECTOR (4 DOWNTO 0));
END MIPS;
ARCHITECTURE structure OF MIPS IS
COMPONENT Ifetch
PORT( Instruction : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
Add_result : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Branch : IN STD_LOGIC;
Zero : IN STD_LOGIC;
PC_out : OUT STD_LOGIC_VECTOR( 9 DOWNTO 0 );
clock,reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT Idecode
PORT( read_data_1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2_ex : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2_mem : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite, MemtoReg : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
PC_plus_4 : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 );
RegWrite_mem : IN STD_LOGIC;
RegWrite_ex : IN STD_LOGIC;
Zero : OUT STD_LOGIC;
Add_Result : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_register_address_mem : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_wb : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_ex : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
Sign_extend : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_mem : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_wb : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_ex : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_register_1_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
read_register_2_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
D_read_register_1_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
D_read_register_2_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
D_write_register_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
DD_write_register_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_data_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT control
PORT( Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
RegDst : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC;
D_RegWrite_out : OUT STD_LOGIC;
DD_RegWrite_out : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemWrite : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
ALUop : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT Execute
PORT( Read_data_1 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Read_data_2 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Sign_Extend : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 );
ALUOp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 );
ALUSrc : IN STD_LOGIC;
ALU_Result_mem : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_wb : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_ex : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC_plus_4 : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 );
read_register_1_address : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
read_register_2_address : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite : IN STD_LOGIC;
RegWrite_mem : IN STD_LOGIC;
clock, reset : IN STD_LOGIC );
END COMPONENT;
COMPONENT dmemory
PORT( read_data : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
MemRead, Memwrite : IN STD_LOGIC;
Clock,reset : IN STD_LOGIC );
END COMPONENT;
-- declare signals used to connect VHDL components
SIGNAL PC_plus_4 : STD_LOGIC_VECTOR( 9 DOWNTO 0 );
SIGNAL read_data_1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL read_data_2_ex : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL read_data_2_mem : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Sign_Extend : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Add_result : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL ALU_result_mem : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL ALU_result_wb : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL ALU_result_ex : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL read_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL ALUSrc : STD_LOGIC;
SIGNAL Branch : STD_LOGIC;
SIGNAL RegDst : STD_LOGIC;
SIGNAL Regwrite : STD_LOGIC;
SIGNAL Regwrite_mem : STD_LOGIC;
SIGNAL Regwrite_ex : STD_LOGIC;
SIGNAL Zero : STD_LOGIC;
SIGNAL MemWrite : STD_LOGIC;
SIGNAL MemtoReg : STD_LOGIC;
SIGNAL MemRead : STD_LOGIC;
SIGNAL ALUop : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
SIGNAL Instruction : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Stall : STD_LOGIC;
SIGNAL Address_V : STD_LOGIC;
SIGNAL Data_Ready : STD_LOGIC;
SIGNAL Memory_Addr : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL Mem_Inst : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL read_register_1_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL read_register_2_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL D_read_register_1_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL D_read_register_2_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address_ex : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address_mem : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address_wb : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
BEGIN
-- copy important signals to output pins for easy
-- display in Simulator
Instruction_out <= Instruction;
ALU_result_out <= ALU_result_mem;
D_ALU_result_out <= ALU_result_wb;
read_data_1_out <= read_data_1;
read_data_2_out <= read_data_2_ex;
write_data_out <= read_data WHEN MemtoReg = '1' ELSE ALU_result_wb;
Branch_out <= Branch;
Zero_out <= Zero;
RegWrite_out <= RegWrite;
MemWrite_out <= MemWrite;
Stall_out <= Stall;
Address_V_out <= Address_V;
Data_Ready_out <= Data_Ready;
Memory_Addr_out <= Memory_Addr;
Mem_Inst_out <= Mem_Inst;
D_RegisterWriteOut <= RegWrite_mem;
DD_RegisterWriteOut <= RegWrite_ex;
WriteRegOut <= write_register_address_wb;
D_WriteRegOut <= write_register_address_mem;
DD_WriteRegOut <= write_register_address_ex;
Add_result_out <= Add_Result;
-- connect the 5 MIPS components
IFE : Ifetch
PORT MAP ( Instruction => Instruction,
PC_plus_4_out => PC_plus_4,
Add_result => Add_result,
Branch => Branch,
Zero => Zero,
PC_out => PC,
clock => clock,
reset => reset );
ID : Idecode
PORT MAP ( read_data_1 => read_data_1,
read_data_2_ex => read_data_2_ex,
read_data_2_mem => read_data_2_mem,
PC_plus_4 => PC_plus_4,
Instruction => Instruction,
read_data => read_data,
RegWrite => RegWrite,
RegWrite_mem => RegWrite_mem,
RegWrite_ex => RegWrite_ex,
MemtoReg => MemtoReg,
RegDst => RegDst,
Zero => Zero,
Sign_extend => Sign_extend,
ALU_result_mem => ALU_result_mem,
ALU_result_wb => ALU_result_wb,
ALU_result_ex => ALU_result_ex,
Add_result => Add_result,
write_register_address_ex => write_register_address_ex,
write_register_address_mem => write_register_address_mem,
write_register_address_wb => write_register_address_wb,
read_register_1_address_out => read_register_1_address,
read_register_2_address_out => read_register_2_address,
D_read_register_1_address_out => D_read_register_1_address,
D_read_register_2_address_out => D_read_register_2_address,
DD_write_register_address_out => write_register_address_ex,
D_write_register_address_out => write_register_address_mem,
write_register_address_out => write_register_address_wb,
write_data_out => write_data,
clock => clock,
reset => reset );
CTL: control
PORT MAP ( Opcode => Instruction( 31 DOWNTO 26 ),
RegDst => RegDst,
ALUSrc => ALUSrc,
MemtoReg => MemtoReg,
RegWrite => RegWrite,
D_RegWrite_out => RegWrite_mem,
DD_RegWrite_out => RegWrite_ex,
MemRead => MemRead,
MemWrite => MemWrite,
Branch => Branch,
ALUop => ALUop,
clock => clock,
reset => reset );
EXE: Execute
PORT MAP ( Read_data_1 => read_data_1,
Read_data_2 => read_data_2_ex,
Sign_extend => Sign_extend,
Function_opcode => Sign_extend( 5 DOWNTO 0 ),
ALUOp => ALUop,
ALUSrc => ALUSrc,
ALU_Result_mem => ALU_Result_mem,
ALU_Result_wb => ALU_Result_wb,
ALU_Result_ex => ALU_Result_ex,
PC_plus_4 => PC_plus_4,
read_register_1_address => read_register_1_address,
read_register_2_address => read_register_2_address,
write_data => write_data,
RegWrite => RegWrite,
RegWrite_mem => RegWrite_mem,
Clock => clock,
Reset => reset );
MEM: dmemory
PORT MAP ( read_data => read_data,
address => ALU_Result_mem (7 DOWNTO 0),
write_data => read_data_2_mem,
MemRead => MemRead,
Memwrite => MemWrite,
clock => clock,
reset => reset );
END structure;
| mit | 6f18b8c3b56c6a9b75055b37de3a2f1b | 0.586201 | 3.053352 | false | false | false | false |
jrrk2/greth_library | greth_library/work/rocket_soc.vhd | 2 | 13,773 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
eth_crsdv : in std_ulogic;
eth_rxerr : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
eth_refclk : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
--! From modules-to-tile requests
signal htifo : host_out_vector;
--! Selected request with the highest priority.
signal htifo_mux : host_out_type;
--! tile-to-module response.
signal htifi : host_in_type;
--! response with the 'grant' signal marking the exact recipient.
signal htifi_grant : host_in_type;
signal gnss_i : gns_in_type;
signal gnss_o : gns_out_type;
signal fse_i : fse_in_type;
signal fse_o : fse_out_type;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked,
o_clk_50_quad => eth_refclk,
o_clk_50 => eth_i.rmii_clk
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
--! @brief HostIO controller.
htif0 : htifctrl port map (
clk => wClkBus,
nrst => wNReset,
srcsi => htifo,
srcso => htifo_mux,
htifii => htifi,
htifio => htifi_grant
);
mst_cfg(CFG_NASTI_MASTER_CACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_CACHED) <= nasti_master_out_none;
mst_cfg(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;
dsu_ena : if CFG_DSU_ENABLE generate
------------------------------------
--! @brief Debug Support Unit with access to the CSRs
--! @details Map address:
--! 0x80080000..0x8009ffff (128 KB total)
dsu0 : nasti_dsu generic map (
xindex => CFG_NASTI_SLAVE_DSU,
xaddr => 16#80080#,
xmask => 16#fffe0#,
htif_index => CFG_HTIF_SRC_DSU
) port map (
clk => wClkBus,
nrst => wNReset,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_DSU),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_DSU),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_DSU),
o_soft_reset => soft_rst
);
end generate;
dsu_dis : if not CFG_DSU_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;
htifo(CFG_HTIF_SRC_DSU) <= host_out_none;
end generate;
axiso(CFG_NASTI_SLAVE_BOOTROM) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_BOOTROM) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_ROMIMAGE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ROMIMAGE) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_SRAM) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_SRAM) <= nasti_slave_config_none;
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip(3 downto 1) & (ib_dip(0) xor eth_rxerr),
o_led => o_led
);
------------------------------------
uart1i.cts <= uart1o.rts;
uart1i.rd <= i_uart1_rd;
--! @brief UART Controller with the AXI4 interface.
--! @details Map address:
--! 0x80001000..0x80001fff (4 KB total)
uart1 : nasti_uart generic map (
xindex => CFG_NASTI_SLAVE_UART1,
xaddr => 16#80001#,
xmask => 16#FFFFF#,
fifosz => 16
) port map (
nrst => wNReset,
clk => wClkbus,
cfg => slv_cfg(CFG_NASTI_SLAVE_UART1),
i_uart => uart1i,
o_uart => uart1o,
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_UART1),
o_irq => irq_pins(CFG_IRQ_UART1)
);
o_uart1_td <= uart1o.td;
------------------------------------
--! @brief Interrupt controller with the AXI4 interface.
--! @details Map address:
--! 0x80002000..0x80002fff (4 KB total)
irq0 : nasti_irqctrl generic map (
xindex => CFG_NASTI_SLAVE_IRQCTRL,
xaddr => 16#80002#,
xmask => 16#FFFFF#,
htif_index => CFG_HTIF_SRC_IRQCTRL
) port map (
clk => wClkBus,
nrst => bus_nrst,
i_irqs => irq_pins,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_IRQCTRL),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_IRQCTRL),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_IRQCTRL)
);
axiso(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
axiso(CFG_NASTI_SLAVE_RFCTRL) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_RFCTRL) <= nasti_slave_config_none;
slv_cfg(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_out_none;
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth0_ena : if CFG_ETHERNET_ENABLE generate
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_er <= eth_rxerr;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= eth_crsdv;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 50, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518,
rmii => CFG_RMII
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
end generate;
--! Ethernet disabled
eth0_dis : if not CFG_ETHERNET_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_out_none;
mst_cfg(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_out_none;
irq_pins(CFG_IRQ_ETHMAC) <= '0';
eth_o <= eth_out_none;
end generate;
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
--! @brief Plug'n'Play controller of the current configuration with the
--! AXI4 interface.
--! @details Map address:
--! 0xfffff000..0xffffffff (4 KB total)
pnp0 : nasti_pnp generic map (
xindex => CFG_NASTI_SLAVE_PNP,
xaddr => 16#fffff#,
xmask => 16#fffff#,
tech => CFG_MEMTECH
) port map (
sys_clk => wClkBus,
adc_clk => wClkAdc,
nrst => wNReset,
mstcfg => mst_cfg,
slvcfg => slv_cfg,
cfg => slv_cfg(CFG_NASTI_SLAVE_PNP),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_PNP)
);
end arch_rocket_soc;
| bsd-2-clause | 9ea6477759566b3e51dc00977d0d4741 | 0.599942 | 3.320395 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_BYTE_CHECK/F_DIV_50000000_SRC.vhd | 2 | 932 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity F_DIV50000000 is
Port ( F_IN : in std_logic; -- Eingangsfrequenz
F_OUT : out std_logic); -- Ausgangsfrequen
-- FOUT ändert sich mit der
-- 0/1-Flanke von F_IN
end F_DIV50000000;
architecture Behavioral of F_DIV50000000 is
signal COUNTER : integer;
-- Maximalwert: Teilungsfaktor - 1
begin
process (F_IN,COUNTER )
begin
if (F_IN'event and F_IN = '1')
then -- am Eingang des Frequenzteilers ist eine 0/1-Flanke aufgetreten
if COUNTER = 0
then COUNTER <= 49999999; -- Teilungsfaktor -1
else COUNTER <= COUNTER -1;
end if;
end if;
if COUNTER < 25000000 -- Teilungsfaktor / 2 (abgerundet)
then F_OUT <= '0';
else F_OUT <= '1';
end if;
end process;
end Behavioral;
| gpl-2.0 | 1cbd53c7e82afad689359ecc11b54df2 | 0.600858 | 3.117057 | false | false | false | false |
AmitThakur/vhdl | priority_encoder/priority_encoder.vhd | 1 | 593 | -- Priority Encoder: Behavioural
-- Amit Kumar Thakur 8EC13
-- https://github.com/AmitThakur/vhdl.git
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity priority_encoder is
Port ( w : in std_logic_vector(3 downto 0);
y : out std_logic_vector(1 downto 0);
z : out std_logic);
end priority_encoder;
architecture Behavioral of priority_encoder is
begin
y <= "11" when w(3) = '1' else
"10" when w(2) = '1' else
"01" when w(1) = '1' else
"00";
z <= '0' when w = "0000" else '1';
end Behavioral;
| mit | 63b4eeec9bbc9e0961368d211c75a305 | 0.647555 | 2.837321 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_19_12_2012/PROFI_MON_25MHZ_CTRL_SRAM/CTRL_9P6_50MHZ.vhd | 6 | 44,801 | -- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 15.11.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
STOP : in std_logic; --Eingangsvariable, Stopp nach einem Byte
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
CTRL_STOP : out std_logic; --Ausgangsvariable, Stopp anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Vektor
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, STOP, ERROR_QUIT, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (STOP = '1')
then
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; -- Stopp nach einem Byte
else --STOP_S = '0'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_STOP <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
| gpl-2.0 | a41f06e9af3f59d5a52756c59612a843 | 0.514029 | 2.543488 | false | false | false | false |
freecores/gamepads | gcpad/rtl/vhdl/gcpad_rx.vhd | 1 | 11,782 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_rx.vhd,v 1.5 2004-10-09 17:05:12 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gcpad_pack.buttons_t;
entity gcpad_rx is
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Control Interface ------------------------------------------------------
rx_en_i : in boolean;
rx_done_o : out boolean;
rx_data_ok_o : out boolean;
rx_size_i : in std_logic_vector(3 downto 0);
-- Gamepad Interface ------------------------------------------------------
pad_data_i : in std_logic;
-- Data Interface ---------------------------------------------------------
rx_data_o : out buttons_t
);
end gcpad_rx;
library ieee;
use ieee.numeric_std.all;
use work.gcpad_pack.all;
architecture rtl of gcpad_rx is
component gcpad_sampler
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
wrap_sample_i : in boolean;
sync_sample_i : in boolean;
sample_underflow_o : out boolean;
pad_data_i : in std_logic;
pad_data_o : out std_logic;
sample_o : out std_logic
);
end component;
type state_t is (IDLE,
DETECT_TIMEOUT,
WAIT_FOR_1,
WAIT_FOR_0,
FINISHED);
signal state_s,
state_q : state_t;
signal buttons_q,
shift_buttons_q : buttons_t;
signal save_buttons_s : boolean;
signal shift_buttons_s : boolean;
signal sync_sample_s : boolean;
signal wrap_sample_s : boolean;
-- timeout counter counts three sample undeflows
constant cnt_timeout_high_c : natural := 3;
subtype cnt_timeout_t is natural range 0 to cnt_timeout_high_c;
signal cnt_timeout_q : cnt_timeout_t;
signal timeout_q : boolean;
signal sync_timeout_s : boolean;
subtype num_buttons_read_t is unsigned(6 downto 0);
signal num_buttons_read_q : num_buttons_read_t;
signal all_buttons_read_s : boolean;
signal reset_num_buttons_s : boolean;
signal pad_data_s : std_logic;
signal sample_s : std_logic;
signal sample_underflow_s : boolean;
signal rx_done_s,
rx_done_q : boolean;
begin
sampler_b : gcpad_sampler
generic map (
reset_level_g => reset_level_g,
clocks_per_1us_g => clocks_per_1us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
wrap_sample_i => wrap_sample_s,
sync_sample_i => sync_sample_s,
sample_underflow_o => sample_underflow_s,
pad_data_i => pad_data_i,
pad_data_o => pad_data_s,
sample_o => sample_s
);
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements of this module.
--
seq: process (reset_i, clk_i)
variable size_v : std_logic_vector(num_buttons_read_t'range);
begin
if reset_i = reset_level_g then
buttons_q <= (others => '0');
shift_buttons_q <= (others => '0');
state_q <= IDLE;
cnt_timeout_q <= cnt_timeout_high_c;
timeout_q <= false;
num_buttons_read_q <= (others => '0');
rx_done_q <= false;
elsif clk_i'event and clk_i = '1' then
state_q <= state_s;
rx_done_q <= rx_done_s;
-- timeout counter
if sync_timeout_s then
-- explicit preload
cnt_timeout_q <= cnt_timeout_high_c;
timeout_q <= false;
elsif cnt_timeout_q = 0 then
-- wrap-around
cnt_timeout_q <= cnt_timeout_high_c;
timeout_q <= true;
elsif sample_underflow_s then
-- decrement counter when sampler wraps around
cnt_timeout_q <= cnt_timeout_q - 1;
end if;
-- count remaining number of buttons to read
if shift_buttons_s then
shift_buttons_q(buttons_t'high downto 1) <= shift_buttons_q(buttons_t'high-1 downto 0);
if sample_s = '1' then
shift_buttons_q(0) <= '1';
else
shift_buttons_q(0) <= '0';
end if;
end if;
if reset_num_buttons_s then
-- explicit preload
size_v(num_buttons_read_t'high downto 3) := rx_size_i;
size_v(2 downto 0) := (others => '0');
num_buttons_read_q <= unsigned(size_v);
elsif shift_buttons_s then
-- decrement counter when a button bit has been read
if not all_buttons_read_s then
num_buttons_read_q <= num_buttons_read_q - 1;
end if;
end if;
-- the buttons
if save_buttons_s then
buttons_q <= shift_buttons_q;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-- indicates that all buttons have been read
all_buttons_read_s <= num_buttons_read_q = 0;
-----------------------------------------------------------------------------
-- Process fsm
--
-- Purpose:
-- Models the controlling state machine.
--
fsm: process (state_q,
rx_en_i,
pad_data_s,
wrap_sample_s,
all_buttons_read_s,
sample_underflow_s,
timeout_q)
begin
sync_sample_s <= false;
sync_timeout_s <= false;
state_s <= IDLE;
shift_buttons_s <= false;
save_buttons_s <= false;
rx_done_s <= false;
reset_num_buttons_s <= false;
wrap_sample_s <= false;
case state_q is
-- IDLE -----------------------------------------------------------------
-- The idle state.
when IDLE =>
if rx_en_i then
state_s <= DETECT_TIMEOUT;
else
-- keep counters synchronized when no reception is running
sync_sample_s <= true;
sync_timeout_s <= true;
reset_num_buttons_s <= true;
state_s <= IDLE;
end if;
when DETECT_TIMEOUT =>
state_s <= DETECT_TIMEOUT;
if pad_data_s = '0' then
sync_sample_s <= true;
state_s <= WAIT_FOR_1;
else
-- wait for timeout
wrap_sample_s <= true;
if timeout_q then
rx_done_s <= true;
state_s <= IDLE;
end if;
end if;
-- WAIT_FOR_1 -----------------------------------------------------------
-- Sample counter has expired and a 0 bit has been detected.
-- We must now wait for pad_data_s to become 1.
-- Or abort upon timeout.
when WAIT_FOR_1 =>
if pad_data_s = '0' then
if not sample_underflow_s then
state_s <= WAIT_FOR_1;
else
-- timeout while reading buttons!
rx_done_s <= true;
state_s <= IDLE;
end if;
else
state_s <= WAIT_FOR_0;
end if;
-- WAIT_FOR_0 -----------------------------------------------------------
-- pad_data_s is at 1 level now and no timeout occured so far.
-- We wait for the next 0 level on pad_data_s or abort upon timeout.
when WAIT_FOR_0 =>
-- wait for falling edge of pad data
if pad_data_s = '0' then
sync_sample_s <= true;
-- loop again in any case
state_s <= WAIT_FOR_1;
if not all_buttons_read_s then
shift_buttons_s <= true;
end if;
else
if sample_underflow_s then
if all_buttons_read_s then
-- last button was read
-- so it's ok to timeout
state_s <= FINISHED;
else
-- timeout while reading buttons!
rx_done_s <= true;
state_s <= IDLE;
end if;
else
state_s <= WAIT_FOR_0;
end if;
end if;
when FINISHED =>
-- finally save buttons
save_buttons_s <= true;
rx_done_s <= true;
when others =>
null;
end case;
end process fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
rx_done_o <= rx_done_q;
rx_data_ok_o <= save_buttons_s;
rx_data_o <= buttons_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/10/09 00:33:55 arniml
-- shift rx_data to button assignment to toplevel
--
-- Revision 1.3 2004/10/08 21:18:39 arniml
-- move sampler to separate unit
--
-- Revision 1.2 2004/10/08 20:51:59 arniml
-- turn rx and tx size into bytes instead of bits
--
-- Revision 1.1 2004/10/07 21:23:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 4dbb2d9aa1172a12a3db8d403da21863 | 0.502971 | 4.106657 | false | false | false | false |
AmitThakur/vhdl | mealy/mealy1.vhd | 2 | 772 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mealy IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END mealy ;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock ='1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
PROCESS ( y, w )
BEGIN
CASE y IS
WHEN A =>
z <= '0' ;
WHEN B =>
z <= w ;
END CASE ;
END PROCESS ;
END Behavior ;
| mit | f819649da3bca468b721b5e4d7cee144 | 0.541451 | 2.757143 | false | false | false | false |
freecores/gamepads | snespad/bench/vhdl/tb.vhd | 1 | 7,094 | -------------------------------------------------------------------------------
--
-- Testbench for the
-- SNESpad controller core
--
-- $Id: tb.vhd,v 1.2 2004-10-05 18:19:08 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb is
end tb;
use work.snespad_pack.all;
use work.snespad_comp.snespad;
architecture behav of tb is
constant period_c : time := 100 ns;
constant num_pads_c : natural := 2;
constant reset_level_c : natural := 0;
constant button_level_c : natural := 0;
signal clk_s : std_logic;
signal reset_s : std_logic;
signal pad_clk_s : std_logic;
signal pad_latch_s : std_logic;
signal pad_data_s : std_logic_vector(num_pads_c-1 downto 0);
type buttons_t is array (11 downto 0) of std_logic_vector(num_pads_c-1 downto 0);
signal buttons_s : buttons_t;
signal buttons0_s,
buttons1_s : std_logic_vector(11 downto 0);
begin
dut : snespad
generic map (
num_pads_g => 2,
reset_level_g => reset_level_c,
button_level_g => button_level_c,
clocks_per_6us_g => 60
)
port map (
clk_i => clk_s,
reset_i => reset_s,
pad_clk_o => pad_clk_s,
pad_latch_o => pad_latch_s,
pad_data_i => pad_data_s,
but_a_o => buttons_s(but_pos_a_c),
but_b_o => buttons_s(but_pos_b_c),
but_x_o => buttons_s(but_pos_x_c),
but_y_o => buttons_s(but_pos_y_c),
but_start_o => buttons_s(but_pos_start_c),
but_sel_o => buttons_s(but_pos_sel_c),
but_tl_o => buttons_s(but_pos_tl_c),
but_tr_o => buttons_s(but_pos_tr_c),
but_up_o => buttons_s(but_pos_up_c),
but_down_o => buttons_s(but_pos_down_c),
but_left_o => buttons_s(but_pos_left_c),
but_right_o => buttons_s(but_pos_right_c)
);
buttons: process (buttons_s)
begin
for i in 0 to 11 loop
buttons0_s(i) <= buttons_s(i)(0);
buttons1_s(i) <= buttons_s(i)(1);
end loop;
end process buttons;
-----------------------------------------------------------------------------
-- DUT Stimuli
-----------------------------------------------------------------------------
stimuli: process
procedure dispatch(pad : in natural;
packet : in std_logic_vector(11 downto 0)) is
begin
wait until pad_latch_s = '0';
for i in 11 downto 0 loop
wait until pad_clk_s = '0';
pad_data_s(pad) <= packet(i);
wait until pad_clk_s = '1';
end loop;
wait for period_c;
assert pad_latch_s = '1'
report "Latch not deasserted!"
severity error;
wait for period_c;
for i in 11 downto 0 loop
assert button_active_f(buttons_s(i)(pad), button_level_c) = packet(i)
report "Mismatch for received vs. sent buttons!"
severity error;
end loop;
end dispatch;
begin
pad_data_s <= (others => '1');
wait until reset_s = '1';
wait for period_c * 4;
for pad in 0 to 1 loop
dispatch(pad, packet => "000000000000");
dispatch(pad, packet => "111111111111");
dispatch(pad, packet => "010101010101");
dispatch(pad, packet => "101010101010");
dispatch(pad, packet => "100000000000");
dispatch(pad, packet => "010000000000");
dispatch(pad, packet => "001000000000");
dispatch(pad, packet => "000100000000");
dispatch(pad, packet => "000010000000");
dispatch(pad, packet => "000001000000");
dispatch(pad, packet => "000000100000");
dispatch(pad, packet => "000000010000");
dispatch(pad, packet => "000000001000");
dispatch(pad, packet => "000000000100");
dispatch(pad, packet => "000000000010");
dispatch(pad, packet => "000000000001");
end loop;
wait for period_c * 4;
assert false
report "End of simulation reached."
severity failure;
end process stimuli;
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/10/05 17:05:31 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 6fe3d7408dbf4efbf0337fbd481aafa0 | 0.554835 | 4.023823 | false | false | false | false |
siavooshpayandehazad/TTU_ElevatorLab | VHDL_FILES/wrapper.vhd | 1 | 1,540 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity wrapper is
Port (
clk : in std_logic;
top_sensor : in STD_LOGIC;
bottom_sensor: in std_logic;
fpga_clk : in STD_LOGIC;
fpga_sleep : in STD_LOGIC;
fpga_direction : in STD_LOGIC;
top_sensor_out : out STD_LOGIC;
motor_clk : out STD_LOGIC;
motor_sleep : out STD_LOGIC;
reset_to_controller: out STD_LOGIC;
motor_direction : out STD_LOGIC
);
end wrapper;
architecture Behavioral of wrapper is
signal rst : std_logic;
signal counter : std_logic_vector (19 downto 0);
signal db1,db2,prev_counter,deb_bottom_sensor : std_logic;
begin
top_sensor_out <= top_sensor;
top_sensor_out <= top_sensor;
process (top_sensor,fpga_clk,fpga_sleep,fpga_direction,rst,counter,deb_bottom_sensor)begin
if rst = '0' then
motor_clk <= fpga_clk;
motor_sleep <=fpga_sleep;
motor_direction <=fpga_direction and (not deb_bottom_sensor);
else
motor_clk <= counter(10);
motor_sleep <= '1';
motor_direction <= '1';
end if;
end process;
process (clk) begin
if rising_edge(clk) then
counter <= counter +1;
if top_sensor = '1' then
rst <= '1';
elsif deb_bottom_sensor ='1' then
rst <= '0';
end if;
prev_counter <= counter(19);
if prev_counter = '0' and counter(19) = '1' then
db1 <= bottom_sensor;
db2 <= db1;
end if;
end if;
end process;
deb_bottom_sensor <= db1 and db2 and bottom_sensor;
reset_to_controller <= rst;
end Behavioral;
| gpl-2.0 | c9ce572aa43f7e70bfe2dbbfb4f55272 | 0.644156 | 2.933333 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER_SD1/NIB4_7SEG_SRC.vhd | 38 | 4,182 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity NIB4_7SEG_SRC is
Port ( NIB0 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 0
NIB1 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 1
NIB2 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 2
NIB3 : in std_logic_vector(3 downto 0); -- Nibble Ziffer 3
CLK_DISPL : in std_logic; -- Umschaltfrequenz empfohlen: 1 kHz
ZI0 : out std_logic; -- 1: Ziffer 0 soll leuchten
ZI1 : out std_logic; -- 1: Ziffer 1 soll leuchten
ZI2 : out std_logic; -- 1: Ziffer 2 soll leuchten
ZI3 : out std_logic; -- 1: Ziffer 3 soll leuchten
BA : out std_logic; -- 0: Segment A soll leuchten
BB : out std_logic; -- 0: Segment B soll leuchten
BC : out std_logic; -- 0: Segment C soll leuchten
BD : out std_logic; -- 0: Segment D soll leuchten
BE : out std_logic; -- 0: Segment E soll leuchten
BF : out std_logic; -- 0: Segment F soll leuchten
BG : out std_logic); -- 0: Segment G soll leuchten
end NIB4_7SEG_SRC;
architecture Behavioral of NIB4_7SEG_SRC is
signal COUNTER : std_logic_vector(1 downto 0);
signal NIB_ANZ : std_logic_vector(3 downto 0);
begin
process(CLK_DISPL, NIB3, NIB2, NIB1, NIB0, NIB_ANZ, COUNTER)
begin
If (CLK_DISPL'event and CLK_DISPL = '1')
then COUNTER <= COUNTER +1;
end if;
case COUNTER is
when "00" => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '0';
ZI3 <= '0';
NIB_ANZ <= NIB0;
when "01" => ZI0 <= '0';
ZI1 <= '1';
ZI2 <= '0';
ZI3 <= '0';
NIB_ANZ <= NIB1;
when "10" => ZI0 <= '0';
ZI1 <= '0';
ZI2 <= '1';
ZI3 <= '0';
NIB_ANZ <= NIB2;
when "11" => ZI0 <= '0';
ZI1 <= '0';
ZI2 <= '0';
ZI3 <= '1';
NIB_ANZ <= NIB3;
when others => ZI0 <= '1';
ZI1 <= '0';
ZI2 <= '0';
ZI3 <= '0';
NIB_ANZ <= NIB0;
end case;
case NIB_ANZ is
when "0000" => BG <= '1'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --0
when "0001" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --1
when "0010" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '0'; BA <= '0'; --2
when "0011" => BG <= '0'; BF <= '1'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --3
when "0100" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '1'; --4
when "0101" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --5
when "0110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '0'; --6
when "0111" => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --7
when "1000" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --8
when "1001" => BG <= '0'; BF <= '0'; BE <= '1'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '0'; --9
when "1010" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '0'; BB <= '0'; BA <= '0'; --A
when "1011" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '1'; BA <= '1'; --B
when "1100" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '1'; --C
when "1101" => BG <= '0'; BF <= '1'; BE <= '0'; BD <= '0'; BC <= '0'; BB <= '0'; BA <= '1'; --D
when "1110" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '0'; BC <= '1'; BB <= '1'; BA <= '0'; --E
when "1111" => BG <= '0'; BF <= '0'; BE <= '0'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '0'; --F
when others => BG <= '1'; BF <= '1'; BE <= '1'; BD <= '1'; BC <= '1'; BB <= '1'; BA <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 | abec118708a0662d4cabd8d0b9028b51 | 0.428025 | 2.735121 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/pll/types_pll.vhd | 2 | 4,742 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Components declaration of the types_pll package.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Target names declaration
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' PLL components
package types_pll is
--! @brief Declaration of the "virtual" PLL component.
--! @details This module instantiates the certain PLL implementation
--! depending generic argument.
--! @param[in] tech Generic PLL implementation selector
--! @param[in] i_reset Reset value. Active high.
--! @param[in] i_int_clkrf ADC source select:
--! 0 = External ADC clock (Real RF front-end)
--! 1 = Disable external ADC/enable internal ADC simulation.
--! @param[in] i_clkp Differential clock input positive
--! @param[in] i_clkn Differential clock input negative
--! @param[in] i_clk_adc External ADC clock
--! @param[out] o_clk_bus System Bus clock 100MHz/40MHz (Virtex6/Spartan6)
--! @param[out] o_clk_adc ADC simulation clock = 26MHz (default).
--! @param[out] o_locked PLL locked status.
component SysPLL_tech is
generic(
tech : integer range 0 to NTECH := 0;
tmode_always_ena : boolean := false
);
port (
i_reset : in std_logic;
i_clkp : in std_logic;
i_clkn : in std_logic;
o_clk_bus : out std_logic;
o_clk_50 : out std_logic;
o_clk_50_quad : out std_logic;
o_locked : out std_logic);
end component;
--! @name Technology specific PLL components.
--! @param[in] CLK_IN1_P Differential clock input positive
--! @param[in] CLK_IN1_N Differential clock input negative
--! @param[out] CLK_OUT1 PLL clock output.
--! @param[out] CLK_OUT2 ADC clock simulation.
--! @param[in] RESET Reset value. Active high.
--! @param[out] LOCKED PLL locked status.
--! @{
--! @brief Declaration of the PLL component used for RTL simulation.
component SysPLL_inferred is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Declaration of the PLL component used for ML605 board.
--! @details This module was generated by Xilinx CoreGen for Virtex6 FPGA.
component SysPLL_v6 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Declaration of the PLL component used for KC705 board.
--! @details This module was generated by Xilinx CoreGen for Kintex7 FPGA.
component SysPLL_k7 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
component SysPLL_a7
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
clk_out3 : out std_logic;
clk_out4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
--! @brief Declaration of the PLL component used Mikron 180nm ASIC.
--! @details This module is made as the netlist generated by fabric.
component SysPLL_micron180 is
port (
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic );
end component;
--! @brief Virtual Clock phase rotator.
--! @param[in] tech Technology selector.
--! @param[in] freq Clock frequency in KHz.
--! @param[in] i_rst Reset signal. Active HIGH.
component clkp90_tech is
generic (
tech : integer range 0 to NTECH := 0;
freq : integer := 125000
);
port (
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end component;
--! @}
end;
| bsd-2-clause | e35a01478832ecaafd89950b387b3769 | 0.583087 | 3.622613 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER_SD1/CLOCK_SINGLE_RUN_SRC.vhd | 26 | 2,585 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CLOCK_SINGLE_RUN_SRC is
Port ( CLK: in std_logic; -- (System) Takt
SINGLE: in std_logic; -- 1: Einzeltakt
RUN_R: in std_logic; -- 1: Dauerbetrieb
-- mit Eingangsregister
RESET: in std_logic; -- 1: Initialzustand soll angenommen werden
OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand
end CLOCK_SINGLE_RUN_SRC;
architecture Behavioral of CLOCK_SINGLE_RUN_SRC is
type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände
signal SV: TYPE_STATE; --Zustangsvariable
signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master
signal RUN_S: std_logic;
signal not_CLK : std_logic;
begin
NOT_CLK_PROC: process (CLK)
begin
not_CLK <= not CLK;
end process;
IREG_PROC: process (RUN_R, not_CLK)
begin
if (not_CLK'event and not_CLK = '1')
then RUN_S <= RUN_R;
end if;
end process;
IL_OL_PROC: process (SINGLE, RUN_S, SV)
begin
case SV is
when CSR_0 =>
if (SINGLE = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2;
else
if (RUN_S = '1')
then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
end if;
when CSR_1 => OUT_NEXT_STATE <= '0';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1;
end if;
when CSR_2 => OUT_NEXT_STATE <= '1';
if (SINGLE = '1')
then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2;
else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0;
end if;
when others => OUT_NEXT_STATE <= '0';
end case;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) -- Master
begin
if(RESET = '1')
then SV_M <= CSR_0;
else
if (CLK'event and CLK = '1')
then SV_M <= n_SV;
else SV_M <= SV_M;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave
begin
if(RESET = '1')
then SV <= CSR_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 7d55a2e61d5d78b6ea025c28c5985fb9 | 0.551644 | 3.103241 | false | false | false | false |
akshayp/college-projects | vhdl/pong/Random.vhd | 1 | 3,875 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY random IS
PORT ( clk,clr : IN STD_LOGIC;
POSITION1, POSITION2 : OUT INTEGER RANGE 0 TO 48);
END random;
ARCHITECTURE behave OF random IS
SIGNAL ranvar_1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ranvar_2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(clk,clr)
BEGIN
if clr = '0' then
ranvar_1 <= "00100101";
-- ranvar_2 <= "00100101";
elsIF clk'event and clk = '1' THEN
ranvar_1 <= ranvar_1(7 DOWNTO 0);-- &PN_1
END IF;
IF conv_integer(ranvar_1)< 32 THEN
POSITION1<=16;
POSITION2<= 16;
elsif (conv_integer(ranvar_1) < 40) and (conv_integer(ranvar_1) >31) then
POSITION1<=17;
POSITION2<= 17;
elsif (conv_integer(ranvar_1) < 48) and (conv_integer(ranvar_1) >39) then
POSITION1<=18;
POSITION2<= 18;
elsif (conv_integer(ranvar_1) < 56) and (conv_integer(ranvar_1) >47) then
POSITION1<=19;
POSITION2<= 19;
ELSIF (conv_integer(ranvar_1) < 64) AND (conv_integer(ranvar_1) > 55) THEN
POSITION1<=20;
POSITION2 <=20;
elsif (conv_integer(ranvar_1) < 72) and (conv_integer(ranvar_1) >63) then
POSITION1<=21;
POSITION2<= 21;
elsif (conv_integer(ranvar_1) < 80) and (conv_integer(ranvar_1) >71) then
POSITION1<=22;
POSITION2<= 22;
elsif (conv_integer(ranvar_1) < 88) and (conv_integer(ranvar_1) >79) then
POSITION1<=23;
POSITION2<= 23;
ELSIF (conv_integer(ranvar_1) < 96) AND (conv_integer(ranvar_1) > 87) THEN
POSITION1<=24;
POSITION2 <=24;
elsif (conv_integer(ranvar_1) < 104) and (conv_integer(ranvar_1) >95) then
POSITION1<=25;
POSITION2<= 25;
elsif (conv_integer(ranvar_1) < 112) and (conv_integer(ranvar_1) >103) then
POSITION1<=26;
POSITION2<= 26;
elsif (conv_integer(ranvar_1) < 120) and (conv_integer(ranvar_1) >111) then
POSITION1<=27;
POSITION2<= 27;
ELSIF (conv_integer(ranvar_1) < 128) AND (conv_integer(ranvar_1) > 119) THEN
POSITION1<=28;
POSITION2 <=28;
elsif (conv_integer(ranvar_1) < 136) and (conv_integer(ranvar_1) >127) then
POSITION1<=29;
POSITION2<= 29;
elsif (conv_integer(ranvar_1) < 144) and (conv_integer(ranvar_1) >135) then
POSITION1<=30;
POSITION2<= 30;
elsif (conv_integer(ranvar_1) < 152) and (conv_integer(ranvar_1) >143) then
POSITION1<=31;
POSITION2<= 31;
ELSIF (conv_integer(ranvar_1) < 160) AND (conv_integer(ranvar_1) > 151) THEN
POSITION1<=32;
POSITION2 <=32;
elsif (conv_integer(ranvar_1) < 168) and (conv_integer(ranvar_1) >159) then
POSITION1<=33;
POSITION2<= 33;
elsif (conv_integer(ranvar_1) < 176) and (conv_integer(ranvar_1) >167) then
POSITION1<=34;
POSITION2<= 34;
elsif (conv_integer(ranvar_1) < 184) and (conv_integer(ranvar_1) >175) then
POSITION1<=35;
POSITION2<= 35;
ELSIF (conv_integer(ranvar_1) < 192) AND (conv_integer(ranvar_1) > 183) THEN
POSITION1<=36;
POSITION2 <=36;
elsif (conv_integer(ranvar_1) < 200) and (conv_integer(ranvar_1) >191) then
POSITION1<=37;
POSITION2<= 37;
elsif (conv_integer(ranvar_1) < 208) and (conv_integer(ranvar_1) >199) then
POSITION1<=38;
POSITION2<= 38;
elsif (conv_integer(ranvar_1) < 216) and (conv_integer(ranvar_1) >207) then
POSITION1<=39;
POSITION2<= 39;
ELSIF (conv_integer(ranvar_1) < 224) AND (conv_integer(ranvar_1) > 215) THEN
POSITION1<=40;
POSITION2 <=40;
elsif (conv_integer(ranvar_1) < 232) and (conv_integer(ranvar_1) >223) then
POSITION1<=41;
POSITION2<= 41;
elsif (conv_integer(ranvar_1) < 240) and (conv_integer(ranvar_1) >231) then
POSITION1<=42;
POSITION2<= 42;
elsif (conv_integer(ranvar_1) < 248) and (conv_integer(ranvar_1) >239) then
POSITION1<=43;
POSITION2<= 43;
ELSIF (conv_integer(ranvar_1) > 247) THEN
POSITION1<=44;
POSITION2 <=44;
END IF;
END PROCESS;
END behave; | mit | 07963ac675c174acedd07120c56f1de9 | 0.648774 | 2.717391 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/tilelink/starter.vhd | 2 | 4,189 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'starter' module.
--! @details Everytime after hard reset Rocket core is in resetting
--! state. Module Uncore::HTIF implements writting into
--! MRESET CSR-register (0x784) and not allow to start CPU
--! execution. This resetting cycle is ongoing upto external
--! write 0-value into this MRESET register.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Hard-reset initialization module.
--! @details L2-cached system implementing Uncore module must be switched
--! from resetting state that is done by this module.
--! param[in] HTIF interface clock.
--! param[in] Reset signal with the active LOW level.
--! param[in] i_host HostIO input signals.
--! param[out] o_host HostIO output signals.
entity starter is port
(
clk : in std_logic;
nrst : in std_logic;
i_host : in host_in_type;
o_host : out host_out_type;
o_init_ena : out std_logic
);
end;
architecture arch_starter of starter is
type state_type is (init_reset, init_cmd, wait_ready, wait_resp, disable);
type registers is record
state : state_type;
init_ena : std_logic;
cmdCnt : integer range 0 to 3;
end record;
signal r, rin: registers;
begin
comblogic : process(i_host, r)
variable v : registers;
begin
v := r;
case r.state is
when init_reset =>
v.state := init_cmd;
o_host.reset <= '1';
o_host.id <= '0';
o_host.csr_req_valid <= '0';
o_host.csr_req_bits_rw <= '0';
o_host.csr_req_bits_addr <= (others => '0');
o_host.csr_req_bits_data <= (others => '0');
o_host.csr_resp_ready <= '1';
when init_cmd =>
o_host.reset <= '0';
--! Select CSR write command
case r.cmdCnt is
when 0 =>
-- PLL divide. One Tile at once.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"03f";
o_host.csr_req_bits_data <= X"0000000000020005";
when 1 =>
-- Set CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000001";
when 2 =>
-- Clear CSR29.
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"01d";
o_host.csr_req_bits_data <= X"0000000000000000";
when 3 =>
-- Write MRESET
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= X"782";
o_host.csr_req_bits_data <= X"0000000000000000";
when others =>
v.state := disable;
end case;
if i_host.csr_req_ready = '0' then
v.state := wait_ready;
else
v.state := wait_resp;
end if;
when wait_ready =>
if i_host.csr_req_ready = '1' then
v.state := wait_resp;
o_host.csr_req_valid <= '0';
end if;
when wait_resp =>
if i_host.csr_resp_valid = '1' then
v.cmdCnt := r.cmdCnt + 1;
if r.cmdCnt = 3 then
v.state := disable;
v.init_ena := '0';
else
v.state := init_cmd;
end if;
end if;
when others =>
end case;
rin <= v;
end process;
o_init_ena <= r.init_ena;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= init_reset;
r.init_ena <= '1';
r.cmdCnt <= 0;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 32219ddd3e20063b24187cc6234d7c44 | 0.51492 | 3.562075 | false | false | false | false |
eiglss/VHDL | UART/counter.vhd | 1 | 1,614 | --******************************************************************************
-- @TITRE : counter.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY counter IS
GENERIC(length : POSITIVE := 8
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
en, rst, incNotDec, load : IN STD_LOGIC;
dIn : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0);
dOut : OUT STD_LOGIC_VECTOR(length-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE Behavioral OF counter IS
SIGNAL countReg : UNSIGNED(length-1 DOWNTO 0);
BEGIN
dOut <= STD_LOGIC_VECTOR(countReg);
counter_p : PROCESS(clk, aNRst)
BEGIN
IF aNRst /= '1' THEN
countReg <= (OTHERS => '0');
ELSIF RISING_EDGE(clk) THEN
IF rst /= '0' THEN
countReg <= (OTHERS => '0');
ELSIF load = '1' THEN
countReg <= UNSIGNED(din);
ELSIF en = '1' THEN
IF incNotDec = '1' THEN
countReg <= countReg+1;
ELSIF incNotDec = '0' THEN
countReg <= countReg-1;
END IF;
END IF;
END IF;
END PROCESS counter_p;
END Behavioral;
| mit | ee73f446334c89ed383b9919d52e2d8f | 0.443618 | 4.373984 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/misc/nasti_uart.vhd | 2 | 12,922 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief RS-232 UART with the AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity nasti_uart is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
o_irq : out std_logic
);
end;
architecture arch_nasti_uart of nasti_uart is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_UART,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type fifo_type is array (0 to fifosz-1) of std_logic_vector(7 downto 0);
type state_type is (idle, startbit, data, parity, stopbit);
type bank_type is record
tx_state : state_type;
tx_fifo : fifo_type;
tx_wr_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
tx_rd_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
tx_byte_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
tx_shift : std_logic_vector(10 downto 0); --! stopbit=1,parity=xor,data[7:0],startbit=0
tx_data_cnt : integer range 0 to 11;
tx_scaler_cnt : integer;
tx_level : std_logic;
tx_irq_thresh : std_logic_vector(log2(fifosz)-1 downto 0);
tx_more_thresh : std_logic_vector(1 downto 0);
rx_state : state_type;
rx_fifo : fifo_type;
rx_wr_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
rx_rd_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
rx_byte_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
rx_shift : std_logic_vector(7 downto 0);
rx_data_cnt : integer range 0 to 7;
rx_scaler_cnt : integer;
rx_level : std_logic;
rx_irq_thresh : std_logic_vector(log2(fifosz)-1 downto 0);
rx_more_thresh : std_logic_vector(1 downto 0);
scaler : integer;
err_parity : std_logic;
err_stopbit : std_logic;
parity_bit : std_logic;
tx_irq_ena : std_logic;
rx_irq_ena : std_logic;
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
signal r, rin : registers;
begin
comblogic : process(i_uart, i_axi, r)
variable v : registers;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable posedge_flag : std_logic;
variable negedge_flag : std_logic;
variable tx_fifo_empty : std_logic;
variable tx_fifo_full : std_logic;
variable rx_fifo_empty : std_logic;
variable rx_fifo_full : std_logic;
variable t_tx, t_rx : std_logic_vector(7 downto 0);
variable par : std_logic;
variable irq_ena : std_logic;
begin
v := r;
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
-- Check FIFOs counters with thresholds:
v.bank0.tx_more_thresh := r.bank0.tx_more_thresh(0) & '0';
if r.bank0.tx_byte_cnt > r.bank0.tx_irq_thresh then
v.bank0.tx_more_thresh(0) := '1';
end if;
v.bank0.rx_more_thresh := r.bank0.rx_more_thresh(0) & '0';
if r.bank0.rx_byte_cnt > r.bank0.rx_irq_thresh then
v.bank0.rx_more_thresh(0) := '1';
end if;
irq_ena := '0';
if (r.bank0.tx_more_thresh(1) and not r.bank0.tx_more_thresh(0)) = '1' then
irq_ena := r.bank0.tx_irq_ena;
end if;
if (not r.bank0.rx_more_thresh(1) and r.bank0.rx_more_thresh(0)) = '1' then
irq_ena := irq_ena or r.bank0.rx_irq_ena;
end if;
-- system bus clock scaler to baudrate:
posedge_flag := '0';
negedge_flag := '0';
if r.bank0.scaler /= 0 then
if r.bank0.tx_scaler_cnt = (r.bank0.scaler-1) then
v.bank0.tx_scaler_cnt := 0;
v.bank0.tx_level := not r.bank0.tx_level;
posedge_flag := not r.bank0.tx_level;
else
v.bank0.tx_scaler_cnt := r.bank0.tx_scaler_cnt + 1;
end if;
if r.bank0.rx_state = idle and i_uart.rd = '1' then
v.bank0.rx_scaler_cnt := 0;
v.bank0.rx_level := '1';
elsif r.bank0.rx_scaler_cnt = (r.bank0.scaler-1) then
v.bank0.rx_scaler_cnt := 0;
v.bank0.rx_level := not r.bank0.rx_level;
negedge_flag := r.bank0.rx_level;
else
v.bank0.rx_scaler_cnt := r.bank0.rx_scaler_cnt + 1;
end if;
end if;
-- Transmitter's FIFO:
tx_fifo_full := '0';
if (r.bank0.tx_wr_cnt + 1) = r.bank0.tx_rd_cnt then
tx_fifo_full := '1';
end if;
tx_fifo_empty := '0';
if r.bank0.tx_rd_cnt = r.bank0.tx_wr_cnt then
tx_fifo_empty := '1';
v.bank0.tx_byte_cnt := (others => '0');
end if;
-- Receiver's FIFO:
rx_fifo_full := '0';
if (r.bank0.rx_wr_cnt + 1) = r.bank0.rx_rd_cnt then
rx_fifo_full := '1';
end if;
rx_fifo_empty := '0';
if r.bank0.rx_rd_cnt = r.bank0.rx_wr_cnt then
rx_fifo_empty := '1';
v.bank0.rx_byte_cnt := (others => '0');
end if;
-- Transmitter's state machine:
if i_uart.cts = '1' and posedge_flag = '1' then
case r.bank0.tx_state is
when idle =>
if tx_fifo_empty = '0' then
-- stopbit=1,parity=xor,data[7:0],startbit=0
t_tx := r.bank0.tx_fifo(conv_integer(r.bank0.tx_rd_cnt));
if r.bank0.parity_bit = '1' then
par := t_tx(7) xor t_tx(6) xor t_tx(5) xor t_tx(4)
xor t_tx(3) xor t_tx(2) xor t_tx(1) xor t_tx(0);
v.bank0.tx_shift := '1' & par & t_tx & '0';
else
v.bank0.tx_shift := "11" & t_tx & '0';
end if;
v.bank0.tx_state := startbit;
v.bank0.tx_rd_cnt := r.bank0.tx_rd_cnt + 1;
v.bank0.tx_byte_cnt := r.bank0.tx_byte_cnt - 1;
v.bank0.tx_data_cnt := 0;
end if;
when startbit =>
v.bank0.tx_state := data;
when data =>
if r.bank0.tx_data_cnt = 8 then
if r.bank0.parity_bit = '1' then
v.bank0.tx_state := parity;
else
v.bank0.tx_state := stopbit;
end if;
end if;
when parity =>
v.bank0.tx_state := stopbit;
when stopbit =>
v.bank0.tx_state := idle;
when others =>
end case;
if r.bank0.tx_state /= idle then
v.bank0.tx_data_cnt := r.bank0.tx_data_cnt + 1;
v.bank0.tx_shift := '1' & r.bank0.tx_shift(10 downto 1);
end if;
end if;
--! Receiver's state machine:
if negedge_flag = '1' then
case r.bank0.rx_state is
when idle =>
if i_uart.rd = '0' then
v.bank0.rx_state := data;
v.bank0.rx_shift := (others => '0');
v.bank0.rx_data_cnt := 0;
end if;
when data =>
v.bank0.rx_shift := i_uart.rd & r.bank0.rx_shift(7 downto 1);
if r.bank0.rx_data_cnt = 7 then
if r.bank0.parity_bit = '1' then
v.bank0.rx_state := parity;
else
v.bank0.rx_state := stopbit;
end if;
else
v.bank0.rx_data_cnt := r.bank0.rx_data_cnt + 1;
end if;
when parity =>
t_rx := r.bank0.rx_shift;
par := t_rx(7) xor t_rx(6) xor t_rx(5) xor t_rx(4)
xor t_rx(3) xor t_rx(2) xor t_rx(1) xor t_rx(0);
if par = i_uart.rd then
v.bank0.err_parity := '0';
else
v.bank0.err_parity := '1';
end if;
v.bank0.rx_state := stopbit;
when stopbit =>
if i_uart.rd = '0' then
v.bank0.err_stopbit := '1';
else
v.bank0.err_stopbit := '0';
end if;
if rx_fifo_full = '0' then
v.bank0.rx_fifo(conv_integer(r.bank0.rx_wr_cnt)) := r.bank0.rx_shift;
v.bank0.rx_wr_cnt := r.bank0.rx_wr_cnt + 1;
v.bank0.rx_byte_cnt := r.bank0.rx_byte_cnt + 1;
end if;
v.bank0.rx_state := idle;
when others =>
end case;
end if;
o_uart.rts <= '1';
if r.bank0.tx_state = idle then
o_uart.td <= '1';
else
o_uart.td <= r.bank0.tx_shift(0);
end if;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := (others => '0');
case conv_integer(r.bank_axi.raddr(n)(11 downto 2)) is
when 0 =>
if rx_fifo_empty = '0' then
tmp(7 downto 0) := r.bank0.rx_fifo(conv_integer(r.bank0.rx_rd_cnt));
v.bank0.rx_rd_cnt := r.bank0.rx_rd_cnt + 1;
v.bank0.rx_byte_cnt := r.bank0.rx_byte_cnt - 1;
end if;
when 1 =>
tmp(1 downto 0) := tx_fifo_empty & tx_fifo_full;
tmp(5 downto 4) := rx_fifo_empty & rx_fifo_full;
tmp(9 downto 8) := r.bank0.err_stopbit & r.bank0.err_parity;
tmp(13) := r.bank0.rx_irq_ena;
tmp(14) := r.bank0.tx_irq_ena;
tmp(15) := r.bank0.parity_bit;
when 2 =>
tmp := conv_std_logic_vector(r.bank0.scaler,32);
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
wstrb := i_axi.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
tmp := i_axi.w_data(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
case conv_integer(r.bank_axi.waddr(n)(11 downto 2)) is
when 0 =>
if tx_fifo_full = '0' then
v.bank0.tx_fifo(conv_integer(r.bank0.tx_wr_cnt)) := tmp(7 downto 0);
v.bank0.tx_wr_cnt := r.bank0.tx_wr_cnt + 1;
v.bank0.tx_byte_cnt := r.bank0.tx_byte_cnt + 1;
end if;
when 1 =>
v.bank0.parity_bit := tmp(15);
v.bank0.tx_irq_ena := tmp(14);
v.bank0.rx_irq_ena := tmp(13);
when 2 =>
v.bank0.scaler := conv_integer(tmp);
v.bank0.rx_scaler_cnt := 0;
v.bank0.tx_scaler_cnt := 0;
when others =>
end case;
end if;
end loop;
end if;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
o_irq <= irq_ena;
rin <= v;
end process;
cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
r.bank0.tx_state <= idle;
r.bank0.tx_level <= '0';
r.bank0.tx_scaler_cnt <= 0;
r.bank0.tx_rd_cnt <= (others => '0');
r.bank0.tx_wr_cnt <= (others => '0');
r.bank0.tx_byte_cnt <= (others => '0');
r.bank0.tx_irq_thresh <= (others => '0');
r.bank0.tx_more_thresh <= (others => '0');
r.bank0.rx_state <= idle;
r.bank0.rx_level <= '1';
r.bank0.rx_scaler_cnt <= 0;
r.bank0.rx_rd_cnt <= (others => '0');
r.bank0.rx_wr_cnt <= (others => '0');
r.bank0.rx_byte_cnt <= (others => '0');
r.bank0.rx_irq_thresh <= (others => '0');
r.bank0.rx_more_thresh <= (others => '0');
r.bank0.scaler <= 0;
r.bank0.err_parity <= '0';
r.bank0.err_stopbit <= '0';
r.bank0.parity_bit <= '0';
r.bank0.tx_irq_ena <= '1';
r.bank0.rx_irq_ena <= '1';
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; | bsd-2-clause | a761bd3ecd22b32b3b6ada042ba230cc | 0.509441 | 3.098058 | false | false | false | false |
akshayp/college-projects | vhdl/pong/bat.vhd | 1 | 2,926 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bat IS
PORT ( clr, CLKBAT : IN STD_LOGIC;
scan_code : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : IN std_logic;
read : OUT std_logic;
paddle_1, paddle_2 : OUT INTEGER RANGE 0 to 48);
END bat;
ARCHITECTURE position OF bat IS
TYPE STATE_TYPE IS (wait_ready, read_data, read_low);
SIGNAL state: STATE_TYPE;
SIGNAL clock_enable :Std_logic;
signal a, b, c, d ,e, f, g, h : std_logic_vector(15 downto 0);
BEGIN
a <= "0001101100011011";
b <= "1111000000011011";
c <= "0001110100011101";
d <= "1111000000011101";
e <= "0100110001001100";
f <= "1111000001001100";
g <= "0100110101001101";
h <= "1111000001001101";
PROCESS(scan_ready, CLR,CLKBAT, clock_enable)
VARIABLE pdl_1, pdl_2 : INTEGER RANGE 0 to 48; -- temporary position
BEGIN
IF clr='0' THEN
pdl_1 := 32;
pdl_2 := 32;
state <= read_low;
ELSIF CLKBAT'EVENT AND CLKBAT = '1' THEN
case state is
when read_low =>
read <= '0';
state <= wait_ready;
WHEN wait_ready =>
IF scan_ready = '1' THEN
read <= '1';
state <= read_data;
ELSE
state <= wait_ready;
END IF;
WHEN read_data =>
IF (("00011011" & scan_code) = a) THEN
pdl_1 := pdl_1 + 1;
paddle_1 <= pdl_1;
state <= read_low;
ELSIF (("11110000" & scan_code) = b) then
pdl_1 :=pdl_1;
paddle_1 <= pdl_1;
state <= read_low;
ELSIF (("00011101" & scan_code) = c) THEN
pdl_1 := pdl_1 - 1;
paddle_1 <= pdl_1;
state <= read_low;
elsif (("11110000" & scan_code) = d) then
pdl_1 :=pdl_1;
paddle_1 <= pdl_1;
state <= read_low;
elsIF (("01001100" & scan_code) = e) THEN
pdl_2 := pdl_2 + 1;
paddle_2 <=pdl_2;
state <= read_low;
elsif (("11110000" & scan_code) = f) then
pdl_2 :=pdl_2;
state <= read_low;
ELSIF (("01001101" & scan_code) = g) THEN
pdl_2 := pdl_2 - 1;
paddle_2 <=pdl_2;
state <= read_low;
elsif ("11110000" & scan_code = h) then
pdl_2 :=pdl_2;
paddle_2 <=pdl_2;
state <= read_low;
END IF;
end case;
END IF;
IF pdl_1 >16 AND pdl_1 < 48 THEN
Paddle_1 <=pdl_1;
ELSIF pdl_1 <= 15 THEN
Paddle_1 <= 16;
ELSIF pdl_1 >= 49 THEN
Paddle_1 <= 48;
END IF;
IF pdl_2 >16 AND pdl_2 < 48 THEN
Paddle_2 <=pdl_2;
ELSIF pdl_2 <= 15 THEN
Paddle_2 <= 16;
ELSIF pdl_2 >= 49 THEN
Paddle_2 <= 48;
END IF;
END PROCESS;
END position;
| mit | 7677a3a3322ada516f0c4272dd15f52a | 0.484279 | 3.032124 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/misc/nasti_gpio.vhd | 1 | 4,437 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Controller of the GPIOs with the AMBA AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_gpio is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type;
i_dip : in std_logic_vector(3 downto 0);
o_led : out std_logic_vector(7 downto 0)
);
end;
architecture arch_nasti_gpio of nasti_gpio is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPIO,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type bank_type is record
led : std_logic_vector(31 downto 0);
dip : std_logic_vector(31 downto 0);
reg32_2 : std_logic_vector(31 downto 0);
reg32_3 : std_logic_vector(31 downto 0);
reg32_4 : std_logic_vector(31 downto 0);
reg32_5 : std_logic_vector(31 downto 0);
reg32_6 : std_logic_vector(31 downto 0);
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
constant RESET_VALUE : registers := (
NASTI_SLAVE_BANK_RESET,
((others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'))
);
signal r, rin : registers;
begin
comblogic : process(i, i_dip, r, nrst)
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
begin
v := r;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := r.bank0.led;
when 1 => tmp := r.bank0.dip;
when 2 => tmp := r.bank0.reg32_2;
when 3 => tmp := r.bank0.reg32_3;
when 4 => tmp := r.bank0.reg32_4;
when 5 => tmp := r.bank0.reg32_5;
when 6 => tmp := r.bank0.reg32_6;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
wstrb := i.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i.w_data(32*(n+1)-1 downto 32*n);
if conv_integer(wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
case waddr_reg(n) is
when 0 => v.bank0.led := tmp;
--when 1 => v.bank0.dip := tmp;
when 2 => v.bank0.reg32_2 := tmp;
when 3 => v.bank0.reg32_3 := tmp;
when 4 => v.bank0.reg32_4 := tmp;
when 5 => v.bank0.reg32_5 := tmp;
when 6 => v.bank0.reg32_6 := tmp;
when others =>
end case;
end if;
end loop;
end if;
o <= functionAxi4Output(r.bank_axi, rdata);
v.bank0.dip(3 downto 0) := i_dip;
if nrst = '0' then
v := RESET_VALUE;
end if;
rin <= v;
end process;
cfg <= xconfig;
o_led <= r.bank0.led(7 downto 0);
-- registers:
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 0534d78db469b76a81e7aaebcbbeb551 | 0.556682 | 3.276957 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/eth/eth_axi_mst.vhd | 2 | 7,538 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief AXI Master device implementing DMA access.
--! @details AMBA4 AXI Master interface module dedicated for the eth MAC.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
use rocketlib.grethpkg.all;
entity eth_axi_mst is
generic (
xindex : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
aximi : in nasti_master_in_type;
aximo : out nasti_master_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end entity;
architecture rtl of eth_axi_mst is
constant STATE_IDLE : integer := 0;
constant STATE_W : integer := STATE_IDLE+1;
constant STATE_R : integer := STATE_W+1;
constant STATE_B : integer := STATE_R+1;
type reg_type is record
state : integer range 0 to STATE_B;
addr : std_logic_vector(31 downto 0);
len : integer;
rx_tx : std_logic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, aximi) is
variable v : reg_type;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
variable vmsto : nasti_master_out_type;
variable rdata_lsb : std_logic_vector(31 downto 0);
variable wdata_lsb : std_logic_vector(31 downto 0);
begin
v := r;
vmsto := nasti_master_out_none;
rready := '0';
tready := '0';
tretry := '0';
rretry := '0';
rerror := '0';
terror := '0';
tgrant := '0';
rgrant := '0';
vmsto.ar_user := '0';
vmsto.ar_id := conv_std_logic_vector(xindex, CFG_ROCKET_ID_BITS);
vmsto.ar_bits.size := "010"; -- 4 bytes
vmsto.ar_bits.burst := NASTI_BURST_INCR;
vmsto.aw_user := '0';
vmsto.aw_id := conv_std_logic_vector(xindex, CFG_ROCKET_ID_BITS);
vmsto.aw_bits.size := "010"; -- 4 bytes
vmsto.aw_bits.burst := NASTI_BURST_INCR;
case r.state is
when STATE_IDLE =>
if rmsti.req = '1' then
v.rx_tx := '0';
v.addr := rmsti.addr;
vmsto.ar_valid := not rmsti.write;
vmsto.aw_valid := rmsti.write;
if rmsti.write = '1' then
vmsto.aw_bits.addr := rmsti.addr(31 downto 4) & "0000";
v.len := conv_integer(rmsti.burst_bytes(10 downto 2)) - 1;
vmsto.aw_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.aw_ready) = '1' then
rgrant := '1';
v.state := STATE_W;
end if;
else
vmsto.ar_bits.addr := rmsti.addr;
v.len := conv_integer(rmsti.burst_bytes(10 downto 2)) - 1;
vmsto.ar_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.ar_ready) = '1' then
rgrant := '1';
v.state := STATE_R;
end if;
end if;
elsif tmsti.req = '1' then
v.rx_tx := '1';
v.addr := tmsti.addr;
vmsto.ar_valid := not tmsti.write;
vmsto.aw_valid := tmsti.write;
if tmsti.write = '1' then
vmsto.aw_bits.addr := tmsti.addr(31 downto 4) & "0000";
v.len := conv_integer(tmsti.burst_bytes(10 downto 2)) - 1;
vmsto.aw_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.aw_ready) = '1' then
tgrant := '1';
v.state := STATE_W;
end if;
else
vmsto.ar_bits.addr := tmsti.addr;
v.len := conv_integer(tmsti.burst_bytes(10 downto 2)) - 1;
vmsto.ar_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.ar_ready) = '1' then
tgrant := '1';
v.state := STATE_R;
end if;
end if;
end if;
when STATE_W =>
vmsto.w_valid := '1';
case r.addr(3 downto 2) is
when "00" => vmsto.w_strb := X"000f";
when "01" => vmsto.w_strb := X"00f0";
when "10" => vmsto.w_strb := X"0f00";
when "11" => vmsto.w_strb := X"f000";
when others =>
end case;
if r.rx_tx = '0' then
wdata_lsb := rmsti.data(7 downto 0) & rmsti.data(15 downto 8)
& rmsti.data(23 downto 16) & rmsti.data(31 downto 24);
else
wdata_lsb := tmsti.data(7 downto 0) & tmsti.data(15 downto 8)
& tmsti.data(23 downto 16) & tmsti.data(31 downto 24);
end if;
vmsto.w_data := wdata_lsb & wdata_lsb & wdata_lsb & wdata_lsb;
if aximi.w_ready = '1' then
tready := r.rx_tx;
rready := not r.rx_tx;
if r.len = 0 then
v.state := STATE_B;
else
tgrant := r.rx_tx;
rgrant := not r.rx_tx;
v.len := r.len - 1;
-- Incremented on slave side
--v.addr = r.addr + 4;
end if;
end if;
when STATE_R =>
vmsto.r_ready := '1';
if aximi.r_valid = '1' then
if aximi.r_resp = NASTI_RESP_OKAY then
tready := r.rx_tx;
rready := not r.rx_tx;
else
terror := r.rx_tx;
rerror := not r.rx_tx;
end if;
if r.len = 0 then
v.state := state_idle;
else
tgrant := r.rx_tx;
rgrant := not r.rx_tx;
v.len := r.len - 1;
end if;
end if;
when STATE_B =>
vmsto.b_ready := '1';
if aximi.b_valid = '1' then
v.state := STATE_IDLE;
end if;
when others =>
end case;
if rst = '0' then
v.state := STATE_IDLE;
v.addr := (others => '0');
v.len := 0;
v.rx_tx := '0';
end if;
-- Pre-fix for SPARC byte order.
-- It is better to fix in MAC itselfm but for now it will be here.
rdata_lsb := aximi.r_data(7 downto 0) & aximi.r_data(15 downto 8)
& aximi.r_data(23 downto 16) & aximi.r_data(31 downto 24);
rin <= v;
aximo <= vmsto;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
tmsto.grant <= tgrant;
tmsto.data <= rdata_lsb;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
rmsto.grant <= rgrant;
rmsto.data <= rdata_lsb;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
| bsd-2-clause | 5454b90159d12c99ad801f9d2edda7a8 | 0.498806 | 3.545626 | false | false | false | false |
freecores/gamepads | gcpad/rtl/vhdl/gcpad_pack-p.vhd | 1 | 3,366 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- $Id: gcpad_pack-p.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package gcpad_pack is
subtype analog_axis_t is std_logic_vector(7 downto 0);
constant num_buttons_c : natural := 64;
subtype buttons_t is std_logic_vector(num_buttons_c-1 downto 0);
function "=" (a : in std_logic; b : in integer) return boolean;
-----------------------------------------------------------------------------
-- The button positions inside a gc packet
-----------------------------------------------------------------------------
-- byte 7 -------------------------------------------------------------------
constant pos_errstat_c : natural := 63;
constant pos_errlatch_c : natural := 62;
constant pos_unknown1_c : natural := 61;
constant pos_start_c : natural := 60;
constant pos_y_c : natural := 59;
constant pos_x_c : natural := 58;
constant pos_b_c : natural := 57;
constant pos_a_c : natural := 56;
-- byte 6 -------------------------------------------------------------------
constant pos_unknown2_c : natural := 55;
constant pos_tl_c : natural := 54;
constant pos_tr_c : natural := 53;
constant pos_z_c : natural := 52;
constant pos_up_c : natural := 51;
constant pos_down_c : natural := 50;
constant pos_right_c : natural := 49;
constant pos_left_c : natural := 48;
-- byte 5 -------------------------------------------------------------------
constant joy_x_high_c : natural := 47;
constant joy_x_low_c : natural := 40;
-- byte 4 -------------------------------------------------------------------
constant joy_y_high_c : natural := 39;
constant joy_y_low_c : natural := 32;
-- byte 3 -------------------------------------------------------------------
constant c_x_high_c : natural := 31;
constant c_x_low_c : natural := 24;
-- byte 2 -------------------------------------------------------------------
constant c_y_high_c : natural := 23;
constant c_y_low_c : natural := 16;
-- byte 1 -------------------------------------------------------------------
constant l_high_c : natural := 15;
constant l_low_c : natural := 8;
-- byte 0 -------------------------------------------------------------------
constant r_high_c : natural := 7;
constant r_low_c : natural := 0;
end gcpad_pack;
package body gcpad_pack is
-----------------------------------------------------------------------------
-- Function =
--
-- Compares a std_logic with an integer.
--
function "=" (a : in std_logic; b : in integer) return boolean is
variable result_v : boolean;
begin
result_v := false;
case a is
when '0' =>
if b = 0 then
result_v := true;
end if;
when '1' =>
if b = 1 then
result_v := true;
end if;
when others =>
null;
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
end gcpad_pack;
| gpl-2.0 | 21c5f23656adfb76d3cead650c4cbea4 | 0.397504 | 4.493992 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/misc/nasti_gptimers.vhd | 2 | 6,389 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief General Purpose Timers with the AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity nasti_gptimers is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
o_irq : out std_logic
);
end;
architecture arch_nasti_gptimers of nasti_gptimers is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPTIMERS,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type timer_type is record
count_ena : std_logic;
irq_ena : std_logic;
value : std_logic_vector(63 downto 0);
init_value : std_logic_vector(63 downto 0);
end record;
constant timer_type_reset : timer_type :=
('0', '0', (others => '0'), (others => '0'));
type vector_timer_type is array (0 to tmr_total-1) of timer_type;
type bank_type is record
tmr : vector_timer_type;
highcnt : std_logic_vector(63 downto 0);
pending : std_logic_vector(tmr_total-1 downto 0);
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
signal r, rin : registers;
begin
comblogic : process(i_axi, r)
variable v : registers;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable raddr : integer;
variable waddr : integer;
variable irq_ena : std_logic;
begin
v := r;
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
v.bank0.highcnt := r.bank0.highcnt + 1;
irq_ena := '0';
for n in 0 to tmr_total-1 loop
if r.bank0.tmr(n).count_ena = '1' then
if r.bank0.tmr(n).value = zero64 then
irq_ena := irq_ena or r.bank0.tmr(n).irq_ena;
v.bank0.pending(n) := r.bank0.tmr(n).irq_ena;
v.bank0.tmr(n).value := r.bank0.tmr(n).init_value;
else
v.bank0.tmr(n).value := r.bank0.tmr(n).value - 1;
end if;
else
v.bank0.tmr(n).value := r.bank0.tmr(n).init_value;
end if;
end loop;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := (others => '0');
raddr := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
case raddr is
when 0 =>
tmp := r.bank0.highcnt(31 downto 0);
when 1 =>
tmp := r.bank0.highcnt(63 downto 32);
when 2 =>
tmp(tmr_total-1 downto 0) := r.bank0.pending;
when others =>
for k in 0 to tmr_total-1 loop
if raddr = (16 + 8*k) then
tmp(0) := r.bank0.tmr(k).count_ena;
tmp(1) := r.bank0.tmr(k).irq_ena;
elsif raddr = (16 + 8*k + 2) then
tmp := r.bank0.tmr(k).value(31 downto 0);
elsif raddr = (16 + 8*k + 3) then
tmp := r.bank0.tmr(k).value(63 downto 32);
elsif raddr = (16 + 8*k + 4) then
tmp := r.bank0.tmr(k).init_value(31 downto 0);
elsif raddr = (16 + 8*k + 5) then
tmp := r.bank0.tmr(k).init_value(63 downto 32);
end if;
end loop;
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
wstrb := i_axi.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
tmp := i_axi.w_data(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
waddr := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
case waddr is
when 2 =>
v.bank0.pending := tmp(tmr_total-1 downto 0);
when others =>
for k in 0 to tmr_total-1 loop
if raddr = (16 + 8*k) then
v.bank0.tmr(k).count_ena := tmp(0);
v.bank0.tmr(k).irq_ena := tmp(1);
elsif raddr = (16 + 8*k + 2) then
v.bank0.tmr(k).value(31 downto 0) := tmp;
elsif raddr = (16 + 8*k + 3) then
v.bank0.tmr(k).value(63 downto 32) := tmp;
elsif raddr = (16 + 8*k + 4) then
v.bank0.tmr(k).init_value(31 downto 0) := tmp;
elsif raddr = (16 + 8*k + 5) then
v.bank0.tmr(k).init_value(63 downto 32) := tmp;
end if;
end loop;
end case;
end if;
end loop;
end if;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
o_irq <= irq_ena;
rin <= v;
end process;
cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
r.bank0.highcnt <= (others => '0');
r.bank0.pending <= (others => '0');
for k in 0 to tmr_total-1 loop
r.bank0.tmr(k) <= timer_type_reset;
end loop;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | 18d403d18701626136d0dfff9f2ca1aa | 0.519956 | 3.423901 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/pll/SysPLL_inferred.vhd | 2 | 1,413 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details PLL instance for the behaviour simulation
--!
--! "Output Output Phase Duty Pk-to-Pk Phase"
--! "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
--!
--! CLK_OUT1____70.000
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--library unisim;
--use unisim.vcomponents.all;
entity SysPLL_inferred is
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_inferred;
architecture rtl of SysPLL_inferred is
signal divider : std_logic_vector(1 downto 0);
begin
CLK_OUT1 <= CLK_IN1_P;
CLK_OUT2 <= divider(1);
LOCKED <= not RESET;
regs : process(CLK_IN1_P, RESET)
begin
if RESET = '1' then
divider <= (others => '0');
elsif rising_edge(CLK_IN1_P) then
divider <= divider + 1;
end if;
end process;
end rtl;
| bsd-2-clause | 6f9613e6ec161272cf9235f085257dfc | 0.534324 | 3.728232 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/types_rocket.vhd | 1 | 24,727 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief System Top level modules and interconnect declarations.
-----------------------------------------------------------------------------
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
--! @brief Declaration of components visible on SoC top level.
package types_rocket is
--! @name Scala inherited constants.
--! @brief The following constants were define in Rocket-chip generator.
--! @{
--! @brief Bits allocated for the memory tag value.
--! @details This value is defined \i Config.scala and depends of others
--! configuration paramters, like number of master, clients, channels
--! and so on. It is not used in VHDL implemenation.
constant MEM_TAG_BITS : integer := 6;
--! @brief SCALA generated value. Not used in VHDL.
constant MEM_ADDR_BITS : integer := 26;
--! @brief Multiplexing HTIF bus data width.
--! @details Not used in a case of disabled L2 cache.
--! If L2 cached is enabled this value defines bitwise of the bus
--! between \i Uncore module and external transievers.
--! Standard message size for the HTID request is 128 bits, so this
--! value defines number of beats required to transmit/recieve such
--! message.
constant HTIF_WIDTH : integer := 16;
--! @}
--! @name HostIO modules unique IDs.
--! @{
--! Interrupt controller
constant CFG_HTIF_SRC_IRQCTRL : integer := 0;
--! Debug Support Unit (DSU)
constant CFG_HTIF_SRC_DSU : integer := CFG_HTIF_SRC_IRQCTRL + 1;
--! Total number of HostIO initiators.
constant CFG_HTIF_SRC_TOTAL : integer := CFG_HTIF_SRC_DSU + 1;
--! @}
--! @name Memory Transaction types.
--! @details TileLinkIO interface uses these constant to identify the payload
--! size of the transaction.
--! @{
constant MT_B : integer := 0; --! int8_t Memory Transaction.
constant MT_H : integer := 1; --! int16_t Memory Transaction.
constant MT_W : integer := 2; --! int32_t Memory Transaction.
constant MT_D : integer := 3; --! int64_t Memory Transaction.
constant MT_BU : integer := 4; --! uint8_t Memory Transaction.
constant MT_HU : integer := 5; --! uint16_t Memory Transaction.
constant MT_WU : integer := 6; --! uint32_t Memory Transaction.
constant MT_Q : integer := 7; --! AXI data-width Memory Transaction (default 128-bits).
--! @}
--! @brief Memory operation types
--! @details The union bits [5:1] contains information about current transaction
constant M_XRD : std_logic_vector(4 downto 0) := "00000"; --! int load
constant M_XWR : std_logic_vector(4 downto 0) := "00001"; --! int store
constant M_PFR : std_logic_vector(4 downto 0) := "00010"; --! prefetch with intent to read
constant M_PFW : std_logic_vector(4 downto 0) := "00011"; --! prefetch with intent to write
constant M_XA_SWAP : std_logic_vector(4 downto 0) := "00100";
constant M_NOP : std_logic_vector(4 downto 0) := "00101";
constant M_XLR : std_logic_vector(4 downto 0) := "00110";
constant M_XSC : std_logic_vector(4 downto 0) := "00111";
constant M_XA_ADD : std_logic_vector(4 downto 0) := "01000";
constant M_XA_XOR : std_logic_vector(4 downto 0) := "01001";
constant M_XA_OR : std_logic_vector(4 downto 0) := "01010";
constant M_XA_AND : std_logic_vector(4 downto 0) := "01011";
constant M_XA_MIN : std_logic_vector(4 downto 0) := "01100";
constant M_XA_MAX : std_logic_vector(4 downto 0) := "01101";
constant M_XA_MINU : std_logic_vector(4 downto 0) := "01110";
constant M_XA_MAXU : std_logic_vector(4 downto 0) := "01111";
constant M_FLUSH : std_logic_vector(4 downto 0) := "10000"; --! write back dirty data and cede R/W permissions
constant M_PRODUCE : std_logic_vector(4 downto 0) := "10001"; --! write back dirty data and cede W permissions
constant M_CLEAN : std_logic_vector(4 downto 0) := "10011"; --! write back dirty data and retain R/W permissions
function isAMO(cmd : std_logic_vector(4 downto 0)) return std_logic;
--def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
--def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
function isWrite(cmd : std_logic_vector(4 downto 0)) return std_logic;
--def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
--! <tilelink.scala> Object Acquire {}
constant ACQUIRE_GET_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "000";
constant ACQUIRE_GET_BLOCK_DATA : std_logic_vector(2 downto 0) := "001"; --
constant ACQUIRE_PUT_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "010"; -- Single beat data.
constant ACQUIRE_PUT_BLOCK_DATA : std_logic_vector(2 downto 0) := "011"; -- For acMultibeat data.
constant ACQUIRE_PUT_ATOMIC_DATA : std_logic_vector(2 downto 0) := "100"; -- Single beat data. 64 bits width
constant ACQUIRE_PREFETCH_BLOCK : std_logic_vector(2 downto 0) := "101";
--! <tilelink.scala> Object Grant {}
constant GRANT_ACK_RELEASE : std_logic_vector(3 downto 0) := "0000"; -- For acking Releases
constant GRANT_ACK_PREFETCH : std_logic_vector(3 downto 0) := "0001"; -- For acking any kind of Prefetch
constant GRANT_ACK_NON_PREFETCH_PUT : std_logic_vector(3 downto 0) := "0011"; -- For acking any kind of non-prfetch Put
constant GRANT_SINGLE_BEAT_GET : std_logic_vector(3 downto 0) := "0100"; -- Supplying a single beat of Get
constant GRANT_BLOCK_GET : std_logic_vector(3 downto 0) := "0101"; -- Supplying all beats of a GetBlock
--! MESI coherence
constant CACHED_ACQUIRE_SHARED : std_logic_vector(2 downto 0) := "000"; -- get
constant CACHED_ACQUIRE_EXCLUSIVE : std_logic_vector(2 downto 0) := "001"; -- put
constant CACHED_GRANT_SHARED : std_logic_vector(3 downto 0) := "0000";
constant CACHED_GRANT_EXCLUSIVE : std_logic_vector(3 downto 0) := "0001";
constant CACHED_GRANT_EXCLUSIVE_ACK : std_logic_vector(3 downto 0) := "0010";
--! @brief Memory Operation size decoder
--! @details TileLink bus has encoded Memory Operation size
--! in the union[8:6] bits of the acquire request.
constant MEMOP_XSIZE_TOTAL : integer := 8;
type memop_xsize_type is array (0 to MEMOP_XSIZE_TOTAL-1) of std_logic_vector(2 downto 0);
constant opSizeToXSize : memop_xsize_type := (
MT_B => "000",
MT_BU => "000",
MT_H => "001",
MT_HU => "001",
MT_W => "010",
MT_WU => "010", --! unimplemented in scala
MT_D => "011",
MT_Q => conv_std_logic_vector(log2(CFG_NASTI_DATA_BYTES),3)
);
type tile_cached_in_type is record
acquire_ready : std_logic;
grant_valid : std_logic;
grant_bits_addr_beat : std_logic_vector(1 downto 0);
--! client's transaction id
grant_bits_client_xact_id : std_logic_vector(1 downto 0);
grant_bits_manager_xact_id : std_logic_vector(3 downto 0);
grant_bits_is_builtin_type : std_logic;
grant_bits_g_type : std_logic_vector(3 downto 0);
grant_bits_data : std_logic_vector(127 downto 0);
probe_valid : std_logic;
probe_bits_addr_block : std_logic_vector(25 downto 0);
probe_bits_p_type : std_logic_vector(1 downto 0);
release_ready : std_logic;
end record;
type tile_cached_out_type is record
acquire_valid : std_logic;
acquire_bits_addr_block : std_logic_vector(25 downto 0);
acquire_bits_client_xact_id : std_logic_vector(1 downto 0);
acquire_bits_addr_beat : std_logic_vector(1 downto 0);
acquire_bits_is_builtin_type : std_logic;
acquire_bits_a_type : std_logic_vector(2 downto 0);
acquire_bits_union : std_logic_vector(16 downto 0);
acquire_bits_data : std_logic_vector(127 downto 0);
grant_ready : std_logic;
probe_ready : std_logic;
release_valid : std_logic;
release_bits_addr_beat : std_logic_vector(1 downto 0);
release_bits_addr_block : std_logic_vector(25 downto 0);
release_bits_client_xact_id : std_logic_vector(1 downto 0);
release_bits_r_type : std_logic_vector(2 downto 0);
release_bits_voluntary : std_logic;
release_bits_data : std_logic_vector(127 downto 0);
end record;
--! HostIO tile input signals
type host_in_type is record
grant : std_logic_vector(CFG_HTIF_SRC_TOTAL-1 downto 0);
csr_req_ready : std_logic;
csr_resp_valid : std_logic;
csr_resp_bits : std_logic_vector(63 downto 0);
debug_stats_csr : std_logic;
end record;
--! HostIO tile output signals
type host_out_type is record
reset : std_logic;
id : std_logic;
csr_req_valid : std_logic;
csr_req_bits_rw : std_logic;
csr_req_bits_addr : std_logic_vector(11 downto 0);
csr_req_bits_data : std_logic_vector(63 downto 0);
csr_resp_ready : std_logic;
end record;
--! Full stack of HostIO output signals from all devices.
type host_out_vector is array (0 to CFG_HTIF_SRC_TOTAL-1)
of host_out_type;
--! @brief Empty output signals of HostIO interface.
--! @details If device was included in the owners of the HostIO interface and
--! was disabled by configuration parameter (for example) then its
--! outputs must be assigned to this empty signals otherwise
--! RTL simulation will fail with undefined states of the processor.
constant host_out_none : host_out_type := (
'0', '0', '0', '0', (others => '0'), (others => '0'), '0');
--! @brief Decode Acquire request from the Cached/Uncached TileLink
--! @param[in] a_type Request type depends of the built_in flag
--! @param[in] built_in This flag defines cached or uncached request. For
--! the uncached this value is set to 1.
--! @param[in] u Union bits. This value is decoding depending of
--! types operation (rd/wr) and cached/uncached.
procedure procedureDecodeTileAcquire (
a_type : in std_logic_vector(2 downto 0);
built_in : in std_logic;
u : in std_logic_vector(16 downto 0);
write : out std_logic;
wmask : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
axi_sz : out std_logic_vector(2 downto 0);
byte_addr : out std_logic_vector(3 downto 0);
beat_cnt : out integer
);
--! @brief HostIO (HTIF) controller declaration.
--! @details This device provides multiplexing of the Host messages
--! from several sources (interrupt controller, ethernet MAC,
--! Debug Support Unit and others) on HostIO bus that is
--! specific for Rocket-chip implementation of RISC-V.
--! @todo Make htifii as a vector to support multi-cores
--! configuration.
component htifctrl is
port (
clk : in std_logic;
nrst : in std_logic;
srcsi : in host_out_vector;
srcso : out host_out_type;
htifii : in host_in_type;
htifio : out host_in_type
);
end component;
--! @brief HTIF serializer input.
--! @details In a case of using L2-cache, 'Uncore' module implements
--! additional layer of the transformation of 128-bits HTIF
--! messages into chunks of HTIF_WIDTH. So we have to
--! implement the same serdes on upper level.
type htif_serdes_in_type is record
--! Chunk was accepted by Uncore subsytem.
ready : std_logic;
--! Current chunk output is valid
valid : std_logic;
--! Chunk bits itself.
bits : std_logic_vector(HTIF_WIDTH-1 downto 0);
end record;
--! @brief HTIF serializer output.
type htif_serdes_out_type is record
valid : std_logic;
bits : std_logic_vector(HTIF_WIDTH-1 downto 0);
ready : std_logic;
end record;
--! @brief RocketTile component declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uncached Tile AXI master index
--! @param[in] rst Reset signal with active HIGH level.
--! @param[in] soft_rst Software Reset via DSU
--! @param[in] clk_sys System clock (BUS/CPU clock).
--! @param[in] slvo Bus-to-Slave device signals.
--! @param[in] msti Bus-to-Master device signals.
--! @param[out] msto1 CachedTile-to-Bus request signals.
--! @param[out] msto2 UncachedTile-to-Bus request signals.
--! @param[in] htifoi Requests from the HostIO-connected devices.
--! @param[out] htifio Response to HostIO-connected devices.
component rocket_l1only is
generic (
xindex1 : integer := 0;
xindex2 : integer := 1
);
port (
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
end component;
--! @brief RocketTile + Uncore component declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uncached Tile AXI master index
--! @param[in] rst Reset signal with active HIGH level.
--! @param[in] soft_rst Software Reset via DSU
--! @param[in] clk_sys System clock (BUS/CPU clock).
--! @param[in] slvo Bus-to-Slave device signals.
--! @param[in] msti Bus-to-Master device signals.
--! @param[out] msto1 CachedTile-to-Bus request signals.
--! @param[out] msto2 UncachedTile-to-Bus request signals.
--! @param[in] htifoi Requests from the HostIO-connected devices.
--! @param[out] htifio Response to HostIO-connected devices.
component rocket_l2cache is
generic (
xindex1 : integer := 0;
xindex2 : integer := 1
);
port (
rst : in std_logic;
soft_rst : in std_logic;
clk_sys : in std_logic;
slvo : in nasti_slave_in_type;
msti : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
htifoi : in host_out_type;
htifio : out host_in_type
);
end component;
--! @brief SOC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[in] inPllLock PLL status.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
component reset_global
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
inPllLock : in std_ulogic;
outReset : out std_ulogic );
end component;
--! Boot ROM with AXI4 interface declaration.
component nasti_bootrom is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
--! AXI4 ROM with the default FW version declaration.
component nasti_romimage is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
--! Internal RAM with AXI4 interface declaration.
component nasti_sram is
generic (
memtech : integer := inferred;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for 'inferred'
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
--! @brief NASTI (AXI4) GPIO controller
component nasti_gpio is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type;
i_dip : in std_logic_vector(3 downto 0);
o_led : out std_logic_vector(7 downto 0)
);
end component;
type uart_in_type is record
rd : std_ulogic;
cts : std_ulogic;
end record;
type uart_out_type is record
td : std_ulogic;
rts : std_ulogic;
end record;
--! UART with the AXI4 interface declaration.
component nasti_uart is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
o_irq : out std_logic);
end component;
--! @brief Interrupt controller with the AXI4 interface declaration.
--! @details To rise interrupt on certain CPU HostIO interface is used.
component nasti_irqctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type
);
end component;
--! @brief Declaration of the Debug Support Unit with the AXI interface.
--! @details This module provides access to processors CSRs via HostIO bus.
component nasti_dsu is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type;
o_soft_reset : out std_logic
);
end component;
--! @brief General Purpose Timers with the AXI interface.
--! @details This module provides high precision counter and
--! generic number of GP timers.
component nasti_gptimers is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
o_irq : out std_logic
);
end component;
--! @brief Plug-n-Play support module with AXI4 interface declaration.
--! @details Each device in a system hase to implements sideband signal
--! structure 'nasti_slave_config_type' that allows FW to
--! detect Hardware configuration in a run-time.
--! @todo Implements PnP signals for all Masters devices.
component nasti_pnp is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in nasti_master_cfg_vector;
slvcfg : in nasti_slave_cfg_vector;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type
);
end component;
end; -- package declaration
--! -----------------
package body types_rocket is
function isAMO(cmd : std_logic_vector(4 downto 0))
return std_logic is
variable t1 : std_logic;
begin
t1 := '0';
if cmd = M_XA_SWAP then
t1 := '1';
end if;
return (cmd(3) or t1);
end;
function isWrite(cmd : std_logic_vector(4 downto 0))
return std_logic is
variable ret : std_logic;
begin
ret := isAMO(cmd);
if cmd = M_XWR then ret := '1'; end if;
if cmd = M_XSC then ret := '1'; end if;
return (ret);
end;
--! @brief Decode Acquire request from the Cached/Uncached TileLink
--! @param[in] a_type Request type depends of the built_in flag
--! @param[in] built_in This flag defines cached or uncached request. For
--! the uncached this value is set to 1.
--! @param[in] u Union bits. This value is decoding depending of
--! types operation (rd/wr) and cached/uncached.
procedure procedureDecodeTileAcquire(
a_type : in std_logic_vector(2 downto 0);
built_in : in std_logic;
u : in std_logic_vector(16 downto 0);
write : out std_logic;
wmask : out std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
axi_sz : out std_logic_vector(2 downto 0);
byte_addr : out std_logic_vector(3 downto 0);
beat_cnt : out integer
) is
begin
if built_in = '1' then
-- Cached request
case a_type is
when ACQUIRE_GET_SINGLE_DATA_BEAT =>
write := '0';
wmask := (others => '0');
byte_addr := u(12 downto 9);--tst.block.byte_addr;
axi_sz := opSizeToXSize(conv_integer(u(8 downto 6)));
beat_cnt := 0;
when ACQUIRE_PREFETCH_BLOCK |
ACQUIRE_GET_BLOCK_DATA =>
-- cache line size / data bits width
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 3;--tlDataBeats-1;
when ACQUIRE_PUT_SINGLE_DATA_BEAT =>
-- Single beat data.
write := '1';
wmask := u(CFG_NASTI_DATA_BYTES downto 1);
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 0;
when ACQUIRE_PUT_BLOCK_DATA =>
-- Multibeat data.
write := '1';
wmask := (others => '1');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 3;--tlDataBeats-1;
when ACQUIRE_PUT_ATOMIC_DATA =>
-- Single beat data. 64 bits width
write := '1';
if CFG_NASTI_DATA_BITS = 128 then
if u(12) = '0' then
wmask(7 downto 0) := (others => '1');
wmask(15 downto 8) := (others => '0');
else
wmask(7 downto 0) := (others => '0');
wmask(15 downto 8) := (others => '1');
end if;
else
wmask := (others => '1');
end if;
byte_addr := (others => '0');
axi_sz := opSizeToXSize(conv_integer(u(8 downto 6)));
beat_cnt := 0;
when others =>
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := (others => '0');
beat_cnt := 0;
end case;
else --! built_in = '0'
-- Cached request
case a_type is
when CACHED_ACQUIRE_SHARED =>
write := '0';
wmask := (others => '0');
byte_addr := u(12 downto 9);--tst.block.byte_addr;
axi_sz := opSizeToXSize(conv_integer(u(8 downto 6)));
beat_cnt := 0;
when CACHED_ACQUIRE_EXCLUSIVE =>
-- Single beat data.
write := '1';
wmask := u(CFG_NASTI_DATA_BYTES downto 1);
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_NASTI_ADDR_OFFSET,3);
beat_cnt := 0;
when others =>
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := (others => '0');
beat_cnt := 0;
end case;
end if;
end procedure;
end; -- package body
| bsd-2-clause | f81178f4bc5b03d89dde2c8c39cd01b8 | 0.615764 | 3.495971 | false | false | false | false |
eiglss/VHDL | UART/txControler.vhd | 1 | 2,096 | --******************************************************************************
-- @TITRE : txControler.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY WORK;
USE WORK.uart_pkg.ALL;
ENTITY txControler IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
datReady : IN STD_LOGIC;
tick : IN STD_LOGIC;
count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
shEn : OUT STD_LOGIC;
ldEn : OUT STD_LOGIC;
txBusy : OUT STD_LOGIC
);
END ENTITY txControler;
ARCHITECTURE mealy OF txControler IS
TYPE state_t IS (idle, send);
SIGNAL state : state_t;
BEGIN
Transition : PROCESS(clk, aNRst) IS
BEGIN
IF aNRst = '0' THEN
state <= idle;
ELSIF RISING_EDGE(clk) THEN
CASE state IS
WHEN idle =>
IF datReady = '1' THEN
state <= send;
END IF;
WHEN send =>
IF tick = '1' AND UNSIGNED(count) >= (dataLength+0+stop) AND parity = N THEN
state <= idle;
ELSIF tick = '1' AND UNSIGNED(count) >= (dataLength+1+stop) AND parity /= N THEN
state <= idle;
END IF;
END CASE;
END IF;
END PROCESS Transition;
shEn <= '1' WHEN state = send AND tick = '1' ELSE
'0';
ldEn <= '1' WHEN state = idle AND datReady = '1' ELSE
'0';
txBusy <= '1' WHEN state = send ELSE
'0';
END ARCHITECTURE mealy;
| mit | 664e61c69bb12720d1e8423958afcfac | 0.445134 | 4.225806 | false | false | false | false |
eiglss/VHDL | UART/uart.vhd | 1 | 6,746 | --******************************************************************************
-- @TITRE : uart.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_pkg.ALL;
ENTITY uart IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
tick : IN STD_LOGIC;
-- tx
txDatReady : IN STD_LOGIC;
datIn : IN STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0);
txBusy : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
-- rx
rx : IN STD_LOGIC;
rxDatReady : OUT STD_LOGIC;
rxBusy : OUT STD_LOGIC;
datOut : OUT STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0)
);
END uart;
ARCHITECTURE Structural OF uart IS
-- TX
SIGNAL iCountTx : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL iTxShEn : STD_LOGIC;
SIGNAL iTxLdEn : STD_LOGIC;
SIGNAL iDataTx : STD_LOGIC_VECTOR(sel(parity = N, 1+dataLength+stop, 1+dataLength+1+stop)-1 DOWNTO 0);
SIGNAL iTx : STD_LOGIC;
SIGNAL iTxBusy : STD_LOGIC;
-- RX
SIGNAL iRxStart : STD_LOGIC;
SIGNAL iRxBusy : STD_LOGIC;
SIGNAL iCountRx : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL iRxShEn : STD_LOGIC;
SIGNAL iRxDatOut : STD_LOGIC_VECTOR(sel(parity = N, dataLength+stop, dataLength+1+stop)-1 DOWNTO 0);
SIGNAL iRxDatReady : STD_LOGIC;
BEGIN
-- TX
tx <= '1' WHEN iTxBusy = '0' OR aNRst = '0' ELSE
iTx;
txBusy <= iTxBusy;
dataTxN1_gen : IF parity = N AND stop = 1 GENERATE
BEGIN
iDataTx <= "1"&datIN&"0";
END GENERATE;
dataTxN2_gen : IF parity = N AND stop = 2 GENERATE
BEGIN
iDataTx <= "11"&datIN&"0";
END GENERATE;
dataTxOE1_gen : IF NOT(parity = N) AND stop = 1 GENERATE
iDataTx <= "1"&TO_STDLOGICVECTOR(getParity(datIn, parity = E))&datIN&"0";
END GENERATE;
dataTxOE2_gen : IF NOT(parity = N) AND stop = 2 GENERATE
iDataTx <= "11"&TO_STDLOGICVECTOR(getParity(datIn, parity = E))&datIN&"0";
END GENERATE;
txControler_ci : txControler
GENERIC MAP(dataLength => dataLength,
parity => parity,
stop => stop
)
PORT MAP(clk => clk,
aNRst => aNRst,
datReady => txDatReady,
tick => tick,
count => iCountTx,
shEn => iTxShEn,
ldEn => iTxLdEn,
txBusy => iTxBusy
);
txCounter_ci : counter
GENERIC MAP(length => 4
)
PORT MAP(clk => clk,
aNRst => aNRst,
rst => iTxLdEn,
en => iTxShEn,
incNotDec => '1',
load => '0',
dIn => (OTHERS => '0'),
dOut => iCountTx
);
txShiftReg_ci : shiftRegister
GENERIC MAP(length => sel(parity = N, 1+dataLength+stop,1+dataLength+1+stop),
rightNotLeft => TRUE
)
PORT MAP(clk => clk,
aNRst => aNRst,
shEn => iTxShEn,
ldEn => iTxLdEn,
serialIn => '0',
datIn => iDataTx,
datOut => OPEN,
serialOut => iTx
);
-- RX
iRxStart <= '1' WHEN rx = '0' AND iRxBusy = '0' ELSE
'0';
rxBusy <= iRxBusy;
rxControler_ci : rxControler
GENERIC MAP(dataLength => dataLength,
parity => parity,
stop => stop
)
PORT MAP(clk => clk,
aNRst => aNRst,
start => iRxStart,
tick => tick,
count => iCountRx,
shEn => iRxShEn,
rxBusy => iRxBusy,
dataReady => iRxDatReady
);
rxCounter_ci : counter
GENERIC MAP(length => 4
)
PORT MAP(clk => clk,
aNRst => aNRst,
rst => iRxStart,
en => iRxShEn,
incNotDec => '1',
load => '0',
dIn => (OTHERS => '0'),
dOut => iCountRx
);
rxShiftReg_ci : shiftRegister
GENERIC MAP(length => sel(parity = N, dataLength+stop,dataLength+1+stop),
rightNotLeft => TRUE
)
PORT MAP(clk => clk,
aNRst => aNRst,
shEn => iRxShEn,
ldEn => iRxStart,
serialIn => rx,
datIn => (OTHERS => '0'),
datOut => iRxDatOut,
serialOut => open
);
datOut <= iRxDatOut(dataLength-1 DOWNTO 0);
datReadyRxN1_gen : IF parity = N AND stop = 1 GENERATE
BEGIN
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength) = '1' ELSE
'0';
END GENERATE;
datReadyExN2_gen : IF parity = N AND stop = 2 GENERATE
BEGIN
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1 DOWNTO dataLength) = "11" ELSE
'0';
END GENERATE;
datReadyRxOE1_gen : IF NOT(parity = N) AND stop = 1 GENERATE
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1) = '1' AND iRxDatOut(dataLength DOWNTO dataLength) = TO_STDLOGICVECTOR(getParity(datIn, parity = E)) ELSE
'0';
END GENERATE;
datReadyRxOE2_gen : IF NOT(parity = N) AND stop = 2 GENERATE
rxDatReady <= iRxDatReady WHEN iRxDatOut(dataLength+1 DOWNTO dataLength) = "11" AND iRxDatOut(dataLength DOWNTO dataLength) = TO_STDLOGICVECTOR(getParity(datIn, parity = E)) ELSE
'0';
END GENERATE;
END Structural;
| mit | 7c812f1148fadff48504f102d599e55a | 0.442484 | 4.476443 | false | false | false | false |
aysteph3/MiniMIPS_Testing | src/alu.vhd | 1 | 9,981 | ------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation; either version 2 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- miniMIPS Processor : Arithmetical and logical unit --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pack_mips.all;
entity alu is
port
(
clock : in bus1;
reset : in bus1;
op1 : in bus32; -- Operand 1
op2 : in bus32; -- Operand 2
ctrl : in alu_ctrl_type; -- Opearator control
res : out bus32; -- The result is 32 bit long
overflow : out bus1 -- Overflow of the result
);
end alu;
architecture rtl of alu is
-- Signals to pre-process the operands
signal efct_op1, efct_op2 : bus33; -- Effective operands of the adder (33 bits)
signal comp_op2 : bus1; -- Select the opposite of operand 2
signal igno_op2 : bus1; -- Ignore op 2 (put zeros)
signal sign_op1 : bus1; -- High bit of op 1
signal sign_op2 : bus1; -- High bit of op 2
signal signe : bus1; -- Signed operation (bit sign extension)
signal shift_val : natural range 0 to 31; -- Value of the shift
-- Signals for internal results
signal res_shl, res_shr : bus32; -- Results of left and right shifter
signal res_lui : bus32; -- Result of Load Upper Immediate
signal res_add : bus33; -- Result of the adder
signal carry : bus33; -- Carry for the adder
signal nul : bus1; -- Check if the adder result is zero
signal hilo : bus64; -- Internal registers to store the multiplication operation
signal tmp_hilo : bus64; -- Internal registers to store the multiplication operation (synchronised)
begin
-- Process if the operation is signed compliant
signe <= '1' when (ctrl=OP_ADD or ctrl=OP_SUB or ctrl=OP_SLT or ctrl=OP_SNEG or ctrl=OP_SPOS or ctrl=OP_LNEG or ctrl=OP_LPOS)
else
'0';
sign_op1 <= signe and op1(31);
sign_op2 <= signe and op2(31);
-- Selection of the value of the second operand : op2 or -op2 (ie not op2 + 1)
comp_op2 <= '1' when -- The opposite of op2 is used
(ctrl=OP_SUB or ctrl=OP_SUBU) -- Opposite of the operand 2 to obtain a substraction
or (ctrl=OP_SLT or ctrl=OP_SLTU) -- Process the difference to check the lesser than operation for the operands
or (ctrl=OP_EQU or ctrl=OP_NEQU) -- Process the difference to check the equality of the operands
else
'0'; -- by default, op2 is used
igno_op2 <= '1' when -- Op 2 will be zero (when comp_op2='0')
(ctrl=OP_SPOS or ctrl=OP_LNEG) -- Process if the op1 is nul with op1+0
else
'0';
-- Effective signals for the adder
efct_op2 <= not (sign_op2 & op2) when (comp_op2='1') else -- We take the opposite of op2 to get -op2 (we will add 1 with the carry)
(others => '0') when (igno_op2='1') else -- Op2 is zero
(sign_op2 & op2); -- by default we use op2 (33 bits long)
efct_op1 <= sign_op1 & op1;
-- Execution of the addition
carry <= X"00000000" & comp_op2; -- Carry to one when -op2 is needed
res_add <= std_logic_vector(unsigned(efct_op1) + unsigned(efct_op2) + unsigned(carry));
nul <= '1' when (res_add(31 downto 0)=X"00000000") else '0'; -- Check the nullity of the result
-- Value of the shift for the programmable shifter
shift_val <= to_integer(unsigned(op1(4 downto 0)));
res_shl <= bus32(shift_left(unsigned(op2), shift_val));
res_shr <= not bus32(shift_right(unsigned(not op2) , shift_val)) when (ctrl=OP_SRA and op2(31)='1') else
bus32(shift_right(unsigned(op2), shift_val));
res_lui <= op2(15 downto 0) & X"0000";
-- Affectation of the hilo register if necessary
tmp_hilo <= std_logic_vector(signed(op1)*signed(op2)) when (ctrl=OP_MULT) else
std_logic_vector(unsigned(op1)*unsigned(op2)) when (ctrl=OP_MULTU) else
op1 & hilo(31 downto 0) when (ctrl=OP_MTHI) else
hilo(63 downto 32) & op1 when (ctrl=OP_MTLO) else
(others => '0');
-- Check the overflows
overflow <= '1' when ((ctrl=OP_ADD and op1(31)=efct_op2(31) and op1(31)/=res_add(31))
or (ctrl=OP_SUB and op1(31)/=op2(31) and op1(31)/=res_add(31))) else
'0'; -- Only ADD and SUB can overflow
-- Result affectation
res <=
-- Arithmetical operations
res_add(31 downto 0) when (ctrl=OP_ADD or ctrl=OP_ADDU or ctrl=OP_SUB or ctrl=OP_SUBU) else
-- Logical operations
op1 and op2 when (ctrl=OP_AND) else
op1 or op2 when (ctrl=OP_OR) else
op1 nor op2 when (ctrl=OP_NOR) else
op1 xor op2 when (ctrl=OP_XOR) else
-- Different tests : the result is one when the test is succesful
(0 => res_add(32), others=>'0') when (ctrl=OP_SLTU or ctrl=OP_SLT) else
(0 => nul, others=>'0') when (ctrl=OP_EQU) else
(0 => not nul, others=>'0') when (ctrl=OP_NEQU) else
(0 => op1(31), others=>'0') when (ctrl=OP_SNEG) else
(0 => not (op1(31) or nul), others=>'0') when (ctrl=OP_SPOS) else
(0 => (op1(31) or nul), others=>'0') when (ctrl=OP_LNEG) else
(0 => not op1(31), others=>'0') when (ctrl=OP_LPOS) else
-- Shifts
res_shl when (ctrl=OP_SLL) else
res_shr when (ctrl=OP_SRL or ctrl=OP_SRA) else
res_lui when (ctrl=OP_LUI) else
-- Internal registers
hilo(63 downto 32) when (ctrl=OP_MFHI) else
hilo(31 downto 0) when (ctrl=OP_MFLO or ctrl=OP_MULT or ctrl=OP_MULTU) else
op1 when (ctrl=OP_MTHI or ctrl=OP_MTLO) else
op2 when (ctrl=OP_OP2) else
-- Always true
X"00000001" when (ctrl=OP_OUI) else
-- Unknown operation or nul result desired
(others => '0');
-- Save the hilo register
process (clock)
begin
if clock = '1' and clock'event then
if reset = '1' then
hilo <= (others => '0');
elsif (ctrl = OP_MULT) or (ctrl = OP_MULTU) or (ctrl = OP_MTLO) or (ctrl = OP_MTHI) then
hilo <= tmp_hilo;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 1fafc04c242061184970b43826a07625 | 0.444945 | 4.518334 | false | false | false | false |
jrrk2/greth_library | greth_library/gnsslib/gnssengine_stub/nasti_gnssstub.vhd | 2 | 5,266 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stub module of the real GNSS engine.
--! @details This module is used for SoC sharing and it generates 1 msec
--! interrupt. It implements AMBA AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! GNSS specific library.
library gnsslib;
use gnsslib.types_gnss.all;
entity gnssengine is
generic (
tech : integer range 0 to NTECH := 0;
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
i : in gns_in_type;
o : out gns_out_type
);
end;
architecture arch_gnssengine of gnssengine is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_ENGINE_STUB,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type bank_tmr_stub_type is record
MsCnt : std_logic_vector(31 downto 0); --!
TOW : std_logic_vector(31 downto 0); --!
TOD : std_logic_vector(31 downto 0); --!
end record;
type adc_bank_type is record
tmr : bank_tmr_stub_type;
clk_cnt : integer; --!
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank_adc : adc_bank_type;
--! Registers clocked by system bus
MsLength : std_logic_vector(31 downto 0); --!
CarrierNcoTh : std_logic_vector(31 downto 0); --!
CarrierNcoIF : std_logic_vector(31 downto 0); --!
end record;
signal r, rin : registers;
begin
comblogic : process(i, r)
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable rise_irq : std_logic;
begin
v := r;
rise_irq := '0';
if conv_integer(r.MsLength) /= 0 then
if (r.bank_adc.clk_cnt + 1) = conv_integer(r.MsLength) then
v.bank_adc.clk_cnt := 0;
rise_irq := '1';
v.bank_adc.tmr.MsCnt := r.bank_adc.tmr.MsCnt + 1;
else
v.bank_adc.clk_cnt := r.bank_adc.clk_cnt + 1;
end if;
end if;
procedureAxi4(i.axi, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
--! Misc. bank (stub):
when 0 => tmp := X"B00BCAFE"; --! hwid of the stub
when 1 => tmp := X"00000021"; --! gnss channels configuration stub
when 2 => tmp := r.CarrierNcoTh; --!
when 3 => tmp := r.CarrierNcoIF; --!
--! Global Timers bank (stub):
when 16#10# => tmp := r.MsLength;
when 16#11# => tmp := r.bank_adc.tmr.MsCnt;
when 16#12# => tmp := r.bank_adc.tmr.TOW;
when 16#13# => tmp := r.bank_adc.tmr.TOD;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i.axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i.axi.w_data(32*(n+1)-1 downto 32*n);
wstrb := i.axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 2 => v.CarrierNcoTh := tmp;
when 3 => v.CarrierNcoIF := tmp;
when 16#10# => v.MsLength := tmp;
when others =>
end case;
end if;
end loop;
end if;
o.ms_pulse <= rise_irq;
o.pps <= '0';
o.axi <= functionAxi4Output(r.bank_axi, rdata);
rin <= v;
end process;
o.cfg <= xconfig;
-- registers:
regadc : process(i.clk_adc, i.nrst)
begin
if i.nrst = '0' then
r.bank_adc.tmr.MsCnt <= (others => '0');
r.bank_adc.clk_cnt <= 15000;
elsif rising_edge(i.clk_adc) then
r.bank_adc <= rin.bank_adc;
end if;
end process;
regs : process(i.clk_bus, i.nrst)
begin
if i.nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
r.MsLength <= (others => '0');
elsif rising_edge(i.clk_bus) then
r.bank_axi <= rin.bank_axi;
r.MsLength <= rin.MsLength;
end if;
end process;
end;
| bsd-2-clause | a28fd3d601d98e118eecd67ecfe46b43 | 0.565894 | 3.337136 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/PROFI_9P6_50MHZ_REC_BYTE/CTRL_TELEGRAM_CHECK.vhd | 2 | 17,718 | -- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 08.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
BYTE_NUM : in std_logic_vector (7 downto 0); --Eingangsvariable, Bytenummer, 8bit
NEXT_TELEGRAM : in std_logic; --Eingangsvariable, naechstes Telegramm
TELEGRAM_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegrammlaenge, 8bit
TELEGRAM_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegrammtyp, 4bit
TELEGRAM_CMPLT : out std_logic; --Ausgangsvariable, Telegramm komplett
-- DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
-- DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
-- DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
-- DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
-- DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11,
ST_TC_12,
ST_TC_13);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal TELE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit
signal n_TELE_COUNT : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal TELE_COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal TELEGRAM_LE : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit
signal n_TELEGRAM_LE : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal TELEGRAM_LE_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal TELEGRAM_LEr : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit
signal n_TELEGRAM_LEr : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal TELEGRAM_LEr_M : std_logic_vector (7 downto 0); -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal BYTE_IN_S : std_logic_vector (7 downto 0); --Eingangsvariable, 8bit, zwischengespeichert im Eingangsregister
signal BYTE_NUM_S : std_logic_vector (7 downto 0); --Eingangsvariable, 8bit, zwischengespeichert im Eingangsregister
signal NEXT_TELEGRAM_S : std_logic; --Eingangsvariable, zwischengespeichert im Eingangsregister
Signal FIRST_4_BITS : std_logic_vector (3 downto 0); -- Zwischenspeicher der ersten 4 bit von BYTE_IN_S
--signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand, Anzeige, in 8 Bit, binär
--signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand, Anzeige, in 8 Bit, binär
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then BYTE_IN_S <= BYTE_IN;
BYTE_NUM_S <= BYTE_NUM;
NEXT_TELEGRAM_S <= NEXT_TELEGRAM;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
TELE_COUNT_M <= n_TELE_COUNT;
TELEGRAM_LE_M <= n_TELEGRAM_LE;
TELEGRAM_LEr_M <= n_TELEGRAM_LEr;
else SV_M <= SV_M;
TELE_COUNT_M <= TELE_COUNT_M;
TELEGRAM_LE_M <= TELEGRAM_LE_M;
TELEGRAM_LEr_M <= TELEGRAM_LEr_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TC_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
TELE_COUNT <= TELE_COUNT_M;
TELEGRAM_LE <= TELEGRAM_LE_M;
TELEGRAM_LEr <= TELEGRAM_LEr_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC:process (BYTE_IN_S, BYTE_NUM_S, NEXT_TELEGRAM_S, SV, TELE_COUNT, FIRST_4_BITS, TELEGRAM_LE, TELEGRAM_LEr) --Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
begin
case SV is
when ST_TC_00 =>
if (NEXT_TELEGRAM_S = '1')
then
-- TC01
n_TELE_COUNT <= x"00"; --Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0'; -- Null (bin)
n_SV <= ST_TC_01; -- Zustandsuebergang
else
-- TC00
n_TELE_COUNT <= x"00"; --Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0'; -- Null (bin)
n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand
end if;
when ST_TC_01 =>
if (BYTE_NUM_S = x"01") -- Eins
then
-- TC01
n_TELE_COUNT <= x"00"; --Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_02; -- Zustandsuebergang
else
-- TC01
n_TELE_COUNT <= x"00"; --Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_01; -- bleibt im aktuellen Zustand
end if;
when ST_TC_02 =>
if (FIRST_4_BITS = "0001") -- SD1
then
-- TC02
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0001"; -- Eins fur SD1
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_03; -- Zustandsuebergang
else
-- TC01
n_TELE_COUNT <= TELE_COUNT; --bleibt gleich
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_04; -- Zustandsuebergang
end if;
when ST_TC_03 =>
if (BYTE_NUM_S = x"06") -- 6 Byte Laenge
then
-- TC04
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0001"; -- Eins fur SD1
TELEGRAM_CMPLT <= '1'; -- komplett
n_SV <= ST_TC_00; -- Zustandsuebergang
else
-- TC03
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= TELE_COUNT; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0001"; -- Eins fur SD1
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_03; -- bleibt im aktuellen Zustand
end if;
when ST_TC_04 =>
if (FIRST_4_BITS = "1010") -- SD3
then
-- TC05
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0011"; -- 3 fuer SD3
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_05; -- Zustandsuebergang
else
-- TC01
n_TELE_COUNT <= TELE_COUNT; -- bleibt gleich
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_06; -- Zustandsuebergang
end if;
when ST_TC_05 =>
if (BYTE_NUM_S = x"07") -- 7 Byte Laenge
then
-- TC07
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0011"; -- 3 fuer SD3
TELEGRAM_CMPLT <= '1'; -- komplett
n_SV <= ST_TC_00; -- Zustandsuebergang
else
-- TC06
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= TELE_COUNT; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- 3 fuer SD3
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_05; -- bleibt im aktuellen Zustand
end if;
when ST_TC_06 =>
if (FIRST_4_BITS = "1101") -- SD4
then
-- TC08
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0100"; -- 4 fur SD4
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_07; -- Zustandsuebergang
else
-- TC01
n_TELE_COUNT <= TELE_COUNT; --bleibt gleich
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_08; -- Zustandsuebergang
end if;
when ST_TC_07 =>
if (BYTE_NUM_S = x"03") -- 3 Byte Laenge
then
-- TC10
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0100"; -- 4 fur SD4
TELEGRAM_CMPLT <= '1'; -- komplett
n_SV <= ST_TC_00; -- Zustandsuebergang
else
-- TC09
n_TELE_COUNT <= TELE_COUNT+1; -- erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0100"; -- 4 fur SD4)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_07; -- Zustandsuebergang
end if;
when ST_TC_08 =>
if (FIRST_4_BITS = "1110") -- SC
then
-- TC11
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "1000"; -- 8 fur SC
TELEGRAM_CMPLT <= '1'; -- komplett
n_SV <= ST_TC_00; -- Zustandsuebergang
else
-- TC01
n_TELE_COUNT <= TELE_COUNT; --bleibt gleich
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_09; -- Zustandsuebergang
end if;
when ST_TC_09 =>
if (FIRST_4_BITS = "0110") -- SD2
then
-- TC12
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT; -- evtl. n_TELE_COUNT hier
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_10; -- Zustandsuebergang
else
-- TC00
n_TELE_COUNT <= x"00"; -- Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_00; -- Zustandsuebergang
end if;
when ST_TC_10 =>
if (BYTE_NUM_S = x"02") -- 2. Byte
then
-- TC14
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= BYTE_IN_S;
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_11; -- Zustandsuebergang
else
-- TC13
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_10; -- bleibt im aktuellen Zustand
end if;
when ST_TC_11 =>
if (BYTE_NUM_S = x"03") -- 3. Byte
then
-- TC16
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= TELEGRAM_LE;
n_TELEGRAM_LEr <= BYTE_IN_S;
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_12; -- Zustandsuebergang
else
-- TC15
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= TELEGRAM_LE;
n_TELEGRAM_LEr <= BYTE_IN_S;
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_11; -- bleibt im aktuellen Zustand
end if;
when ST_TC_12 =>
if (TELEGRAM_LE = TELEGRAM_LEr) -- Vergleich ob Laenge uebereinstimmt
then
-- TC17
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= TELEGRAM_LE;
n_TELEGRAM_LEr <= TELEGRAM_LEr;
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_13; -- Zustandsuebergang
else
-- TC00
n_TELE_COUNT <= x"00"; --Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= TELEGRAM_LE;
n_TELEGRAM_LEr <= TELEGRAM_LEr;
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0'; -- Null (bin)
n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand
end if;
when ST_TC_13 =>
if (BYTE_NUM_S = TELEGRAM_LE) -- Wenn ermittelte Laenge eintritt
then
-- TC19
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= n_TELE_COUNT; -- n_TELE_COUNT um aktuellen Wert auszugeben da sonst eins zu niedrig
n_TELEGRAM_LE <= TELEGRAM_LE;
n_TELEGRAM_LEr <= TELEGRAM_LEr;
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '1'; -- komplett
n_SV <= ST_TC_00; -- Zustandsuebergang
else
-- TC18
n_TELE_COUNT <= TELE_COUNT+1; --erhoehen
TELEGRAM_LENGTH <= TELE_COUNT;
n_TELEGRAM_LE <= TELEGRAM_LE;
n_TELEGRAM_LEr <= TELEGRAM_LEr;
TELEGRAM_TYPE <= "0010"; -- 2 fur SD2
TELEGRAM_CMPLT <= '0';
n_SV <= ST_TC_13; -- bleibt im aktuellen Zustand
end if;
when others =>
-- TC00
n_TELE_COUNT <= x"00"; --Null (hex)
TELEGRAM_LENGTH <= x"00"; -- Null (hex)
n_TELEGRAM_LE <= x"00";
n_TELEGRAM_LEr <= x"00";
TELEGRAM_TYPE <= "0000"; -- Null (bin)
TELEGRAM_CMPLT <= '0'; -- Null (bin)
n_SV <= ST_TC_00; -- bleibt im aktuellen Zustand
end case;
end process;
BYTE_IN_8_TO_4_PROC: process (BYTE_IN_S) -- Umwandlung von BYTE_IN zu FIRST_4_BITS
begin
FIRST_4_BITS(0) <= BYTE_IN_S(0);
FIRST_4_BITS(1) <= BYTE_IN_S(1);
FIRST_4_BITS(2) <= BYTE_IN_S(2);
FIRST_4_BITS(3) <= BYTE_IN_S(3);
end process;
--STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, TELE_COUNT) -- Zustandsanzeige
-- begin
-- STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
-- STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--anktuellen Zustand anzeigen
-- DISPL1_SV(0) <= STATE_SV(0); --Bit0
-- DISPL1_SV(1) <= STATE_SV(1); --Bit1
-- DISPL1_SV(2) <= STATE_SV(2); --Bit2
-- DISPL1_SV(3) <= STATE_SV(3); --Bit3
-- DISPL2_SV(0) <= STATE_SV(4); --usw.
-- DISPL2_SV(1) <= STATE_SV(5);
-- DISPL2_SV(2) <= STATE_SV(6);
-- DISPL2_SV(3) <= STATE_SV(7);
-- if (DISPL_COUNT ='0') --Original
-- then --Folgezustand anzeigen
-- DISPL1_n_SV(0) <= STATE_n_SV(0);
-- DISPL1_n_SV(1) <= STATE_n_SV(1);
-- DISPL1_n_SV(2) <= STATE_n_SV(2);
-- DISPL1_n_SV(3) <= STATE_n_SV(3);
-- DISPL2_n_SV(0) <= STATE_n_SV(4);
-- DISPL2_n_SV(1) <= STATE_n_SV(5);
-- DISPL2_n_SV(2) <= STATE_n_SV(6);
-- DISPL2_n_SV(3) <= STATE_n_SV(7);
-- else --Telegrammzaehler anzeigen
-- DISPL1_n_SV(0) <= TELE_COUNT(0);
-- DISPL1_n_SV(1) <= TELE_COUNT(1);
-- DISPL1_n_SV(2) <= TELE_COUNT(2);
-- DISPL1_n_SV(3) <= TELE_COUNT(3);
-- DISPL2_n_SV(0) <= TELE_COUNT(4);
-- DISPL2_n_SV(1) <= TELE_COUNT(5);
-- DISPL2_n_SV(2) <= TELE_COUNT(6);
-- DISPL2_n_SV(3) <= TELE_COUNT(7);
-- end if;
-- end process;
end Behavioral;
| gpl-2.0 | 5455e072cd40d2d86b2276132d53d4f4 | 0.563156 | 3.169022 | false | false | false | false |
jrrk2/greth_library | greth_library/work/rocket_soc_nexys4.vhd | 1 | 7,644 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! DIP switch.
i_dip : in std_logic_vector(3 downto 0);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! Ethernet MAC PHY interface signals
o_erefclk : out std_ulogic; -- RMII clock out
i_gmiiclk_p : in std_ulogic; -- GMII clock in
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic;
wPllLocked : in std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
i_clk50_quad : in std_ulogic;
i_clk50 : in std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
dipx : for i in 0 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
diffclk: if CFG_RMII = 0 generate
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
end generate;
wClkBus <= i_clk50;
o_erefclk <= i_clk50_quad;
eth_i.rmii_clk <= i_clk50;
wSysReset <= i_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip,
o_led => o_led
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth0_rmii_ena1 : if CFG_RMII = 1 generate
eth_i.rx_crs <= i_erx_dv;
end generate;
eth0_rmii_ena0 : if CFG_RMII = 0 generate -- plain MII
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_crs <= i_erx_crs;
end generate;
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rxd <= i_erxd;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 50, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518,
rmii => CFG_RMII
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
end arch_rocket_soc;
| bsd-2-clause | fa97ccba13305376246663b0b8167809 | 0.60348 | 3.43705 | false | false | false | false |
eiglss/VHDL | UART/uart_pkg.vhd | 1 | 4,626 | --******************************************************************************
-- @TITRE : uart_pkg.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE uart_pkg IS
-- UART
SUBTYPE uartLength_t IS INTEGER RANGE 5 TO 9;
TYPE uartParity_t IS (N, E, O);
SUBTYPE uartStop_t IS INTEGER RANGE 1 TO 2;
FUNCTION getParity(data : IN STD_LOGIC_VECTOR; even : IN BOOLEAN) RETURN STD_LOGIC;
FUNCTION sel(cond : BOOLEAN; ifTrue, ifFalse: INTEGER) RETURN INTEGER;
FUNCTION to_stdLogicVector(i: STD_LOGIC) RETURN STD_LOGIC_VECTOR;
-- uart component
COMPONENT uart IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
tick : IN STD_LOGIC;
-- tx
txDatReady : IN STD_LOGIC;
datIn : IN STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0);
txBusy : OUT STD_LOGIC;
tx : OUT STD_LOGIC;
-- rx
rx : IN STD_LOGIC;
rxDatReady : OUT STD_LOGIC;
rxBusy : OUT STD_LOGIC;
datOut : OUT STD_LOGIC_VECTOR(dataLength-1 DOWNTO 0)
);
END COMPONENT;
-- additional component
COMPONENT txControler IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
datReady : IN STD_LOGIC;
tick : IN STD_LOGIC;
count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
shEn : OUT STD_LOGIC;
ldEn : OUT STD_LOGIC;
txBusy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT rxControler IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
start : IN STD_LOGIC;
tick : IN STD_LOGIC;
count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
shEn : OUT STD_LOGIC;
rxBusy : OUT STD_LOGIC;
dataReady : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT shiftRegister IS
GENERIC(length : POSITIVE := 8;
rightNotLeft : BOOLEAN := TRUE
);
PORT(clk, aNRst : IN STD_LOGIC;
shEn, ldEn : IN STD_LOGIC;
serialIn : IN STD_LOGIC;
datIn : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0);
datOut : OUT STD_LOGIC_VECTOR(length-1 DOWNTO 0);
serialOut : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT counter IS
GENERIC(length : POSITIVE := 8
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
en, rst, incNotDec, load : IN STD_LOGIC;
dIn : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0);
dOut : OUT STD_LOGIC_VECTOR(length-1 DOWNTO 0)
);
END COMPONENT;
END uart_pkg;
PACKAGE BODY uart_pkg IS
FUNCTION getParity(data : IN STD_LOGIC_VECTOR; even : IN BOOLEAN) RETURN STD_LOGIC IS
VARIABLE rtn : STD_LOGIC := '0';
BEGIN
FOR i IN data'RANGE LOOP
rtn := rtn XOR data(i);
END LOOP;
IF even THEN
RETURN rtn;
ELSE
RETURN NOt rtn;
END IF;
END FUNCTION;
FUNCTION sel(cond : BOOLEAN; ifTrue, ifFalse: INTEGER) RETURN INTEGER IS
BEGIN
IF cond THEN
RETURN(ifTrue);
ELSE
RETURN(ifFalse);
END IF;
END FUNCTION;
FUNCTION to_stdlogicvector(i: STD_LOGIC) RETURN STD_LOGIC_VECTOR IS
VARIABLE stdlv :STD_LOGIC_VECTOR(0 DOWNTO 0):= (0 => i);
BEGIN
RETURN stdlv;
END;
END uart_pkg;
| mit | ba7ecf6cef3be96a71a05a689749209f | 0.460009 | 4.351834 | false | false | false | false |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/CPU_FiFo_Bridge.vhd | 2 | 11,144 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CPU_FiFo_Bridge is
port (
clk : in std_logic := '0'; -- clock.clk
reset : in std_logic := '0'; -- .reset
cpu1_address : in std_logic_vector(7 downto 0) := (others => '0'); -- s0.address
cpu1_read : in std_logic := '0'; -- .read
cpu1_readdata : out std_logic_vector(31 downto 0); -- .readdata
cpu1_write : in std_logic := '0'; -- .write
cpu1_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
cpu1_irq : out std_logic; -- irq0.irq
cpu2_address : in std_logic_vector(7 downto 0) := (others => '0'); -- s1.address
cpu2_read : in std_logic := '0'; -- .read
cpu2_readdata : out std_logic_vector(31 downto 0); -- .readdata
cpu2_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
cpu2_write : in std_logic := '0'; -- .write
cpu2_irq : out std_logic -- irq1.irq
);
end entity CPU_FiFo_Bridge;
architecture rtl of CPU_FiFo_Bridge is
signal cpu1_readData_signal : std_logic_vector (31 downto 0);
signal cpu1_cpu2_fifo_clear : std_logic ;
signal cpu1_cpu2_fifo_wrreq : std_logic ;
signal cpu1_cpu2_fifo_rdreq : std_logic ;
signal cpu1_cpu2_fifo_readData : std_logic_vector (31 downto 0);
signal cpu1_cpu2_fifo_full : std_logic;
signal cpu1_cpu2_fifo_almostfull : std_logic;
signal cpu1_cpu2_fifo_almostempty : std_logic;
signal cpu1_cpu2_fifo_empty : std_logic;
signal cpu1_cpu2_fifo_count : std_logic_vector (4 downto 0);
signal cpu1_cpu2_fifo_count_out : std_logic_vector (5 downto 0);
signal cpu2_readData_signal : std_logic_vector (31 downto 0);
signal cpu2_cpu1_fifo_clear : std_logic ;
signal cpu2_cpu1_fifo_wrreq : std_logic ;
signal cpu2_cpu1_fifo_rdreq : std_logic ;
signal cpu2_cpu1_fifo_readData : std_logic_vector (31 downto 0);
signal cpu2_cpu1_fifo_full : std_logic;
signal cpu2_cpu1_fifo_almostfull : std_logic;
signal cpu2_cpu1_fifo_almostempty : std_logic;
signal cpu2_cpu1_fifo_empty : std_logic;
signal cpu2_cpu1_fifo_count : std_logic_vector (4 downto 0);
signal cpu2_cpu1_fifo_count_out : std_logic_vector (5 downto 0);
signal statusRegister : std_logic_vector (7 downto 0); -- Bit 0 ( 1 = Sende-FIFO ist leer )
-- Bit 1 ( 1 = Sende-FIFO ist fast leer )
-- Bit 2 ( 1 = Sende-FIFO ist fast voll )
-- Bit 3 ( 1 = Sende-FIFO ist voll )
-- Bit 4 ( 1 = Empfangs-FIFO ist leer )
-- Bit 5 ( 1 = Empfangs-FIFO ist fast leer )
-- Bit 6 ( 1 = Empfangs-FIFO ist fast voll )
-- Bit 7 ( 1 = Empfangs-FIFO ist voll )
signal cpu1_interruptRegister : std_logic_vector (7 downto 0); -- Bit 0 ( 1 = FiFo_cpu1_cpu2 ist fast leer )
-- Bit 1 ( 1 = FiFo_cpu2_cpu1 ist fast voll )
signal cpu1_interruptEnableRegister : std_logic_vector (7 downto 0); -- Bit 0 ( 1 = FiFo_cpu1_cpu2 ist fast leer )
-- Bit 1 ( 1 = FiFo_cpu2_cpu1 ist fast voll )
signal cpu2_interruptRegister : std_logic_vector (7 downto 0); -- Bit 0 ( 1 = FiFo_cpu2_cpu1 ist fast leer )
-- Bit 1 ( 1 = FiFo_cpu1_cpu2 ist fast voll )
signal cpu2_interruptEnableRegister : std_logic_vector (7 downto 0); -- Bit 0 ( 1 = FiFo_cpu2_cpu1 ist fast leer )
-- Bit 1 ( 1 = FiFo_cpu1_cpu2 ist fast voll )
signal fueller : std_logic_vector(23 downto 0) := "000000000000000000000000";
signal cpu1_interruptRegister_last : std_logic_vector (7 downto 0);
signal cpu2_interruptRegister_last : std_logic_vector (7 downto 0);
-- Komponentendeklaration des FiFos
component fifo is
port( clock : in std_logic ;
data : in std_logic_vector (31 DOWNTO 0);
rdreq : in std_logic ;
sclr : in std_logic ;
wrreq : in std_logic ;
almost_empty : out std_logic ;
almost_full : out std_logic ;
empty : out std_logic ;
full : out std_logic ;
q : out std_logic_vector (31 DOWNTO 0);
usedw : out std_logic_vector (4 DOWNTO 0));
end component fifo;
begin
fifo_cpu1_to_cpu2 : fifo port map (
clock => clk,
data => cpu1_writedata,
rdreq => cpu1_cpu2_fifo_rdreq,
sclr => cpu1_cpu2_fifo_clear,
wrreq => cpu1_cpu2_fifo_wrreq,
almost_empty => cpu1_cpu2_fifo_almostempty,
almost_full => cpu1_cpu2_fifo_almostfull,
empty => cpu1_cpu2_fifo_empty,
full => cpu1_cpu2_fifo_full,
q => cpu1_cpu2_fifo_readData,
usedw => cpu1_cpu2_fifo_count
);
fifo_cpu2_to_cpu1 : fifo port map (
clock => clk,
data => cpu2_writedata,
rdreq => cpu2_cpu1_fifo_rdreq,
sclr => cpu2_cpu1_fifo_clear,
wrreq => cpu2_cpu1_fifo_wrreq,
almost_empty => cpu2_cpu1_fifo_almostempty,
almost_full => cpu2_cpu1_fifo_almostfull,
empty => cpu2_cpu1_fifo_empty,
full => cpu2_cpu1_fifo_full,
q => cpu2_cpu1_fifo_readData,
usedw => cpu2_cpu1_fifo_count
);
-- Prozess zum reseten der Fifos und zum Setzen der IEnable Register
process (clk, reset)
begin
if (reset = '1') then
cpu1_cpu2_fifo_clear <= '1';
cpu2_cpu1_fifo_clear <= '1';
cpu1_interruptEnableRegister <= "00000000";
cpu2_interruptEnableRegister <= "00000000";
else
if rising_edge(clk) then
if (cpu1_address = "00000001" and cpu1_write = '1') then
cpu1_interruptEnableRegister <= cpu1_interruptEnableRegister XOR cpu1_writedata(7 downto 0);
end if;
if (cpu2_address = "00000001" AND cpu2_write = '1') then
cpu2_interruptEnableRegister <= cpu2_interruptEnableRegister XOR cpu2_writedata(7 downto 0);
end if;
if (cpu1_address = "00000011" AND cpu1_write = '1' AND cpu1_writedata(0) = '1') then
cpu1_cpu2_fifo_clear <= '1';
else
cpu1_cpu2_fifo_clear <= '0';
end if;
if (cpu2_address = "00000011" AND cpu2_write = '1' AND cpu2_writedata(0) = '1') then
cpu2_cpu1_fifo_clear <= '1';
else
cpu2_cpu1_fifo_clear <= '0';
end if;
end if;
end if;
end process;
-- Prozess zur Verarbeitung und Definition der Interruptregister von CPU1
interrupt_process_cpu1 : process (clk, reset)
begin
if (reset = '1') then
cpu1_interruptRegister <= "00000000";
cpu1_interruptRegister_last <= "00000000";
elsif (rising_edge(clk)) then
if (cpu1_address = "00000010" AND cpu1_write = '1') then
cpu1_interruptRegister <= cpu1_interruptRegister XOR (cpu1_interruptRegister AND cpu1_writedata(7 downto 0));
end if;
if (cpu1_cpu2_fifo_almostempty = '1' AND cpu1_interruptRegister_last(0) = '0' AND cpu1_interruptEnableRegister(0) = '1') then
cpu1_interruptRegister(0) <= '1';
end if;
if (cpu2_cpu1_fifo_almostfull = '1' AND cpu1_interruptRegister_last(1) = '0' AND cpu1_interruptEnableRegister(1) = '1') then
cpu1_interruptRegister(1) <= '1';
end if;
cpu1_interruptRegister_last <= cpu1_interruptRegister;
end if;
end process;
-- Prozess zur Verarbeitung und Definition der Interruptregister von CPU2
interrupt_process_cpu2 : process (clk, reset)
begin
if (reset = '1') then
cpu2_interruptRegister <= "00000000";
cpu2_interruptRegister_last <= "00000000";
elsif (rising_edge(clk)) then
if (cpu2_address = "00000010" AND cpu2_write = '1') then
cpu2_interruptRegister <= cpu2_interruptRegister XOR (cpu2_interruptRegister AND cpu2_writedata(7 downto 0));
end if;
if (cpu2_cpu1_fifo_almostempty = '1' AND cpu2_interruptRegister_last(0) = '0' AND cpu2_interruptEnableRegister(0) = '1') then
cpu2_interruptRegister(0) <= '1';
end if;
if (cpu1_cpu2_fifo_almostfull = '1' AND cpu2_interruptRegister_last(1) = '0' AND cpu2_interruptEnableRegister(1) = '1') then
cpu2_interruptRegister(1) <= '1';
end if;
cpu2_interruptRegister_last <= cpu2_interruptRegister;
end if;
end process;
-- Statusregister mit aktuellen Werten füllen
statusRegister(0) <= cpu1_cpu2_fifo_empty;
statusRegister(1) <= cpu1_cpu2_fifo_almostempty;
statusRegister(2) <= cpu1_cpu2_fifo_almostfull;
statusRegister(3) <= cpu1_cpu2_fifo_full;
statusRegister(4) <= cpu2_cpu1_fifo_empty;
statusRegister(5) <= cpu2_cpu1_fifo_almostempty;
statusRegister(6) <= cpu2_cpu1_fifo_almostfull;
statusRegister(7) <= cpu2_cpu1_fifo_full;
-- Steuerleitungen der Fifos setzen
cpu2_cpu1_fifo_rdreq <= '1' when cpu1_read = '1' and cpu1_address = "00000000" else
'0';
cpu1_cpu2_fifo_rdreq <= '1' when cpu2_read = '1' and cpu2_address = "00000000" else
'0';
cpu1_cpu2_fifo_wrreq <= '1' when cpu1_write = '1' and cpu1_address = "00000000" else
'0';
cpu2_cpu1_fifo_wrreq <= '1' when cpu2_write = '1' and cpu2_address = "00000000" else
'0';
-- Füllstand setzen
cpu2_cpu1_fifo_count_out <= ("0" & cpu2_cpu1_fifo_count) when cpu2_cpu1_fifo_full = '0' else
"100000";
cpu1_cpu2_fifo_count_out <= ("0" & cpu1_cpu2_fifo_count) when cpu1_cpu2_fifo_full = '0' else
"100000";
-- Avalon-Datenleitung je nach gewählter Adresse füllen
cpu1_readdata <= cpu2_cpu1_fifo_readData when cpu1_address = "00000000" else
(fueller & cpu1_interruptEnableRegister) when cpu1_address = "00000001" else
(fueller & cpu1_interruptRegister) when cpu1_address = "00000010" else
(fueller & statusRegister) when cpu1_address = "00000011" else
(fueller & "00" & cpu2_cpu1_fifo_count_out) when cpu1_address = "00000100" else
(fueller & "00" & cpu1_cpu2_fifo_count_out) when cpu1_address = "00000101" else
(fueller & "11111111");
cpu2_readdata <= cpu1_cpu2_fifo_readData when cpu2_address = "00000000" else
(fueller & cpu2_interruptEnableRegister) when cpu2_address = "00000001" else
(fueller & cpu2_interruptRegister) when cpu2_address = "00000010" else
(fueller & statusRegister(3 downto 0) & statusRegister(7 downto 4) ) when cpu2_address = "00000011" else
(fueller & "00" & cpu1_cpu2_fifo_count_out) when cpu2_address = "00000100" else
(fueller & "00" & cpu2_cpu1_fifo_count_out) when cpu2_address = "00000101" else
(fueller & "11111111");
-- Interrupt setzen
cpu1_irq <= '0' when cpu1_interruptRegister = "00000000" else
'1';
cpu2_irq <= '0' when cpu2_interruptRegister = "00000000" else
'1';
end architecture rtl; -- of CPU_FiFo_Bridge
| gpl-2.0 | 5428a11a7a0d68520bfb3c4e89833bd5 | 0.60122 | 3.043977 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/mem/types_mem.vhd | 2 | 6,529 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_mem package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! Provide common generic log() function
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief Declaration of 'virtual' Memory components.
package types_mem is
--! @brief Declaration of the "virtual" BootROM component.
--! @details BootRom start address must implements address matching to the
--! CPU reset vector (0x200) and all processing after power-on is
--! using this memory block. BootRom size depends of the configuration
--! and size of the generated hex file.
--! Component implements one-clock access to the
--! ROM without wait-staits. Datawidth depends of the AXI4 bus
--! configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] hex_filename Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component BootRom_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
--! @brief Declaration of the "virtual" RomImage component.
--! @details This module stores pre-built firmware image that is coping
--! into internal SRAM during Boot stage without any modificaiton.
--! RomImage size is limited by global configuration parameter and
--! it cannot be more than internal SRAM size. Component implements
--! one-clock access to the ROM without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] sim_hexfile Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component RomImage_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
--! @brief Galileo PRN codes ROM storage:
--! @details This ROM is used in FSE Engine to form reference E1 reference
--! signals. HEX-file isn't used for this ROM because 'inferred'
--! module was built using "case when" operators.
component RomPrn_tech is
generic (
generic_tech : integer := 0
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Declaration of the "virtual" SRAM component with unaligned access.
--! @details This module implements internal SRAM and support unaligned access
--! without wait-states. For example it allows to read 4 bytes from
--! address 0x3 for one clock.
--! Component implements one-clock access without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] memtech Generic technology selector.
--! @param[in] abits Generic argument defining SRAM size as 2**abits.
--! @param[in] clk System bus clock.
--! @param[in] raddr Read address.
--! @param[out] rdata Output data value.
--! @param[in] waddr Write address.
--! @param[in] we Write enable.
--! @param[in] wstrb Byte selector to form write only for the specified bytes.
--! @param[in] wdata Write data.
component srambytes_tech is
generic (
memtech : integer := 0;
abits : integer := 16;
init_file : string := ""
);
port (
clk : in std_logic;
raddr : in global_addr_array_type;
rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
waddr : in global_addr_array_type;
we : in std_logic;
wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 32-bits data width.
--! @details This module doesn't support byte access and always implements
--! 4-bytes alignment.
component Ram32_tech
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 64-bits data width.
--! @details This module doesn't support byte access and always implements
--! 8-bytes alignment.
component Ram64_tech
generic (
generic_tech : integer := 0;
generic_abits : integer := 4
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(63 downto 0);
o_data : out std_logic_vector(63 downto 0)
);
end component;
--! @brief dual-port RAM declaration.
component syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end component;
end;
| bsd-2-clause | 3562d4f579decdc3e297ce9d8f6b3cf1 | 0.610966 | 3.952179 | false | false | false | false |
freecores/gamepads | gcpad/rtl/vhdl/gcpad_tx.vhd | 1 | 9,727 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_tx.vhd,v 1.2 2004-10-08 20:51:59 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gcpad_tx is
generic (
reset_level_g : natural := 0;
clocks_per_1us_g : natural := 2
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Pad Interface ----------------------------------------------------------
pad_data_o : out std_logic;
-- Control Interface ------------------------------------------------------
tx_start_i : in boolean;
tx_finished_o : out boolean;
tx_size_i : in std_logic_vector( 1 downto 0);
tx_command_i : in std_logic_vector(23 downto 0)
);
end gcpad_tx;
library ieee;
use ieee.numeric_std.all;
use work.gcpad_pack.all;
architecture rtl of gcpad_tx is
subtype command_t is std_logic_vector(24 downto 0);
signal command_q : command_t;
signal load_command_s : boolean;
signal shift_bits_s : boolean;
constant cnt_long_c : natural := clocks_per_1us_g * 4 - 1;
constant cnt_short_c : natural := clocks_per_1us_g * 1 - 1;
subtype cnt_t is natural range 0 to cnt_long_c;
signal cnt_q : cnt_t;
signal cnt_load_long_s : boolean;
signal cnt_load_short_s : boolean;
signal cnt_finished_s : boolean;
subtype num_bits_t is unsigned(4 downto 0);
signal num_bits_q : num_bits_t;
signal all_bits_sent_s : boolean;
signal cnt_bit_s : boolean;
type state_t is (IDLE,
LOAD_COMMAND,
SEND_COMMAND_PHASE1,
SEND_COMMAND_PHASE2);
signal state_s,
state_q : state_t;
signal pad_data_s,
pad_data_q : std_logic;
signal tx_finished_s,
tx_finished_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements of this module.
--
seq: process (reset_i, clk_i)
variable size_v : std_logic_vector(num_bits_t'range);
begin
if reset_i = reset_level_g then
command_q <= (others => '1');
cnt_q <= cnt_long_c;
num_bits_q <= (others => '0');
pad_data_q <= '1';
state_q <= IDLE;
tx_finished_q <= false;
elsif clk_i'event and clk_i = '1' then
tx_finished_q <= tx_finished_s;
-- fsm
state_q <= state_s;
-- command register and bit counter
if load_command_s then
command_q(24 downto 1) <= tx_command_i;
command_q(0) <= '1';
-- workaround for GHDL concatenation
size_v(num_bits_t'high downto 3) := tx_size_i;
size_v(2 downto 0) := (others => '0');
num_bits_q <= unsigned(size_v) + 1;
else
if shift_bits_s then
command_q(command_t'high downto 1) <= command_q(command_t'high-1 downto 0);
end if;
if cnt_bit_s and not all_bits_sent_s then
num_bits_q <= num_bits_q - 1;
end if;
end if;
-- PWM counter
if cnt_load_long_s then
cnt_q <= cnt_long_c;
elsif cnt_load_short_s then
cnt_q <= cnt_short_c;
else
if not cnt_finished_s then
cnt_q <= cnt_q - 1;
end if;
end if;
-- PWM output = pad data
pad_data_q <= pad_data_s;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-- indicates that PWM counter has finished
cnt_finished_s <= cnt_q = 0;
-- indicates that all bits have been sent
all_bits_sent_s <= num_bits_q = 0;
-----------------------------------------------------------------------------
-- Process fsm
--
-- Purpose:
-- Models the controlling state machine.
--
fsm: process (state_q,
cnt_finished_s,
all_bits_sent_s,
tx_start_i,
command_q)
begin
-- defaul assignments
state_s <= IDLE;
shift_bits_s <= false;
cnt_load_long_s <= false;
cnt_load_short_s <= false;
pad_data_s <= '1';
tx_finished_s <= false;
load_command_s <= false;
cnt_bit_s <= false;
case state_q is
-- IDLE -----------------------------------------------------------------
-- The idle state.
-- Advances when the transmitter is started
when IDLE =>
if tx_start_i then
state_s <= LOAD_COMMAND;
else
state_s <= IDLE;
end if;
-- LOAD_COMMAND ---------------------------------------------------------
-- Prepares the first and all subsequent low phases on pad_data_s.
when LOAD_COMMAND =>
state_s <= SEND_COMMAND_PHASE2;
load_command_s <= true;
-- start counter once to kick the loop
cnt_load_short_s <= true;
-- SEND_COMMAND_PHASE1 --------------------------------------------------
-- Wait for completion of phase 1, the low phase of pad_data_s.
-- The high phase is prepared when the PWM counter has expired.
when SEND_COMMAND_PHASE1 =>
state_s <= SEND_COMMAND_PHASE1;
pad_data_s <= '0';
if cnt_finished_s then
-- initiate high phase
pad_data_s <= '1';
if command_q(command_t'high) = '1' then
cnt_load_long_s <= true;
else
cnt_load_short_s <= true;
end if;
state_s <= SEND_COMMAND_PHASE2;
-- provide next bit
shift_bits_s <= true;
end if;
-- SEND_COMMAND_PHASE2 --------------------------------------------------
-- Wait for completion of phase 2, the high phase of pad_data_s.
-- The next low phase is prepared when the PWM counter has expired.
-- In case all bits have been sent, the tx handshake is asserted and
-- the FSM returns to IDLE state.
when SEND_COMMAND_PHASE2 =>
pad_data_s <= '1';
state_s <= SEND_COMMAND_PHASE2;
if cnt_finished_s then
if not all_bits_sent_s then
-- more bits to send so loop
-- prepare low phase
if command_q(command_t'high) = '1' then
cnt_load_short_s <= true;
else
cnt_load_long_s <= true;
end if;
-- decrement bit counter
cnt_bit_s <= true;
state_s <= SEND_COMMAND_PHASE1;
else
-- all bits sent, we're finished
tx_finished_s <= true;
state_s <= IDLE;
end if;
end if;
when others =>
null;
end case;
end process fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
tx_finished_o <= tx_finished_q;
pad_data_o <= pad_data_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2004/10/07 21:23:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 8b4c4c32d89f2f8700e61b4ce50d015d | 0.506117 | 4.142675 | false | false | false | false |
jrrk2/greth_library | greth_library/gnsslib/sync/greycnt.vhd | 2 | 1,347 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity GrayCounter is
generic (
generic_width : integer := 4
);
port ( --'Gray' code count output.
i_nrst : in std_logic; -- Count reset.
i_clk : in std_logic; -- Input clock
i_ena : in std_logic; -- Count enable.
o_cnt : out std_logic_vector (generic_width-1 downto 0)
);
end entity;
architecture rtl of GrayCounter is
type regs is record
bin_cnt : std_logic_vector (generic_width-1 downto 0);
grey_cnt : std_logic_vector (generic_width-1 downto 0);
end record;
signal r : regs;
begin
process (i_clk, i_nrst) begin
if i_nrst = '0' then
r.bin_cnt <= conv_std_logic_vector(1, generic_width);
r.grey_cnt <= (others=>'0');
elsif (rising_edge(i_clk)) then
if i_ena = '1' then
r.bin_cnt <= r.bin_cnt + 1;
r.grey_cnt <= r.bin_cnt(generic_width-1) &
(r.bin_cnt(generic_width-2 downto 0) xor
r.bin_cnt(generic_width-1 downto 1));
end if;
end if;
end process;
o_cnt <= r.grey_cnt;
end architecture;
| bsd-2-clause | 6ed62d3d07f600c5a32c9a04a19b6c3e | 0.515219 | 3.507813 | false | false | false | false |
akshayp/college-projects | vhdl/pong/ping.vhd | 1 | 15,097 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; --for using std_logic
USE IEEE.STD_LOGIC_UNSIGNED.ALL; --for addition of std_logic
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY PING IS
PORT( CLK,CLR : IN STD_LOGIC;
SERVE1, SERVE2 : IN STD_LOGIC; --Players
POSITION1, PADDLE1 : IN INTEGER RANGE 0 TO 48;
POSITION2, PADDLE2 : IN INTEGER RANGE 0 TO 48;
SCORE11,SCORE22 : INOUT INTEGER RANGE 0 TO 9; --display score in waveform which is later converted to BCD
ROW, COLUMN : OUT INTEGER RANGE 0 TO 64;
OUT1,OUT2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --BCD display of the score
HEXOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)); --Winners(P1,P0)
END PING;
ARCHITECTURE ALG OF PING IS
TYPE STATE_TYPE IS (SERVE_DECIDE,STEP_DECIDE_STATE_1,STEP_DECIDE_STATE_2,POSITION_STATE_1,POSITION_STATE_2,
LOOP_STATE_1,LOOP_STATE_2,SCORE_INC_1,SCORE_INC_2,IDLE_STATE_1,IDLE_STATE_2);
SIGNAL STATE : STATE_TYPE;
BEGIN
PROCESS(CLK,CLR) --process wakes up on CLK or CLR
VARIABLE SCORE1 : INTEGER RANGE 0 TO 9; --temporary score
VARIABLE SCORE2 : INTEGER RANGE 0 TO 9;
VARIABLE CURRENT_ROW,PREVIOUS_ROW,CURRENT_COLUMN : INTEGER RANGE 0 TO 64;
VARIABLE STEP : INTEGER RANGE 0 TO 64;
variable a, b : integer range 1 to 4;
BEGIN
IF CLR = '0' THEN
SCORE11 <= 0; --the scores reset on CLR
SCORE22 <= 0;
HEXOUT <= x"20202020202020202020202020202020";
SCORE1 := 1;
SCORE2 := 1;
CURRENT_ROW := 32;
PREVIOUS_ROW := 32;
CURRENT_COLUMN := 32;
STATE <= SERVE_DECIDE;
ELSIF CLK'EVENT AND CLK = '1' THEN
CASE STATE IS
WHEN SERVE_DECIDE =>
IF serve1 = '0' THEN --when player 1 serves
STATE <= POSITION_STATE_1;
ELSIF SERVE2 = '0' THEN --when player 2 serves
STATE <= POSITION_STATE_2;
ELSE
STATE <= SERVE_DECIDE; --rest condition
END IF ;
--PART DEALING WITH THE PLAYER 1
WHEN POSITION_STATE_1 =>
if b = 1 then
CURRENT_ROW := PADDLE1;
PREVIOUS_ROW := PADDLE1;
elsif b = 2 then
CURRENT_ROW := PADDLE1+1;
PREVIOUS_ROW := PADDLE1+1;
elsif b =3 then
CURRENT_ROW := PADDLE1-2;
PREVIOUS_ROW := PADDLE1-2;
elsif b = 4 then
CURRENT_ROW := PADDLE1-1;
PREVIOUS_ROW := PADDLE1-1;
else
CURRENT_ROW := PADDLE1;
PREVIOUS_ROW := PADDLE1;
end if;
CURRENT_COLUMN := 16;
STATE <= STEP_DECIDE_STATE_1;
WHEN STEP_DECIDE_STATE_1 =>
CURRENT_ROW := POSITION1;
CURRENT_COLUMN := CURRENT_COLUMN + 1;
IF POSITION1 >= PREVIOUS_ROW THEN
STEP := (POSITION1 - PREVIOUS_ROW)/4;
ELSE
STEP := (PREVIOUS_ROW - POSITION1)/4;
END IF;
STATE <= LOOP_STATE_1;
WHEN LOOP_STATE_1 =>
--ROW_IF
IF CURRENT_ROW > PREVIOUS_ROW THEN
IF (CURRENT_ROW + STEP) > 48 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := 48;
ELSIF CURRENT_ROW = 48 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW - STEP;
ELSE
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW + STEP;
END IF;
ELSE
IF CURRENT_ROW = 16 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW + STEP;
ELSIF (CURRENT_ROW - STEP) < 16 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := 16;
ELSE
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW - STEP;
END IF;
END IF;
--COLUMN_IF AND NEXT STATE DECISION
IF CURRENT_COLUMN = 48 THEN
CURRENT_COLUMN := CURRENT_COLUMN + 1;
IF CURRENT_ROW > PREVIOUS_ROW THEN
IF PADDLE2 = (CURRENT_ROW ) THEN--step
a:=1;
STATE <= POSITION_STATE_2;
ELSIF ((paddle2 + 1) = current_row) THEN
a:=2;
STATE <= POSITION_STATE_2;
ELSIF ((paddle2 - 2) = current_row) THEN
a:=3;
STATE <= POSITION_STATE_2;
ELSIF ((paddle2 - 1) = current_row) THEN
a:=4;
STATE <= POSITION_STATE_2;
ELSE
STATE <= SCORE_INC_1;
END IF;
ELSE
IF PADDLE2 = (CURRENT_ROW-step) THEN--step
a := 1;
STATE <= POSITION_STATE_2;
ELSIF ((paddle2 + 1) = current_row) THEN
a:=2;
STATE <= POSITION_STATE_2;
ELSIF ((paddle2 - 2) = current_row) THEN
a:=3;
STATE <= POSITION_STATE_2;
ELSIF ((paddle2 - 1) = current_row) THEN
a:=4;
STATE <= POSITION_STATE_2;
ELSE
STATE <= SCORE_INC_1;
END IF;
END IF;
ELSE
CURRENT_COLUMN := CURRENT_COLUMN + 1;
STATE <= LOOP_STATE_1;
END IF;
WHEN SCORE_INC_1 =>
SCORE1 := SCORE11 + 1;
SCORE11 <= SCORE1; --Player P1 gets the point
IF (SCORE11 + SCORE22) > 3 AND (SCORE11 + SCORE22) < 9 THEN --This portion decide the serving player
STATE <= IDLE_STATE_2;
ELSIF (SCORE11 + SCORE22) > 13 AND (SCORE11 + SCORE22) < 19 THEN
STATE <= IDLE_STATE_2;
ELSIF (SCORE11 + SCORE22) > 23 AND (SCORE11 + SCORE22) < 30 THEN
STATE <= IDLE_STATE_2;
ELSE
STATE <= IDLE_STATE_1;
END IF;
WHEN IDLE_STATE_1 =>
CURRENT_ROW := CURRENT_ROW;
CURRENT_COLUMN := CURRENT_COLUMN;
IF SCORE11 = 9 THEN
HEXOUT <= X"506C6179657220312057696E73212121";
STATE <= IDLE_STATE_1;
ELSIF SCORE22 = 9 THEN
HEXOUT <= X"506C6179657220322057696E73212121";
STATE <= IDLE_STATE_1;
ELSE --Player serves again
STATE <= POSITION_STATE_1;
END IF;
--PART DEALING WITH THE PLAYER 2
WHEN POSITION_STATE_2 =>
IF a = 1 THEN
CURRENT_ROW := PADDLE2;
PREVIOUS_ROW := PADDLE2;
ELSIF a = 2 THEN
CURRENT_ROW := PADDLE2+1;
PREVIOUS_ROW := PADDLE2+1;
ELSIF a =3 THEN
CURRENT_ROW := PADDLE2-2;
PREVIOUS_ROW := PADDLE2-2;
ELSIF a = 4 THEN
CURRENT_ROW := PADDLE2-1;
PREVIOUS_ROW := PADDLE2-1;
ELSE
CURRENT_ROW := PADDLE2;
PREVIOUS_ROW := PADDLE2;
END IF;
CURRENT_COLUMN := 48;
STATE <= STEP_DECIDE_STATE_2;
WHEN STEP_DECIDE_STATE_2 =>
CURRENT_ROW := POSITION2;
CURRENT_COLUMN := CURRENT_COLUMN - 1;
IF POSITION2 >= PREVIOUS_ROW THEN
STEP := (POSITION2 - PREVIOUS_ROW)/4;
ELSE
STEP := (PREVIOUS_ROW - POSITION2)/4;
END IF;
STATE <= LOOP_STATE_2;
WHEN LOOP_STATE_2 =>
--ROW_IF
IF CURRENT_ROW > PREVIOUS_ROW THEN
IF (CURRENT_ROW + STEP) > 48 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := 48;
ELSIF CURRENT_ROW = 48 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW - STEP;
ELSE
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW + STEP;
END IF;
ELSE
IF CURRENT_ROW = 16 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW + STEP;
ELSIF (CURRENT_ROW - STEP) < 16 THEN
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := 16;
ELSE
PREVIOUS_ROW := CURRENT_ROW;
CURRENT_ROW := CURRENT_ROW - STEP;
END IF;
END IF;
--COLUMN_IF AND NEXT STATE DECISION
IF CURRENT_COLUMN = 16 THEN
CURRENT_COLUMN := CURRENT_COLUMN - 1;
IF CURRENT_ROW > PREVIOUS_ROW THEN
IF PADDLE1 = (CURRENT_ROW) THEN--+step
b:=1;
STATE <= POSITION_STATE_1;
ELSif ((paddle1 + 1) = current_row) then
b:=2;
STATE <= POSITION_STATE_1;
ELSif ((paddle1 - 2) = current_row) then
b:=3;
STATE <= POSITION_STATE_1;
ELSif ((paddle1 - 1) = current_row) then
b:=4;
STATE <= POSITION_STATE_1;
else
STATE <= SCORE_INC_2;
END IF;
ELSE
IF PADDLE1 = (CURRENT_ROW) THEN--step
STATE <= POSITION_STATE_1;
ELSif ((paddle1 + 1) = current_row) then
STATE <= POSITION_STATE_1;
ELSif ((paddle1 - 2) = current_row) then
STATE <= POSITION_STATE_1;
ELSif ((paddle1 - 1) = current_row) then
STATE <= POSITION_STATE_1;
ELSE
STATE <= SCORE_INC_2;
END IF;
END IF;
ELSE
CURRENT_COLUMN := CURRENT_COLUMN - 1;
STATE <= LOOP_STATE_2;
END IF;
WHEN SCORE_INC_2 =>
SCORE2 := SCORE22 + 1;
SCORE22 <= SCORE2; --P0 gets the point
IF (SCORE11 + SCORE22) > 3 AND (SCORE11 + SCORE22) < 9 THEN --CHANGE OF SERVICE
STATE <= IDLE_STATE_1;
ELSIF (SCORE11 + SCORE22) > 13 AND (SCORE11 + SCORE22) < 18 THEN
STATE <= IDLE_STATE_1;
ELSE
STATE <= IDLE_STATE_2;
END IF;
WHEN IDLE_STATE_2 =>
CURRENT_ROW := CURRENT_ROW;
CURRENT_COLUMN := CURRENT_COLUMN;
IF SCORE11 = 9 THEN
HEXOUT <= X"506C6179657220312057696E73212121";
STATE <= IDLE_STATE_2;
ELSIF SCORE22 = 9 THEN
HEXOUT <= X"506C6179657220322057696E73212121";
STATE <= IDLE_STATE_2;
ELSE --Player serves again
STATE <= POSITION_STATE_2;
END IF;
END CASE;
END IF;
ROW <= CURRENT_ROW;
COLUMN <= CURRENT_COLUMN;
END PROCESS;
PROCESS(SCORE11,SCORE22) --to convert to BCD
BEGIN
CASE SCORE11 IS
WHEN 0 => OUT1 <= "0000001";
WHEN 1 => OUT1 <= "1001111";
WHEN 2 => OUT1 <= "0010010";
WHEN 3 => OUT1 <= "0000110";
WHEN 4 => OUT1 <= "1001100";
WHEN 5 => OUT1 <= "0100100";
WHEN 6 => OUT1 <= "0100000";
WHEN 7 => OUT1 <= "0001111";
WHEN 8 => OUT1 <= "0000000";
WHEN 9 => OUT1 <= "0001100";
END CASE;
CASE SCORE22 IS --score for Player P0
WHEN 0 => OUT2 <= "0000001";
WHEN 1 => OUT2 <= "1001111";
WHEN 2 => OUT2 <= "0010010";
WHEN 3 => OUT2 <= "0000110";
WHEN 4 => OUT2 <= "1001100";
WHEN 5 => OUT2 <= "0100100";
WHEN 6 => OUT2 <= "0100000";
WHEN 7 => OUT2 <= "0001111";
WHEN 8 => OUT2 <= "0000000";
WHEN 9 => OUT2 <= "0001100";
END CASE;
END PROCESS;
END ALG; | mit | a3767f71bed7fb68022d7b4dec95382d | 0.373849 | 4.930438 | false | false | false | false |
jrrk2/greth_library | greth_library/work/simple_soc.vhd | 2 | 10,798 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! @}
--! @name ADC channel A inputs (1575.4 GHz):
--! @{
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name ADC channel B inputs (1602 GHz):
--! @{
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name MAX2769 SPIs and antenna controls signals:
--! @{
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_type;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slave_out_type;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
aximi.grant <= "1";
aximi.aw_ready <= axiso.aw_ready;
aximi.w_ready <= axiso.w_ready;
aximi.b_valid <= axiso.b_valid;
aximi.b_resp <= axiso.b_resp;
aximi.b_id <= axiso.b_id;
aximi.b_user <= axiso.b_user;
aximi.ar_ready <= axiso.ar_ready;
aximi.r_valid <= axiso.r_valid;
aximi.r_resp <= axiso.r_resp;
aximi.r_data <= axiso.r_data;
aximi.r_last <= axiso.r_last;
aximi.r_id <= axiso.r_id;
aximi.r_user <= axiso.r_user;
axisi.aw_valid <= aximo.aw_valid;
axisi.aw_bits <= aximo.aw_bits;
axisi.aw_id <= aximo.aw_id;
axisi.aw_user <= aximo.aw_user;
axisi.w_valid <= aximo.w_valid;
axisi.w_data <= aximo.w_data;
axisi.w_last <= aximo.w_last;
axisi.w_strb <= aximo.w_strb;
axisi.w_user <= aximo.w_user;
axisi.b_ready <= aximo.b_ready;
axisi.ar_valid <= aximo.ar_valid;
axisi.ar_bits <= aximo.ar_bits;
axisi.ar_id <= aximo.ar_id;
axisi.ar_user <= aximo.ar_user;
axisi.r_ready <= aximo.r_ready;
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso,
i_dip => ib_dip,
o_led => o_led
);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => wReset,
i_clk => ib_gmiiclk,
o_clk => eth_i.gtx_clk,
o_clkp90 => eth_i.tx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo,
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => open,
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
end arch_rocket_soc;
| bsd-2-clause | 0b39d4c8d656d5b5f489cca181750297 | 0.592795 | 3.231966 | false | false | false | false |
jrrk2/greth_library | greth_library/rocketlib/tilelink/htifserdes.vhd | 2 | 5,057 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'htifserdes' module.
--! @details Used only for system with enabled L2-cache.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Uncore messages serializer/deserializer.
--! @details There is implemented logic of conversion of the 128-bit
--! 'Uncore' messages on chunks of HTIF_WIDTH bits size (default 16
--! bits). Message is formed using HostIO signal request.
entity htif_serdes is
generic (
core_idx : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
hostoi : in host_out_type;
hostio : out host_in_type;
srdi : in htif_serdes_in_type;
srdo : out htif_serdes_out_type
);
end;
architecture arch_htif_serdes of htif_serdes is
--! @name Uncore message IDs specific for HostIO interface.
--! @brief Used See htif.scala, class Htif, line about 105.
--! @{
--! Reading from physical memory. Not used in this SOC.
constant HTIF_CMD_READ_MEMORY : std_logic_vector(3 downto 0) := X"0";
--! Writting into physical memory. Not used in this SOC.
constant HTIF_CMD_WRITE_MEMORY : std_logic_vector(3 downto 0) := X"1";
--! Reading Control Register (CSR).
constant HTIF_CMD_READ_CONTROL_REG : std_logic_vector(3 downto 0) := X"2";
--! Writting Control Register (CSR).
constant HTIF_CMD_WRITE_CONTROL_REG : std_logic_vector(3 downto 0) := X"3";
--! Handshake success.
constant HTIF_CMD_ACK : std_logic_vector(3 downto 0) := X"4";
--! Handshake error.
constant HTIF_CMD_NACK : std_logic_vector(3 downto 0) := X"5";
--! @}
constant HTIF_DATA_EMPTY :
std_logic_vector(HTIF_WIDTH-1 downto 0) := (others => '1');
type state_type is (wait_cmd, transmit, response, resp_ready);
type registers is record
state : state_type;
muxCnt : integer range 0 to 128/HTIF_WIDTH + 1;
cmd : std_logic_vector(127 downto 0);
seqno : std_logic_vector(7 downto 0);
end record;
signal r, rin: registers;
function functionMakeMessage( r : registers;
hst : host_out_type)
return std_logic_vector is
variable ret : std_logic_vector(127 downto 0);
begin
ret(127 downto 64) := hst.csr_req_bits_data;
ret(63 downto 44) := conv_std_logic_vector(core_idx, 20);
ret(43 downto 36) := X"00";
ret(35 downto 24) := hst.csr_req_bits_addr;
ret(23 downto 16) := r.seqno;
ret(15 downto 4) := X"001"; -- total number of words
if hst.csr_req_bits_rw = '1' then
ret(3 downto 0) := HTIF_CMD_WRITE_CONTROL_REG;
else
ret(3 downto 0) := HTIF_CMD_READ_CONTROL_REG;
end if;
return ret;
end;
begin
comblogic : process(hostoi, srdi, r)
variable v : registers;
variable vo : host_in_type;
begin
v := r;
vo.grant := (others => '0');
vo.csr_req_ready := '0';
vo.csr_resp_valid := '0';
vo.csr_resp_bits := (others => '0');
vo.debug_stats_csr := '0';
case r.state is
when wait_cmd =>
vo.csr_req_ready := '1';
if hostoi.csr_req_valid = '1' then
v.state := transmit;
v.seqno := r.seqno + 1;
v.cmd := functionMakeMessage(r, hostoi);
end if;
srdo.valid <= '0';
srdo.ready <= '0';
srdo.bits <= (others => '0');
when transmit =>
--! Multiplexer of the command into HTIF bus
if srdi.ready = '1' then
v.muxCnt := r.muxCnt + 1;
end if;
v.cmd := HTIF_DATA_EMPTY & r.cmd(127 downto HTIF_WIDTH);
if r.muxCnt = (128/HTIF_WIDTH) - 1 then
v.state := response;
v.muxCnt := 0;
end if;
srdo.valid <= '1';
srdo.ready <= '0';
srdo.bits <= r.cmd(HTIF_WIDTH-1 downto 0);
when response =>
if srdi.valid = '1' then
v.muxCnt := r.muxCnt + 1;
v.cmd := srdi.bits & r.cmd(127 downto HTIF_WIDTH);
if r.muxCnt = (128/HTIF_WIDTH) - 1 then
v.state := resp_ready;
end if;
end if;
srdo.valid <= '0';
srdo.ready <= '1';
srdo.bits <= (others => '0');
when resp_ready =>
if hostoi.csr_resp_ready = '1' then
v.state := wait_cmd;
end if;
srdo.valid <= '0';
srdo.ready <= '0';
srdo.bits <= (others => '0');
vo.csr_resp_valid := '1';
vo.csr_resp_bits := r.cmd(127 downto 64);
when others =>
end case;
rin <= v;
hostio <= vo;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= wait_cmd;
r.muxCnt <= 0;
r.cmd <= (others => '0');
r.seqno <= X"01";
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| bsd-2-clause | a411cd7d0350d749c5bda206a0322182 | 0.571287 | 3.362367 | false | false | false | false |
rxfx/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER/CTRL_TELEGRAM_FILTER_VHDL.vhd | 8 | 10,937 | -- CTRL_TELEGRAM_FILTER
-- Voreingestellten Profibus Telegramtyp ermitteln und Bytes ausgeben, alternativ alle Bytes durchlassen
-- Ersteller: Martin Harndt
-- Erstellt: 22.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 22.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_FILTER_VHDL is
Port (BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
FILTER_ON : in std_logic; --Eingangsvariable, Filter einschalten
FILTER_T : in std_logic_vector (2 downto 0); --Eingangsvariable, Telegramfilter einstellen, 3bit
FILTER_BYTE_OUT : out std_logic_vector (7 downto 0);--Ausgangsvariable, gefilterte Telegramme
SEND_OUT : out std_logic; --Ausgangsvariable, Byte senden
T_CMPLT: out std_logic; --Ausgangsvariable, Telegramm komplett
DISPL_COUNT : in std_logic; --Eingangsvariable, Folgeszustand oder Bytezaehler anzeigen
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_FILTER_VHDL;
architecture Behavioral of CTRL_TELEGRAM_FILTER_VHDL is
type TYPE_STATE is
(ST_FI_00, --Zustaende TELEGRAM_CHECK
ST_FI_01,
ST_FI_02,
ST_FI_03,
ST_FI_04,
ST_FI_05,
ST_FI_06,
ST_FI_07,
ST_FI_08,
ST_FI_09,
ST_FI_10,
ST_FI_11,
ST_FI_12,
ST_FI_13,
ST_FI_14,
ST_FI_15);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit
signal n_COUNT : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0); -- Vektor, Zaehler, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal not_CLK : std_logic; --negierte Taktvariable
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_FI_00;
COUNT_M <= x"00";
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_FI_00;
COUNT <= x"00";
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_FILTER_PROC:process (FILTER_ON, FILTER_T, BYTE_IN, SV, COUNT) --Telegramme Filtern und ausgeben
begin
case SV is
when ST_FI_00 =>
if (FILTER_ON = '1')
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_01;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_01 =>
if (FILTER_T = "000")
then
--FI01
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI01
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_02;
end if;
when ST_FI_02 =>
if (FILTER_T = "001")
then
--FI01
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_03;
else
--FI01
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_05;
end if;
when ST_FI_03 =>
if (BYTE_IN = x"10")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_04;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_04 =>
if (COUNT = x"06")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_04;
end if;
when ST_FI_05 =>
if (FILTER_T= "010")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_06;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_08;
end if;
when ST_FI_06 =>
if (BYTE_IN = x"68")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_07;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_07 =>
if (COUNT = x"F9" OR BYTE_IN = x"16")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_07;
end if;
when ST_FI_08 =>
if (FILTER_T= "011")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_09;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_11;
end if;
when ST_FI_09 =>
if (BYTE_IN = x"A2")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_10;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_10 =>
if (COUNT = x"0E")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_10;
end if;
when ST_FI_11 =>
if (FILTER_T= "100")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_12;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_14;
end if;
when ST_FI_12 =>
if (BYTE_IN = x"DC")
then
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_13;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_13 =>
if (COUNT = x"03")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI02
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '0';
SEND_OUT <= '1';
n_COUNT <= COUNT+1;
n_SV <= ST_FI_13;
end if;
when ST_FI_14 =>
if (FILTER_T= "101")
then
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_15;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when ST_FI_15 =>
if (BYTE_IN = x"E5")
then
--FI03
FILTER_BYTE_OUT <= BYTE_IN;
T_CMPLT <= '1';
SEND_OUT <= '1';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
else
--FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end if;
when others =>
-- FI00
FILTER_BYTE_OUT <= x"00";
T_CMPLT <= '0';
SEND_OUT <= '0';
n_COUNT <= x"00";
n_SV <= ST_FI_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--anktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT ='0') --Original
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
else --Telegrammzaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
end if;
end process;
end Behavioral;
| gpl-2.0 | 4ca2fc244745c4b30fa553457b5e93f3 | 0.48944 | 2.911099 | false | false | false | false |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/fifo.vhd | 1 | 8,083 | -- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
almost_empty : OUT STD_LOGIC ;
almost_full : OUT STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fifo;
ARCHITECTURE SYN OF fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
almost_empty_value : NATURAL;
almost_full_value : NATURAL;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
almost_full : OUT STD_LOGIC ;
usedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
almost_empty : OUT STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
full : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
almost_full <= sub_wire0;
usedw <= sub_wire1(4 DOWNTO 0);
empty <= sub_wire2;
almost_empty <= sub_wire3;
q <= sub_wire4(31 DOWNTO 0);
full <= sub_wire5;
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
almost_empty_value => 32,
almost_full_value => 1,
intended_device_family => "Cyclone II",
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 32,
lpm_widthu => 5,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
rdreq => rdreq,
sclr => sclr,
clock => clock,
wrreq => wrreq,
data => data,
almost_full => sub_wire0,
usedw => sub_wire1,
empty => sub_wire2,
almost_empty => sub_wire3,
q => sub_wire4,
full => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "32"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "32"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "32"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "32"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "32"
-- Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
-- Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL usedw[4..0]
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
-- Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
-- Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 9e8130e8c3a359f7a4af38efebf819f8 | 0.669059 | 3.464638 | false | false | false | false |
jrrk2/greth_library | greth_library/techmap/mem/romimage_inferred.vhd | 2 | 2,228 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief ROM Image with the Firmware
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity RomImage_inferred is
generic (
hex_filename : string
);
port (
clk : in std_ulogic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end;
architecture rtl of RomImage_inferred is
constant ROM_ADDR_WIDTH : integer := 18;
constant ROM_LENGTH : integer := 2**(ROM_ADDR_WIDTH - log2(CFG_NASTI_DATA_BYTES));
type rom_block is array (0 to ROM_LENGTH-1) of std_logic_vector(31 downto 0);
type rom_type is array (0 to CFG_WORDS_ON_BUS-1) of rom_block;
type local_addr_arr is array (0 to CFG_WORDS_ON_BUS-1) of integer;
impure function init_rom(file_name : in string) return rom_type is
file rom_file : text open read_mode is file_name;
variable rom_line : line;
variable temp_bv : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable temp_mem : rom_type;
begin
for i in 0 to (ROM_LENGTH-1) loop
readline(rom_file, rom_line);
hread(rom_line, temp_bv);
for n in 0 to (CFG_WORDS_ON_BUS-1) loop
temp_mem(n)(i) := temp_bv((n+1)*32-1 downto 32*n);
end loop;
end loop;
return temp_mem;
end function;
constant rom : rom_type := init_rom(hex_filename);
begin
reg : process (clk)
variable t_adr : local_addr_arr;
begin
if rising_edge(clk) then
for n in 0 to (CFG_WORDS_ON_BUS-1) loop
t_adr(n) := conv_integer(address(n)(ROM_ADDR_WIDTH-1 downto log2(CFG_NASTI_DATA_BYTES)));
data(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) <= rom(n)(t_adr(n));
end loop;
end if;
end process;
end;
| bsd-2-clause | c44459533b15f4fed2d6325928d80d0e | 0.616697 | 3.320417 | false | false | false | false |
eiglss/VHDL | UART/rxControler.vhd | 1 | 2,192 | --******************************************************************************
-- @TITRE : rxControler.vhd
-- @VERSION : 0
-- @CREATION : october, 2016
-- @MODIFICATION :
-- @AUTEURS : Enzo IGLESIS
-- @COPYRIGHT : Copyright (c) 2016 Enzo IGLESIS
-- @LICENSE : MIT License (MIT)
--******************************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.uart_pkg.ALL;
ENTITY rxControler IS
GENERIC(dataLength : uartLength_t := 8;
parity : uartParity_t := N;
stop : uartStop_t := 1
);
PORT(clk : IN STD_ULOGIC;
aNRst : IN STD_LOGIC;
start : IN STD_LOGIC;
tick : IN STD_LOGIC;
count : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
shEn : OUT STD_LOGIC;
rxBusy : OUT STD_LOGIC;
dataReady : OUT STD_LOGIC
);
END ENTITY rxControler;
ARCHITECTURE mealy OF rxControler IS
TYPE state_t IS (idle, receive);
SIGNAL state : state_t;
BEGIN
Transition : PROCESS(clk, aNRst) IS
BEGIN
IF aNRst = '0' THEN
state <= idle;
dataReady <= '0';
ELSIF RISING_EDGE(clk) THEN
CASE state IS
WHEN idle =>
dataReady <= '0';
IF start = '1' AND tick = '1' THEN
state <= receive;
END IF;
WHEN receive =>
IF tick = '1' AND UNSIGNED(count) >= (dataLength+0+stop-1) AND parity = N THEN
state <= idle;
dataReady <= '1';
ELSIF tick = '1' AND UNSIGNED(count) >= (dataLength+1+stop-1) AND parity /= N THEN
state <= idle;
dataReady <= '1';
END IF;
END CASE;
END IF;
END PROCESS Transition;
shEn <= '1' WHEN state = receive AND tick = '1' ELSE
'0';
rxBusy <= '1' WHEN state = receive ELSE
'0';
END ARCHITECTURE mealy;
| mit | d0e16d97ca908874043ba6b35e411d2d | 0.4375 | 4.298039 | false | false | false | false |
freecores/gamepads | gcpad/rtl/vhdl/gcpad_basic.vhd | 1 | 9,394 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_basic.vhd,v 1.5 2004-10-09 22:18:35 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gcpad_basic is
generic (
-- active level of reset_i
reset_level_g : integer := 0;
-- number of clk_i periods during 1us
clocks_per_1us_g : integer := 2
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
-- Gamepad Interface ------------------------------------------------------
pad_data_io : inout std_logic;
-- Buttons Interface ------------------------------------------------------
but_a_o : out std_logic;
but_b_o : out std_logic;
but_x_o : out std_logic;
but_y_o : out std_logic;
but_z_o : out std_logic;
but_start_o : out std_logic;
but_tl_o : out std_logic;
but_tr_o : out std_logic;
but_left_o : out std_logic;
but_right_o : out std_logic;
but_up_o : out std_logic;
but_down_o : out std_logic;
ana_joy_x_o : out std_logic_vector(7 downto 0);
ana_joy_y_o : out std_logic_vector(7 downto 0);
ana_c_x_o : out std_logic_vector(7 downto 0);
ana_c_y_o : out std_logic_vector(7 downto 0);
ana_l_o : out std_logic_vector(7 downto 0);
ana_r_o : out std_logic_vector(7 downto 0)
);
end gcpad_basic;
use work.gcpad_pack.all;
architecture struct of gcpad_basic is
component gcpad_ctrl
generic (
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
rx_timeout_o : out std_logic;
tx_start_o : out boolean;
tx_finished_i : in boolean;
rx_en_o : out boolean;
rx_done_i : in boolean;
rx_data_ok_i : in boolean
);
end component;
component gcpad_tx
generic (
reset_level_g : natural := 0;
clocks_per_1us_g : natural := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_data_o : out std_logic;
tx_start_i : in boolean;
tx_finished_o : out boolean;
tx_size_i : in std_logic_vector( 1 downto 0);
tx_command_i : in std_logic_vector(23 downto 0)
);
end component;
component gcpad_rx
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
rx_en_i : in boolean;
rx_done_o : out boolean;
rx_data_ok_o : out boolean;
rx_size_i : in std_logic_vector(3 downto 0);
pad_data_i : in std_logic;
rx_data_o : out buttons_t
);
end component;
-----------------------------------------------------------------------------
-- constants for standard status polling
constant rx_size_c : std_logic_vector( 3 downto 0) := "1000";
signal rx_size_s : std_logic_vector( 3 downto 0);
--
constant tx_size_c : std_logic_vector( 1 downto 0) := "11";
signal tx_size_s : std_logic_vector( 1 downto 0);
--
constant tx_command_c : std_logic_vector(23 downto 0) := "010000000000001100000010";
signal tx_command_s : std_logic_vector(23 downto 0);
--
-----------------------------------------------------------------------------
signal pad_data_tx_s : std_logic;
signal tx_start_s : boolean;
signal tx_finished_s : boolean;
signal rx_en_s,
rx_done_s,
rx_data_ok_s : boolean;
signal rx_data_s : buttons_t;
begin
rx_size_s <= rx_size_c;
tx_size_s <= tx_size_c;
tx_command_s <= tx_command_c;
ctrl_b : gcpad_ctrl
generic map (
reset_level_g => reset_level_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
pad_request_i => pad_request_i,
pad_avail_o => pad_avail_o,
rx_timeout_o => open,
tx_start_o => tx_start_s,
tx_finished_i => tx_finished_s,
rx_en_o => rx_en_s,
rx_done_i => rx_done_s,
rx_data_ok_i => rx_data_ok_s
);
tx_b : gcpad_tx
generic map (
reset_level_g => reset_level_g,
clocks_per_1us_g => clocks_per_1us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
pad_data_o => pad_data_tx_s,
tx_start_i => tx_start_s,
tx_finished_o => tx_finished_s,
tx_size_i => tx_size_s,
tx_command_i => tx_command_s
);
rx_b : gcpad_rx
generic map (
reset_level_g => reset_level_g,
clocks_per_1us_g => clocks_per_1us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
rx_en_i => rx_en_s,
rx_done_o => rx_done_s,
rx_data_ok_o => rx_data_ok_s,
rx_size_i => rx_size_s,
pad_data_i => pad_data_io,
rx_data_o => rx_data_s
);
-----------------------------------------------------------------------------
-- Open collector driver to pad data
-----------------------------------------------------------------------------
pad_data_io <= '0'
when pad_data_tx_s = '0' else
'Z';
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
but_a_o <= rx_data_s(pos_a_c);
but_b_o <= rx_data_s(pos_b_c);
but_x_o <= rx_data_s(pos_x_c);
but_y_o <= rx_data_s(pos_y_c);
but_z_o <= rx_data_s(pos_z_c);
but_start_o <= rx_data_s(pos_start_c);
but_tl_o <= rx_data_s(pos_tl_c);
but_tr_o <= rx_data_s(pos_tr_c);
but_left_o <= rx_data_s(pos_left_c);
but_right_o <= rx_data_s(pos_right_c);
but_up_o <= rx_data_s(pos_up_c);
but_down_o <= rx_data_s(pos_down_c);
ana_joy_x_o <= rx_data_s(joy_x_high_c downto joy_x_low_c);
ana_joy_y_o <= rx_data_s(joy_y_high_c downto joy_y_low_c);
ana_c_x_o <= rx_data_s(c_x_high_c downto c_x_low_c);
ana_c_y_o <= rx_data_s(c_y_high_c downto c_y_low_c);
ana_l_o <= rx_data_s(l_high_c downto l_low_c);
ana_r_o <= rx_data_s(r_high_c downto r_low_c);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/10/09 17:03:43 arniml
-- enhance handshaking between gcpad_rx and gcpad_ctrl
--
-- Revision 1.3 2004/10/09 00:33:55 arniml
-- shift rx_data to button assignment to toplevel
--
-- Revision 1.2 2004/10/08 20:51:59 arniml
-- turn rx and tx size into bytes instead of bits
--
-- Revision 1.1 2004/10/07 21:23:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | b1e35375c1a19bff650062af5a33048b | 0.516393 | 3.411038 | false | false | false | false |
RECS-Tsukuba/fpga-filter-hardware | user_app.vhd | 1 | 10,457 | --
-- user_app.vhd - user application code
--
-- This module is an implementation of the 'user_app' component that can be
-- commanded to perform a memory test of some or all of the memory banks.
--
-- SYNTHESIZABLE
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
library work;
use work.memif.all;
use work.memory_common.all;
use work.user_defs.all;
entity user_app is
port(
rst : in std_logic; -- Reset from memory clock domain
clk : in std_logic; -- Clock from memory clock domain
-- To/from local bus interface
reg_in : in std_logic_vector(31 downto 0); -- Incoming register write values
reg_wr : in std_logic_vector(255 downto 0); -- Byte write enables for 'reg_in'
reg_out : out std_logic_vector(2047 downto 0); -- Outgoing register values
-- To/from memory banks
valid : in control_vector_t(max_num_bank - 1 downto 0);
q : in data_vector_t(max_num_bank - 1 downto 0);
qtag : in tag_vector_t(max_num_bank - 1 downto 0);
ready : in control_vector_t(max_num_bank - 1 downto 0);
req : out control_vector_t(max_num_bank - 1 downto 0);
ce : out control_vector_t(max_num_bank - 1 downto 0);
w : out control_vector_t(max_num_bank - 1 downto 0);
a : out address_vector_t(max_num_bank - 1 downto 0);
tag : out tag_vector_t(max_num_bank - 1 downto 0);
d : out data_vector_t(max_num_bank - 1 downto 0);
be : out be_vector_t(max_num_bank - 1 downto 0));
end entity;
architecture mixed of user_app is
type user_vector_t is array(0 to 63) of std_logic_vector(31 downto 0);
signal user_out : user_vector_t;
type user_wr_vector_t is array(0 to 63) of std_logic_vector(3 downto 0);
signal user_wr : user_wr_vector_t;
signal user_enable : std_logic;
signal refresh : std_logic;
signal image_size : std_logic_vector(rd_width(0)- 1 downto 0);
signal image_width : std_logic_vector(9 downto 0);
signal user_flag : std_logic;
signal pos_x : std_logic_vector(9 downto 0);
signal pos_y : std_logic_vector(9 downto 0);
signal debug_signal0 : std_logic_vector(rd_width(0)- 1 downto 0);
signal debug_signal1 : std_logic_vector(rd_width(0)- 1 downto 0);
signal debug_signal2 : std_logic_vector(rd_width(0)- 1 downto 0);
signal debug_signal3 : std_logic_vector(rd_width(0)- 1 downto 0);
signal is_end : std_logic;
constant user_bank_present : boolean_vector_t :=
(0 => true, 1 => true, others => false);
component filter
generic(
ADDRESS_WIDTH : natural;
DATA_WIDTH : natural;
TAG_WIDTH : natural);
port(
request0 : out std_logic;
request1 : out std_logic;
command_entry0 : out std_logic;
command_entry1 : out std_logic;
write_enable1 : out std_logic;
address0 : out std_logic_vector(max_address_width - 1 downto 0);
address1 : out std_logic_vector(max_address_width - 1 downto 0);
tag0 : out std_logic_vector(tag_width - 1 downto 0);
data_out1 : out std_logic_vector(bank_width(1) - 1 downto 0);
is_end : out std_logic;
debug_signal0 : out std_logic_vector(31 downto 0);
debug_signal1 : out std_logic_vector(31 downto 0);
debug_signal2 : out std_logic_vector(31 downto 0);
debug_signal3 : out std_logic_vector(31 downto 0);
valid0 : in std_logic;
valid1 : in std_logic;
query0 : in std_logic_vector(bank_width(0) - 1 downto 0);
qtag0 : in std_logic_vector(tag_width - 1 downto 0);
ready0 : in std_logic;
ready1 : in std_logic;
image_size : in std_logic_vector(32 - 1 downto 0);
image_width : in std_logic_vector(9 downto 0);
user_flag : in std_logic;
pos_x : in std_logic_vector(9 downto 0);
pos_y : in std_logic_vector(9 downto 0);
refresh : in std_logic;
reset : in std_logic;
clock : in std_logic);
end component;
begin
-- Divide 'reg_wr' into an array of 64 x 4-bit vectors for easy access
gen_user_in : for i in 0 to 63 generate
user_wr(i) <= reg_wr(4 * i + 3 downto 4 * i);
end generate;
-- Combine the 64 32-bit registers of 'user_out' into the vector 'reg_out'
gen_reg_out : for i in 0 to 63 generate
reg_out(32 * i + 31 downto 32 * i) <= user_out(i);
end generate;
set_refresh: process(rst, clk) begin
if rst = '1' then
refresh <= '0';
elsif clk'event and clk = '1' then
if user_wr(0)(0) = '1' then
refresh <= reg_in(0);
end if;
end if;
end process;
set_user_enable: process(rst, clk) begin
if rst = '1' then
user_enable <= '0';
elsif clk'event and clk = '1' then
if user_wr(1)(0) = '1' then
user_enable <= reg_in(0);
end if;
end if;
end process;
set_image_size : process(rst, clk) begin
if rst = '1' then
image_size <= (others => '0');
elsif clk'event and clk = '1' then
for j in 0 to 3 loop
if user_wr(2)(j) = '1' then
image_size(8 * j + 7 downto 8 * j) <= reg_in(8 * j + 7 downto 8 * j);
end if;
end loop;
end if;
end process;
set_image_width : process(rst, clk) begin
if rst = '1' then
image_width <= (others => '0');
elsif clk'event and clk = '1' then
if user_wr(3)(0) = '1' then
image_width(7 downto 0) <= reg_in(7 downto 0);
end if;
if user_wr(3)(1) = '1' then
image_width(9 downto 8) <= reg_in(9 downto 8);
end if;
end if;
end process;
set_user_flag : process(rst, clk) begin
if rst = '1' then
user_flag <= '0';
elsif clk'event and clk = '1' then
if user_wr(4)(0) = '1' then
user_flag <= reg_in(0);
end if;
end if;
end process;
set_pos_x : process(rst, clk) begin
if rst = '1' then
pos_x <= (others => '0');
elsif clk'event and clk = '1' then
if user_wr(5)(0) = '1' then
pos_x(7 downto 0) <= reg_in(7 downto 0);
end if;
if user_wr(5)(1) = '1' then
pos_x(9 downto 8) <= reg_in(9 downto 8);
end if;
end if;
end process;
set_pos_y : process(rst, clk) begin
if rst = '1' then
pos_y <= (others => '0');
elsif clk'event and clk = '1' then
if user_wr(6)(0) = '1' then
pos_y(7 downto 0) <= reg_in(7 downto 0);
end if;
if user_wr(6)(1) = '1' then
pos_y(9 downto 8) <= reg_in(9 downto 8);
end if;
end if;
end process;
user_out(0)(0) <= refresh;
user_out(0)(31 downto 1) <= (others => '0');
user_out(1)(0) <= user_enable;
user_out(1)(31 downto 1) <= (others => '0');
user_out(2) <= image_size;
user_out(3)(9 downto 0) <= image_width;
user_out(3)(31 downto 10) <= (others => '0');
user_out(4)(0) <= user_flag;
user_out(4)(31 downto 1) <= (others => '0');
user_out(5)(9 downto 0) <= pos_x;
user_out(5)(31 downto 10) <= (others => '0');
user_out(6)(9 downto 0) <= pos_y;
user_out(6)(31 downto 10) <= (others => '0');
user_out(32)(0) <= is_end;
user_out(32)(31 downto 1) <= (others => '0');
user_out(60) <= debug_signal0;
user_out(61) <= debug_signal1;
user_out(62) <= debug_signal2;
user_out(63) <= debug_signal3;
-- Unused regisers return undefined
user_out(7 to 31) <= (others => (others => '0'));
-- user_out(33 to 61) <= (others => (others => '-'));
user_out(33 to 59) <= (others => (others => '0'));
w(0) <= '0';
tag(1) <= (others => '0');
d(0) <= (others => '0');
d(1)(max_data_width - 1 downto bank_width(1)) <= (others => '0');
be(0) <= (others => '1');
be(1) <= (others => '1');
filter0 : filter
generic map(
ADDRESS_WIDTH => max_address_width,
DATA_WIDTH => bank_width(0),
TAG_WIDTH => tag_width)
port map(
request0 => req(0),
request1 => req(1),
command_entry0 => ce(0),
command_entry1 => ce(1),
write_enable1 => w(1),
address0 => a(0),
address1 => a(1),
tag0 => tag(0),
data_out1 => d(1)(bank_width(0) - 1 downto 0),
is_end => is_end,
debug_signal0 => debug_signal0,
debug_signal1 => debug_signal1,
debug_signal2 => debug_signal2,
debug_signal3 => debug_signal3,
valid0 => valid(0),
valid1 => valid(1),
query0 => q(0)(bank_width(0) - 1 downto 0),
qtag0 => qtag(0),
ready0 => ready(0),
ready1 => ready(1),
image_size => image_size,
image_width => image_width,
user_flag => user_flag,
pos_x => pos_x,
pos_y => pos_y,
refresh => refresh,
reset => rst,
clock => clk);
gen_memory_test : for i in 0 to max_num_bank - 1 generate
-- Generate dummy code for nonexistent memory banks
gen_dummy : if not user_bank_present(i) generate
req(i) <= '0';
ce(i) <= '0';
w(i) <= '-';
a(i) <= (others => '-');
tag(i) <= (others => '-');
d(i) <= (others => '-');
be(i) <= (others => '-');
end generate;
end generate;
-- gen_memory_test : for i in 0 to max_num_bank - 1 generate
-- req(i) <= '0';
-- ce(i) <= '0';
-- w(i) <= '-';
-- a(i) <= (others => '-');
-- tag(i) <= (others => '-');
-- d(i) <= (others => '-');
-- be(i) <= (others => '-');
-- end generate;
end architecture;
| gpl-3.0 | 421ac49fdd2b25b97fceac32d62b887c | 0.506264 | 3.368879 | false | false | false | false |
freecores/gamepads | gcpad/rtl/vhdl/gcpad_full.vhd | 1 | 6,749 | -------------------------------------------------------------------------------
--
-- GCpad controller core
--
-- $Id: gcpad_full.vhd,v 1.1 2004-10-10 17:25:08 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gcpad_full is
generic (
-- active level of reset_i
reset_level_g : integer := 0;
-- number of clk_i periods during 1us
clocks_per_1us_g : integer := 2
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
-- Pad Communication Interface --------------------------------------------
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
pad_timeout_o : out std_logic;
tx_size_i : in std_logic_vector( 1 downto 0);
tx_command_i : in std_logic_vector(23 downto 0);
rx_size_i : in std_logic_vector( 3 downto 0);
rx_data_o : out std_logic_vector(63 downto 0);
-- Gamepad Interface ------------------------------------------------------
pad_data_io : inout std_logic
);
end gcpad_full;
use work.gcpad_pack.all;
architecture struct of gcpad_full is
component gcpad_ctrl
generic (
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_request_i : in std_logic;
pad_avail_o : out std_logic;
rx_timeout_o : out std_logic;
tx_start_o : out boolean;
tx_finished_i : in boolean;
rx_en_o : out boolean;
rx_done_i : in boolean;
rx_data_ok_i : in boolean
);
end component;
component gcpad_tx
generic (
reset_level_g : natural := 0;
clocks_per_1us_g : natural := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_data_o : out std_logic;
tx_start_i : in boolean;
tx_finished_o : out boolean;
tx_size_i : in std_logic_vector( 1 downto 0);
tx_command_i : in std_logic_vector(23 downto 0)
);
end component;
component gcpad_rx
generic (
reset_level_g : integer := 0;
clocks_per_1us_g : integer := 2
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
rx_en_i : in boolean;
rx_done_o : out boolean;
rx_data_ok_o : out boolean;
rx_size_i : in std_logic_vector(3 downto 0);
pad_data_i : in std_logic;
rx_data_o : out buttons_t
);
end component;
signal pad_data_tx_s : std_logic;
signal tx_start_s : boolean;
signal tx_finished_s : boolean;
signal rx_en_s,
rx_done_s,
rx_data_ok_s : boolean;
begin
ctrl_b : gcpad_ctrl
generic map (
reset_level_g => reset_level_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
pad_request_i => pad_request_i,
pad_avail_o => pad_avail_o,
rx_timeout_o => pad_timeout_o,
tx_start_o => tx_start_s,
tx_finished_i => tx_finished_s,
rx_en_o => rx_en_s,
rx_done_i => rx_done_s,
rx_data_ok_i => rx_data_ok_s
);
tx_b : gcpad_tx
generic map (
reset_level_g => reset_level_g,
clocks_per_1us_g => clocks_per_1us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
pad_data_o => pad_data_tx_s,
tx_start_i => tx_start_s,
tx_finished_o => tx_finished_s,
tx_size_i => tx_size_i,
tx_command_i => tx_command_i
);
rx_b : gcpad_rx
generic map (
reset_level_g => reset_level_g,
clocks_per_1us_g => clocks_per_1us_g
)
port map (
clk_i => clk_i,
reset_i => reset_i,
rx_en_i => rx_en_s,
rx_done_o => rx_done_s,
rx_data_ok_o => rx_data_ok_s,
rx_size_i => rx_size_i,
pad_data_i => pad_data_io,
rx_data_o => rx_data_o
);
-----------------------------------------------------------------------------
-- Open collector driver to pad data
-----------------------------------------------------------------------------
pad_data_io <= '0'
when pad_data_tx_s = '0' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | e156f4d76785d3568256c626398d0525 | 0.527337 | 3.739058 | false | false | false | false |
akshayp/college-projects | vhdl/pong/video_PLL.vhd | 1 | 9,568 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: video_PLL.vhd
-- Megafunction Name(s):
-- altpll
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.2 Build 156 11/29/2004 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY video_PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END video_PLL;
ARCHITECTURE SYN OF video_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_duty_cycle : NATURAL;
lpm_type : STRING;
clk0_multiply_by : NATURAL;
inclk0_input_frequency : NATURAL;
clk0_divide_by : NATURAL;
pll_type : STRING;
intended_device_family : STRING;
operation_mode : STRING;
compensate_clock : STRING;
clk0_phase_shift : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_duty_cycle => 50,
lpm_type => "altpll",
clk0_multiply_by => 1007,
inclk0_input_frequency => 20833,
clk0_divide_by => 1920,
pll_type => "AUTO",
intended_device_family => "Cyclone",
operation_mode => "NORMAL",
compensate_clock => "CLK0",
clk0_phase_shift => "0"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.175"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1920"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT VCC "@inclk[1..0]"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_PLL_inst.vhd TRUE FALSE
| mit | 11e5b4f12381d947c7799a04de9e4137 | 0.680811 | 3.422031 | false | false | false | false |
Subsets and Splits