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wifidar/wifidar_fpga | src/uart.vhd | 2 | 1,753 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity uart is
generic(
clk_freq: integer := 50000000;
baud_rate: integer := 115200
);
port(
uart_tx: out std_logic;
data_in: in std_logic_vector(7 downto 0);
ready: out std_logic;
send_data: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end uart;
architecture behavioral of uart is
type uart_state is (reset,waiting,sending);
signal curr_state: uart_state;
signal clock_divide: integer range 0 to 5208 := 0;
signal slow_clock: std_logic := '0';
signal uart_tx_sig: std_logic;
signal current_bit: integer range 0 to 9;
begin
slower_clock: process(clk,rst)
begin
if(rst = '1') then
clock_divide <= 0;
slow_clock <= '0';
elsif(rising_edge(clk)) then
clock_divide <= clock_divide + 1;
if(clock_divide = 215) then -- 651->38400 baud
clock_divide <= 0;
slow_clock <= not slow_clock;
end if;
end if;
end process;
main_uart: process(slow_clock,rst)
begin
if(rst = '1') then
curr_state <= reset;
elsif(rising_edge(slow_clock)) then
case curr_state is
when reset =>
uart_tx_sig <= '1';
curr_state <= waiting;
when waiting =>
ready <= '1';
current_bit <= 0;
uart_tx_sig <= '1';
if(send_data = '1') then
curr_state <= sending;
end if;
when sending =>
ready <= '0';
current_bit <= current_bit + 1;
if(current_bit = 9) then
current_bit <= 0;
uart_tx_sig <= '1';
curr_state <= waiting;
elsif(current_bit = 0) then
uart_tx_sig <= '0';
else
uart_tx_sig <= data_in(current_bit - 1);
end if;
end case;
end if;
end process;
uart_tx <= uart_tx_sig;
end behavioral;
| mit | 0ce34f3ce7969a1edc9c418f53511b2e | 0.6081 | 2.791401 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_extract_udp_header.vhd | 1 | 4,826 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_extract_udp_header.vhd - Behavioral
--
-- Description: Extract the UDP header fields from a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_extract_udp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
udp_src_port : out STD_LOGIC_VECTOR (15 downto 0);
udp_dst_port : out STD_LOGIC_VECTOR (15 downto 0);
udp_length : out STD_LOGIC_VECTOR (15 downto 0);
udp_checksum : out STD_LOGIC_VECTOR (15 downto 0));
end udp_extract_udp_header;
architecture Behavioral of udp_extract_udp_header is
signal count : unsigned(3 downto 0) := (others => '0');
signal i_udp_src_port : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_udp_dst_port : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_udp_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_udp_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
-- 'data_count' us used for trimming off padding on the end of the UDP packet
signal data_count : unsigned(11 downto 0) := (others => '0');
begin
udp_length <= i_udp_length;
udp_checksum <= i_udp_checksum;
udp_dst_port <= i_udp_dst_port;
udp_src_port <= i_udp_src_port;
process(clk)
begin
if rising_edge(clk) then
data_out <= data_in;
if data_valid_in = '1' then
case count is
when "0000" => i_udp_src_port(15 downto 8) <= data_in;
when "0001" => i_udp_src_port( 7 downto 0) <= data_in;
when "0010" => i_udp_dst_port(15 downto 8) <= data_in;
when "0011" => i_udp_dst_port( 7 downto 0) <= data_in;
when "0100" => i_udp_length(15 downto 8) <= data_in;
when "0101" => i_udp_length( 7 downto 0) <= data_in;
when "0110" => i_udp_checksum(15 downto 8) <= data_in;
when "0111" => i_udp_checksum( 7 downto 0) <= data_in;
when others => if data_count < unsigned(i_udp_length) then
data_valid_out <= data_valid_in;
data_out <= data_in;
else
data_valid_out <= '0';
data_out <= data_in;
end if;
end case;
if count /= "1111" then
count <= count+1;
end if;
data_count <= data_count + 1;
else
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
data_count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| mit | 63e124069c5039d1ad58df9492535dcb | 0.518649 | 4.171132 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/FPGA_webserver.vhd | 1 | 25,227 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: FPGA_webserver - Behavioral
--
-- Description: Top level of my HDL webserver
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FPGA_webserver is
Port ( clk100MHz : in std_logic; -- system clock
switches : in std_logic_vector(3 downto 0);
leds : out std_logic_vector(7 downto 0);
-- Ethernet Control signals
eth_int_b : in std_logic; -- interrupt
eth_pme_b : in std_logic; -- power management event
eth_rst_b : out std_logic := '0'; -- reset
-- Ethernet Management interface
eth_mdc : out std_logic := '0';
eth_mdio : inout std_logic := '0';
-- Ethernet Receive interface
eth_rxck : in std_logic;
eth_rxctl : in std_logic;
eth_rxd : in std_logic_vector(3 downto 0);
-- Ethernet Transmit interface
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0')
);
end FPGA_webserver;
architecture Behavioral of FPGA_webserver is
constant our_mac : std_logic_vector(47 downto 0) := x"AB_89_67_45_23_02"; -- NOTE this is 02:23:45:67:89:AB
constant our_ip : std_logic_vector(31 downto 0) := x"0A_00_00_0A"; -- NOTE octets are reversed
constant our_netmask : std_logic_vector(31 downto 0) := x"00_FF_FF_FF"; -- NOTE octets are reversed
constant our_gateway : std_logic_vector(31 downto 0) := x"FE_00_00_0A"; -- NOTE octets are reversed
signal phy_ready : std_logic := '0';
-----------------------------
-- For the clocking
-----------------------------
component clocking is
Port ( clk100MHz : in STD_LOGIC;
clk125MHz : out STD_LOGIC;
clk125MHz90 : out STD_LOGIC);
end component;
signal clk125MHz : STD_LOGIC;
signal clk125MHz90 : STD_LOGIC;
component reset_controller is
Port ( clk125mhz : in STD_LOGIC;
phy_ready : out STD_LOGIC;
eth_rst_b : out STD_LOGIC);
end component;
--------------------------------------
-- To receive the raw data from the PHY
-- (runs in the eth_rxck clock domain)
--------------------------------------
component receive_raw_data is
Port ( eth_rxck : in STD_LOGIC;
eth_rxctl : in STD_LOGIC;
eth_rxd : in STD_LOGIC_VECTOR (3 downto 0);
rx_data_enable : out STD_LOGIC;
rx_data : out STD_LOGIC_VECTOR (7 downto 0);
rx_data_present : out STD_LOGIC;
rx_data_error : out STD_LOGIC);
end component ;
signal rx_data_enable : STD_LOGIC;
signal rx_data : STD_LOGIC_VECTOR (7 downto 0);
signal rx_data_present : STD_LOGIC;
signal rx_data_error : STD_LOGIC;
-------------------------------------------------------
-- A FIFO to pass the data into the 125MHz clock domain
-------------------------------------------------------
component fifo_rxclk_to_clk125MHz is
Port ( rx_clk : in STD_LOGIC;
rx_write : in STD_LOGIC := '1';
rx_data : in STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
rx_data_present : in STD_LOGIC := '0';
rx_data_error : in STD_LOGIC := '0';
clk125Mhz : in STD_LOGIC;
empty : out STD_LOGIC;
read : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (7 downto 0);
data_present : out STD_LOGIC;
data_error : out STD_LOGIC);
end component;
signal input_empty : STD_LOGIC;
signal input_read : STD_LOGIC;
signal input_data : STD_LOGIC_VECTOR (7 downto 0);
signal input_data_present : STD_LOGIC;
signal input_data_error : STD_LOGIC;
component main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic;
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_checksum : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal udp_rx_valid : std_logic := '0';
signal udp_rx_data : std_logic_vector(7 downto 0) := (others => '0');
signal udp_rx_src_ip : std_logic_vector(31 downto 0) := (others => '0');
signal udp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_rx_dst_broadcast : std_logic := '0';
signal udp_rx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_rx_valid_last : std_logic := '0';
component udp_test_source is
Port (
clk : in STD_LOGIC;
-- data to be sent over UDP
udp_tx_busy : in std_logic := '0';
udp_tx_valid : out std_logic := '0';
udp_tx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : out std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
component udp_test_sink is
Port (
clk : in STD_LOGIC;
-- data received over UDP
udp_rx_valid : in std_logic := '0';
udp_rx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : in std_logic := '0';
udp_rx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
leds : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal udp_tx_busy : std_logic;
signal udp_tx_valid : std_logic;
signal udp_tx_data : std_logic_vector(7 downto 0);
signal udp_tx_src_port : std_logic_vector(15 downto 0);
signal udp_tx_dst_mac : std_logic_vector(47 downto 0);
signal udp_tx_dst_ip : std_logic_vector(31 downto 0);
signal udp_tx_dst_port : std_logic_vector(15 downto 0);
-- data received over TCP/IP
signal tcp_rx_data_valid : std_logic := '0';
signal tcp_rx_data : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_rx_hdr_valid : std_logic := '0';
signal tcp_rx_src_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_rx_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_rx_flag_urg : std_logic := '0';
signal tcp_rx_flag_ack : std_logic := '0';
signal tcp_rx_flag_psh : std_logic := '0';
signal tcp_rx_flag_rst : std_logic := '0';
signal tcp_rx_flag_syn : std_logic := '0';
signal tcp_rx_flag_fin : std_logic := '0';
signal tcp_rx_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
signal tcp_tx_busy : std_logic := '0';
signal tcp_tx_data_valid : std_logic := '0';
signal tcp_tx_data : std_logic_vector(7 downto 0) := (others => '0');
signal tcp_tx_hdr_valid : std_logic := '0';
signal tcp_tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal tcp_tx_window : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_tx_flag_urg : std_logic := '0';
signal tcp_tx_flag_ack : std_logic := '0';
signal tcp_tx_flag_psh : std_logic := '0';
signal tcp_tx_flag_rst : std_logic := '0';
signal tcp_tx_flag_syn : std_logic := '0';
signal tcp_tx_flag_fin : std_logic := '0';
signal tcp_tx_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal tcp_engine_status : std_logic_vector(7 downto 0) := (others => '0');
component tcp_engine is
port ( clk : in STD_LOGIC;
status : out std_logic_vector(7 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : in std_logic := '0';
tcp_rx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : in std_logic := '0';
tcp_rx_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : in std_logic := '0';
tcp_rx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : in std_logic := '0';
tcp_rx_flag_ack : in std_logic := '0';
tcp_rx_flag_psh : in std_logic := '0';
tcp_rx_flag_rst : in std_logic := '0';
tcp_rx_flag_syn : in std_logic := '0';
tcp_rx_flag_fin : in std_logic := '0';
tcp_rx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
tcp_tx_busy : in std_logic := '0';
tcp_tx_data_valid : out std_logic := '0';
tcp_tx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : out std_logic := '0';
tcp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : out std_logic := '0';
tcp_tx_flag_ack : out std_logic := '0';
tcp_tx_flag_psh : out std_logic := '0';
tcp_tx_flag_rst : out std_logic := '0';
tcp_tx_flag_syn : out std_logic := '0';
tcp_tx_flag_fin : out std_logic := '0';
tcp_tx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end component;
begin
i_clocking: clocking port map (
clk100MHz => clk100MHz,
clk125MHz => clk125MHz,
clk125MHz90 => clk125MHz90);
----------------------------------------
-- Control reseting the PHY
----------------------------------------
i_reset_controller: reset_controller port map (
clk125mhz => clk125mhz,
phy_ready => phy_ready,
eth_rst_b => eth_rst_b);
i_receive_raw_data: receive_raw_data port map (
eth_rxck => eth_rxck,
eth_rxctl => eth_rxctl,
eth_rxd => eth_rxd,
rx_data_enable => rx_data_enable,
rx_data => rx_data,
rx_data_present => rx_data_present,
rx_data_error => rx_data_error);
i_fifo_rxclk_to_clk125MHz: fifo_rxclk_to_clk125MHz port map (
rx_clk => eth_rxck,
rx_write => rx_data_enable,
rx_data => rx_data,
rx_data_present => rx_data_present,
rx_data_error => rx_data_error,
clk125Mhz => clk125Mhz,
empty => input_empty,
read => input_read,
data => input_data,
data_present => input_data_present,
data_error => input_data_error);
i_main_design: main_design generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip
) port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => open,
-- data received over UDP
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port,
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port,
-- data received over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_checksum => tcp_rx_checksum,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_checksum => tcp_tx_checksum,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
--------------------------------
-- Modules to check UDP TX & RX
--------------------------------
i_udp_test_source: udp_test_source port map (
clk => clk125MHz,
-- Data to be sent over UDP
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port);
i_udp_test_sink: udp_test_sink port map (
clk => clk125MHz,
-- data received over UDP
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port,
-- Where to show the data
leds => open);
process(clk125Mhz)
begin
if tcp_rx_hdr_valid = '1' then
leds <= tcp_engine_status;
end if;
end process;
i_tcp_engine: tcp_engine port map (
clk => clk125MHz,
-- data received over TCP/IP
status => tcp_engine_status,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr);
end Behavioral;
| mit | fe301fac8b4cd9b2a323cd4356807e1e | 0.497285 | 3.388449 | false | false | false | false |
alexkernphysiker/JPET-FPGA-parser | packet_simulation/TDC_parser.vhd | 1 | 4,648 | -- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TDC_parser is
port(
clock:in std_logic;
in_data:in std_logic;
dataWORD:in std_logic_vector(31 downto 0);
channel_offset:in std_logic_vector(15 downto 0);
eventID: in std_logic_vector(31 downto 0);
triggerID: in std_logic_vector(31 downto 0);
out_data: out std_logic;
time_isrising:out std_logic;
time_channel: out std_logic_vector(15 downto 0);
time_epoch: out std_logic_vector(27 downto 0);
time_fine: out std_logic_vector(9 downto 0);
time_coasser:out std_logic_vector(10 downto 0)
);
end TDC_parser;
architecture Behavioral of TDC_parser is
signal saved_channel_offset: std_logic_vector(15 downto 0);
signal saved_eventID: std_logic_vector(31 downto 0);
signal saved_triggerID: std_logic_vector(31 downto 0);
signal reset:std_logic:='0';
signal parse:std_logic:='0';
signal offset:integer:=0;
type tdc_state is(IDLE,HEADER_READ,EPOCH_READ);
signal current_tdc_state,next_tdc_state:tdc_state:=IDLE;
begin
state_change:process(reset,in_data)
begin
if rising_edge(clock) then
if reset='1' then
current_tdc_state<=IDLE;
elsif in_data='0' then
current_tdc_state<=next_tdc_state;
end if;
end if;
end process state_change;
trigger_change_check:process(clock)
begin
if rising_edge(clock) then
if(not(saved_eventID=eventID))or
(not(saved_triggerID=triggerID))or
(not(saved_channel_offset=channel_offset))then
reset<='1';
end if;
if(reset='1')and(current_tdc_state=IDLE)then
saved_eventID<=eventID;
saved_triggerID<=triggerID;
saved_channel_offset<=channel_offset;
reset<='0';
end if;
end if;
end process trigger_change_check;
in_data_to_parse:process(in_data, clock)
begin
if rising_edge(clock) then
parse <= in_data;
end if;
end process in_data_to_parse;
state_machine:process(parse, clock)
variable channel:integer:=0;
begin
if rising_edge(clock) then
if parse = '1' then
case current_tdc_state is
when IDLE =>
if(dataWORD(31)='0')and(dataWORD(30)='0')and(dataWORD(29)='1')then
next_tdc_state<=HEADER_READ;
for i in 15 downto 0 loop
if dataWORD(i)='1' then
next_tdc_state<=IDLE;
end if;
end loop;
offset<=0;
for i in 15 downto 0 loop
offset<=offset*2;
if channel_offset(i)='1' then
offset<=offset+1;
end if;
end loop;
end if;
when HEADER_READ =>
if(dataWORD(31)='0')and(dataWORD(30)='1')and(dataWORD(29)='1')then
next_tdc_state<=EPOCH_READ;
end if;
when EPOCH_READ =>
if dataWORD(31)='1' then
for i in 9 downto 0 loop
time_fine(i)<=dataWORD(i+12);
end loop;
for i in 10 downto 0 loop
time_coasser(i)<=dataWORD(i);
end loop;
time_isrising<=dataWORD(11);
channel:=0;
for i in 6 downto 0 loop
channel:=channel*2;
if dataWORD(i+22)='1'then
channel:=channel+1;
end if;
end loop;
channel:=channel+offset;
for i in 0 to 15 loop
if channel mod 2 = 1 then
time_channel(i)<='1';
else
time_channel(i)<='0';
end if;
channel:=channel/2;
end loop;
out_data<='1';
end if;
end case;
if(dataWORD(31)='0')and(dataWORD(30)='1')and(dataWORD(29)='1')then
for i in 27 downto 0 loop
time_epoch(i)<=dataWORD(i);
end loop;
end if;
elsif parse = '0' then
out_data<='0';
end if;
end if;
end process state_machine;
end Behavioral;
| gpl-3.0 | 8fdb2b6d090dc97794bcd511573042bd | 0.515275 | 4.031223 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp_engine/tcp_engine_tx_fifo.vhd | 1 | 6,138 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_engine_tx_fifo - Behavioral
--
-- Description: A FIFO for the packet headers, before they have data added
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_tx_fifo is
Port ( clk : in STD_LOGIC;
write_en : in std_logic := '0';
full : out std_logic := '0';
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_addr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_len : in std_logic_vector(10 downto 0) := (others => '0');
read_en : in std_logic := '0';
empty : out std_logic := '0';
out_src_port : out std_logic_vector(15 downto 0) := (others => '0');
out_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_addr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_len : out std_logic_vector(10 downto 0) := (others => '0'));
end tcp_engine_tx_fifo;
architecture Behavioral of tcp_engine_tx_fifo is
component fifo_32 is
port (
clk : in std_logic;
full : out std_logic := '0';
write_en : in std_logic;
data_in : in std_logic_vector;
empty : out std_logic := '0';
read_en : in std_logic;
data_out : out std_logic_vector := (others => '0'));
end component;
signal data_in : std_logic_vector(192 downto 0) := (others => '0');
signal data_out : std_logic_vector(192 downto 0) := (others => '0');
begin
out_data_addr <= data_out(192 downto 177);
out_data_len <= data_out(176 downto 166);
out_src_port <= data_out(165 downto 150);
out_dst_ip <= data_out(149 downto 118);
out_dst_port <= data_out(117 downto 102);
out_seq_num <= data_out(101 downto 70);
out_ack_num <= data_out(69 downto 38);
out_window <= data_out(37 downto 22);
out_flag_urg <= data_out(21);
out_flag_ack <= data_out(20);
out_flag_psh <= data_out(19);
out_flag_rst <= data_out(18);
out_flag_syn <= data_out(17);
out_flag_fin <= data_out(16);
out_urgent_ptr <= data_out(15 downto 0);
data_in <= in_data_addr
& in_data_len
& in_src_port
& in_dst_ip
& in_dst_port
& in_seq_num
& in_ack_num
& in_window
& in_flag_urg
& in_flag_ack
& in_flag_psh
& in_flag_rst
& in_flag_syn
& in_flag_fin
& in_urgent_ptr;
i_generic_fifo: fifo_32
port map (
clk => clk,
full => full,
write_en => write_en,
data_in => data_in,
empty => empty,
read_en => read_en,
data_out => data_out);
end Behavioral;
| mit | cade5e912384227349e7cab49ba414ea | 0.515803 | 3.581097 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx2/wrapper.vhdl | 1 | 3,343 | --
-- Wrapper of gtx2 example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
clk_i : in std_logic;
rst_i : in std_logic;
clk_o : out std_logic;
--
rxp_i : in std_logic;
rxn_i : in std_logic;
txp_o : out std_logic;
txn_o : out std_logic;
--
loopback_i: in std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_isk_o : out std_logic_vector(1 downto 0);
tx_data_i : in std_logic_vector(15 downto 0);
tx_isk_i : in std_logic_vector(1 downto 0);
ready_o : out std_logic
);
end entity Wrapper;
architecture Structural of Wrapper is
signal refclk : std_logic_vector(1 downto 0);
signal outclk : std_logic;
signal rx_plllkdet : std_logic;
signal usrclk2 : std_logic;
signal rx_ready, tx_ready : std_logic;
signal loopback : std_logic_vector(2 downto 0);
begin
txoutclk_bufg0_i : BUFG
port map (
I => outclk,
O => usrclk2
);
refclk <= '0' & clk_i;
loopback <= '0' & loopback_i & '0';
gtx_v6_i : entity work.gbt2_gtx
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
GTX_TX_CLK_SOURCE => "RXPLL",
GTX_POWER_SAVE => "0000110100"
)
port map (
LOOPBACK_IN => loopback, -- Near-End PMA Loopback
-- RX 8b10b Decoder
RXCHARISK_OUT => rx_isk_o,
RXDISPERR_OUT => open,
RXNOTINTABLE_OUT => open,
-- RX Comma Detection and Alignment
RXBYTEISALIGNED_OUT => open,
RXENMCOMMAALIGN_IN => '1',
RXENPCOMMAALIGN_IN => '1',
-- RX Data Path interface
RXDATA_OUT => rx_data_o,
RXUSRCLK2_IN => usrclk2,
-- RX Driver
RXN_IN => rxn_i,
RXP_IN => rxp_i,
-- RX PLL Ports
GTXRXRESET_IN => rst_i,
MGTREFCLKRX_IN => refclk,
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rx_plllkdet,
RXRESETDONE_OUT => rx_ready,
-- TX 8b10b Encoder Control Ports
TXCHARISK_IN => tx_isk_i,
-- TX Data Path interface
TXDATA_IN => tx_data_i,
TXOUTCLK_OUT => outclk,
TXUSRCLK2_IN => usrclk2,
-- TX Driver
TXN_OUT => txn_o,
TXP_OUT => txp_o,
TXPOSTEMPHASIS_IN => "00000",
TXPREEMPHASIS_IN => "0000",
-- TX PLL Ports
GTXTXRESET_IN => rst_i,
MGTREFCLKTX_IN => refclk,
PLLTXRESET_IN => '0',
TXPLLLKDET_OUT => open,
TXRESETDONE_OUT => tx_ready
);
clk_o <= usrclk2;
ready_o <= rx_ready and tx_ready and rx_plllkdet;
end architecture Structural;
| bsd-3-clause | e55c921f063a04fbcffaba1da689b645 | 0.466946 | 3.97503 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/gpio.vhd | 2 | 1,862 | -------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity gpio is
port(rst : in std_logic;
clk : in std_logic;
-- GPIO bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- GPIO pin signals
pin_in : in t_gpio_pin_in;
pin_out : out t_gpio_pin_out
);
end gpio;
architecture rtl of gpio is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
bus_out.data <= (others => '0');
elsif rising_edge(clk) then
if bus_in.we = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
pin_out.out_0 <= pin_in.in_0;
pin_out.out_1 <= pin_in.in_1;
pin_out.out_2 <= pin_in.in_2;
pin_out.out_3 <= pin_in.in_3;
pin_out.enb_0 <= pin_in.in_3 and pin_in.in_0;
pin_out.enb_1 <= pin_in.in_0 and pin_in.in_1;
pin_out.enb_2 <= pin_in.in_1 and pin_in.in_2;
pin_out.enb_3 <= pin_in.in_2 and pin_in.in_3;
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | bf73e176a82962ea5fdc57b950c5d558 | 0.402256 | 3.731463 | false | false | false | false |
wifidar/wifidar_fpga | src/adc_controller.vhd | 2 | 1,549 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity adc_controller is
generic(
sample_div: integer := 2500
);
port(
spi_to_amp: out std_logic_vector(3 downto 0);
--uart_to_amp: in std_logic_vector(3 downto 0);
req_adc: out std_logic;
req_amp: out std_logic;
--serial_adc_req: in std_logic;
--serial_amp_req: in std_logic;
rst: in std_logic;
clk: in std_logic
);
end adc_controller;
architecture Behavioral of adc_controller is
type adc_state is (reset_amp,normal_op,update_adc); -- TODO: add serial update and ability to update amplifier
signal curr_state: adc_state := reset_amp;
signal count_before_adc_req: integer range 0 to 50000 := 0;
begin
process(clk,rst)
begin
if(rst = '1') then
curr_state <= reset_amp;
req_adc <= '0';
req_amp <= '0';
spi_to_amp <= (others => '0');
count_before_adc_req <= 0;
elsif(rising_edge(clk)) then
req_amp <= '0';
req_adc <= '0';
case curr_state is
when reset_amp =>
req_amp <= '1';
spi_to_amp <= "0001";
count_before_adc_req <= count_before_adc_req + 1;
if(count_before_adc_req = 24) then
curr_state <= normal_op;
count_before_adc_req <= 750;
end if;
when normal_op =>
count_before_adc_req <= count_before_adc_req + 1;
if(count_before_adc_req = sample_div - 1) then
count_before_adc_req <= 0;
curr_state <= update_adc;
end if;
when update_adc =>
req_adc <= '1';
curr_state <= normal_op;
end case;
end if;
end process;
end Behavioral;
| mit | af8c68e7b5addd318240190f8021e142 | 0.622337 | 2.741593 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx/testbench/top_tb.vhdl | 1 | 1,045 | --
-- Xilinx ml605 Minimal Transceiver Testbench
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Top_tb is
end entity Top_tb;
architecture Structural of Top_tb is
constant PERIOD : time := 5 ns;
signal clk, nclk, rst : std_logic;
signal stop : boolean;
signal ready : std_logic;
signal dips : std_logic_vector(7 downto 0):=(others => '0');
begin
nclk <= not(clk);
do_clk: Clock
generic map(PERIOD => PERIOD, RESET_CLKS => 15.0)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: entity work.top
port map(
rst_i => rst,
clk_p_i => clk,
clk_n_i => nclk,
sma_rx_p_i => '0',
sma_rx_n_i => '0',
sma_tx_p_o => open,
sma_tx_n_o => open,
pbc_i => '0',
dips_i => "11000011",
leds_o => open
);
end architecture Structural;
| bsd-3-clause | 5adc2d434576b488888476984bae13c3 | 0.554067 | 3.205521 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/icmp/icmp_build_reply.vhd | 1 | 11,819 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: icmp_build_reply - Behavioral
--
-- Description: Build the ICMP reply packet by adding headers to the data.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity icmp_build_reply is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
ether_is_ipv4 : in STD_LOGIC;
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0);
ip_version : in STD_LOGIC_VECTOR (3 downto 0);
ip_type_of_service : in STD_LOGIC_VECTOR (7 downto 0);
ip_length : in STD_LOGIC_VECTOR (15 downto 0);
ip_identification : in STD_LOGIC_VECTOR (15 downto 0);
ip_flags : in STD_LOGIC_VECTOR (2 downto 0);
ip_fragment_offset : in STD_LOGIC_VECTOR (12 downto 0);
ip_ttl : in STD_LOGIC_VECTOR (7 downto 0);
ip_protocol : in STD_LOGIC_VECTOR (7 downto 0);
ip_checksum : in STD_LOGIC_VECTOR (15 downto 0);
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0);
ip_dest_ip : in STD_LOGIC_VECTOR (31 downto 0);
icmp_type : in STD_LOGIC_VECTOR (7 downto 0);
icmp_code : in STD_LOGIC_VECTOR (7 downto 0);
icmp_checksum : in STD_LOGIC_VECTOR (15 downto 0);
icmp_identifier : in STD_LOGIC_VECTOR (15 downto 0);
icmp_sequence : in STD_LOGIC_VECTOR (15 downto 0));
end icmp_build_reply;
architecture Behavioral of icmp_build_reply is
signal count : unsigned(5 downto 0) := (others => '0');
type t_delay is array( 0 to 42) of std_logic_vector(8 downto 0);
signal delay : t_delay := (others => (others => '0'));
signal flipped_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal flipped_our_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal h_ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_ether_src_mac : STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
signal h_ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal h_icmp_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_icmp_identifier : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal h_icmp_sequence : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal checksum_static1 : unsigned(19 downto 0) := x"04500";
signal checksum_static2 : unsigned(19 downto 0) := x"08001";
signal checksum_part1 : unsigned(19 downto 0) := (others => '0');
signal checksum_part2 : unsigned(19 downto 0) := (others => '0');
signal checksum_part3 : unsigned(19 downto 0) := (others => '0');
signal checksum_part4 : unsigned(19 downto 0) := (others => '0');
signal checksum_final : unsigned(15 downto 0) := (others => '0');
begin
flipped_src_ip <= h_ip_src_ip(7 downto 0) & h_ip_src_ip(15 downto 8) & h_ip_src_ip(23 downto 16) & h_ip_src_ip(31 downto 24);
flipped_our_ip <= our_ip(7 downto 0) & our_ip(15 downto 8) & our_ip(23 downto 16) & our_ip(31 downto 24);
process(clk)
variable v_icmp_check : unsigned (16 downto 0);
begin
if rising_edge(clk) then
-- This splits the IP checksumming over four cycles
checksum_part1 <= checksum_static1 + unsigned(h_ip_identification)
+ unsigned(flipped_src_ip(31 downto 16))
+ unsigned(flipped_src_ip(15 downto 0));
checksum_part2 <= checksum_static2 + unsigned(h_ip_length)
+ unsigned(flipped_our_ip(31 downto 16))
+ unsigned(flipped_our_ip(15 downto 0));
checksum_part3 <= to_unsigned(0,20) + checksum_part1(15 downto 0) + checksum_part1(19 downto 16)
+ checksum_part2(15 downto 0) + checksum_part2(19 downto 16);
checksum_part4 <= to_unsigned(0,20) + checksum_part3(15 downto 0) + checksum_part3(19 downto 16);
checksum_final <= not(checksum_part4(15 downto 0) + checksum_part4(19 downto 16));
if data_valid_in = '1' then
if count /= "101011" then
count <= count+1;
end if;
else
if count = "000000" or count = "101011" then
count <= (others => '0');
else
count <= count+1;
end if;
end if;
if count = 0 and data_valid_in = '1' then
v_icmp_check(15 downto 0) := unsigned(icmp_checksum);
v_icmp_check(16) := '0';
v_icmp_check := v_icmp_check + 8;
v_icmp_check := v_icmp_check + v_icmp_check(16 downto 16);
h_ether_src_mac <= ether_src_mac;
h_ip_src_ip <= ip_src_ip;
h_ip_length <= ip_length;
h_icmp_checksum <= std_logic_vector(v_icmp_check(15 downto 0));
h_icmp_identifier <= icmp_identifier;
h_icmp_sequence <= icmp_sequence;
end if;
if count /= "000000" then
data_valid_out <= '1';
end if;
case count is
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
-- when "000000" => data_out <= (others => '0'); data_valid_out <= '0';
when "000001" => data_out <= h_ether_src_mac( 7 downto 0);
when "000010" => data_out <= h_ether_src_mac(15 downto 8);
when "000011" => data_out <= h_ether_src_mac(23 downto 16);
when "000100" => data_out <= h_ether_src_mac(31 downto 24);
when "000101" => data_out <= h_ether_src_mac(39 downto 32);
when "000110" => data_out <= h_ether_src_mac(47 downto 40);
-- Source MAC address
when "000111" => data_out <= our_mac( 7 downto 0);
when "001000" => data_out <= our_mac(15 downto 8);
when "001001" => data_out <= our_mac(23 downto 16);
when "001010" => data_out <= our_mac(31 downto 24);
when "001011" => data_out <= our_mac(39 downto 32);
when "001100" => data_out <= our_mac(47 downto 40);
-- Ethernet frame tyoe
when "001101" => data_out <= x"08"; -- Ether Type 08:00 - IP
when "001110" => data_out <= x"00";
------------------------
-- IP Header
------------------------
when "001111" => data_out <= x"45"; -- Protocol & Header Len
when "010000" => data_out <= x"00";
when "010001" => data_out <= h_ip_length(15 downto 8); -- Length
when "010010" => data_out <= h_ip_length(7 downto 0);
when "010011" => data_out <= h_ip_identification(15 downto 8); -- Identificaiton
when "010100" => data_out <= h_ip_identification(7 downto 0);
when "010101" => data_out <= x"00"; -- Flags and offset
when "010110" => data_out <= x"00";
when "010111" => data_out <= x"80"; -- TTL
when "011000" => data_out <= x"01"; -- Protocol
when "011001" => data_out <= std_logic_vector(checksum_final(15 downto 8));
when "011010" => data_out <= std_logic_vector(checksum_final(7 downto 0));
when "011011" => data_out <= our_ip( 7 downto 0); -- Source IP Address
when "011100" => data_out <= our_ip(15 downto 8);
when "011101" => data_out <= our_ip(23 downto 16);
when "011110" => data_out <= our_ip(31 downto 24);
when "011111" => data_out <= h_ip_src_ip( 7 downto 0); -- Destination IP address
when "100000" => data_out <= h_ip_src_ip(15 downto 8); -- (bounce back to the source)
when "100001" => data_out <= h_ip_src_ip(23 downto 16);
when "100010" => data_out <= h_ip_src_ip(31 downto 24);
-------------------------------------
-- ICMP Header
-------------------------------------
when "100011" => data_out <= x"00"; -- ICMP Type = reply
when "100100" => data_out <= x"00"; -- Code
when "100101" => data_out <= h_icmp_checksum(7 downto 0); -- Checksum
when "100110" => data_out <= h_icmp_checksum(15 downto 8);
when "100111" => data_out <= h_icmp_identifier(7 downto 0); -- Identifier
when "101000" => data_out <= h_icmp_identifier(15 downto 8);
when "101001" => data_out <= h_icmp_sequence(7 downto 0); -- Sequence
when "101010" => data_out <= h_icmp_sequence(15 downto 8);
when others => data_valid_out <= delay(0)(8);
data_out <= delay(0)(7 downto 0);
end case;
delay(0 to delay'high-1) <= delay(1 to delay'high);
delay(delay'high) <= data_valid_in & data_in;
end if;
end process;
end Behavioral;
| mit | 17ea68ee78f8b5f939609af5ced11428 | 0.502411 | 3.971438 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/industrial_output/hdl/industrial_output.vhd | 1 | 10,181 | --
-- Copyright (c) ARMadeus Project 2009
--
-- Wishbone component that drive sn74hc594 8 bits shift register
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : industrial_output.vhd
-- Created on : 08/06/2009
-- Author : Fabien Marteau <[email protected]>
--
-- TODO: adding busy bit on data register to inform operating system
-- that component is sending a value -> done but not tested
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity industrial_output is
---------------------------------------------------------------------------
generic(
id : natural := 1; -- identification register value
wb_size : natural := 16; -- Data port size for wishbone
serial_speed : natural := 1000; -- serial speed in kHz (min : 9, max 133000)
clk_freq : natural := 133000 -- fpga clock speed in kHz
);
port
(
-- Syscon signals
reset : in std_logic ; -- reset
clk : in std_logic ; -- general clock
-- Wishbone signals
wbs_add : in std_logic ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- sn74hc594 signals
reset_n : out std_logic;
rclk : out std_logic;
srclk : out std_logic;
ser : out std_logic;
qh : in std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture industrial_output_1 of industrial_output is
---------------------------------------------------------------------------
-- usefull constant
constant ZERO : std_logic_vector(15 downto 0) := x"0000";
-- state machine
type state_type is (out_void, out_init, out_write_value, out_write_pulse, out_out);
signal state_reg : state_type;
signal next_state: state_type;
-- registers addresses
constant CTRL_DATA : std_logic := '0';
constant ID_ADDR : std_logic := '1';
-- registers
signal data : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal ser_reg : std_logic ;
signal spi_count_reg: natural range 0 to 10;
signal busy_reg : std_logic ;
signal busy_next : std_logic ;
signal data_next : std_logic_vector(7 downto 0);
signal ser_next: std_logic ;
-- spi clock
signal spi_clk : std_logic ;
signal spi_clk_rise : std_logic ;
signal spi_clk_fall : std_logic ;
-- state machine signals
signal data_wrote : std_logic ;
--
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal enable_spi_clk : std_logic ;
begin
wbs_ack <= write_ack or read_ack;
-- read process
read_p : process (clk, reset)
begin
if reset = '1' then
wbs_readdata <= ( others => '0');
elsif rising_edge(clk) then
if (wbs_strobe and (not wbs_write) and wbs_cycle) = '1' then
read_ack <= '1';
case wbs_add is
when CTRL_DATA =>
wbs_readdata <= ZERO(15 downto 9)&busy_reg&data;
when ID_ADDR =>
wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
when others =>
wbs_readdata <= (others => '0');
end case;
else
read_ack <= '0';
wbs_readdata <= (others => '0');
end if;
end if;
end process read_p;
-- write process
write_p : process (clk, reset)
variable wrote_v : std_logic;
begin
if reset = '1' then
data <= (others => '0');
wrote_v := '0';
write_ack <= '0';
elsif rising_edge(clk) then
write_ack <= '0';
data_wrote <= '0';
if (wbs_strobe and wbs_write and wbs_cycle) = '1' then
write_ack <= '1';
data <= wbs_writedata(7 downto 0);
wrote_v := '1';
elsif wrote_v = '1' then
data_wrote <= '1';
wrote_v := '0';
end if;
end if;
end process write_p;
-- clock generator
clock_divider : process (clk, reset)
variable count : natural range 0 to (2**14)-1;
begin
if reset = '1' then
count := 0;
spi_clk <= '0';
spi_clk_rise <= '0';
spi_clk_fall <= '0';
spi_count_reg <= 0;
elsif rising_edge(clk) then
if enable_spi_clk = '1' then
if (count <= (clk_freq / (2*serial_speed))) then
count := count + 1;
spi_clk <= spi_clk;
spi_clk_rise <= '0';
spi_clk_fall <= '0';
else
count := 0;
spi_clk <= not spi_clk;
if spi_clk = '0' then
spi_count_reg <= spi_count_reg + 1;
spi_clk_rise <= '1';
spi_clk_fall <= '0';
else
spi_clk_rise <= '0';
spi_clk_fall <= '1';
end if;
end if;
else
spi_count_reg <= 0;
spi_clk <= '0';
spi_clk_fall <= '0';
spi_clk_rise <= '0';
end if;
end if;
end process clock_divider;
--state register
spi_state_register_p : process (clk, reset)
begin
if reset = '1' then
state_reg <= out_void;
data_reg <= (others => '0');
ser_reg <= '0';
busy_reg <= '0';
elsif rising_edge(clk) then
busy_reg <= busy_next;
state_reg <= next_state;
ser_reg <= ser_next;
data_reg <= data_next;
end if;
end process spi_state_register_p;
-- next-state logic
nstate_p : process( state_reg, spi_clk_fall, spi_clk_rise,
data_wrote,spi_count_reg )
begin
next_state <= state_reg;
case state_reg is
when out_void =>
if data_wrote = '1' then
next_state <= out_init;
end if;
when out_init =>
if spi_clk_fall = '1' then
next_state <= out_write_value;
end if;
when out_write_value =>
if spi_clk_rise = '1' then
next_state <= out_write_pulse;
end if;
when out_write_pulse =>
if (spi_count_reg < 9) and spi_clk_fall = '1' then
next_state <= out_write_value;
elsif (spi_count_reg >= 9) then
next_state <= out_out;
end if;
when out_out =>
if spi_count_reg < 10 then
next_state <= out_out;
else
next_state <= out_void;
end if;
when others =>
next_state <= out_void;
end case;
end process nstate_p;
-- output logic
output_p : process (state_reg, spi_clk, data_reg, ser_reg,
spi_count_reg,data,spi_clk_rise,qh)
begin
ser_next <= ser_reg;
data_next <= data_reg;
case state_reg is
when out_void =>
rclk <= '0';
srclk <= '1';
ser_next <= '0';
enable_spi_clk <= '0';
data_next <= data;
busy_next <= '0';
when out_init =>
rclk <= '0';
srclk <= '1';
ser_next <= '0';
enable_spi_clk <= '1';
busy_next <= '1';
when out_write_value =>
rclk <= '0';
srclk <= spi_clk;
ser_next <= data_reg(7);
if spi_clk_rise = '1' then
data_next <= data_reg(6 downto 0)&qh;
end if;
enable_spi_clk <= '1';
busy_next <= '1';
when out_write_pulse =>
rclk <= '0';
srclk <= spi_clk;
ser_next <= ser_reg;
data_next <= data_reg;
enable_spi_clk <= '1';
busy_next <= '1';
when out_out =>
rclk <= '1'; -- refresh output
srclk <= '1';
ser_next <= ser_reg;
data_next <= data_reg;
enable_spi_clk <= '1';
busy_next <= '1';
when others =>
rclk <= '0';
srclk <= '1';
ser_next <= '0';
enable_spi_clk <= '0';
busy_next <= '0';
end case;
end process output_p;
ser <= ser_reg;
reset_n <= '1';
end architecture industrial_output_1;
| lgpl-2.1 | 89f1e574fb76930818ad8e708f85dd16 | 0.448679 | 4.181109 | false | false | false | false |
alexkernphysiker/JPET-FPGA-parser | packet_simulation/top.vhd | 1 | 3,646 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top IS
END top;
ARCHITECTURE behavior OF top IS
component packet_simulation port(
clock : IN std_logic;
data_valid: out std_logic;
data_out : out std_logic_vector(7 downto 0);
start_packet: out std_logic;
end_packet : out std_logic
);end component;
component parser port (
clk_read : in STD_LOGIC;
reset : in STD_LOGIC;
start_packet : in STD_LOGIC;
end_packet : in STD_LOGIC;
data_valid : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
eventID: out std_logic_vector(31 downto 0);
triggerID: out std_logic_vector(31 downto 0);
deviceID: out std_logic_vector(15 downto 0);
dataWORD: out std_logic_vector(31 downto 0);
out_data: out std_logic
);end component;
component devicefilter port(
deviceID: in std_logic_vector(15 downto 0);
in_data: in std_logic;
clock: in std_logic;
channel_offset: out std_logic_vector(15 downto 0);
accepted: out std_logic
);end component;
component tdc_parser port(
in_data:in std_logic;
dataWORD: in std_logic_vector(31 downto 0);
channel_offset: in std_logic_vector(15 downto 0);
eventID: in std_logic_vector(31 downto 0);
triggerID: in std_logic_vector(31 downto 0);
out_data: out std_logic;
time_isrising:out std_logic;
time_channel: out std_logic_vector(15 downto 0);
time_epoch: out std_logic_vector(27 downto 0);
time_fine: out std_logic_vector(9 downto 0);
time_coasser:out std_logic_vector(10 downto 0)
);end component;
signal clock : std_logic:='0';
signal reset : std_logic:='0';
signal data_valid : std_logic:='0';
signal start_packet : std_logic;
signal end_packet : std_logic;
signal data_bus : std_logic_vector(7 downto 0);
signal beforefilter:std_logic:='0';
signal afterfilter:std_logic:='0';
signal data_word: std_logic_vector(31 downto 0);
signal deviceID: std_logic_vector(15 downto 0);
signal eventID: std_logic_vector(31 downto 0);
signal triggerID: std_logic_vector(31 downto 0);
signal channel_offset: std_logic_vector(15 downto 0);
signal tdc_data: std_logic;
signal time_channel: std_logic_vector(15 downto 0);
signal time_isrising: std_logic;
signal time_epoch: std_logic_vector(27 downto 0);
signal time_fine: std_logic_vector(9 downto 0);
signal time_coasser: std_logic_vector(10 downto 0);
constant clock_period : time := 10 ns;
BEGIN
uut: packet_simulation PORT MAP (
clock => clock,
data_valid => data_valid,
data_out => data_bus,
start_packet => start_packet,
end_packet => end_packet
);
parse:parser port map (
clk_read => clock,
reset => reset,
start_packet => start_packet,
end_packet => end_packet,
data_valid => data_valid,
data_in => data_bus,
eventID => eventID,
triggerID => triggerID,
deviceID => deviceID,
dataWORD => data_word,
out_data => beforefilter
);
filter:devicefilter port map (
deviceID => deviceID,
in_data => beforefilter,
clock => clock,
channel_offset => channel_offset,
accepted => afterfilter
);
tdc:tdc_parser port map(
in_data => afterfilter,
dataWORD => data_word,
channel_offset => channel_offset,
eventID => eventID,
triggerID => triggerID,
out_data => tdc_data,
time_isrising => time_isrising,
time_channel => time_channel,
time_epoch => time_epoch,
time_fine => time_fine,
time_coasser => time_coasser
);
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
begin
wait;
end process;
end;
| gpl-3.0 | f0121caecacc2a1907315b0c9d5a1a7e | 0.671421 | 3.118905 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/clock/top.vhdl | 1 | 1,659 | --
-- Clocks on ml605
--
-- There are four clock sources on ml605 board:
-- * On-board differential 200 MHz oscillator.
-- * On-board single-ended Oscillator Socket populated with 66 MHz.
-- * User differential through SMA.
-- * MGT differential through SMA.
-- This example is about on-board clock sources. They are used to blink user leds.
-- The clock of 200 MHz is used to blink the 8 GPIO LEDs.
-- The clock of 66 MHz is used to blink the 5 direction LEDs.
-- CPU Reset push-button (SW10) is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(12 downto 0)
);
end entity Top;
architecture RTL of Top is
signal clk200, led66, led200 : std_logic;
begin
IBUFGDS_inst: IBUFGDS
port map (I => clk_p_i, IB => clk_n_i, O => clk200);
blink66_inst: Blink
generic map (FREQUENCY => 66e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led66);
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => rst_i, blink_o => led200);
leds_o(4 downto 0) <= led66 & led66 & led66 & led66 & not(led66);
leds_o(12 downto 5) <= led200 & not(led200) & led200 & not(led200) &
led200 & not(led200) & led200 & not(led200);
end architecture RTL;
| bsd-3-clause | 5a18292914d3ed7e5b6d54608f3358d3 | 0.649186 | 3.178161 | false | false | false | false |
xcthulhu/periphondemand | src/platforms/apf51/simulation/apf51_test_pkg.vhd | 1 | 4,823 | --
-- Copyright (c) ARMadeus Systems 2010
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--*********************************************************************
--
-- File : apf51_test_pkg.vhd
-- Created on : 20/12/2010
-- Author : Fabien Marteau <[email protected]>
--
--*********************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
package apf51_test_pkg is
CONSTANT CS_MIN : time := 13.6 ns;
CONSTANT HALF_CLOCK_PERIOD : time := 6 ns;
CONSTANT WE3 : time := 2.25 ns;
CONSTANT WE4 : time := 2.25 ns;
-- write procedures
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_rw : Read/Write signal
-- imx_adv : address/data mux signal
-- imx_da : Data/Address signal
-- WWSC : Value of imx WWSC
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_rw : out std_logic ;
signal imx_adv : out std_logic ;
signal imx_da : inout std_logic_vector (15 downto 0);
WWSC : natural
);
-- read procedures
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_rw : Read/Write signal
-- imx_adv : address/data mux signal
-- imx_da : Data/Address signal
-- RWSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_read(
address : in std_logic_vector( 15 downto 0);
signal value : out std_logic_vector( 15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n: out std_logic ;
signal imx_rw : out std_logic ;
signal imx_adv : out std_logic ;
signal imx_da : inout std_logic_vector( 15 downto 0) ;
RWSC : natural
);
end package apf51_test_pkg;
package body apf51_test_pkg is
-- Write value from imx
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_rw : out std_logic ;
signal imx_adv : out std_logic ;
signal imx_da : inout std_logic_vector (15 downto 0);
WWSC : natural
) is
begin
-- Write value
wait until rising_edge(gls_clk);
imx_da <= address(15 downto 0);
imx_rw <= '0';
imx_adv <= '0';
imx_cs_n <= '1';
wait until rising_edge(gls_clk);
imx_adv <= '1';
imx_cs_n <= '0';
imx_da <= value;
if WWSC <= 1 then
wait until rising_edge(gls_clk);
else
for n in 1 to WWSC loop
wait until rising_edge(gls_clk); -- WWSC > 1
end loop;
end if;
wait for 1 ns;
imx_cs_n <= '1';
imx_adv <= '1';
imx_da <= (others => 'Z');
end procedure imx_write;
-- Read a value from imx
procedure imx_read(
address : in std_logic_vector( 15 downto 0);
signal value : out std_logic_vector( 15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n: out std_logic ;
signal imx_rw : out std_logic ;
signal imx_adv : out std_logic ;
signal imx_da : inout std_logic_vector( 15 downto 0 ) ;
RWSC : natural
) is
begin
-- Read value
wait until rising_edge(gls_clk);
imx_da <= address(15 downto 0);
imx_cs_n <= '1';
imx_rw <= '1';
imx_adv <= '0';
wait until rising_edge(gls_clk);
imx_da <= (others => 'Z');
imx_cs_n <= '0';
imx_adv <= '1';
if RWSC > 1 then
for n in 2 to RWSC loop
wait until rising_edge(gls_clk);
end loop;
end if;
value <= imx_da;
imx_cs_n <= '1';
imx_da <= (others => 'Z');
end procedure imx_read;
end package body apf51_test_pkg;
| lgpl-2.1 | a7d3ffc44b2972b7d1d5abec6cae8094 | 0.56272 | 3.55941 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/generate01.vhd | 1 | 626 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
port(x: in std_logic;
F: out std_logic);
end ent;
architecture beh of ent is
begin
mygen: for I in 5 downto 0 generate
mygen_nested: for J in I downto 0 generate
myproc: process(x) is
variable foo : integer := J;
variable bar : integer := I;
begin
if (x='1') then
F <= '1';
else
F <= '0';
end if;
end process myproc;
end generate mygen_nested;
end generate mygen;
end beh;
| gpl-3.0 | 560cea330bf538fe4cec4ca55c57463b | 0.485623 | 4.258503 | false | false | false | false |
xcthulhu/periphondemand | src/library/test/int_gen/hdl/int_gen.vhd | 1 | 3,013 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 25/07/2008
-- File : int_gen.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity int_gen is
---------------------------------------------------------------------------
generic
(
periode : integer := 1_000_000; -- period between two IT in microseconds
clockperiode : integer := 10 -- clock period in nanoseconds
);
port
(
-- candr
clk : in std_logic ;
reset : in std_logic ;
-- wb16
readdata : out std_logic_vector( 15 downto 0) ;
writedata : in std_logic_vector( 15 downto 0) ;
ack : out std_logic ;
strobe : in std_logic ;
cycle : in std_logic ;
write : in std_logic ;
-- interrupts
interrupts : out std_logic_vector( 15 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture int_gen_1 of int_gen is
---------------------------------------------------------------------------
constant N : integer := ((periode)/(clockperiode))*1000;
signal rd_ack : std_logic := '0';
signal wr_ack : std_logic := '0';
signal state : std_logic_vector( 15 downto 0);
signal count : integer range 0 to (N-1);
begin
-- read process
readp : process(clk,reset)
begin
if(reset='1') then
rd_ack <= '0';
readdata <= (others => '0');
elsif(rising_edge(clk)) then
rd_ack <= '0';
if(strobe = '1' and write = '0' and cycle = '1') then
rd_ack <= '1';
readdata <= state;
end if;
end if;
end process;
-- write process
writep : process(clk,reset)
variable enable : std_logic := '0';
begin
if (reset = '1') then
wr_ack <= '0';
count <= 0;
state <= (others => '0');
enable := '0';
elsif rising_edge(clk) then
if(strobe = '1' and write = '1' and cycle = '1') then
wr_ack <= '1';
state <= writedata;
count <= 0;
elsif enable = '1' or wr_ack = '1' then
enable := '1';
if count = (N-1) then
count <= 0;
state <= state(14 downto 0)&state(15);
interrupts <= state;
else
count <= count + 1;
state <= state;
interrupts <= (others => '0');
end if;
else
wr_ack <= '0';
end if;
end if;
end process writep;
ack <= wr_ack or rd_ack;
end architecture int_gen_1;
| lgpl-2.1 | 3a29731f630273fe84167a1bbb9eb7f8 | 0.410886 | 4.261669 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/receive_raw_data.vhd | 1 | 4,721 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: receive_raw_data - Behavioral
-- Project Name: FPGA_Webserver
--
-- Description: The idea here is to receive the data from the PHY, then
-- pass it out to an external dual-clocked FIFO.
--
-- This will minimise the size of the eth_rxck driven clocking domain
--
-- To allow for the rx and tx_clocks being asynchronous only the first
-- of the idle bytes will be written to the FIFO. Because the Ethernet
-- standard enforces 12 idle bytes following each 1512 bytes of data
-- the clock can be over 7200 parts per million (>900KHz) faster and we
-- still won't over-run the input FIFO running at the local 125MHz clock
--
-- Dependencies: None
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity receive_raw_data is
Port ( eth_rxck : in STD_LOGIC;
eth_rxctl : in STD_LOGIC;
eth_rxd : in STD_LOGIC_VECTOR (3 downto 0);
rx_data_enable : out STD_LOGIC := '1';
rx_data : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
rx_data_present : out STD_LOGIC := '0';
rx_data_error : out STD_LOGIC := '0');
end receive_raw_data;
architecture Behavioral of receive_raw_data is
signal raw_ctl : std_logic_vector(1 downto 0);
signal raw_data : std_logic_vector(7 downto 0) := (others => '0');
signal data_enable_last : std_logic := '0';
begin
ddr_rx_ctl : IDDR generic map (DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", INIT_Q1 => '0', INIT_Q2 => '0', SRTYPE => "SYNC")
port map (Q1 => raw_ctl(0), Q2 => raw_ctl(1), C => eth_rxck, CE => '1', D => eth_rxctl, R => '0', S => '0');
ddr_rxd0 : IDDR generic map (DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", INIT_Q1 => '0', INIT_Q2 => '0', SRTYPE => "SYNC")
port map (Q1 => raw_data(0), Q2 => raw_data(4), C => eth_rxck, CE => '1', D => eth_rxd(0), R => '0', S => '0');
ddr_rxd1 : IDDR generic map (DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", INIT_Q1 => '0', INIT_Q2 => '0', SRTYPE => "SYNC")
port map (Q1 => raw_data(1), Q2 => raw_data(5), C => eth_rxck, CE => '1', D => eth_rxd(1), R => '0', S => '0');
ddr_rxd2 : IDDR generic map (DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", INIT_Q1 => '0', INIT_Q2 => '0', SRTYPE => "SYNC")
port map (Q1 => raw_data(2), Q2 => raw_data(6), C => eth_rxck, CE => '1', D => eth_rxd(2), R => '0', S => '0');
ddr_rxd3 : IDDR generic map (DDR_CLK_EDGE => "SAME_EDGE_PIPELINED", INIT_Q1 => '0', INIT_Q2 => '0', SRTYPE => "SYNC")
port map (Q1 => raw_data(3), Q2 => raw_data(7), C => eth_rxck, CE => '1', D => eth_rxd(3), R => '0', S => '0');
process(eth_rxck)
begin
if rising_edge(eth_rxck) then
rx_data_enable <= data_enable_last or raw_ctl(0);
rx_data_present <= raw_ctl(0);
data_enable_last <= raw_ctl(0);
rx_data <= raw_data;
rx_data_error <= raw_ctl(0) XOR raw_ctl(1);
end if;
end process;
end Behavioral;
| mit | 8fc1de30027992f5265e51cdcd675634 | 0.571913 | 3.557649 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/reset_controller.vhd | 1 | 2,500 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Control the timing of reset signals
--
-- Dependencies:
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity reset_controller is
Port ( clk125mhz : in STD_LOGIC;
phy_ready : out STD_LOGIC;
eth_rst_b : out STD_LOGIC);
end reset_controller;
architecture Behavioral of reset_controller is
signal reset_counter : unsigned(24 downto 0) := (others => '0');
begin
control_reset: process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if reset_counter(reset_counter'high) = '0' then
reset_counter <= reset_counter + 1;
end if;
eth_rst_b <= reset_counter(reset_counter'high) or reset_counter(reset_counter'high-1);
phy_ready <= reset_counter(reset_counter'high);
end if;
end process;
end Behavioral;
| mit | 89c7b4b0bea9e10399fbb423fe37ce6b | 0.6088 | 4.562044 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/arp/arp_tx_fifo.vhd | 1 | 3,511 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: my_fifo - Behavioral
--
-- Description: A 32 entry FIFO using inferred storage
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arp_tx_fifo is
Port ( clk : in STD_LOGIC;
arp_in_write : in STD_LOGIC;
arp_in_full : out STD_LOGIC;
arp_in_op_request : in STD_LOGIC;
arp_in_tgt_hw : in STD_LOGIC_VECTOR(47 downto 0);
arp_in_tgt_ip : in STD_LOGIC_VECTOR(31 downto 0);
arp_out_empty : out std_logic := '0';
arp_out_read : in std_logic := '0';
arp_out_op_request : out std_logic := '0';
arp_out_tgt_hw : out std_logic_vector(47 downto 0) := (others => '0');
arp_out_tgt_ip : out std_logic_vector(31 downto 0) := (others => '0'));
end arp_tx_fifo;
architecture Behavioral of arp_tx_fifo is
component fifo_32 is
port (
clk : in std_logic;
full : out std_logic;
write_en : in std_logic;
data_in : in std_logic_vector;
empty : out std_logic;
read_en : in std_logic;
data_out : out std_logic_vector);
end component;
signal data_in : std_logic_vector(80 downto 0) := (others => '0');
signal data_out : std_logic_vector(80 downto 0) := (others => '0');
begin
arp_out_op_request <= data_out(80);
arp_out_tgt_hw <= data_out(79 downto 32);
arp_out_tgt_ip <= data_out(31 downto 0);
data_in <= arp_in_op_request & arp_in_tgt_hw & arp_in_tgt_ip;
i_generic_fifo: fifo_32
port map (
clk => clk,
full => arp_in_full,
write_en => arp_in_write,
data_in => data_in,
empty => arp_out_empty,
read_en => arp_out_read,
data_out => data_out);
end Behavioral; | mit | 53b1ff1edf57d7f8abb6ba5b6d9111d7 | 0.560239 | 3.892461 | false | false | false | false |
daniw/ecs | vhdl/sw02/ueb2_1/tb_EnableGate.vhd | 1 | 3,361 | -------------------------------------------------------------------------------
-- Company : HSLU, Waj
-- Create Date: 20-Apr-12
-- Project : ECS, Uebung 2
-- Description: Testbench for enable gate with configuration selection
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_EnableGate is
end tb_EnableGate;
architecture TB of tb_EnableGate is
component EnableGate
port(
x : in std_ulogic_vector(3 downto 0);
en : in std_ulogic;
y : out std_ulogic_vector(3 downto 0));
end component EnableGate;
-- configure architecture of UUT to be simulated
for UUT1 : EnableGate use entity work.EnableGate(A_conc_sig_ass_1);
for UUT2 : EnableGate use entity work.EnableGate(A_conc_sig_ass_2);
for UUT3 : EnableGate use entity work.EnableGate(A_cond_sig_ass_1);
for UUT4 : EnableGate use entity work.EnableGate(A_sel_sig_ass_1);
for UUT5 : EnableGate use entity work.EnableGate(A_proc_seq_sig_ass_1);
signal x : std_ulogic_vector(3 downto 0);
signal en : std_ulogic;
signal y1 : std_ulogic_vector(3 downto 0);
signal y2 : std_ulogic_vector(3 downto 0);
signal y3 : std_ulogic_vector(3 downto 0);
signal y4 : std_ulogic_vector(3 downto 0);
signal y5 : std_ulogic_vector(3 downto 0);
begin
-- Unit Under Test port map
UUT1 : EnableGate
port map (
x => x,
en => en,
y => y1
);
UUT2 : EnableGate
port map (
x => x,
en => en,
y => y2
);
UUT3 : EnableGate
port map (
x => x,
en => en,
y => y3
);
UUT4 : EnableGate
port map (
x => x,
en => en,
y => y4
);
UUT5 : EnableGate
port map (
x => x,
en => en,
y => y5
);
process
begin
for e in std_ulogic'('0') to '1' loop
en <= e;
for i in 0 to 3 loop
x <= (others => '0');
x(i) <= '1';
wait for 1us; -- wait before checking response and applying next stimuli vector
if e = '1' then
assert y1 = x report "ERROR: Simulation failed!!!" severity failure;
assert y2 = x report "ERROR: Simulation failed!!!" severity failure;
assert y3 = x report "ERROR: Simulation failed!!!" severity failure;
assert y4 = x report "ERROR: Simulation failed!!!" severity failure;
assert y5 = x report "ERROR: Simulation failed!!!" severity failure;
else
assert y1 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y2 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y3 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y4 = "0000" report "ERROR: Simulation failed!!!" severity failure;
assert y5 = "0000" report "ERROR: Simulation failed!!!" severity failure;
end if;
end loop;
end loop;
report "Simulation completed - Waiting for 8hr";
wait for 153min;
report "o.k. Simulation done" severity failure; -- failure: stop simulation
-- note: continue simulation
wait; -- suspend process forever
end process;
end TB;
| gpl-2.0 | 6358ab62e4e546ad3715c6d0d655cf48 | 0.549836 | 4.029976 | false | false | false | false |
daniw/ecs | vhdl/sw01/ueb1/vhd/MyNand.vhd | 1 | 824 | library ieee;
use ieee.std_logic_1164.all;
entity MyNand is
port ( a : in std_ulogic;
b : in std_ulogic;
x : out std_ulogic);
end MyNand;
architecture TWONAND of MyNand is -- Connection from and to inv
signal tmp : std_ulogic;
component myand
port ( a_and : in std_ulogic;
b_and : in std_ulogic;
x_and : out std_ulogic);
end component myand;
component myinv
port ( a_inv : in std_ulogic;
x_inv : out std_ulogic);
end component myinv;
begin
inst_and : myand
port map ( a_and => a,
b_and => b,
x_and => tmp);
inst_inv : myinv
port map ( a_inv => tmp,
x_inv => x);
end architecture TWONAND;
| gpl-2.0 | 8c950e34c91b57a36aa8c8abc4d38141 | 0.493932 | 3.506383 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/example_design/rtl/example_top.vhd | 1 | 44,785 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 6000;
-- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C1_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 2
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_cke : out std_logic;
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk : in std_logic;
c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc1_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb1_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb1_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb1_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb1_dram_cke : out std_logic;
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc1_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p0_DATA_MODE : std_logic_vector(3 downto 0);
C_p0_END_ADDRESS : std_logic_vector(31 downto 0);
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p1_DATA_MODE : std_logic_vector(3 downto 0);
C_p1_END_ADDRESS : std_logic_vector(31 downto 0);
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_CLKOUT0_DIVIDE : integer := 2;
constant C1_CLKOUT1_DIVIDE : integer := 2;
constant C1_CLKOUT2_DIVIDE : integer := 16;
constant C1_CLKOUT3_DIVIDE : integer := 8;
constant C1_CLKFBOUT_MULT : integer := 4;
constant C1_DIVCLK_DIVIDE : integer := 1;
constant C1_INCLK_PERIOD : integer := ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
constant C1_ARB_NUM_TIME_SLOTS : integer := 12;
constant C1_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"10";
constant C1_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"01";
constant C1_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"10";
constant C1_MEM_TRAS : integer := 42000;
constant C1_MEM_TRCD : integer := 18000;
constant C1_MEM_TREFI : integer := 7800000;
constant C1_MEM_TRFC : integer := 70000;
constant C1_MEM_TRP : integer := 18000;
constant C1_MEM_TWR : integer := 15000;
constant C1_MEM_TRTP : integer := 7500;
constant C1_MEM_TWTR : integer := 1;
constant C1_MEM_TYPE : string := "MDDR";
constant C1_MEM_DENSITY : string := "256Mb";
constant C1_MEM_BURST_LEN : integer := 4;
constant C1_MEM_CAS_LATENCY : integer := 3;
constant C1_MEM_NUM_COL_BITS : integer := 9;
constant C1_MEM_DDR1_2_ODS : string := "FULL";
constant C1_MEM_DDR2_RTT : string := "50OHMS";
constant C1_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C1_MEM_DDR2_3_PA_SR : string := "FULL";
constant C1_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C1_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C1_MEM_DDR3_ODS : string := "DIV6";
constant C1_MEM_DDR3_RTT : string := "DIV2";
constant C1_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C1_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C1_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C1_MEM_MOBILE_PA_SR : string := "FULL";
constant C1_MEM_MDDR_ODS : string := "HALF";
constant C1_MC_CALIB_BYPASS : string := "NO";
constant C1_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C1_MC_CALIBRATION_DELAY : string := "HALF";
constant C1_SKIP_IN_TERM_CAL : integer := 1;
constant C1_SKIP_DYNAMIC_CAL : integer := 0;
constant C1_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_DQ0_TAP_DELAY_VAL : integer := 0;
constant C1_DQ1_TAP_DELAY_VAL : integer := 0;
constant C1_DQ2_TAP_DELAY_VAL : integer := 0;
constant C1_DQ3_TAP_DELAY_VAL : integer := 0;
constant C1_DQ4_TAP_DELAY_VAL : integer := 0;
constant C1_DQ5_TAP_DELAY_VAL : integer := 0;
constant C1_DQ6_TAP_DELAY_VAL : integer := 0;
constant C1_DQ7_TAP_DELAY_VAL : integer := 0;
constant C1_DQ8_TAP_DELAY_VAL : integer := 0;
constant C1_DQ9_TAP_DELAY_VAL : integer := 0;
constant C1_DQ10_TAP_DELAY_VAL : integer := 0;
constant C1_DQ11_TAP_DELAY_VAL : integer := 0;
constant C1_DQ12_TAP_DELAY_VAL : integer := 0;
constant C1_DQ13_TAP_DELAY_VAL : integer := 0;
constant C1_DQ14_TAP_DELAY_VAL : integer := 0;
constant C1_DQ15_TAP_DELAY_VAL : integer := 0;
constant C1_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000300", x"03000000");
constant C1_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000004ff", x"04ffffff");
constant C1_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffff800", x"f8000000");
constant C1_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000300", x"03000000");
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_async_rst : std_logic;
signal c1_sysclk_2x : std_logic;
signal c1_sysclk_2x_180 : std_logic;
signal c1_pll_ce_0 : std_logic;
signal c1_pll_ce_90 : std_logic;
signal c1_pll_lock : std_logic;
signal c1_mcb_drp_clk : std_logic;
signal c1_cmp_error : std_logic;
signal c1_cmp_data_valid : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c1_cmp_data : std_logic_vector(31 downto 0);
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_p1_cmd_en : std_logic;
signal c1_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p1_cmd_empty : std_logic;
signal c1_p1_cmd_full : std_logic;
signal c1_p1_wr_en : std_logic;
signal c1_p1_wr_mask : std_logic_vector(C1_P1_MASK_SIZE - 1 downto 0);
signal c1_p1_wr_data : std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
signal c1_p1_wr_full : std_logic;
signal c1_p1_wr_empty : std_logic;
signal c1_p1_wr_count : std_logic_vector(6 downto 0);
signal c1_p1_wr_underrun : std_logic;
signal c1_p1_wr_error : std_logic;
signal c1_p1_rd_en : std_logic;
signal c1_p1_rd_data : std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
signal c1_p1_rd_full : std_logic;
signal c1_p1_rd_empty : std_logic;
signal c1_p1_rd_count : std_logic_vector(6 downto 0);
signal c1_p1_rd_overflow : std_logic;
signal c1_p1_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
begin
error <= c1_error;
calib_done <= c1_calib_done;
c1_sys_clk_p <= '0';
c1_sys_clk_n <= '0';
c1_selfrefresh_enter <= '0';
memc1_infrastructure_inst : memc1_infrastructure
generic map
(
C_RST_ACT_LOW => C1_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C1_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C1_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C1_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C1_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C1_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C1_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C1_INCLK_PERIOD
)
port map
(
sys_clk_p => c1_sys_clk_p,
sys_clk_n => c1_sys_clk_n,
sys_clk => c1_sys_clk,
sys_rst_i => c1_sys_rst_i,
clk0 => c1_clk0,
rst0 => c1_rst0,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk
);
-- wrapper instantiation
memc1_wrapper_inst : memc1_wrapper
generic map
(
C_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C1_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C1_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C1_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C1_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C1_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C1_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C1_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C1_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C1_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C1_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C1_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C1_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C1_ARB_TIME_SLOT_11,
C_MEM_TRAS => C1_MEM_TRAS,
C_MEM_TRCD => C1_MEM_TRCD,
C_MEM_TREFI => C1_MEM_TREFI,
C_MEM_TRFC => C1_MEM_TRFC,
C_MEM_TRP => C1_MEM_TRP,
C_MEM_TWR => C1_MEM_TWR,
C_MEM_TRTP => C1_MEM_TRTP,
C_MEM_TWTR => C1_MEM_TWTR,
C_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_TYPE => C1_MEM_TYPE,
C_MEM_DENSITY => C1_MEM_DENSITY,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C1_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C1_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C1_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C1_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C1_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C1_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C1_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C1_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C1_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C1_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C1_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C1_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C1_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C1_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C1_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C1_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C1_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C1_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C1_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C1_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C1_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C1_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C1_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C1_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C1_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C1_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C1_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C1_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C1_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C1_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C1_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C1_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C1_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C1_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C1_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C1_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C1_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C1_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C1_DQ15_TAP_DELAY_VAL
)
port map
(
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_rzq => mcb1_rzq,
mcb1_dram_udm => mcb1_dram_udm,
calib_done => c1_calib_done,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
p0_cmd_clk => c1_clk0,
p0_cmd_en => c1_p0_cmd_en,
p0_cmd_instr => c1_p0_cmd_instr,
p0_cmd_bl => c1_p0_cmd_bl,
p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
p0_cmd_empty => c1_p0_cmd_empty,
p0_cmd_full => c1_p0_cmd_full,
p0_wr_clk => c1_clk0,
p0_wr_en => c1_p0_wr_en,
p0_wr_mask => c1_p0_wr_mask,
p0_wr_data => c1_p0_wr_data,
p0_wr_full => c1_p0_wr_full,
p0_wr_empty => c1_p0_wr_empty,
p0_wr_count => c1_p0_wr_count,
p0_wr_underrun => c1_p0_wr_underrun,
p0_wr_error => c1_p0_wr_error,
p0_rd_clk => c1_clk0,
p0_rd_en => c1_p0_rd_en,
p0_rd_data => c1_p0_rd_data,
p0_rd_full => c1_p0_rd_full,
p0_rd_empty => c1_p0_rd_empty,
p0_rd_count => c1_p0_rd_count,
p0_rd_overflow => c1_p0_rd_overflow,
p0_rd_error => c1_p0_rd_error,
p1_cmd_clk => c1_clk0,
p1_cmd_en => c1_p1_cmd_en,
p1_cmd_instr => c1_p1_cmd_instr,
p1_cmd_bl => c1_p1_cmd_bl,
p1_cmd_byte_addr => c1_p1_cmd_byte_addr,
p1_cmd_empty => c1_p1_cmd_empty,
p1_cmd_full => c1_p1_cmd_full,
p1_wr_clk => c1_clk0,
p1_wr_en => c1_p1_wr_en,
p1_wr_mask => c1_p1_wr_mask,
p1_wr_data => c1_p1_wr_data,
p1_wr_full => c1_p1_wr_full,
p1_wr_empty => c1_p1_wr_empty,
p1_wr_count => c1_p1_wr_count,
p1_wr_underrun => c1_p1_wr_underrun,
p1_wr_error => c1_p1_wr_error,
p1_rd_clk => c1_clk0,
p1_rd_en => c1_p1_rd_en,
p1_rd_data => c1_p1_rd_data,
p1_rd_full => c1_p1_rd_full,
p1_rd_empty => c1_p1_rd_empty,
p1_rd_count => c1_p1_rd_count,
p1_rd_overflow => c1_p1_rd_overflow,
p1_rd_error => c1_p1_rd_error,
selfrefresh_enter => c1_selfrefresh_enter,
selfrefresh_mode => c1_selfrefresh_mode
);
memc1_tb_top_inst : memc1_tb_top
generic map
(
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C1_SMALL_DEVICE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C1_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C1_p1_DATA_MODE,
C_p1_END_ADDRESS => C1_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C1_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C1_p1_PRBS_SADDR_MASK_POS
)
port map
(
error => c1_error,
calib_done => c1_calib_done,
clk0 => c1_clk0,
rst0 => c1_rst0,
cmp_error => c1_cmp_error,
cmp_data_valid => c1_cmp_data_valid,
vio_modify_enable => c1_vio_modify_enable,
error_status => c1_error_status,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
cmp_data => c1_cmp_data,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count,
p1_mcb_cmd_en_o => c1_p1_cmd_en,
p1_mcb_cmd_instr_o => c1_p1_cmd_instr,
p1_mcb_cmd_bl_o => c1_p1_cmd_bl,
p1_mcb_cmd_addr_o => c1_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c1_p1_cmd_full,
p1_mcb_wr_en_o => c1_p1_wr_en,
p1_mcb_wr_mask_o => c1_p1_wr_mask,
p1_mcb_wr_data_o => c1_p1_wr_data,
p1_mcb_wr_full_i => c1_p1_wr_full,
p1_mcb_wr_fifo_counts => c1_p1_wr_count,
p1_mcb_rd_en_o => c1_p1_rd_en,
p1_mcb_rd_data_i => c1_p1_rd_data,
p1_mcb_rd_empty_i => c1_p1_rd_empty,
p1_mcb_rd_fifo_counts => c1_p1_rd_count
);
end arc;
| cc0-1.0 | 78be3fc0a878863ae7cfa74b8efacf58 | 0.454259 | 3.392032 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp/tcp_handler.vhd | 1 | 11,557 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_handler - Behavioral
--
-- Description: Provide the processing for TCP packets.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
-- For receiving data from the PHY
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : out std_logic := '0';
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- For sending data to the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end tcp_handler;
architecture Behavioral of tcp_handler is
component tcp_rx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_broadcast : out std_logic := '0';
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0')
);
end component;
component tcp_tx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port(
clk : in STD_LOGIC;
tcp_tx_busy : out std_logic;
tcp_tx_data_valid : in std_logic;
tcp_tx_data : in std_logic_vector(7 downto 0);
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_dst_mac : in std_logic_vector(47 downto 0);
tcp_tx_dst_ip : in std_logic_vector(31 downto 0);
tcp_tx_src_port : in std_logic_vector(15 downto 0);
tcp_tx_dst_port : in std_logic_vector(15 downto 0);
tcp_tx_seq_num : in std_logic_vector(31 downto 0);
tcp_tx_ack_num : in std_logic_vector(31 downto 0);
tcp_tx_window : in std_logic_vector(15 downto 0);
tcp_tx_flag_urg : in std_logic;
tcp_tx_flag_ack : in std_logic;
tcp_tx_flag_psh : in std_logic;
tcp_tx_flag_rst : in std_logic;
tcp_tx_flag_syn : in std_logic;
tcp_tx_flag_fin : in std_logic;
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal i_packet_out_valid : std_logic := '0';
begin
--==============================================
-- Start of UDP RX processing
--==============================================
i_tcp_rx_packet: tcp_rx_packet generic map (
our_ip => our_ip,
our_mac => our_mac
) port map (
clk => clk,
packet_in_valid => packet_in_valid,
packet_in_data => packet_in_data,
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_broadcast => tcp_rx_dst_broadcast,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_checksum => tcp_rx_checksum,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr);
--==============================================
-- End of TCP RX processing
--==============================================
-- Start of TCP TX processing
--==============================================
i_tcp_tx_packet : tcp_tx_packet generic map (
our_ip => our_ip,
our_mac => our_mac
) port map (
clk => clk,
tcp_tx_busy => tcp_tx_busy,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_dst_mac => tcp_tx_dst_mac,
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
packet_out_request => packet_out_request,
packet_out_granted => packet_out_granted,
packet_out_valid => packet_out_valid,
packet_out_data => packet_out_data);
--==============================================
-- End of TCP TX processing
--==============================================
end Behavioral; | mit | 5695357f40191867704db5a840aca6ec | 0.49139 | 3.534251 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/ip/ip_add_header.vhd | 1 | 9,483 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: ip_add_header - Behavioral
--
-- Description: Add the IP header fields to a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ip_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_data_length : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end ip_add_header;
architecture Behavioral of ip_add_header is
type a_data_delay is array(0 to 20) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
-------------------------------------------------------
-- Note: Set the initial state to pass the data through
-------------------------------------------------------
signal count : unsigned(4 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
constant ip_version : STD_LOGIC_VECTOR ( 3 downto 0) := x"4";
constant ip_header_len : STD_LOGIC_VECTOR ( 3 downto 0) := x"5";
constant ip_type_of_service : STD_LOGIC_VECTOR ( 7 downto 0) := x"00"; --zzz
constant ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); --zzz
constant ip_flags : STD_LOGIC_VECTOR ( 2 downto 0) := (others => '0'); --zzz
constant ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0'); --zzz
constant ip_ttl : STD_LOGIC_VECTOR ( 7 downto 0) := x"FF";
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_checksum_1a : unsigned(19 downto 0) := (others => '0');
signal ip_checksum_1b : unsigned(19 downto 0) := (others => '0');
signal ip_checksum_2 : unsigned(19 downto 0) := (others => '0');
signal ip_checksum_3 : unsigned(16 downto 0) := (others => '0');
signal ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_0 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_1 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_2 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_3 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_4 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_5 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_6 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_7 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_8 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_word_9 : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
begin
ip_length <= std_logic_vector(unsigned(ip_data_length)+20);
ip_word_0 <= ip_version & ip_header_len & ip_type_of_service;
ip_word_1 <= ip_length;
ip_word_2 <= ip_identification;
ip_word_3 <= ip_flags & ip_fragment_offset;
ip_word_4 <= ip_ttl & ip_protocol;
ip_word_5 <= ip_checksum;
ip_word_6 <= ip_src_ip( 7 downto 0) & ip_src_ip(15 downto 8);
ip_word_7 <= ip_src_ip(23 downto 16) & ip_src_ip(31 downto 24);
ip_word_8 <= ip_dst_ip( 7 downto 0) & ip_dst_ip(15 downto 8);
ip_word_9 <= ip_dst_ip(23 downto 16) & ip_dst_ip(31 downto 24);
process(clk)
begin
if rising_edge(clk) then
case count is
when "00000" => data_out <= ip_word_0(15 downto 8); data_valid_out <= '1';
when "00001" => data_out <= ip_word_0( 7 downto 0); data_valid_out <= '1';
when "00010" => data_out <= ip_word_1(15 downto 8); data_valid_out <= '1';
when "00011" => data_out <= ip_word_1( 7 downto 0); data_valid_out <= '1';
when "00100" => data_out <= ip_word_2(15 downto 8); data_valid_out <= '1';
when "00101" => data_out <= ip_word_2( 7 downto 0); data_valid_out <= '1';
when "00110" => data_out <= ip_word_3(15 downto 8); data_valid_out <= '1';
when "00111" => data_out <= ip_word_3( 7 downto 0); data_valid_out <= '1';
when "01000" => data_out <= ip_word_4(15 downto 8); data_valid_out <= '1';
when "01001" => data_out <= ip_word_4( 7 downto 0); data_valid_out <= '1';
when "01010" => data_out <= ip_word_5(15 downto 8); data_valid_out <= '1';
when "01011" => data_out <= ip_word_5( 7 downto 0); data_valid_out <= '1';
when "01100" => data_out <= ip_word_6(15 downto 8); data_valid_out <= '1';
when "01101" => data_out <= ip_word_6( 7 downto 0); data_valid_out <= '1';
when "01110" => data_out <= ip_word_7(15 downto 8); data_valid_out <= '1';
when "01111" => data_out <= ip_word_7( 7 downto 0); data_valid_out <= '1';
when "10000" => data_out <= ip_word_8(15 downto 8); data_valid_out <= '1';
when "10001" => data_out <= ip_word_8( 7 downto 0); data_valid_out <= '1';
when "10010" => data_out <= ip_word_9(15 downto 8); data_valid_out <= '1';
when "10011" => data_out <= ip_word_9( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "11111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "11111" then
count <= count + 1;
end if;
end if;
--------------------------------------------------------------------------------
-- Checksum is calculated in a pipeline, it will be ready by the time we need it
--------------------------------------------------------------------------------
ip_checksum_1a <= to_unsigned(0,20)
+ unsigned(ip_word_0)
+ unsigned(ip_word_1)
+ unsigned(ip_word_2)
+ unsigned(ip_word_3)
+ unsigned(ip_word_4);
ip_checksum_1b <= to_unsigned(0,20)
+ unsigned(ip_word_6)
+ unsigned(ip_word_7)
+ unsigned(ip_word_8)
+ unsigned(ip_word_9);
ip_checksum_2 <= ip_checksum_1a + ip_checksum_1b;
ip_checksum_3 <= to_unsigned(0,17) + ip_checksum_2(15 downto 0) + ip_checksum_2(19 downto 16);
ip_checksum <= not std_logic_vector(ip_checksum_3(15 downto 0) + ip_checksum_3(16 downto 16));
data_valid_in_last <= data_valid_in;
end if;
end process;
end Behavioral;
| mit | 7c53a20504fb991636028a2fee713d78 | 0.499947 | 3.678433 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/mcu.vhd | 1 | 4,378 | -------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description:
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers for
-- bi-directional GPIO pins are described here.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity mcu is
port(rst : in std_logic;
clk : in std_logic;
-- General-Purpose I/O ports
GPIO_0 : inout std_logic_vector(DW-1 downto 0);
GPIO_1 : inout std_logic_vector(DW-1 downto 0);
GPIO_2 : inout std_logic_vector(DW-1 downto 0);
GPIO_3 : inout std_logic_vector(DW-1 downto 0);
-- Dedicated LCD port
LCD : out std_logic_vector(LCD_PW-1 downto 0)
);
end mcu;
architecture rtl of mcu is
-- CPU signals
signal cpu2bus : t_cpu2bus;
signal bus2cpu : t_bus2cpu;
-- ROM signals
signal bus2rom : t_bus2ros;
signal rom2bus : t_ros2bus;
-- ROM signals
signal bus2ram : t_bus2rws;
signal ram2bus : t_rws2bus;
-- GPIO signals
signal bus2gpio : t_bus2rws;
signal gpio2bus : t_rws2bus;
signal gpio_in : t_gpio_pin_in;
signal gpio_out : t_gpio_pin_out;
-- LCD signals
signal bus2lcd : t_bus2rws;
signal lcd2bus : t_rws2bus;
signal lcd_out : std_logic_vector(LCD_PW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Tri-state buffers for GPIO pins
-----------------------------------------------------------------------------
gpio_in.in_0 <= GPIO_0;
gpio_in.in_1 <= GPIO_1;
gpio_in.in_2 <= GPIO_2;
gpio_in.in_3 <= GPIO_3;
gen_gpin: for k in 0 to DW-1 generate
GPIO_0(k) <= gpio_out.out_0(k) when gpio_out.enb_0(k) = '1' else 'Z';
GPIO_1(k) <= gpio_out.out_1(k) when gpio_out.enb_1(k) = '1' else 'Z';
GPIO_2(k) <= gpio_out.out_2(k) when gpio_out.enb_2(k) = '1' else 'Z';
GPIO_3(k) <= gpio_out.out_3(k) when gpio_out.enb_3(k) = '1' else 'Z';
end generate;
-----------------------------------------------------------------------------
-- LCD interface pins
-----------------------------------------------------------------------------
LCD <= lcd_out;
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- CPU ----------------------------------------------------------------------
i_cpu: entity work.cpu
port map(
rst => rst,
clk => clk,
bus_in => bus2cpu,
bus_out => cpu2bus
);
-- BUS ----------------------------------------------------------------------
i_bus: entity work.buss
port map(
rst => rst,
clk => clk,
cpu_in => cpu2bus,
cpu_out => bus2cpu,
rom_in => rom2bus,
rom_out => bus2rom,
ram_in => ram2bus,
ram_out => bus2ram,
gpio_in => gpio2bus,
gpio_out => bus2gpio,
lcd_in => lcd2bus,
lcd_out => bus2lcd
);
-- ROM ----------------------------------------------------------------------
i_rom: entity work.rom
port map(
clk => clk,
bus_in => bus2rom,
bus_out => rom2bus
);
-- RAM ----------------------------------------------------------------------
i_ram: entity work.ram
port map(
clk => clk,
bus_in => bus2ram,
bus_out => ram2bus
);
-- GPIO ---------------------------------------------------------------------
i_gpio: entity work.gpio
port map(
rst => rst,
clk => clk,
bus_in => bus2gpio,
bus_out => gpio2bus,
pin_in => gpio_in,
pin_out => gpio_out
);
-- LCD ----------------------------------------------------------------------
i_lcd: entity work.lcd
port map(
rst => rst,
clk => clk,
bus_in => bus2lcd,
bus_out => lcd2bus,
lcd_out => lcd_out
);
end rtl;
| gpl-2.0 | 173598704b8ed0594ff282ecf55b188a | 0.404979 | 3.905442 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/example_design/sim/functional/sim_tb_top.vhd | 1 | 14,911 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:22 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C1_HW_TESTING : string := "FALSE";
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_MEMCLK_PERIOD : integer := 6000;
constant C1_RST_ACT_LOW : integer := 0;
constant C1_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C1_CLK_PERIOD_NS : real := 6000.0 / 1000.0;
constant C1_TCYC_SYS : real := C1_CLK_PERIOD_NS/2.0;
constant C1_TCYC_SYS_DIV2 : time := C1_TCYC_SYS * 1 ns;
constant C1_NUM_DQ_PINS : integer := 16;
constant C1_MEM_ADDR_WIDTH : integer := 13;
constant C1_MEM_BANKADDR_WIDTH : integer := 2;
constant C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C1_P0_MASK_SIZE : integer := 4;
constant C1_P0_DATA_PORT_SIZE : integer := 32;
constant C1_P1_MASK_SIZE : integer := 4;
constant C1_P1_DATA_PORT_SIZE : integer := 32;
constant C1_CALIB_SOFT_IP : string := "TRUE";
constant C1_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C1_P0_MASK_SIZE : integer;
C1_P0_DATA_PORT_SIZE : integer;
C1_P1_MASK_SIZE : integer;
C1_P1_DATA_PORT_SIZE : integer;
C1_MEMCLK_PERIOD : integer;
C1_RST_ACT_LOW : integer;
C1_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C1_CALIB_SOFT_IP : string;
C1_SIMULATION : string;
C1_HW_TESTING : string;
C1_MEM_ADDR_ORDER : string;
C1_NUM_DQ_PINS : integer;
C1_MEM_ADDR_WIDTH : integer;
C1_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
c1_sys_clk : in std_logic;
c1_sys_rst_i : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_ck_n : out std_logic
);
end component;
component lpddr_model_c1 is
port (
Clk : in std_logic;
Clk_n : in std_logic;
Cke : in std_logic;
Cs_n : in std_logic;
Ras_n : in std_logic;
Cas_n : in std_logic;
We_n : in std_logic;
Dm : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
Ba : in std_logic_vector((C1_MEM_BANKADDR_WIDTH - 1) downto 0);
Addr : in std_logic_vector((C1_MEM_ADDR_WIDTH - 1) downto 0);
Dq : inout std_logic_vector((C1_NUM_DQ_PINS - 1) downto 0);
Dqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c1_sys_clk : std_logic := '0';
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
-- System Reset
signal c1_sys_rst : std_logic := '0';
signal c1_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb1_dram_a : std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
signal mcb1_dram_ba : std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb1_dram_ck : std_logic;
signal mcb1_dram_ck_n : std_logic;
signal mcb1_dram_dq : std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
signal mcb1_dram_dqs : std_logic;
signal mcb1_dram_dm : std_logic;
signal mcb1_dram_ras_n : std_logic;
signal mcb1_dram_cas_n : std_logic;
signal mcb1_dram_we_n : std_logic;
signal mcb1_dram_cke : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb1_dram_udqs : std_logic;
signal mcb1_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_udm :std_logic; -- for X16 parts
signal mcb1_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb1_command : std_logic_vector(2 downto 0);
signal mcb1_enable1 : std_logic;
signal mcb1_enable2 : std_logic;
signal rzq1 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c1_sys_clk <= not c1_sys_clk;
wait for (C1_TCYC_SYS_DIV2);
end process;
c1_sys_clk_p <= c1_sys_clk;
c1_sys_clk_n <= not c1_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c1_sys_rst <= '0';
wait for 200 ns;
c1_sys_rst <= '1';
wait;
end process;
c1_sys_rst_i <= c1_sys_rst when (C1_RST_ACT_LOW = 1) else (not c1_sys_rst);
rzq_pulldown1 : PULLDOWN port map(O => rzq1);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C1_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C1_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C1_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C1_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C1_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C1_RST_ACT_LOW => C1_RST_ACT_LOW,
C1_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C1_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C1_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C1_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C1_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C1_HW_TESTING => C1_HW_TESTING,
C1_SIMULATION => C1_SIMULATION,
C1_CALIB_SOFT_IP => C1_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c1_sys_clk => c1_sys_clk,
c1_sys_rst_i => c1_sys_rst_i,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb1_dram_udqs => mcb1_dram_udqs, -- for X16 parts
mcb1_dram_udm => mcb1_dram_udm, -- for X16 parts
mcb1_dram_dm => mcb1_dram_dm,
mcb1_rzq => rzq1,
mcb1_dram_dqs => mcb1_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb1_command <= (mcb1_dram_ras_n & mcb1_dram_cas_n & mcb1_dram_we_n);
process(mcb1_dram_ck)
begin
if (rising_edge(mcb1_dram_ck)) then
if (c1_sys_rst = '0') then
mcb1_enable1 <= '0';
mcb1_enable2 <= '0';
elsif (mcb1_command = "100") then
mcb1_enable2 <= '0';
elsif (mcb1_command = "101") then
mcb1_enable2 <= '1';
else
mcb1_enable2 <= mcb1_enable2;
end if;
mcb1_enable1 <= mcb1_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb1_dram_dqs_vector(1 downto 0) <= (mcb1_dram_udqs & mcb1_dram_dqs)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb1_dram_dqs <= mcb1_dram_dqs_vector(0)
when ( mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs <= mcb1_dram_dqs_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_dm_vector <= (mcb1_dram_udm & mcb1_dram_dm);
u_mem_c1 : lpddr_model_c1 port map(
Clk => mcb1_dram_ck,
Clk_n => mcb1_dram_ck_n,
Cke => mcb1_dram_cke,
Cs_n => '0',
Ras_n => mcb1_dram_ras_n,
Cas_n => mcb1_dram_cas_n,
We_n => mcb1_dram_we_n,
Dm => mcb1_dram_dm_vector ,
Ba => mcb1_dram_ba,
Addr => mcb1_dram_a,
Dq => mcb1_dram_dq,
Dqs => mcb1_dram_dqs_vector
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| cc0-1.0 | 50c5a01a9c44d7be547a71c10eabd11c | 0.470928 | 3.795113 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/led/hdl/led.vhd | 1 | 2,417 | ---------------------------------------------------------------------------
-- Company : ARMadeus Systems
-- Author(s) : Fabien Marteau
--
-- Creation Date : 05/03/2008
-- File : led.vhd
--
-- Abstract : drive one led with Wishbone bus
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-----------------------------------------------------------------------
Entity led is
-----------------------------------------------------------------------
generic(
id : natural := 1;
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_add : in std_logic ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
led : out std_logic
);
end entity led;
-----------------------------------------------------------------------
Architecture led_1 of led is
-----------------------------------------------------------------------
signal reg : std_logic_vector( wb_size-1 downto 0);
begin
-- connect led
led <= reg(0);
wbs_ack <= wbs_strobe;
-- manage register
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg <= (others => '0');
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg <= wbs_writedata;
else
reg <= reg;
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
wbs_readdata <= (others => '0');
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
if wbs_add = '0' then
wbs_readdata <= reg;
else
wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
end if;
else
wbs_readdata <= (others => '0');
end if;
end if;
end process read_bloc;
end architecture led_1;
| lgpl-2.1 | 37ac16d21d40e946cf8034e9f1e2638d | 0.441456 | 4.138699 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart16550_wb16.vhd | 1 | 3,824 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 25/06/2008
-- File : uart_top_vhdl.vhd
--
-- Abstract : wrapper for uart16550 from opencores to VHDL-Wishbone16 bus
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity uart16550 is
---------------------------------------------------------------------------
generic(
id : natural := 1;
wb_size : natural := 16
);
port (
-- clock
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector( 3 downto 0);
wb_dat_i : in std_logic_vector( 15 downto 0);
wb_dat_o : out std_logic_vector( 15 downto 0);
wb_we_i : in std_logic ;
wb_stb_i : in std_logic ;
wb_cyc_i : in std_logic ;
wb_ack_o : out std_logic ;
-- interrupt
int_o : out std_logic ;
-- uart signals
srx_pad_i : in std_logic ;
stx_pad_o : out std_logic ;
rts_pad_o : out std_logic ;
cts_pad_i : in std_logic ;
dtr_pad_o : out std_logic ;
dsr_pad_i : in std_logic ;
ri_pad_i : in std_logic ;
dcd_pad_i : in std_logic
-- optional baudrate output
-- baud_o : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture uart_top_vhdl_1 of uart16550 is
---------------------------------------------------------------------------
component uart_top
port (
-- clock
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector( 2 downto 0);
wb_dat_i : in std_logic_vector( 7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic ;
wb_stb_i : in std_logic ;
wb_cyc_i : in std_logic ;
wb_sel_i : in std_logic_vector( 3 downto 0);
wb_ack_o : out std_logic ;
int_o : out std_logic ;
-- uart signals
srx_pad_i : in std_logic ;
stx_pad_o : out std_logic ;
rts_pad_o : out std_logic ;
cts_pad_i : in std_logic ;
dtr_pad_o : out std_logic ;
dsr_pad_i : in std_logic ;
ri_pad_i : in std_logic ;
dcd_pad_i : in std_logic
-- optional baudrate output
-- baud_o : out std_logic
);
end component;
signal wb_dat_i_int : std_logic_vector( 7 downto 0);
signal wb_dat_o_int : std_logic_vector( 7 downto 0);
signal strobe : std_logic ;
begin
wb_dat_i_int <= wb_dat_i(7 downto 0);
strobe <= wb_stb_i when wb_adr_i(3) = '0' else '0';
wb_dat_o <= std_logic_vector(to_unsigned(id,wb_size))
when wb_adr_i = "1000" and wb_stb_i = '1' and wb_we_i = '0'
else "00000000"&wb_dat_o_int
when wb_adr_i(3)= '0' and wb_stb_i = '1' and wb_we_i = '0'
else (others => '0');
uart_connect : uart_top
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
-- Wishbone
wb_adr_i => wb_adr_i(2 downto 0),
wb_dat_i => wb_dat_i_int,
wb_dat_o => wb_dat_o_int,
wb_we_i => wb_we_i,
wb_stb_i => strobe,
wb_cyc_i => wb_cyc_i,
wb_sel_i => "0001", -- byte always on LSB
wb_ack_o => wb_ack_o,
int_o => int_o,
-- uart s
srx_pad_i => srx_pad_i,
stx_pad_o => stx_pad_o,
rts_pad_o => rts_pad_o,
cts_pad_i => cts_pad_i,
dtr_pad_o => dtr_pad_o,
dsr_pad_i => dsr_pad_i,
ri_pad_i => ri_pad_i,
dcd_pad_i => dcd_pad_i
-- option
-- baud_o => baud_o
);
end architecture uart_top_vhdl_1;
| lgpl-2.1 | 503c29e4013503036cf4207c6ee728f4 | 0.480649 | 3.08636 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp_engine/tcp_engine_session_filter.vhd | 1 | 5,447 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.06.2016 16:36:27
-- Design Name:
-- Module Name: tcp_engine_session_filter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_session_filter is
port ( clk : in STD_LOGIC;
listen_port : in std_logic_vector(15 downto 0) := (others => '0');
drop_connection : in STD_LOGIC;
connected : out STD_LOGIC;
-- data received over TCP/IP
in_data_valid : in std_logic := '0';
in_data : in std_logic_vector(7 downto 0) := (others => '0');
in_hdr_valid : in std_logic := '0';
in_src_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
out_data_valid : out std_logic := '0';
out_data : out std_logic_vector(7 downto 0) := (others => '0');
out_hdr_valid : out std_logic := '0';
out_from_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_from_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end tcp_engine_session_filter;
architecture Behavioral of tcp_engine_session_filter is
signal i_connected : std_logic := '0';
signal do_drop : std_logic := '0';
signal session_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal session_src_ip : std_logic_vector(31 downto 0) := (others => '0');
begin
connected <= i_connected;
out_from_ip <= session_src_ip;
out_from_port <= session_src_port;
clk_proc: process(clk)
begin
if rising_edge(clk) then
if i_connected = '1' then
if do_drop = '1' and in_data_valid = '0' and in_hdr_valid = '0' then
-- Drop the connection
i_connected <= '0';
out_data_valid <= '0';
out_hdr_valid <= '0';
do_drop <= '0';
else
if in_dst_port = listen_port and in_src_ip = session_src_ip and in_src_port = session_src_port then
out_data_valid <= in_data_valid;
out_hdr_valid <= in_hdr_valid;
else
out_data_valid <= '0';
out_hdr_valid <= '0';
end if;
end if;
else
if in_hdr_valid = '1' then
if in_dst_port = listen_port and in_flag_syn = '1' then
i_connected <= '1';
session_src_port <= in_src_port;
session_src_ip <= in_src_ip;
out_data_valid <= in_data_valid;
out_hdr_valid <= in_hdr_valid;
end if;
end if;
end if;
-- Copy non-key data over anyway (just don't assert the valid siganls!
out_data <= in_data;
out_seq_num <= in_seq_num;
out_ack_num <= in_ack_num;
out_window <= in_window;
out_flag_urg <= in_flag_urg;
out_flag_ack <= in_flag_ack;
out_flag_psh <= in_flag_psh;
out_flag_rst <= in_flag_rst;
out_flag_syn <= in_flag_syn;
out_flag_fin <= in_flag_fin;
out_urgent_ptr <= in_urgent_ptr;
-- Remember if we are asked to drop the connection
if do_drop = '0' then
do_drop <= drop_connection;
end if;
end if;
end process;
end Behavioral;
| mit | cf5d0bf905c1881ec446ee1586d4e1cb | 0.459152 | 3.562459 | false | false | false | false |
wifidar/wifidar_fpga | src/sample_buffer.vhd | 2 | 2,448 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity sample_buffer is
generic(
num_samples: integer range 0 to 20000 := 400;
sample_length_bits: integer range 0 to 32 := 14
);
port(
sample_in: in std_logic_vector(sample_length_bits - 1 downto 0);
sample_out: out std_logic_vector(sample_length_bits - 1 downto 0);
sample_in_ready: in std_logic;
initial_sample: in std_logic;
sample_out_index: in std_logic_vector(integer(ceil(log(real(num_samples))/log(real(2)))) downto 0);
buffer_full: out std_logic;
rst: in std_logic;
clk: in std_logic
);
end sample_buffer;
architecture behavioral of sample_buffer is
type sample_buffer_mem_type is array (0 to (num_samples - 1)) of std_logic_vector(sample_length_bits - 1 downto 0);
signal sample_buffer_mem: sample_buffer_mem_type;
type sample_buffer_state is (reset,filling,emptying);
signal curr_state: sample_buffer_state;
signal curr_input_address: integer range 0 to num_samples := 0;
signal buffer_full_sig: std_logic := '0';
signal initialized: std_logic := '0';
signal initial_sample_prev: std_logic;
begin
process(clk,rst)
begin
if(rst = '1') then
curr_state <= reset;
elsif(rising_edge(clk)) then
initial_sample_prev <= initial_sample;
buffer_full_sig <= '0';
case curr_state is
when reset =>
curr_state <= filling;
buffer_full_sig <= '0';
curr_input_address <= 0;
when filling =>
if(initial_sample_prev = '1' and initial_sample = '0') then
initialized <= '1';
curr_input_address <= 0;
end if;
if(sample_in_ready = '1' and initialized = '1') then
curr_input_address <= curr_input_address + 1;
if(curr_input_address = num_samples) then
curr_input_address <= 0;
curr_state <= emptying;
buffer_full_sig <= '1';
else
sample_buffer_mem(curr_input_address) <= std_logic_vector(signed(sample_in) + (2**13));
end if;
end if;
when emptying =>
initialized <= '0';
buffer_full_sig <= '1';
if(sample_out_index = std_logic_vector(to_unsigned(num_samples,sample_out_index'length))) then
curr_state <= filling;
buffer_full_sig <= '0';
sample_out <= (others => '0');
else
sample_out <= sample_buffer_mem(to_integer(unsigned(sample_out_index)));
end if;
end case;
end if;
end process;
buffer_full <= buffer_full_sig;
end behavioral;
| mit | ef967e6e06f9deeb1b41ed2a1ba8822d | 0.650735 | 3.003681 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/mcu_pkg.vhd | 1 | 6,194 | -------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-- Date : 12-Mar-14
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu_pkg is
-----------------------------------------------------------------------------
-- design parameters
-----------------------------------------------------------------------------
-- system clock frequency in Hz
constant CF : natural := 50_000_000; -- 50 MHz
-- bus architecture parameters
constant DW : natural range 4 to 64 := 16; -- data word width
constant AW : natural range 2 to 64 := 8; -- total address width
constant AWH : natural range 1 to 64 := 2; -- high address width
constant AWL : natural range 1 to 64 := AW-AWH; -- low address width
-- memory map
type t_bus_slave is (ROM, RAM, GPIO, LCD); -- list of bus slaves
type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0);
constant BA : t_ba := ( -- full base addresses
ROM => X"00",
RAM => X"40",
GPIO => X"80",
LCD => X"C0"
);
type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0);
constant HBA : t_hba := ( -- high base address for decoding
ROM => BA(ROM)(AW-1 downto AW-AWH),
RAM => BA(RAM)(AW-1 downto AW-AWH),
GPIO => BA(GPIO)(AW-1 downto AW-AWH),
LCD => BA(LCD)(AW-1 downto AW-AWH)
);
-- LCD peripheral
constant LCD_PW : natural := 7; -- # of LCD control + data signal
-----------------------------------------------------------------------------
-- global types
-----------------------------------------------------------------------------
-- Master bus interface -----------------------------------------------------
type t_bus2cpu is record
data : std_logic_vector(DW-1 downto 0);
end record;
type t_cpu2bus is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
r_w : std_logic; -- read = '0', write = '1'
end record;
-- Read-only slave bus interface -------------------------------------------
type t_bus2ros is record
addr : std_logic_vector(AWL-1 downto 0);
end record;
type t_ros2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- read/write slave bus interface -------------------------------------------
type t_bus2rws is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AWL-1 downto 0);
we : std_logic; -- read = '0', write = '1'
end record;
type t_rws2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- GPIO ---------------------------------------------------------------------
type t_gpio_pin_in is record
in_0 : std_logic_vector(DW-1 downto 0);
in_1 : std_logic_vector(DW-1 downto 0);
in_2 : std_logic_vector(DW-1 downto 0);
in_3 : std_logic_vector(DW-1 downto 0);
end record;
type t_gpio_pin_out is record
out_0 : std_logic_vector(DW-1 downto 0);
out_1 : std_logic_vector(DW-1 downto 0);
out_2 : std_logic_vector(DW-1 downto 0);
out_3 : std_logic_vector(DW-1 downto 0);
enb_0 : std_logic_vector(DW-1 downto 0);
enb_1 : std_logic_vector(DW-1 downto 0);
enb_2 : std_logic_vector(DW-1 downto 0);
enb_3 : std_logic_vector(DW-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- CPU internal types and
-----------------------------------------------------------------------------
type t_alu2reg is record
result : std_logic_vector(DW-1 downto 0);
end record;
type t_reg2alu is record
op1 : std_logic_vector(DW-1 downto 0);
op2 : std_logic_vector(DW-1 downto 0);
end record;
type t_flag is record
Z : std_logic;
N : std_logic;
C : std_logic;
O : std_logic;
end record;
type t_ctrl2alu is record
op : t_opcode;
enb : std_logic;
end record;
type t_alu2ctrl is record
flag : t_flag;
end record;
type t_ctrl2reg is record
data : std_logic_vector(DW-1 downto 0);
src1 : std_logic_vector(2 downto 0);
src2 : std_logic_vector(2 downto 0);
dest : std_logic_vector(2 downto 0);
enb_res : std_logic;
enb_data_low : std_logic;
enb_data_high : std_logic;
end record;
type t_reg2ctrl is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
end record;
type t_ctrl2prc is record
addr : std_logic_vector(AW-1 downto 0);
mode : std_logic; -- ?????????
enb : std_logic;
end record;
type t_prc2ctrl is record
pc : std_logic_vector(7 downto 0);
exc : std_logic_vector; -- ????????
end record;
-----------------------------------------------------------------------------
-- CPU instruction set
-----------------------------------------------------------------------------
type t_opcode is := (
add => "00000",
sub => "00001",
andi => "00010",
ori => "00011",
xori => "00100",
slai => "00101",
srai => "00110",
mov => "00111",
----------------------------------------------------------------------------
addil => "01100",
addih => "01101",
----------------------------------------------------------------------------
ld => "10000",
st => "10001",
----------------------------------------------------------------------------
jmp => "11000",
bne => "11001",
bge => "11010",
blt => "11011",
----------------------------------------------------------------------------
nop => "11111"
);
end mcu_pkg;
| gpl-2.0 | f940691a75db79e91284744a89592315 | 0.43413 | 4.099272 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/block_simple_two.vhd | 1 | 816 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fnord : block
constant f : natural := 11;
begin
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result(n);
end block fnord;
foo : block
constant i : natural := 10;
begin
result <= ('0' & A) + ('0' & B);
sum <= result(n - 1 downto 0);
carry <= result(n);
end block foo;
end beh;
| gpl-3.0 | 2497a8463fa4d388891f2c224ce69709 | 0.552696 | 3.162791 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_ml605/gtx/wrapper.vhdl | 1 | 3,361 | --
-- Wrapper of gtx example
--
-- Author:
-- * Rodrigo A. Melo, [email protected]
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
clk_i : in std_logic;
rst_i : in std_logic;
clk_o : out std_logic;
--
rxp_i : in std_logic;
rxn_i : in std_logic;
txp_o : out std_logic;
txn_o : out std_logic;
--
loopback_i: in std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_isk_o : out std_logic_vector(1 downto 0);
tx_data_i : in std_logic_vector(15 downto 0);
tx_isk_i : in std_logic_vector(1 downto 0);
ready_o : out std_logic
);
end entity Wrapper;
architecture Structural of Wrapper is
signal refclk : std_logic_vector(1 downto 0);
signal outclk : std_logic;
signal rx_plllkdet : std_logic;
signal usrclk2 : std_logic;
signal rx_ready, tx_ready : std_logic;
signal loopback : std_logic_vector(2 downto 0);
begin
txoutclk_bufg0_i : BUFG
port map (
I => outclk,
O => usrclk2
);
refclk <= '0' & clk_i;
loopback <= '0' & loopback_i & '0';
gtx_v6_i : entity work.gbt1_gtx
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
GTX_TX_CLK_SOURCE => "RXPLL",
GTX_POWER_SAVE => "0000110100"
)
port map (
LOOPBACK_IN => loopback, -- Near-End PMA Loopback
-- RX 8b10b Decoder
RXCHARISK_OUT => rx_isk_o,
RXDISPERR_OUT => open,
RXNOTINTABLE_OUT => open,
-- RX Comma Detection and Alignment
RXBYTEISALIGNED_OUT => open,
RXENMCOMMAALIGN_IN => '1',
RXENPCOMMAALIGN_IN => '1',
-- RX Data Path interface
RXDATA_OUT => rx_data_o,
RXUSRCLK2_IN => usrclk2,
-- RX Driver
RXN_IN => rxn_i,
RXP_IN => rxp_i,
-- RX PLL Ports
GTXRXRESET_IN => rst_i,
MGTREFCLKRX_IN => refclk,
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rx_plllkdet,
RXRESETDONE_OUT => rx_ready,
-- TX 8b10b Encoder Control Ports
TXCHARISK_IN => tx_isk_i,
-- TX Data Path interface
TXDATA_IN => tx_data_i,
TXOUTCLK_OUT => outclk,
TXUSRCLK2_IN => usrclk2,
-- TX Driver
TXN_OUT => txn_o,
TXP_OUT => txp_o,
TXPOSTEMPHASIS_IN => "00000",
TXPREEMPHASIS_IN => "0000",
-- TX PLL Ports
GTXTXRESET_IN => rst_i,
MGTREFCLKTX_IN => refclk,
PLLTXRESET_IN => '0',
TXPLLLKDET_OUT => open,
TXRESETDONE_OUT => tx_ready
);
clk_o <= usrclk2;
ready_o <= rx_ready and tx_ready and rx_plllkdet;
end architecture Structural;
| bsd-3-clause | 17fd830c7a5893d88ffdde710112e694 | 0.468313 | 3.949471 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_simple02.vhd | 1 | 637 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
-- sum <= A xor B xor carryIn;
sum <= '0';
carryOut <= (a and b) or
(b and carryIn) or
(a and carryIn) >
(not ('0' < '1') =
not ('1' > '0'));
fnord <= ('1' or '0') and '1';
end behv;
| gpl-3.0 | 6eecf780a9176b34eaa43f49d146f314 | 0.496075 | 3.266667 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_dff_complex.vhd | 1 | 765 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
clock : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return std_logic;
begin
process(A) is
begin
if rising_edge(clock) then
case "100" is
when "000" => A <= '0';
when "001" => A <= '1';
when "010" => A <= '1';
when "011" => B <= '1';
when "100" => A <= '0';
when "101" => A <= '1';
when "110" => A <= '1';
when "111" => A <= '1';
end case;
end if;
end process;
end behv;
| gpl-3.0 | 3c29a2ffcc6ab60f7128749833f81a54 | 0.47451 | 3.255319 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/elsif_eliminator_nested_test.vhd | 1 | 1,045 | -- FM. MA
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- dummy entity
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fooProc : process is
variable baz : natural := 4711;
begin
-- with else
if (3 = 3) then
baz := 3;
-- nested :3
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
end if;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
else
baz := 100000;
end if;
end process fooProc;
end beh;
| gpl-3.0 | fc4c1cf24ba0e1f632f7df7ece2b2b02 | 0.488038 | 3.392857 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_main_design.vhd | 1 | 8,877 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tb_main_design - Behavioral
--
-- Description:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_main_design is
end tb_main_design;
architecture Behavioral of tb_main_design is
signal clk125Mhz : STD_LOGIC := '0';
signal clk125Mhz90 : STD_LOGIC := '0';
signal phy_ready : STD_LOGIC := '1';
signal status : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
signal input_empty : STD_LOGIC := '0';
signal input_read : STD_LOGIC := '0';
signal input_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal input_data_present : STD_LOGIC := '0';
signal input_data_error : STD_LOGIC := '0';
component main_design is
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal eth_txck : std_logic := '0';
signal eth_txctl : std_logic := '0';
signal eth_txd : std_logic_vector(3 downto 0) := (others => '0');
signal count : integer := 999;
signal count2 : integer := 180;
signal arp_src_hw : std_logic_vector(47 downto 0) := x"A0B3CC4CF9EF";
signal arp_src_ip : std_logic_vector(31 downto 0) := x"0A000001";
signal arp_tgt_hw : std_logic_vector(47 downto 0) := x"000000000000";
signal arp_tgt_ip : std_logic_vector(31 downto 0) := x"0A00000A";
begin
process
begin
clk125Mhz <= '1';
wait for 2 ns;
clk125Mhz90 <= '1';
wait for 2 ns;
clk125Mhz <= '0';
wait for 2 ns;
clk125Mhz90 <= '0';
wait for 2 ns;
end process;
i_main_design: main_design port map (
clk125Mhz => clk125Mhz,
clk125Mhz90 => clk125Mhz90,
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
phy_ready => phy_ready,
status => status,
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
process(clk125MHz)
begin
if rising_edge(clk125MHz) then
if count < 72 then
input_empty <= '0';
else
input_empty <= '1';
end if;
if count2 = 200 then
count <= 0;
count2 <= 0;
else
count2 <= count2+1;
end if;
if input_read = '1' then
if count = 73 then
count <= 0;
else
count <= count + 1;
end if;
case count is
when 0 => input_data <= x"55"; input_data_present <= '1';
when 1 => input_data <= x"55";
when 2 => input_data <= x"55";
when 3 => input_data <= x"55";
when 4 => input_data <= x"55";
when 5 => input_data <= x"55";
when 6 => input_data <= x"55";
when 7 => input_data <= x"D5";
-----------------------------
-- Ethernet Header
-----------------------------
-- Destination MAC address
when 8 => input_data <= x"FF";
when 9 => input_data <= x"FF";
when 10 => input_data <= x"FF";
when 11 => input_data <= x"FF";
when 12 => input_data <= x"FF";
when 13 => input_data <= x"FF";
-- Source MAC address
when 14 => input_data <= x"A0";
when 15 => input_data <= x"B3";
when 16 => input_data <= x"CC";
when 17 => input_data <= x"4C";
when 18 => input_data <= x"F9";
when 19 => input_data <= x"EF";
------------------------
-- ARP packet
------------------------
when 20 => input_data <= x"08"; -- Ether Type 08:06 << ARP!
when 21 => input_data <= x"06";
when 22 => input_data <= x"00"; -- Media type
when 23 => input_data <= x"01";
when 24 => input_data <= x"08"; -- Protocol (IP)
when 25 => input_data <= x"00";
when 26 => input_data <= x"06"; -- Hardware address length
when 27 => input_data <= x"04"; -- Protocol address length
-- Operation
when 28 => input_data <= x"00";
when 29 => input_data <= x"01"; -- request
-- Target MAC
when 30 => input_data <= arp_src_hw(47 downto 40);
when 31 => input_data <= arp_src_hw(39 downto 32);
when 32 => input_data <= arp_src_hw(31 downto 24);
when 33 => input_data <= arp_src_hw(23 downto 16);
when 34 => input_data <= arp_src_hw(15 downto 8);
when 35 => input_data <= arp_src_hw( 7 downto 0);
-- Target IP
when 36 => input_data <= arp_src_ip(31 downto 24);
when 37 => input_data <= arp_src_ip(23 downto 16);
when 38 => input_data <= arp_src_ip(15 downto 8);
when 39 => input_data <= arp_src_ip( 7 downto 0);
-- Source MAC
when 40 => input_data <= arp_tgt_hw(47 downto 40);
when 41 => input_data <= arp_tgt_hw(39 downto 32);
when 42 => input_data <= arp_tgt_hw(31 downto 24);
when 43 => input_data <= arp_tgt_hw(23 downto 16);
when 44 => input_data <= arp_tgt_hw(15 downto 8);
when 45 => input_data <= arp_tgt_hw( 7 downto 0);
-- Source IP
when 46 => input_data <= arp_tgt_ip(31 downto 24);
when 47 => input_data <= arp_tgt_ip(23 downto 16);
when 48 => input_data <= arp_tgt_ip(15 downto 8);
when 49 => input_data <= arp_tgt_ip( 7 downto 0);
-- We can release the bus now and go back to the idle state.
when 50 => input_data <= x"00";
when 51 => input_data <= x"00";
when 52 => input_data <= x"00";
when 53 => input_data <= x"00";
when 54 => input_data <= x"00";
when 55 => input_data <= x"00";
when 56 => input_data <= x"00";
when 57 => input_data <= x"00";
when 58 => input_data <= x"00";
when 59 => input_data <= x"00";
when 60 => input_data <= x"00";
when 61 => input_data <= x"00";
when 62 => input_data <= x"00";
when 63 => input_data <= x"00";
when 64 => input_data <= x"00";
when 65 => input_data <= x"00";
when 66 => input_data <= x"00";
when 67 => input_data <= x"12";
when 68 => input_data <= x"12";
when 69 => input_data <= x"12";
when 70 => input_data <= x"12";
when 71 => input_data <= x"DD"; input_data_present <= '0';
when others => input_data <= x"DD"; input_data_present <= '0';
end case;
count2 <= 0;
end if;
end if;
end process;
end Behavioral;
| mit | 9af4c7f4d16672425f1bf82efeac056e | 0.404641 | 4.219106 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/icmp/icmp_extract_ip_header.vhd | 1 | 6,555 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.05.2016 21:56:31
-- Design Name:
-- Module Name: icmp_extract_ip_header - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity icmp_extract_ip_header is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_version : out STD_LOGIC_VECTOR ( 3 downto 0) := (others => '0');
ip_type_of_service : out STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_length : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_identification : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_flags : out STD_LOGIC_VECTOR ( 2 downto 0) := (others => '0');
ip_fragment_offset : out STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
ip_ttl : out STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_protocol : out STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_checksum : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_src_ip : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dest_ip : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end icmp_extract_ip_header;
architecture Behavioral of icmp_extract_ip_header is
signal count : unsigned(6 downto 0) := (others => '0');
signal header_len : unsigned(6 downto 0) := (others => '0');
signal i_ip_version : STD_LOGIC_VECTOR ( 3 downto 0) := (others => '0');
signal i_ip_type_of_service : STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
signal i_ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ip_identification : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ip_flags : STD_LOGIC_VECTOR ( 2 downto 0) := (others => '0');
signal i_ip_fragment_offset : STD_LOGIC_VECTOR (12 downto 0) := (others => '0');
signal i_ip_ttl : STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
signal i_ip_protocol : STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
signal i_ip_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_ip_src_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
signal i_ip_dest_ip : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
begin
ip_version <= i_ip_version;
ip_type_of_service <= i_ip_type_of_service;
ip_length <= i_ip_length;
ip_identification <= i_ip_identification;
ip_flags <= i_ip_flags;
ip_fragment_offset <= i_ip_fragment_offset;
ip_ttl <= i_ip_ttl;
ip_protocol <= i_ip_protocol;
ip_checksum <= i_ip_checksum;
ip_src_ip <= i_ip_src_ip;
ip_dest_ip <= i_ip_dest_ip;
process(clk)
begin
if rising_edge(clk) then
data_out <= data_in;
if data_valid_in = '1' then
-- Note, at count of zero,
case count is
when "0000000" => i_ip_version <= data_in(7 downto 4);
header_len(5 downto 2) <= unsigned(data_in(3 downto 0));
when "0000001" => i_ip_type_of_service <= data_in;
when "0000010" => i_ip_length(15 downto 8) <= data_in;
when "0000011" => i_ip_length( 7 downto 0) <= data_in;
when "0000100" => i_ip_identification(15 downto 8) <= data_in;
when "0000101" => i_ip_identification( 7 downto 0) <= data_in;
when "0000110" => i_ip_fragment_offset(12 downto 8) <= data_in(4 downto 0);
i_ip_flags <= data_in(7 downto 5);
when "0000111" => i_ip_fragment_offset( 7 downto 0) <= data_in;
when "0001000" => i_ip_ttl <= data_in;
when "0001001" => i_ip_protocol <= data_in;
when "0001010" => i_ip_checksum(15 downto 8) <= data_in;
when "0001011" => i_ip_checksum( 7 downto 0) <= data_in;
when "0001100" => i_ip_src_ip( 7 downto 0) <= data_in;
when "0001101" => i_ip_src_ip(15 downto 8) <= data_in;
when "0001110" => i_ip_src_ip(23 downto 16) <= data_in;
when "0001111" => i_ip_src_ip(31 downto 24) <= data_in;
when "0010000" => i_ip_dest_ip( 7 downto 0) <= data_in;
when "0010001" => i_ip_dest_ip(15 downto 8) <= data_in;
when "0010010" => i_ip_dest_ip(23 downto 16) <= data_in;
when "0010011" => i_ip_dest_ip(31 downto 24) <= data_in;
when others => null;
end case;
-- So that additional IP options get dropped
if unsigned(count) >= unsigned(header_len) and unsigned(count) > 4
and i_ip_version = x"4" and i_ip_protocol = x"01"
and i_ip_dest_ip = our_ip then
data_valid_out <= data_valid_in;
data_out <= data_in;
end if;
if count /= "1111111" then
count <= count+1;
end if;
else
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| mit | e2825262edf6f78f3335c545f0a41258 | 0.45553 | 3.69921 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/main_design.vhd | 1 | 26,620 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: main_design - Behavioral
--
-- Description: Top level of the IP processing design.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity main_design is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
Port (
clk125Mhz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
phy_ready : in STD_LOGIC;
status : out STD_LOGIC_VECTOR (3 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '1';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_checksum : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
eth_txck : out std_logic := '0';
eth_txctl : out std_logic := '0';
eth_txd : out std_logic_vector(3 downto 0) := (others => '0'));
end main_design;
architecture Behavioral of main_design is
constant our_broadcast : std_logic_vector(31 downto 0) := our_ip or (not our_netmask);
component detect_speed_and_reassemble_bytes is
Port ( clk125Mhz : in STD_LOGIC;
-- Interface to input FIFO
input_empty : in STD_LOGIC;
input_read : out STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
link_10mb : out STD_LOGIC;
link_100mb : out STD_LOGIC;
link_1000mb : out STD_LOGIC;
link_full_duplex : out STD_LOGIC;
output_data_enable : out STD_LOGIC;
output_data : out STD_LOGIC_VECTOR (7 downto 0);
output_data_present : out STD_LOGIC;
output_data_error : out STD_LOGIC);
end component;
signal spaced_out_data_enable : STD_LOGIC;
signal spaced_out_data : STD_LOGIC_VECTOR (7 downto 0);
signal spaced_out_data_present : STD_LOGIC;
signal spaced_out_data_error : STD_LOGIC;
signal link_10mb : STD_LOGIC;
signal link_100mb : STD_LOGIC;
signal link_1000mb : STD_LOGIC;
signal link_full_duplex : STD_LOGIC;
component defragment_and_check_crc is
Port (
clk : in STD_LOGIC;
input_data_enable : in STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
packet_data_valid : out STD_LOGIC;
packet_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal packet_data_valid : STD_LOGIC;
signal packet_data : STD_LOGIC_VECTOR (7 downto 0);
-------------------------------------------
-- Protocol handlers
-------------------------------------------
component arp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_netmask : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic;
packet_out_data : out std_logic_vector(7 downto 0);
-- For the wider design to send any ARP on the wire
queue_request : in std_logic;
queue_request_ip : in std_logic_vector(31 downto 0);
-- to enable IP->MAC lookup for outbound packets
update_valid : out std_logic;
update_ip : out std_logic_vector(31 downto 0);
update_mac : out std_logic_vector(47 downto 0));
end component;
signal packet_arp_request : std_logic;
signal packet_arp_granted : std_logic;
signal packet_arp_valid : std_logic;
signal packet_arp_data : std_logic_vector(7 downto 0);
signal arp_queue_request : std_logic := '0';
signal arp_queue_request_ip : std_logic_vector(31 downto 0) := (others => '0');
signal arp_update_valid : std_logic := '0';
signal arp_update_ip : std_logic_vector(31 downto 0) := (others => '0');
signal arp_update_mac : std_logic_vector(47 downto 0) := (others => '0');
component icmp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- For receiving data from the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic;
packet_out_data : out std_logic_vector(7 downto 0));
end component;
signal packet_icmp_request : std_logic;
signal packet_icmp_granted : std_logic;
signal packet_icmp_valid : std_logic;
signal packet_icmp_data : std_logic_vector(7 downto 0);
component udp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_broadcast : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
-- For receiving data from the PHY
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- data received over UDP
udp_rx_valid : out std_logic := '0';
udp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_rx_dst_broadcast : out std_logic := '0';
udp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over UDP
udp_tx_busy : out std_logic := '0';
udp_tx_valid : in std_logic := '0';
udp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
-- For sending data to the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal packet_udp_request : std_logic;
signal packet_udp_granted : std_logic;
signal packet_udp_valid : std_logic;
signal packet_udp_data : std_logic_vector(7 downto 0);
component tcp_handler is
generic (
our_mac : std_logic_vector(47 downto 0) := (others => '0');
our_ip : std_logic_vector(31 downto 0) := (others => '0'));
port ( clk : in STD_LOGIC;
-- For receiving data from the PHY
packet_in_valid : in STD_LOGIC;
packet_in_data : in STD_LOGIC_VECTOR (7 downto 0);
-- data received over TCP/IP
tcp_rx_data_valid : out std_logic := '0';
tcp_rx_data : out std_logic_vector(7 downto 0) := (others => '0');
tcp_rx_hdr_valid : out std_logic := '0';
tcp_rx_src_ip : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_rx_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_rx_flag_urg : out std_logic := '0';
tcp_rx_flag_ack : out std_logic := '0';
tcp_rx_flag_psh : out std_logic := '0';
tcp_rx_flag_rst : out std_logic := '0';
tcp_rx_flag_syn : out std_logic := '0';
tcp_rx_flag_fin : out std_logic := '0';
tcp_rx_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
-- data to be sent over TCP/IP
tcp_tx_busy : out std_logic := '0';
tcp_tx_data_valid : in std_logic := '0';
tcp_tx_data : in std_logic_vector(7 downto 0) := (others => '0');
tcp_tx_hdr_valid : in std_logic := '0';
tcp_tx_src_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_dst_mac : in std_logic_vector(47 downto 0) := (others => '0');
tcp_tx_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_tx_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_tx_flag_urg : in std_logic := '0';
tcp_tx_flag_ack : in std_logic := '0';
tcp_tx_flag_psh : in std_logic := '0';
tcp_tx_flag_rst : in std_logic := '0';
tcp_tx_flag_syn : in std_logic := '0';
tcp_tx_flag_fin : in std_logic := '0';
tcp_tx_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
-- For sending data to the PHY
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic;
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
signal packet_tcp_request : std_logic;
signal packet_tcp_granted : std_logic;
signal packet_tcp_valid : std_logic;
signal packet_tcp_data : std_logic_vector(7 downto 0);
-------------------------------------------
-- TX Interface
-------------------------------------------
component tx_interface is
Port ( clk125MHz : in STD_LOGIC;
clk125Mhz90 : in STD_LOGIC;
--
phy_ready : in STD_LOGIC;
link_10mb : in STD_LOGIC;
link_100mb : in STD_LOGIC;
link_1000mb : in STD_LOGIC;
---
arp_request : in STD_LOGIC;
arp_granted : out STD_LOGIC;
arp_valid : in STD_LOGIC;
arp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
icmp_request : in STD_LOGIC;
icmp_granted : out STD_LOGIC;
icmp_valid : in STD_LOGIC;
icmp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
tcp_request : in STD_LOGIC;
tcp_granted : out STD_LOGIC;
tcp_valid : in STD_LOGIC;
tcp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
udp_request : in STD_LOGIC;
udp_granted : out STD_LOGIC;
udp_valid : in STD_LOGIC;
udp_data : in STD_LOGIC_VECTOR (7 downto 0);
---
eth_txck : out STD_LOGIC;
eth_txctl : out STD_LOGIC;
eth_txd : out STD_LOGIC_VECTOR (3 downto 0));
end component;
begin
status <= link_full_duplex & link_1000mb & link_100mb & link_10mb;
----------------------------------------------------------------------
-- As well as converting nibbles to bytes (for the slowe speeds)
-- this also strips out the preamble and start of frame symbols
----------------------------------------------------------------------
i_detect_speed_and_reassemble_bytes: detect_speed_and_reassemble_bytes port map (
clk125Mhz => clk125Mhz,
-- Interface to input FIFO
input_empty => input_empty,
input_read => input_read,
input_data => input_data,
input_data_present => input_data_present,
input_data_error => input_data_error,
link_10mb => link_10mb,
link_100mb => link_100mb,
link_1000mb => link_1000mb,
link_full_duplex => link_full_duplex,
output_data_enable => spaced_out_data_enable,
output_data => spaced_out_data,
output_data_present => spaced_out_data_present,
output_data_error => spaced_out_data_error);
----------------------------------------------------------------------
-- Even at gigabit speeds the stream of bytes might include
-- gaps due to differences between the source and destination clocks.
-- This module packs all the bytes in a packet close togeather, so
-- they can be streamed though the rest of the design without using
-- a Data Enable line.
--
-- It also provides a handy place to check the FCS, allowing pacckets
-- with errors or corruption to be dropped early.
----------------------------------------------------------------------
i_defragment_and_check_crc: defragment_and_check_crc port map (
clk => clk125Mhz,
input_data_enable => spaced_out_data_enable,
input_data => spaced_out_data,
input_data_present => spaced_out_data_present,
input_data_error => spaced_out_data_error,
packet_data_valid => packet_data_valid,
packet_data => packet_data);
i_arp_handler:arp_handler generic map (
our_mac => our_mac,
our_netmask => our_netmask,
our_ip => our_ip)
port map (
clk => clk125MHz,
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- For Sending data to the PHY
packet_out_request => packet_arp_request,
packet_out_granted => packet_arp_granted,
packet_out_valid => packet_arp_valid,
packet_out_data => packet_arp_data,
-- to enable the wider design to send ARP requests
queue_request => arp_queue_request,
queue_request_ip => arp_queue_request_ip,
-- to enable IP->MAC lookup for outbound packets
update_valid => arp_update_valid,
update_ip => arp_update_ip,
update_mac => arp_update_mac);
i_icmp_handler: icmp_handler generic map (
our_mac => our_mac,
our_ip => our_ip)
port map (
clk => clk125MHz,
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- For Sending data to the PHY
packet_out_request => packet_icmp_request,
packet_out_granted => packet_icmp_granted,
packet_out_valid => packet_icmp_valid,
packet_out_data => packet_icmp_data);
i_udp_handler: udp_handler
generic map (
our_mac => our_mac,
our_ip => our_ip,
our_broadcast => our_broadcast)
port map (
clk => clk125MHz,
-- For receiving data from the PHY
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- data received over UDP. Note IP address and port numbers
-- are only valid for the first cycle of a packet each
udp_rx_valid => udp_rx_valid,
udp_rx_data => udp_rx_data,
udp_rx_src_ip => udp_rx_src_ip,
udp_rx_src_port => udp_rx_src_port,
udp_rx_dst_broadcast => udp_rx_dst_broadcast,
udp_rx_dst_port => udp_rx_dst_port,
-- data to be sent over UDP
udp_tx_busy => udp_tx_busy,
udp_tx_valid => udp_tx_valid,
udp_tx_data => udp_tx_data,
udp_tx_src_port => udp_tx_src_port,
udp_tx_dst_mac => udp_tx_dst_mac,
udp_tx_dst_ip => udp_tx_dst_ip,
udp_tx_dst_port => udp_tx_dst_port,
-- For sending data to the PHY
packet_out_request => packet_udp_request,
packet_out_granted => packet_udp_granted,
packet_out_valid => packet_udp_valid,
packet_out_data => packet_udp_data);
i_tcp_handler: tcp_handler
generic map (
our_mac => our_mac,
our_ip => our_ip)
port map (
clk => clk125MHz,
-- For receiving data from the PHY
packet_in_valid => packet_data_valid,
packet_in_data => packet_data,
-- data received over TCP/IP
tcp_rx_data_valid => tcp_rx_data_valid,
tcp_rx_data => tcp_rx_data,
tcp_rx_hdr_valid => tcp_rx_hdr_valid,
tcp_rx_src_ip => tcp_rx_src_ip,
tcp_rx_src_port => tcp_rx_src_port,
tcp_rx_dst_port => tcp_rx_dst_port,
tcp_rx_seq_num => tcp_rx_seq_num,
tcp_rx_ack_num => tcp_rx_ack_num,
tcp_rx_window => tcp_rx_window,
tcp_rx_checksum => tcp_rx_checksum,
tcp_rx_flag_urg => tcp_rx_flag_urg,
tcp_rx_flag_ack => tcp_rx_flag_ack,
tcp_rx_flag_psh => tcp_rx_flag_psh,
tcp_rx_flag_rst => tcp_rx_flag_rst,
tcp_rx_flag_syn => tcp_rx_flag_syn,
tcp_rx_flag_fin => tcp_rx_flag_fin,
tcp_rx_urgent_ptr => tcp_rx_urgent_ptr,
-- data to be sent over TCP/IP
tcp_tx_busy => tcp_tx_busy,
tcp_tx_data_valid => tcp_tx_data_valid,
tcp_tx_data => tcp_tx_data,
tcp_tx_hdr_valid => tcp_tx_hdr_valid,
tcp_tx_src_port => tcp_tx_src_port,
tcp_tx_dst_mac => x"EF_F9_4C_CC_B3_A0",
tcp_tx_dst_ip => tcp_tx_dst_ip,
tcp_tx_dst_port => tcp_tx_dst_port,
tcp_tx_seq_num => tcp_tx_seq_num,
tcp_tx_ack_num => tcp_tx_ack_num,
tcp_tx_window => tcp_tx_window,
tcp_tx_flag_urg => tcp_tx_flag_urg,
tcp_tx_flag_ack => tcp_tx_flag_ack,
tcp_tx_flag_psh => tcp_tx_flag_psh,
tcp_tx_flag_rst => tcp_tx_flag_rst,
tcp_tx_flag_syn => tcp_tx_flag_syn,
tcp_tx_flag_fin => tcp_tx_flag_fin,
tcp_tx_urgent_ptr => tcp_tx_urgent_ptr,
-- For sending data to the PHY
packet_out_request => packet_tcp_request,
packet_out_granted => packet_tcp_granted,
packet_out_valid => packet_tcp_valid,
packet_out_data => packet_tcp_data);
i_tx_interface: tx_interface port map (
clk125MHz => clk125MHz,
clk125Mhz90 => clk125Mhz90,
--- Link status
phy_ready => phy_ready,
link_10mb => link_10mb,
link_100mb => link_100mb,
link_1000mb => link_1000mb,
--- ARP channel
arp_request => packet_arp_request,
arp_granted => packet_arp_granted,
arp_valid => packet_arp_valid,
arp_data => packet_arp_data,
--- TCP channel
tcp_request => packet_tcp_request,
tcp_granted => packet_tcp_granted,
tcp_valid => packet_tcp_valid,
tcp_data => packet_tcp_data,
--- ICMP channel
icmp_request => packet_icmp_request,
icmp_granted => packet_icmp_granted,
icmp_valid => packet_icmp_valid,
icmp_data => packet_icmp_data,
--- UDP channel
udp_request => packet_udp_request,
udp_granted => packet_udp_granted,
udp_valid => packet_udp_valid,
udp_data => packet_udp_data,
---
eth_txck => eth_txck,
eth_txctl => eth_txctl,
eth_txd => eth_txd);
end Behavioral; | mit | 4bdc8aacc2389419a9dbeff54257f82e | 0.508565 | 3.606557 | false | false | false | false |
hamsternz/FPGA_Webserver | testbenches/tb_defragment_and_check_crc.vhd | 1 | 3,285 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23.05.2016 06:48:08
-- Design Name:
-- Module Name: tb_defragment_and_check_crc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_defragment_and_check_crc is
Port ( a : in STD_LOGIC);
end tb_defragment_and_check_crc;
architecture Behavioral of tb_defragment_and_check_crc is
component defragment_and_check_crc is
Port ( clk : in STD_LOGIC;
input_data_enable : in STD_LOGIC;
input_data : in STD_LOGIC_VECTOR (7 downto 0);
input_data_present : in STD_LOGIC;
input_data_error : in STD_LOGIC;
packet_data_valid : out STD_LOGIC;
packet_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal count : unsigned (7 downto 0) := "00000000";
signal clk : std_logic := '0';
signal spaced_out_data_enable : std_logic := '0';
signal spaced_out_data : std_logic_vector(7 downto 0);
signal spaced_out_data_present : std_logic := '0';
signal spaced_out_data_error : std_logic := '0';
signal packet_data_valid : std_logic := '0';
signal packet_data : std_logic_vector(7 downto 0) := (others => '0');
begin
process
begin
wait for 5 ns;
clk <= not clk;
end process;
process(clk)
begin
if rising_edge(clk) then
-- if count(1 downto 0) = "000" then
spaced_out_data <= "000" & std_logic_vector(count(4 downto 0));
spaced_out_data_enable <= '1';
if count(4 downto 0) = "00000" then
spaced_out_data_enable <= '0';
spaced_out_data_present <= '0';
elsif count(4 downto 0) = "11111" then
spaced_out_data_enable <= '1';
spaced_out_data_present <= '0';
else
spaced_out_data_enable <= '1';
spaced_out_data_present <= '1';
end if;
-- else
-- spaced_out_data <= "00000000";
-- spaced_out_data_present <= '0';
-- end if;
count <= count + 1;
end if;
end process;
uut: defragment_and_check_crc port map (
clk => clk,
input_data_enable => spaced_out_data_enable,
input_data => spaced_out_data,
input_data_present => spaced_out_data_present,
input_data_error => spaced_out_data_error,
packet_data_valid => packet_data_valid,
packet_data => packet_data);
end Behavioral;
| mit | 5e34dec0cbb6b058bc555cea1976bf72 | 0.499543 | 3.851114 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_latch_complex.vhd | 1 | 701 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : out std_logic;
B : out std_logic;
sig : in std_logic_vector(1 downto 0);
C : in std_logic);
end adder;
architecture behv of adder is
function rising_edge(c : in std_logic) return boolean;
begin
process(A) is
begin
if A = B then
if not A then
case sig is
when "00" => C <= '0';
when "01" => C <= '0';
when "10" => C <= '1';
when "11" => C <= '0';
end case;
end if;
end if;
end process;
end behv;
| gpl-3.0 | 78823c02aad20ef2173a5625a40378ed | 0.49786 | 3.386473 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/icmp/icmp_extract_icmp_header.vhd | 1 | 4,969 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: icmp_extract_icmp_header - Behavioral
--
-- Description: Remove the ICMP header details off of the data packet
-- and pass the data on if valid.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity icmp_extract_icmp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
icmp_type : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
icmp_code : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
icmp_checksum : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
icmp_identifier : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
icmp_sequence : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0'));
end icmp_extract_icmp_header;
architecture Behavioral of icmp_extract_icmp_header is
signal count : unsigned(3 downto 0) := (others => '0');
signal i_icmp_type : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal i_icmp_code : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal i_icmp_checksum : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_icmp_identifier : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal i_icmp_sequence : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
begin
icmp_type <= i_icmp_type;
icmp_code <= i_icmp_code;
icmp_checksum <= i_icmp_checksum;
icmp_identifier <= i_icmp_identifier;
icmp_sequence <= i_icmp_sequence;
process(clk)
begin
if rising_edge(clk) then
data_out <= data_in;
if data_valid_in = '1' then
-- Note, at count of zero,
case count is
when "0000" => i_icmp_type <= data_in;
when "0001" => i_icmp_code <= data_in;
when "0010" => i_icmp_checksum(7 downto 0) <= data_in;
when "0011" => i_icmp_checksum(15 downto 8) <= data_in;
when "0100" => i_icmp_identifier(7 downto 0) <= data_in;
when "0101" => i_icmp_identifier(15 downto 8) <= data_in;
when "0110" => i_icmp_sequence(7 downto 0) <= data_in;
when "0111" => i_icmp_sequence(15 downto 8) <= data_in;
when others => if i_icmp_type = x"08" and i_icmp_code = x"00" then
data_valid_out <= data_valid_in;
data_out <= data_in;
else
data_valid_out <= '0';
data_out <= (others => '0');
end if;
end case;
if count /= "1111" then
count <= count+1;
end if;
else
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| mit | 7201980d54a66754bad26c3d95813bf6 | 0.516603 | 4.161642 | false | false | false | false |
Remillard/VHDL-Mode | Test/beautify_test.vhd | 1 | 26,841 | -------------------------------------------------------------------------------
-- Last update : Fri Jun 14 13:31:50 2019
-- Project : VHDL Mode for Sublime Text
-------------------------------------------------------------------------------
-- Description: This VHDL file is intended as a test of scope and beautifier
-- functions for the VHDL Mode package. It should never be actually compiled
-- as I do several strange things to make sure various aspects of beautification
-- and syntax scoping are checked.
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- VHDL-2008 package library use.
package master_bfm is new work.avalon_bfm_pkg
generic map
(
G_DATA_WIDTH => 32,
G_ADDR_WIDTH => 10,
G_BURST_WIDTH => 4
);
use work.master_bfm.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
/*
VHDL-2008 Block Comment
test zone.
*/
--/* Invalid layered
commenting */
--/* Valid layered
-- commenting */
-------------------------------------------------------------------------------
-- ENTITY STYLE TEST
-------------------------------------------------------------------------------
---------------------------------------
-- Sloppy Comment Test
-- Basically checking that comments are
-- preserved and do not affect
-- beautification or port copying.
---------------------------------------
-- Comment above
entity my_entity is -- comments everywhere
generic( -- I mean everywhere
DATA_WIDTH : integer := 8; -- This value is 8
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4" -- This comment should align with prior
); -- Holy crap another comment -- with a comment inside the -- comment
port ( -- What about a comment here?
-- Basic ports
clk : in std_logic;
-- Another comment on a line by itself!
reset : in std_logic; -- And here's an inline comment.
--d : in std_logic; -- Oh no! I commented out an actual line
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic); -- And finally
-- A final
end entity my_entity; -- Comment
-- Comment below.
---------------------------------------
-- Blank Entity (and variations)
---------------------------------------
entity foobar is
end entity foobar;
entity entity_1 is
end entity_1;
entity entity_1 is
end entity;
package foo2 is
end package foo2;
package body foo2 is
end package body foo2;
architecture test of thing is
begin
end architecture test;
configuration MY_IDENT of thing is
end configuration MY_IDENT;
---------------------------------------
-- K&R Style Approximate. entity/end
-- form the main block which shares the
-- same indent level, and inside opening
-- parens are on the same line as the
-- keyword, closing parens are at same
-- level as keyword.
---------------------------------------
entity kr_style_entity is
generic (
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default
);
port (
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : type(3 downto 0) := X"4";
item_12345 : out type
);
end entity kr_style_entity;
---------------------------------------
-- Allman Style (C Style). Parens share
-- same indent level as associated keyword
---------------------------------------
entity allman_style_entity is
generic
(
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default
);
port
(
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : in type(3 downto 0) := X"4";
item_12345 : out type
);
end entity allman_style_entity;
---------------------------------------
-- Lisp Style: emacs vhdl-mode style
-- with the closing paren on the final
-- item line.
---------------------------------------
entity lisp_style_entity is
generic (
item_1 : type;
item_12 : type := default;
item_123 : longer_type := other_default);
port (
item_1 : in type;
item_12 : out type;
item_123 : inout type := default;
item_1234 : in type(3 downto 0) := X"4";
item_12345 : out type);
end entity lisp_style_entity;
--------------------------------------------------------------------------------
-- EXTENDED ENTITY TEST -- Uses the passive statements, assertion, a passive
-- procedure, a passive process. VHDL-2008 inclusion of PSL Directives is
-- beyond the scope of this as I don't have a PSL syntax file.
--------------------------------------------------------------------------------
entity passive_test is
generic (
G_ADDR_WIDTH : integer := 10;
G_DATA_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
addr : in std_logic_vector(G_ADDR_WIDTH-1 downto 0);
data_in : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
we : in std_logic;
data_out : out std_logic_vector(G_DATA_WIDTH-1 downto 0)
);
begin
CHECK : assert (G_DATA_WIDTH <= 32)
report "ERROR : DATA WIDTH TOO LARGE (>32)"
severity ERROR;
TIME_CHECK : process (we) is
begin
if (we = '1') then
report "MEMORY WRITTEN AT TIME" & to_string(now);
end if;
end process TIME_CHECK;
my_passive_procedure(clk, addr, result);
end entity passive_test;
-------------------------------------------------------------------------------
-- END ENTITY TEST
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 0 HERE IF ALL TESTS PASS
-------------------------------------------------------------------------------
configuration foobar of my_entity is
use work.my_package.all;
for rtl
use lala.other_thing.all;
end for;
end configuration foobar;
architecture rtl of my_entity is
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- COMPONENT STYLE TEST. Also checking lexing of variations in optional
-- words for components.
-------------------------------------------------------------------------------
-- K&R Style
component kr_style_component is
generic (
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4"
);
port (
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic
);
end component kr_style_component;
-- Allman Style
component allman_style_component
generic
(
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4"
);
port
(
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic
);
end component allman_style_component;
-- Lisp Style
component lisp_style_component is
generic (
DATA_WIDTH : integer := 8;
REALLY_LONG_GENERIC : std_logic_vector(3 downto 0) := X"4");
port (
clk : in std_logic;
reset : in std_logic;
a, b, c : in std_logic_vector(3 downto 0);
q : out std_logic);
end component;
-------------------------------------------------------------------------------
-- END COMPONENT STYLE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- SIGNALS TEST
-------------------------------------------------------------------------------
signal my_signal_1 : std_logic;
signal my_signal_2 : std_logic_vector(3 downto 0);
signal a, b, c : std_logic := '1';
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
constant C_CLOCK_PERIOD : real := 1.23e-9;
constant MY_PI : real := 3.141592654;
constant C_FOO, C_BAR : integer := 999;
constant C_OPERATOR_CHECK : std_logic_vector(31 downto 0) :=
std_logic_vector(to_unsigned(1, 8)) &
std_logic_vector(to_unsigned(2, 8)) &
std_logic_vector(to_unsigned(3, 8)) &
std_logic_vector(to_unsigned(4, 8));
alias slv is std_logic_vector;
alias 'c' is letter_c;
alias + is plus;
alias bus_rev : std_logic_vector is bus_thing;
begin
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INSTANTIATION TESTS
-------------------------------------------------------------------------------
-- Direct entity instantiation tests.
-- K&R Style
my_entity_1 : entity work.my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Allman Style
my_entity_1 : entity work.my_entity
generic map
(
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map
(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Lisp Style
my_entity_1 : entity work.my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q);
-- Component instantiation tests
-- K&R Style
my_entity_1 : component my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Allman Style
my_entity_1 : my_entity
generic map
(
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC
)
port map
(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q
);
-- Lisp Style
my_entity_1 : my_entity
generic map (
DATA_WIDTH => DATA_WIDTH,
REALLY_LONG_GENERIC => REALLY_LONG_GENERIC)
port map (
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
q => q,
x(1) => z,
y(3 downto 0) => 9,
z(x'range) => zz);
i_if_cpu : if_cpu
port map (
clk => clk,
reset => reset,
a => a,
b => b
);
-------------------------------------------------------------------------------
-- END OF INSTANTIATION TESTS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MIXED CODE TESTS
-------------------------------------------------------------------------------
SEQUENTIAL_PROCESS : process (clk, reset)
variable my_variable : integer;
shared variable alpha : std_logic_vector(31 downto 0);
begin
-- If/then normal style
IF_LABEL : if (reset = '1') then
q1 <= '0';
q2_long <= '1';
q3 <= b"1010Y";
octal_test <= 12o"01234567_XY";
hex_test := 7X"0123456789--aAbBcCdDeEfF_XY"; -- Comment
bool_test := true;
elsif rising_edge(clk) then
if (ce = '1') then
q1 <= d1;
q2_long <= d2_long;
-- Some syntax number matching.
x0 <= 25_6;
x1 <= 16#1234_ABCD_EF#;
x2 <= 10#1024#E+00;
x3 <= 1_024e-9;
y0 <= 3.141_592_654;
y1 <= 1_2.5e-9;
y2 <= 2#0.1_0#;
y3 <= 10#10_24.0#E+00;
z0 <= math_pi;
a <= 3 + 4;
pt1 <= 0;
pt2 <= (0);
end if;
end if;
-- If/then Leo style (heaven help us)
if (my_condition_a = 1)
then a <= b;
elsif (my_condition_b = 2)
then c <= d;
else e <= f;
end if;
-- Extremely long conditional test
if (((a and b) and (x or y) or
((m or n) and c
or d) and
boolean)) then
g <= h;
end if;
-- Case test long form
CASE_LABEL : case my_tester is
when 1 =>
a <= b;
c <= d;
when 2 =>
e <= f;
g <= h;
when 3 =>
i <= j;
k <= l;
when 4 =>
foo <= (others => '0');
when others =>
null;
end case CASE_LABEL;
-- Case test compact form
-- The fix for the alignment of => breaks alignment here, but it's
-- probably okay. Compact is already readable.
case my_test is
when a => a <= b;
when c => c <= d;
when others => e <= f;
end case;
-- Case test for alignment of => in a case statement.
case my_alignment_test is
when a =>
long_signal_name <= (others => '0');
when b =>
another_long_name <= (others => '0');
when others =>
a_third_long_name <= (others => '0');
end case;
end process SEQUENTIAL_PROCESS;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
COMBINATORIAL_PROCESS : process (all)
begin
wait;
wait until (a > b);
wait for 10 ns;
-- Procedure calls
SUBPROGRAM_CALL_LABEL : my_subprogram_call(values);
ANOTHER_CALL : some_write(L, string'("Text"));
write(L, string'("foobar"));
std.env.stop(0);
stop(0);
-- Loop tests
MY_BASIC_LOOP : loop
end loop MY_BASIC_LOOP;
MY_LOOP : loop
MY_INNER_LOOP : loop
next;
end loop MY_INNER_LOOP;
MY_WHILE_LOOP : while (a > b) loop
a <= b;
end loop;
exit;
end loop MY_LOOP;
MY_FOR_LOOP : for index in 0 to 9 loop
if (condition) then
a := b;
counter := counter + 1;
else
next;
end if;
end loop MY_FOR_LOOP;
end process COMBINATORIAL_PROCESS;
-------------------------------------------------------------------------------
-- Process name variations
-------------------------------------------------------------------------------
process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end process;
LABEL : process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end process;
LABEL : postponed process (clk, reset)
begin
if (reset = '1') then
elsif rising_edge(clk) then
end if;
end postponed process LABEL;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
-- Assignment statements
foo <= bar;
foo(99) <= signal_name;
foo(15 downto 0) <= other_signal_name(15 downto 0);
foo(some_signal'range) <= yet_another_name'range;
foo(other_signal'reverse_range) <= foo(15 downto 0);
foo(to_integer(my_unsigned)) <= 97;
foo(some_signal'range) <= yet_another_name'range;
foo(other_signal'reverse_range) <= foo(15 downto 0);
adder1 <= ( '0' & add_l) + ( '0' & add_m);
adder2 <= ("0" & add_r) + ('0' & add_b);
adder <= ('0' & adder1) + ('0' & adder2);
bus_rw <= '1' when (condition) else '0';
mux_output <= selection_1 when condition else
selection_2 when condition else
selection_3 when condition else
selection_4 when others;
mux_output <=
selection_1 when condition else
selection_2 when condition else
selection_3 when condition else
selection_4 when others;
with my_signal select
address <=
adc_addr when choice1,
temp_sensor_addr when choice2,
light_sense_addr when choice3,
X"0000" when others;
with my_signal select
a <= adc_addr when choice1,
temp_sensor_addr when choice2,
light_sense_addr when choice3,
X"0000" when others;
with my_signal select a <=
tiny when choice1,
bigger when choice2,
really_long when choice3,
X"0000" when others;
data_bus_miso <=
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"00000001" when (std_match(addr_bus, C_MY_ADDRESS_1)),
X"FFFFFFFF" when others;
assert (condition)
report "This string would \nget printed in a simulator. -- Comment Test /* Other comment test */"
severity WARNING;
-------------------------------------------------------------------------------
-- INDENT LEVEL SHOULD BE AT LEVEL 1 HERE
-------------------------------------------------------------------------------
MY_GENERATOR : for x in 0 to 7 generate
signal a : std_logic;
begin
x <= a;
end generate MY_GENERATOR;
for i in foobar'range generate
end generate;
for x in std_logic_vector generate
end generate;
for index in 0 to 9 generate
end generate;
MY_THING : if (x>1) generate
else
elsif (y<0) generate
end generate;
MY_CASE_GEN : case thing generate
when choice =>
when choice =>
end generate MY_CASE_GEN;
end architecture rtl;
-------------------------------------------------------------------------------
-- Syntax testing some architecture end clause variations.
-------------------------------------------------------------------------------
architecture testing of my_entity is
begin
end architecture testing;
architecture testing of my_entity is
begin
end testing;
architecture testing of my_entity is
begin
end architecture;
architecture testing of my_entity is
begin
end;
-------------------------------------------------------------------------------
-- PACKAGE, PROCEDURE, AND FUNCTION TESTS
-------------------------------------------------------------------------------
package my_package is
-------------------------------------------------------------------------------
-- Type and constant declarations
-------------------------------------------------------------------------------
-- Fairly simple enumerated type.
type MY_STATES is (IDLE, STATE1, STATE2, STATE3);
-- Enumerated type with entries on different lines
type MY_STATES is
(
IDLE,
S1,
S2,
S3
);
-- Complex type with record
type T_MY_TYPE is record
name : type;
name : type;
name : type(3 downto 0);
name : other_type;
really_long_name : yat;
a, b, c : std_logic;
end record;
type T_MY_ARRAY_TYPE is array (3 downto 0) of integer;
type word is array (0 to 31) of bit;
type state_counts is array (idle to error) of natural;
type state_counts is array (controller_state range idle to error) of natural;
type coeff_array is array (coeff_ram_address'reverse_range) of real;
type my_range is range 0 to 31;
type bit_index is range 0 to number_of_bits-1;
type resistance is range 0 to 1e9 units
ohm;
kohm = 1000 ohm;
Mohm = 1000 kohm;
end units resistance;
-- Simple constant
constant C_CLOCK_SPEED : real := 3.75e-9; -- seconds
-- Complex constant
constant C_MY_BFM_INIT : T_MY_TYPE :=
(
clk => 'z',
addr => (others => '0'),
addr_data => (others => '0'),
oe_n => 'z',
gta_n => 'z'
);
-------------------------------------------------------------------------------
-- Procedure Declarations
-------------------------------------------------------------------------------
-- K&R Style
procedure another_procedure (
signal name : inout type;
name : in type2;
variable data_out : out std_logic_vector(3 downto 0);
debug : in boolean := FALSE
);
-- Allman Style. It looks a little like the GNU style because parens are
-- indented, however it's only because these are being treated as the code
-- block. Might be able to mix it up a little with the continuation
-- clauses.
procedure my_init_procedure
(
signal name : inout type
);
-- Lisp Style
procedure another_procedure (
signal name : inout type;
name : in type2;
variable data_out : out std_logic_vector(3 downto 0);
debug : in boolean := FALSE);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- One line style
function reverse_bus (bus_in : in std_logic_vector) return std_logic_vector;
-- K&R Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : in integer
) return boolean;
-- Allman Style
function equal_with_tol
(
a : in unsigned;
b : in unsigned;
tol : in integer
) return boolean;
-- Lisp Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : in integer) return boolean;
end package my_package;
package body my_package is
-------------------------------------------------------------------------------
-- Procedure Body Tests
-------------------------------------------------------------------------------
-- K&R Style
procedure elbc_gpcm_init (
signal elbc_if_rec : inout T_ELBC_GPCM_IF
) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-- Allman Style
procedure elbc_gpcm_init
(
signal elbc_if_rec : inout T_ELBC_GPCM_IF
) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-- Lisp Style
procedure elbc_gpcm_init (
signal elbc_if_rec : inout T_ELBC_GPCM_IF) is
begin
elbc_if_rec.addr <= (others => 'Z');
elbc_if_rec.addr_data <= (others => 'Z');
elbc_if_rec.cs_n <= (others => '1');
elbc_if_rec.oe_n <= '1';
elbc_if_rec.we_n <= (others => '1');
elbc_if_rec.ale <= '0';
elbc_if_rec.ctrl <= '1';
elbc_if_rec.gta_n <= 'Z';
end procedure elbc_gpcm_init;
-------------------------------------------------------------------------------
-- Function Body Tests
-------------------------------------------------------------------------------
-- Single line style.
function reverse_bus (bus_in : in slv) return slv is
variable bus_out : std_logic_vector(bus_in'range);
alias bus_in_rev : std_logic_vector(bus_in'reverse_range) is bus_in;
begin
for i in bus_in_rev'range loop
bus_out(i) := bus_in_rev(i);
end loop;
return bus_out;
end; -- function reverse_bus
-- K&$ Style
function equal_with_tol (
a : in unsigned;
b : in unsigned;
tol : integer
) return boolean is
variable low_limit : unsigned(b'range);
variable high_limit : unsigned(b'range);
variable foo, bar : std_logic;
begin
low_limit := b - tol;
high_limit := b + tol;
if (a >= low_limit and a <= high_limit) then
return TRUE;
else
return FALSE;
end if;
end function equal_with_tol;
-- Allman Style
function equal_with_tol
(
a : in unsigned;
b : in unsigned;
tol : integer
) return boolean is
variable low_limit : unsigned(b'range);
variable high_limit : unsigned(b'range);
begin
low_limit := b - tol;
high_limit := b + tol;
if (a >= low_limit and a <= high_limit) then
return TRUE;
else
return FALSE;
end if;
end function equal_with_tol;
-- Lisp Style
function onehot_vector (
size : in integer;
index : in integer) return slv is
variable vector_out : std_logic_vector(size-1 downto 0);
begin
for i in vector_out'range loop
if (i = index) then
vector_out(i) := '1';
else
vector_out(i) := '0';
end if;
end loop;
return vector_out;
end function onehot_vector;
-- Padding function
function make_miso_word (d_in : std_logic_vector)
return std_logic_vector is
variable d_out : std_logic_vector(C_SPI_DATA_LEN-1 downto 0);
begin
end function make_miso_word;
end package body my_package;
| mit | ef3874c9a419cc9b1a4697043965066e | 0.46198 | 3.70732 | false | false | false | false |
Skif-off/geany | tests/ctags/vhdl-type.vhd | 7 | 9,685 | --
-- Taken from rtl/misclib/types_misc.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
--! @brief Declaration of components visible on SoC top level.
package types_misc is
--! @defgroup irq_id_group AXI4 interrupt generic IDs.
--! @ingroup axi4_config_generic_group
--! @details Unique indentificator of the interrupt pin also used
--! as an index in the interrupts bus.
--! @{
--! Zero interrupt index must be unused.
constant CFG_IRQ_UNUSED : integer := 0;
--! UART_A interrupt pin.
constant CFG_IRQ_UART1 : integer := 1;
--! Ethernet MAC interrupt pin.
constant CFG_IRQ_ETHMAC : integer := 2;
--! GP Timers interrupt pin
constant CFG_IRQ_GPTIMERS : integer := 3;
--! GNSS Engine IRQ pin that generates 1 msec pulses.
constant CFG_IRQ_GNSSENGINE : integer := 4;
--! Total number of used interrupts in a system
constant CFG_IRQ_TOTAL : integer := 5;
--! @}
--! @brief SOC global reset former.
--! @details This module produces output reset signal in a case if
--! button 'Reset' was pushed or PLL isn't a 'lock' state.
--! param[in] inSysReset Button generated signal
--! param[in] inSysClk Clock from the PLL. Bus clock.
--! param[out] outReset Output reset signal with active 'High' (1 = reset).
component reset_global
port (
inSysReset : in std_ulogic;
inSysClk : in std_ulogic;
outReset : out std_ulogic );
end component;
--! Boot ROM with AXI4 interface declaration.
component axi4_rom is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
sim_hexfile : string
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! Internal RAM with AXI4 interface declaration.
component axi4_sram is
generic (
memtech : integer := inferred;
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
abits : integer := 17;
init_file : string := "" -- only for 'inferred'
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type
);
end component;
--! AXI4 to SPI brdige for external Flash IC Micron M25AA1024
type spi_in_type is record
SDI : std_logic;
end record;
type spi_out_type is record
SDO : std_logic;
SCK : std_logic;
nCS : std_logic;
nWP : std_logic;
nHOLD : std_logic;
RESET : std_logic;
end record;
constant spi_out_none : spi_out_type := (
'0', '0', '1', '1', '1', '0'
);
component axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end component;
--! @brief AXI4 GPIO controller
component axi4_gpio is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
width : integer := 12
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
i_gpio : in std_logic_vector(width-1 downto 0);
o_gpio : out std_logic_vector(width-1 downto 0);
o_gpio_dir : out std_logic_vector(width-1 downto 0)
);
end component;
type uart_in_type is record
rd : std_ulogic;
cts : std_ulogic;
end record;
type uart_out_type is record
td : std_ulogic;
rts : std_ulogic;
end record;
--! UART with the AXI4 interface declaration.
component axi4_uart is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic);
end component;
--! Test Access Point via UART (debug access)
component uart_tap is
port (
nrst : in std_logic;
clk : in std_logic;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end component;
-- JTAG TAP
component tap_jtag is
generic (
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3);
port (
nrst : in std_logic;
clk : in std_logic;
i_tck : in std_logic; -- in: Test Clock
i_ntrst : in std_logic; -- in:
i_tms : in std_logic; -- in: Test Mode State
i_tdi : in std_logic; -- in: Test Data Input
o_tdo : out std_logic; -- out: Test Data Output
o_jtag_vref : out std_logic;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end component;
--! @brief Interrupt controller with the AXI4 interface declaration.
--! @details To rise interrupt on certain CPU HostIO interface is used.
component axi4_irqctrl is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq_meip : out std_logic
);
end component;
--! @brief General Purpose Timers with the AXI interface.
--! @details This module provides high precision counter and
--! generic number of GP timers.
component axi4_gptimers is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_pwm : out std_logic_vector(tmr_total-1 downto 0);
o_irq : out std_logic
);
end component;
--! @brief Plug-n-Play support module with AXI4 interface declaration.
--! @details Each device in a system hase to implements sideband signal
--! structure 'nasti_slave_config_type' that allows FW to
--! detect Hardware configuration in a run-time.
--! @todo Implements PnP signals for all Masters devices.
component axi4_pnp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
tech : integer := 0;
hw_id : std_logic_vector(31 downto 0) := X"20170101"
);
port (
sys_clk : in std_logic;
adc_clk : in std_logic;
nrst : in std_logic;
mstcfg : in bus0_xmst_cfg_vector;
slvcfg : in bus0_xslv_cfg_vector;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
-- OTP Timing control
i_otp_busy : in std_logic;
o_otp_cfg_rsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wadrsetup : out std_logic_vector(3 downto 0);
o_otp_cfg_wactive : out std_logic_vector(31 downto 0);
o_otp_cfg_whold : out std_logic_vector(3 downto 0)
);
end component;
component axi4_otp is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#ffffe#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_otp_we : out std_ulogic;
o_otp_re : out std_ulogic;
o_otp_addr : out std_logic_vector(11 downto 0);
o_otp_wdata : out std_logic_vector(15 downto 0);
i_otp_rdata : in std_logic_vector(15 downto 0);
i_cfg_rsetup : in std_logic_vector(3 downto 0);
i_cfg_wadrsetup : in std_logic_vector(3 downto 0);
i_cfg_wactive : in std_logic_vector(31 downto 0);
i_cfg_whold : in std_logic_vector(3 downto 0);
o_busy : out std_logic
);
end component;
end; -- package declaration
| gpl-2.0 | bc1040ec180f3396080a395e5bf716f5 | 0.62571 | 3.245643 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/xilinx_sp601/clock/top.vhdl | 1 | 1,470 | --
-- Clocks on sp601
--
-- There are four clock sources on sp601 board:
-- * On-board differential 200 MHz oscillator.
-- * On-board single-ended Oscillator Socket populated with 27 MHz.
-- * User differential through SMA.
-- * Differential through SMA.
-- This example is about on-board clock sources. They are used to blink user leds.
-- The clock of 200 MHz is used to blink LEDs 0 and 1.
-- The clock of 27 MHz is used to blink LEDs 2 and 3.
-- CPU_RESET push-button is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
signal clk200, led27, led200 : std_logic;
begin
IBUFGDS_inst: IBUFGDS
port map (I => clk_p_i, IB => clk_n_i, O => clk200);
blink27_inst: Blink
generic map (FREQUENCY => 27e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led27);
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => rst_i, blink_o => led200);
leds_o <= led27 & led27 & led200 & led200;
end architecture RTL;
| bsd-3-clause | 83c77dbe6b5edbf70368f28e251fe485 | 0.659864 | 3.181818 | false | false | false | false |
99yen/vhdl-snake | lfsr16.vhd | 1 | 570 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity LFSR16 is
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(15 downto 0)
);
end LFSR16;
architecture RTL of LFSR16 is
signal FEEDBACK : std_logic;
signal SR : std_logic_vector(15 downto 0);
begin
RAND <= SR;
FEEDBACK <= SR(15) xor SR(13) xor SR(12) xor SR(10);
process (CLK, RST) begin
if (RST = '0') then
SR <= "0000000000000001";
elsif(CLK'event and CLK = '1') then
SR <= SR(14 downto 0) & FEEDBACK;
end if;
end process;
end RTL;
| gpl-2.0 | f1ec17895c3c5649af283e20e0726e20 | 0.659649 | 2.688679 | false | false | false | false |
wifidar/wifidar_fpga | src/dac_section/amplitude_adjust.vhd | 1 | 2,563 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity amplitude_adjust is
port(
sine_in: in std_logic_vector(11 downto 0);
sine_out: out std_logic_vector(11 downto 0);
adjust: in std_logic_vector(5 downto 0);
clk: in std_logic
);
end amplitude_adjust;
architecture Behavioral of amplitude_adjust is
signal one_shift: unsigned(10 downto 0);
signal two_shift: unsigned(9 downto 0);
signal three_shift: unsigned(8 downto 0);
signal four_shift: unsigned(7 downto 0);
signal five_shift: unsigned(6 downto 0);
signal six_shift: unsigned(6 downto 0);
signal one_shift_temp: unsigned(11 downto 0);
signal two_shift_temp: unsigned(11 downto 0);
signal three_shift_temp: unsigned(11 downto 0);
signal four_shift_temp: unsigned(11 downto 0);
signal five_shift_temp: unsigned(11 downto 0);
signal six_shift_temp: unsigned(11 downto 0);
begin
-- Placed into a process to improve timing
process(clk)
begin
if(rising_edge(clk)) then
if adjust(5) = '1' then
one_shift_temp <= (unsigned(sine_in) srl 1);
else
one_shift_temp <= (others => '0');
end if;
if adjust(4) = '1' then
two_shift_temp <= unsigned(sine_in) srl 2;
else
two_shift_temp <= (others => '0');
end if;
if adjust(3) = '1' then
three_shift_temp <= unsigned(sine_in) srl 3;
else
three_shift_temp <= (others => '0');
end if;
if adjust(2) = '1' then
four_shift_temp <= unsigned(sine_in) srl 4;
else
four_shift_temp <= (others => '0');
end if;
if adjust(1) = '1' then
five_shift_temp <= unsigned(sine_in) srl 5;
else
five_shift_temp <= (others => '0');
end if;
if adjust(0) = '1' then
six_shift_temp <= unsigned(sine_in) srl 5;
else
six_shift_temp <= (others => '0');
end if;
--
-- four_shift <= unsigned(sine_in) srl 4 if adjust(2) = '1' else (others => '0');
-- five_shift <= unsigned(sine_in) srl 5 if adjust(1) = '1' else (others => '0');
-- six_shift <= unsigned(sine_in) srl 5 if adjust(0) = '1' else (others => '0');
if(adjust = "111111") then
sine_out <= sine_in;
else
sine_out <= std_logic_vector(one_shift_temp + two_shift_temp + three_shift_temp + four_shift_temp + five_shift_temp + six_shift_temp);
end if;
end if;
end process;
-- one_shift_temp <= '0' & one_shift;
-- two_shift_temp <= "00" & two_shift;
-- three_shift_temp <= "000" & three_shift;
-- four_shift_temp <= "0000" & four_shift;
-- five_shift_temp <= "00000" & five_shift;
-- six_shift_temp <= "00000" & six_shift;
end Behavioral;
| mit | 8c86486393b2599c5c163c72bc45661c | 0.629341 | 2.801093 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/uart16750/hdl/slib_fifo.vhd | 3 | 4,928 | --
-- FIFO
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.3
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end slib_fifo;
architecture rtl of slib_fifo is
-- Signals
signal iEMPTY : std_logic; -- Internal EMPTY
signal iFULL : std_logic; -- Internal FULL
signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address
signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address
signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage
-- FIFO memory
type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0'));
begin
-- Full signal (biggest difference of read and write address)
iFULL <= '1' when (iRDAddr(SIZE_E-1 downto 0) = iWRAddr(SIZE_E-1 downto 0)) and
(iRDAddr(SIZE_E) /= iWRAddr(SIZE_E)) else '0';
-- Write/read address counter and empty signal
FF_ADDR: process (RST, CLK)
begin
if (RST = '1') then
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
iEMPTY <= '1';
elsif (CLK'event and CLK='1') then
if (WRITE = '1' and iFULL = '0') then -- Write to FIFO
iWRAddr <= iWRAddr + 1;
end if;
if (READ = '1' and iEMPTY = '0') then -- Read from FIFO
iRDAddr <= iRDAddr + 1;
end if;
if (CLEAR = '1') then -- Reset FIFO
iWRAddr <= (others => '0');
iRDAddr <= (others => '0');
end if;
if (iRDAddr = iWRAddr) then -- Empty signal (read address same as write address)
iEMPTY <= '1';
else
iEMPTY <= '0';
end if;
end if;
end process;
-- FIFO memory process
FF_MEM: process (RST, CLK)
begin
if (RST = '1') then
--iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0'));
elsif (CLK'event and CLK = '1') then
if (WRITE = '1' and iFULL = '0') then
iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D;
end if;
Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0)));
end if;
end process;
-- Usage counter
FF_USAGE: process (RST, CLK)
begin
if (RST = '1') then
iUSAGE <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iUSAGE <= (others => '0');
else
if (READ = '0' and WRITE = '1' and iFULL = '0') then
iUSAGE <= iUSAGE + 1;
end if;
if (WRITE = '0' and READ = '1' and iEMPTY = '0') then
iUSAGE <= iUSAGE - 1;
end if;
end if;
end if;
end process;
-- Output signals
EMPTY <= iEMPTY;
FULL <= iFULL;
USAGE <= std_logic_vector(iUSAGE);
end rtl;
| lgpl-2.1 | cb91edbe6cf158b450e253f292da6f38 | 0.489651 | 4.169205 | false | false | false | false |
forflo/yodl | vhdlpp/vhdl_testfiles/netlist_gen_case_nested.vhd | 1 | 781 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
process(A) is
begin
case A is
when '0' =>
case B is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
when '1' =>
case C is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
end case;
end process;
end behv;
| gpl-3.0 | eabda60c709cd1af57b3b4e5efdefd7c | 0.455826 | 3.518018 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | shared/vivado_repo/AXIF_MASTER_DPRAM/AXIF_MASTER_DPRAM_S_AXIL.vhdl | 1 | 11,585 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIF_MASTER_DPRAM_S_AXIL is
generic (
C_S_AXI_DATA_WIDTH : integer:= 32;
C_S_AXI_ADDR_WIDTH : integer:= 4
);
port (
status_i : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
control_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
length_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_addr_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_addr_o : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end AXIF_MASTER_DPRAM_S_AXIL;
architecture arch_imp of AXIF_MASTER_DPRAM_S_AXIL is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal aw_en : std_logic;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
aw_en <= '1';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
aw_en <= '1';
axi_awready <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
control_o <= (others => '0');
length_o <= (others => '0');
rd_addr_o <= (others => '0');
wr_addr_o <= (others => '0');
else
control_o <= (others => '0'); -- to have only a pulse
if (slv_reg_wren = '1') then
case axi_awaddr(ADDR_LSB+1 downto ADDR_LSB) is
when "00" =>
control_o <= S_AXI_WDATA;
when "01" =>
length_o <= S_AXI_WDATA;
when "10" =>
rd_addr_o <= S_AXI_WDATA;
when "11" =>
wr_addr_o <= S_AXI_WDATA;
when others =>
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (status_i, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
begin
-- Address decoding for reading registers
case axi_araddr(ADDR_LSB+1 downto ADDR_LSB) is
when "00" =>
reg_data_out <= status_i;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
end arch_imp;
| bsd-3-clause | 6cbcf20dea6967075b7c3cbe65a22d8b | 0.565904 | 3.646522 | false | false | false | false |
INTI-CMNB-FPGA/fpga_examples | examples/altera_10M08/clock/top.vhdl | 1 | 723 | --
-- Clock on 10M08
--
-- There is one clock source on de0nano board:
-- * On-board 50MHz clock oscillator.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_i : in std_logic;
leds_o : out std_logic_vector(4 downto 0)
);
end entity Top;
architecture RTL of Top is
signal rst, led : std_logic;
begin
rst <= '0';
blink_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk_i, rst_i => rst, blink_o => led);
leds_o <= led & not(led) & led & not(led) & led;
end architecture RTL;
| bsd-3-clause | 3da79ab30e4ea1cf2299f8f1578936a7 | 0.630705 | 3.025105 | false | false | false | false |
jocover/hackrf | firmware/cpld/sgpio_if/top.vhd | 2 | 5,614 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | fef7a4e0bb7166f9fbf122ed4ef4d052 | 0.526363 | 3.686146 | false | false | false | false |
freecores/hilbert_transformer | vhdl/analytic_filter_h_a3.vhd | 1 | 6,954 | -- Implementation of Filter H_a3(z)
-- using Complex Frequency sampling filer (FSF) as Hilbert transformer
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
package analytic_filter_h_a3_pkg is
component analytic_filter_h_a3
generic(
data_width : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end analytic_filter_h_a3_pkg;
package body analytic_filter_h_a3_pkg is
end analytic_filter_h_a3_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.fsf_comb_filter_pkg.all;
use work.fsf_pole_filter_pkg.all;
use work.fsf_pole_filter_coeff_def_pkg.all;
use work.complex_fsf_filter_c_90_pkg.all;
use work.complex_fsf_filter_inv_c_m30_m150_pkg.all;
use work.resize_tools_pkg.all;
entity analytic_filter_h_a3 is
generic(
data_width : integer := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_i_o : out std_logic_vector(data_width-1 downto 0);
data_q_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end analytic_filter_h_a3;
architecture analytic_filter_h_a3_arch of analytic_filter_h_a3 is
--signal y : std_logic_vector (data_width-1 downto 0);
--signal x : std_logic_vector (data_width-1 downto 0);
signal data_i_res : std_logic_vector (data_width-1 downto 0);
signal t1 : std_logic_vector (data_width-1 downto 0);
signal t1_res : std_logic_vector (data_width-1 downto 0);
signal t2 : std_logic_vector (data_width-1 downto 0);
signal t3 : std_logic_vector (data_width-1 downto 0);
signal t4 : std_logic_vector (data_width-1 downto 0);
signal c1_i : std_logic_vector (data_width-1 downto 0);
signal c1_q : std_logic_vector (data_width-1 downto 0);
signal c2_i : std_logic_vector (data_width-1 downto 0);
signal c2_q : std_logic_vector (data_width-1 downto 0);
signal c2_i_res : std_logic_vector (data_width-1 downto 0);
signal c2_q_res : std_logic_vector (data_width-1 downto 0);
signal c3_i : std_logic_vector (data_width-1 downto 0);
signal c3_q : std_logic_vector (data_width-1 downto 0);
signal c3_i_res : std_logic_vector (data_width-1 downto 0);
signal c3_q_res : std_logic_vector (data_width-1 downto 0);
signal c4_i : std_logic_vector (data_width-1 downto 0);
signal c4_q : std_logic_vector (data_width-1 downto 0);
signal t1_str : std_logic;
signal t2_str : std_logic;
signal t3_str : std_logic;
signal t4_str : std_logic;
signal c1_str : std_logic;
signal c2_str : std_logic;
signal c3_str : std_logic;
signal c4_str : std_logic;
begin
data_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(data_i),1)),data_width);
comb_stage1 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => data_i_res,
data_str_i => data_str_i,
data_o => t1,
data_str_o => t1_str
);
t1_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(t1),1)),data_width);
comb_stage2 : fsf_comb_filter
generic map (
data_width => data_width,
comb_delay => 4
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t1_res,
data_str_i => t1_str,
data_o => t2,
data_str_o => t2_str
);
c_0_180_filter1 : fsf_pole_filter
generic map (
data_width => data_width,
coeff => c_0_180_coeff,
no_of_coefficients => 2
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t2,
data_str_i => t2_str,
data_o => t3,
data_str_o => t3_str
);
c_0_180_filter2 : fsf_pole_filter
generic map (
data_width => data_width,
coeff => c_0_180_coeff,
no_of_coefficients => 2
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i => t3,
data_str_i => t3_str,
data_o => t4,
data_str_o => t4_str
);
complex_fsf_filter_c_90_1 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => t4,
data_q_i => (others => '0'),
data_str_i => t4_str,
data_i_o => c1_i,
data_q_o => c1_q,
data_str_o => c1_str
);
complex_fsf_filter_c_90_2 : complex_fsf_filter_c_90
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c1_i,
data_q_i => c1_q,
data_str_i => c1_str,
data_i_o => c2_i,
data_q_o => c2_q,
data_str_o => c2_str
);
c2_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c2_i),1)),data_width);
c2_q_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c2_q),1)),data_width);
complex_fsf_filter_inv_c_m30_m150_1 : complex_fsf_filter_inv_c_m30_m150
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c2_i_res,
data_q_i => c2_q_res,
data_str_i => c2_str,
data_i_o => c3_i,
data_q_o => c3_q,
data_str_o => c3_str
);
c3_i_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c3_i),2)),data_width);
c3_q_res <= resize_to_msb_round(std_logic_vector(shift_right(signed(c3_q),2)),data_width);
complex_fsf_filter_inv_c_m30_m150_2 : complex_fsf_filter_inv_c_m30_m150
generic map (
data_width => data_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
data_i_i => c3_i_res,
data_q_i => c3_q_res,
data_str_i => c3_str,
data_i_o => c4_i,
data_q_o => c4_q,
data_str_o => c4_str
);
data_i_o <= c4_i;
data_q_o <= c4_q;
data_str_o <= c4_str;
end analytic_filter_h_a3_arch;
| gpl-3.0 | 21b966ee84baaa9dddeaf05a224e9066 | 0.606701 | 2.534257 | false | false | false | false |
xcthulhu/periphondemand | src/library/wrappers/atmega_wb8_wrapper/hdl/atmega_wb8_wrapper.vhd | 1 | 2,550 | ---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 23/04/2008
-- File : atmega_wb8_wrapper.vhd
--
-- Abstract : An atmega128 to wishbone wrapper components.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity atmega_wb8_wrapper is
---------------------------------------------------------------------------
port
(
-- Atmega128 port
Address_H : in std_logic_vector( 6 downto 0);
DA : inout std_logic_vector( 7 downto 0);
ALE : in std_logic ;
RD : in std_logic ;
WR : in std_logic ;
DIR_buffer: out std_logic ;
-- Wishbone port
wbm_address : out std_logic_vector( 14 downto 0);
wbm_readdata : in std_logic_vector( 7 downto 0);
wbm_writedata: out std_logic_vector( 7 downto 0);
wbm_strobe : out std_logic ;
wbm_write : out std_logic ;
wbm_ack : in std_logic ;
wbm_cycle : out std_logic ;
-- clock 50MHz and reset
clk : in std_logic ;
reset : in std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture atmega_wb8_wrapper_1 of atmega_wb8_wrapper is
---------------------------------------------------------------------------
signal write : std_logic ;
signal strobe : std_logic ;
signal cycle : std_logic ;
signal writedata : std_logic_vector( 7 downto 0);
signal address : std_logic_vector( 14 downto 0);
begin
synchro : process(clk,reset)
begin
if reset = '1' then
strobe <= '0';
write <= '0';
cycle <= '0';
address <= (others => '0');
writedata <= (others => '0');
elsif rising_edge(clk) then
-- Address bus latching
if ALE = '1' then
address(14 downto 8) <= Address_H;
address(7 downto 0) <= DA;
else
address <= address;
end if;
writedata <= DA;
-- signals controls
strobe <= not(RD and WR);
cycle <= not(RD and WR);
write <= (not WR);
end if;
end process synchro;
wbm_write <= write;
wbm_strobe<= strobe;
wbm_cycle <= cycle;
wbm_address <= address;
wbm_writedata <= writedata when (write = '1') else (others => '0');
-- buffer direction
DIR_buffer <= '1' when write = '0' and strobe='1' else '0';
DA <= wbm_readdata when write = '0' and strobe='1' else (others => 'Z');
end architecture atmega_wb8_wrapper_1;
| lgpl-2.1 | 259cf2b25cd96891ea5b3c1ef3f1221b | 0.503922 | 3.591549 | false | false | false | false |
freecores/hilbert_transformer | vhdl/analytic_filter_tb.vhd | 1 | 65,741 | -- Testbench for Filters H_a1-4(z)
-- Uses a sine sweep as stimuli
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.analytic_filter_h_a1_pkg.all;
use work.analytic_filter_h_a2_pkg.all;
use work.analytic_filter_h_a3_pkg.all;
use work.analytic_filter_h_a4_pkg.all;
entity analytic_filter_tb is
generic(
clk_period : time := 10 ns;
input_data_width : integer := 16;
output_data_width : integer := 16;
filter_delay_in_clks : integer := 7; --delay of hilbert filter
data_width : integer := 16
);
end analytic_filter_tb;
architecture analytic_filter_tb_arch of analytic_filter_tb is
signal x : std_logic_vector(input_data_width-1 downto 0) := (others => '0'); --input
signal i,q : std_logic_vector(output_data_width-1 downto 0); --output
signal i_real,q_real : real;
signal x_real : real;
signal anal_data_i : std_logic_vector(input_data_width-1 downto 0);
signal clk : std_logic := '0';
signal rst : std_logic;
type filter_in_table is array (0 to 1034) of std_logic_vector(15 downto 0);
-- sine sweep
constant filter_in_force : filter_in_table :=
(
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F68"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F0D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D02"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A79"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78BC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"769F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7416"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7116"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6D93"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64D6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"598B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"52DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"434B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3A68"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"30CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2679"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B7F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FEC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"03D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F751"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA82"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DD8B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D098"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C3D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B781"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ABCC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0F5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"973D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8EE4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"882C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8353"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8092"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8220"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86B8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"97D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A450"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B334"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C445"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D731"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EB8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"00D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"167D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2BDA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"403C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"52ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6336"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7067"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79DF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F16"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B4F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7205"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"63F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5174"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B2D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"21F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EAFC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CFCB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B6A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FDB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"84A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8012"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8CA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9D8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B4AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D0C5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1110"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3124"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6620"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"76FA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E28"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7359"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F67"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"43A0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"220B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FD49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D863"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B68F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9AE7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"881B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"842D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9413"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AEA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D193"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F985"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"227F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4837"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6687"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7793"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"615E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3F93"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"15ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E947"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A66"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A483"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CB45"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F99D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2936"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"534A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"719F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F76"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B9C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AF3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D835"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8C4E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8010"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8940"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A6C3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D3EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"091C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D09"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"664B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D1B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CDD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6523"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"39FC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"035B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CBBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E1D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82C7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9B7C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C958"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"030C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3C71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"690F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EDA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"788B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"570B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"217E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E3E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC88"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8896"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8107"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"982E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0791"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"44AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"70AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E20"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3F3F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FF51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF3C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"906C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8006"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9319"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C4DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"489A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74CD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6387"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2A25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E3B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A59D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8327"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8789"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B1F6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F579"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3CB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"707C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"644F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2751"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DCBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9DDF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FB4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C665"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"11D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5729"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7596"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"427D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F660"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83C7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8977"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BD0F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0B04"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"54F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D62"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B06"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA0E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A1D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"807A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9488"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D62B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"29ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5AED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0E39"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BAE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8655"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"88C0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C1B6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"179A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62D5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"60C0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1349"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BC47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85C6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AC6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"237F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C0A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E59"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5081"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F944"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9DF7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EFB7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A67"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"20DC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C29A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8602"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D4E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"352D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7775"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"755D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2F64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8916"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D217"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3543"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7890"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"72BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C26F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"843C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E6E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F00"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"61D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A4F2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8033"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"14EF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C4A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7AD7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3607"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CC1A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"859C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"93B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED52"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5449"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"50D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E7B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FD3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8906"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D8FC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"45C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A53"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9396"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"875D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D710"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4658"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F9B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E908"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DEF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8CD3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E756"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55CB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F6C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"41EF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE96"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"837D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9EE4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E0B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"750F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1948"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A7D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8172"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C7A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3EB0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F80"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"510B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CAA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0C6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"713E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"08E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9987"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"881F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E571"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5B9D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2872"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AE1B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"814B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A26"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"396C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BB15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8014"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C308"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4281"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8014"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C529"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"467D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3515"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B354"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8155"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D40C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5535"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A08C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8849"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F14F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6A71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FA75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B33"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9D15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1D08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CB8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5075"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C953"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C86D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5095"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"185B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"980F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0BEE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"791F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5727"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD8B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8001"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CBEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"56B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78B1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F50"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2883"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FB5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3825"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA56"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"87E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FCD2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"75EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"592F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8047"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DA9B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6570"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E5F2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"815A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C370"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7649"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F920"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"850B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B641"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02DA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8770"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B187"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47E9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7AD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86D6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B487"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4C8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7879"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F96B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFBB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"583C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7193"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E66D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"805A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D490"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6885"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CB18"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F458"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7872"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AAFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E89"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1E51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1DEF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADA0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4CEA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E69F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8006"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E264"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7383"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4DE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC86"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9022"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"26BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"84C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C6ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6620"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5E5E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BBB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8978"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8A7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6948"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"582A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B19A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9051"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2DA6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CDD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F580"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8031"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E808"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"798A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"374F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9458"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AE34"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5814"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"666D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF3C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B2B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1F6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8002"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F579"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E12"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2138"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"87AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA8F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FB2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9AE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5952"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6140"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B2EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"957C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"40F7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"718C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8951"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2ABE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A48"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DEC7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8351"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1905"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E31"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EDC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0CED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F6DD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"803D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F9D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8029"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06F8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F6AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"807B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0D35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"197B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DE3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85E6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2B5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"766B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C9EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8ED4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"41B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6A04"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B229"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"54A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA1C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"704A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3448"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"873C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E01A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E4E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0912"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8009"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0F96"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D6E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8BDF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4244"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6557"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFAA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3584"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA13"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F357"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2FC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFC0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A999"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3515"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8484"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FBB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E22C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46A6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C6E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"982B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C98F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BFD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8128"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"29B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA1E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B4B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A57"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8001"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1CBE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7360"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B049"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B067"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73C5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"800E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"21F8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FA5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A825"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BB61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"827E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"389D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6017"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"951D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D895"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E231"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9084"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5B64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3C5B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82A4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0B25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"76D5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B863"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A9D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE23"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4BEA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A80"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85DA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0232"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B0C1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C4F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F3DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8BDB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"599D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"37BB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"973D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E00E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C54C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB12"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7814"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FD49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A0F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A05"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"32A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8007"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2E47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AB6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE54"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7671"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A4BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D1D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C7A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADC3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B18"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9454"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BBC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"11A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8598"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3140"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8028"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3CF1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23F7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5E2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"886B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0CD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BDC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"91A0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F8BB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9BB0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E834"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A50"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB63"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD34"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D22E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EC8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B2FF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CC64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F62"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B630"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C9D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F88"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B696"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B429"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D555"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D33"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A7A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DFEC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A16"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E73"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EE2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7478"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"946A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"001F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6B3F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8ACE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"157E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5D49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8350"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2D85"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"499B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8004"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46BC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2FAE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8339"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5ED9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FC9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8F2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"72B0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EB6B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A58F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C59B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C6CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A306"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F14F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"89AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"20F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E0A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4EC6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1EF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B44"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"71A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E742"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD7F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B180"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E35A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7293"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B02"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"22E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"480A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C45"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D32"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C20E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D464"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"772F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2019"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"815B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62CB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F99C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A616"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC27"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F287"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6601"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81BE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B05"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"931B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C13"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFF8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DDA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"851A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23B5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9022"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B5C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFB9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E0E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CAC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4837"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1468"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A6C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F5E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FC99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5935"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6382"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EC3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA22"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D72"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3010"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2A25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D89"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B13A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FA2E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5754"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80E2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6AF2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB11"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE14"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"718C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5063"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"004A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF76"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D0E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D27"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3703"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1C2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"98B7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2DDE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F7E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"197B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3607"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FCA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EF3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A2CF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1858"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3555"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"911C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E73"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"209A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2BB7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"97C4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"94C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"31B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"186F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A5FA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"88F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"49EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FAED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BEED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7243"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64DC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D485"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E527"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8411"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AAC2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"17A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2C5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9C79"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"895A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EEF4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CF8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8166"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7795"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADE6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1820"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A2DD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8390"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D3A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EF30"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"49C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E46"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B11"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EBBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D97E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"878B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"93C3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"43CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D64A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5955"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"883E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4C25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E51D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"912D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85B6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"614C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C747"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0762"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2AC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F7E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3A65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F3AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DCE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4D63"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9319"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DBF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF6B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2933"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02E3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D1BD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"53D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90A4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8197"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"70F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A899"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"34D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E456"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4142"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9FE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"755D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C5EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"16A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0E55"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"50D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"96D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7928"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8EE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5D5A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCA0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2524"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FB36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E481"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"39AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC0C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"68E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8899"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80B8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78B7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9429"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5992"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2987"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F19F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C016"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"553A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9949"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8148"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"791F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"908B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6240"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADE6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3FAC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D45A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"16B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EC9E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"275F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C5FF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A64C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"663C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FAD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"77E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8307"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F94"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DDE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"861D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7417"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"63F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A5F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4F48"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BC2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"37E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D448"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ECCA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0732"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0481"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A8F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB3A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2E61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8A7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3FA9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B8B1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB5A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0));
begin
analytic_filter_inst : analytic_filter_h_a4 --change this to analytic_filter_h_ax to test other filters
generic map(
-- input_data_width => input_data_width, --uncomment this for analytic_filter_h_a1
-- output_data_width => output_data_width, --uncomment this for analytic_filter_h_a1
-- filter_delay_in_clks => filter_delay_in_clks --uncomment this for analytic_filter_h_a1
data_width => data_width --uncomment this for analytic_filter_h_a3-4
)
port map(
rst_i => rst,
clk_i => clk,
data_str_i => '1',
data_i => anal_data_i,
data_i_o => i,
data_q_o => q,
data_str_o => open
);
clk <= not clk after clk_period/2;
rst <= '1', '0' after 20 ns;
--choose scaling, not all filters have the full dynamic range
anal_data_i <= x;
-- anal_data_i <= std_logic_vector(shift_right(signed(x),1));
-- anal_data_i <= std_logic_vector(shift_right(signed(x),2));
x_real <= real(to_integer(signed(x)))/ 2.0**(input_data_width-1);
i_real <= real(to_integer(signed(i)))/ 2.0**(output_data_width-1);
q_real <= real(to_integer(signed(q)))/ 2.0**(output_data_width-1);
--choose imput stimuli:
-- x <= x"7FFF", x"0000" after 40 ns; --impulse response
-- x <= x"7FFF"; --step response
filter_in_gen: process
begin
x <= filter_in_force(0);
wait for clk_period*3;
x <= filter_in_force(1);
wait for clk_period;
for n in 0 to 1034 loop
if n + 2 <= 1034 then
x <= filter_in_force(n + 2);
end if;
wait for clk_period;
end loop;
assert false report "**** test complete. ****" severity note;
end process filter_in_gen;
end analytic_filter_tb_arch; | gpl-3.0 | a3a3e883afaf1c3bec2e7f00e50e29f4 | 0.649321 | 3.252895 | false | false | false | false |
alexkernphysiker/JPET-FPGA-parser | packet_simulation/devicefilter.vhd | 1 | 1,338 | -- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity devicefilter is
port(
deviceID: in std_logic_vector(15 downto 0);
in_data: in std_logic;
clock: in std_logic;
channel_offset: out std_logic_vector(15 downto 0);
accepted: out std_logic
);
end devicefilter;
architecture Behavioral of devicefilter is
signal accept : std_logic:='0';
signal counter : integer:=0;
begin
check_device:process(in_data, clock)
begin
if rising_edge(clock) then
if in_data = '1' then
counter <= 4;
elsif accept = '1' then
accept <= '0';
elsif counter > 0 then
counter <= counter-1;
if counter = 0 then
accept <= '1';
end if;
end if;
end if;
end process check_device;
accept_device:process(accept, clock)
begin
if rising_edge(clock)then
accepted<=accept;
end if;
end process accept_device;
calculate_channel_offset:process(accept, clock)
begin
if rising_edge(clock) then
if accept='1' then
channel_offset<=deviceID;
end if;
end if;
end process calculate_channel_offset;
end Behavioral;
| gpl-3.0 | 26867ae9bfb2ea4ae897c7ccb3d90c93 | 0.650972 | 3.558511 | false | false | false | false |
wifidar/wifidar_fpga | src/dac_section/buttons_to_switches.vhd | 1 | 1,404 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity buttons_to_switches is
port(
adjust: out std_logic_vector(1 downto 0);
rotary_pulse: in std_logic;
rotary_direction: in std_logic;
buttons_in: in std_logic_vector(3 downto 0);
current_mode: out std_logic_vector(1 downto 0);
current_channel: out std_logic_vector(1 downto 0);
clk: in std_logic
);
end buttons_to_switches;
architecture behavioral of buttons_to_switches is
signal current_mode_sig: unsigned(1 downto 0);
signal current_channel_sig: unsigned(1 downto 0);
begin
rotary_handle: process(clk)
begin
if(rising_edge(clk)) then
adjust <= "00";
if(rotary_pulse = '1' and rotary_direction = '1') then
adjust <= "01";
elsif (rotary_pulse = '1') then
adjust <= "10";
end if;
end if;
end process;
button_handle: process(clk)
begin
if(rising_edge(clk)) then
if(buttons_in = "0001") then
current_mode_sig <= current_mode_sig + 1;
elsif(buttons_in = "0010") then
current_mode_sig <= current_mode_sig - 1;
elsif(buttons_in = "0100") then
current_channel_sig <= current_channel_sig + 1;
elsif(buttons_in = "1000") then
current_channel_sig <= current_channel_sig - 1;
end if;
end if;
end process;
current_channel <= std_logic_vector(current_channel_sig);
current_mode <= std_logic_vector(current_mode_sig);
end behavioral;
| mit | b31ba4c5cbf2452264613090dbdf4554 | 0.674501 | 2.962025 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/other/fifo_32.vhd | 1 | 3,917 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: fifo_32 - Behavioral
--
-- Description: A 32-entry singla-clock FIFO of unknown data width.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fifo_32 is
port (
clk : in std_logic;
full : out std_logic := '0';
write_en : in std_logic := '0';
data_in : in std_logic_vector := (others => '1');
data_out : out std_logic_vector := (others => '1');
empty : out std_logic := '0';
read_en : in std_logic := '0'
);
end fifo_32;
architecture Behavioral of fifo_32 is
signal i_full : std_logic := '0';
signal i_empty : std_logic := '1';
type mem_array is array(31 downto 0) of std_logic_vector(data_in'high downto 0);
signal memory : mem_array := (others => (others => '0'));
signal wr_ptr : unsigned(4 downto 0) := (others => '0');
signal rd_ptr : unsigned(4 downto 0) := (others => '0');
signal i_data_out : std_logic_vector(data_in'high downto 0) := (others => '0');
begin
full <= i_full;
empty <= i_empty;
data_out <= i_data_out;
flag_proc: process(wr_ptr, rd_ptr)
begin
if wr_ptr = rd_ptr then
i_empty <= '1';
else
i_empty <= '0';
end if;
if wr_ptr+1 = rd_ptr then
i_full <= '1';
else
i_full <= '0';
end if;
end process;
clk_proc: process(clk)
begin
if rising_edge(clk) then
if read_en = '1' then
if write_en = '1' then
if i_empty = '0' then
i_data_out <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr + 1;
end if;
memory(to_integer(wr_ptr)) <= data_in;
wr_ptr <= wr_ptr + 1;
elsif i_empty = '0' then
i_data_out <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr + 1;
end if;
elsif write_en = '1' then
if i_full = '0' then
memory(to_integer(wr_ptr)) <= data_in;
wr_ptr <= wr_ptr + 1;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 52cdd047291be3856d304c7c0762e8f1 | 0.521573 | 4.038144 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_tx_packet.vhd | 1 | 11,365 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 05.06.2016 22:31:14
-- Module Name: udp_tx_packet - Behavioral
--
-- Description: Construct and send out UDP packets
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_tx_packet is
generic (
our_ip : std_logic_vector(31 downto 0) := (others => '0');
our_mac : std_logic_vector(47 downto 0) := (others => '0'));
port( clk : in STD_LOGIC;
udp_tx_busy : out std_logic := '0';
udp_tx_valid : in std_logic;
udp_tx_data : in std_logic_vector(7 downto 0);
udp_tx_src_port : in std_logic_vector(15 downto 0);
udp_tx_dst_mac : in std_logic_vector(47 downto 0);
udp_tx_dst_ip : in std_logic_vector(31 downto 0);
udp_tx_dst_port : in std_logic_vector(15 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end udp_tx_packet;
architecture Behavioral of udp_tx_packet is
signal busy_countdown : unsigned(7 downto 0) := (others => '0');
-- For holding the destination and port details on the first data transfer
signal udp_tx_valid_last : STD_LOGIC := '0';
signal tx_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal tx_dst_mac : std_logic_vector(47 downto 0) := (others => '0');
signal tx_dst_ip : std_logic_vector(31 downto 0) := (others => '0');
signal tx_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal udp_tx_length : std_logic_vector(15 downto 0) := (others => '0');
signal udp_tx_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal pre_udp_valid : STD_LOGIC := '0';
signal pre_udp_data : STD_LOGIC_VECTOR (7 downto 0);
component buffer_count_and_checksum_data is
generic (min_length : natural);
Port ( clk : in STD_LOGIC;
hdr_valid_in : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_length : out std_logic_vector(15 downto 0);
data_checksum : out std_logic_vector(15 downto 0));
end component;
signal data_length : std_logic_vector(15 downto 0);
signal data_checksum : std_logic_vector(15 downto 0);
component udp_add_udp_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0);
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0);
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0);
udp_src_port : in std_logic_vector(15 downto 0);
udp_dst_port : in std_logic_vector(15 downto 0));
end component;
signal pre_ip_valid : STD_LOGIC := '0';
signal pre_ip_data : STD_LOGIC_VECTOR (7 downto 0);
signal ip_length : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal ip_data_length : std_logic_vector(15 downto 0);
component ip_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_data_length : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ip_protocol : in STD_LOGIC_VECTOR ( 7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0'));
end component;
signal pre_header_valid : STD_LOGIC := '0';
signal pre_header_data : STD_LOGIC_VECTOR (7 downto 0);
component ethernet_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ether_type : in STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
ether_dst_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0');
ether_src_mac : in STD_LOGIC_VECTOR (47 downto 0) := (others => '0'));
end component;
signal complete_valid : STD_LOGIC := '0';
signal complete_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
component transport_commit_buffer
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
packet_out_request : out std_logic := '0';
packet_out_granted : in std_logic := '0';
packet_out_valid : out std_logic := '0';
packet_out_data : out std_logic_vector(7 downto 0) := (others => '0'));
end component;
begin
process(clk)
begin
if rising_edge(clk) then
-- Capture the destination address data on the first cycle of the data packet
if udp_tx_valid = '1' then
if udp_tx_valid_last = '0' then
tx_src_port <= udp_tx_src_port;
tx_dst_mac <= udp_tx_dst_mac;
tx_dst_ip <= udp_tx_dst_ip;
tx_dst_port <= udp_tx_dst_port;
busy_countdown <= to_unsigned(8+64+12-4,8);
-- 8 = preamble
-- 64 = minimum ethernet header
-- 12 = minimum inter-packet gap
-- and -4 is a fix for latency
udp_tx_busy <= '1';
else
-- Allow for the bytes that will be added
if busy_countdown > 8+14+20+8+4+12 -3 then
-- allow for premable (8)
-- and ethernet Header(14)
-- and ip header (20)
-- and udp hereader (8)
-- and ethernet FCS (4)
-- and minimum inter-packet gap
-- and -3 is a fix for latency
busy_countdown <= busy_countdown-1;
end if;
end if;
else
-- Keep udp_tx_busy asserted to allow for
-- everything to be wrapped around the data
if busy_countdown > 0 then
busy_countdown <= busy_countdown - 1;
else
udp_tx_busy <= '0';
end if;
end if;
udp_tx_valid_last <= udp_tx_valid;
end if;
end process;
i_buffer_count_and_checksum_data: buffer_count_and_checksum_data generic map (
min_length => 64-14-20-8)
port map (
clk => clk,
hdr_valid_in => '0',
data_valid_in => udp_tx_valid,
data_in => udp_tx_data,
data_valid_out => pre_udp_valid,
data_out => pre_udp_data,
data_length => data_length,
data_checksum => data_checksum);
i_udp_add_udp_header: udp_add_udp_header port map (
clk => clk,
data_valid_in => pre_udp_valid,
data_in => pre_udp_data,
data_valid_out => pre_ip_valid,
data_out => pre_ip_data,
ip_src_ip => our_ip,
ip_dst_ip => tx_dst_ip,
data_length => data_length,
data_checksum => data_checksum,
udp_src_port => tx_src_port,
udp_dst_port => tx_dst_port);
ip_data_length <= std_logic_vector(unsigned(data_length)+8);
i_ip_add_header: ip_add_header port map (
clk => clk,
data_valid_in => pre_ip_valid,
data_in => pre_ip_data,
data_valid_out => pre_header_valid,
data_out => pre_header_data,
ip_data_length => ip_data_length,
ip_protocol => x"11",
ip_src_ip => our_ip,
ip_dst_ip => tx_dst_ip);
i_ethernet_add_header: ethernet_add_header port map (
clk => clk,
data_valid_in => pre_header_valid,
data_in => pre_header_data,
data_valid_out => complete_valid,
data_out => complete_data,
ether_type => x"0800",
ether_dst_mac => tx_dst_mac,
ether_src_mac => our_mac);
i_transport_commit_buffer: transport_commit_buffer port map (
clk => clk,
data_valid_in => complete_valid,
data_in => complete_data,
packet_out_request => packet_out_request,
packet_out_granted => packet_out_granted,
packet_out_valid => packet_out_valid,
packet_out_data => packet_out_data);
end Behavioral; | mit | 5af6a4ca4d87bba2bcfa90a19f4b8eba | 0.513242 | 3.775748 | false | false | false | false |
daniw/ecs | vhdl/sw12/mcu1/ram.vhd | 1 | 1,572 | -------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 12_May-14
-------------------------------------------------------------------------------
-- Description:
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (better to use BRAM)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram : t_ram;
signal r_addr : std_logic_vector(AWL-1 downto 0);
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.we = '1' then
ram(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
r_addr <= bus_in.addr;
-- read before write
bus_out.data <= ram(to_integer(unsigned(r_addr)));
end if;
end process;
-- write before read
--bus_out.data <= ram(to_integer(unsigned(bus_in.r_addr)));
end rtl;
| gpl-2.0 | 39e73fbfe62ba2ee2414f8af08d8d0da | 0.429389 | 4.180851 | false | false | false | false |
daniw/ecs | vhdl/sw10/calc/proc.vhd | 1 | 1,852 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:59:02 11/20/2014
-- Design Name:
-- Module Name: proc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity proc is
Port (
op1 : in STD_ULOGIC_VECTOR (3 downto 0);
op2 : in STD_ULOGIC_VECTOR (3 downto 0);
op : in STD_ULOGIC_VECTOR (2 downto 0);
led : out STD_ULOGIC_VECTOR (7 downto 0));
end proc;
architecture Behavioral of proc is
begin
opcalc: process (op1, op2, op)
begin
case op is
when "000" => -- no output
led <= "00000000";
when "001" => -- display op1
led <= "0010" & op1;
when "010" => -- display op2
--led <= "0100" & op2;
led <= op1 & op2;
when "011" => -- add
led <= std_ulogic_vector( signed( op1 ) + signed( op2 ) );
when "100" => -- sub
led <= std_ulogic_vector( signed( op1 ) - signed( op2 ) );
when "101" => -- mult
led <= std_ulogic_vector( signed( op1 ) * signed( op2 ) );
when others => -- no output
led <= "00000000";
end case;
end process;
end Behavioral;
| gpl-2.0 | 3f246397219fcce8c67c7918db059b85 | 0.515119 | 3.858333 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/uart16750/hdl/slib_fifo_cyclone2.vhd | 3 | 2,516 | --
-- FIFO (using Altera scfifo for Cyclone II)
--
-- Author: Sebastian Witt
-- Date: 07.03.2008
-- Version: 1.0
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
entity slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end slib_fifo;
architecture altera of slib_fifo is
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
usedw : OUT STD_LOGIC_VECTOR (SIZE_E-1 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC
);
END COMPONENT;
begin
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone II",
lpm_numwords => 2**SIZE_E,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => WIDTH,
lpm_widthu => SIZE_E,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
rdreq => READ,
sclr => CLEAR,
clock => CLK,
wrreq => WRITE,
data => D,
usedw => USAGE,
empty => EMPTY,
q => Q,
full => FULL
);
end altera;
| lgpl-2.1 | c726aa1b513be4b05fcbbc167433c23a | 0.495628 | 3.513966 | false | false | false | false |
99yen/vhdl-snake | game.vhd | 1 | 8,078 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity GAME is
port (
CLK : in std_logic;
RST : in std_logic;
BLANKING : in std_logic;
KEYCODE : in std_logic_vector(7 downto 0);
CODE_ENABLE : in std_logic;
MAP_X, MAP_Y : in std_logic_vector(5 downto 0);
TITLE : out std_logic;
SCORE : out std_logic_vector(7 downto 0);
VISIBLE : out std_logic
;DEBUG : out std_logic
);
end GAME;
architecture RTL of GAME is
component LFSR16
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(15 downto 0)
);
end component;
component LFSR15
port (
CLK : in std_logic;
RST : in std_logic;
RAND : out std_logic_vector(14 downto 0)
);
end component;
type POINT is
record
X : integer range -1 to 31;
Y : integer range -1 to 31;
end record;
type REGISTERFILE is array(47 downto 0) of POINT;
signal SNAKE_FILE : REGISTERFILE;
signal SNAKE_NEXT : POINT;
type DIRECTION is (UP, DOWN, RIGHT, LEFT);
type GAME_STATE_T is (IDLE, VISIBLE_WAIT, BLANK_WAIT, COUNTER_WAIT,
CHECK_BORDER, CHECK_EAT_ONESELF, SHIFT, CHECK_FOOD, CHECK_WIN,
MAKE_FOOD, SET_WAIT, GAMECLEAR, GAMEOVER);
signal GAME_STATE : GAME_STATE_T;
signal FOOD : POINT;
signal RAND : POINT;
signal COMPRD_POINT : POINT;
signal POINT_EXIST : std_logic;
signal SNAKE_DIRECTION, PREV_DIRECTION : DIRECTION;
signal KEY_PUSH, CODE_ENABLE_PRE : std_logic;
signal SNAKE_SPEED, WAIT_CNT : integer range 0 to 120;
signal SNAKE_LENGTH : integer range 0 to 48;
signal WALL : std_logic;
signal RAND_A : std_logic_vector(15 downto 0);
signal RAND_B : std_logic_vector(14 downto 0);
begin
U_LFSR16 : LFSR16 port map(CLK => CLK, RST => RST, RAND => RAND_A);
U_LFSR15 : LFSR15 port map(CLK => CLK, RST => RST, RAND => RAND_B);
SNAKE_NEXT.Y <= (SNAKE_FILE(0).Y - 1) when SNAKE_DIRECTION = UP else
(SNAKE_FILE(0).Y + 1) when SNAKE_DIRECTION = DOWN else
SNAKE_FILE(0).Y;
SNAKE_NEXT.X <= (SNAKE_FILE(0).X - 1) when SNAKE_DIRECTION = LEFT else
(SNAKE_FILE(0).X + 1) when SNAKE_DIRECTION = RIGHT else
SNAKE_FILE(0).X;
WALL <= '1' when SNAKE_NEXT.X = -1 or SNAKE_NEXT.Y = -1 or
SNAKE_NEXT.X = 26 or SNAKE_NEXT.Y = 26 else
'0';
DEBUG <= '1' when GAME_STATE = IDLE else '0';
SCORE <= CONV_std_logic_vector(SNAKE_LENGTH, 8);
-- Compare Snake Point with oneself or food
COMPRD_POINT <= SNAKE_NEXT when GAME_STATE = CHECK_EAT_ONESELF else FOOD;
process (COMPRD_POINT, SNAKE_LENGTH, SNAKE_FILE)
variable TMP : std_logic;
begin
TMP := '0';
for I in 0 to 47 loop
if (SNAKE_FILE(I) = COMPRD_POINT and I < SNAKE_LENGTH) then
TMP := '1';
end if;
end loop;
POINT_EXIST <= TMP;
end process;
-- Compare Snake point with Graphic output
process (MAP_X, MAP_Y, SNAKE_LENGTH, SNAKE_FILE, FOOD)
variable TMP : std_logic;
begin
TMP := '0';
for I in 0 to 47 loop
if (SNAKE_FILE(I).X = MAP_X and SNAKE_FILE(I).Y = MAP_Y and I < SNAKE_LENGTH) then
TMP := '1';
elsif (FOOD.X = MAP_X and FOOD.Y = MAP_Y) then
TMP := '1';
end if;
end loop;
VISIBLE <= TMP;
end process;
-- game main state machine
process(CLK, RST)
variable TMP : std_logic;
begin
if (RST = '0') then
GAME_STATE <= IDLE;
SNAKE_LENGTH <= 1;
WAIT_CNT <= 0;
FOOD.X <= 31;
FOOD.Y <= 31;
elsif (CLK'event and CLK = '1') then
case GAME_STATE is
when IDLE =>
if (KEY_PUSH = '1' and KEYCODE = X"29") then -- push space key
WAIT_CNT <= 0;
SNAKE_LENGTH <= 1;
case RAND_A(1 downto 0) is
when "00" =>
FOOD.X <= 5;
FOOD.Y <= 5;
when "01" =>
FOOD.X <= 20;
FOOD.Y <= 5;
when "10" =>
FOOD.X <= 5;
FOOD.Y <= 20;
when others =>
FOOD.X <= 20;
FOOD.Y <= 20;
end case;
GAME_STATE <= VISIBLE_WAIT;
else
GAME_STATE <= IDLE;
end if;
when VISIBLE_WAIT =>
if (BLANKING = '1') then
GAME_STATE <= BLANK_WAIT;
else
GAME_STATE <= VISIBLE_WAIT;
end if;
when BLANK_WAIT =>
if (BLANKING = '0') then
GAME_STATE <= COUNTER_WAIT;
else
GAME_STATE <= BLANK_WAIT;
end if;
when COUNTER_WAIT =>
if (WAIT_CNT = 0) then
GAME_STATE <= CHECK_BORDER;
else
WAIT_CNT <= WAIT_CNT - 1;
GAME_STATE <= VISIBLE_WAIT;
end if;
when CHECK_BORDER =>
if (WALL = '1') then
GAME_STATE <= GAMEOVER;
else
GAME_STATE <= CHECK_EAT_ONESELF;
end if;
when CHECK_EAT_ONESELF =>
if (POINT_EXIST = '1') then
GAME_STATE <= GAMEOVER;
else
GAME_STATE <= SHIFT;
end if;
when SHIFT =>
PREV_DIRECTION <= SNAKE_DIRECTION;
GAME_STATE <= CHECK_FOOD;
when CHECK_FOOD =>
if (SNAKE_FILE(0) = FOOD) then
SNAKE_LENGTH <= SNAKE_LENGTH + 1;
GAME_STATE <= CHECK_WIN;
else
GAME_STATE <= SET_WAIT;
end if;
when CHECK_WIN =>
if (SNAKE_LENGTH = 47) then
GAME_STATE <= GAMECLEAR;
else
FOOD <= RAND;
GAME_STATE <= MAKE_FOOD;
end if;
when MAKE_FOOD =>
if (POINT_EXIST = '0') then
GAME_STATE <= SET_WAIT;
else
FOOD <= RAND;
GAME_STATE <= MAKE_FOOD;
end if;
when SET_WAIT =>
case SNAKE_LENGTH is
when 0 to 3 =>
WAIT_CNT <= 14;
when 4 to 10 =>
WAIT_CNT <= 13;
when 11 to 15 =>
WAIT_CNT <= 10;
when 16 to 20 =>
WAIT_CNT <= 8;
when 21 to 25 =>
WAIT_CNT <= 6;
when 26 to 35 =>
WAIT_CNT <= 5;
when 36 to 43 =>
WAIT_CNT <= 5;
when 44 to 47 =>
WAIT_CNT <= 3;
when others =>
WAIT_CNT <= 40;
end case;
GAME_STATE <= VISIBLE_WAIT;
when GAMECLEAR =>
GAME_STATE <= IDLE;
when GAMEOVER =>
GAME_STATE <= IDLE;
end case;
end if;
end process;
-- make food
process (RAND_A, RAND_B)
variable CANADIATE : POINT;
begin
CANADIATE.X := CONV_INTEGER(RAND_A(4 downto 0));
CANADIATE.Y := CONV_INTEGER(RAND_B(4 downto 0));
if (CANADIATE.X > 25) then
CANADIATE.X := CANADIATE.X - 13;
end if;
if (CANADIATE.Y > 25) then
CANADIATE.Y := CANADIATE.Y - 13;
end if;
RAND <= CANADIATE;
end process;
-- Shift Snake Shift Register File
-- I don't know why, but State machie viewer does not work when this process is exist.
process (CLK, RST, GAME_STATE, SNAKE_FILE, SNAKE_NEXT) begin
if (RST = '0') then
SNAKE_FILE(0).X <= 13;
SNAKE_FILE(0).Y <= 13;
for I in 1 to 47 loop
SNAKE_FILE(I).X <= 0;
SNAKE_FILE(I).Y <= 0;
end loop;
elsif (CLK'event and CLK = '1') then
if (GAME_STATE = IDLE) then
SNAKE_FILE(0).X <= 13;
SNAKE_FILE(0).Y <= 13;
elsif (GAME_STATE = SHIFT) then
SNAKE_FILE(0) <= SNAKE_NEXT;
for I in 1 to 47 loop
SNAKE_FILE(I) <= SNAKE_FILE(I-1);
end loop;
end if;
end if;
end process;
-- keyboard input
process(CLK, RST) begin
if (RST = '0') then
CODE_ENABLE_PRE <= '0';
KEY_PUSH <= '0';
elsif (CLK'event and CLK = '1') then
if (CODE_ENABLE = '1' and CODE_ENABLE_PRE = '0') then
KEY_PUSH <= '1';
CODE_ENABLE_PRE <= CODE_ENABLE;
else
KEY_PUSH <= '0';
CODE_ENABLE_PRE <= CODE_ENABLE;
end if;
end if;
end process;
-- keyboard direction
process(CLK, RST) begin
if (RST = '0') then
SNAKE_DIRECTION <= UP;
elsif(CLK'event and CLK ='1') then
if (KEY_PUSH = '1') then
if (KEYCODE = X"72" and PREV_DIRECTION /= UP) then
SNAKE_DIRECTION <= DOWN;
elsif (KEYCODE = X"75" and PREV_DIRECTION /= DOWN) then
SNAKE_DIRECTION <= UP;
elsif (KEYCODE = X"74" and PREV_DIRECTION /= LEFT) then
SNAKE_DIRECTION <= RIGHT;
elsif (KEYCODE = X"6B" and PREV_DIRECTION /= RIGHT) then
SNAKE_DIRECTION <= LEFT;
end if;
end if;
end if;
end process;
end RTL;
| gpl-2.0 | f2417fa9e33556010880982d048f60d0 | 0.571057 | 2.91204 | false | false | false | false |
daniw/ecs | vhdl/sw10/calc/ctrl.vhd | 1 | 4,219 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:57:17 11/20/2014
-- Design Name:
-- Module Name: ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ctrl is
Port (
rst : in STD_ULOGIC;
clk : in STD_ULOGIC;
rot_c : in STD_ULOGIC;
btn_east : in STD_ULOGIC;
btn_west : in STD_ULOGIC;
btn_north : in STD_ULOGIC;
sw : in STD_ULOGIC_VECTOR (3 downto 0);
op1 : out STD_ULOGIC_VECTOR (3 downto 0);
op2 : out STD_ULOGIC_VECTOR (3 downto 0);
op : out STD_ULOGIC_VECTOR (2 downto 0));
end ctrl;
architecture Behavioral of ctrl is
type state is (s_start, s_op1, s_op2, s_add, s_sub, s_mult);
signal c_st : state;
signal n_st : state;
signal rot_c_prev : STD_ULOGIC;
signal op1_ff : STD_ULOGIC_VECTOR (3 downto 0);
signal op2_ff : STD_ULOGIC_VECTOR (3 downto 0);
begin
-- memorizing process
p_seq: process (rst, clk)
begin
if rst = '1' then
c_st <= s_start;
rot_c_prev <= '0';
elsif rising_edge(clk) then
c_st <= n_st;
rot_c_prev <= rot_c;
op1 <= op1_ff;
op2 <= op2_ff;
else
c_st <= c_st;
rot_c_prev <= rot_c_prev;
end if;
end process;
-- memoryless process
p_com: process (rst, rot_c, btn_east, btn_west, btn_north, sw, c_st)
begin
-- default assignments
n_st <= c_st; -- remain in current state
op1_ff <= "0000"; --
op2_ff <= "0000"; --
op <= "000"; --
-- specific assignments
case c_st is
when s_start =>
if rot_c = '1' and rot_c_prev = '0' then
n_st <= s_op1;
else
n_st <= c_st;
end if;
op1_ff <= "0000";
op2_ff <= "0000";
op <= "000";
when s_op1 =>
if rot_c = '1' and rot_c_prev = '0' then
n_st <= s_op2;
else
n_st <= c_st;
end if;
op1_ff <= sw;
op2_ff <= "0000";
op <= "001"; -- display op1
when s_op2 =>
if btn_west = '1' then
n_st <= s_add;
elsif btn_east = '1' then
n_st <= s_sub;
elsif btn_north = '1' then
n_st <= s_mult;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= sw;
op <= "010"; -- display op2
when s_add =>
if rst = '1' then
n_st <= s_start;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= op2_ff;
op <= "011"; -- add
when s_sub =>
if rst = '1' then
n_st <= s_start;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= op2_ff;
op <= "100"; -- sub
when s_mult =>
if rst = '1' then
n_st <= s_start;
else
n_st <= c_st;
end if;
op1_ff <= op1_ff;
op2_ff <= op2_ff;
op <= "101"; -- mul
when others =>
n_st <= s_start; -- undefined state -> reset to start
op1_ff <= "0000";
op2_ff <= "0000";
op <= "000";
end case;
end process;
end Behavioral;
| gpl-2.0 | cfc09c2fd9e9fa0e46a08d288e3310b8 | 0.424745 | 3.472428 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tx/tx_arbiter.vhd | 1 | 4,377 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tx_arbiter - Behavioral
--
-- Description: Control who has access to the transmit queue
-- The higher number bit in "request" have higher priority
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tx_arbiter is
generic (idle_time : std_logic_vector(5 downto 0));
Port ( clk : in STD_LOGIC;
ready : in STD_LOGIC;
ch0_request : in STD_LOGIC;
ch0_granted : out STD_LOGIC;
ch0_valid : in STD_LOGIC;
ch0_data : in STD_LOGIC_VECTOR (7 downto 0);
ch1_request : in STD_LOGIC;
ch1_granted : out STD_LOGIC;
ch1_valid : in STD_LOGIC;
ch1_data : in STD_LOGIC_VECTOR (7 downto 0);
ch2_request : in STD_LOGIC;
ch2_granted : out STD_LOGIC;
ch2_valid : in STD_LOGIC;
ch2_data : in STD_LOGIC_VECTOR (7 downto 0);
ch3_request : in STD_LOGIC;
ch3_granted : out STD_LOGIC;
ch3_valid : in STD_LOGIC;
ch3_data : in STD_LOGIC_VECTOR (7 downto 0);
merged_data_valid : out STD_LOGIC;
merged_data : out STD_LOGIC_VECTOR (7 downto 0));
end tx_arbiter;
architecture Behavioral of tx_arbiter is
signal count : unsigned(5 downto 0) := (others => '0');
signal request : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal grant : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
request(0) <= ch0_request;
ch0_granted <= grant(0) and request(0);
request(1) <= ch1_request;
ch1_granted <= grant(1) and request(1);
request(2) <= ch2_request;
ch2_granted <= grant(2) and request(2);
request(3) <= ch3_request;
ch3_granted <= grant(3) and request(3);
merged_data_valid <= ch0_valid or ch1_valid or ch2_valid or ch3_valid;
merged_data <= ch0_data or ch1_data or ch2_data or ch3_data;
process(clk)
begin
if rising_edge(clk) then
grant <= grant and request;
if count = 0 and ready = '1' then
if request(3) = '1' then
grant(3) <= '1';
count <= unsigned(idle_time);
elsif request(2) = '1' then
grant(2) <= '1';
count <= unsigned(idle_time);
elsif request(1) = '1' then
grant(1) <= '1';
count <= unsigned(idle_time);
elsif request(0) = '1' then
grant(0) <= '1';
count <= unsigned(idle_time);
end if;
elsif (grant and request) /= "00000000" then
count <= unsigned(idle_time)-2;
else
count <= count-1;
end if;
end if;
end process;
end Behavioral; | mit | 4ac60199afde3e1894e77f1ce941e2b3 | 0.562943 | 3.806087 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tx/tx_rgmii.vhd | 1 | 9,926 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field<[email protected]>
--
-- Module Name: rgmii_tx - Behavioral
--
-- Description: Low level interface to a RGMII Ethernet PHY
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity tx_rgmii is
Port ( clk : in STD_LOGIC;
clk90 : in STD_LOGIC;
phy_ready : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
data_valid : in STD_LOGIC;
data_enable : in STD_LOGIC := '1';
data_error : in STD_LOGIC;
eth_txck : out STD_LOGIC := '0';
eth_txctl : out STD_LOGIC := '0';
eth_txd : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0'));
end tx_rgmii;
architecture Behavioral of tx_rgmii is
signal enable_count : unsigned(6 downto 0) := (others => '0');
signal enable_frequency : unsigned(6 downto 0) := (others => '1');
signal times_3 : unsigned(8 downto 0) := (others => '0');
signal first_quarter : unsigned(6 downto 0) := (others => '0');
signal second_quarter : unsigned(6 downto 0) := (others => '0');
signal third_quarter : unsigned(6 downto 0) := (others => '0');
signal dout1 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal doutctl1 : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal doutclk1 : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal dout0 : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal doutctl0 : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal doutclk0 : STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
signal hold_data : STD_LOGIC_VECTOR (7 downto 0);
signal hold_valid : STD_LOGIC;
signal hold_error : STD_LOGIC;
signal ok_to_send : STD_LOGIC := '0';
signal tx_ready : STD_LOGIC;
signal tx_ready_meta : STD_LOGIC;
-- ATTRIBUTE IOB : STRING ;
-- ATTRIBUTE IOB OF dout : signal IS "TRUE";
-- ATTRIBUTE IOB OF doutctl : signal IS "TRUE";
begin
times_3 <= ("0" & enable_frequency & "0") + ("00" & enable_frequency);
-------------------------------------------------
-- Map the data and control signals so that they
-- can be sent via the DDR registers
-------------------------------------------------
process(clk90)
begin
if rising_edge(clk90) then
doutclk0 <= doutclk1;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
-- one cycle delay to improve timing
dout0 <= dout1;
doutctl0 <= doutctl1;
first_quarter <= "00" & enable_frequency(enable_frequency'high downto 2);
second_quarter <= "0" & enable_frequency(enable_frequency'high downto 1);
third_quarter <= times_3(times_3'high downto 2);
if data_enable = '1' then
enable_frequency <= enable_count+1;
enable_count <= (others => '0');
elsif enable_count /= "1111111" then
enable_count <= enable_count + 1;
end if;
if data_enable = '1' then
hold_data <= data;
hold_valid <= data_valid;
hold_error <= data_error;
if enable_frequency = 1 then
-- Double data rate transfer at full frequency
dout1(3 downto 0) <= data(3 downto 0);
dout1(7 downto 4) <= data(7 downto 4);
doutctl1(0) <= ok_to_send and data_valid;
doutctl1(1) <= ok_to_send and (data_valid XOR data_error);
doutclk1(0) <= '1';
doutclk1(1) <= '0';
else
-- Send the low nibble
dout1(3 downto 0) <= data(3 downto 0);
dout1(7 downto 4) <= data(3 downto 0);
doutctl1(0) <= ok_to_send and data_valid;
doutctl1(1) <= ok_to_send and data_valid;
doutclk1(0) <= '1';
doutclk1(1) <= '1';
end if;
elsif enable_count = first_quarter-1 then
if enable_frequency(1) = '1' then
-- Send the high nibble and valid signal for the last half of this cycle
doutctl1(1) <= ok_to_send and (hold_valid XOR hold_error);
doutclk1(1) <= '0';
else
doutctl1(0) <= ok_to_send and (hold_valid XOR hold_error);
doutctl1(1) <= ok_to_send and (hold_valid XOR hold_error);
doutclk1(0) <= '0';
doutclk1(1) <= '0';
end if;
elsif enable_count = first_quarter then
doutctl1(0) <= ok_to_send and (hold_valid XOR hold_error);
doutctl1(1) <= ok_to_send and (hold_valid XOR hold_error);
doutclk1(0) <= '0';
doutclk1(1) <= '0';
elsif enable_count = second_quarter-1 then
dout1(3 downto 0) <= hold_data(7 downto 4);
dout1(7 downto 4) <= hold_data(7 downto 4);
-- Send the high nibble and valid signal for the last half of this cycle
doutclk1(0) <= '1';
doutclk1(1) <= '1';
doutctl1(0) <= ok_to_send and hold_valid;
doutctl1(1) <= ok_to_send and hold_valid;
elsif enable_count = third_quarter-1 then
if enable_frequency(1) = '1' then
doutctl1(1) <= ok_to_send and (hold_valid XOR hold_error);
doutclk1(1) <= '0';
else
doutctl1(0) <= ok_to_send and (hold_valid XOR hold_error);
doutctl1(1) <= ok_to_send and (hold_valid XOR hold_error);
doutclk1(0) <= '0';
doutclk1(1) <= '0';
end if;
elsif enable_count = third_quarter then
doutclk1(0) <= '0';
doutclk1(1) <= '0';
doutctl1(0) <= ok_to_send and (hold_valid XOR hold_error);
doutctl1(1) <= ok_to_send and (hold_valid XOR hold_error);
end if;
end if;
end process;
----------------------------------------------------
-- DDR output registers
----------------------------------------------------
tx_d0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC")
port map (Q => eth_txd(0), C => clk, CE => '1', R => '0', S => '0', D1 => dout0(0), D2 => dout0(4));
tx_d1 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC")
port map (Q => eth_txd(1), C => clk, CE => '1', R => '0', S => '0', D1 => dout0(1), D2 => dout0(5));
tx_d2 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC")
port map (Q => eth_txd(2), C => clk, CE => '1', R => '0', S => '0', D1 => dout0(2), D2 => dout0(6));
tx_d3 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC")
port map (Q => eth_txd(3), C => clk, CE => '1', R => '0', S => '0', D1 => dout0(3), D2 => dout0(7));
tx_ctl : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC")
port map (Q => eth_txctl, C => clk, CE => '1', R => '0', S => '0', D1 => doutctl0(0), D2 => doutctl0(1));
tx_c : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE", INIT => '0', SRTYPE => "SYNC")
port map (Q => eth_txck, C => clk90, CE => '1', R => '0', S => '0', D1 => doutclk0(0), D2 => doutclk0(1));
monitor_reset_state: process(clk)
begin
if rising_edge(clk) then
tx_ready <= tx_ready_meta;
tx_ready_meta <= phy_ready;
if tx_ready = '1' and data_valid = '0' and data_enable = '1' then
ok_to_send <= '1';
end if;
end if;
end process;
end Behavioral;
| mit | 9d931b26778861ee4c53132a2d02bb34 | 0.488515 | 3.887975 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/sim/sim_tb_top.vhd | 1 | 33,513 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:22 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C1_HW_TESTING : string := "FALSE";
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_MEMCLK_PERIOD : integer := 6000;
constant C1_RST_ACT_LOW : integer := 0;
constant C1_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C1_CLK_PERIOD_NS : real := 6000.0 / 1000.0;
constant C1_TCYC_SYS : real := C1_CLK_PERIOD_NS/2.0;
constant C1_TCYC_SYS_DIV2 : time := C1_TCYC_SYS * 1 ns;
constant C1_NUM_DQ_PINS : integer := 16;
constant C1_MEM_ADDR_WIDTH : integer := 13;
constant C1_MEM_BANKADDR_WIDTH : integer := 2;
constant C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C1_P0_MASK_SIZE : integer := 4;
constant C1_P0_DATA_PORT_SIZE : integer := 32;
constant C1_P1_MASK_SIZE : integer := 4;
constant C1_P1_DATA_PORT_SIZE : integer := 32;
constant C1_MEM_BURST_LEN : integer := 4;
constant C1_MEM_NUM_COL_BITS : integer := 9;
constant C1_SIMULATION : string := "TRUE";
constant C1_CALIB_SOFT_IP : string := "TRUE";
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000300", x"03000000");
constant C1_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p1_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000004ff", x"04ffffff");
constant C1_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffff800", x"f8000000");
constant C1_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000300", x"03000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component mig_39_2 is
generic
(
C1_P0_MASK_SIZE : integer;
C1_P0_DATA_PORT_SIZE : integer;
C1_P1_MASK_SIZE : integer;
C1_P1_DATA_PORT_SIZE : integer;
C1_MEMCLK_PERIOD : integer;
C1_RST_ACT_LOW : integer;
C1_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C1_CALIB_SOFT_IP : string;
C1_SIMULATION : string;
C1_MEM_ADDR_ORDER : string;
C1_NUM_DQ_PINS : integer;
C1_MEM_ADDR_WIDTH : integer;
C1_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
c1_sys_clk : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_ck_n : out std_logic; c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c1_p1_cmd_clk : in std_logic;
c1_p1_cmd_en : in std_logic;
c1_p1_cmd_instr : in std_logic_vector(2 downto 0);
c1_p1_cmd_bl : in std_logic_vector(5 downto 0);
c1_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p1_cmd_empty : out std_logic;
c1_p1_cmd_full : out std_logic;
c1_p1_wr_clk : in std_logic;
c1_p1_wr_en : in std_logic;
c1_p1_wr_mask : in std_logic_vector(C1_P1_MASK_SIZE - 1 downto 0);
c1_p1_wr_data : in std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_wr_full : out std_logic;
c1_p1_wr_empty : out std_logic;
c1_p1_wr_count : out std_logic_vector(6 downto 0);
c1_p1_wr_underrun : out std_logic;
c1_p1_wr_error : out std_logic;
c1_p1_rd_clk : in std_logic;
c1_p1_rd_en : in std_logic;
c1_p1_rd_data : out std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
c1_p1_rd_full : out std_logic;
c1_p1_rd_empty : out std_logic;
c1_p1_rd_count : out std_logic_vector(6 downto 0);
c1_p1_rd_overflow : out std_logic;
c1_p1_rd_error : out std_logic
);
end component;
component lpddr_model_c1 is
port (
Clk : in std_logic;
Clk_n : in std_logic;
Cke : in std_logic;
Cs_n : in std_logic;
Ras_n : in std_logic;
Cas_n : in std_logic;
We_n : in std_logic;
Dm : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
Ba : in std_logic_vector((C1_MEM_BANKADDR_WIDTH - 1) downto 0);
Addr : in std_logic_vector((C1_MEM_ADDR_WIDTH - 1) downto 0);
Dq : inout std_logic_vector((C1_NUM_DQ_PINS - 1) downto 0);
Dqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0)
);
end component;
component memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c1_sys_clk : std_logic := '0';
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
-- System Reset
signal c1_sys_rst : std_logic := '0';
signal c1_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal mcb1_dram_a : std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
signal mcb1_dram_ba : std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb1_dram_ck : std_logic;
signal mcb1_dram_ck_n : std_logic;
signal mcb1_dram_dq : std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
signal mcb1_dram_dqs : std_logic;
signal mcb1_dram_dm : std_logic;
signal mcb1_dram_ras_n : std_logic;
signal mcb1_dram_cas_n : std_logic;
signal mcb1_dram_we_n : std_logic;
signal mcb1_dram_cke : std_logic;
signal mcb1_dram_udqs : std_logic;
signal mcb1_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_udm :std_logic; -- for X16 parts
signal mcb1_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_cmp_error : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb1_command : std_logic_vector(2 downto 0);
signal mcb1_enable1 : std_logic;
signal mcb1_enable2 : std_logic;
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_p1_cmd_en : std_logic;
signal c1_p1_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p1_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p1_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p1_cmd_empty : std_logic;
signal c1_p1_cmd_full : std_logic;
signal c1_p1_wr_en : std_logic;
signal c1_p1_wr_mask : std_logic_vector(C1_P1_MASK_SIZE - 1 downto 0);
signal c1_p1_wr_data : std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
signal c1_p1_wr_full : std_logic;
signal c1_p1_wr_empty : std_logic;
signal c1_p1_wr_count : std_logic_vector(6 downto 0);
signal c1_p1_wr_underrun : std_logic;
signal c1_p1_wr_error : std_logic;
signal c1_p1_rd_en : std_logic;
signal c1_p1_rd_data : std_logic_vector(C1_P1_DATA_PORT_SIZE - 1 downto 0);
signal c1_p1_rd_full : std_logic;
signal c1_p1_rd_empty : std_logic;
signal c1_p1_rd_count : std_logic_vector(6 downto 0);
signal c1_p1_rd_overflow : std_logic;
signal c1_p1_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
signal rzq1 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c1_sys_clk <= not c1_sys_clk;
wait for (C1_TCYC_SYS_DIV2);
end process;
c1_sys_clk_p <= c1_sys_clk;
c1_sys_clk_n <= not c1_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c1_sys_rst <= '0';
wait for 200 ns;
c1_sys_rst <= '1';
wait;
end process;
c1_sys_rst_i <= c1_sys_rst when (C1_RST_ACT_LOW = 1) else (not c1_sys_rst);
error <= c1_error;
calib_done <= c1_calib_done;
rzq_pulldown1 : PULLDOWN port map(O => rzq1);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : mig_39_2 generic map
(
C1_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C1_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C1_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C1_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C1_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C1_RST_ACT_LOW => C1_RST_ACT_LOW,
C1_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C1_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C1_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C1_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C1_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C1_SIMULATION => C1_SIMULATION,
C1_CALIB_SOFT_IP => C1_CALIB_SOFT_IP
)
port map (
c1_sys_clk => c1_sys_clk,
c1_sys_rst_i => c1_sys_rst_i,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_udqs => mcb1_dram_udqs, -- for X16 parts
mcb1_dram_udm => mcb1_dram_udm, -- for X16 parts
mcb1_dram_dm => mcb1_dram_dm,
c1_clk0 => c1_clk0,
c1_rst0 => c1_rst0,
c1_calib_done => c1_calib_done,
mcb1_rzq => rzq1,
c1_p0_cmd_clk => (c1_clk0),
c1_p0_cmd_en => c1_p0_cmd_en,
c1_p0_cmd_instr => c1_p0_cmd_instr,
c1_p0_cmd_bl => c1_p0_cmd_bl,
c1_p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
c1_p0_cmd_empty => c1_p0_cmd_empty,
c1_p0_cmd_full => c1_p0_cmd_full,
c1_p0_wr_clk => (c1_clk0),
c1_p0_wr_en => c1_p0_wr_en,
c1_p0_wr_mask => c1_p0_wr_mask,
c1_p0_wr_data => c1_p0_wr_data,
c1_p0_wr_full => c1_p0_wr_full,
c1_p0_wr_empty => c1_p0_wr_empty,
c1_p0_wr_count => c1_p0_wr_count,
c1_p0_wr_underrun => c1_p0_wr_underrun,
c1_p0_wr_error => c1_p0_wr_error,
c1_p0_rd_clk => (c1_clk0),
c1_p0_rd_en => c1_p0_rd_en,
c1_p0_rd_data => c1_p0_rd_data,
c1_p0_rd_full => c1_p0_rd_full,
c1_p0_rd_empty => c1_p0_rd_empty,
c1_p0_rd_count => c1_p0_rd_count,
c1_p0_rd_overflow => c1_p0_rd_overflow,
c1_p0_rd_error => c1_p0_rd_error,
c1_p1_cmd_clk => (c1_clk0),
c1_p1_cmd_en => c1_p1_cmd_en,
c1_p1_cmd_instr => c1_p1_cmd_instr,
c1_p1_cmd_bl => c1_p1_cmd_bl,
c1_p1_cmd_byte_addr => c1_p1_cmd_byte_addr,
c1_p1_cmd_empty => c1_p1_cmd_empty,
c1_p1_cmd_full => c1_p1_cmd_full,
c1_p1_wr_clk => (c1_clk0),
c1_p1_wr_en => c1_p1_wr_en,
c1_p1_wr_mask => c1_p1_wr_mask,
c1_p1_wr_data => c1_p1_wr_data,
c1_p1_wr_full => c1_p1_wr_full,
c1_p1_wr_empty => c1_p1_wr_empty,
c1_p1_wr_count => c1_p1_wr_count,
c1_p1_wr_underrun => c1_p1_wr_underrun,
c1_p1_wr_error => c1_p1_wr_error,
c1_p1_rd_clk => (c1_clk0),
c1_p1_rd_en => c1_p1_rd_en,
c1_p1_rd_data => c1_p1_rd_data,
c1_p1_rd_full => c1_p1_rd_full,
c1_p1_rd_empty => c1_p1_rd_empty,
c1_p1_rd_count => c1_p1_rd_count,
c1_p1_rd_overflow => c1_p1_rd_overflow,
c1_p1_rd_error => c1_p1_rd_error
);
-- user interface
memc1_tb_top_inst : memc1_tb_top generic map
(
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS,
C_p1_BEGIN_ADDRESS => C1_p1_BEGIN_ADDRESS,
C_p1_DATA_MODE => C1_p1_DATA_MODE,
C_p1_END_ADDRESS => C1_p1_END_ADDRESS,
C_p1_PRBS_EADDR_MASK_POS => C1_p1_PRBS_EADDR_MASK_POS,
C_p1_PRBS_SADDR_MASK_POS => C1_p1_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c1_clk0,
rst0 => c1_rst0,
calib_done => c1_calib_done,
cmp_error => c1_cmp_error,
error => c1_error,
error_status => c1_error_status,
vio_modify_enable => c1_vio_modify_enable,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count,
p1_mcb_cmd_en_o => c1_p1_cmd_en,
p1_mcb_cmd_instr_o => c1_p1_cmd_instr,
p1_mcb_cmd_bl_o => c1_p1_cmd_bl,
p1_mcb_cmd_addr_o => c1_p1_cmd_byte_addr,
p1_mcb_cmd_full_i => c1_p1_cmd_full,
p1_mcb_wr_en_o => c1_p1_wr_en,
p1_mcb_wr_mask_o => c1_p1_wr_mask,
p1_mcb_wr_data_o => c1_p1_wr_data,
p1_mcb_wr_full_i => c1_p1_wr_full,
p1_mcb_wr_fifo_counts => c1_p1_wr_count,
p1_mcb_rd_en_o => c1_p1_rd_en,
p1_mcb_rd_data_i => c1_p1_rd_data,
p1_mcb_rd_empty_i => c1_p1_rd_empty,
p1_mcb_rd_fifo_counts => c1_p1_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb1_command <= (mcb1_dram_ras_n & mcb1_dram_cas_n & mcb1_dram_we_n);
process(mcb1_dram_ck)
begin
if (rising_edge(mcb1_dram_ck)) then
if (c1_sys_rst = '0') then
mcb1_enable1 <= '0';
mcb1_enable2 <= '0';
elsif (mcb1_command = "100") then
mcb1_enable2 <= '0';
elsif (mcb1_command = "101") then
mcb1_enable2 <= '1';
else
mcb1_enable2 <= mcb1_enable2;
end if;
mcb1_enable1 <= mcb1_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb1_dram_dqs_vector(1 downto 0) <= (mcb1_dram_udqs & mcb1_dram_dqs)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb1_dram_dqs <= mcb1_dram_dqs_vector(0)
when ( mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs <= mcb1_dram_dqs_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_dm_vector <= (mcb1_dram_udm & mcb1_dram_dm);
u_mem_c1 : lpddr_model_c1 port map(
Clk => mcb1_dram_ck,
Clk_n => mcb1_dram_ck_n,
Cke => mcb1_dram_cke,
Cs_n => '0',
Ras_n => mcb1_dram_ras_n,
Cas_n => mcb1_dram_cas_n,
We_n => mcb1_dram_we_n,
Dm => mcb1_dram_dm_vector ,
Ba => mcb1_dram_ba,
Addr => mcb1_dram_a,
Dq => mcb1_dram_dq,
Dqs => mcb1_dram_dqs_vector
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| cc0-1.0 | f820c4f76255f7406b646edf7210db34 | 0.449557 | 3.336287 | false | false | false | false |
qu1x/fsio | src/lib/fsio_top.vhd | 1 | 6,221 | -- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library fsio;
use fsio.fsio.all;
entity fsio_top is
port (
DDR_addr : inout std_logic_vector(14 downto 0);
DDR_ba : inout std_logic_vector(2 downto 0);
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector(3 downto 0);
DDR_dq : inout std_logic_vector(31 downto 0);
DDR_dqs_n : inout std_logic_vector(3 downto 0);
DDR_dqs_p : inout std_logic_vector(3 downto 0);
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_mio : inout std_logic_vector(53 downto 0);
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic
);
end fsio_top;
architecture behavioral of fsio_top is
component ps is
port (
DDR_cas_n : inout std_logic;
DDR_cke : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_we_n : inout std_logic;
DDR_ba : inout std_logic_vector(2 downto 0);
DDR_addr : inout std_logic_vector(14 downto 0);
DDR_dm : inout std_logic_vector(3 downto 0);
DDR_dq : inout std_logic_vector(31 downto 0);
DDR_dqs_n : inout std_logic_vector(3 downto 0);
DDR_dqs_p : inout std_logic_vector(3 downto 0);
FIXED_IO_mio : inout std_logic_vector(53 downto 0);
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
clk180 : out std_logic;
hsi0 : in std_logic_vector(0 to 0);
hso0 : out std_logic_vector(0 to 0);
fsi1 : in std_logic_vector(31 downto 0);
fso1 : out std_logic_vector(31 downto 0);
fsi2 : in std_logic_vector(31 downto 0);
fso2 : out std_logic_vector(31 downto 0);
fsi3 : in std_logic_vector(31 downto 0);
fso3 : out std_logic_vector(31 downto 0);
fsi4 : in std_logic_vector(31 downto 0);
fso4 : out std_logic_vector(31 downto 0);
hsi5 : in std_logic_vector(0 to 0);
hso5 : out std_logic_vector(0 to 0);
fsi6 : in std_logic_vector(31 downto 0);
fso6 : out std_logic_vector(31 downto 0);
fsi7 : in std_logic_vector(31 downto 0);
fso7 : out std_logic_vector(31 downto 0);
fsi8 : in std_logic_vector(31 downto 0);
fso8 : out std_logic_vector(31 downto 0);
fsi9 : in std_logic_vector(31 downto 0);
fso9 : out std_logic_vector(31 downto 0)
);
end component ps;
signal clk180: std_logic;
signal req0, ack0: std_logic;
signal hsi0, hso0: std_logic;
signal fsi0, fso0, dat0: std_logic_vector(127 downto 0);
signal req1, ack1: std_logic;
signal hsi1, hso1: std_logic;
signal fsi1, fso1, dat1: std_logic_vector(127 downto 0);
signal data: std_logic_vector(127 downto 0);
signal full: std_logic;
begin
ps0: component ps
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
clk180 => clk180,
hsi0(0) => hso0,
hso0(0) => hsi0,
fsi1(31 downto 0) => fso0(31 downto 0),
fso1(31 downto 0) => fsi0(31 downto 0),
fsi2(31 downto 0) => fso0(63 downto 32),
fso2(31 downto 0) => fsi0(63 downto 32),
fsi3(31 downto 0) => fso0(95 downto 64),
fso3(31 downto 0) => fsi0(95 downto 64),
fsi4(31 downto 0) => fso0(127 downto 96),
fso4(31 downto 0) => fsi0(127 downto 96),
hsi5(0) => hso1,
hso5(0) => hsi1,
fsi6(31 downto 0) => fso1(31 downto 0),
fso6(31 downto 0) => fsi1(31 downto 0),
fsi7(31 downto 0) => fso1(63 downto 32),
fso7(31 downto 0) => fsi1(63 downto 32),
fsi8(31 downto 0) => fso1(95 downto 64),
fso8(31 downto 0) => fsi1(95 downto 64),
fsi9(31 downto 0) => fso1(127 downto 96),
fso9(31 downto 0) => fsi1(127 downto 96)
);
fsio0: fsio_put
generic map (
cap => 128,
len => 128
)
port map (
clk => clk180,
hsi => hsi0,
hso => hso0,
fsi => fsi0,
fso => fso0,
dat => dat0,
req => req0,
ack => ack0
);
fsio1: fsio_get
generic map (
cap => 128,
len => 128
)
port map (
clk => clk180,
hsi => hsi1,
hso => hso1,
fsi => fsi1,
fso => fso1,
dat => dat1,
req => req1,
ack => ack1
);
ctl: process(clk180)
begin
if rising_edge(clk180) then
if req0 then
if full and not ack0 then
dat0 <= data;
full <= '0';
ack0 <= '1';
end if;
else
ack0 <= '0';
end if;
ack1 <= '0';
if req1 then
if not full then
data <= dat1;
full <= '1';
ack1 <= '1';
end if;
end if;
end if;
end process ctl;
end behavioral;
| agpl-3.0 | 92cd1dc72d75190501301ade292e06e7 | 0.640251 | 2.60948 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/tcp/tcp_add_header.vhd | 1 | 10,927 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_add_header - Behavioral
--
-- Description: Add the TCP header to a data stream
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_add_header is
Port ( clk : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
ip_src_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
ip_dst_ip : in STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
tcp_src_port : in std_logic_vector(15 downto 0);
tcp_dst_port : in std_logic_vector(15 downto 0);
tcp_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
tcp_window : in std_logic_vector(15 downto 0) := (others => '0');
tcp_flag_urg : in std_logic := '0';
tcp_flag_ack : in std_logic := '0';
tcp_flag_psh : in std_logic := '0';
tcp_flag_rst : in std_logic := '0';
tcp_flag_syn : in std_logic := '0';
tcp_flag_fin : in std_logic := '0';
tcp_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
data_length : in std_logic_vector(15 downto 0);
data_checksum : in std_logic_vector(15 downto 0));
end tcp_add_header;
architecture Behavioral of tcp_add_header is
type a_data_delay is array(0 to 20) of std_logic_vector(8 downto 0);
signal data_delay : a_data_delay := (others => (others => '0'));
----------------------------------------------------------------
-- Note: Set the initial state to pass the data striaght through
----------------------------------------------------------------
signal count : unsigned(4 downto 0) := (others => '1');
signal data_valid_in_last : std_logic := '0';
signal tcp_length : std_logic_vector(15 downto 0);
signal tcp_checksum_u1a : unsigned(19 downto 0);
signal tcp_checksum_u1b : unsigned(19 downto 0);
signal tcp_checksum_u2 : unsigned(16 downto 0);
signal tcp_checksum_u3 : unsigned(15 downto 0);
signal tcp_checksum : std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- TCP checksum is calculated based on a pseudo header that
-- includes the source and destination IP addresses
--------------------------------------------------------------------
signal pseudohdr_00 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_01 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_02 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_03 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_04 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_05 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_06 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_07 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_08 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_09 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_10 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_11 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_12 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_13 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_14 : std_logic_vector(15 downto 0) := (others => '0');
signal pseudohdr_15 : std_logic_vector(15 downto 0) := (others => '0');
begin
tcp_length <= std_logic_vector(unsigned(data_length)+20);
pseudohdr_00 <= ip_src_ip( 7 downto 0) & ip_src_ip(15 downto 8);
pseudohdr_01 <= ip_src_ip(23 downto 16) & ip_src_ip(31 downto 24);
pseudohdr_02 <= ip_dst_ip( 7 downto 0) & ip_dst_ip(15 downto 8);
pseudohdr_03 <= ip_dst_ip(23 downto 16) & ip_dst_ip(31 downto 24);
pseudohdr_04 <= x"0006"; -- TCP Protocol
pseudohdr_05 <= tcp_length;
pseudohdr_06 <= tcp_src_port;
pseudohdr_07 <= tcp_dst_port;
pseudohdr_08 <= tcp_seq_num(31 downto 16);
pseudohdr_09 <= tcp_seq_num(15 downto 0);
pseudohdr_10 <= tcp_ack_num(31 downto 16);
pseudohdr_11 <= tcp_ack_num(15 downto 0);
pseudohdr_12 <= "01010000" & "00"
& tcp_flag_urg & tcp_flag_ack
& tcp_flag_psh & tcp_flag_rst
& tcp_flag_syn & tcp_flag_fin;
pseudohdr_13 <= tcp_window;
pseudohdr_14 <= tcp_checksum;
pseudohdr_15 <= tcp_urgent_ptr;
process(clk)
begin
if rising_edge(clk) then
case count is
when "00000" => data_out <= pseudohdr_06(15 downto 8); data_valid_out <= '1';
when "00001" => data_out <= pseudohdr_06( 7 downto 0); data_valid_out <= '1';
when "00010" => data_out <= pseudohdr_07(15 downto 8); data_valid_out <= '1';
when "00011" => data_out <= pseudohdr_07( 7 downto 0); data_valid_out <= '1';
when "00100" => data_out <= pseudohdr_08(15 downto 8); data_valid_out <= '1';
when "00101" => data_out <= pseudohdr_08( 7 downto 0); data_valid_out <= '1';
when "00110" => data_out <= pseudohdr_09(15 downto 8); data_valid_out <= '1';
when "00111" => data_out <= pseudohdr_09( 7 downto 0); data_valid_out <= '1';
when "01000" => data_out <= pseudohdr_10(15 downto 8); data_valid_out <= '1';
when "01001" => data_out <= pseudohdr_10( 7 downto 0); data_valid_out <= '1';
when "01010" => data_out <= pseudohdr_11(15 downto 8); data_valid_out <= '1';
when "01011" => data_out <= pseudohdr_11( 7 downto 0); data_valid_out <= '1';
when "01100" => data_out <= pseudohdr_12(15 downto 8); data_valid_out <= '1';
when "01101" => data_out <= pseudohdr_12( 7 downto 0); data_valid_out <= '1';
when "01110" => data_out <= pseudohdr_13(15 downto 8); data_valid_out <= '1';
when "01111" => data_out <= pseudohdr_13( 7 downto 0); data_valid_out <= '1';
when "10000" => data_out <= pseudohdr_14(15 downto 8); data_valid_out <= '1';
when "10001" => data_out <= pseudohdr_14( 7 downto 0); data_valid_out <= '1';
when "10010" => data_out <= pseudohdr_15(15 downto 8); data_valid_out <= '1';
when "10011" => data_out <= pseudohdr_15( 7 downto 0); data_valid_out <= '1';
when others => data_out <= data_delay(0)(7 downto 0); data_valid_out <= data_delay(0)(8);
end case;
data_delay(0 to data_delay'high-1) <= data_delay(1 to data_delay'high);
if data_valid_in = '1' then
data_delay(data_delay'high) <= '1' & data_in;
if data_valid_in_last = '0' then
count <= (others => '0');
elsif count /= "11111" then
count <= count + 1;
end if;
else
data_delay(data_delay'high) <= (others => '0');
if count /= "11111" then
count <= count + 1;
end if;
end if;
data_valid_in_last <= data_valid_in;
-- Pipelined checksum calculation
tcp_checksum_u1a <= to_unsigned(0,20) + unsigned(pseudohdr_00) + unsigned(pseudohdr_01)
+ unsigned(pseudohdr_02) + unsigned(pseudohdr_03)
+ unsigned(pseudohdr_04) + unsigned(pseudohdr_05)
+ unsigned(pseudohdr_06) + unsigned(pseudohdr_07);
tcp_checksum_u1b <= to_unsigned(0,20) + unsigned(pseudohdr_08) + unsigned(pseudohdr_09)
+ unsigned(pseudohdr_10) + unsigned(pseudohdr_11)
+ unsigned(pseudohdr_12) + unsigned(pseudohdr_13)
+ x"0000" + unsigned(pseudohdr_15)
+ unsigned(data_checksum);
tcp_checksum_u2 <= to_unsigned(0,17) + tcp_checksum_u1a(15 downto 0) + tcp_checksum_u1a(19 downto 16)
+ tcp_checksum_u1b(15 downto 0) + tcp_checksum_u1b(19 downto 16);
tcp_checksum_u3 <= tcp_checksum_u2(15 downto 0) + tcp_checksum_u2(16 downto 16);
tcp_checksum <= not std_logic_vector(tcp_checksum_u3);
end if;
end process;
end Behavioral; | mit | 4a1c283580e59cb15af553a4e7d34cf9 | 0.516061 | 3.891382 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/arp/arp_request.vhd | 1 | 7,048 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: rx_arp_request - Behavioral
--
-- Description: Receive ARP packets and decode them
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rx_arp is
Port ( clk : in STD_LOGIC;
packet_data : in STD_LOGIC_VECTOR (7 downto 0);
packet_data_valid : in STD_LOGIC;
arp_de : out STD_LOGIC := '0';
arp_op_request : out STD_LOGIC := '0';
arp_sender_hw : out STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
arp_sender_ip : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
arp_target_hw : out STD_LOGIC_VECTOR(47 downto 0) := (others => '0');
arp_target_ip : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0'));
end rx_arp;
architecture Behavioral of rx_arp is
signal ethertype_data : std_logic_vector(15 downto 0) := (others => '0');
signal data : std_logic_vector(8*28-1 downto 0) := (others => '0');
signal hwtype : std_logic_vector(15 downto 0) := (others => '0');
signal ptype : std_logic_vector(15 downto 0) := (others => '0');
signal hlen : std_logic_vector(7 downto 0) := (others => '0');
signal plen : std_logic_vector(7 downto 0) := (others => '0');
signal op : std_logic_vector(15 downto 0) := (others => '0');
signal sender_hw : std_logic_vector(47 downto 0) := (others => '0');
signal sender_ip : std_logic_vector(31 downto 0) := (others => '0');
signal target_hw : std_logic_vector(47 downto 0) := (others => '0');
signal target_ip : std_logic_vector(31 downto 0) := (others => '0');
signal ethertype_valid : std_logic := '0';
signal hwtype_valid : std_logic := '0';
signal ptype_valid : std_logic := '0';
signal len_valid : std_logic := '0';
signal op_valid : std_logic := '0';
signal op_request : std_logic := '0';
signal packet_valid_delay : std_logic := '0';
signal valid_count : unsigned(5 downto 0) := (others => '0');
begin
---------------------------------------------
-- Breaking out fields for easy reference
-------------------------------------------
hwtype <= data( 7+8*0+8 downto 0+8*0+8) & data(15+8*0+8 downto 8+8*0+8);
ptype <= data( 7+8*2+8 downto 0+8*2+8) & data(15+8*2+8 downto 8+8*2+8);
hlen <= data( 7+8*4+8 downto 0+8*4+8);
plen <= data(15+8*4+8 downto 8+8*4+8);
op <= data( 7+8*6+8 downto 0+8*6+8) & data(15+8*6+8 downto 8+8*6+8);
process(clk)
begin
if rising_edge(clk) then
arp_de <= '0';
arp_op_request <= op_request;
arp_sender_hw <= sender_hw;
arp_sender_ip <= sender_ip;
arp_target_hw <= target_hw;
arp_target_ip <= target_ip;
if ethertype_valid = '1' and hwtype_valid = '1' and ptype_valid = '1' and
len_valid = '1' and op_valid = '1' and valid_count = 41 then
arp_de <= '1';
end if;
sender_hw <= data(15+8*12+8 downto 0+8*8+8);
sender_ip <= data(15+8*16+8 downto 0+8*14+8);
target_hw <= data(15+8*22+8 downto 0+8*18+8);
target_ip <= packet_data & data(15+8*26 downto 0+8*24+8);
ethertype_valid <= '0';
hwtype_valid <= '0';
ptype_valid <= '0';
op_valid <= '0';
op_request <= '0';
len_valid <= '0';
---------------------------------
-- Validate the ethernet protocol
---------------------------------
if ethertype_data = x"0806" then
ethertype_valid <= '1';
end if;
----------------------------
-- Validate operation code
----------------------------
if hwtype = x"0001" then
hwtype_valid <= '1';
end if;
if ptype = x"0800" then
ptype_valid <= '1';
end if;
----------------------------
-- Validate operation code
----------------------------
if op = x"0001" then
op_valid <= '1';
op_request <= '1';
end if;
if op = x"0002" then
op_valid <= '1';
op_request <= '0';
end if;
if hlen = x"06" and plen = x"04" then
len_valid <= '1';
end if;
-------------------------------------------
-- Move the data through the shift register
-------------------------------------------
ethertype_data <= ethertype_data(7 downto 0) & data(15 downto 8);
data <= packet_data & data(data'high downto 8);
if packet_valid_delay = '1' then
if valid_count /= 63 then -- Clamp at max value
valid_count <= valid_count+1;
end if;
else
valid_count <= (others => '0');
end if;
packet_valid_delay <= packet_data_valid;
end if;
end process;
end Behavioral;
| mit | cdf18b5cd0f0b1f2cdc6d4e9a6b50da5 | 0.472616 | 3.975183 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/rtl/mcb_soft_calibration.vhd | 9 | 92,176 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for MCB Soft
-- Calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
-- correctly)
-- 1.2: 2/12/09: Many other changes.
-- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
-- STATE
-- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
-- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
-- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
-- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
-- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
-- RST_DELAY.
-- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
-- 16 clocks. Added PNSKEW option.
-- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
-- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
-- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
-- with 8bit TARGET_DQS_DELAY which
-- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
-- Changed DQS_COUNT* to DQS_DELAY*.
-- Changed MCB_SYSRST port back to wire (from reg).
-- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
-- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
-- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
-- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
-- 3.4: 03/04/10: Recoded the RST_Reg logic.
-- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
-- 3.6 03/10/10: Improvements to Reset logic.
-- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
-- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.
-- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
-- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that
-- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value.
-- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT
-- are set to 8 for LPDDR,DDR and DDR2 interface .
-- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing
-- Premable detection until the second deassertion of MCB_SYSRST.
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic ;
MCB_UIDQLOWERINC : out std_logic ;
MCB_UIDQUPPERDEC : out std_logic ;
MCB_UIDQUPPERINC : out std_logic ;
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end entity mcb_soft_calibration;
architecture trans of mcb_soft_calibration is
constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
constant START : std_logic_vector(5 downto 0) := "000000";
constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
constant SKEW : std_logic_vector(5 downto 0) := "001100";
constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010";
constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011";
constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100";
constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101";
constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110";
constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111";
constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000";
constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001";
constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010";
constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011";
constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100";
constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101";
constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110";
constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111";
constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000";
constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001";
constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010";
constant WAIT7 : std_logic_vector(5 downto 0) := "100011";
constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100";
constant WAIT8 : std_logic_vector(5 downto 0) := "100101";
constant RST_DELAY : std_logic_vector(5 downto 0) := "100110";
constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111";
constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000";
constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001";
constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010";
constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011";
constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100";
constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101";
constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110";
constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111";
constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000";
constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001";
constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010";
constant WAIT9 : std_logic_vector(5 downto 0) := "110011";
constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100";
constant WAIT10 : std_logic_vector(5 downto 0) := "110101";
constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110";
constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111";
constant INCREMENT : std_logic_vector(5 downto 0) := "111000";
constant DECREMENT : std_logic_vector(5 downto 0) := "111001";
constant DONE : std_logic_vector(5 downto 0) := "111010";
--constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011";
constant RZQ : std_logic_vector(1 downto 0) := "00";
constant ZIO : std_logic_vector(1 downto 0) := "01";
constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
constant WRITE_MODE : std_logic := '0';
constant READ_MODE : std_logic := '1';
-- IOI Registers
constant NoOp : std_logic_vector(7 downto 0) := "00000000";
constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-- IOB Registers
constant PDrive : std_logic_vector(7 downto 0) := "10000000";
constant PTerm : std_logic_vector(7 downto 0) := "10000001";
constant NDrive : std_logic_vector(7 downto 0) := "10000010";
constant NTerm : std_logic_vector(7 downto 0) := "10000011";
constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
constant InputControl : std_logic_vector(7 downto 0) := "10000111";
constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-- No multi/divide is required when a 55 ohm resister is used on RZQ
-- localparam MULT = 1;
-- localparam DIV = 1;
-- use 7/4 scaling factor when the 100 ohm RZQ is used
constant MULT : integer := 7;
constant DIV : integer := 4;
constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
constant PNSKEWDQS : std_logic := '1';
constant MULT_S : integer := 9;
constant DIV_S : integer := 8;
constant MULT_W : integer := 7;
constant DIV_W : integer := 8;
constant DQS_NUMERATOR : integer := 3;
constant DQS_DENOMINATOR : integer := 8;
constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
-- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
-- 3 for three eighths
constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
constant IN_TERM_PASS : std_logic := '0';
constant DYN_CAL_PASS : std_logic := '1';
function TZQINIT_MAXCNT_W return std_logic_vector is
variable temp : std_logic_vector(9 downto 0) := (others=>'0');
begin
if (C_MEM_TYPE = "DDR3") then
temp := C_MEM_TZQINIT_MAXCNT + RST_CNT;
else
temp := 8 + RST_CNT;
end if;
return temp(9 downto 0);
end function;
constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W;
component iodrp_mcb_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end component;
component iodrp_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end component;
signal P_Term : std_logic_vector(5 downto 0) := "000000";
signal N_Term : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_s : std_logic_vector(5 downto 0) := "000000";
signal N_Term_s : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_w : std_logic_vector(5 downto 0) := "000000";
signal N_Term_w : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
signal STATE : std_logic_vector(5 downto 0);
signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
signal Active_IODRP : std_logic_vector(1 downto 0);
signal IODRPCTRLR_R_WB : std_logic := '0';
signal IODRPCTRLR_CMD_VALID : std_logic := '0';
signal IODRPCTRLR_USE_BKST : std_logic := '0';
signal MCB_CMD_VALID : std_logic := '0';
signal MCB_USE_BKST : std_logic := '0';
signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
signal IODRP_SDO : std_logic;
signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
signal counter_en : std_logic := '0'; -- counter enable for "count"
signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
-- state machine will wait for this to be high
signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
-- the Max Value changes by more than the threshold
signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
signal IODRPCTRLR_RDY_BUSY_N : std_logic;
signal IODRP_CS : std_logic;
signal MCB_READ_DATA : std_logic_vector(7 downto 0);
signal RST_reg : std_logic;
signal Block_Reset : std_logic;
signal MCB_UODATAVALID_U : std_logic;
signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
signal rst_tmp : std_logic;
signal LastPass_DynCal : std_logic;
signal First_In_Term_Done : std_logic;
signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
-- parameter = "CALIBRATION"
signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
-- one-time or dynamic parameters are 1
signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
-- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
signal Quarter_Max_Value : std_logic_vector(7 downto 0);
signal Half_Max_Value : std_logic_vector(7 downto 0);
signal PLL_LOCK_R1 : std_logic;
signal PLL_LOCK_R2 : std_logic;
signal MCB_RDY_BUSY_N : std_logic;
signal SELFREFRESH_REQ_R1 : std_logic;
signal SELFREFRESH_REQ_R2 : std_logic;
signal SELFREFRESH_REQ_R3 : std_logic;
signal SELFREFRESH_MCB_MODE_R1 : std_logic;
signal SELFREFRESH_MCB_MODE_R2 : std_logic;
signal SELFREFRESH_MCB_MODE_R3 : std_logic;
signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
signal START_DYN_CAL_STATE_R1 : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-- Declare intermediate signals for referenced outputs
signal IODRP_ADD_xilinx0 : std_logic;
signal IODRP_SDI_xilinx1 : std_logic;
signal MCB_UIADD_xilinx2 : std_logic;
signal MCB_UISDI_xilinx11 : std_logic;
signal MCB_UICS_xilinx6 : std_logic;
signal MCB_UIBROADCAST_xilinx4 : std_logic;
signal MCB_UIADDR_int : std_logic_vector(4 downto 0);
signal MCB_UIDONECAL_xilinx7 : std_logic;
signal MCB_UIREAD_xilinx10 : std_logic;
signal SELFREFRESH_MODE_xilinx11 : std_logic;
signal Max_Value_int : std_logic_vector(7 downto 0);
signal Rst_condition1 : std_logic;
--signal Rst_condition2 : std_logic;
signal non_violating_rst : std_logic;
signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
signal WaitTimer : std_logic_vector(7 downto 0);
signal WarmEnough : std_logic;
signal WaitCountEnable : std_logic;
signal State_Start_DynCal_R1 : std_logic;
signal State_Start_DynCal : std_logic;
signal pre_sysrst_minpulse_width_ok : std_logic;
signal pre_sysrst_cnt : std_logic_vector(3 downto 0);
-- This function multiplies by a constant MULT and then divides by the DIV constant
function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
variable Result : integer := 0;
variable temp : std_logic_vector(14 downto 0) := "000000000000000";
begin
for count in 0 to (MULT-1) loop
temp := temp + ("0000000" & Input);
end loop;
Result := (to_integer(unsigned(temp))) / (DIV);
temp := std_logic_vector(to_unsigned(Result,15));
return temp(7 downto 0);
end function Mult_Divide;
attribute syn_preserve : boolean;
attribute syn_preserve of P_Term : signal is TRUE;
attribute syn_preserve of N_Term : signal is TRUE;
attribute syn_preserve of P_Term_s : signal is TRUE;
attribute syn_preserve of N_Term_s : signal is TRUE;
attribute syn_preserve of P_Term_w : signal is TRUE;
attribute syn_preserve of N_Term_w : signal is TRUE;
attribute syn_preserve of P_Term_Prev : signal is TRUE;
attribute syn_preserve of N_Term_Prev : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
attribute syn_preserve of Max_Value_Previous : signal is TRUE;
attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
attribute iob : string;
attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
begin
-- move the default assignment here to make FORMALITY happy.
START_BROADCAST <= '1';
MCB_RECAL <= '0';
MCB_UIDQLOWERDEC <= '0';
MCB_UIADDR <= MCB_UIADDR_int;
MCB_UIDQLOWERINC <= '0';
MCB_UIDQUPPERDEC <= '0';
MCB_UIDQUPPERINC <= '0';
Max_Value <= Max_Value_int;
-- Drive referenced outputs
IODRP_ADD <= IODRP_ADD_xilinx0;
IODRP_SDI <= IODRP_SDI_xilinx1;
MCB_UIADD <= MCB_UIADD_xilinx2;
MCB_UISDI <= MCB_UISDI_xilinx11;
MCB_UICS <= MCB_UICS_xilinx6;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
MCB_UIREAD <= MCB_UIREAD_xilinx10;
SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
-- skip dynamic input termination if either the one-time or dynamic parameters are 1
SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
-- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
else
DONE_SOFTANDHARD_CAL <= '0';
end if;
end if;
end process;
iodrp_controller_inst : iodrp_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => IODRPCTRLR_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => IODRPCTRLR_CMD_VALID,
rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
use_broadcast => '0',
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => IODRP_CS,
DRP_SDI => IODRP_SDI_xilinx1,
DRP_ADD => IODRP_ADD_xilinx0,
DRP_SDO => IODRP_SDO,
DRP_BKST => open
);
iodrp_mcb_controller_inst : iodrp_mcb_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => MCB_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => MCB_CMD_VALID,
rdy_busy_n => MCB_RDY_BUSY_N,
use_broadcast => MCB_USE_BKST,
drp_ioi_addr => MCB_UIADDR_int,
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => MCB_UICS_xilinx6,
DRP_SDI => MCB_UISDI_xilinx11,
DRP_ADD => MCB_UIADD_xilinx2,
DRP_BKST => MCB_UIBROADCAST_xilinx4,
DRP_SDO => MCB_UOSDO,
MCB_UIREAD => MCB_UIREAD_xilinx10
);
process (UI_CLK, RST) begin
if (RST = '1') then
if (C_SIMULATION = "TRUE") then
WAIT_200us_COUNTER <= X"7FF0";
else
WAIT_200us_COUNTER <= (others => '0');
end if;
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '1') then
WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
else
WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
end if;
end if;
end process;
-- init_sequence_skip: if (C_SIMULATION = "TRUE") generate
-- WAIT_200us_COUNTER <= X"FFFF";
-- process
-- begin
-- report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
-- wait;
-- end process;
-- end generate;
gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
process (UI_CLK, RST) begin
if (RST = '1') then
CKE_Train <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
CKE_Train <= '0';
elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
CKE_Train <= '1';
else
CKE_Train <= '0';
end if;
end if;
end process;
end generate ;
gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
CKE_Train <= '0';
end if;
end process;
end generate ;
--********************************************
-- PLL_LOCK and RST signals
--********************************************
--MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
process (UI_CLK, RST) begin
if (RST = '1') then
--Block_Reset <= '0';
--RstCounter <= (others => '0');
--elsif (UI_CLK'event and UI_CLK = '1') then
-- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
if (Pre_SYSRST = '1') then
RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
else
if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
end if;
end if;
end if;
--end if;
end process;
-- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
non_violating_rst <= RST and Rst_condition1;
MCB_SYSRST <= Pre_SYSRST;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter >= TZQINIT_MAXCNT) then
Rst_condition1 <= '1';
else
Rst_condition1 <= '0';
end if;
end if;
end process;
-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process.
-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
-- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which
-- will cause MCB to reset and reinitialize the memory afterwards.
-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at
-- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
-- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration
-- state machine will not reset during SUSPEND.
-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to
-- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST.
-- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT
-- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
--process (UI_CLK) begin
-- if (UI_CLK'event and UI_CLK = '1') then
--
-- if (RstCounter < RST_CNT) then
-- Rst_condition2 <= '1';
-- else
-- Rst_condition2 <= '0';
-- end if;
-- end if;
--end process;
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '1';
else
--RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;
--*************************************************************
-- Stretching the pre_sysrst to satisfy the minimum pulse width
--*************************************************************
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (STATE = START_DYN_CAL_PRE) then
pre_sysrst_cnt <= pre_sysrst_cnt + '1';
else
pre_sysrst_cnt <= (others=>'0');
end if;
end if;
end process;
pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3);
--********************************************
-- SUSPEND Logic
--********************************************
process (UI_CLK,RST)
begin
if (RST = '1') then
SELFREFRESH_MCB_MODE_R1 <= '0';
SELFREFRESH_MCB_MODE_R2 <= '0';
SELFREFRESH_MCB_MODE_R3 <= '0';
SELFREFRESH_REQ_R1 <= '0';
SELFREFRESH_REQ_R2 <= '0';
SELFREFRESH_REQ_R3 <= '0';
PLL_LOCK_R1 <= '0';
PLL_LOCK_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
-- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-- SELFREFRESH_REQ is clocked by user's application clock
SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
PLL_LOCK_R1 <= PLL_LOCK;
PLL_LOCK_R2 <= PLL_LOCK_R1;
end if;
end process;
-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
-- This is to make sure MCB get a locked sys_2x_clk before exiting
-- SELFREFRESH mode.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MCB_REQ <= '0';
--elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then
SELFREFRESH_MCB_REQ <= '0';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then
SELFREFRESH_MCB_REQ <= '1';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
-- START_DYN_CAL is next state
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
end if;
end if;
end process;
-- Need to detect when SM entering START_DYN_CAL
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
START_DYN_CAL_STATE_R1 <= '0';
else
-- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
if (STATE = START_DYN_CAL) then
START_DYN_CAL_STATE_R1 <= '1';
else
START_DYN_CAL_STATE_R1 <= '0';
end if;
if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
end if;
end if;
end if;
end process;
-- SELFREFRESH_MCB_MODE deasserted status is hold off
-- until Soft_Calib has at least done one loop of DQS update.
-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before
-- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before
-- user logic sending new commands to MCB.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
SELFREFRESH_MODE_xilinx11 <= '1';
elsif (WarmEnough = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitCountEnable <= '0';
elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then
WaitCountEnable <= '0';
elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
WaitCountEnable <= '1';
else
WaitCountEnable <= WaitCountEnable;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal <= '0';
elsif (STATE = START_DYN_CAL) then
State_Start_DynCal <= '1';
else
State_Start_DynCal <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal_R1 <= '0';
else
State_Start_DynCal_R1 <= State_Start_DynCal;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitTimer <= (others => '0');
WarmEnough <= '1';
elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then
WaitTimer <= (others => '0');
WarmEnough <= '0';
elsif (WaitTimer = X"04") then
WaitTimer <= WaitTimer ;
WarmEnough <= '1';
elsif (WaitCountEnable = '1') then
WaitTimer <= WaitTimer + '1';
else
WaitTimer <= WaitTimer ;
end if;
end if;
end process;
--********************************************
--Comparitor for Dynamic Calibration circuit
--********************************************
Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
--*********************************************************************************************
--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
--*********************************************************************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then
count <= "000000";
elsif (counter_en = '1') then
count <= count + "000001";
else
count <= "000000";
end if;
end if;
end process;
--*********************************************************************************************
-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
--*********************************************************************************************
process (UI_CLK, MCB_UODATAVALID)
begin
if(MCB_UODATAVALID = '1') then
MCB_UODATAVALID_U <= '1';
elsif(UI_CLK'event and UI_CLK = '1') then
MCB_UODATAVALID_U <= MCB_UODATAVALID;
end if;
end process;
--**************************************************************************************************************
--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
--**************************************************************************************************************
process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
begin
case Active_IODRP is
when RZQ =>
RZQ_IODRP_CS <= IODRP_CS;
ZIO_IODRP_CS <= '0';
IODRP_SDO <= RZQ_IODRP_SDO;
when ZIO =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= IODRP_CS;
IODRP_SDO <= ZIO_IODRP_SDO;
when MCB_PORT =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
when others =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
end case;
end process;
--******************************************************************
--State Machine's Always block / Case statement for Next State Logic
--
--The WAIT1,2,etc states were required after every state where the
--DRP controller was used to do a write to the IODRPs - this is because
--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
--sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
--soley for the purpose of reducing power, particularly on RZQ as
--that pin is expected to have a permanent external resistor to gnd.
--******************************************************************
NEXT_STATE_LOGIC: process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then -- Synchronous reset
MCB_CMD_VALID <= '0';
MCB_UIADDR_int <= "00000"; -- take control of UI/UO port
MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
MCB_UIDONECAL_xilinx7 <= '0';
MCB_USE_BKST <= '0';
MCB_UIDRPUPDATE <= '1';
Pre_SYSRST <= '1'; -- keeps MCB in reset
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
P_Term_s <= "000000";
N_Term_w <= "0000000";
P_Term_w <= "000000";
N_Term_s <= "0000000";
P_Term_Prev <= "000000";
N_Term_Prev <= "0000000";
Active_IODRP <= RZQ;
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
counter_en <= '0'; --flag that the First Dynamic Calibration completed
First_Dyn_Cal_Done <= '0';
Max_Value_int <= "00000000";
Max_Value_Previous <= "00000000";
STATE <= START;
DQS_DELAY <= "00000000";
DQS_DELAY_INITIAL <= "00000000";
TARGET_DQS_DELAY <= "00000000";
LastPass_DynCal <= IN_TERM_PASS;
First_In_Term_Done <= '0';
MCB_UICMD <= '0';
MCB_UICMDIN <= '0';
MCB_UIDQCOUNT <= "0000";
counter_inc <= "00000000";
counter_dec <= "00000000";
else
counter_en <= '0';
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_R_WB <= READ_MODE;
IODRPCTRLR_USE_BKST <= '0';
MCB_CMD_VALID <= '0'; --no inc or dec
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
MCB_USE_BKST <= '0';
MCB_UICMDIN <= '0';
DQS_DELAY <= DQS_DELAY;
TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
case STATE is
when START => --h00
MCB_UICMDEN <= '1'; -- take control of UI/UO port
MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
P_Term <= "000000";
N_Term <= "0000000";
Pre_SYSRST <= '1'; -- keeps MCB in reset
LastPass_DynCal <= IN_TERM_PASS;
if (SKIP_IN_TERM_CAL = 1) then
--STATE <= WRITE_CALIBRATE;
STATE <= WAIT_FOR_START_BROADCAST;
P_Term <= "000000";
N_Term <= "0000000";
elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= START;
end if;
--***************************
-- IOB INPUT TERMINATION CAL
--***************************
when LOAD_RZQ_NTERM => --h01
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= WAIT1;
end if;
when WAIT1 => --h02
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT1;
else
STATE <= LOAD_RZQ_PTERM;
end if;
when LOAD_RZQ_PTERM => --h03
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_PTERM;
else
STATE <= WAIT2;
end if;
when WAIT2 => --h04
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT2;
elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
else
STATE <= INC_PTERM;
end if;
when INC_PTERM => --h05
P_Term <= P_Term + "000001";
STATE <= LOAD_RZQ_PTERM;
when MULTIPLY_DIVIDE => -- h06
-- 13/4/2011 compensate the added sync FF
P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
STATE <= LOAD_ZIO_PTERM;
when LOAD_ZIO_PTERM => --h07
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_PTERM;
else
STATE <= WAIT3;
end if;
when WAIT3 => --h08
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT3;
else
STATE <= LOAD_ZIO_NTERM;
end if;
when LOAD_ZIO_NTERM => --h09
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_NTERM;
else
STATE <= WAIT4;
end if;
when WAIT4 => --h0A
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
else
STATE <= INC_NTERM;
end if;
when INC_NTERM => --h0B
N_Term <= N_Term + "0000001";
STATE <= LOAD_ZIO_NTERM;
when SKEW => -- h0C
P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0);
P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
STATE <= WAIT_FOR_START_BROADCAST;
when WAIT_FOR_START_BROADCAST => --h0D
Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
-- keeping the MCB in calibration mode
Active_IODRP <= MCB_PORT;
if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then
STATE <= BROADCAST_PTERM;
P_Term_Prev <= P_Term;
elsif (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
when BROADCAST_PTERM => --h0E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
MCB_USE_BKST <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_PTERM;
else
STATE <= WAIT5;
end if;
when WAIT5 => --h0F
if ((not(MCB_RDY_BUSY_N)) = '1') then
STATE <= WAIT5;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
if (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT5; -- wait for a Refresh cycle
end if;
else
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
end if;
when BROADCAST_NTERM => -- h10
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_USE_BKST <= '1';
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_NTERM;
else
STATE <= WAIT6;
end if;
when WAIT6 => -- h11
if (MCB_RDY_BUSY_N = '0') then
STATE <= WAIT6;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT6; -- wait for a Refresh cycle
end if;
else
-- if (PNSKEWDQS = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
-- else
-- STATE <= OFF_RZQ_PTERM;
-- end if;
end if;
-- *********************
when LDQS_CLK_WRITE_P_TERM => -- h12
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
else
STATE <= LDQS_CLK_P_TERM_WAIT;
end if;
when LDQS_CLK_P_TERM_WAIT => --7'h13
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_P_TERM_WAIT;
else
STATE <= LDQS_CLK_WRITE_N_TERM;
end if;
when LDQS_CLK_WRITE_N_TERM => --7'h14
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_N_TERM;
else
STATE <= LDQS_CLK_N_TERM_WAIT;
end if;
--**
when LDQS_CLK_N_TERM_WAIT => --7'h15
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_N_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_P_TERM;
end if;
when LDQS_PIN_WRITE_P_TERM => --7'h16
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_P_TERM;
else
STATE <= LDQS_PIN_P_TERM_WAIT;
end if;
when LDQS_PIN_P_TERM_WAIT => --7'h17
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_P_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_N_TERM;
end if;
when LDQS_PIN_WRITE_N_TERM => --7'h18
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_N_TERM;
else
STATE <= LDQS_PIN_N_TERM_WAIT;
end if;
when LDQS_PIN_N_TERM_WAIT => --7'h19
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_N_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_P_TERM;
end if;
when UDQS_CLK_WRITE_P_TERM => --7'h1A
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_P_TERM;
else
STATE <= UDQS_CLK_P_TERM_WAIT;
end if;
when UDQS_CLK_P_TERM_WAIT => --7'h1B
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_P_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_N_TERM;
end if;
when UDQS_CLK_WRITE_N_TERM => --7'h1C
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_N_TERM;
else
STATE <= UDQS_CLK_N_TERM_WAIT;
end if;
when UDQS_CLK_N_TERM_WAIT => --7'h1D
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_N_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_P_TERM;
end if;
when UDQS_PIN_WRITE_P_TERM => --7'h1E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_P_TERM;
else
STATE <= UDQS_PIN_P_TERM_WAIT;
end if;
when UDQS_PIN_P_TERM_WAIT => --7'h1F
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_P_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_N_TERM;
end if;
when UDQS_PIN_WRITE_N_TERM => --7'h20
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_N_TERM;
else
STATE <= UDQS_PIN_N_TERM_WAIT;
end if;
when UDQS_PIN_N_TERM_WAIT => --7'h21
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_N_TERM_WAIT;
else
STATE <= OFF_RZQ_PTERM;
end if;
-- *********************
when OFF_RZQ_PTERM => -- h22
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
P_Term <= "000000";
N_Term <= "0000000";
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT7;
end if;
when WAIT7 => -- h23
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT7;
else
STATE <= OFF_ZIO_NTERM;
end if;
when OFF_ZIO_NTERM => -- h24
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_ZIO_NTERM;
else
STATE <= WAIT8;
end if;
when WAIT8 => -- h25
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT8;
else
if (First_In_Term_Done = '1') then
STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
else
STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
end if;
end if;
when RST_DELAY => -- h26
--MCB_UICMDEN <= '0'; -- release control of UI/UO port
if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
STATE <= RST_DELAY;
else
STATE <= START_DYN_CAL_PRE;
end if;
--***************************
--DYNAMIC CALIBRATION PORTION
--***************************
when START_DYN_CAL_PRE => -- h27
LastPass_DynCal <= IN_TERM_PASS;
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '1'; -- SYSRST pulse
if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
elsif (pre_sysrst_minpulse_width_ok = '1') then
STATE <= WAIT_FOR_UODONE;
end if;
when WAIT_FOR_UODONE => -- h28
Pre_SYSRST <= '0'; -- SYSRST pulse
if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
MCB_UICMDEN <= '1'; -- grab UICMDEN
DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= WAIT_FOR_UODONE;
end if;
when LDQS_WRITE_POS_INDELAY => -- h29
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= LDQS_WAIT1;
end if;
when LDQS_WAIT1 => -- h2A
if (MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT1;
else
STATE <= LDQS_WRITE_NEG_INDELAY;
end if;
when LDQS_WRITE_NEG_INDELAY => -- h2B
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= LDQS_WRITE_NEG_INDELAY;
else
STATE <= LDQS_WAIT2;
end if;
when LDQS_WAIT2 => -- 7'h2C
if(MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT2;
else
STATE <= UDQS_WRITE_POS_INDELAY;
end if;
when UDQS_WRITE_POS_INDELAY => -- 7'h2D
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_POS_INDELAY;
else
STATE <= UDQS_WAIT1;
end if;
when UDQS_WAIT1 => -- 7'h2E
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT1;
else
STATE <= UDQS_WRITE_NEG_INDELAY;
end if;
when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_NEG_INDELAY;
else
STATE <= UDQS_WAIT2;
end if;
when UDQS_WAIT2 => -- 7'h30
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT2;
else
DQS_DELAY <= DQS_DELAY_INITIAL;
TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
STATE <= START_DYN_CAL;
end if;
when START_DYN_CAL => -- h31
Pre_SYSRST <= '0'; -- SYSRST not driven
counter_inc <= (others => '0');
counter_dec <= (others => '0');
if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
--IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
-- Alternate between Dynamic Input Termination and Dynamic Tuning routines
if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
LastPass_DynCal <= IN_TERM_PASS;
STATE <= LOAD_RZQ_NTERM;
else
LastPass_DynCal <= DYN_CAL_PASS;
STATE <= WRITE_CALIBRATE;
end if;
else
STATE <= START_DYN_CAL;
end if;
when WRITE_CALIBRATE => -- h32
Pre_SYSRST <= '0';
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
IODRPCTRLR_WRITE_DATA <= "00100000";
IODRPCTRLR_R_WB <= WRITE_MODE;
Active_IODRP <= RZQ;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= WRITE_CALIBRATE;
else
STATE <= WAIT9;
end if;
when WAIT9 => -- h33
counter_en <= '1';
if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
STATE <= WAIT9;
else
STATE <= READ_MAX_VALUE;
end if;
when READ_MAX_VALUE => -- h34
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
IODRPCTRLR_R_WB <= READ_MODE;
Max_Value_Previous <= Max_Value_int;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= READ_MAX_VALUE;
else
STATE <= WAIT10;
end if;
when WAIT10 => -- h35
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT10;
else
Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
if (First_In_Term_Done = '0') then
STATE <= RST_DELAY;
First_In_Term_Done <= '1';
else
STATE <= ANALYZE_MAX_VALUE;
end if;
end if;
when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle.
if (First_Dyn_Cal_Done = '0')then
STATE <= FIRST_DYN_CAL;
elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
STATE <= DECREMENT; -- May need to Decrement
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
-- DQS_COUNT_VIRTUAL updated (could be negative value)
elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
STATE <= INCREMENT; -- May need to Increment
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
else
Max_Value_int <= Max_Value_Previous;
STATE <= START_DYN_CAL;
end if;
when FIRST_DYN_CAL => -- h37
First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
STATE <= START_DYN_CAL;
when INCREMENT => -- h38
STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "101" =>
counter_inc <= counter_inc + '1';
STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
-- if not at the upper limit yet, and you've waited 4 clks, increment
MCB_UILDQSINC <= '1';
MCB_UIUDQSINC <= '1';
DQS_DELAY <= DQS_DELAY + '1';
end if;
when "100" =>
if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
when DECREMENT => -- h39
STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
if (DQS_DELAY /= "00000000") then
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "011" =>
counter_dec <= counter_dec + '1';
STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
-- if not at the lower limit, and you've waited 4 clks, decrement
MCB_UILDQSDEC <= '1'; -- decrement
MCB_UIUDQSDEC <= '1'; -- decrement
DQS_DELAY <= DQS_DELAY - '1'; -- SBS
end if;
when "010" =>
if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
end if;
when DONE => -- h3A
Pre_SYSRST <= '0'; -- SYSRST cleared
MCB_UICMDEN <= '0'; -- release UICMDEN
STATE <= DONE;
when others =>
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '0'; -- SYSRST not driven
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= "00000000";
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= '0';
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
Active_IODRP <= ZIO;
Max_Value_Previous <= "00000000";
MCB_UILDQSINC <= '0'; -- no inc or dec
MCB_UIUDQSINC <= '0'; -- no inc or dec
MCB_UILDQSDEC <= '0'; -- no inc or dec
MCB_UIUDQSDEC <= '0'; -- no inc or dec
counter_en <= '0';
First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
Max_Value_int <= Max_Value_int;
STATE <= START;
end case;
end if;
end if;
end process;
end architecture trans;
| cc0-1.0 | f20b00bd7618100894b8543f31f279fc | 0.474288 | 4.244221 | false | false | false | false |
freecores/hilbert_transformer | vhdl/hilbert_11_tap_opt.vhd | 1 | 5,430 | -- optimized version of a 10 tap FIR hilbert filter
-- The impulse response is h={-0.1066 0 -0.1781 0 -0.5347 0 0.5347 0 0.1781 0 0.1066}
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
package hilbert_filter_pkg is
component hilbert_filter
generic(
input_data_width : integer;
output_data_width : integer;
internal_data_width : integer
);
port(
clk : in std_logic;
clk_enable : in std_logic;
reset : in std_logic;
filter_in : in std_logic_vector(15 downto 0); -- sfix16_en15
filter_out : out std_logic_vector(15 downto 0) -- sfix16_en10
);
end component;
end hilbert_filter_pkg;
package body hilbert_filter_pkg is
end hilbert_filter_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.resize_tools_pkg.all;
entity hilbert_filter is
generic(
input_data_width : integer := 16;
output_data_width : integer := 16;
internal_data_width : integer := 16
);
port(
clk : in std_logic;
clk_enable : in std_logic;
reset : in std_logic;
filter_in : in std_logic_vector(15 downto 0); -- sfix16_en15
filter_out : out std_logic_vector(15 downto 0) -- sfix16_en10
);
end hilbert_filter;
architecture hilbert_filter_arch of hilbert_filter is
constant no_of_coefficients : integer := 3;
constant h0_real : real := -32.0/256.0; -- -0.106635588611691;
constant h2_real : real := -54.0/256.0;-- -0.178063554399423;
constant h4_real : real := -163.0/256.0;-- -0.534697271169593;
constant h0_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h0_real * 2.0**(internal_data_width-1)),internal_data_width));
constant h2_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h2_real * 2.0**(internal_data_width-1)),internal_data_width));
constant h4_int : std_logic_vector(internal_data_width-1 downto 0) := std_logic_vector(to_signed(integer(h4_real * 2.0**(internal_data_width-1)),internal_data_width));
type xmh_type is array(0 to no_of_coefficients-1) of std_logic_vector(internal_data_width-1 downto 0);
signal xmh : xmh_type; --x mult with coeff. h
signal xmhd : xmh_type; --xmh delayed one clock
signal xmhd0inv : std_logic_vector(internal_data_width-1 downto 0);
signal xmhd0invd : std_logic_vector(internal_data_width-1 downto 0);
signal xmhd0invdd : std_logic_vector(internal_data_width-1 downto 0);
type tmp_type is array(0 to no_of_coefficients) of std_logic_vector(internal_data_width-1 downto 0);
signal t : tmp_type; --temporary signal ater each addition
signal td : tmp_type; --t delayed one clock
signal tdd : tmp_type; --t delayed two clocks
signal y : std_logic_vector(internal_data_width-1 downto 0);
begin
xmh(0) <= std_logic_vector(shift_left(signed(resize_to_msb_trunc(filter_in,internal_data_width/2)) * signed(resize_to_msb_round(h0_int,internal_data_width/2)),1));
xmh(1) <= std_logic_vector(shift_left(signed(resize_to_msb_trunc(filter_in,internal_data_width/2)) * signed(resize_to_msb_round(h2_int,internal_data_width/2)),1));
xmh(2) <= std_logic_vector(shift_left(signed(resize_to_msb_trunc(filter_in,internal_data_width/2)) * signed(resize_to_msb_round(h4_int,internal_data_width/2)),1));
xmhd0inv <= std_logic_vector(to_signed(-1 * to_integer(signed(xmhd(0))),internal_data_width));
t(0) <= std_logic_vector(signed(xmhd0invdd) - signed(xmhd(1)));
t(1) <= std_logic_vector(signed(tdd(0)) - signed(xmhd(2)));
t(2) <= std_logic_vector(signed(tdd(1)) + signed(xmhd(2)));
t(3) <= std_logic_vector(signed(tdd(2)) + signed(xmhd(1)));
y <= std_logic_vector(signed(tdd(3)) + signed(xmhd(0)));
process (clk, reset)
begin
if reset = '1' then
for i in 0 to no_of_coefficients-1 loop
xmhd(i) <= (others => '0');
end loop;
for i in 0 to no_of_coefficients loop
td(i) <= (others => '0');
tdd(i) <= (others => '0');
end loop;
xmhd0invd <= (others => '0');
xmhd0invdd <= (others => '0');
filter_out <= (others => '0');
elsif clk'event and clk = '1' then
if clk_enable = '1' then
for i in 0 to no_of_coefficients-1 loop
xmhd(i) <= xmh(i);
end loop;
for i in 0 to no_of_coefficients loop
td(i) <= t(i);
tdd(i) <= td(i);
end loop;
xmhd0invd <= xmhd0inv;
xmhd0invdd <= xmhd0invd;
filter_out <= resize_to_msb_trunc(y,output_data_width);
end if;
end if;
end process;
end hilbert_filter_arch;
| gpl-3.0 | 75d6f613147dbef14688a41fbc581cce | 0.648435 | 3.113532 | false | false | false | false |
B-George/ECEGR_4220_MIPS_PROC | Processor.vhd | 1 | 5,628 | --------------------------------------------------------------------------------
--
-- LAB #5 - Processor
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Processor IS
PORT ( instruction : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemdatain : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemdataout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
InstMemAddr : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemAddr : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DataMemRead : OUT STD_LOGIC;
DataMemWrite : OUT STD_LOGIC;
clock : IN STD_LOGIC);
END Processor;
architecture holistic of Processor IS
--signals
SIGNAL RegDst1, Branch1, MemRead1, MemtoReg1,
MemWrite1, ALUSrc,Regwrite, zero1, shiftSel
: STD_LOGIC;
SIGNAL ALUOp1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL aluctrl1, intoReg1, intowrite
: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL rdata1, rdata2, intowriteD, extendsig,
extendsig2, tempaluin2,aluin2, alures,
tempMemAddr, add_in, add_out
: STD_LOGIC_VECTOR(31 DOWNTO 0);
--components
COMPONENT Control
PORT(opcode : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
clk : IN STD_LOGIC;
RegDst : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC;
ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC);
END COMPONENT;
COMPONENT ALUControl
PORT( op : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
funct : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
aluctrl : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
ShiftReg : OUT STD_LOGIC);
END COMPONENT;
COMPONENT ALU
PORT( DataIn1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DataIn2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Control : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Zero : OUT STD_LOGIC;
ALUResult: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END COMPONENT;
COMPONENT Registers
PORT( ReadReg1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ReadReg2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WriteReg : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WriteData: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
WriteCmd : IN STD_LOGIC;
ReadData1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ReadData2: OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT;
COMPONENT BusMux2to1
PORT( selector : IN STD_LOGIC;
In0, In1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END COMPONENT;
COMPONENT SmallbusMux2to1
PORT( selector : IN STD_LOGIC;
In0, In1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END COMPONENT;
COMPONENT adder_subtracter IS
PORT( datain_a : IN STD_LOGIC_vector(31 DOWNTO 0);
datain_b : IN STD_LOGIC_vector(31 DOWNTO 0);
add_sub : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0);
co : OUT STD_LOGIC);
END COMPONENT;
BEGIN
--
--
extendsig <= "1111111111111111" & instruction(15 DOWNTO 0) WHEN instruction(15) = '1' ELSE
"0000000000000000" & instruction(15 DOWNTO 0);
-- shift amount. not sure why we need to signify a negative number if inst(10) = '1'
extendsig2 <= "111111111111111111111111111" & instruction(10 DOWNTO 6) WHEN instruction(10) = '1' ELSE
"000000000000000000000000000" & instruction(10 DOWNTO 6);
CO: Control PORT MAP(instruction(31 DOWNTO 26),clock,RegDst1,Branch1,MemRead1,MemtoReg1,ALUOp1,MemWrite1,ALUSrc,Regwrite);
-- Selects register to read from based on whether we are doing a shift operation.
-- reads from register at inst(25-21) for shiftSel = '0', inst(20-16) for shiftSel = '1'
-- shiftSel is set by the ALUControl unit
RM: SmallbusMux2to1 PORT MAP(shiftSel,instruction(25 DOWNTO 21),instruction(20 DOWNTO 16), intoReg1);
-- Selects 2nd input to ALU, based on whether we are doing a shift operation
-- 1st input is from MX mux, 2nd input is sign-extended shift amount
-- shiftSel is set by the ALUControl unit
M2: BusMux2to1 PORT MAP(shiftSel,tempaluin2,extendsig2,aluin2);
AL: ALUControl PORT MAP(ALUOp1,instruction(5 DOWNTO 0),aluctrl1,shiftSel);
-- Selects write register. instruction (15 downto 11) for RegDst1 = '1',
-- instruction (20 downto 16) for RegDst1 = '0'
-- RegDst1 is set by control unit = '1' for R-type ops
-- '0' for others.
MU: SmallbusMux2to1 PORT MAP(RegDst1,instruction(20 DOWNTO 16),instruction(15 DOWNTO 11),intowrite);
-- 32 x 32-bit register bank
RE: Registers PORT MAP(intoReg1,instruction(20 DOWNTO 16),intowrite,intowriteD,Regwrite,rdata1,rdata2);
-- 32-bit mux
-- Selects 1st input to M2 mux, based on ALUSrc.
-- ALUSrc is '0' for R-type instructions, '1' for others
-- output is register data for R-type,
-- sign extended lower 16 bits of instruction for I-type
MX: BusMux2to1 PORT MAP(ALUSrc, rdata2, extendsig,tempaluin2);
AU: ALU PORT MAP(rdata1,aluin2,aluctrl1, zero1, tempMemAddr);
-- 32-bit mux
-- Selects Data to be written to registers in LW op
-- Input : tempMemAddr [ALU Output], DataMemDatain [Register Contents]
-- Output: intowriteD [Write Data -- is written to location specified by 5-bit MU mux]
-- Control: MemtoReg1 ['1' for LW op, '0' for others]
MZ: BusMux2to1 PORT MAP(MemtoReg1,tempMemAddr,DataMemdatain,intowriteD);
DataMemAddr <= tempMemAddr;
DataMemWrite <= MemWrite1;
DataMemdataout <= rdata2;
DataMemRead <= MemRead1;
END holistic;
| mit | 42ca097d3c2c67d8914705bd1e0788e1 | 0.661336 | 3.217839 | false | false | false | false |
B-George/ECEGR_4220_MIPS_PROC | ProcElements.vhd | 1 | 12,436 | --------------------------------------------------------------------------------
--
-- LAB #5 - Processor Elements
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SmallBusMux2to1 IS
PORT(selector : IN STD_LOGIC;
In0, In1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
Result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) );
END ENTITY SmallBusMux2to1;
ARCHITECTURE switching OF SmallBusMux2to1 IS
BEGIN
WITH selector SELECT
Result <= In0 WHEN '0',
In1 WHEN OTHERS;
END ARCHITECTURE switching;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BusMux2to1 IS
PORT(selector : IN STD_LOGIC;
In0, In1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END ENTITY BusMux2to1;
ARCHITECTURE selection OF BusMux2to1 IS
BEGIN
WITH selector SELECT
Result <= In0 WHEN '0',
In1 WHEN OTHERS;
END ARCHITECTURE selection;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Control IS
PORT ( opcode : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
clk : IN STD_LOGIC;
RegDst : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC;
ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC);
END Control;
ARCHITECTURE Boss OF Control IS
BEGIN
-- selects register to be written to
-- instruction(15-11) when = '1'
-- instruction(20-16) when = '0'
RegDst <= '1' WHEN opcode(5 DOWNTO 0) = "000000" ELSE
'0';
-- defines source of 1st input to MUX(M2)
-- registers for '0' (R-type)
-- sign extender for '1' (I-type)
ALUSrc <= '0' WHEN opcode(5 DOWNTO 0) = "000000" ELSE
'1';
-- flag bit for LW op
-- input to 32-bit MZ mux
MemtoReg <= '1' WHEN opcode(5 DOWNTO 0) = "100011" ELSE
'0';
-- flag bit for register write
-- '0' for SW op
-- else writes on clock = '0' (between cycles)
RegWrite <= '0' WHEN opcode(5 DOWNTO 0) = "101011" ELSE
not(clk);
-- flag bit for lw op
-- toggles DataMemRead bit in processor
MemRead <= '1' WHEN opcode(5 DOWNTO 0) = "100011" ELSE
'0';
-- flag bit for SW op
-- toggles DataMemWrite bit in processor
MemWrite <= '1' WHEN opcode(5 DOWNTO 0) = "101011" ELSE
'0';
-- In to ALU control
-- Defines which type of op to be performed
ALUOp <= "01" WHEN opcode(5 DOWNTO 0) = "000000" ELSE -- R-Type
"10" WHEN opcode(5 DOWNTO 0) = "001101" ELSE -- or, ori
"00"; -- LW, SW
END Boss;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALUControl IS
PORT(op : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
funct : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
aluctrl : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
ShiftReg : OUT STD_LOGIC);
END ENTITY ALUControl;
ARCHITECTURE bossy OF ALUControl IS
SIGNAL tempctrl: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
tempctrl <= "00000" WHEN op = "00" ELSE
"00011" WHEN op = "10" ELSE
"00000" WHEN op = "01" and funct = "100000" ELSE -- add op
"00001" WHEN op = "01" and funct = "100010" ELSE -- sub op
"00010" WHEN op = "01" and funct = "100100" ELSE -- or op
"00011" WHEN op = "01" and funct = "100101" ELSE -- ori op
"00100" WHEN op = "01" and funct = "000000" ELSE -- srl op
"00101" WHEN op = "01" and funct = "000010" ELSE -- sll op
"11111";
ShiftReg <= '1' WHEN tempctrl = "00100" or tempctrl = "00101" ELSE
'0';
aluctrl <= tempctrl;
END ARCHITECTURE bossy;
----------------------------------------------------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Registers IS
PORT(ReadReg1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
ReadReg2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WriteReg : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
WriteData : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
WriteCmd : IN STD_LOGIC;
ReadData1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ReadData2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END ENTITY Registers;
ARCHITECTURE remember OF Registers IS
COMPONENT register32
port(datain : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
enout32, enout16, enout8
: IN STD_LOGIC;
writein32, writein16, writein8
: IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT;
SIGNAL rzero, at, v0, v1, a0, a1, a2, a3, t0, t1, t2, t3, t4, t5, t6, t7,
s0, s1, s2, s3, s4, s5, s6, s7, t8, t9, k0, k1,
gp, sp, fp, ra: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL writeit : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
zero: register32 PORT MAP(WriteData,'0','0','0',writeit(0),'0','0',rzero);
rAT: register32 PORT MAP(WriteData,'0','0','0',writeit(1),'0','0',at);
rV0: register32 PORT MAP(WriteData,'0','0','0',writeit(2),'0','0',v0);
rV1: register32 PORT MAP(WriteData,'0','0','0',writeit(3),'0','0',v1);
rA0: register32 PORT MAP(WriteData,'0','0','0',writeit(4),'0','0',a0);
rA1: register32 PORT MAP(WriteData,'0','0','0',writeit(5),'0','0',a1);
rA2: register32 PORT MAP(WriteData,'0','0','0',writeit(6),'0','0',a2);
rA3: register32 PORT MAP(WriteData,'0','0','0',writeit(7),'0','0',a3);
rT0: register32 PORT MAP(WriteData,'0','0','0',writeit(8),'0','0',t0);
rT1: register32 PORT MAP(WriteData,'0','0','0',writeit(9),'0','0',t1);
rT2: register32 PORT MAP(WriteData,'0','0','0',writeit(10),'0','0',t2);
rT3: register32 PORT MAP(WriteData,'0','0','0',writeit(11),'0','0',t3);
rT4: register32 PORT MAP(WriteData,'0','0','0',writeit(12),'0','0',t4);
rT5: register32 PORT MAP(WriteData,'0','0','0',writeit(13),'0','0',t5);
rT6: register32 PORT MAP(WriteData,'0','0','0',writeit(14),'0','0',t6);
rT7: register32 PORT MAP(WriteData,'0','0','0',writeit(15),'0','0',t7);
rS0: register32 PORT MAP(WriteData,'0','0','0',writeit(16),'0','0',s0);
rS1: register32 PORT MAP(WriteData,'0','0','0',writeit(17),'0','0',s1);
rS2: register32 PORT MAP(WriteData,'0','0','0',writeit(18),'0','0',s2);
rS3: register32 PORT MAP(WriteData,'0','0','0',writeit(19),'0','0',s3);
rS4: register32 PORT MAP(WriteData,'0','0','0',writeit(20),'0','0',s4);
rS5: register32 PORT MAP(WriteData,'0','0','0',writeit(21),'0','0',s5);
rS6: register32 PORT MAP(WriteData,'0','0','0',writeit(22),'0','0',s6);
rS7: register32 PORT MAP(WriteData,'0','0','0',writeit(23),'0','0',s7);
rT8: register32 PORT MAP(WriteData,'0','0','0',writeit(24),'0','0',t8);
rT9: register32 PORT MAP(WriteData,'0','0','0',writeit(25),'0','0',t9);
rK0: register32 PORT MAP(WriteData,'0','0','0',writeit(26),'0','0',k0);
rK1: register32 PORT MAP(WriteData,'0','0','0',writeit(27),'0','0',k1);
rGp: register32 PORT MAP(WriteData,'0','0','0',writeit(28),'0','0',gp);
rSp: register32 PORT MAP(WriteData,'0','0','0',writeit(29),'0','0',sp);
rFp: register32 PORT MAP(WriteData,'0','0','0',writeit(30),'0','0',fp);
rRa: register32 PORT MAP(WriteData,'0','0','0',writeit(31),'0','0',ra);
writeit <= x"00000001" WHEN WriteReg = "00001" and WriteCmd = '1' ELSE --01
x"00000002" WHEN WriteReg = "00010" and WriteCmd = '1' ELSE --02
x"00000003" WHEN WriteReg = "00011" and WriteCmd = '1' ELSE --03
x"00000004" WHEN WriteReg = "00100" and WriteCmd = '1' ELSE --04
x"00000005" WHEN WriteReg = "00101" and WriteCmd = '1' ELSE --05
x"00000006" WHEN WriteReg = "00110" and WriteCmd = '1' ELSE --06
x"00000007" WHEN WriteReg = "00111" and WriteCmd = '1' ELSE --07
x"00000008" WHEN WriteReg = "01000" and WriteCmd = '1' ELSE --08
x"00000009" WHEN WriteReg = "01001" and WriteCmd = '1' ELSE --09
x"0000000A" WHEN WriteReg = "01010" and WriteCmd = '1' ELSE --10
x"0000000B" WHEN WriteReg = "01011" and WriteCmd = '1' ELSE --11
x"0000000C" WHEN WriteReg = "01100" and WriteCmd = '1' ELSE --12
x"0000000D" WHEN WriteReg = "01101" and WriteCmd = '1' ELSE --13
x"0000000E" WHEN WriteReg = "01110" and WriteCmd = '1' ELSE --14
x"0000000F" WHEN WriteReg = "01111" and WriteCmd = '1' ELSE --15
x"00000010" WHEN WriteReg = "10000" and WriteCmd = '1' ELSE --16
x"00000011" WHEN WriteReg = "10001" and WriteCmd = '1' ELSE --17
x"00000012" WHEN WriteReg = "10010" and WriteCmd = '1' ELSE --18
x"00000013" WHEN WriteReg = "10011" and WriteCmd = '1' ELSE --19
x"00000014" WHEN WriteReg = "10100" and WriteCmd = '1' ELSE --20
x"00000015" WHEN WriteReg = "10101" and WriteCmd = '1' ELSE --21
x"00000016" WHEN WriteReg = "10110" and WriteCmd = '1' ELSE --22
x"00000017" WHEN WriteReg = "10111" and WriteCmd = '1' ELSE --23
x"00000018" WHEN WriteReg = "11000" and WriteCmd = '1' ELSE --24
x"00000019" WHEN WriteReg = "11001" and WriteCmd = '1' ELSE --25
x"0000001A" WHEN WriteReg = "11010" and WriteCmd = '1' ELSE --26
x"0000001B" WHEN WriteReg = "11011" and WriteCmd = '1' ELSE --27
x"0000001C" WHEN WriteReg = "11100" and WriteCmd = '1' ELSE --28
x"0000001D" WHEN WriteReg = "11101" and WriteCmd = '1' ELSE --29
x"0000001E" WHEN WriteReg = "11110" and WriteCmd = '1' ELSE --30
x"0000001F" WHEN WriteReg = "11111" and WriteCmd = '1' ELSE --31
x"00000000"; --0
ReadData1 <=
at WHEN ReadReg1 = "00001" ELSE --1
v0 WHEN ReadReg1 = "00010" ELSE --2
v1 WHEN ReadReg1 = "00011" ELSE --3
a0 WHEN ReadReg1 = "00100" ELSE --4
a1 WHEN ReadReg1 = "00101" ELSE --5
a2 WHEN ReadReg1 = "00110" ELSE --6
a3 WHEN ReadReg1 = "00111" ELSE --7
t0 WHEN ReadReg1 = "01000" ELSE --8
t1 WHEN ReadReg1 = "01001" ELSE --9
t2 WHEN ReadReg1 = "01010" ELSE --10
t3 WHEN ReadReg1 = "01011" ELSE --11
t4 WHEN ReadReg1 = "01100" ELSE --12
t5 WHEN ReadReg1 = "01101" ELSE --13
t6 WHEN ReadReg1 = "01110" ELSE --14
t7 WHEN ReadReg1 = "01111" ELSE --15
s0 WHEN ReadReg1 = "10000" ELSE --16
s1 WHEN ReadReg1 = "10001" ELSE --17
s2 WHEN ReadReg1 = "10010" ELSE --18
s3 WHEN ReadReg1 = "10011" ELSE --19
s4 WHEN ReadReg1 = "10100" ELSE --20
s5 WHEN ReadReg1 = "10101" ELSE --21
s6 WHEN ReadReg1 = "10110" ELSE --22
s7 WHEN ReadReg1 = "10111" ELSE --23
t8 WHEN ReadReg1 = "11000" ELSE --24
t9 WHEN ReadReg1 = "11001" ELSE --25
k0 WHEN ReadReg1 = "11010" ELSE --26
k1 WHEN ReadReg1 = "11011" ELSE --27
gp WHEN ReadReg1 = "11100" ELSE --28
sp WHEN ReadReg1 = "11101" ELSE --29
fp WHEN ReadReg1 = "11110" ELSE --30
ra WHEN ReadReg1 = "11111" ELSE --31
rzero; --0
ReadData2 <=
at WHEN ReadReg2 = "00001" ELSE --1
v0 WHEN ReadReg2 = "00010" ELSE --2
v1 WHEN ReadReg2 = "00011" ELSE --3
a0 WHEN ReadReg2 = "00100" ELSE --4
a1 WHEN ReadReg2 = "00101" ELSE --5
a2 WHEN ReadReg2 = "00110" ELSE --6
a3 WHEN ReadReg2 = "00111" ELSE --7
t0 WHEN ReadReg2 = "01000" ELSE --8
t1 WHEN ReadReg2 = "01001" ELSE --9
t2 WHEN ReadReg2 = "01010" ELSE --10
t3 WHEN ReadReg2 = "01011" ELSE --11
t4 WHEN ReadReg2 = "01100" ELSE --12
t5 WHEN ReadReg2 = "01101" ELSE --13
t6 WHEN ReadReg2 = "01110" ELSE --14
t7 WHEN ReadReg2 = "01111" ELSE --15
s0 WHEN ReadReg2 = "10000" ELSE --16
s1 WHEN ReadReg2 = "10001" ELSE --17
s2 WHEN ReadReg2 = "10010" ELSE --18
s3 WHEN ReadReg2 = "10011" ELSE --19
s4 WHEN ReadReg2 = "10100" ELSE --20
s5 WHEN ReadReg2 = "10101" ELSE --21
s6 WHEN ReadReg2 = "10110" ELSE --22
s7 WHEN ReadReg2 = "10111" ELSE --23
t8 WHEN ReadReg2 = "11000" ELSE --24
t9 WHEN ReadReg2 = "11001" ELSE --25
k0 WHEN ReadReg2 = "11010" ELSE --26
k1 WHEN ReadReg2 = "11011" ELSE --27
gp WHEN ReadReg2 = "11100" ELSE --28
sp WHEN ReadReg2 = "11101" ELSE --29
fp WHEN ReadReg2 = "11110" ELSE --30
ra WHEN ReadReg2 = "11111" ELSE --31
rzero; --0
END remember;
----------------------------------------------------------------------------------------------------------------------------------------------------------------
| mit | 6bbf64fb88e9f129e835cd43cfe60d2f | 0.594564 | 3.032431 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/udp/udp_test_source.vhd | 1 | 4,597 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: udp_test_source - Behavioral
--
-- Description: Generate a few UDP packets for testing.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity udp_test_source is
Port (
clk : in STD_LOGIC;
-- interface for data to be sent over UDP
udp_tx_busy : in std_logic := '0';
udp_tx_valid : out std_logic := '0';
udp_tx_data : out std_logic_vector(7 downto 0) := (others => '0');
udp_tx_src_port : out std_logic_vector(15 downto 0) := (others => '0');
udp_tx_dst_mac : out std_logic_vector(47 downto 0) := (others => '0');
udp_tx_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
udp_tx_dst_port : out std_logic_vector(15 downto 0) := (others => '0'));
end udp_test_source;
architecture Behavioral of udp_test_source is
type t_state is (waiting, armed, sending);
signal state : t_state := waiting;
signal countdown : unsigned(27 downto 0) := to_unsigned(1000,28);
signal data_count : unsigned(7 downto 0) := to_unsigned(0,8);
begin
process(clk)
begin
if rising_edge(clk) then
udp_tx_valid <= '0';
udp_tx_data <= (others => '0');
udp_tx_src_port <= (others => '0');
udp_tx_dst_mac <= (others => '0');
udp_tx_dst_ip <= (others => '0');
udp_tx_dst_port <= (others => '0');
case state is
when waiting =>
udp_tx_valid <= '0';
if countdown = 0 then
countdown <= to_unsigned(124_999_999,28); -- 1 packet per second
-- countdown <= to_unsigned(499,24);
state <= armed;
else
countdown <= countdown-1;
end if;
when armed =>
udp_tx_valid <= '0';
if udp_tx_busy = '0' then
data_count <= (others => '0');
state <= sending;
end if;
when sending =>
-- Broadcast data from port 4660 to port 9029 on 10.0.0.255
udp_tx_valid <= '1';
udp_tx_src_port <= std_logic_vector(to_unsigned(4660,16));
udp_tx_dst_mac <= x"FF_FF_FF_FF_FF_FF";
udp_tx_dst_ip <= x"FF_00_00_0A";
udp_tx_dst_port <= std_logic_vector(to_unsigned(9029,16));
udp_tx_data <= std_logic_vector(data_count);
data_count <= data_count + 1;
if data_count = 2 then
state <= waiting;
end if;
when others =>
state <= waiting;
end case;
end if;
end process;
end Behavioral; | mit | a9c8b78cd9380bd53751c43ee64d501d | 0.507287 | 4.296262 | false | false | false | false |
hamsternz/FPGA_Webserver | hdl/other/buffer_count_and_checksum_data.vhd | 1 | 7,300 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: buffer_count_and_checksum_data - Behavioral
--
-- Description: Count and checksum the data to be put into a UDP or TCP packet
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity buffer_count_and_checksum_data is
generic (min_length : natural);
Port (
clk : in STD_LOGIC;
hdr_valid_in : in STD_LOGIC;
data_valid_in : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid_out : out STD_LOGIC := '0';
data_out : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
data_length : out std_logic_vector(15 downto 0) := (others => '0');
data_checksum : out std_logic_vector(15 downto 0) := (others => '0'));
end buffer_count_and_checksum_data;
architecture Behavioral of buffer_count_and_checksum_data is
type a_data_buffer is array (0 to 2047) of std_logic_vector(8 downto 0);
signal write_ptr : unsigned(10 downto 0) := (others => '0');
signal read_ptr : unsigned(10 downto 0) := (others => '1');
signal checkpoint : unsigned(10 downto 0) := (others => '1');
signal data_buffer : a_data_buffer := (others =>( others => '0'));
attribute ram_style : string;
attribute ram_style of data_buffer : signal is "block";
signal data_count : unsigned(10 downto 0) := to_unsigned(128,11);
signal wrote_valid_data : std_logic := '0';
signal data_valid_in_last : std_logic := '0';
signal checksum : unsigned(16 downto 0) := (others => '0');
signal read_data : std_logic_vector(8 downto 0) := (others => '0');
begin
data_valid_out <= read_data(8);
data_out <= read_data(7 downto 0);
infer_dp_mem_process: process(clk)
variable write_data : std_logic_vector(8 downto 0) := (others => '0');
variable write_enable : std_logic;
begin
if rising_edge(clk) then
write_enable := '0';
if data_valid_in = '1' then
write_data := data_valid_in & data_in;
write_enable := '1';
wrote_valid_data <= '1';
elsif hdr_valid_in = '1' then
write_data := '1'& x"00";
write_enable := '1';
wrote_valid_data <= '0';
elsif data_count < min_length-4 then -- Minimum UDP datasize to make minimum ethernet frame
-- Padding to make minimum packet size
write_data := '1'& x"00";
write_enable := '1';
wrote_valid_data <= '1';
else
write_data := '0'& x"00";
write_enable := wrote_valid_data;
wrote_valid_data <= '0';
end if;
if write_enable = '1' then
data_buffer(to_integer(write_ptr)) <= write_data;
end if;
read_data <= data_buffer(to_integer(read_ptr));
end if;
end process;
main_proc: process(clk)
variable v_checksum : unsigned(16 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if data_valid_in = '1' or hdr_valid_in = '1' or data_valid_in_last = '1' or data_count < min_length-3 then
write_ptr <= write_ptr + 1;
end if;
if data_valid_in = '1' then
if data_valid_in_last = '0' then
data_count <= to_unsigned(1,11);
else
data_count <= data_count + 1;
end if;
elsif hdr_valid_in = '1' then
-----------------------------------------------------
--For when there is no data to be sent, just a packet
-----------------------------------------------------
data_count <= to_unsigned(1,11);
end if;
if data_valid_in = '1' then
--- Update the checksum here
if data_count(0) = '0' or data_valid_in_last = '0' then
checksum <= to_unsigned(0,17) + checksum(15 downto 0) + checksum(16 downto 16) + (unsigned(data_in) & to_unsigned(0,8));
else
checksum <= to_unsigned(0,17) + checksum(15 downto 0) + checksum(16 downto 16) + unsigned(data_in);
end if;
else -- data_valid_in = '0'
if hdr_valid_in = '1' and data_valid_in = '0' then
data_length <= (others => '0');
data_checksum <= (others =>'0');
elsif data_valid_in_last = '1' then
-- End of packet
v_checksum := to_unsigned(0,17) + checksum(15 downto 0) + checksum(16 downto 16);
data_checksum <= std_logic_vector(v_checksum(15 downto 0) + v_checksum(16 downto 16));
data_length <= "00000" & std_logic_vector(data_count);
end if;
-- This is where padding is added
if data_count < min_length-3 then
data_count <= data_count + 1;
else
-- Enough data so checkpoint it
checkpoint <= write_ptr-1;
end if;
checksum <= (others => '0');
end if;
data_valid_in_last <= data_valid_in;
if read_ptr /= checkpoint then
read_ptr <= read_ptr+1;
end if;
end if;
end process;
end Behavioral;
| mit | ea297c16097d5105bd94cb17b713d4ed | 0.507534 | 4.176201 | false | false | false | false |
forflo/yodl | vhdlpp/elsif_eliminator_test.vhd | 1 | 1,010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- dummy entity
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fooProc : process() is
variable baz : natural := 4711;
begin
-- without else
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
end if;
-- with else
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
else
baz := 100000;
end if;
end process fooProc;
end beh;
| gpl-3.0 | ed4354710f2f6fbc5e6f83747ad5af42 | 0.50495 | 3.333333 | false | false | false | false |
cpavlina/logicanalyzer | la-hdl/ipcore_dir/mig_39_2/user_design/rtl/memc1_wrapper.vhd | 2 | 47,712 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc1_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:24 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector (15 downto 0) := x"0000";
C_MC_CALIBRATION_BA : bit_vector (2 downto 0):= "000";
C_MC_CALIBRATION_CA : bit_vector (11 downto 0):= x"000";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
-- memory interface signals
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
-- mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb1_dram_dqs : inout std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc1_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011";
constant C_PORT_CONFIG : string := "B32_B32_B32_B32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations
constant C_SKIP_DYN_IN_TERM : integer := 1;
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb1_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_92_lpddr_s6, Coregen 14.7";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb1_lpddr_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=LPDDR, CLK_PERIOD=6000, MEMORY_PART=mt46h16m16xxxx-6-it, MEMORY_DEVICE_WIDTH=16, PA_SR=FULL, OUTPUT_DRV=HALF, PORT_CONFIG=Four 32-bit bi-directional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc1_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb1_dram_a,
mcbx_dram_ba => mcb1_dram_ba,
mcbx_dram_ras_n => mcb1_dram_ras_n,
mcbx_dram_cas_n => mcb1_dram_cas_n,
mcbx_dram_we_n => mcb1_dram_we_n,
mcbx_dram_cke => mcb1_dram_cke,
mcbx_dram_clk => mcb1_dram_ck,
mcbx_dram_clk_n => mcb1_dram_ck_n,
mcbx_dram_dq => mcb1_dram_dq,
mcbx_dram_odt => open,
mcbx_dram_ldm => mcb1_dram_dm,
mcbx_dram_udm => mcb1_dram_udm,
mcbx_dram_dqs => mcb1_dram_dqs,
mcbx_dram_dqs_n => open,
mcbx_dram_udqs => mcb1_dram_udqs,
mcbx_dram_udqs_n => open,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb1_rzq,
zio => mcb1_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '0',
p2_cmd_clk => '0',
p2_cmd_en => '0',
p2_cmd_instr => (others => '0'),
p2_cmd_bl => (others => '0'),
p2_cmd_byte_addr => (others => '0'),
p2_cmd_empty => open,
p2_cmd_full => open,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => '0',
p2_wr_en => '0',
p2_wr_mask => (others => '0'),
p2_wr_data => (others => '0'),
p2_wr_full => open,
p2_wr_empty => open,
p2_wr_count => open,
p2_wr_underrun => open,
p2_wr_error => open,
p3_arb_en => '0',
p3_cmd_clk => '0',
p3_cmd_en => '0',
p3_cmd_instr => (others => '0'),
p3_cmd_bl => (others => '0'),
p3_cmd_byte_addr => (others => '0'),
p3_cmd_empty => open,
p3_cmd_full => open,
p3_rd_clk => '0',
p3_rd_en => '0',
p3_rd_data => open,
p3_rd_full => open,
p3_rd_empty => open,
p3_rd_count => open,
p3_rd_overflow => open,
p3_rd_error => open,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '0',
p4_cmd_clk => '0',
p4_cmd_en => '0',
p4_cmd_instr => (others => '0'),
p4_cmd_bl => (others => '0'),
p4_cmd_byte_addr => (others => '0'),
p4_cmd_empty => open,
p4_cmd_full => open,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => '0',
p4_wr_en => '0',
p4_wr_mask => (others => '0'),
p4_wr_data => (others => '0'),
p4_wr_full => open,
p4_wr_empty => open,
p4_wr_count => open,
p4_wr_underrun => open,
p4_wr_error => open,
p5_arb_en => '0',
p5_cmd_clk => '0',
p5_cmd_en => '0',
p5_cmd_instr => (others => '0'),
p5_cmd_bl => (others => '0'),
p5_cmd_byte_addr => (others => '0'),
p5_cmd_empty => open,
p5_cmd_full => open,
p5_rd_clk => '0',
p5_rd_en => '0',
p5_rd_data => open,
p5_rd_full => open,
p5_rd_empty => open,
p5_rd_count => open,
p5_rd_overflow => open,
p5_rd_error => open,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| cc0-1.0 | c9f2a5674423105b89463944cfd173db | 0.42396 | 3.506431 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/bram/hdl/bram.vhd | 1 | 1,980 | ---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 14/11/2008
-- File : bram.vhd
--
-- Abstract :
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity bram is
---------------------------------------------------------------------------
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_add : in std_logic_vector( 9 downto 0);
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture bram_1 of bram is
---------------------------------------------------------------------------
component xilinx_one_port_ram_async
generic (
ADDR_WIDTH : integer := 10;
DATA_WIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic ;
addr : in std_logic_vector( ADDR_WIDTH - 1 downto 0);
din : in std_logic_vector( DATA_WIDTH - 1 downto 0);
dout : out std_logic_vector( DATA_WIDTH - 1 downto 0)
);
end component xilinx_one_port_ram_async;
begin
ram : xilinx_one_port_ram_async
generic map (
ADDR_WIDTH => 10,
DATA_WIDTH => 16
)
port map (
clk => gls_clk,
we => wbs_write,
addr => wbs_add,
din => wbs_writedata,
dout => wbs_readdata
);
wbs_ack <= wbs_strobe;
end architecture bram_1;
| lgpl-2.1 | cb1b010755cbfdbffa77426b3f675360 | 0.442424 | 4.142259 | false | false | false | false |
xcthulhu/periphondemand | src/library/components/i2cocore/hdl/i2cocore_wb16.vhd | 1 | 4,559 | ---------------------------------------------------------------------------
-- Company : ARMades Systems
-- Author(s) : Fabien Marteau <[email protected]>
--
-- Creation Date : 16/04/2008
-- File : i2cocore_wb16.vhd
--
-- Abstract : A wrapper to include i2c open cores in
-- a 16bits data wishbone bus
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity i2cocore is
---------------------------------------------------------------------------
generic(
id : natural := 1;
wb_size : natural := 16
);
port
(
clk_i : in std_logic ; -- master clock input
rst_i : in std_logic ; -- asynchronous reset
adr_i : in std_logic_vector( 3 downto 0);
dat_i : in std_logic_vector( 15 downto 0);
dat_o : out std_logic_vector( 15 downto 0);
we_i : in std_logic ;
stb_i : in std_logic ;
ack_o : out std_logic ;
cyc_i : in std_logic;
inta_o: out std_logic ;
scl : inout std_logic ;
sda : inout std_logic
);
end entity i2cocore;
---------------------------------------------------------------------------
Architecture i2cocore_1 of i2cocore is
---------------------------------------------------------------------------
component wishbone_i2c_master
port (
-- wishbone signals
CLK_I : in std_logic; -- master clock input
RST_I : in std_logic := '0'; -- synchronous active high reset
nRESET : in std_logic := '1'; -- asynchronous active low reset
ADR_I : in std_logic_vector(1 downto 0); -- lower address bits
DAT_I : in std_logic_vector(15 downto 0); -- Databus input
DAT_O : out std_logic_vector(15 downto 0); -- Databus output
SEL_I : in std_logic_vector(1 downto 0); -- Byte select signals
WE_I : in std_logic; -- Write enable input
STB_I : in std_logic; -- Strobe signals / core select signal
CYC_I : in std_logic; -- Valid bus cycle input
ACK_O : out std_logic; -- Bus cycle acknowledge output
INTA_O : out std_logic; -- interrupt request output signal
-- I2C signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end component;
signal SCLi : std_logic ;
signal SCLo : std_logic ;
signal SDAi : std_logic ;
signal SDAo : std_logic ;
signal dataI : std_logic_vector( 15 downto 0);
signal dataO : std_logic_vector( 15 downto 0);
signal sel : std_logic_vector( 1 downto 0);
signal rst : std_logic ;
signal strobe : std_logic ;
begin
connect_wishbone_i2c_master : wishbone_i2c_master
port map (
-- wishbone signals
CLK_I => clk_i, -- master clock input
RST_I => '0', -- synchronous active high reset
NRESET => rst, -- asynchronous active low reset
ADR_I => adr_i(2 downto 1), -- lower address bits
DAT_I => dataI, -- Databus input
DAT_O => dataO, -- Databus output
SEL_I => sel, -- Byte select signals
WE_I => we_i, -- Write enable input
STB_I => strobe, -- Strobe signals/
-- core select signal
CYC_I => cyc_i, -- Valid bus cycle input
ACK_O => ack_o, -- Bus cycle acknowledge output
INTA_O => inta_o, -- interrupt request output signal
-- I2C signals
SCLi => SCLi, -- I2C clock line
SCLo => SCLo,
SDAi => SDAi, -- I2C data line
SDAo => SDAo
);
rst <= not rst_i;
-- controls
strobe <= stb_i when adr_i(3) = '0' else '0';
sel <= "01" when (adr_i(0) = '0') else "10";
-- write data
write_p : process (adr_i(0))
begin
if (adr_i(0) = '0') then
dataI <= "00000000"&dat_i(7 downto 0);
else
dataI <= dat_i(7 downto 0)&"00000000";
end if;
end process write_p;
-- read data
read_p : process (adr_i, stb_i)
begin
if stb_i = '1' then
if (adr_i(3) = '1') then
dat_o <= std_logic_vector( to_unsigned(id,wb_size));
elsif (adr_i(0) = '0') then
dat_o <= "00000000"&dataO(7 downto 0);
else
dat_o <= "00000000"&dataO(15 downto 8);
end if;
else
dat_o <= (others => '0');
end if;
end process read_p;
-- I2C bus
scl <= '0' when (SCLo = '0') else 'Z';
sda <= '0' when (SDAo = '0') else 'Z';
SCLi <= scl;
SDAi <= sda;
end architecture i2cocore_1;
| lgpl-2.1 | 8c16ee2704d945bd3b2e259e912e2d6c | 0.515025 | 3.399702 | false | false | false | false |
S0obi/SY23 | state_machine/state_machine.vhdl | 1 | 1,185 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity state_machine is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
state_input : in STD_LOGIC;
tc : out STD_LOGIC);
end state_machine;
architecture architecture_state_machine of state_machine is
type T_etat is (idle,edge,one);
signal next_state, state_reg : T_etat;
begin
state_reg_process: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state_reg <= idle;
else
state_reg <= next_state;
end if;
end if;
end process state_reg_process;
tc <= '1' when state_reg = edge else '0';
next_state_process: process(state_reg, state_input)
begin
next_state <= state_reg;
case state_reg is
when idle =>
if state_input = '1' then
next_state <= edge;
end if;
when edge =>
next_state <= one;
when one =>
if state_input = '0' then
next_state <= idle;
end if;
end case;
end process next_state_process;
end architecture_state_machine;
| gpl-2.0 | 80a6057e35898dd299f3edb0c80e4da2 | 0.577215 | 3.612805 | false | false | false | false |
aurabindo/altersync | get_freq.vhd | 1 | 1,718 | --------------------------------------------------------------------------------
--Author: Jay Aurabind
--Email : [email protected]
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_counter is
port ( DAT_O : out std_logic_vector(63 downto 0);
ERR_O : out std_logic; --This is '1' if the pulse freq is more than clk freq.
Pulse_I : in std_logic;
CLK_I : in std_logic
);
end pulse_counter;
architecture Behavioral of pulse_counter is
signal Curr_Count,Prev_Count : std_logic_vector(63 downto 0):=(others => '0');
begin
--Increment Curr_Count every clock cycle.This is the max freq which can be measured by the module.
process(CLK_I)
begin
if( CLK_I'event and CLK_I='1' ) then
Curr_Count <= Curr_Count + 1;
end if;
end process;
--Calculate the time period of the pulse input using the current and previous counts.
process(Pulse_I)
begin
if( Pulse_I'event and Pulse_I = '1' ) then
--These different conditions eliminate the count overflow problem
--which can happen once the module is run for a long time.
if( Prev_Count < Curr_Count ) then
DAT_O <= Curr_Count - Prev_Count;
ERR_O <= '0';
elsif( Prev_Count > Curr_Count ) then
--X"F_F" is same as "1111_1111".
--'_' is added for readability.
DAT_O <= X"1_0000_0000_0000" - Prev_Count + Curr_Count;
ERR_O <= '0';
else
DAT_O <= (others => '0');
ERR_O <= '1'; --Error bit is inserted here.
end if;
Prev_Count <= Curr_Count; --Re-setting the Prev_Count.
end if;
end process;
end Behavioral;
| lgpl-3.0 | 2bf71ce321ca3977f816e7bff9216a8b | 0.588475 | 3.375246 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/MSPAC_ROM/synth/MSPAC_ROM.vhd | 1 | 13,915 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY MSPAC_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MSPAC_ROM;
ARCHITECTURE MSPAC_ROM_arch OF MSPAC_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MSPAC_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF MSPAC_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF MSPAC_ROM_arch : ARCHITECTURE IS "MSPAC_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF MSPAC_ROM_arch: ARCHITECTURE IS "MSPAC_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=MSPAC_ROM.mif,C_INIT_FILE=MSPAC_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "MSPAC_ROM.mif",
C_INIT_FILE => "MSPAC_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END MSPAC_ROM_arch;
| gpl-2.0 | 27ae4934a7942ab9a8e7f711087cc559 | 0.624793 | 3.025658 | false | false | false | false |
545/Atari7800 | tia/sound_interface/i2s_data_interface.vhd | 3 | 3,303 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: i2s_data_interface - Behavioral
-- Description: Send & Receive I2S data
-- New_sample is asserted for one cycle when a new sample has been
-- received (and one transmitted)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2s_data_interface is
Port ( clk : in STD_LOGIC;
audio_l_in : in STD_LOGIC_VECTOR (15 downto 0);
audio_r_in : in STD_LOGIC_VECTOR (15 downto 0);
audio_l_out : out STD_LOGIC_VECTOR (15 downto 0);
audio_r_out : out STD_LOGIC_VECTOR (15 downto 0);
new_sample : out STD_LOGIC;
i2s_bclk : in STD_LOGIC;
i2s_d_out : out STD_LOGIC;
i2s_d_in : in STD_LOGIC;
i2s_lr : in STD_LOGIC);
end i2s_data_interface;
architecture Behavioral of i2s_data_interface is
signal bit_counter : unsigned(5 downto 0) := (others => '0');
signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0');
signal lr_delay : std_logic_vector(9 downto 0) := (others => '0');
signal sr_in : std_logic_vector(126 downto 0) := (others => '0');
signal sr_out : std_logic_vector(63 downto 0) := (others => '0');
signal i2s_lr_last : std_logic := '0';
signal i2s_d_in_last : std_logic := '0';
begin
process(clk)
begin
-- Process to predict when the falling edge of i2s_bclk should be
if rising_edge(clk) then
new_sample <= '0';
------------------------------
-- is there a rising edge two cycles ago? If so the data bit is
-- validand we can capture a bit
------------------------------
if bclk_delay(bclk_delay'high-1 downto bclk_delay'high-2) = "10" then
sr_in <= sr_in(sr_in'high-1 downto 0) & i2s_d_in_last;
end if;
------------------------------
-- Was there a rising edge on BCLK 9 cycles ago?
-- If so, this should be about the falling edge so
-- the output can change.
------------------------------
if bclk_delay(1 downto 0) = "10" then
i2s_d_out <= sr_out(sr_out'high);
-- if we are starting a new frame, then load the samples into the shift register
if i2s_lr = '1' and i2s_lr_last = '0' then
audio_l_out <= sr_in(sr_in'high downto sr_in'high-15);
audio_r_out <= sr_in(sr_in'high-32 downto sr_in'high-15-32);
sr_out <= audio_l_in & x"0000" & audio_r_in & x"0000";
new_sample <= '1';
else
sr_out <= sr_out(sr_out'high-1 downto 0) & '0';
end if;
-- remember what lr was, for edge detection
i2s_lr_last <= i2s_lr;
end if;
bclk_delay <= i2s_bclk & bclk_delay(bclk_delay'high downto 1);
i2s_d_in_last <= i2s_d_in;
end if;
end process;
end Behavioral; | gpl-2.0 | 64296001b77eb11db39fd65e95f1ffdc | 0.480472 | 3.617744 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/FOODFIGHT_ROM/synth/FOODFIGHT_ROM.vhd | 1 | 13,975 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY FOODFIGHT_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FOODFIGHT_ROM;
ARCHITECTURE FOODFIGHT_ROM_arch OF FOODFIGHT_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FOODFIGHT_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FOODFIGHT_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FOODFIGHT_ROM_arch : ARCHITECTURE IS "FOODFIGHT_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FOODFIGHT_ROM_arch: ARCHITECTURE IS "FOODFIGHT_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FOODFIGHT_ROM.mif,C_INIT_FILE=FOODFIGHT_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FOODFIGHT_ROM.mif",
C_INIT_FILE => "FOODFIGHT_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FOODFIGHT_ROM_arch;
| gpl-2.0 | 4ef1cf6f73e7a9e386237798b281388c | 0.626404 | 3.038704 | false | false | false | false |
freecores/spi_boot | bench/vhdl/tb_rl.vhd | 1 | 7,766 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Testbench for ram_loader
--
-- $Id: tb_rl.vhd,v 1.1 2005-04-10 18:07:25 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
entity tb_rl is
end tb_rl;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_rl is
component chip
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_n_i : in std_logic_vector(3 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
component card
generic (
card_type_g : string := "none";
is_sd_card_g : integer := 1
);
port (
spi_clk_i : in std_logic;
spi_cs_n_i : in std_logic;
spi_data_i : in std_logic;
spi_data_o : out std_logic
);
end component;
component ram_loader
port (
clk_i : in std_logic;
reset_i : in std_logic;
lamp_o : out std_logic;
cfg_clk_i : in std_logic;
cfg_data_i : in std_logic;
start_o : out std_logic;
mode_o : out std_logic;
done_o : out std_logic;
detached_i : in std_logic;
ram_addr_o : out std_logic_vector(15 downto 0);
ram_data_b : out std_logic_vector( 7 downto 0);
ram_ce_no : out std_logic_vector( 3 downto 0);
ram_oe_no : out std_logic;
ram_we_no : out std_logic
);
end component;
constant period_c : time := 100 ns;
constant rl_period_c : time := 20 ns;
constant reset_level_c : integer := 0;
signal clk_s : std_logic;
signal rl_clk_s: std_logic;
signal reset_s : std_logic;
-- SPI interface signals
signal spi_clk_s : std_logic;
signal spi_data_to_card_s : std_logic;
signal spi_data_from_card_s : std_logic;
signal spi_cs_n_s : std_logic;
-- config related signals
signal start_s : std_logic;
signal mode_s : std_logic;
signal config_n_s : std_logic;
signal cfg_init_n_s : std_logic;
signal cfg_done_s : std_logic;
signal dat_done_s : std_logic;
signal cfg_clk_s : std_logic;
signal cfg_dat_s : std_logic;
signal detached_s : std_logic;
signal set_sel_n_s : std_logic_vector(3 downto 0);
begin
set_sel_n_s <= (others => '1');
cfg_init_n_s <= '1';
cfg_done_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
dut_b : chip
port map (
clk_i => clk_s,
reset_i => reset_s,
set_sel_n_i => set_sel_n_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_from_card_s,
spi_data_out_o => spi_data_to_card_s,
start_i => start_s,
mode_i => mode_s,
config_n_o => config_n_s,
detached_o => detached_s,
cfg_init_n_i => cfg_init_n_s,
cfg_done_i => cfg_done_s,
dat_done_i => dat_done_s,
cfg_clk_o => cfg_clk_s,
cfg_dat_o => cfg_dat_s
);
card_b : card
generic map (
card_type_g => "Full Chip",
is_sd_card_g => 1
)
port map (
spi_clk_i => spi_clk_s,
spi_cs_n_i => spi_cs_n_s,
spi_data_i => spi_data_to_card_s,
spi_data_o => spi_data_from_card_s
);
rl_b : ram_loader
port map (
clk_i => rl_clk_s,
reset_i => reset_s,
lamp_o => open,
cfg_clk_i => cfg_clk_s,
cfg_data_i => cfg_dat_s,
start_o => start_s,
mode_o => mode_s,
done_o => dat_done_s,
detached_i => detached_s,
ram_addr_o => open,
ram_data_b => open,
ram_ce_no => open,
ram_oe_no => open,
ram_we_no => open
);
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clk: process
begin
clk_s <= '0';
wait for period_c / 2;
clk_s <= '1';
wait for period_c / 2;
end process clk;
rl_clk: process
begin
rl_clk_s <= '0';
wait for rl_period_c / 2;
rl_clk_s <= '1';
wait for rl_period_c / 2;
end process rl_clk;
-----------------------------------------------------------------------------
-- Reset Generator
-----------------------------------------------------------------------------
reset: process
begin
if reset_level_c = 0 then
reset_s <= '0';
else
reset_s <= '1';
end if;
wait for period_c * 4 + 10 ns;
reset_s <= not reset_s;
wait;
end process reset;
-----------------------------------------------------------------------------
-- End of Simulation
-----------------------------------------------------------------------------
eos: process
begin
wait for 4 ms;
assert false
report "No checks have been performed. Investigate waveforms."
severity note;
assert false
report "End of simulation."
severity failure;
end process eos;
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 4c7ae37a4bb5cd1c1f4ca429467a9515 | 0.516353 | 3.634066 | false | false | false | false |
545/Atari7800 | core/cpu6502_true_cycle/tags/arelease/rtl/vhdl/core.vhd | 2 | 14,532 | -- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:05 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity Core is
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector (7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
d_o : out std_logic_vector (7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
-- Declarations
end Core ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
-- 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Core
-- Path: R6502_TC/Core/struct
-- Edited: by eda on 04 Jan 2009
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:43:06 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
library R6502_TC;
architecture struct of Core is
-- Architecture declarations
-- Internal signal declarations
signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
signal adr_o_i : std_logic_vector(15 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal adr_sp_o_i : std_logic_vector(15 downto 0);
signal ch_a_o_i : std_logic_vector(7 downto 0);
signal ch_b_o_i : std_logic_vector(7 downto 0);
signal d_alu_n_o_i : std_logic;
signal d_alu_o_i : std_logic_vector(7 downto 0);
signal d_alu_or_o_i : std_logic;
signal d_regs_in_o_i : std_logic_vector(7 downto 0);
signal d_regs_out_o_i : std_logic_vector(7 downto 0);
signal fetch_o_i : std_logic;
signal ld_o_i : std_logic_vector(1 downto 0);
signal ld_pc_o_i : std_logic;
signal ld_sp_o_i : std_logic;
signal load_regs_o_i : std_logic;
signal nmi_o_i : std_logic;
signal offset_o_i : std_logic_vector(15 downto 0);
signal q_a_o_i : std_logic_vector(7 downto 0);
signal q_x_o_i : std_logic_vector(7 downto 0);
signal q_y_o_i : std_logic_vector(7 downto 0);
signal reg_0flag_o_i : std_logic;
signal reg_1flag_o_i : std_logic;
signal reg_7flag_o_i : std_logic;
signal sel_pc_as_o_i : std_logic;
signal sel_pc_in_o_i : std_logic;
signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
signal sel_reg_o_i : std_logic_vector(1 downto 0);
signal sel_sp_as_o_i : std_logic;
signal sel_sp_in_o_i : std_logic;
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
-- Component Declarations
component FSM_Execution_Unit
port (
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic ;
nmi_i : in std_logic ;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic ;
reg_0flag_i : in std_logic ;
reg_1flag_i : in std_logic ;
reg_7flag_i : in std_logic ;
rst_rst_n_i : in std_logic ;
so_n_i : in std_logic ;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
fetch_o : out std_logic ;
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic ;
ld_sp_o : out std_logic ;
load_regs_o : out std_logic ;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic ;
sel_pc_as_o : out std_logic ;
sel_pc_in_o : out std_logic ;
sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
sel_reg_o : out std_logic_vector ( 1 downto 0 );
sel_sp_as_o : out std_logic ;
sel_sp_in_o : out std_logic ;
sync_o : out std_logic ;
wr_n_o : out std_logic ;
wr_o : out std_logic
);
end component;
component FSM_NMI
port (
clk_clk_i : in std_logic ;
fetch_i : in std_logic ;
nmi_n_i : in std_logic ;
rst_rst_n_i : in std_logic ;
nmi_o : out std_logic
);
end component;
component RegBank_AXY
port (
clk_clk_i : in std_logic ;
d_regs_in_i : in std_logic_vector (7 downto 0);
load_regs_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_rb_in_i : in std_logic_vector (1 downto 0);
sel_rb_out_i : in std_logic_vector (1 downto 0);
sel_reg_i : in std_logic_vector (1 downto 0);
d_regs_out_o : out std_logic_vector (7 downto 0);
q_a_o : out std_logic_vector (7 downto 0);
q_x_o : out std_logic_vector (7 downto 0);
q_y_o : out std_logic_vector (7 downto 0)
);
end component;
component Reg_PC
port (
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic ;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic ;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic ;
sel_pc_as_i : in std_logic ;
sel_pc_in_i : in std_logic ;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
end component;
component Reg_SP
port (
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic ;
ld_low_i : in std_logic ;
ld_sp_i : in std_logic ;
rst_rst_n_i : in std_logic ;
sel_sp_as_i : in std_logic ;
sel_sp_in_i : in std_logic ;
adr_sp_o : out std_logic_vector (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit;
for all : FSM_NMI use entity R6502_TC.FSM_NMI;
for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
for all : Reg_PC use entity R6502_TC.Reg_PC;
for all : Reg_SP use entity R6502_TC.Reg_SP;
-- pragma synthesis_on
begin
-- ModuleWare code(v1.9) for instance 'U_11' of 'add'
mw_U_11temp_din0 <= '0' & ch_a_o_i;
mw_U_11temp_din1 <= '0' & ch_b_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1)
variable temp_carry : std_logic;
begin
temp_carry := '0';
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
end process u_11combo_proc;
d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
reg_0flag_o_i <= mw_U_11sum(8) ;
-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
reg_1flag_o_i <= not(d_alu_or_o_i);
-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
reg_7flag_o_i <= not(d_alu_n_o_i);
-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
d_alu_n_o_i <= not(d_alu_o_i(7));
-- ModuleWare code(v1.9) for instance 'U_7' of 'por'
d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
-- Instance port mappings.
U_4 : FSM_Execution_Unit
port map (
adr_nxt_pc_i => adr_nxt_pc_o_i,
adr_pc_i => adr_pc_o_i,
adr_sp_i => adr_sp_o_i,
clk_clk_i => clk_clk_i,
d_alu_i => d_alu_o_i,
d_i => d_i,
d_regs_out_i => d_regs_out_o_i,
irq_n_i => irq_n_i,
nmi_i => nmi_o_i,
q_a_i => q_a_o_i,
q_x_i => q_x_o_i,
q_y_i => q_y_o_i,
rdy_i => rdy_i,
reg_0flag_i => reg_0flag_o_i,
reg_1flag_i => reg_1flag_o_i,
reg_7flag_i => reg_7flag_o_i,
rst_rst_n_i => rst_rst_n_i,
so_n_i => so_n_i,
a_o => a_o,
adr_o => adr_o_i,
ch_a_o => ch_a_o_i,
ch_b_o => ch_b_o_i,
d_o => d_o,
d_regs_in_o => d_regs_in_o_i,
fetch_o => fetch_o_i,
ld_o => ld_o_i,
ld_pc_o => ld_pc_o_i,
ld_sp_o => ld_sp_o_i,
load_regs_o => load_regs_o_i,
offset_o => offset_o_i,
rd_o => rd_o,
sel_pc_as_o => sel_pc_as_o_i,
sel_pc_in_o => sel_pc_in_o_i,
sel_pc_val_o => sel_pc_val_o_i,
sel_rb_in_o => sel_rb_in_o_i,
sel_rb_out_o => sel_rb_out_o_i,
sel_reg_o => sel_reg_o_i,
sel_sp_as_o => sel_sp_as_o_i,
sel_sp_in_o => sel_sp_in_o_i,
sync_o => sync_o,
wr_n_o => wr_n_o,
wr_o => wr_o
);
U_6 : FSM_NMI
port map (
clk_clk_i => clk_clk_i,
fetch_i => fetch_o_i,
nmi_n_i => nmi_n_i,
rst_rst_n_i => rst_rst_n_i,
nmi_o => nmi_o_i
);
U_2 : RegBank_AXY
port map (
clk_clk_i => clk_clk_i,
d_regs_in_i => d_regs_in_o_i,
load_regs_i => load_regs_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_rb_in_i => sel_rb_in_o_i,
sel_rb_out_i => sel_rb_out_o_i,
sel_reg_i => sel_reg_o_i,
d_regs_out_o => d_regs_out_o_i,
q_a_o => q_a_o_i,
q_x_o => q_x_o_i,
q_y_o => q_y_o_i
);
U_0 : Reg_PC
port map (
adr_i => adr_o_i,
clk_clk_i => clk_clk_i,
ld_i => ld_o_i,
ld_pc_i => ld_pc_o_i,
offset_i => offset_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_pc_as_i => sel_pc_as_o_i,
sel_pc_in_i => sel_pc_in_o_i,
sel_pc_val_i => sel_pc_val_o_i,
adr_nxt_pc_o => adr_nxt_pc_o_i,
adr_pc_o => adr_pc_o_i
);
U_1 : Reg_SP
port map (
adr_low_i => adr_o_i(7 DOWNTO 0),
clk_clk_i => clk_clk_i,
ld_low_i => ld_o_i(0),
ld_sp_i => ld_sp_o_i,
rst_rst_n_i => rst_rst_n_i,
sel_sp_as_i => sel_sp_as_o_i,
sel_sp_in_i => sel_sp_in_o_i,
adr_sp_o => adr_sp_o_i
);
end struct;
| gpl-2.0 | 56f0eff5a3051faa71e8acf44350a7be | 0.444949 | 3.136629 | false | false | false | false |
545/Atari7800 | maria/maria.srcs/sources_1/ip/dll_img_ram/dll_img_ram_funcsim.vhdl | 1 | 347,610 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Fri Oct 16 15:22:50 2015
-- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
-- Command : write_vhdl -force -mode funcsim
-- /afs/ece.cmu.edu/usr/cmbarker/Private/Atari7800/maria/maria.srcs/sources_1/ip/dll_img_ram/dll_img_ram_funcsim.vhdl
-- Design : dll_img_ram
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end dll_img_ram_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of dll_img_ram_blk_mem_gen_prim_wrapper_init is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "NONE",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 1),
DOADO(0) => douta(0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end dll_img_ram_blk_mem_gen_prim_width;
architecture STRUCTURE of dll_img_ram_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.dll_img_ram_blk_mem_gen_prim_wrapper_init
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \dll_img_ram_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \dll_img_ram_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \dll_img_ram_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \dll_img_ram_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\dll_img_ram_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end dll_img_ram_blk_mem_gen_generic_cstr;
architecture STRUCTURE of dll_img_ram_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.dll_img_ram_blk_mem_gen_prim_width
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized0\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(1),
douta(0) => douta(1),
ena => ena,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized1\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(2),
douta(0) => douta(2),
ena => ena,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized2\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(3),
douta(0) => douta(3),
ena => ena,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized3\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(4),
douta(0) => douta(4),
ena => ena,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized4\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(5),
douta(0) => douta(5),
ena => ena,
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized5\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(6),
douta(0) => douta(6),
ena => ena,
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\dll_img_ram_blk_mem_gen_prim_width__parameterized6\
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(0) => dina(7),
douta(0) => douta(7),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_top : entity is "blk_mem_gen_top";
end dll_img_ram_blk_mem_gen_top;
architecture STRUCTURE of dll_img_ram_blk_mem_gen_top is
begin
\valid.cstr\: entity work.dll_img_ram_blk_mem_gen_generic_cstr
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end dll_img_ram_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of dll_img_ram_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.dll_img_ram_blk_mem_gen_top
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram_blk_mem_gen_v8_2 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 15 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 16;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 16;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of dll_img_ram_blk_mem_gen_v8_2 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of dll_img_ram_blk_mem_gen_v8_2 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of dll_img_ram_blk_mem_gen_v8_2 : entity is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of dll_img_ram_blk_mem_gen_v8_2 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of dll_img_ram_blk_mem_gen_v8_2 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of dll_img_ram_blk_mem_gen_v8_2 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of dll_img_ram_blk_mem_gen_v8_2 : entity is "Estimated Power for IP : 16.114201 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of dll_img_ram_blk_mem_gen_v8_2 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of dll_img_ram_blk_mem_gen_v8_2 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of dll_img_ram_blk_mem_gen_v8_2 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of dll_img_ram_blk_mem_gen_v8_2 : entity is "dll_img_ram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of dll_img_ram_blk_mem_gen_v8_2 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of dll_img_ram_blk_mem_gen_v8_2 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of dll_img_ram_blk_mem_gen_v8_2 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of dll_img_ram_blk_mem_gen_v8_2 : entity is "NONE";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of dll_img_ram_blk_mem_gen_v8_2 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of dll_img_ram_blk_mem_gen_v8_2 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 65536;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of dll_img_ram_blk_mem_gen_v8_2 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of dll_img_ram_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of dll_img_ram_blk_mem_gen_v8_2 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of dll_img_ram_blk_mem_gen_v8_2 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of dll_img_ram_blk_mem_gen_v8_2 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dll_img_ram_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dll_img_ram_blk_mem_gen_v8_2 : entity is "yes";
end dll_img_ram_blk_mem_gen_v8_2;
architecture STRUCTURE of dll_img_ram_blk_mem_gen_v8_2 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.dll_img_ram_blk_mem_gen_v8_2_synth
port map (
addra(15 downto 0) => addra(15 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dll_img_ram is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dll_img_ram : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dll_img_ram : entity is "dll_img_ram,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of dll_img_ram : entity is "dll_img_ram,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=0,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=dll_img_ram.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=65536,C_READ_DEPTH_A=65536,C_ADDRA_WIDTH=16,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=65536,C_READ_DEPTH_B=65536,C_ADDRB_WIDTH=16,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=NONE,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=1,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=1,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.114201 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dll_img_ram : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dll_img_ram : entity is "blk_mem_gen_v8_2,Vivado 2015.2";
end dll_img_ram;
architecture STRUCTURE of dll_img_ram is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 16;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 16;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 0;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 1;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 1;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 16.114201 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "dll_img_ram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 65536;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 65536;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "NONE";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 65536;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 65536;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.dll_img_ram_blk_mem_gen_v8_2
port map (
addra(15 downto 0) => addra(15 downto 0),
addrb(15) => '0',
addrb(14) => '0',
addrb(13) => '0',
addrb(12) => '0',
addrb(11) => '0',
addrb(10) => '0',
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(15 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(15 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(15 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(15 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-2.0 | 0943d8484a9b641ee8b742a70a5348b2 | 0.715552 | 4.81261 | false | false | false | false |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_funcsim.vhdl | 1 | 53,410 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sat Oct 31 15:04:15 2015
-- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
-- Command : write_vhdl -force -mode funcsim
-- /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_funcsim.vhdl
-- Design : BIOS_ROM
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end BIOS_ROM_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00F46C48",
INIT_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFD2DFFFCADF410CA88EAD0FD80D9FE00BD7FA2FFA0018516A926C24C26C24C",
INIT_21 => X"F9ADC5D0F029F049FFF8ADCED0FFC9FE09FFF8ADD4F0FFFD0DFFFCADDCF0FFC9",
INIT_22 => X"A9253620A7B0FFFDCD01E9AE9040C924068DEE85F029FFF9ADBCD003C90B29FF",
INIT_23 => X"D0F8C088180099FF00B97FA048FAD0CA18009D8A00A2018516A9241B20F08500",
INIT_24 => X"241B20EED0FFC92406AD2406EE4823FF2068241B20240A8D24A924098D2EA9F5",
INIT_25 => X"06AD2406CE4823FF2068241B202406CE240A8D24A924098D36A9241220241220",
INIT_26 => X"8D07291A00ADF110CA1A009D18885D18505D1800BD77A23C8560A9EEB0EEC524",
INIT_27 => X"A226C24C26B94CF510CA06D01A00DD2000BD77A220009D1A009D04A200A91A00",
INIT_28 => X"0C10F0C60860FAD0E818003E00A260F0D0E818009D2DD5B9A8FF007D18007D00",
INIT_29 => X"918E5572B6626792D0E10983F7EECAAB65C76028018516A9FC30F0A5018502A9",
INIT_2A => X"EDB890FA94A38734FC17A98473FBD1383108C8AF45063DE6B7592078BE81C5DC",
INIT_2B => X"EC352656F6E3E741807FE4BC1011B9A7519D605A6D0DB38253F3D9430A5B3BCE",
INIT_2C => X"3E022B7718805805B18C42B01C4A971513A43FA2BFCFEF4652AC9EF47F0CDFD6",
INIT_2D => X"93DE0307F94B2EE80E762D2AF819579B9FD88B79144FF1EB8A0B6ECB6A1A49A8",
INIT_2E => X"C02F0FAD9689AA391FFE85361E2295A0235EE01DCCA1D2DA7A7DF0B2E5D47E16",
INIT_2F => X"54BD9986BB752C7B33D770A6CD7CC1DD2574AE8F401B5F21F5A5C3EA245D2747",
INIT_30 => X"440164DB3A88C2E94D04E26B69D59C98C61237294EC4615CBA8D4C4832636C9A",
INIT_31 => X"9DFF80BDE586E48677A2EE0965F7ABC783CAD3C96866B43C7150FD2830F2B56F",
INIT_32 => X"10CA19019DFED5BDE48677A2F2C6257B20FB8420018502A9F410CA20009D1901",
INIT_33 => X"E5A426392060F710CA20009D1800BD77A225728DE0A5F2C625E120E385E1A5F7",
INIT_34 => X"7C8C26748C266E8CC818008DFAD0CA18009D26718D00A9AA48E2651898E184C8",
INIT_35 => X"09F025D93D2000B9E1A41B30E1C62681CE267CCE2674CE266ECE00A226818C26",
INIT_36 => X"4020100804020160E08501A9E1856825A44CE83008E0E8266A2026728D2662BD",
INIT_37 => X"8E268C8E26A98ECA26AC8E268F8E18008E00A2E185E085E4E538E3A526392080",
INIT_38 => X"2662BD1730E1C6269FEE269AEE2692EE268CEE26A9EE07A2269F8E269A8E2692",
INIT_39 => X"00A0E286E8E4A660E185E3A526084CEC10CA268820039026A62026AD8D26908D",
INIT_3A => X"3007C0F610CA19009D2A1900BD18E2A626598D2662B9C826558D2662B919008C",
INIT_3B => X"00691700B90C90F410881800991900791800B918E2A4211F1E1D1C1B1A1960E2",
INIT_3C => X"009900E91700B90CB0F410881800991900F91800B938E2A46026794C88170099",
INIT_3D => X"6CF89A018616A226A84CC8FBF0E2C46001F01900D91800B900A06026974C8817",
INIT_3E => X"F9D02AE0E803950185AA00A904804CF710CA04809DF7D4BD7FA2018502A9FFFC",
INIT_3F => X"85EA0F851C851B85118504CB2004CB2001108D9AFD10CA04A22330EA04A90285",
INIT_40 => X"608DF1188D068502A90C3002241ED0F1128D098502A9093003240430EA00A902",
INIT_41 => X"FFFFFFFFFFFFFFEAFFFC6C0885FDA9D9300224EA04CB201B8508A92C850ED0F4",
INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_44 => X"A0F91DBD05A2208500A93C857FA9F48512A9F585FBA9018502A9D87801851DA9",
INIT_45 => X"0BD080C520808D43A9E510CAEDD0881FD02100D921009927D02000D920009900",
INIT_46 => X"4C02A0F8804C01A00AD01800CD18008DF8804C04A0F9384C03D00180CD21808D",
INIT_47 => X"F91DBD05A2F385F92BB9F185F923B9F48407A0F285F08500A9F8804C03A0F880",
INIT_48 => X"55FF00FB174CD710F4A4F4C6E910CAF1D088CFD0F2D1F291D0D0F0D1F09100A0",
INIT_49 => X"0330F510F7F0AAA9F8804C00A01F1E1D1C1B1A191823222726252423220F69AA",
INIT_4A => X"00C9F9334C03F0F9334C0310DF30E1D000A9E5D0AAC5AA85F9334C03D0F9334C",
INIT_4B => X"B3D001AAEC01AA8EBBF056E055A2F9334C0390C6B001C9F9334C03B0CF90D1D0",
INIT_4C => X"AAC9984ED00155EC488A55D0AAC968E89ACAA5D00155CC01558CADF0ABC0AAA4",
INIT_4D => X"00D92DD055C5000099FF4936D0AAC93AD0AAC500B540D055C0A80100BDAA49D0",
INIT_4E => X"85EEA90ED02121CDF09115D0CCC54681F085CCA9F18520A923D020ABDD28D001",
INIT_4F => X"5569EDD0AAC9F1F0F310F5B0EA55691855A9F9334CF9EB4C00F06CF185F9A9F0",
INIT_50 => X"E8AAFFA9CFD0D130D390AAE918D8D0ABC9DCF0DE10E0B055E9E4D0E630E890EA",
INIT_51 => X"C619D0F0C41DD0F0E6F08523D0C826F08829D0C8A82DD0FFE0311033F0CA36D0",
INIT_52 => X"B00AFA900AF9334C03F0AAC96A6A6A07D052C92A2A2A18AAA911D0F0C515F0F0",
INIT_53 => X"C91B295529DDD05FC91B0955A9E5D00AC94AEAB04AED904A0549F2D050C90AF7",
INIT_54 => X"B8D0FAC968BDD08DC968C2D052E0BAFA584CFA9120CDD04EC91B495509D5D011",
INIT_55 => X"2485248502100650F3242285EFA50FA23C8543A9488AFA584C6048E6A948F8A9",
INIT_56 => X"0609F029EFA527850E09F0293C8640A2EC10CA22850FE902B010C910E9382485",
INIT_57 => X"0290106918EFA511906069F3A51910F1C6268503090F690290406918F0292585",
INIT_58 => X"E80195AA00A99AFFA2FB144C4068AA68F08502A9F38500A9F185F2A5EF850F69",
INIT_59 => X"00BD25009DF600BD24009DF500BD23009DF400BD208600A2018502A9F9D02CE0",
INIT_5A => X"19849DFCC6BD1F849DFC4BBD2A3000E022009DFBBEBD27009DF800BD26009DF7",
INIT_5B => X"D0CA1E849DFE96BD1D849DFE57BD1C849DFE18BD1B849DFDB4BD1A849DFD3DBD",
INIT_5C => X"852EA9268556A9258566A9EF8549A9F285F18503A932F00429FFF9AD23064CAB",
INIT_5D => X"1F84603C8543A92C851FA9308584A9FC102824FC302824F585FAA9F485AAA927",
INIT_5E => X"191B91000048191C8D00004A191C8900004A191C850000BB1F1940840000BB19",
INIT_5F => X"AF0000501C2CAF001C2CAF00003E1917A600003E19179D000042191996000046",
INIT_60 => X"0028192DE8000028192DD5000028192DC2000028192DAF0000501D2CAF001D2C",
INIT_61 => X"C20000281B2DAF0000281A2DE80000281A2DD50000281A2DC20000281A2DAF00",
INIT_62 => X"1322050D228500220300220F00220F00220F06220F0000281B2DD50000281B2D",
INIT_63 => X"22025122003722024B220037220100220F3122052B22052522051F2205192205",
INIT_64 => X"003722026F22003722026922003722026322003722025D220037220257220037",
INIT_65 => X"00220F00220F00220F4122018722003722028122003722027B22003722027522",
INIT_66 => X"1FF87F807F80FF07FC817FE00F7EF8871FC08F7FFC808F7F7C0000220F00220F",
INIT_67 => X"FF3F0000C000F0FFFFFF3F000C00003E0000807F0000001FFEFF03807F00F0FF",
INIT_68 => X"0000FF0300C0FF0000FC03FCFFFF3F0000F003F0FFFFFF3F003F0000FC0300FF",
INIT_69 => X"7F7C00FCC33F00F03F0000FF3F0000FF0300F0FF0300FCC3FF03F03F0000FC0F",
INIT_6A => X"1FFEFF07807F00F8FF1FE07F807F80FF01FC837FF00F7EF8871F808F7F7C808F",
INIT_6B => X"00FFC03F00FCC3FF00F03F00C03FFF0000FF0300FCF30F00FE0300807F0000F0",
INIT_6C => X"03C0FFF03F00FC03F00F00FF03C03F00FF00FC03FC3FF03F00F00FFC0300FF03",
INIT_6D => X"F8871F808F7F7C808F7F7C00FC03F03FF03F00FFFFFF3F00FF03F0FFFFFF03FC",
INIT_6E => X"0FFE0F00807F0000FC1FFEFF0F807F00FCFF1FC0FF807FC0FF00F8837FF0077E",
INIT_6F => X"3FF03F0000FF03FF03FF0300F03FFC03FC0FF03FC0FFFFFFFF00FF03FCFFFFFF",
INIT_70 => X"8F7F7C808F7F7C00FCC3FF00F03FFC0F0000FC0FFFC3FF0000C0FFFC03FF03F0",
INIT_71 => X"807F0000FF1FFEFF1F807F00FEFF1F80FF807FC07F00F8837FF0077CF8870F80",
INIT_72 => X"808F7F7C808F7F7C005555555555555555555555555555555555555555FE3F00",
INIT_73 => X"00807F00C0FF1FE0FF1F807F00FEFF0100FF817FE03F00F0837FF003FCF8C70F",
INIT_74 => X"0F808F7F7C808F7F7C00AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAFEFF",
INIT_75 => X"FF01807F00E0FF1F00FE3F807F00FF1F0000FE817FE01F00F0877FF803FCF8C7",
INIT_76 => X"8158601B0812B4C6C9CA095555555555555555555555555555555555555555FE",
INIT_77 => X"9306CD8A2DAFECC53B000A8DFAE2E22FBC7C3B847932DC7BA025D9BFD801864B",
INIT_78 => X"C855510C4723EF20B5066DF7E873D37168A20CCE8CEF3653B26AC4774614A56A",
INIT_79 => X"BD870A801D8F71B388CC222D3B583CF86305D8C4E276B03867A7203FC458F4FE",
INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA3942806846ECD3E270E92359A1",
INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_7F => X"F933F884F000F72D34383931294328434347FFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end BIOS_ROM_blk_mem_gen_prim_width;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.BIOS_ROM_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end BIOS_ROM_blk_mem_gen_generic_cstr;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.BIOS_ROM_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_top : entity is "blk_mem_gen_top";
end BIOS_ROM_blk_mem_gen_top;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_top is
begin
\valid.cstr\: entity work.BIOS_ROM_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end BIOS_ROM_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.BIOS_ROM_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM_blk_mem_gen_v8_2 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of BIOS_ROM_blk_mem_gen_v8_2 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of BIOS_ROM_blk_mem_gen_v8_2 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of BIOS_ROM_blk_mem_gen_v8_2 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of BIOS_ROM_blk_mem_gen_v8_2 : entity is "Estimated Power for IP : 2.535699 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of BIOS_ROM_blk_mem_gen_v8_2 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of BIOS_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of BIOS_ROM_blk_mem_gen_v8_2 : entity is "BIOS_ROM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of BIOS_ROM_blk_mem_gen_v8_2 : entity is "BIOS_ROM.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of BIOS_ROM_blk_mem_gen_v8_2 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of BIOS_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of BIOS_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of BIOS_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of BIOS_ROM_blk_mem_gen_v8_2 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of BIOS_ROM_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of BIOS_ROM_blk_mem_gen_v8_2 : entity is "yes";
end BIOS_ROM_blk_mem_gen_v8_2;
architecture STRUCTURE of BIOS_ROM_blk_mem_gen_v8_2 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.BIOS_ROM_blk_mem_gen_v8_2_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity BIOS_ROM is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of BIOS_ROM : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of BIOS_ROM : entity is "BIOS_ROM,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of BIOS_ROM : entity is "BIOS_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=BIOS_ROM.mif,C_INIT_FILE=BIOS_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.535699 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of BIOS_ROM : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of BIOS_ROM : entity is "blk_mem_gen_v8_2,Vivado 2015.2";
end BIOS_ROM;
architecture STRUCTURE of BIOS_ROM is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.535699 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "BIOS_ROM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "BIOS_ROM.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.BIOS_ROM_blk_mem_gen_v8_2
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11) => '0',
addrb(10) => '0',
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| gpl-2.0 | 37d7d1f5a453a786f6f970c86a8ec02e | 0.671391 | 2.906192 | false | false | false | false |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/imports/dsp_base_project/adau1761_test.vhd | 1 | 4,275 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 19:23:40 01/06/2014
-- Module Name: adau1761_test - Behavioral
-- Description: Implement a Line in => I2S => FPGA => I2S => Headphones
-- using the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity adau1761_test is
Port ( clk_100 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
aud_signal : in STD_LOGIC_VECTOR(15 downto 0)
);
end adau1761_test;
architecture Behavioral of adau1761_test is
COMPONENT dsp_block
PORT(
clk : IN std_logic;
new_sample : IN std_logic;
in_l : IN std_logic_vector(20 downto 0);
in_r : IN std_logic_vector(20 downto 0);
out_l : OUT std_logic_vector(20 downto 0);
out_r : OUT std_logic_vector(20 downto 0)
);
END COMPONENT;
COMPONENT adau1761_izedboard
PORT(
clk_48 : IN std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
hphone_l : IN std_logic_vector(15 downto 0);
hphone_r : IN std_logic_vector(15 downto 0);
AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
line_in_l : OUT std_logic_vector(15 downto 0);
line_in_r : OUT std_logic_vector(15 downto 0);
new_sample: out std_logic
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
signal clk_48 : std_logic;
signal new_sample : std_logic;
signal AUD_SIGNAL : std_logic_vector(15 downto 0);
signal line_in_l : std_logic_vector(15 downto 0);
signal line_in_r : std_logic_vector(15 downto 0);
signal hphone_l : std_logic_vector(15 downto 0);
signal hphone_r : std_logic_vector(15 downto 0);
signal count : unsigned(15 downto 0) := "0000000000000000";
signal filter0_l : std_logic_vector(20 downto 0);
signal filter0_r : std_logic_vector(20 downto 0);
signal line_in_l_extended : std_logic_vector(20 downto 0);
signal line_in_r_extended : std_logic_vector(20 downto 0);
constant hi : natural := 15;
begin
-- extend the line in sample to 21 bits.
line_in_l_extended <= line_in_l(hi) & line_in_l(hi) & line_in_l(hi) & line_in_l(hi) & line_in_l(hi) & line_in_l;
line_in_r_extended <= line_in_r(hi) & line_in_r(hi) & line_in_r(hi) & line_in_r(hi) & line_in_r(hi) & line_in_r;
-- source the files
-- choose the output, and adjust for filter gain
hphone_l <= aud_signal;
hphone_r <= aud_signal;
i_clocking : clocking port map (
CLK_100 => CLK_100,
CLK_48 => CLK_48,
RESET => '0',
LOCKED => open
);
Inst_adau1761_izedboard: adau1761_izedboard PORT MAP(
clk_48 => clk_48,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA => AC_SDA,
hphone_l => hphone_l,
hphone_r => hphone_r,
line_in_l => line_in_l,
line_in_r => line_in_r,
new_sample => new_sample
);
Inst_dsp_block: dsp_block PORT MAP(
clk => clk_48,
new_sample => new_sample,
in_l => line_in_l_extended,
in_r => line_in_r_extended,
out_l => filter0_l,
out_r => filter0_r
);
end Behavioral; | gpl-2.0 | 0673955f2ed9b494ea7e28c27ac942ea | 0.542924 | 3.006329 | false | false | false | false |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/ip/ram1/synth/ram1.vhd | 1 | 14,182 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY ram1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram1;
ARCHITECTURE ram1_arch OF ram1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ram1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ram1_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ram1_arch : ARCHITECTURE IS "ram1,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ram1_arch: ARCHITECTURE IS "ram1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=ram1.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=ae,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 1.3396 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "ram1.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "ae",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 1.3396 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ram1_arch;
| gpl-2.0 | 848e66248befde0ccf7ab51b92c07f7c | 0.626146 | 3.025171 | false | false | false | false |
id101010/vhdl-irdecoder | outputswitcher_tb.vhd | 1 | 4,300 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:36:49 01/22/2016
-- Design Name:
-- Module Name: /home/aaron/Dokumente/STUDIUM/SEM5/Elektronik3/Digital/Miniprojekt/vhdl-irdecoder/outputswitcher_tb.vhd
-- Project Name: irdecoder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: outputswitcher
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY outputswitcher_tb IS
END outputswitcher_tb;
ARCHITECTURE behavior OF outputswitcher_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT outputswitcher
PORT(
sel_raw : IN std_logic;
sel_decoded : IN std_logic;
dclk : IN std_logic;
data : IN std_logic_vector(19 downto 0);
seg6_en : OUT std_logic;
seg6 : OUT std_logic_vector(3 downto 0);
seg5_en : OUT std_logic;
seg5 : OUT std_logic_vector(3 downto 0);
seg4_en : OUT std_logic;
seg4 : OUT std_logic_vector(3 downto 0);
seg3_en : OUT std_logic;
seg3 : OUT std_logic_vector(3 downto 0);
seg2_en : OUT std_logic;
seg2 : OUT std_logic_vector(3 downto 0);
seg1_en : OUT std_logic;
seg1 : OUT std_logic_vector(3 downto 0);
dp : OUT std_logic
);
END COMPONENT;
--Inputs
signal sel_raw : std_logic := '0';
signal sel_decoded : std_logic := '0';
signal dclk : std_logic := '0';
signal data : std_logic_vector(19 downto 0) := (others => '0');
--Outputs
signal seg6_en : std_logic;
signal seg6 : std_logic_vector(3 downto 0);
signal seg5_en : std_logic;
signal seg5 : std_logic_vector(3 downto 0);
signal seg4_en : std_logic;
signal seg4 : std_logic_vector(3 downto 0);
signal seg3_en : std_logic;
signal seg3 : std_logic_vector(3 downto 0);
signal seg2_en : std_logic;
signal seg2 : std_logic_vector(3 downto 0);
signal seg1_en : std_logic;
signal seg1 : std_logic_vector(3 downto 0);
signal dp : std_logic;
-- Clock period definitions
constant dclk_period : time := 1000 ms / 81;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: outputswitcher PORT MAP (
sel_raw => sel_raw,
sel_decoded => sel_decoded,
dclk => dclk,
data => data,
seg6_en => seg6_en,
seg6 => seg6,
seg5_en => seg5_en,
seg5 => seg5,
seg4_en => seg4_en,
seg4 => seg4,
seg3_en => seg3_en,
seg3 => seg3,
seg2_en => seg2_en,
seg2 => seg2,
seg1_en => seg1_en,
seg1 => seg1,
dp => dp
);
-- Clock process definitions
dclk_process :process
begin
dclk <= '0';
wait for dclk_period/2;
dclk <= '1';
wait for dclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for dclk_period*10;
data <= "00001001110100011111"; -- apply valid signal (Signal 1)
wait for dclk_period * 10;
-- configuration 1
sel_raw <= '0';
sel_decoded <= '0';
wait for dclk_period * 10;
-- configuration 2
sel_raw <= '1';
sel_decoded <= '0';
wait for dclk_period * 10;
-- configuration 3
sel_raw <= '0';
sel_decoded <= '1';
wait for dclk_period * 10;
-- configuration 4
sel_raw <= '1';
sel_decoded <= '1';
wait;
end process;
END;
| lgpl-3.0 | 0e2b2ec78115e90b48a7518691bd8335 | 0.56 | 3.647159 | false | false | false | false |
jhladky/ratload | RAT_CPU/register_file.vhd | 1 | 1,468 | ----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer: Jacob Hladky and Curtis Jonaitis
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register_file is
Port( FROM_IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
FROM_TRI_STATE : in STD_LOGIC_VECTOR(7 downto 0);
FROM_ALU : in STD_LOGIC_VECTOR(7 downto 0);
RF_MUX_SEL : in STD_LOGIC_VECTOR(1 downto 0);
ADRX, ADRY : in STD_LOGIC_VECTOR(4 downto 0);
WE, CLK, DX_OE : in STD_LOGIC;
DX_OUT, DY_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end register_file;
architecture register_file_a of register_file is
TYPE memory is array (0 to 31) of std_logic_vector(7 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
SIGNAL D_IN : STD_LOGIC_VECTOR(7 downto 0);
begin
with RF_MUX_SEL select
D_IN <= FROM_IN_PORT when "00",
FROM_TRI_STATE when "01",
FROM_ALU when "10",
(others => 'X') when others;
process(clk, we, d_in) begin
if (rising_edge(clk)) then
if (WE = '1') then
REG(conv_integer(ADRX)) <= D_IN;
end if;
end if;
end process;
DX_OUT <= REG(conv_integer(ADRX)) when DX_OE='1' else (others=>'Z');
DY_OUT <= REG(conv_integer(ADRY));
end register_file_a;
| mit | 6880dba761ce43667e9c0772f247bed8 | 0.526567 | 3.406032 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_1/DIGDUG_ROM_funcsim.vhdl | 1 | 122,965 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Mon Nov 30 13:52:22 2015
-- Host : centennial.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
-- Command : write_vhdl -force -mode funcsim
-- /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7900/Atari7900.srcs/sources_1/ip/DIGDUG_ROM_1/DIGDUG_ROM_funcsim.vhdl
-- Design : DIGDUG_ROM
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_bindec is
port (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : out STD_LOGIC;
ram_ena : out STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_bindec : entity is "bindec";
end DIGDUG_ROM_bindec;
architecture STRUCTURE of DIGDUG_ROM_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end DIGDUG_ROM_blk_mem_gen_mux;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe(0),
O => douta(0)
);
\douta[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe(0),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe(0),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe(0),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe(0),
O => douta(4)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe(0),
O => douta(5)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe(0),
O => douta(6)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe(0),
O => douta(7)
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_prim_wrapper_init is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\addra[12]\ : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end DIGDUG_ROM_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"011A1A1026227B5901FF0104090904F0D0F0D0F0B07E3E1C1D3F5E3E7E1E3E7E",
INIT_02 => X"0603060203030200000201010107010201160E0F0C07060E0508140F09050808",
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INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => X"522900B3976B28A6BB3D296384BD5C2B430094BD6C2300B58D392300009BB435",
INIT_09 => X"A3BA293200CA827B3900A6BC3B3300B88C7234B6727A3C2800B8966D5400AC6D",
INIT_0A => X"4C7274766ADE6C6E706ADE000000003B0000009B5300B49A39520083B94B3200",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000001FBD",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"94A6A529A505A4299A16685A505A681A47D553375337543757D1DCC5DCC5DC15",
INIT_10 => X"9500000000F2008E001A1A003722B1A6302AD0E800138030ED0762F700000B00",
INIT_11 => X"033300222203D4DDD4DD0404D4D400040404470D1100D4D4044D46DD9A0000C0",
INIT_12 => X"0000FE0260B085F7A923308DAAA9232F8DD5A944004433050734740704000333",
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INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"543D95AE913694A67C15BA569C469A16555557D557D555D5555557D557D55755",
INIT_18 => X"00BDAACC6518E7BFBDAA2490BDAA4A4A8ACC854A4A4A68AA0CE93849B5485CB5",
INIT_19 => X"D0CCC560D28501A909B02EE0CCA6DF752000A00AA912B01EC9FD4020CC856026",
INIT_1A => X"10CA03F0EAACDD40A50FA260D28500A904B024C9C30A20E1E920A880651860F7",
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INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"5073D4FF543D4A05CD05FF177C1550A155505415541555150555541554155455",
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INIT_22 => X"0000000000000000A02A00000000000000000000000000000000000000000000",
INIT_23 => X"281A0000600A682A00008002282800008002282800010C000000000000000000",
INIT_24 => X"A024A225A2240000000000000000A00A000000000000000000000000A4280000",
INIT_25 => X"00000000000000000000000000000C0003C00404A82AA028A028281AA0692828",
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INIT_27 => X"D420D6FF543DAA050817FF977C1550AAD50055555555EA5500575555555555AB",
INIT_28 => X"000000005041050000000000AA2AA8AAB53FFE5EA802A80AA80A802AA02AA02A",
INIT_29 => X"0000000000000000000000000000000000000000000040050000000100008155",
INIT_2A => X"4001541554555015A81600000000000000000000000000000000000000000000",
INIT_2B => X"200800005829682A052AA400A80AA850002AA02A04413C000000000000000050",
INIT_2C => X"A424AA25AA249005900590050280282800000000A5A9690A6A5AA06920080000",
INIT_2D => X"00000000000000000000000000003C0003C01515DE57A8AAA8AA20086815A02A",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"D4C0D5FF553DA8010317FF577C55402A350055555555FA5A005C55555555A5AF",
INIT_30 => X"014059004055250054000000AAAAAAAAD516D457A81AA82AA82AA42AA42AA42A",
INIT_31 => X"0000000000000000000000000000000000000000000055420000400100004551",
INIT_32 => X"A02AA8AAA8AAA8AA7A55FCFFFF3FFCFFFF3FFCFFFF3FFCFFFF3F000000000000",
INIT_33 => X"54F528CA682AA82AA50AA5AAA82AA05AAA5AA42A10113000FCFF3FFCFF3F00A0",
INIT_34 => X"A626AA26AA26A4296A29AA291AA48AA200000A2895165429945668155F15A328",
INIT_35 => X"FF3FFCFF3FFCFF3FFCFF3FFCFF3F300003C00C0C75965A96589654F55AA5A42A",
INIT_36 => X"0000FCFFFF3FFCFFFF3FFCFFFF3FFCFFFF3FFCFFFF3FFCFFFF3FFCFFFF3FFCFF",
INIT_37 => X"D500D5FF5535DF050057FF575C5550F715C055555555397B035455555555ED6C",
INIT_38 => X"1055A6014015590054210000AAAAAAAA540BF015962AA56A962AA896A95AA896",
INIT_39 => X"3C003C00003C003C000000003C003C003C000065014045510054500100006905",
INIT_3A => X"50140050005014507E7D7F77FFFD7F777FFF7F777FFF7F775FFD003C00003C00",
INIT_3B => X"55D59AD6682AA82AA922A5A6AA6A886A9A5AA9AA0000C000DFFDFDDF7DFF0050",
INIT_3C => X"AAAEAAAEA8AE68295A2A6A29A28A2288A8A82A2A540A5AA5A0155AA5575597A6",
INIT_3D => X"F7D5DFFDFDDFFDFDDFFDF5DF7DF5C0000C300C0C9624765D765DCAAC37FFDD25",
INIT_3E => X"0000FFDD7DFFDFDDDFF7DFDD57F77F77F7FD7F777FFF7F777FFF7F77DFFF7FF7",
INIT_3F => X"6AC055FF6A55FF1C03A9FF5555A934FF35005555A6553973005C5555559ACD6C",
INIT_40 => X"5189FA1A5441650555150014AA9AA6AABC05503EA51AA91AA51AA45AA46AA45A",
INIT_41 => X"C300C30000C300C300000400C300C300C300409A550450690056550000005900",
INIT_42 => X"A8A800A000A028A07555DFDDFDFDDFDDDDFDDFDDDDFDDFDDFDFD00C30000C300",
INIT_43 => X"69DA96F5A82AA82AA9AAA95AA95AAA6AA56AA56A0000C0007777F77777FFA0AA",
INIT_44 => X"A8A6A8A6A8A668AA98AA68AA08200AA0E8BEFE3FA8056A05502A50A9A7695F96",
INIT_45 => X"DDDF7777F77777F77777FF77F7F7C0003C3C3C3C2000B57D757DCAACCCF7DDA5",
INIT_46 => X"00007F7777FF777777F777777FF7DFDDDDFDDFDDDDFDDFDDDDFDDFDDDDFFDFDD",
INIT_47 => X"AA23547FDAD5CC11C8AAFD1557A7443356005555EA5AA53300955555A5ABCC5A",
INIT_48 => X"41A5BAAA0555EA17555A0555A955556A6F5555F9691569156915546954695469",
INIT_49 => X"C300C31000C300C31000F500C300C300C310A4AF624500654019550000156900",
INIT_4A => X"1450545500501450DD5DDFDD7DFDDFDDDDFFDFDDDDFFDFDD7DFF10C31000C310",
INIT_4B => X"BE6F695AA82AA82AA99A5A556955A66A55A555691551C0007777F77757F55455",
INIT_4C => X"6AAEA8AE68AE6AA6A8A668A6A40A200828B3C2206A55A80555A9502AF9BEA569",
INIT_4D => X"FDF77777F77777FF7777FF77F7FDC000300C303000005D56DD55FA6F5573AAAA",
INIT_4E => X"00007F7777FF7777F7F77777DFF7DFDDDDFDDFDDDDFDDFDDDDFDDFDD55FDDFDD",
INIT_4F => X"6D3D6A15FFCCF4037C7954A933FFC01FEAC1A559FA6B543F43AB655AE9AFFC15",
INIT_50 => X"9599E95B0565E91694595569AA9AA6AADBCC33E7587758775877DD25DD25DD25",
INIT_51 => X"00C3005FC300C3005F0004C300C300C3005FAAAE5A4100695456500548156401",
INIT_52 => X"14505455005014505D5DDFDD7DFFDFDD7DFDDFDD5DFFDFDDDDFF5F005FC3005F",
INIT_53 => X"CAACBE6FA82AA82A5A55D61D597755A57497DD650000303077F7F57777F71450",
INIT_54 => X"6AA6A8A668A66AAEA8AE68AE0690296828B3CE2CDACC681533A754293AA3F9BE",
INIT_55 => X"D7FD77F7FD77F7F57777FD7777FF3030C003C00000005D5E5D5DA95A543FA02A",
INIT_56 => X"00007F7777FF77775FF77777F7F7DFDDDDFDDFDD7DFFDFDD7DFDDFDDDDFDDFDD",
INIT_57 => X"5F555A15CF00400D55F554A500F37001FA2FEA6B296E5005F8AFE9ABB9685005",
INIT_58 => X"595584145415110540141A14AAAAAAAAFA0000AF5A775A775A77DDA5DDA5DDA5",
INIT_59 => X"00C30010C300C300100000C300C300C30010E56B66564019F56A155454555456",
INIT_5A => X"14500050005014505DBDDFDD5DFFDFDDFDFDDFDDDDFDDFDDDDFD100010C30010",
INIT_5B => X"CAACCAACA82AA82A1611D61D597744947497DD6500003C3C77F7F77777FD1450",
INIT_5C => X"68AA98AA68AAAAA6A8A6A8A62AA82EB8E8BFF80BFA00FFDC00AF37FF3AA33AA3",
INIT_5D => X"DFDD7777F777F7F77777FF7777F73C3CC003C00000005D5A5D5D54155007A00A",
INIT_5E => X"00007F7777FF77777FF7777777F7DFDDDDFDDFDDDDFDDFDDFDFDDFDD5DFFDFDD",
INIT_5F => X"FF1D7E55FC03000574FF55BDC03F5000296E2A62D5320000B96889A88C5B0000",
INIT_60 => X"550161001440140010000500AAAAAAAADF33CCF7AAAAAAAAAAAAAAAAAAAAAAAA",
INIT_61 => X"003C00003C003C000000003C003C003C0000141255659515E55A1654A5555554",
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INIT_64 => X"68295A2A6A29AAAEAAAEA8AE2EB82EB8A02AA002DF33DF33CC57CCF7F9AF3AA3",
INIT_65 => X"D5F7DFFDFDDF7DF5DFFDF5DFFDFD0C0CC003C0000000BDBA7DBD000000000000",
INIT_66 => X"0000FFDD7DFFDFDD57F7DFDDDFF77F77F7FD7F77DFFD7F775FFF7F77DFFF7FF7",
INIT_67 => X"CC94DFCCF0350000163333F75C0F0000E5322932543F00008C5B8C68FC150000",
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INIT_6A => X"14505455005054555609FCFFFF3FFCFFFF3FFCFFFF3FFCFFFF3F000000000000",
INIT_6B => X"A95AFA6FA82A682AA802A902A55A802A806AA55A04410303FCFF3FFCFF3F5455",
INIT_6C => X"A4296A29AA29A626AA26AA262EB82EB800000000CD55CD5555735573A56AF9AF",
INIT_6D => X"FF3FFCFF3FFCFF3FFCFF3FFCFF3F0C0C300C3000000095205629000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000010005040000401000040000",
INIT_7A => X"0000000000000000F40000000000000000000000000000000000000000000000",
INIT_7B => X"00005415682A600A000000000000000000000000000003030000000000000000",
INIT_7C => X"000000000000A024A225A22429680AA000000000D005D0055007500700005415",
INIT_7D => X"000000000000000000000000000004040C300C0000002400F402000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0015D00500000000540050070000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \addra[12]\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"A1A5FC2E203C8550A9E6F720D05720018500A93C857FA99AFFA2018517A9D878",
INIT_01 => X"20EF0020DA6820D753200FD084A5DF2020DE6D20DBFE202300EEAA8586A5FC10",
INIT_02 => X"C08D02848D018500A9C7D0FCF086C5CDD0AAC586A5FB5820F4EF20FA3320F71C",
INIT_03 => X"A223E88D38851FBF8EEEA21FBE8E57A21FBD8E4CA2A186B5A23486E0A2AA851F",
INIT_04 => X"8DF710CA24C99D24CF9D03A2A88501A9F810CA24C09D409512A2FB10CA7E950A",
INIT_05 => X"8502A90FA02FA2ED10CAF810CCC688240099C008BDCC85EACCBD28A28FA024CD",
INIT_06 => X"EFD06806F0072998E8C822009948D579BDAAA8F01088F810CCC6CA24909D98CC",
INIT_07 => X"B9235D9DEBC1B9E825009D23A29D235D9DE7AAB911A000A2E790C8C068EFD0CA",
INIT_08 => X"108807F045E0E825009DE7A923A29D235D9DEBABB9E825009D23A923A29DEBD7",
INIT_09 => X"A2D1CA4CD1DE20AAE9F920D60D20D19A20FAD0CA25F09D1EA90EA2C7D014A0CB",
INIT_0A => X"81A5D16C206023078E2086EE1088F1D00329988809F0CA230799E7CEBD1FA018",
INIT_0B => X"1BBE8DDB9160A9C8DB91E7BFBD00A0DBD6200FA260818568D16C208185404948",
INIT_0C => X"009DF0A200A960D5D0CADB9100A9C8C8DB9110A9C8DB912480BDC8DB9126A9C8",
INIT_0D => X"F72060270F8D260F8D25FF8D88A927008D26008D25F08D8CA9F7D0E827009D26",
INIT_0E => X"A086602C8523A93085EAAABDE80150812400A2E6F720602C8525A9308500A9E6",
INIT_0F => X"A5FB10CA409512A223F18D84858385878523F38D8AD13F20D15B20858501498A",
INIT_10 => X"D60D209F86AA01D082A59E8605A228D0A0A6D24420DE1C20E804F082A508D0A0",
INIT_11 => X"8500A99E86E8DD3B4C87C6DF7D20A800A91BEE8D96A987E60FF082A5DF7D20A8",
INIT_12 => X"19D085A5D50020D2C02023008DC885C285F910CA4B95B29500A907A2609F85A9",
INIT_13 => X"85BFA9538560A90CD026778E08A2F2D060C0A81069189826179914A9E4DB20A8",
INIT_14 => X"9920A90BF08ACC85F9B00AC90AE9E807900AC900A20EA09BB587A6668506A940",
INIT_15 => X"60FAD0882600991EA9F7D0CA0BF08826009922A90BF0CCA6F7D0CA1AF0882600",
INIT_16 => X"26108D2600994CA9E7BFBC0DA2E2EF2076A2FAD0CA260F9DE0A224A956D0C2A5",
INIT_17 => X"18980EF088A5889B94C803D09BB487A627D0A0A48A26EF8DEDD0CA25FF994AA9",
INIT_18 => X"E01FC4BE87A41FC49D0A6903299BB506900FC0980BD011A90F9011C904B00F69",
INIT_19 => X"20C986D185E9E2BDAA072986A5D3424CCAA5D185E9E2BDC9A60CF0C2A5299011",
INIT_1A => X"A9CF8500A9A80A0A0A8AD284E8E3BCD184E9D1BC0BD01169188ACA85D285D56A",
INIT_1B => X"16A90FD0E2EF2005B016D0C2A5D20623F008488A05D02200BECE8607A2D08504",
INIT_1C => X"D0A604D0CFE6CFA606B0D1068A0848E4E8208A26209D1CA926109D14A926009D",
INIT_1D => X"7D03B068281330B29580A9682808D000C9419500A902B0E7E7FD07900828D0E6",
INIT_1E => X"D012A204F088A587A49010CEC6C8419500A904F0B29500A90630B2B55495E9AA",
INIT_1F => X"E0A9231E8DE8D0BD23F08DE8AABD23EF8DE8BDBD11A2029011E0CA07F09BB60B",
INIT_20 => X"262C8D0AA926D088A504D0A0A52ED0C2A532D0CA03F09BB61FCF8DBEA91FCE8D",
INIT_21 => X"DA8D26628D1CA926CA8D26BA8D26528D26428D14A926A68D262D8D0EA926A58D",
INIT_22 => X"D709BD00A023228DE9C5BD23208DD708BDAA0C29FAB00CC90CE906900CC98A26",
INIT_23 => X"9D00A907A2FA10CA24C09D08A2D4B920ED9006C0C8C8E823EA99E9C6BD23E999",
INIT_24 => X"01A90D90CC460A1290CC4604A9CC854AD7282021389D08A922E89D21309D2337",
INIT_25 => X"068D3C691886A5F3204CC710CAF38520F25C20BA9500A90290CC460A0790CC46",
INIT_26 => X"A27F857E85FF6720C24D2023018E02A2029018C9009BB987A405D088A543A223",
INIT_27 => X"E3EF4C23038E04A2AF8689868A86B5A2808523058D23048D7B86FB10CAE09513",
INIT_28 => X"0810CFE6049011C91FC4BD87A604A0D0856A86A5FA108800D19907A0CF8500A9",
INIT_29 => X"B5AA0729D045D56A20D0661AF00129D56A201CF0CFA5CEA6CE851FC47D180A0A",
INIT_2A => X"A9006F99A6A94996005C99E4E82006F0AA03D0C100BD08D0D195C000BDF2D0D1",
INIT_2B => X"BB97009A22A32A60AB8568AC85ABA548AC65AB6586A560BF1088CEE600C39900",
INIT_2C => X"3A3A0053B6928A3434006B2A36AB9332007C38C8A434009638C9522B0092623B",
INIT_2D => X"44446A542C2CBAA448485D35BBB2B296595900833636C5AA4A32002626B99393",
INIT_2E => X"6A2B4D3434A4A48A3838546CCBCBA6A63A3A4DB5AAAA58584343936D4A4A6262",
INIT_2F => X"00BA23003A23BAB200A7426B003A932300BA426B00A72300A23B989636367272",
INIT_30 => X"10CAA29500A905A2F710CA1BBD9DE6AABD3AA2003A426B9300A73A2300BAA7B2",
INIT_31 => X"1AB011C91E90D1E538066949B527B006C90169FF490410D0E5385CB5D18560FB",
INIT_32 => X"603817A960186038D2A502D0D1A5049004C90890D1E5129017C9D28505E949B5",
INIT_33 => X"A923079D85A923228D23218D37A9600FA9604A02A902901EC908B024C92600B9",
INIT_34 => X"A2EBEC206023EF8DE8CEAD231E8DE8E1AD23F08DE8BBAD23099D0EA923089D37",
INIT_35 => X"0CB987A400A2E6E54C22A099A90CA2E6E52022A01DA90DA2E6E5200EA0A3A909",
INIT_36 => X"86EA86E860EC86EB86E860EA86EB86EC8602D009F018C9ECE615F0ECA50C3000",
INIT_37 => X"11000C0C0CF4000000F400000048E0BE3260B18510A904D0B1A508F0C87BA4EC",
INIT_38 => X"CEA56024C92600B9A810E93804B2150A271E150A1024271A17000C0C0CE80000",
INIT_39 => X"CC6518CC852490B9A84A4A01691840A5F39F4CCE84F42B20602600B9A8106918",
INIT_3A => X"A52DF0A0A5D285E1A5D085EDA90304010260CCE53801691840A5CC850A0ACC65",
INIT_3B => X"A80329A98500690329D56A2037D0E2AABDA9C607F0A9A50BD0F2A580A662D0E3",
INIT_3C => X"A5FDEF2013A0A88400A009D060C953A53CF085A5F11098C823D0E2BBDDE2AAB9",
INIT_3D => X"B94C858500A9DD332028A9668502A910D06BC949D038E053A6BFA908D0BFC940",
INIT_3E => X"C90F090A0A0A0A04F087A60280ADF3D0EE05E3A560EDC602F0EDA531D0DFA9D4",
INIT_3F => X"C802900A00A080A6F2E6E2B4BDF7D0CA9804F0E2AD3DA806A2ED860AA213F0FF",
INIT_40 => X"E2BBD907B0B006E2AABDE2D0E2AABD05F0072953A5BAB00AC804900AC87B900A",
INIT_41 => X"30DA0920E0C4208AE605908A0606F0D28500A906F0E2AAD98084B0E602F069D0",
INIT_42 => X"C3AD1390EABBECE814904A9840A6D9C44CD28500A907B007C9C3B506D002C011",
INIT_43 => X"5520D8D84CFAB00CC90CE9388A4086CADBF017E060808400A04085BFA96685E1",
INIT_44 => X"E2BBD907B023302E232F0EE2AABD80A660F28500A9D7F84CE2AABD80A60DF0C3",
INIT_45 => X"07B04A9853A69110DA0920E0C420D28500A904F0E2AAD98084232FEE03F0E9D0",
INIT_46 => X"4CD8E220E48601A2CCE53853A5CC85F8298A5386CA80F008E005D0E887F070E0",
INIT_47 => X"CF85E1B3B93ED0E1CFD9C3424C0CA905D0E1E5D905F0E1D9D90AF0E1DDD9D989",
INIT_48 => X"E1BBB980A4D28500A9FD432003B024C9C30A20E0DC791853A5AAD6F3791840A5",
INIT_49 => X"00A916D0E1D6D9C3224CFD434C68CF85E1B7B9480AB024C9C30A20E1E920CF85",
INIT_4A => X"53A50FD0C3552014D0E1D2D9C3224C1C9024C9C30A20E1E920CF85E1AFB9D285",
INIT_4B => X"0020D68648D0C3B54C30DA0920A80C0980A560E48502B0C3422004A909D00729",
INIT_4C => X"00A9C39502A9CBA60AD080C488053011F0E5A4F28500A92E903DB024C9D6A6C3",
INIT_4D => X"04D0C3B4D74FB980A40530FFA9BB30DA092003A00B10DA0920A8040980A5E585",
INIT_4E => X"AAB0865BA223308E52A2232F8E52A214F0AAE18513F0E1C5D2A580A4CB86E585",
INIT_4F => X"1840A56285C25C791853A57585E1BFB980A4604F85F7C820C24D20D9EE4C06F0",
INIT_50 => X"D05CD5D3A504A2CD85D6F8791840A5D385E0E1791853A5E2B0E19017C9C25E79",
INIT_51 => X"2490CDE507691849B52DD0022980A533F0C3B534F049D5CDA53DB0B2C96FB543",
INIT_52 => X"D02CC904F024C9D5A6C30A20D3A5AA0CE93840A5D58617F017C940A520B011C9",
INIT_53 => X"6BC940A5EB900FC9F1A55285E68500A9F7D0E7C60AF0E6A560B410CA6000A903",
INIT_54 => X"A2029013E09BB687A40AD088A5E78530A9F186CAE68601A2DFD038C953A5E5D0",
INIT_55 => X"A01FCE8DC4A9DF752000A9658535A9E2C9BC1FCF8D2400B9A84A7885E2DCBD12",
INIT_56 => X"A2E6EB2059A226A0DBD62006A2D69C20D1BE20818540A9A885E9F920FDEF4C0E",
INIT_57 => X"FC1420E5E820DBA620D6722011A2D1861BBE8E00A2E6EB2037A21EA0DBD62009",
INIT_58 => X"100CA52322EECD8588A5CC854A69AEA5F9904A4A0282ADF7D0FFC90F090280AD",
INIT_59 => X"D1C60CB04A56F048D0CDC588A5A08600A2E9F920FB9002824E14B04A0282AD0E",
INIT_5A => X"714C8AE886A6081009900A13900A15900A01A20280AD03D0E2B5BDAA0329D1A5",
INIT_5B => X"F0CDC588A5A08601A21FD0AEE4CCA6146986A5DBA6208886CADB6A4C8286CADB",
INIT_5C => X"9AFFA2DB1A4CD7D086C56008D0A0A6DFB12003F082A6DFB120AAD60D20A08610",
INIT_5D => X"198D32A9DBE82005D048A9D6892007D088A519608D98690A82A5D01B4CD13F20",
INIT_5E => X"EBD6BD03708124EBC0BD602086E8F210CAF5D003298ACA20952307BD1FA2601A",
INIT_5F => X"83A560231D8D23EF8DE8CFAD231E8DE8E2AD23F08DE8BCAD60DB85EBAABDDC85",
INIT_60 => X"07A200A0DD332028A9C39502A9CBA606F0E5A5F2FC2003B00FC907F0F1A5FBF0",
INIT_61 => X"A952844E84E510CA4194A8F18A20FB092003D004C92337BD0ED002C98629B2B5",
INIT_62 => X"D5C6DD332012A96685C155BDD586C031BE80A4D68604A2FDEF2012A0DD332008",
INIT_63 => X"A512D0A0A519D0A0A51DF082A508D09ED687A6838600A2DF3320EE10D6C6D5A6",
INIT_64 => X"8EA08601A2DD3B2010D0A0A6DD104C03F09EB522D0009EB9A8014987A50EF082",
INIT_65 => X"9D6840952000BD4840B525A2D1BE208784FC2E4CA88501A9DD5E20DE1C2023F1",
INIT_66 => X"A91FC69D68B2951FC6BD48B2B520269D68C3952026BD48C3B507A2F110CA2000",
INIT_67 => X"10D023F3AEEDD0FFE0CA27009D6826009D2700BD482600BDF0A2E110CA6F95A6",
INIT_68 => X"C28501A9DE1C20CA04F082A608D0A0A6DD264CD24420DE1C20CA858623F38EE8",
INIT_69 => X"00A01887A6DD4C4C68FB58204828A9DD3B2003D0A0A5808500A9E4DB20D2C020",
INIT_6A => X"88A5606860F4D086C56806F098DE6D2048866518601BF28CA894690A04F09EB5",
INIT_6B => X"8D01092602AD260E8D0AA912F082A5DD9B20260E8ECA04F082A634D08ADDB120",
INIT_6C => X"1FC38DA2B5601FBE8D57A93485E0A93C8550A9D19A20D1BE20DD9B2001A22602",
INIT_6D => X"FEC93904AD5FD0C6C93900AD01A2483FFD4C26A000A21FC18DA6B51FC28DA4B5",
INIT_6E => X"72201DA2D69C20818540A9F710CA26009DE9EABD0EA21FBE8DD9A9D1BE2058D0",
INIT_6F => X"89200DD04868DBE8201ADB8E1B1E8EFCA2F710CA1A059DD6EFBD05A2231E8DD6",
INIT_70 => X"01A9488A6068DBC220231D8D23EFAD231C8D23F0AD1A058D48A926028D04A9D6",
INIT_71 => X"E6EB20AAC038BDC03ABCAA4868DB91D0A903A0DBD6200AA21BBE8EEBEC20A885",
INIT_72 => X"84C8E8F420DD4C2064A9D1CA20E5E820FC1420DB919AA904F087A61DA00AD068",
INIT_73 => X"02822CA886E85ED002822C08A95AD0A0A601A0601BBE8D60A9D15B20D1BE20A8",
INIT_74 => X"0CD0FFE00280AE13100CA63C8670A221D0AEA63CB0DF5C20DF172088AE86FBF0",
INIT_75 => X"3C8650A2FBF002822CD1D002822CAE853C8650A2E9901FB0DF5C2012F002822C",
INIT_76 => X"F9200EB04A0282ADE82D100CA5CA06D023F1AD11F036D00FF0A88600A2DF1720",
INIT_77 => X"F0F0C9F0290280AD63D023F1AD68F0A0A512904A18B000A2FB9002824EA885E9",
INIT_78 => X"60FCD086E4E8E886A6D01E4C9AFFA2DF2A20D1DE20A0A6D1BE20A086DAC4205A",
INIT_79 => X"CA1A10B2B507A220D0E30584A5DD334C28A9A885A0A5E4DB20808636D0DF3320",
INIT_7A => X"82AD00A26001A26000A2D24420D1BE209BF687A6DD4C209AA9FDEF2011A0F910",
INIT_7B => X"1887A6DED085A6E2D0A0A66001E008A93C8550A902A206B04A05D0E803B04A02",
INIT_7C => X"B5D813D005C904F00F2908F002C9A695A67500A92590A495A47598A295A275F8",
INIT_7D => X"3EA909F088A5381DA002F08A05A0D887A6FDEF200FA0DD3B209EF60CF00AC99E",
INIT_7E => X"B51BC599E3E020A4B51BC199DFF020A6B51BBD99E3E020A6B505D032A91BBE99",
INIT_7F => X"30609669180A04F000A904D006900F29601BCD99E3E020A2B51BC999DFF020A4",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"A96A5D555454545400400040004000405D545D54545454540000000000000000",
INIT_01 => X"0000800A0000EF0E00000080B00E01405D555D555D5501405D555D556AA55AA9",
INIT_02 => X"330C00CCCCCCCC00000000000000000000000D000050A80A0000000000000000",
INIT_03 => X"60FF030000A8AA00AA2AA8AA00A8AA00A8AA80AA80AAAA2AAA0280AAC0C03033",
INIT_04 => X"00000000000000000000F0FFFFFFFFFF00000A00000000A0A00AAAAAC03FFF00",
INIT_05 => X"F6F6F6F5F5F5C4B8A3A368522A22D6D2CECAC6C2BEDA00000000000000000000",
INIT_06 => X"00000800606685E1C3BDAACC65CC840A0AE08502A9021001E938E0A5AAA8F6F6",
INIT_07 => X"7500600050004000300020001250050000F9070000F8100000FD030000F80800",
INIT_08 => X"AAAA055000500050014001400040004005000500000000000100010000000000",
INIT_09 => X"0000A02A0000B803005700A02C2B01405005555550550140550555555A9556A5",
INIT_0A => X"330C00CCCCCCCC001450501540051450505505000050EA2AC003000030330000",
INIT_0B => X"C0FF3F00C0FFFF0FFF3FFCFFC0FFFF0F0000C0FFF0FFFFFFFF03C0FF30333333",
INIT_0C => X"F003F03FFCFFFCFFF03FF0FFFFFFFFFF14500A00000000A0F00FFFFFC00F3F00",
INIT_0D => X"108274909EA5C8ECDAC8A5DAEC7B6D8997FF47042F7C00FFF03F00FFF03FF03F",
INIT_0E => X"000107090102060403050B0B00000A0701989E0A04969C0802949A0600787A12",
INIT_0F => X"5F609D850469189DA560E0DD791853A5AAD6F4791840A508020206050403020A",
INIT_10 => X"AAAA014000C00040010001000000000001000100000000000100010000000000",
INIT_11 => X"4004A0960069FC03405500A88BEC01C0400155D540D501C0550155D5565B6696",
INIT_12 => X"F30C000CCFCFFC0028A0A8AA800A28A0A8AA050000D0AE2AC003A00AC00F0000",
INIT_13 => X"C0FFFF00A0AAAA2AAA2AA8AAA0AAAA0A000080AAA8AAAAAAAA0280AA300333F3",
INIT_14 => X"F003FCFFFCFFFCFFFCFFF0FFFFFFFFFF28A00A00000000A0A82AAAAAC0030F00",
INIT_15 => X"C9DFEF7FBFFFFF7FEFBFDF7FC03090104020EFDFBF7FC0FFFCFFC0FFFCFFFCFF",
INIT_16 => X"BB6562B2807070606050504040303020201010080604021E10106003C902F002",
INIT_17 => X"546026029D0EA926019D0AA926009D1AA9CA5252C6C64E4EC2C24A4A4646DADA",
INIT_18 => X"AAAA004000400040004000400040004001000100000000000000000000000000",
INIT_19 => X"5015A85A806EF0E3705500BA23E201404001555540550140550155559AABEAAB",
INIT_1A => X"F30F00CCCCCCCC001450145040051450140005000050AA2EC0036829A46A5415",
INIT_1B => X"F05F0500FCFFFF3FFF3FFCFFFCFFFF3FF00FF0FFFCFFFFFFFF0FC0FF3003F333",
INIT_1C => X"FCFFFCFCFC3FFCFFFCFFF0FFFFFFFFFF14500A00000000A0FC3FFFFFC0FF0F00",
INIT_1D => X"010001FF00FF0000010100000101FFFF0000FFFF0000C03FFCFCC03FFCFCFCF0",
INIT_1E => X"0202010202020154A9FFFF248977F74A95FF7F4892EEEE00010001FF00FF0000",
INIT_1F => X"6023568C23558CFA108823509900A904A06096694A4A4A6000A9039005D0F029",
INIT_20 => X"AAAA004000400040004000400040004003000000000000000000000000000000",
INIT_21 => X"5455A86EE01AF0AB5055002A2BEA07504001575540550750570157556AAFFAAF",
INIT_22 => X"330F00CCCCCCCC0028A028A0800AA8AA280007000050EA2AC0035964A86B5555",
INIT_23 => X"FC451400A8AAAAAAAA2AA8AAA8AAAA2AA82AA8AAAAAAAAAAAAAAAAAA3033F333",
INIT_24 => X"FCFFFC00C00FC00FFCFCF0FFFFFFFFFFA0AA0A00000000A0A82AAAAAD0FF1F00",
INIT_25 => X"89827C4846464444424240403E3E3C3C3A3A38363432F00FFCFCF00FFCFCFC00",
INIT_26 => X"A940856BA93031323334352009372009200937CAC6C2BBB77BB0A9A59E7B9790",
INIT_27 => X"60280A0A0A0F2968AAEAACBDAA106918FF494A4A4A4A480860668500A9538538",
INIT_28 => X"AAAA010000400000010001000000000001000100000000000100010000000000",
INIT_29 => X"5465A86FB402B0AA5055802BABEA5557400355574057555755035557DABFFEBD",
INIT_2A => X"300C000C03F333001451545050155455545505000050AB3AF00F5AA5E8AE5555",
INIT_2B => X"FC451400FFFFFFFFFF3FFCFFFFFFFF3FFCFFFF3FFFFFFFFFFFFFFFFFC0C030C3",
INIT_2C => X"FCFCFC3FF003C00FFCFCF0FFFFFFFFFF50550A00000000A0FFFFFFFFF0FF3F0A",
INIT_2D => X"6968DEDEDEDEB1B1B1B1B1B0AFAEAFAEADACDEDEDEDEF00FF03FF003FCFCFC00",
INIT_2E => X"E6E4E2E0EEECEAE86265BBDAB2B562B804060810020304052E373C4043456969",
INIT_2F => X"5560F7108823509900F4B906A060F810CA23149D84A902A2F6F4F2F0FEFCFAF8",
INIT_30 => X"AAAA014000400040014001400040004001000100000000000100010000000000",
INIT_31 => X"5475AA17A800A89A5055800A88285555400155554055555555015555DABFDEBF",
INIT_32 => X"00000000000000001451545054541450545505000050AC0EE82B1695E8AE555D",
INIT_33 => X"FC551500AAAAAAAAAA2AA8AAAAAAAAAAA8AAAA2AAAAAAAAAAAAAAAAA00000000",
INIT_34 => X"F0FCFC3FFCF0C00FFCFCF0FFFFFFFFFF14500A00000000A0AAAAAAAAB0DF3F2A",
INIT_35 => X"0030E03E0028E03E0020E03E0018E03E0010B02560F0FC3CFCFFFC00FCFFFCFF",
INIT_36 => X"0080E03E0078E03E0070E03E0068E03E0060E03E0058E03E0040E03E9638E03E",
INIT_37 => X"60F8102824FC10282460F5B005C088CADB91FD4BBDAA68DBD6204800004CE09E",
INIT_38 => X"AAAA014000400040014001400040004001000100000000000100010000000000",
INIT_39 => X"5475EA19A800AAAA50D5800BA82A0550400105504055555555015555DAB3FEBF",
INIT_3A => X"303030F033303030545500501450145000500500005050057BAD5691E46E555D",
INIT_3B => X"FCFFFF03FFFFFFFFFF3FFCFFFF3FF0FFFCFFFF3FFFFFFFFFFCFFFFFFF0F33330",
INIT_3C => X"F03CFC00FCF0C00FFCFCF0FFFFFFFFFF14500A00000000A0FFFFFFFFAA96AAAA",
INIT_3D => X"EF4B4BCC474F4BCBCB4B4B4BCB4B4B4BCB4B4B4B4B4BFCFCFCFCFC00F0FFF0FF",
INIT_3E => X"8686A0851A0E24D64400300E1A34000E8500102030405060708090A0B0C0D0E0",
INIT_3F => X"94332114022A330B14FFFF047CFF042F7C0C180C000C180C003486D424851A0E",
INIT_40 => X"AAAA004000C00040004000400040004001000000000000000100000000000000",
INIT_41 => X"9454AA062A006AE640D5A002AAAA01C0400101C040D555D5550155D5DABFFEB7",
INIT_42 => X"0CC3303033300CC354551450145054540050050000D014155AA51695A02B5555",
INIT_43 => X"F0FF1F00AA2AA8AAAA2AA8AAAA0A80AAA0AAAA0AAA0A80AAA8AAAAAA00333330",
INIT_44 => X"F03FFCFCFCFFF0FFFCFFF0FFFFFFFFFF14500A00000000A0AAAAA82AF0D67F2A",
INIT_45 => X"22D63416D27474343426263232D4D45050F4F43F1ED2FCFFFCFCFCFF00FC00FC",
INIT_46 => X"541A1A16163636E8E85858FCFC04EE381A1A1A1AD8D81E1ED2D23A3A5252D6D6",
INIT_47 => X"60F71088231499E7D8B902A080400F0703010F0F030E06041C18180830142454",
INIT_48 => X"AAAA010000400000014001000040000001000100000000000100010000000000",
INIT_49 => X"10116A020A00A62AA0959000E28B01404001014040555D555D015D556AAFDEBF",
INIT_4A => X"0CCCF0F3F3330CCC545454551450501554550D00005045515AA50000800A1416",
INIT_4B => X"F0FF0700FF3FFCFFFC3FFCFFFF0FC0FFC0FFFF03FF03C0FFF0FFFFFFF0F3F333",
INIT_4C => X"F03FFCFFFCFFF0FFFCFFF0FFFFFFFFFF54550A00000000A0FFFFFC3FB0F51F0A",
INIT_4D => X"EDECECECECECECECECECECEDEDEC0008100800081008FCFFFCFFFCFFFCFFFCFF",
INIT_4E => X"333A3C4E47633CA3A93C654BA36347520042521024425226171424EDECECECED",
INIT_4F => X"609C859B8501A90ADD9AEE3F1FC00000000001004241962D698D0F55E1AA7887",
INIT_50 => X"AAAA010000500000055001000050000005000100000000000500010000000000",
INIT_51 => X"0001AA0006006A0A280250002AAC0140500501405055555555055555AAAAFEBD",
INIT_52 => X"0CC3303333330CC3501450151450400554150500005041445695000040068000",
INIT_53 => X"C0FF0100AA2AA8AAA80AA02AAAAA80AA80AAAA00AA0280AAA0AAAA2A30303333",
INIT_54 => X"F00FF03FF03FF003F03FF0FFFFFFFFFF50150A00000000A0AAAAA00A60FD1F00",
INIT_55 => X"050505BFBFB3A79B8F83776B5F53473B2F23170BA25DF03FF03FFCFFFC3FFCFF",
INIT_56 => X"070007000000010200000401000201000001010505212105050D050505050505",
INIT_57 => X"1C18161428242215901AE000020303020007080F050202000008010303010600",
INIT_58 => X"AAAA0140C1510040D5750140C151004055410100C1410000D5410100C1410000",
INIT_59 => X"000028000000A803200A140128280140D5750140D575D575D575D575AAAAFAAF",
INIT_5A => X"303030F3F3333030000000000000000000000500007000005285000000020000",
INIT_5B => X"00FF0000FF3FFCFFF003C00FFFFFC0FF00FC3F00FF03C0FFC0FFFF3FF0F3F333",
INIT_5C => X"00000000000000000000F0FFFFFFFFFF00000A00000000A0FFFFC00360FF0700",
INIT_5D => X"E7E7E7E7E7BD7E3F00BD7E3F00BD7E3F00BD7E3F00BD00000000000000000000",
INIT_5E => X"1E1D1D1D1D1C1C1C1C1B23232323231B1B1B1B1A1A1A1A19191919181818181B",
INIT_5F => X"60EFD0CADB9106A098DB91F0A900A0DBD6200FA223232323231B1F1F1F1E1E1E",
INIT_60 => X"11100F0E0F1E1F1E1F1E1F1E1F0E0F0E0F0E0F0E0F131412141315141C1E1C1E",
INIT_61 => X"0404050505060606080B06080B06080B2C3312111011100F100F0E0F0E0D0E10",
INIT_62 => X"0202020303030404040505052D3413121112111011100F100F0E080203030304",
INIT_63 => X"040404040404040A0A0A0A0A0A0A0A040404040D0D0D0D0E10121415181B0801",
INIT_64 => X"9320939393200E1814110E0F11131516191C1B1A19181732939495969798999A",
INIT_65 => X"172B9717189417921491128F10111291928D9291928E9291928F139393209393",
INIT_66 => X"009440608D8D8D8D8F919294979C97970F8F8F208F208F8B8F208F8B8F208F8B",
INIT_67 => X"0E0C8A860E0C8A86608A8A8A8A8A2E2D2E2F300F1915120F408F009000920093",
INIT_68 => X"D1D1D0D0CFCF10313231D1D12F313231D1D1328F8F8FCF8F8F8F8F8F8FCF8F8F",
INIT_69 => X"2D2F722F726F8F8F8F6F8D9F171214170F0D0F10111250D2D4D4D3D3D3D3D2D2",
INIT_6A => X"342F342F342F342F342F342F342F342F303234549494767F367F767734729292",
INIT_6B => X"2C2A16262430082C18300C2C142E1C2A28262410343034303431343194949431",
INIT_6C => X"2626300A2C2A280E24102E182A122E2A300A2C1A28262430023012280628142E",
INIT_6D => X"47472F17472F17170022201E141210161412100604020006040200042E0C2E06",
INIT_6E => X"0A080604020022201E1C1818141410100C0C0808040400000000000000000000",
INIT_6F => X"080422201E181A18121012100A080A080200020022201E0C0A08060402000E0C",
INIT_70 => X"045E4040227C04008E8E8E8C008080808080808282007C7C7C7C7C7C7E7E1810",
INIT_71 => X"CF040402000402010092929290008A8A88888A8A88880086868484868684847C",
INIT_72 => X"23F0AD23EFAE488A48E7234C051A4BE72343C21A4B051B4BE72343E7234FE723",
INIT_73 => X"488A4811D07DA93F853D86248523EAAD23E9AE488A4824D06AA9358536862485",
INIT_74 => X"3D86248523EEAD23EDAE488A4842D01FBE8D93A93B853986248523ECAD23EBAE",
INIT_75 => X"FB1088248504A04898488A48DAD0B4A9AEE602D0ADE6A1E60290A10686E63F85",
INIT_76 => X"E0A93C8550A9484068AA68A8681FBE8D57A9FDFC20DBC2200B1028A50F1028A5",
INIT_77 => X"40681FBE8DD9A9348539A93C854BA9480BD0F0A93B8524852322AD2322EE3485",
INIT_78 => X"1DD02301ADFA10CAEF3E2007A2F44A20F2E620F790204AD085A5AFE60290AF06",
INIT_79 => X"B2B560F610CAF385200330B2B507A2FDEF2010A023058D01A916D0E9052305AD",
INIT_7A => X"908906F79021003E20381E600FB021003E20381E0810AFA50DF00A29BAB512D0",
INIT_7B => X"2038FE21289D986795C8F9F0A803D0CCB12128BCCD85EEA9CC852118BD89E61C",
INIT_7C => X"E87D18E3B9B941951A9017C91EB0C0C9417518E3B9B95495547518E3AAB9BAB4",
INIT_7D => X"94D022E81D07290AD02130BC54B522E89D0BA902D0FFC906F000A904D00CC922",
INIT_7E => X"1DB0D7142098CE8549B01EC929B024C9F42B206038F022E8BD06F00729F0424C",
INIT_7F => X"F2804CBA9505F004294AD728200DD022E8BCF3852021305E15D00229CE054A4A",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"D00429CE054A4AE4B024C92600B9C8CE8512B01EC9F2B024C9F42B20F91005A9",
INIT_01 => X"6CCD85F0A9CC85E4BDB90FA002900FC9A84AD72820D2100AA9F3852021305EDC",
INIT_02 => X"1B90F0850F69F0A523F00A29BAB529D02130BD2E9004E03230B2B5F02B2000CC",
INIT_03 => X"4CF0FB2060618508691854B54E8541B5EF86F4D820B294C87485DEA917D0EFA4",
INIT_04 => X"FB20E1100E29F0FB205C100329F0FB20EF100729F0FB20F6100B29F0FB20F280",
INIT_05 => X"0C29F0FB20381001A93C100929F0FB20CF100D29F0FB204A1002A94E100629F0",
INIT_06 => X"CEA5CC85CC25F0FB20CC850B4901A902F0E229D71E20291004A92D1008A93110",
INIT_07 => X"F00A29BAB5F2804CCCA5F1E74CF729CCA507D00EC9F2804CFD29CCA507D001C9",
INIT_08 => X"501008299803D002299808D00429980DD00129A8F2A220600A09BAB560050903",
INIT_09 => X"0410CCA5CE85F2A220391001299803D004299808D00229980DD00829A8F2A220",
INIT_0A => X"10D00429CEA516D00229CEA51CD00829CEA50CB0CCC5FF490210CDA5CC85FF49",
INIT_0B => X"5C20BA9502A921309D00A9F25C4CBA950229CEA504D00829CEA50AD00129CEA5",
INIT_0C => X"CE8541B5CD8510A9CC8554B5D0856041950AB29580A907D0023054B5F38520F2",
INIT_0D => X"03F00A29BA950AF02130BCC0D020309DF1A922F09D75A90CD0F3FE20CF85BFA9",
INIT_0E => X"5C20BA952130FED09005B010C054B44A0990BFC041B404A91CD0D0256021389D",
INIT_0F => X"009BB987A405D088A52DF022F0DD92A9D8850F49F0FB20CC85F13A4CF3854CF2",
INIT_10 => X"ACE8851AB0E865184A4A4A4A4AF2A5E88528B0E8652CB023046D31B00A69180A",
INIT_11 => X"20CCA5F28500A9E885F2804CBAB591D022F0DD92A9F25C20BA95CCA513F02303",
INIT_12 => X"03F00A29F2264CD0A568F1D94C6823038D04A909D0D02504F0D8C4D0A448F28D",
INIT_13 => X"6021289D00A96795EE00B9A821189DE7F7B9A821305D4A21381D04298A21389D",
INIT_14 => X"4CCF8540A5CE8541B5CD8553A5CC8554B5D08500CC6CCD842030BCCC8422F0BC",
INIT_15 => X"B507A260D0A502D0D02560686821389D03F00A29BA950CF02130BCF28D20F3FE",
INIT_16 => X"01A922F09D09A909D0E9A50D9003C922E8BD14D004C9BAB51AD02130BD1F30B2",
INIT_17 => X"88C400A023D00EC921F0C0C9F1E6982E904A2300ADA835F0F1A560DA10CABA95",
INIT_18 => X"605285F18500A904106BA9658538A97885E4AAB912A0029012C09BB487A60AD0",
INIT_19 => X"AD5FD02305AD27F088ED10CAC820309DF1A922F09DE4CDB90C30B2B500A007A2",
INIT_1A => X"23018D01A943B0E1E0DD98AA4A4A4C9004C99BB587A604D088A5589003C92301",
INIT_1B => X"F1A922F09D92A9FDEF200DA005F002C90629980CD04029FA30A8B2B5CA08A260",
INIT_1C => X"856020389DE3CAB921009DE3C9B9A80A2A23050D4A21301D04298AE9E620309D",
INIT_1D => X"CEA4CC8514B0CD46CCA5CC85CC0502A90690D71420CEA5CC8511B0CD46CD46CD",
INIT_1E => X"0508A9069024C9D71E20CC8511B0CD46CCA5CC85CC0504A9069024C92600B9C8",
INIT_1F => X"00A060CCA5CC85CC0510A9069024C92600B988CEA4CC8514B0CD46CCA5CC85CC",
INIT_20 => X"05B00BF0CD85CFE538CEA5A802099804D0A808099806B00CF0CC85CDE538CCA5",
INIT_21 => X"0A0F492490B9A84A4A0BE93841B5CC854A4A4A54B56098A801099860A8040998",
INIT_22 => X"38BDCC854A4A0F29FF497DE64E101BF07DA51EF0EFA6602600B9A8CC050A0A0A",
INIT_23 => X"C92600B9C87CE611D0022902A22138BDF42B20606795ECF8B9A82ACCA54A4A21",
INIT_24 => X"2007A0EFA67CC6F310CA05B024C92600B9887CC67CC611D07CE6F310CA18B024",
INIT_25 => X"A40CF07DC509D0EAF8B96185EDFEF93854B57DA41FF07DC5FF4915107CA5FDEF",
INIT_26 => X"7D85E8A97C8500A90E30AFA57485DEA9F8D02302CEF7604C7DE67485EAFCB97D",
INIT_27 => X"A6F610CACEA6F50D20CE8604A2D48500A960B295EF854E8500A96023028D07A9",
INIT_28 => X"6CD385E0B8B9D285E0B0B9D4E6F99002C0C3B4608386E8848605F084A509D0D4",
INIT_29 => X"08C9E9B019C9FBB5FBF66F94A6A002F00829FBB556A0F6B14CFDEF200BA000D2",
INIT_2A => X"07E9049007C9FBB5F6F017C049B4D510CEA6F2BD4C23048D20A905D018C9CA90",
INIT_2B => X"F00AC9FAB00CC90CE949B5D085EDA9689006C0FBB44995E3D9F93849B5A8F8D0",
INIT_2C => X"0020B0D03DF02CC941F030C9459024C9BEB0F0E0C3002050D00BC919F004C92F",
INIT_2D => X"20CF84C8A007B024C9C30020CF8574A9291026009D14A9A5D030C9349024C9C3",
INIT_2E => X"00B2B907A0CEA6FD432003B024C9C30A2068AA49B5485CB5CEA6CF85A5A9FD43",
INIT_2F => X"3F90D622200041B903D02120B905D006C968D0850054B94857F002C95B308629",
INIT_30 => X"B2994109F92900B2B9D2A4FDEF2005A0D2842550998A0DD0402900B2B9004199",
INIT_31 => X"88F7C82003D07BC4CEA667964E85EF8500A906D0EFC4A2A20CF0042998A4A200",
INIT_32 => X"A9E38401A0FDEF2005A005D0E3A4F7C82040851690D6222040A5D08553A59B10",
INIT_33 => X"00B2B907A023279DF6B120259010C9FBB5FBF623048D00A9F2BD4CFBF66685A0",
INIT_34 => X"01C919D0E9A4FDEF4C06A0E8108800419900A92327FE08D02550D98A0EF04029",
INIT_35 => X"E0A9B9F4F02327BC60C3F6FB9500A90690E2C0D9FBB5FBF66F95E0BCB96077F0",
INIT_36 => X"C8E38400A007F0E3A5F1854A03D002C9C8A5C8E6D4C64995C39500A9E2D008A0",
INIT_37 => X"0A9888BAF02327BCEC108800B2990A04F0402900B2B90BD02550D98A07A08484",
INIT_38 => X"3FD0E3A5F3204CDF7520E0F0BDCAE0F0BCD2A6DF7520D286E0F0BCE8E0F0BDAA",
INIT_39 => X"FF4904B041F53840A525B005C90169FF4904B054F53853A534B002C9B2B507A2",
INIT_3A => X"60C310CAFDEF4C0CA0F7C8206685C155BDC031BE80A4848501A916B007C90169",
INIT_3B => X"04B04EE53840A5E6B07DC54A4A4A0369FF49F1B053E53807E93861A5FBD0E3A5",
INIT_3C => X"8504307BA408D0B1C60CF0B1A5D6BA20B6F0EF85B29500A9D7B00AC90169FF49",
INIT_3D => X"EDA5EE8518D0ECA50AF008290E300A1130B2B515307BA647102EF0E2A4EC85EB",
INIT_3E => X"F0EAA5F7D0E3A5FBD0E1A560518550854F8500A97B85FFA9E285EE8500A912F0",
INIT_3F => X"E2A50FD0F8C620F81220CCF001C99DA5F7F64CF95220FDEF2008A0EE8501A9F3",
INIT_40 => X"0A2A00A96AE2A5084BB06A6A80A560E285FFA960B6D001C99DA506D09DC5E2E6",
INIT_41 => X"CD854AE2A51DD0E4D5B9A84AE2A54F8540A562850669CC651853A5163028CC85",
INIT_42 => X"DEA57685DEA57585E5C2B9CDA44F8540A56285CEE502E9CCE53853A5CE850A0A",
INIT_43 => X"65180AE2A57785E5BAB97685E5BCB97585E5B4B9CDA4CD854AE2A52910607785",
INIT_44 => X"B9A84AE2A5CC85CC65CC6518CC850129E2A5FA0B4CBFA90290C0C903694065E2",
INIT_45 => X"B017C9056902D0ACC075A409E9CCE53840A57785E5AAB97685E5ACB97585E5AE",
INIT_46 => X"CC8505E93862A5F8DE4C01695365180AE2A50B301EB06A6A80A5FA0B4C17A902",
INIT_47 => X"E938CCE53840A5CC85E265180AE2A5F9014C4FA50510F90A4CCD8504E9384FA5",
INIT_48 => X"2C90CCE53854B533F004C90C2939300A3C30B2B507A2CC8505E93862A5CD8509",
INIT_49 => X"03D0EFE47B8612B008C91690CDE53841B502D02120BD05F00229B2B528B006C9",
INIT_4A => X"4F8540A5628553A59D8500A90EA260EBA5BD10CA60EB8501A9B29507A9F4E620",
INIT_4B => X"CAE1F72006D00229D66020C8E1F72003D0E4A523303EB06A6A80A502A2F42B20",
INIT_4C => X"CA88E1F72007D00829D6602007F0E4A5631003494A01E93806F0072953A5F210",
INIT_4D => X"F72006D00129D66020A810E93898E1F72003D0E4A529104A104A072953A5F210",
INIT_4E => X"200BD00429D6602007F0E4A51F102490B9A8FF490DE905F0A8D73020EE10CAE1",
INIT_4F => X"38609D850BA902900CC99D651800102490B9A8D73020EE10CAA810691898E1F7",
INIT_50 => X"1803D077C45085F9FF2006691803D076C4ACA04F856017A902B017C904900CE9",
INIT_51 => X"02292337BC2530B2B5CE8607A26064856385628502691853A55185F9FF200669",
INIT_52 => X"FB092003D0233FDE0BD004C0FAE44CF32020F18A2015D0233FDE0ED005C021F0",
INIT_53 => X"0290C0C9036921209D41B522F89D67B514D02337BD47D07BE44BF0EBA5FAE44C",
INIT_54 => X"FDEF200AA0C5D004C92337BDFDEF2009A0FAEC20233F9D20A92337FE4195BFA9",
INIT_55 => X"9D20A927D0233FDE2CF00229B2B52F10233F9D1EA923479D80A5B295FB29B2B5",
INIT_56 => X"D07BE441952120BD679522F8BDB295F829B2B5FAE44CFAEC2006F02337DE233F",
INIT_57 => X"0A04298ACF85CF650A4A4A2138BDCF84882337BCFA354C1F30CACEA6F7C82003",
INIT_58 => X"298AA84A4A98F810C803900CE93804E92120BD00A0CE86606795E5D8B9A8CF65",
INIT_59 => X"A941952120BD5495029054D508A96795E5D0B9C8C8C8C804D023473D4A0AF004",
INIT_5A => X"D0CA8B950FA205A9602337FE233F9D1EA9CEA6DF752000A9A8E5C8B924C19D01",
INIT_5B => X"90BDAA4A4AD7855FF00040B964D0DEC524C0B9DD8400A0DF85C4A9DE8501A9FB",
INIT_5C => X"B4DBD620D9852400B905F012C9DDA5A84AD8850066B9DA851069180053B9AA24",
INIT_5D => X"94C8DB91DAA5C8DB91D7E538EAAC7DDFA5C8DB91D9A5C8DB91D8A51CB03DC08B",
INIT_5E => X"D00C9012C0C8DDA4C4D0CA03B0EAACDD04E90790EAACDD0790D7A5E0C9D8A58B",
INIT_5F => X"0EA29A84FC1D200FA2FB654CDEC605F0DEA5FB6B4CD9851FCFADDF851FCEAD0D",
INIT_60 => X"DBD620D1CA4C8185404981A5F3D0CADB9100A9C88BB4DBD6200FA29984FC1D20",
INIT_61 => X"BD07A2D69C208185404981A5D69C20D1BE2060F710CAC8DB91EAF4BD03A28BB4",
INIT_62 => X"95EDB7BD12A2AD8523F18D1BBE8DED10CAB29500A921109DE7EFBD21089DEE37",
INIT_63 => X"CE8501A9DBD6200AA22322EE4886A5231D8DD6722011A2F310CA5395EE18BD40",
INIT_64 => X"357954B5A835B04A2108BDCEE66030B2B507A2CEC64807296FB04A72B04AADA5",
INIT_65 => X"EE0BB9059028A81E69029004E00848684A9845F0F18A20CEC6079096C95495C0",
INIT_66 => X"6795EE0BB9A81E69029004E0486841F617F025D02110DD54B56795EE02B903B0",
INIT_67 => X"FCF086C5681CF0CEA5689910CA21109DE1AAB92108BC2108FE0CD02110DD41B5",
INIT_68 => X"D08ADDB120E9F92068FC714C36F0A0A5DE6D20FB6120F810CA8B95EABDBD0FA2",
INIT_69 => X"DF044C01A2DD87203FFA2026A00AD08ADDB12000A9DD87203FFA2026A000A20A",
INIT_6A => X"6C64E0DC7454E0DC6434E0DC6C2CE0DE841CE0DC646026009DCFB1A84A24E938",
INIT_6B => X"E0BE4846C47E5A3EC47E5C36C47E5E2EC47E5C26C47E5A000044E09C7C74E0DC",
INIT_6C => X"984EE07E8E46C47E5C3EE07E5236E07E502EC47E5A26C47E6056E07E4E000068",
INIT_6D => X"C47E5C5CC47E5E54C47E5844C47E5C3CE07E5634E07E502CE07E54000068E07E",
INIT_6E => X"8074E0DC7064E0DC7854E0DC6834E0DC702CE0DE861CE0DC6800006CE07E8E64",
INIT_6F => X"06CD86A5FF2B4CE5F320607F8402907FC400005FE03A5E24E03A58000044E09C",
INIT_70 => X"00A90BF0A8A52303CE03F02303AD2301CE03F02301ADF3E623068D3B6917D023",
INIT_71 => X"03D0E2BF2025B027D004F009C908F005C90AD07FC57EA5607F857E851A851985",
INIT_72 => X"F7108800F4992350B906A00B30FF672005F0E2BF207F8400A07E857FA5E5F320",
INIT_73 => X"F4C67A85E9B1BD7EA6B110F8C683D0830584A589F0EDA50AD0E2BF2095F07EA5",
INIT_74 => X"03D0E2BF208A0CD0C03BDD98F9A4F9E64E10F4851985F68500A90A10F6245C10",
INIT_75 => X"BD11F01F2979B1F4852A2A2A0A60291785F68579B17985C200BDFF2B4CE3EF20",
INIT_76 => X"4EBD1585EC69B903D00F29C226BD1985EC38B903F009E0EC71B90AD00F29C239",
INIT_77 => X"B1FAA4FAE6601A85F585F78500A90910F7243C10F5C6798510F0C213BDF885C0",
INIT_78 => X"85EC54B903D04A4A4A4AC239BD0CF01F2979B1F5852A2A2A0A60291885F78579",
INIT_79 => X"05830584A524B005E07E857EA67F851A85198500A96016854A4A4A4AC226BD1A",
INIT_7A => X"A004F001E008F004E0FDEF4C03A002F0E90502A02305AD0EF0EDA51AD08505E3",
INIT_7B => X"3438393129432843434760FA84F984FA108800F49900A904A0ED1001A0F11004",
INIT_7C => X"33BDCDA95F5C770901722B5D99E3E7DA64E55D4D743F9E0AA13E657236C66F01",
INIT_7D => X"5B3EBE08C484AA50B29B88ED3A1578D792D88BD9584E7278149C7A04D3746AC7",
INIT_7E => X"F6C0ACEB97C5EA112D5AD2F7848D6DB113D52C23BC82569D4D1F43A0E804AB61",
INIT_7F => X"EED8D000C15FC7FFCC9956F585465C4E9AC3B3F78A55DDBAEBF7C431BC62E3CF",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_71\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_prim_width is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\addra[12]\ : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end DIGDUG_ROM_blk_mem_gen_prim_width;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.DIGDUG_ROM_blk_mem_gen_prim_wrapper_init
port map (
addra(11 downto 0) => addra(11 downto 0),
\addra[12]\ => \addra[12]\,
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_ena : in STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \DIGDUG_ROM_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\DIGDUG_ROM_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
ram_ena => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end DIGDUG_ROM_blk_mem_gen_generic_cstr;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_generic_cstr is
signal \bindec_a.bindec_inst_a_n_0\ : STD_LOGIC;
signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_douta1_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_douta3_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_douta5_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_ena : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.DIGDUG_ROM_bindec
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ => \bindec_a.bindec_inst_a_n_0\,
addra(1 downto 0) => addra(13 downto 12),
ram_ena => ram_ena
);
\has_mux_a.A\: entity work.DIGDUG_ROM_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7 downto 0) => ram_douta3_out(7 downto 0),
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_douta1_out(7 downto 0),
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7 downto 0) => ram_douta5_out(7 downto 0),
DOADO(7 downto 0) => ram_douta(7 downto 0),
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
\ramloop[0].ram.r\: entity work.DIGDUG_ROM_blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
\addra[12]\ => \bindec_a.bindec_inst_a_n_0\,
clka => clka,
\douta[7]\(7 downto 0) => ram_douta5_out(7 downto 0)
);
\ramloop[1].ram.r\: entity work.\DIGDUG_ROM_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => ram_douta3_out(7 downto 0)
);
\ramloop[2].ram.r\: entity work.\DIGDUG_ROM_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => ram_douta1_out(7 downto 0)
);
\ramloop[3].ram.r\: entity work.\DIGDUG_ROM_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7 downto 0) => ram_douta(7 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
ram_ena => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_top : entity is "blk_mem_gen_top";
end DIGDUG_ROM_blk_mem_gen_top;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_top is
begin
\valid.cstr\: entity work.DIGDUG_ROM_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end DIGDUG_ROM_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.DIGDUG_ROM_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM_blk_mem_gen_v8_2 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "Estimated Power for IP : 2.326399 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "DIGDUG_ROM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "DIGDUG_ROM.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of DIGDUG_ROM_blk_mem_gen_v8_2 : entity is "yes";
end DIGDUG_ROM_blk_mem_gen_v8_2;
architecture STRUCTURE of DIGDUG_ROM_blk_mem_gen_v8_2 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.DIGDUG_ROM_blk_mem_gen_v8_2_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity DIGDUG_ROM is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of DIGDUG_ROM : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of DIGDUG_ROM : entity is "DIGDUG_ROM,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of DIGDUG_ROM : entity is "DIGDUG_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=DIGDUG_ROM.mif,C_INIT_FILE=DIGDUG_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of DIGDUG_ROM : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of DIGDUG_ROM : entity is "blk_mem_gen_v8_2,Vivado 2015.2";
end DIGDUG_ROM;
architecture STRUCTURE of DIGDUG_ROM is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.326399 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "DIGDUG_ROM.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "DIGDUG_ROM.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.DIGDUG_ROM_blk_mem_gen_v8_2
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13) => '0',
addrb(12) => '0',
addrb(11) => '0',
addrb(10) => '0',
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7) => '0',
dina(6) => '0',
dina(5) => '0',
dina(4) => '0',
dina(3) => '0',
dina(2) => '0',
dina(1) => '0',
dina(0) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
| gpl-2.0 | 877a374bcc6dffbaa80adbae33342ca2 | 0.69275 | 2.733163 | false | false | false | false |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/imports/dsp_base_project/low_pass_moving_average.vhd | 1 | 1,628 | ------------------------------------------------------
-- low_pass : A generic DSP low pass filter.
--
-- It is a moving sum, as it doesn't divide by the
-- number of samples. Make sure that data_width is wide
-- enough that no overflows occur - you might have to
-- add leading zeros to sample_in!
--
-- PS. Also note that sample_in is unsigned.
--
-- Author : Mike Field <[email protected]>
--
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity low_pass_moving_average is
generic ( data_width : natural := 16;
window_width : natural := 5);
Port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
sample_in : in STD_LOGIC_VECTOR (data_width-1 downto 0);
sample_out : out STD_LOGIC_VECTOR (data_width-1 downto 0));
end low_pass_moving_average;
architecture Behavioral of low_pass_moving_average is
signal total : unsigned( data_width-1 downto 0) := (others =>'0');
signal end_sample : STD_LOGIC_VECTOR ( data_width-1 downto 0);
signal delay_line : STD_LOGIC_VECTOR (window_width * data_width-1 downto 0) := (others => '0');
begin
end_sample <= Delay_line(Delay_line'high downto Delay_line'high-data_width+1);
sample_out <= std_logic_vector(total);
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
total <= total + unsigned(sample_in) - unsigned(end_sample);
delay_line <= Delay_line(Delay_line'high-data_width downto 0) & sample_in;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 0a353fed77c73e63f8a1dd4e620a38cd | 0.596437 | 3.593819 | false | false | false | false |
MonsieurOenologue/Paprotto | composants_fonctionnels/fsm.vhd | 1 | 3,540 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fsm IS
PORT(
clk, reset, run : IN STD_LOGIC;
IR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
R0, R1, R2, R3, R4, R5, R6, R7, Aset, Gset, IRset, done : OUT STD_LOGIC;
multSel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := "ZZZZ";
aluSel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := "ZZZZ"
);
END ENTITY fsm;
ARCHITECTURE Behavior OF fsm IS
TYPE fsm_states IS (ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7);
SIGNAL current_state, next_state : fsm_states;
SIGNAL mults, CODOP, mults2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RegChoice : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
CODOP <= IR(15 DOWNTO 12);
RegChoice <= IR(11 DOWNTO 9);
mults <= IR(8 DOWNTO 5);
mults2 <= IR(4 DOWNTO 1);
NSL : process(current_state, run, CODOP)
BEGIN
next_state <= current_state;
CASE current_state IS
WHEN ST7 =>
IF run = '1' THEN
next_state <= ST0;
END IF;
WHEN ST0 =>
CASE CODOP IS
WHEN "0000" =>
next_state <= ST1;
WHEN "0001" =>
next_state <= ST2;
when "0010" =>
next_state <= ST3;
WHEN "0011" =>
next_state <= ST3;
WHEN "0100" =>
next_state <= ST3;
WHEN others =>
next_state <= ST0;
END CASE;
WHEN ST1 =>
next_state <= ST6;
WHEN ST2 =>
next_state <= ST6;
WHEN ST3 =>
next_state <= ST4;
WHEN ST4 =>
next_state <= ST5;
WHEN ST5 =>
next_state <= ST6;
WHEN ST6 =>
next_state <= ST7;
END CASE;
END PROCESS NSL;
OL : PROCESS(current_state, run, RegChoice)
BEGIN
R0 <= '0';
R1 <= '0';
R2 <= '0';
R3 <= '0';
R4 <= '0';
R5 <= '0';
R6 <= '0';
R7 <= '0';
Aset <= '0';
Gset <= '0';
multSel <= "0000";
aluSel <= "0000";
IRSet <= '0';
CASE current_state IS
WHEN ST7 =>
IF run = '1' THEN
IRSet <= '1';
done <= '0';
END IF;
WHEN ST0 =>
WHEN ST1 =>
multSel <= "0000";
CASE RegChoice IS
WHEN "000" =>
R7 <= '1';
WHEN "001" =>
R6 <= '1';
WHEN "010" =>
R5 <= '1';
WHEN "011" =>
R4 <= '1';
WHEN "100" =>
R3 <= '1';
WHEN "101" =>
R2 <= '1';
WHEN "110" =>
R1 <= '1';
WHEN "111" =>
R0 <= '1';
WHEN others =>
END CASE;
WHEN ST2 =>
multSel <= mults;
CASE RegChoice IS
WHEN "000" =>
R7 <= '1';
WHEN "001" =>
R6 <= '1';
WHEN "010" =>
R5 <= '1';
WHEN "011" =>
R4 <= '1';
WHEN "100" =>
R3 <= '1';
WHEN "101" =>
R2 <= '1';
WHEN "110" =>
R1 <= '1';
WHEN "111" =>
R0 <= '1';
WHEN others =>
END CASE;
WHEN ST3 =>
multSel <= mults;
Aset <= '1';
WHEN ST4 =>
multSel <= mults2;
aluSel <= CODOP;
Gset <= '1';
WHEN ST5 =>
multSel <= "1001";
CASE RegChoice IS
WHEN "000" =>
R7 <= '1';
WHEN "001" =>
R6 <= '1';
WHEN "010" =>
R5 <= '1';
WHEN "011" =>
R4 <= '1';
WHEN "100" =>
R3 <= '1';
WHEN "101" =>
R2 <= '1';
WHEN "110" =>
R1 <= '1';
WHEN "111" =>
R0 <= '1';
WHEN others =>
END CASE;
WHEN ST6 =>
done <= '1';
END CASE;
END PROCESS OL;
SM : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF reset = '1' THEN
current_state <= ST6;
-- done <= '1';
ELSE
CODOP <= IR(15 DOWNTO 12);
RegChoice <= IR(11 DOWNTO 9);
mults <= IR(8 DOWNTO 5);
mults2 <= IR(4 DOWNTO 1);
current_state <= next_state;
END IF;
END PROCESS SM;
END Behavior;
| gpl-3.0 | 96f5964d9402b33ad15b79d6344b9ff5 | 0.479096 | 2.655664 | false | false | false | false |
545/Atari7800 | new_atari/project_1/project_1.srcs/sources_1/ip/clock_divider/clock_divider.vhd | 1 | 5,045 | -- file: clock_divider.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______144.719____114.212
-- CLK_OUT2_____7.143______0.000______50.0______244.806____114.212
-- CLK_OUT3____25.000______0.000______50.0______191.696____114.212
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock_divider is
port
(-- Clock in ports
CLOCK_PLL : in std_logic;
-- Clock out ports
CLOCK_100 : out std_logic;
CLOCK_7_143 : out std_logic;
CLOCK_25 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end clock_divider;
architecture xilinx of clock_divider is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock_divider,clk_wiz_v5_1,{component_name=clock_divider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clock_divider_clk_wiz
port
(-- Clock in ports
CLOCK_PLL : in std_logic;
-- Clock out ports
CLOCK_100 : out std_logic;
CLOCK_7_143 : out std_logic;
CLOCK_25 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
begin
U0: clock_divider_clk_wiz
port map (
-- Clock in ports
CLOCK_PLL => CLOCK_PLL,
-- Clock out ports
CLOCK_100 => CLOCK_100,
CLOCK_7_143 => CLOCK_7_143,
CLOCK_25 => CLOCK_25,
-- Status and control signals
reset => reset,
locked => locked
);
end xilinx;
| gpl-2.0 | c575c1b52f2301062d1d83151b9bf560 | 0.620218 | 4.111654 | false | false | false | false |
545/Atari7800 | Atari7900/Atari7900.srcs/sources_1/ip/CHOPLIFTER/synth/CHOPLIFTER.vhd | 1 | 13,930 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY CHOPLIFTER IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END CHOPLIFTER;
ARCHITECTURE CHOPLIFTER_arch OF CHOPLIFTER IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF CHOPLIFTER_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF CHOPLIFTER_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF CHOPLIFTER_arch : ARCHITECTURE IS "CHOPLIFTER,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF CHOPLIFTER_arch: ARCHITECTURE IS "CHOPLIFTER,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=CHOPLIFTER.mif,C_INIT_FILE=CHOPLIFTER.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=32768,C_READ_DEPTH_A=32768,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=32768,C_READ_DEPTH_B=32768,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "CHOPLIFTER.mif",
C_INIT_FILE => "CHOPLIFTER.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 32768,
C_READ_DEPTH_A => 32768,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 32768,
C_READ_DEPTH_B => 32768,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END CHOPLIFTER_arch;
| gpl-2.0 | 5b3e593a1385731203f1a9cea2038caf | 0.626274 | 3.048807 | false | false | false | false |
MonsieurOenologue/Paprotto | composants_fonctionnels/IRegister.vhd | 1 | 639 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Instruction_register IS
GENERIC(N : POSITIVE := 8);
PORT(
clk,rst,set : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END ENTITY Instruction_register;
Architecture behavior OF Instruction_register IS
SIGNAL sint: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
shift : PROCESS (clk, rst, set)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF rst='1' THEN
sint <= (others=>'0');
ELSE
IF set = '1' THEN
sint <= din;
END IF;
END IF;
END IF;
END PROCESS shift;
dout <= sint;
END ARCHITECTURE behavior;
| gpl-3.0 | 7bff2d355ef8495fdb21892d86c60031 | 0.652582 | 3.163366 | false | false | false | false |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 14,673 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_mem_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=83151,C_READ_DEPTH_A=83151,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=83151,C_READ_DEPTH_B=83151,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=35,C_COUNT_18K_BRAM=9,C_EST_POWER_SUMMARY=Estimated Power for IP _ 32.560338 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 83151,
C_READ_DEPTH_A => 83151,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "READ_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 83151,
C_READ_DEPTH_B => 83151,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 1,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "35",
C_COUNT_18K_BRAM => "9",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 32.560338 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| gpl-2.0 | 6e571481f4f5a8916b5795227aa41377 | 0.629455 | 3.015413 | false | false | false | false |
Subsets and Splits