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OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part5/lpm_constant0.vhd | 2 | 3,509 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i3",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "i3"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i3"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | d6a415d2b65671ebc18e805e692c604b | 0.646338 | 3.801733 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part5/lpm_constant2.vhd | 1 | 3,509 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I1",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I1"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | a94b3ce7918e3e425a2d202f087312df | 0.646338 | 3.801733 | false | false | false | false |
notti/dis_lu | test/tb_core.vhd | 1 | 2,146 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_core is
end tb_core;
architecture behav of tb_core is
signal clk : std_logic := '0';
signal rst_n_i : std_logic:='0';
signal address : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal lcd_wr : std_logic;
signal lcd_out : std_logic_vector(7 downto 0);
signal rightInt : std_logic := '0';
signal leftInt : std_logic := '0';
signal pushInt : std_logic := '0';
signal switch_i : std_logic_vector(3 downto 0) := (others => '0');
begin
process
begin
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
begin
wait for 100 ns;
rst_n_i <= '1';
wait for 100 ns;
pushInt <= '1', '0' after 20 ns;
wait for 400 ns;
switch_i(0) <= '1';
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
switch_i(0) <= '0';
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
rightInt <= '1', '0' after 20 ns;
wait for 400 ns;
pushInt <= '1', '0' after 20 ns;
wait for 1000 ns;
assert false report "done" severity failure;
wait;
end process;
mem_inst: entity work.memory
port map(
address => address,
data => data
);
cpu_core: entity work.core
port map(
clk => clk,
rst => rst_n_i,
address => address,
data => data,
lcd_out => lcd_out,
lcd_wr => lcd_wr,
rightInt => rightInt,
leftInt => leftInt,
pushInt => pushInt,
switch => switch_i
);
end behav;
| mit | 613c4e8c41a11defe4e5002105db2c7c | 0.493476 | 3.59464 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_or7x16_inst.vhd | 2 | 241 | gl_or7x16_inst : gl_or7x16 PORT MAP (
data0x => data0x_sig,
data1x => data1x_sig,
data2x => data2x_sig,
data3x => data3x_sig,
data4x => data4x_sig,
data5x => data5x_sig,
data6x => data6x_sig,
result => result_sig
);
| unlicense | cf0f7447fb4c302c302fbf87b3802151 | 0.609959 | 1.991736 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_dff0.vhd | 2 | 4,103 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff0.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_dff0;
ARCHITECTURE SYN OF lpm_dff0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enable : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 5
)
PORT MAP (
enable => enable,
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | e7775a5eacc0cfebe2a9ef29127eb0da | 0.638801 | 3.602283 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_dff9.vhd | 2 | 3,893 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff9.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 215 05/29/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_dff9 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END gl_dff9;
ARCHITECTURE SYN OF gl_dff9 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(8 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 9
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL data[8..0]
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL q[8..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
-- Retrieval info: CONNECT: @data 0 0 9 0 data 0 0 9 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff9.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff9.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff9.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff9.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff9_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | cb6dbf0438338de67a77e3789a9482fc | 0.636527 | 3.61803 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part4/part4.vhd | 1 | 929 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- simple module that connects the buttons on our Master 21EDA board.
-- based on labs from Altera
-- ftp://ftp.altera.com/up/pub/Altera_Material/11.1/Laboratory_Exercises/Digital_Logic/DE2/vhdl/lab1_VHDL.pdf
ENTITY part4 IS
PORT (LED_EN : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- our 7 segment displays
A : IN STD_LOGIC;
B : IN STD_LOGIC ); -- our buttons
END part4;
ARCHITECTURE Behavior OF part4 IS
BEGIN -- entry from truth table=segment of display
LED(7) <= '1'; -- F(7)=DP is always off
LED(6) <= A; -- F(6)=G
LED(5) <= (NOT B) OR A ; -- F(5)=F
LED(4) <= A; -- F(4)=E
LED(3) <= A; -- F(3)=D
LED(2) <= B; -- F(2)=C
LED(1) <= B; -- F(1)=B
LED(0) <= (NOT B) OR A; -- F(0)=A
LED_EN <= "01111111";
END Behavior; | unlicense | e153e751987c1f27760724769da58be7 | 0.548977 | 2.930599 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/pdi/src/portio.vhd | 3 | 8,348 | -------------------------------------------------------------------------------
-- Simple Port I/O
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity portio is
generic (
pioValLen_g : integer := 50; --clock ticks of pcp_clk
pioGenIoBuf_g : boolean := true
);
port (
s0_address : in std_logic;
s0_read : in std_logic;
s0_readdata : out std_logic_vector(31 downto 0);
s0_write : in std_logic;
s0_writedata : in std_logic_vector(31 downto 0);
s0_byteenable : in std_logic_vector(3 downto 0);
s0_waitrequest : out std_logic;
clk : in std_logic;
reset : in std_logic;
x_pconfig : in std_logic_vector(3 downto 0);
x_portInLatch : in std_logic_vector(3 downto 0);
x_portOutValid : out std_logic_vector(3 downto 0);
x_portio : inout std_logic_vector(31 downto 0);
x_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
x_portio_O : out std_logic_vector(31 downto 0);
x_portio_T : out std_logic_vector(31 downto 0);
x_operational : out std_logic
);
end entity portio;
architecture rtl of portio is
signal sPortConfig : std_logic_vector(x_pconfig'range);
signal sPortOut : std_logic_vector(x_portio'range);
signal sPortIn, sPortIn_s, sPortInL : std_logic_vector(x_portio'range);
signal x_portInLatch_s : std_logic_vector(x_portInLatch'range);
signal x_operational_s : std_logic;
signal x_portOutValid_s : std_logic_vector(x_portOutValid'range);
begin
sPortConfig <= x_pconfig;
x_operational <= x_operational_s;
portGen : for i in 3 downto 0 generate
genIoBuf : if pioGenIoBuf_g generate
begin
--if port configuration bit is set to '0', the appropriate port-byte is an output
x_portio((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '0' else (others => 'Z');
--if port configuration bit is set to '1', the appropriate port-byte is forwarded to the portio registers for the PCP
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio((i+1)*8-1 downto (i+1)*8-8) when sPortConfig(i) = '1' else (others => '0');
end generate;
dontGenIoBuf : if not pioGenIoBuf_g generate
begin
x_portio_O((i+1)*8-1 downto (i+1)*8-8) <= sPortOut((i+1)*8-1 downto (i+1)*8-8);
sPortIn((i+1)*8-1 downto (i+1)*8-8) <= x_portio_I((i+1)*8-1 downto (i+1)*8-8);
--if port configuration bit is set to '0', the appropriate port-byte is an output ('0')
--if port configuration bit is set to '1', the appropriate port-byte is an input ('1')
x_portio_T((i+1)*8-1 downto (i+1)*8-8) <= (others => '0') when sPortConfig(i) = '0' else (others => '1');
end generate;
end generate;
--Avalon interface
avalonPro : process(clk, reset)
begin
if reset = '1' then
x_portOutValid_s <= (others => '0');
sPortOut <= (others => '0');
x_operational_s <= '0';
elsif clk = '1' and clk'event then
x_portOutValid_s <= (others => '0');
if s0_write = '1' then
case s0_address is
when '0' => --write port
for i in 3 downto 0 loop
if s0_byteenable(i) = '1' then
sPortOut((i+1)*8-1 downto (i+1)*8-8) <= s0_writedata((i+1)*8-1 downto (i+1)*8-8);
x_portOutValid_s(i) <= '1';
end if;
end loop;
when '1' => --write to config register operational flag
if s0_byteenable(3) = '1' then
x_operational_s <= s0_writedata(s0_writedata'left);
end if;
when others =>
end case;
end if;
end if;
end process;
s0_readdata <= sPortInL when s0_read = '1' and s0_address = '0' else
x_operational_s & "000" & x"00000" & x"0" & sPortConfig;
thePortioCnters : for i in 0 to 3 generate
thePortioCnt : entity work.portio_cnt
generic map (
maxVal => pioValLen_g
)
port map (
clk => clk,
rst => reset,
pulse => x_portOutValid_s(i),
valid => x_portOutValid(i)
);
end generate;
--latch input signals
latchInPro : process(clk, reset)
begin
if reset = '1' then
sPortInL <= (others => '0');
elsif clk = '1' and clk'event then
for i in 3 downto 0 loop
if x_portInLatch_s(i) = '1' then
sPortInL((i+1)*8-1 downto (i+1)*8-8) <= sPortIn_s((i+1)*8-1 downto (i+1)*8-8);
end if;
end loop;
end if;
end process;
-- waitrequest signals
theWaitrequestGenerators : block
signal s0_rd_ack, s0_wr_ack : std_logic;
begin
-- PCP
thePcpWrWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_write,
ack => s0_wr_ack
);
thePcpRdWaitReqAckGen : entity work.req_ack
generic map (
zero_delay_g => true
)
port map (
clk => clk,
rst => reset,
enable => s0_read,
ack => s0_rd_ack
);
s0_waitrequest <= not(s0_rd_ack or s0_wr_ack);
end block;
--synchronize input signals
genSyncInputs : for i in sPortIn'range generate
syncInputs : entity work.sync
port map (
din => sPortIn(i),
dout => sPortIn_s(i),
clk => clk,
rst => reset
);
end generate;
--synchronize latch signals
genSyncLatch : for i in x_portInLatch'range generate
syncInputs : entity work.sync
port map (
din => x_portInLatch(i),
dout => x_portInLatch_s(i),
clk => clk,
rst => reset
);
end generate;
end architecture rtl;
| gpl-2.0 | e4c6e6153d2cc02fe9854668f47ec1df | 0.537494 | 3.904584 | false | true | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/spi/src/spi_sreg.vhd | 3 | 1,407 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi_sreg is
generic (
size_g : integer := 8
);
port (
clk : in std_logic;
rst : in std_logic;
--control signals
shift : in std_logic; --shift left
load : in std_logic; --load parallel
--data signals
din : in std_logic_vector(size_g-1 downto 0); --parallel data in (latched)
dout : out std_logic_vector(size_g-1 downto 0); --parallel data out
sin : in std_logic; --serial data in (to lsb)
sout : out std_logic --serial data out (from msb)
);
end spi_sreg;
architecture rtl of spi_sreg is
signal shiftReg : std_logic_vector(size_g-1 downto 0);
begin
theShiftRegister : process(clk, rst)
begin
if rst = '1' then
shiftReg <= (others => '0');
elsif clk = '1' and clk'event then
if shift = '1' then
shiftReg <= shiftReg(size_g-2 downto 0) & sin;
elsif load = '1' then
shiftReg <= din;
end if;
end if;
end process;
dout <= shiftReg;
sout <= shiftReg(size_g-1);
end rtl;
| gpl-2.0 | 40df90e1d37ef3d00a96b1b66e06bf48 | 0.482587 | 3.96338 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part5/part5_code.vhd | 1 | 1,807 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part5_code IS
PORT(
BUTTONS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CONSTANTS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clk_in : IN STD_LOGIC;
carry_in : IN STD_LOGIC;
carry_out : OUT STD_LOGIC
);
END part5_code;
ARCHITECTURE Behaviour of part5_code IS
SIGNAL carry : STD_LOGIC;
SIGNAL HEX_0, HEX_1, BLANK: STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL s_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT circuitb PORT ( SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT;
COMPONENT bcd_adder PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));END COMPONENT;
BEGIN
BLANK <= "1111111";
S0 : segseven PORT MAP (SW=>s_o, LEDSEG=>HEX_0);
S1 : circuitb PORT MAP (SW=>carry, LEDSEG=>HEX_1);
DE1: DE1_disp PORT MAP (HEX0=>HEX_0, HEX1=>HEX_1, HEX2=>BLANK, HEX3=>BLANK, clk=>clk_in,HEX=>LED,DISPn=>DISP);
badder: bcd_adder PORT MAP (b_in=> NOT BUTTONS, a_in => CONSTANTS, c_in =>carry_in, c_out=> carry, s_out => s_o);
carry_out <= carry;
END Behaviour; | unlicense | 087889a78af66cecbc308ea4f803e5c6 | 0.590481 | 3.164623 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ram_dq_INST_nb.vhd | 2 | 7,075 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_nb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_nb IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_nb;
ARCHITECTURE SYN OF ram_dq_inst_nb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_nb",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_nb"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_nb"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_nb.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_nb.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_nb.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_nb.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_nb_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | 5a4d90da58198f5e5bb8d615f2568aca | 0.672085 | 3.439475 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_counter5b.vhd | 2 | 4,624 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: gl_counter5b.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_counter5b IS
PORT
(
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END gl_counter5b;
ARCHITECTURE SYN OF gl_counter5b IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
cnt_en : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 5
)
PORT MAP (
sclr => sclr,
clock => clock,
cnt_en => cnt_en,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL cnt_en
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | dff72b938c49a01258aa647866271356 | 0.653547 | 3.601246 | false | false | false | false |
Voveky/WSIAUSB | bus_as_cpu.vhd | 1 | 42,241 | --=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
--= Wonderfully Simple ISP1362 Altera DE2 Interface Thing =-
--= VERSION 0.1 -- data can be sent from computer to board =-
--= =-
--= ...simple description goes here... after I figure out what this thing is going to do
--=
--= I'm currently too pressed for time to make this officially public domain=-
--= or open licence but that will happen. I can't stop you from stealing my=-
--= work and claiming it as your own, but if you do, try and remember me =-
--= when the boss says you're looking to hire. Some credit and an email =-
--= wouldn't hurt if you find this useful for any sort of official project. =-
--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
library ieee, wsiaUSBlib, wsiaDescriptors;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use wsiaUSBlib.wsiaUseful.all;
use wsiaUSBlib.wsiaDescriptors.all;
entity bus_as_cpu is
port(
CLOCK_50 : in std_logic;
-- reset_n : in std_logic;
-- instruction : in worker_states;
-- w_data32 : in word32;
-- w_length : in word;
-- w_endpoint : in std_logic_vector(3 downto 0);
-- w_execute : in std_logic; --'1' => start executing instruction.
-- w_done : out std_logic;
-- w_ctrl_xfer : out byte16;
--registers
-- wi_DcAddress : in byte;
-- wi_DcMode : in byte;
-- wi_DcHardwareConfiguration : in word;
-- wi_DcEndpointConfiguration : in word;
-- wi_DcInterruptEnable : in dWord;
-- wo_DcAddress : buffer byte;
-- wo_DcMode : buffer byte;
-- wo_DcHardwareConfiguration : buffer word;
-- wo_DcInterruptEnable : buffer dWord;
-- wo_DcInterrupt : buffer dWord;
-- wo_ESR : out byte;
OTG_INT1 : in std_logic; --ISP1362 Interrupt 2 (Peripheral Interrupts)
OTG_DATA : inout std_logic_vector(15 downto 0); --ISP1362 Data bus 16 bits
OTG_RST_N : out std_logic; --ISP1362 Reset pin
OTG_ADDR : out std_logic_vector(1 downto 0); --ISP1362 Address 2 Bits[peripheral,command]
OTG_CS_N : out std_logic; --ISP1362 Chip Select
OTG_RD_N : out std_logic; --ISP1362 Write
OTG_WR_N : out std_logic; --ISP1362 Read
--IGNORE/SET AND FORGET
OTG_FSPEED : out std_logic:='0'; --USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED : out std_logic:='Z'; --USB Low Speed, 0 = Enable, Z = Disable
OTG_INT0 : in std_logic; --ISP1362 Interrupt 1 (Host Interrupts)
OTG_DREQ0 : in std_logic; --ISP1362 DMA Request 1
OTG_DREQ1 : in std_logic; --ISP1362 DMA Request 2
OTG_DACK0_N : out std_logic:='1'; --ISP1362 DMA Acknowledge 1
OTG_DACK1_N : out std_logic:='1'; --ISP1362 DMA Acknowledge 2
--DIAGNOSTICS STUFF...
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDR : out std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(8 downto 0);
HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 : out std_logic_vector(0 to 6)
);
end bus_as_cpu;
architecture handler of bus_as_cpu is
component SevenSeg is port(
inNum :in std_logic_vector(3 downto 0);
outSeg :out std_logic_vector(6 downto 0));
end component SevenSeg;
signal w_count : integer;
signal segs1 : std_logic_vector(15 downto 0);
signal segs2, segs3 : std_logic_vector(7 downto 0);
signal CLOCK_25 : std_logic;
signal cur_instruction : worker_states;
signal stack : word32;
signal SENT_DATA : word32;
signal IP, IP_JMP : word := x"0000";
signal JMP : std_logic := 'L'; --Weak 0
signal SP, SP_NEXT : unsigned(4 downto 0) := "00000";
signal EAX,EBX,ECX,EDX,nEAX,nEBX,nECX,nEDX : dword := x"00000000";
alias ax : word is eax(15 downto 0);alias bx : word is ebx(15 downto 0);
alias cx : word is ecx(15 downto 0);alias dx : word is edx(15 downto 0);
alias ah : byte is eax(15 downto 8);alias al : byte is eax(7 downto 0);
alias bh : byte is ebx(15 downto 8);alias bl : byte is ebx(7 downto 0);
alias ch : byte is ecx(15 downto 8);alias cl : byte is ecx(7 downto 0);
alias dh : byte is edx(15 downto 8);alias dl : byte is edx(7 downto 0);
alias nax : word is neax(15 downto 0);alias nbx : word is nebx(15 downto 0);
alias ncx : word is necx(15 downto 0);alias ndx : word is nedx(15 downto 0);
alias nah : byte is neax(15 downto 8);alias nal : byte is neax(7 downto 0);
alias nbh : byte is nebx(15 downto 8);alias nbl : byte is nebx(7 downto 0);
alias nch : byte is necx(15 downto 8);alias ncl : byte is necx(7 downto 0);
alias ndh : byte is nedx(15 downto 8);alias ndl : byte is nedx(7 downto 0);
--registers
signal OTG_DcAddress : byte;
signal OTG_DcMode : byte;
signal OTG_DcHardwareConfiguration : word;
signal OTG_DcEndpointConfiguration : word16;
signal OTG_DcInterruptEnable : dWord;
signal OTG_DcInterrupt : dWord;
signal OTG_ESR : byte16;
signal OTG_INT1_latch : std_logic;
signal instruction : worker_states;
signal which_interface : byte:=x"00";
signal what_config : byte:=x"00";
signal w_buffer64 : buffer64;
signal w_data32 : word32;--w_data32<=(w_buffer64(0*16+8 to 0*16+15) & w_buffer64(0*16 to 0*16+7),w_buffer64(1*16+8 to 1*16+15) & w_buffer64(1*16 to 1*16+7),w_buffer64(2*16+8 to 2*16+15) & w_buffer64(2*16 to 2*16+7),w_buffer64(3*16+8 to 3*16+15) & w_buffer64(3*16 to 3*16+7),w_buffer64(4*16+8 to 4*16+15) & w_buffer64(4*16 to 4*16+7),w_buffer64(5*16+8 to 5*16+15) & w_buffer64(5*16 to 5*16+7),w_buffer64(6*16+8 to 6*16+15) & w_buffer64(6*16 to 6*16+7),w_buffer64(7*16+8 to 7*16+15) & w_buffer64(7*16 to 7*16+7),w_buffer64(8*16+8 to 8*16+15) & w_buffer64(8*16 to 8*16+7),w_buffer64(9*16+8 to 9*16+15) & w_buffer64(9*16 to 9*16+7),w_buffer64(10*16+8 to 10*16+15) & w_buffer64(10*16 to 10*16+7),w_buffer64(11*16+8 to 11*16+15) & w_buffer64(11*16 to 11*16+7),w_buffer64(12*16+8 to 12*16+15) & w_buffer64(12*16 to 12*16+7),w_buffer64(13*16+8 to 13*16+15) & w_buffer64(13*16 to 13*16+7),w_buffer64(14*16+8 to 14*16+15) & w_buffer64(14*16 to 14*16+7),w_buffer64(15*16+8 to 15*16+15) & w_buffer64(15*16 to 15*16+7),w_buffer64(16*16+8 to 16*16+15) & w_buffer64(16*16 to 16*16+7),w_buffer64(17*16+8 to 17*16+15) & w_buffer64(17*16 to 17*16+7),w_buffer64(18*16+8 to 18*16+15) & w_buffer64(18*16 to 18*16+7),w_buffer64(19*16+8 to 19*16+15) & w_buffer64(19*16 to 19*16+7),w_buffer64(20*16+8 to 20*16+15) & w_buffer64(20*16 to 20*16+7),w_buffer64(21*16+8 to 21*16+15) & w_buffer64(21*16 to 21*16+7),w_buffer64(22*16+8 to 22*16+15) & w_buffer64(22*16 to 22*16+7),w_buffer64(23*16+8 to 23*16+15) & w_buffer64(23*16 to 23*16+7),w_buffer64(24*16+8 to 24*16+15) & w_buffer64(24*16 to 24*16+7),w_buffer64(25*16+8 to 25*16+15) & w_buffer64(25*16 to 25*16+7),w_buffer64(26*16+8 to 26*16+15) & w_buffer64(26*16 to 26*16+7),w_buffer64(27*16+8 to 27*16+15) & w_buffer64(27*16 to 27*16+7),w_buffer64(28*16+8 to 28*16+15) & w_buffer64(28*16 to 28*16+7),w_buffer64(29*16+8 to 29*16+15) & w_buffer64(29*16 to 29*16+7),w_buffer64(30*16+8 to 30*16+15) & w_buffer64(30*16 to 30*16+7),w_buffer64(31*16+8 to 31*16+15) & w_buffer64(31*16 to 31*16+7));
signal w_length : word;
signal w_endpoint : std_logic_vector(3 downto 0);
signal w_execute : std_logic; --'1' => start executing instruction.
signal w_done : std_logic;
signal w_ctrl_xfer : setup_packet_type;
type eight_ctrls is array(0 to 7) of setup_packet_type;
signal raw_ctrl_xfers:eight_ctrls;
signal e_state : enum_state;
signal IP_History : word32;
signal IP_H_View : boolean;
signal IP_H_V_num : integer range 0 to 31;
signal keylast : std_logic_vector(3 downto 0);
signal EP1_Buffer : buffer64;--EP1 --64b Bulk Out
signal EP1_Buff : word32;
signal EP2_Buffer : buffer64:=x"5400680065002000620075006700670061007200200077006F0072006B0073002100210021002000490020004C00750076002000530061007200610021002100";--EP2 --64b Bulk In
signal EP3_Buffer : buffer16;--EP3 --16b Int Out
signal EP3_Buff : word8;
signal EP4_Buffer : buffer16;--EP4 --16b Int In
constant sub_reset_Dc : word := x"1000"; --resets the device controller of the ISP1362
constant sub_port_out_cmd : word := x"1100"; --writes a command from AX
constant sub_port_out : word := x"1200"; --writes a word from AX
constant sub_port_in : word := x"1300"; --reads a word into AX
constant sub_send_data : word := x"1400"; --endpoint in DL, length in w_length, data in w_data32
constant sub_port_dump : word := x"1500"; --number of bytes in CX, data in w_data32
constant sub_rd_cfg_regs : word := x"1600"; --reads from chip to reg_DcRegisters (mode, hwcfg, intenable only)
constant sub_CRwrite : word := x"1700"; --writes command from AX and corresponding Reg_DcRegister
constant sub_rcv_setup : word := x"1800"; --recieves 8 bytes from ctrlOut to w_ctrl_xfer
constant sub_init_isp1362 : word := x"1900"; --initilizes isp1362 configuration DcRegisters
constant sub_disp_cfg_regs : word := x"1A00"; --displays masked Dcmode, DcHardwareConfiguration and last word of DcInterruptEnable
constant sub_DcInterrupt : word := x"1B00"; --loads OTG_DcInterrupt from isp1362
constant sub_suspender : word := x"1C00"; --handles suspend state and wakeup
constant sub_ctrlOut_handler: word := x"1D00"; --
constant sub_Get_ESR : word := x"1E00"; --reads ESR specified by command in AX into OTG_ESR register and AL
constant sub_SET_ADDRESS : word := x"1F00"; --handles SET_ADDRESS setup packet
constant sub_configureEps_n_ack:word:= x"2000"; --configures endpoints and acknowledges
constant sub_sendEpStatus : word := x"2200"; --send EpStatus and ack
constant sub_EP_Int_handler : word := x"2300"; --handles endpoint interrupts
--constant sub_ : word := x"2200"; --
--constant sub_ : word := x"2300"; --
procedure reset_cpu is
begin
OTG_RST_N <= '1';
OTG_ADDR(0) <= '1';
OTG_CS_N <= '1';
OTG_RD_N <= '1';
OTG_WR_N <= '1';
nEAX <= x"00000000";
nEBX <= x"00000000";
nECX <= x"00000000";
nEDX <= x"00000000";
sp_next <= "00000";
w_done <= '1';
e_state <= default;
w_count <= 0;
end reset_cpu;
procedure push(constant data : in word) is
begin
stack(to_integer(SP-1)) <= data;
SP_NEXT <= SP-1;
end push;
procedure pop(signal data : out word) is
begin
data <= stack(to_integer(sp));
SP_NEXT <= SP+1;
end pop;
procedure jump(constant New_IP : in word) is
begin
JMP <= '1';
IP_JMP <= New_IP;
end jump;
procedure loopJump(constant New_IP : in word) is
begin
nCX <= to_vec(16,to_int(CX) - 1);
if CX /= x"0000" then
jump(New_IP);
end if;
end loopJump;
procedure go_sub(constant new_ip : in word) is
begin
stack(to_integer(SP-1)) <= IP+1; --we'll return to next ip
SP_NEXT <= SP-1;
JMP <= '1';
IP_JMP <= new_ip;
end go_sub;
procedure ret_sub is
begin
IP_JMP <= stack(to_integer(SP)); --ip incremented by go_sub
JMP <= '1';
SP_NEXT <= SP+1;
end ret_sub;
procedure wait_here(constant num_clocks : in unsigned) is --wait_here(x"0000") is same as NoOp
begin
if w_count < num_clocks then
w_count <= w_count + 1;
IP_JMP <= IP;
JMP <= '1';
else
w_count <= 0;
end if;
end wait_here;
procedure wait_for_command is
begin
if w_execute = '1' then
cur_instruction <= instruction;
w_done <= '0';
else
jump(IP);
end if;
end wait_for_command;
procedure loadBuffer(constant with_me : in std_logic_vector) is
begin
w_buffer64(0 to with_me'Length-1)<=with_me;
end loadBuffer;
procedure port_dump(constant destination:in nibble;
constant to_send :in std_logic_vector;
constant length_limit :in word := x"FFFF") is
begin
w_length<=smaller(to_vec(16,(to_send'length)/8),length_limit);
loadBuffer(to_send);
nDL(3 downto 0)<=destination;
go_sub(sub_send_data);
end port_dump;
begin
Hexx0 : SevenSeg port map(segs1(3 downto 0),HEX0(0 to 6));
Hexx1 : SevenSeg port map(segs1(7 downto 4),HEX1(0 to 6));
Hexx2 : SevenSeg port map(segs1(11 downto 8),HEX2(0 to 6));
Hexx3 : SevenSeg port map(segs1(15 downto 12),HEX3(0 to 6));
Hexx4 : SevenSeg port map(segs2(3 downto 0),HEX4(0 to 6));
Hexx5 : SevenSeg port map(segs2(7 downto 4),HEX5(0 to 6));
Hexx6 : SevenSeg port map(segs3(3 downto 0),HEX6(0 to 6));
Hexx7 : SevenSeg port map(segs3(7 downto 4),HEX7(0 to 6));
--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-CLOCK PROCESS-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=--
clock_halfer: process
begin
wait until clock_50'EVENT and clock_50='1';
if clock_25 = '1' then
clock_25 <= '0';
else
clock_25 <= '1';
end if;
end process;
--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-IP_Mover PROCESS-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=--
IP_Mover : process --Increments IP on falling clock edge (IP stable for 20ns after clock rise)
begin --If jmp = true then instead sets IP to IP_JMP
--ALSO SETS SP = SP_NEXT
--ALSO SETS EAX,EBX,ECX,EDX to nEAX,nEBX,nECX,nEDX
--ALSO latches OTG_INT1_latch
--ALSO translates w_buffer64 into w_data32
wait until CLOCK_25'EVENT and CLOCK_25 = '0';
if JMP = '1' then
IP <= IP_JMP;
else
IP <= IP+1;
end if;
SP <= SP_NEXT;
EAX <= nEAX;
EBX <= nEBX;
ECX <= nECX;
EDX <= nEDX;
OTG_INT1_latch <= OTG_INT1;
w_data32<=(w_buffer64(0*16+8 to 0*16+15) & w_buffer64(0*16 to 0*16+7), w_buffer64(1*16+8 to 1*16+15) & w_buffer64(1*16 to 1*16+7), w_buffer64(2*16+8 to 2*16+15) & w_buffer64(2*16 to 2*16+7), w_buffer64(3*16+8 to 3*16+15) & w_buffer64(3*16 to 3*16+7), w_buffer64(4*16+8 to 4*16+15) & w_buffer64(4*16 to 4*16+7), w_buffer64(5*16+8 to 5*16+15) & w_buffer64(5*16 to 5*16+7), w_buffer64(6*16+8 to 6*16+15) & w_buffer64(6*16 to 6*16+7), w_buffer64(7*16+8 to 7*16+15) & w_buffer64(7*16 to 7*16+7), w_buffer64(8*16+8 to 8*16+15) & w_buffer64(8*16 to 8*16+7), w_buffer64(9*16+8 to 9*16+15) & w_buffer64(9*16 to 9*16+7), w_buffer64(10*16+8 to 10*16+15) & w_buffer64(10*16 to 10*16+7),w_buffer64(11*16+8 to 11*16+15) & w_buffer64(11*16 to 11*16+7),w_buffer64(12*16+8 to 12*16+15) & w_buffer64(12*16 to 12*16+7),w_buffer64(13*16+8 to 13*16+15) & w_buffer64(13*16 to 13*16+7),w_buffer64(14*16+8 to 14*16+15) & w_buffer64(14*16 to 14*16+7),w_buffer64(15*16+8 to 15*16+15) & w_buffer64(15*16 to 15*16+7),w_buffer64(16*16+8 to 16*16+15) & w_buffer64(16*16 to 16*16+7),w_buffer64(17*16+8 to 17*16+15) & w_buffer64(17*16 to 17*16+7),w_buffer64(18*16+8 to 18*16+15) & w_buffer64(18*16 to 18*16+7),w_buffer64(19*16+8 to 19*16+15) & w_buffer64(19*16 to 19*16+7),w_buffer64(20*16+8 to 20*16+15) & w_buffer64(20*16 to 20*16+7),w_buffer64(21*16+8 to 21*16+15) & w_buffer64(21*16 to 21*16+7),w_buffer64(22*16+8 to 22*16+15) & w_buffer64(22*16 to 22*16+7),w_buffer64(23*16+8 to 23*16+15) & w_buffer64(23*16 to 23*16+7),w_buffer64(24*16+8 to 24*16+15) & w_buffer64(24*16 to 24*16+7),w_buffer64(25*16+8 to 25*16+15) & w_buffer64(25*16 to 25*16+7),w_buffer64(26*16+8 to 26*16+15) & w_buffer64(26*16 to 26*16+7),w_buffer64(27*16+8 to 27*16+15) & w_buffer64(27*16 to 27*16+7),w_buffer64(28*16+8 to 28*16+15) & w_buffer64(28*16 to 28*16+7),w_buffer64(29*16+8 to 29*16+15) & w_buffer64(29*16 to 29*16+7),w_buffer64(30*16+8 to 30*16+15) & w_buffer64(30*16 to 30*16+7),w_buffer64(31*16+8 to 31*16+15) & w_buffer64(31*16 to 31*16+7));
end process;
OTG_ADDR(1) <= '1'; --always talking to the peripheral
--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-WORKER PROCESS-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=--
worker : process
begin
wait until clock_25'EVENT and clock_25 = '1';
JMP <= 'L'; --Weak Low If someone else wants to jump, force it with '1';
keylast<=key;
if keylast(3)='0' and key(3)='1' then --start viewing ip history
if IP_H_View then
IP_H_View <= false;
else
IP_H_View <= true;
IP_H_V_Num <= 0;
end if;
end if;
if IP_H_View then
LEDR(17)<='0';
SEGS1 <= IP_History(IP_H_V_Num);
SEGS2 <= std_logic_vector(to_unsigned(IP_H_V_Num,8));
case sw(17 downto 15) is
when "000" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).bmRequestType;
when "001" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).bRequest;
when "010" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wValue(7 downto 0);
when "011" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wValue(15 downto 8);
when "100" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wIndex(7 downto 0);
when "101" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wIndex(15 downto 8);
when "110" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wLength(7 downto 0);
when "111" => SEGS3 <= raw_ctrl_xfers(to_int(sw(9 downto 7))).wLength(15 downto 8);
end case;
if keylast(2)='0' and key(2) = '1' then
IP_H_V_Num <= IP_H_V_Num+1;
elsif keylast(1)='0' and key(1) = '1' then
IP_H_V_Num <= IP_H_V_Num-1;
end if;
else
LEDR(17)<='1';
if sw(1 downto 0) = "00" then
SEGS1 <= w_data32(to_integer(unsigned(sw(14 downto 10))));--OTG_DcInterrupt(31 downto 16);
elsif sw(1 downto 0) = "01" then
SEGS1 <= sent_data(to_integer(unsigned(sw(14 downto 10))));
elsif sw(1 downto 0) = "10" then
SEGS1 <= EP1_Buff(to_integer(unsigned(sw(14 downto 10))));--
end if;
SEGS2 <= IP(7 downto 0);
SEGS3 <= OTG_ESR(0);
if IP/=IP_History(0) then
IP_History(31)<=IP_History(30);IP_History(30)<=IP_History(29);IP_History(29)<=IP_History(28);IP_History(28)<=IP_History(27);IP_History(27)<=IP_History(26);IP_History(26)<=IP_History(25);IP_History(25)<=IP_History(24);IP_History(24)<=IP_History(23);IP_History(23)<=IP_History(22);IP_History(22)<=IP_History(21);IP_History(21)<=IP_History(20);IP_History(20)<=IP_History(19);IP_History(19)<=IP_History(18);IP_History(18)<=IP_History(17);IP_History(17)<=IP_History(16);IP_History(16)<=IP_History(15);IP_History(15)<=IP_History(14);IP_History(14)<=IP_History(13);IP_History(13)<=IP_History(12);IP_History(12)<=IP_History(11);IP_History(11)<=IP_History(10);IP_History(10)<=IP_History(9);IP_History(9) <=IP_History(8);IP_History(8) <=IP_History(7);IP_History(7) <=IP_History(6);IP_History(6) <=IP_History(5);IP_History(5) <=IP_History(4);IP_History(4) <=IP_History(3);IP_History(3) <=IP_History(2);IP_History(2) <=IP_History(1);IP_History(1) <=IP_History(0);IP_History(0) <=IP;
end if;
end if;
LEDR(15 downto 0) <= OTG_DcInterrupt(15 downto 0);
if SP = "00001" then
LEDR(16) <= '1';
IP_H_View <= true;
end if;
if e_state = default then
ledg(2 downto 0) <= "100";
elsif e_state = address then
ledg(2 downto 0) <= "110";
else
ledg(2 downto 0) <= "111";
end if;
LEDG(8)<=OTG_INT1;
if key(0) = '0' then
jump(x"0000");
LEDR(16)<='0';
else
case ip is
--=-=-=-=-=-MAIN LOOP STARTS HERE-=-=-=-=-=--
when x"0000" => --reset cpu
reset_cpu;
when x"0001" =>
go_sub(sub_reset_Dc);
when x"0002" =>
go_sub(sub_init_isp1362);
when x"0003" =>
wait_here(x"09C4");
when x"0004" =>--0111111100000101
if OTG_INT1_latch = '1' then
go_sub(sub_DcInterrupt);
else
jump(IP); --wait here;
end if;
when x"0005" =>--interrupt in ax
if OTG_DcInterrupt(0) = '1' then --reset
jump(x"0000");--0003");
elsif OTG_DcInterrupt(2) = '1' or OTG_DcInterrupt(7) = '1' then --suspend detected
go_sub(sub_suspender);
elsif OTG_DcInterrupt(8) = '1' then --ctrlOut is paging
go_sub(sub_ctrlOut_handler);
elsif OTG_DcInterrupt(14 downto 10)/="00000" then --endpoint paging
go_sub(sub_ep_int_handler);
else
jump(IP); --i.e. Lock Up here
end if;
when x"0006" =>
jump(x"0004");
--=-=-=-=-=-PROGRAMMATIC SUBROUTINES-=-=-=-=-=--
--GO_SUB(x"1000");reset_dc--resets isp1362
when x"1000" =>
OTG_RST_N <= '0';
when x"1001" =>
wait_here(x"09C4"); --clock at 25MHz => cycle lasts 40ns. we need to wait 100us. 100/.04=2500
when x"1002" =>
OTG_RST_N <= '1';
when x"1003" =>
ret_sub;
--GO_SUB(x"1100");port_out_cmd--
when x"1100" => --0ns
OTG_ADDR(0) <= '1';
OTG_CS_N <= '0';
OTG_RD_N <= '1';
OTG_WR_N <= '0';
OTG_DATA <= AX;
when x"1101" => --40ns
OTG_WR_N <= '1';
when x"1102" => --80ns
OTG_CS_N <= '1';
when x"1103" => --120ns
when x"1104" => --160ns
OTG_DATA <= "ZZZZZZZZZZZZZZZZ";
ret_sub;
--GO_SUB(x"1200");port_out--
when x"1200" => --0ns
OTG_ADDR(0) <= '0';
OTG_CS_N <= '0';
OTG_RD_N <= '1';
OTG_WR_N <= '0';
OTG_DATA <= AX;
when x"1201" => --40ns
OTG_WR_N <= '1';
when x"1202" => --80ns
OTG_CS_N <= '1';
when x"1203" => --120ns
OTG_DATA <= "ZZZZZZZZZZZZZZZZ";
ret_sub;
--GO_SUB(x"1300");port_in--
when x"1300" => --0ns
OTG_ADDR(0) <= '0';
OTG_CS_N <= '0';
OTG_RD_N <= '0';
OTG_WR_N <= '1';
when x"1301" => --40ns
nAX <= OTG_DATA;
when x"1302" => --80ns
OTG_RD_N <= '1';
OTG_CS_N <= '1';
when x"1303" => --120ns
OTG_DATA <= "ZZZZZZZZZZZZZZZZ";
ret_sub;
--GO_SUB(x"1400");send_data_to_endpoint_in_DL(3 downto 0)--
when x"1400" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_Buffer & DL(3 downto 0);
when x"1401" =>
go_sub(sub_port_out);
nAX <= w_length;
when x"1402" =>
go_sub(sub_port_dump);
when x"1403" =>
go_sub(sub_port_out_cmd);
nAX <= Validate & DL(3 downto 0);
when x"1404" =>
ret_sub;
--GO_SUB(x"1500");port_dump_from_data32 number of bytes in w_Length
when x"1500" =>
w_count <= 0;
nBX <= x"0000";
if w_Length = x"0000" then
ret_sub;
end if;
when x"1501" => --0ns
OTG_ADDR(0) <= '0';
OTG_CS_N <= '0';
OTG_RD_N <= '1';
OTG_WR_N <= '0';
OTG_DATA <= w_data32(w_count);
when x"1502" => --40ns
OTG_WR_N <= '1';
sent_data(w_count)<=OTG_DATA;
when x"1503" => --80ns
OTG_CS_N <= '1';
w_count<=w_count+1;
when x"1504" => --120ns
when x"1505" => --160ns
if w_count < (to_int(w_length)+1)/2 then
jump(x"1501");
end if;
when x"1506" =>
w_count <= 0;
OTG_DATA<= "ZZZZZZZZZZZZZZZZ";
ret_sub;
--GO_SUB(x"1600");read_cfg_regs
when x"1600" =>
go_sub(sub_port_out_cmd);
nAX <= Rd_DcInterruptEnable;
when x"1601" =>
go_sub(sub_port_in);
when x"1602" =>
OTG_DcInterruptEnable(15 downto 0) <= AX;
go_sub(sub_port_in);
when x"1603" =>
OTG_DcInterruptEnable(31 downto 16) <= AX;
go_sub(sub_port_out_cmd);
nAX <= Rd_DcHardwareConfiguration;
when x"1604" =>
go_sub(sub_port_in);
when x"1605" =>
OTG_DcHardwareConfiguration <= AX;
go_sub(sub_port_out_cmd);
nAX <= Rd_DcMode;
when x"1606" =>
go_sub(sub_port_in);
when x"1607" =>
OTG_DcMode <= AL;
ret_sub;
--GO_SUB(x"1700");CRwrite --writes value from Reg_DcRegister commanded by AX into register
when x"1700" =>
go_sub(sub_port_out_cmd);
nDX <= AX;
when x"1701" =>
go_sub(sub_port_out);
case AX is
when Wr_DcAddress => --byte
nAL <= OTG_DcAddress;
when Wr_DcMode => --byte
nAL <= OTG_DcMode;
when Wr_DcHardwareConfiguration => --word
nAX <= OTG_DcHardwareConfiguration;
when Wr_DcInterruptEnable => --dword
nAX <= OTG_DcInterruptEnable(15 downto 0);
when UnlockDevice => --byte (special)
nAX <= x"AA37";
when others =>
if AX(15 downto 4)=Wr_DcEndpointConfiguration then
nAX <= OTG_DcEndpointConfiguration(to_integer(unsigned(AX(3 downto 0))));
end if;
end case;
when x"1702" =>
if DX = Wr_DcInterruptEnable then
nAX <= OTG_DcInterruptEnable(31 downto 16);
go_sub(sub_port_out);
else
ret_sub;
end if;
when x"1703" =>
ret_sub;
--GO_SUB(x"1800");rcv_setup --recieves 8 bytes from ctrlOut to w_ctrl_xfer
when x"1800" =>
nAX <= Rd_Buffer & ctrlOut;
go_sub(sub_port_out_cmd);
when x"1801" =>
go_sub(sub_port_in);
when x"1802" =>
go_sub(sub_port_in);
raw_ctrl_xfers(7)<=raw_ctrl_xfers(6);
raw_ctrl_xfers(6)<=raw_ctrl_xfers(5);
raw_ctrl_xfers(5)<=raw_ctrl_xfers(4);
raw_ctrl_xfers(4)<=raw_ctrl_xfers(3);
raw_ctrl_xfers(3)<=raw_ctrl_xfers(2);
raw_ctrl_xfers(2)<=raw_ctrl_xfers(1);
raw_ctrl_xfers(1)<=raw_ctrl_xfers(0);
when x"1803" =>
w_ctrl_xfer.bmRequestType <= AL;
w_ctrl_xfer.bRequest <= AH;
go_sub(sub_port_in);
when x"1804" =>
w_ctrl_xfer.wValue <= AX;
go_sub(sub_port_in);
when x"1805" =>
w_ctrl_xfer.wIndex <= AX;
go_sub(sub_port_in);
when x"1806" =>
w_ctrl_xfer.wLength <= AX;
nAX <= AcknowledgeSetup;
go_sub(sub_port_out_cmd);
when x"1807" =>
raw_ctrl_xfers(0)<=w_ctrl_xfer;
nAX <= ClearBuffer & ctrlOut;
go_sub(sub_port_out_cmd);
when x"1808" =>
ret_sub;
--GO_SUB(x"1900");init_isp1362 --initilizes isp1362 DcRegisters
when x"1900" =>
go_sub(sub_rd_cfg_regs);
when x"1901" =>
OTG_DcMode <= (OTG_DcMode and x"D2") or x"09";
OTG_DcHardwareConfiguration <= (OTG_DcHardwareConfiguration and x"8014") or x"20E1";
OTG_DcInterruptEnable <= (OTG_DcInterruptEnable and x"11000080") or x"00007D06";
go_sub(sub_CRwrite);
nAX <= Wr_DcMode;
when x"1902" =>
go_sub(sub_CRwrite);
nAX <= Wr_DcHardwareConfiguration;
when x"1903" =>
go_sub(sub_CRwrite);
nAX <= Wr_DcInterruptEnable;
when x"1904" =>
ret_sub;
--GO_SUB(x"1A00");Disp_Cfg_Regs --displays masked Dcmode, DcHardwareConfiguration and last word of DcInterruptEnable
when x"1A00" =>
go_sub(sub_rd_cfg_regs);
when x"1A01" =>
-- segs1 <= (OTG_DcInterruptEnable(15 downto 0) and x"FF7F");
segs2 <= (OTG_DcHardwareConfiguration(7 downto 0) and x"EB");
segs3 <= (OTG_DcHardwareConfiguration(15 downto 8) and x"7F");
LEDR(15 downto 0)<= x"00" & (OTG_DcMode and x"2D");
ret_sub;
--GO_SUB(x"");DcInterrupt --loads OTG_DcInterrupt from isp1362
when x"1B00" =>
go_sub(sub_port_out_cmd);
nAX <= Rd_DcInterrupt;
when x"1B01" =>
go_sub(sub_port_in);
when x"1B02" =>
OTG_DcInterrupt(15 downto 0) <= AX;
go_sub(sub_port_in);
when x"1B03" =>
OTG_DcInterrupt(31 downto 16) <= AX;
ret_sub;
--GO_SUB(x"");sub_suspender
when x"1C00" =>
go_sub(sub_DcInterrupt);
when x"1C01" =>
if (OTG_DcInterrupt(2)='1' and OTG_DcInterrupt(7)='1') then
go_sub(sub_rd_cfg_regs);
else
ret_sub;
end if;
when x"1C02" =>
go_sub(sub_CRwrite);
nAX <= Wr_DcMode or "00100000";
when x"1C03" =>
go_sub(sub_CRwrite);
nAX <= Wr_DcMode and "11011111";
when x"1C04" =>
wait_here(x"FFFF"); --5 ms before bus will wake up for sure
when x"1C05" =>
wait_here(x"E847"); --(rest of 5ms)
when x"1C06" =>
if OTG_INT1_latch = '1' then
wait_here(x"09C4"); --100us to wake up
else
jump(IP);--MODIFIED MODIFIED MODIFIED!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!ADDED THIS
end if;
when x"1C07" =>
go_sub(sub_CRwrite);
nAX <= UnlockDevice;
when x"1C08" =>
go_sub(sub_DcInterrupt);
when x"1C09" =>
if OTG_DcInterrupt(7)='1' then
jump(x"1C06");
else
ret_sub;
end if;
--GO_SUB(x"1D00");ctrlOut_handler --handles an interrupt by ctrlOut
when x"1D00" =>
go_sub(sub_get_esr);
nAX <= Rd_ESR & ctrlOut;
when x"1D01" =>
if AL(2)='1' and AL(3)='0' and AL(5)='1' then --setup packet ready
go_sub(sub_rcv_setup);
else --error
ret_sub;
end if;
when x"1D02" =>
case w_ctrl_xfer.bRequest is
when GET_DESCRIPTOR =>
case w_ctrl_xfer.wValue(15 downto 8) is
when desc_DEVICE =>
if (w_ctrl_xfer.bmRequestType=x"80" and w_ctrl_xfer.wIndex=x"0000" and w_ctrl_xfer.wValue(7 downto 0)=x"00" ) then
port_dump(ctrlIn,byte_deviceDescriptor(CRD_devDesc),w_ctrl_xfer.wLength);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when desc_STRING =>
ledg(7)<='1';
case w_ctrl_xfer.wValue(7 downto 0) is
when x"00" =>
port_dump(ctrlIn,CRD_strDesc_00_Langs,w_ctrl_xfer.wLength);
when x"01" =>
if w_ctrl_xfer.wIndex = x"0409" then
port_dump(ctrlIn,CRD_strDesc_01_Vendor);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when x"02" =>
if w_ctrl_xfer.wIndex = x"0409" then
port_dump(ctrlIn,CRD_strDesc_02_Product,w_ctrl_xfer.wLength);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when x"03" =>
if w_ctrl_xfer.wIndex = x"0409" then
port_dump(ctrlIn,CRD_strDesc_03_Serial,w_ctrl_xfer.wLength);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when others => --CRD_strDesc_03_Serial
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end case;
when desc_CONFIGURATION =>
if w_ctrl_xfer.wValue(7 downto 0) = x"00" then
-- port_dump(ctrlIn,CRD_Full_Cfg_Desc,w_ctrl_xfer.wLength);
port_dump(ctrlIn,CRD_Full_Cfg1_Desc,w_ctrl_xfer.wLength);
elsif w_ctrl_xfer.wValue(7 downto 0) = x"01" then
port_dump(ctrlIn,CRD_Full_Cfg2_Desc,w_ctrl_xfer.wLength);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when others =>
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end case;
when SET_ADDRESS =>
if e_state = configured then
ret_sub;
else
go_sub(sub_SET_ADDRESS);
end if;
when SET_CONFIGURATION =>
if e_state = default then
ret_sub;
elsif w_ctrl_xfer.wValue = x"0000" then
e_state <= address;
port_dump(ctrlIn,x"0000",x"0000");
elsif w_ctrl_xfer.wValue = x"0001" or w_ctrl_xfer.wValue = x"0002" then
what_config<=w_ctrl_xfer.wValue(7 downto 0);
go_sub(sub_configureEps_n_ack);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when GET_STATUS =>
if e_state = default then
ret_sub;
elsif w_ctrl_xfer.bmRequestType = x"80" then
port_dump(ctrlIn, x"0001");
elsif w_ctrl_xfer.bmRequestType = x"81" and w_ctrl_xfer.wIndex = x"0000" then
port_dump(ctrlIn, x"0000");
elsif ((e_state=address and w_ctrl_xfer.wIndex = x"0000") or (e_state = configured)) and (w_ctrl_xfer.bmRequestType=x"82") then
go_sub(sub_sendEpStatus);
else
go_sub(sub_port_out_cmd);
nAX <= Stall & ctrlIn;
end if;
when CLEAR_FEATURE =>
if e_state = default then
ret_sub;
elsif (w_ctrl_xfer.bmRequestType = x"02") and (w_ctrl_xfer.wValue=x"0000") then
case(w_ctrl_xfer.wIndex(7 downto 0)) is
when x"80"|x"00"=> --ctrlInOut
nAX <=(Unstall & ctrlIn);
when x"81" => --ep1
nAX <=(Unstall & ep1);
when x"02" => --ep2
nAX <=(Unstall & ep2);
when x"83" => --ep3
nAX <=(Unstall & ep3);
when x"04" => --ep4
nAX <=(Unstall & ep4);
when x"85" => --ep5
nAX <=(Unstall & ep5);
when others => --unsupported or error
nAX <=(Stall & ctrlIn);
end case;
go_sub(sub_port_out_cmd);
else
nAX <=(Stall & ctrlIn);
go_sub(sub_port_out_cmd);
end if;
--NEED TO ACK AFTER SET AND CLEAR FEATURES!!!!!!!!!!1
when SET_FEATURE =>
if e_state = default then
ret_sub;
elsif (w_ctrl_xfer.bmRequestType = x"02") and (w_ctrl_xfer.wValue=x"0000") then
case(w_ctrl_xfer.wIndex(7 downto 0)) is
when x"81" => --ep1
nAX <=(Stall & ep1);
when x"02" => --ep2
nAX <=(Stall & ep2);
when x"83" => --ep3
nAX <=(Stall & ep3);
when x"04" => --ep4
nAX <=(Stall & ep4);
when x"85" => --ep5
nAX <=(Stall & ep5);
when others => --unsupported or error
nAX <=(Stall & ctrlIn);
end case;
go_sub(sub_port_out_cmd);
else
nAX <=(Stall & ctrlIn);
go_sub(sub_port_out_cmd);
end if;
when GET_CONFIGURATION =>
if e_state = default then
ret_sub;
elsif e_state = address then
port_dump(ctrlIn,x"00");
elsif e_state = configured then
port_dump(ctrlIn,what_config);
end if;
when GET_INTERFACE|SET_INTERFACE =>
if (e_state=address)or((w_ctrl_xfer.wIndex(7 downto 0)/=x"00")) then
nAX<=(Stall & ctrlIn);
go_sub(sub_port_out_cmd);
else
if w_ctrl_xfer.bRequest = GET_INTERFACE then
w_length<=x"0001";
loadBuffer(x"00"&which_interface);
elsif w_ctrl_xfer.wValue(7 downto 1) = "0000000" then
which_interface <= w_ctrl_xfer.wValue(7 downto 0);
w_length<= x"0000";
go_sub(sub_send_data);
else
nAX<=(Stall & ctrlIn);
go_sub(sub_port_out_cmd);
end if;
end if;
when others =>
jump(x"FFFF");--LOCK UP and display unrecognized request
end case;
when x"1D03" =>
ret_sub;
--GO_SUB(x"");get_ESR --reads an ESR specified by command in AL into its corresponding OTG_ESR register and AL
when x"1E00" => --7:stall 6:2ndary full 5:primary full 4:PID 3:missed_setup go home 2:setup_pkt 1:2ndary selected 0:none
go_sub(sub_port_out_cmd);
nBX <= AX;
when x"1E01" =>
go_sub(sub_port_in);
when x"1E02" =>
OTG_ESR(to_integer(unsigned(BL(3 downto 0))))<= AL;
ret_sub;
--GO_SUB(x"1F00");sub_SET_ADDRESS
when x"1F00" =>
if e_state = configured then
ret_sub;
else
go_sub(sub_port_out_cmd);
nAX <= Wr_DcAddress;
end if;
when x"1F01" =>
go_sub(sub_port_out);
nAX <= x"0080" or w_ctrl_xfer.wValue;
if w_ctrl_xfer.wValue = x"0000" then
e_state <= default;
else
e_state <= address;
end if;
when x"1F02" =>
nAX <= Wr_Buffer & ctrlIn;
go_sub(sub_port_out_cmd);
when x"1F03" =>
nAX <= x"0000";
go_sub(sub_port_out);
when x"1F04" =>
nAX <= Validate & ctrlIn;
go_sub(sub_port_out_cmd);
when x"1F05" =>
ret_sub;
--GO_SUB(x"2000");sub_configureEps_n_ack
when x"2000" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ctrlOut;
when x"2001" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(0);
when x"2002" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ctrlIn;
when x"2003" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(1);
when x"2004" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep1;
when x"2005" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(2);
when x"2006" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep2;
when x"2007" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(3);
when x"2008" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep3;
when x"2009" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(4);
when x"200A" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep4;
when x"200B" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(5);
when x"200C" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep5;
when x"200D" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(6);
when x"200E" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep6;
when x"200F" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(7);
when x"2010" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep7;
when x"2011" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(8);
when x"2012" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep8;
when x"2013" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(9);
when x"2014" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep9;
when x"2015" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(10);
when x"2016" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep10;
when x"2017" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(11);
when x"2018" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep11;
when x"2019" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(12);
when x"201A" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep12;
when x"201B" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(13);
when x"201C" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep13;
when x"201D" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(14);
when x"201E" =>
go_sub(sub_port_out_cmd);
nAX <= Wr_DcEndpointConfiguration & ep14;
when x"201F" =>
go_sub(sub_port_out);
nAL <= DcEndpointConfiguration(15);
when x"2020" =>
e_state <= configured;
port_dump(ctrlIn,x"0000",x"0000");
when x"2021" =>
ret_sub;
--GO_SUB(x"2200");sub_sendEpStatus
when x"2200" =>
case w_ctrl_xfer.windex(7 downto 0) is
when x"80"|x"00"=> --ctrlInOut
go_sub(sub_port_out_cmd);
nAX <= (Rd_DcEndpointStatusImage & ctrlIn);
when x"81" => --ep1
go_sub(sub_port_out_cmd);
nAX <= (Rd_DcEndpointStatusImage & ep1);
when x"02" => --ep2
go_sub(sub_port_out_cmd);
nAX <= (Rd_DcEndpointStatusImage & ep2);
when x"83" => --ep3
go_sub(sub_port_out_cmd);
nAX <= (Rd_DcEndpointStatusImage & ep3);
when x"04" => --ep4
go_sub(sub_port_out_cmd);
nAX <= (Rd_DcEndpointStatusImage & ep4);
when x"85" => --ep5
go_sub(sub_port_out_cmd);
nAX <= (Rd_DcEndpointStatusImage & ep5);
when others => --unsupported or error
jump(x"2210");
end case;
when x"2201" =>
go_sub(sub_send_data);
w_length<=x"0002";
loadBuffer(x"000"&"000"&AL(7));
when x"2202" =>
ret_sub;
when x"2203" =>
when x"2204" =>
when x"2205" =>
when x"2206" =>
when x"2207" =>
when x"2208" =>
when x"2209" =>
when x"220A" =>
when x"220B" =>
when x"220C" =>
when x"220D" =>
when x"220E" =>
when x"220F" =>
when x"2210" =>
go_sub(sub_port_out_cmd);
nAX <= (Stall & ctrlIn);
when x"2211" =>
ret_sub;
--GO_SUB(x"2300");sub_EP_Int_Handler handles endpoing interrupts OTG_DcInterrupt(14 downto 10)/="00000"
when x"2300" =>
if OTG_DcInterrupt(10)='1' then --EP1 --64b Bulk Out signal EP1_Buffer : buffer64
go_sub(sub_get_esr);
nAX <= Rd_ESR & ep1;
elsif OTG_DcInterrupt(11)='1' then --EP2 --64b Bulk In signal EP2_Buffer : buffer64
go_sub(sub_get_esr);
nAX <= Rd_ESR & ep2;
elsif OTG_DcInterrupt(12)='1' then --EP3 --16b Int Out signal EP3_Buffer : buffer16
go_sub(sub_get_esr);
nAX <= Rd_ESR & ep3;
elsif OTG_DcInterrupt(13)='1' then --EP4 --16b Int In signal EP4_Buffer : buffer16
go_sub(sub_get_esr);
nAX <= Rd_ESR & ep4;
elsif OTG_DcInterrupt(14)='1' then --EP5 --1023b Iso In (dblBuff) (IMPLEMENT SRAM BUFFER)
go_sub(sub_get_esr);
nAX <= Rd_ESR & ep5;
end if;
when x"2301" =>
if OTG_DcInterrupt(10)='1' then --EP1 --64b Bulk Out signal EP1_Buffer : buffer64
if AX(5)='1' then
go_sub(x"2310");
else
ret_sub;
end if;
elsif OTG_DcInterrupt(11)='1' then --EP2 --64b Bulk In signal EP2_Buffer : buffer64
if AX(5)='0' then
port_dump(ep2,EP2_Buffer);
else
ret_sub;
end if;
elsif OTG_DcInterrupt(12)='1' then --EP3 --16b Int Out signal EP3_Buffer : buffer16
if AX(5)='1' then
go_sub(x"2320");
else
ret_sub;
end if;
elsif OTG_DcInterrupt(13)='1' then --EP4 --16b Int In signal EP4_Buffer : buffer16
if AX(5)='0' then
port_dump(ep4,EP4_Buffer);
else
ret_sub;
end if;
elsif OTG_DcInterrupt(14)='1' then --EP5 --1023b Iso In (dblBuff) (IMPLEMENT SRAM BUFFER)
if AX(5)='0' then
port_dump(ep5,EP2_Buffer);
else
ret_sub;
end if;
end if;
when x"2302" =>
ret_sub;
when x"2303" =>
when x"2304" =>
when x"2310" =>
nAX <= Rd_Buffer & ep1;
go_sub(sub_port_out_cmd);
when x"2311" =>
go_sub(sub_port_in); --read length
when x"2312" =>
nCX <= to_vec(16,((to_int(AX)+1) / 2));--num words to read
nBX <= x"0000";
when x"2313" =>
go_sub(sub_port_in); --THIS COULD BE IMPLEMENTED WAAAAAAAY FASTER (like sub_send_data)
when x"2314" =>
EP1_Buff(to_int(BX))<=AX; --signal EP1_Buffer : buffer64
nBX<=to_vec(16,to_int(BX)+1);
loopJump(x"2313");
when x"2315" =>
go_sub(sub_port_out_cmd);
nAX <= ClearBuffer & ep1;
when x"2316" =>
ret_sub;
when x"2320" =>
nAX <= Rd_Buffer & ep3;
go_sub(sub_port_out_cmd);
when x"2321" =>
go_sub(sub_port_in); --read length
when x"2322" =>
nCX <= to_vec(16,((to_int(AX)+1) / 2));--num words to read
nBX <= x"0000";
when x"2323" =>
go_sub(sub_port_in); --THIS COULD BE IMPLEMENTED WAAAAAAAY FASTER (like sub_send_data)
when x"2324" =>
EP3_Buff(to_int(BX))<=AX; --signal EP3_Buffer : buffer16
nBX<=to_vec(16,to_int(BX)+1);
loopJump(x"2313");
when x"2325" =>
go_sub(sub_port_out_cmd);
nAX <= ClearBuffer & ep3;
when x"2326" =>
ret_sub;
when x"2400" =>
when x"2401" =>
when x"2402" =>
when x"2403" =>
when x"2404" =>
when x"2405" =>
when x"2406" =>
when x"2407" =>
when x"2408" =>
when x"2409" =>
when x"240A" =>
when x"240B" =>
when x"240C" =>
when x"240D" =>
when x"240E" =>
when x"240F" =>
when x"2500" =>
when x"2501" =>
when x"2502" =>
when x"2503" =>
when x"2504" =>
when x"2505" =>
when x"2506" =>
when x"2507" =>
when x"2508" =>
when x"2509" =>
when x"250A" =>
when x"250B" =>
when x"250C" =>
when x"250D" =>
when x"250E" =>
when x"250F" =>
when x"2600" =>
when x"2601" =>
when x"2602" =>
when x"2603" =>
when x"2604" =>
when x"2605" =>
when x"2606" =>
when x"2607" =>
when x"2608" =>
when x"2609" =>
when x"260A" =>
when x"260B" =>
when x"260C" =>
when x"260D" =>
when x"260E" =>
when x"260F" =>
when x"2700" =>
when x"2701" =>
when x"2702" =>
when x"2703" =>
when x"2704" =>
when x"2705" =>
when x"2706" =>
when x"2707" =>
when x"2708" =>
when x"2709" =>
when x"270A" =>
when x"270B" =>
when x"270C" =>
when x"270D" =>
when x"270E" =>
when x"270F" =>
when x"FFFF" =>
jump(x"FFFF");
when others =>
jump(IP);
end case;
end if;
end process worker;
end handler; | mit | c82f54eea0a745763ddbeb49fc81a839 | 0.602401 | 2.493566 | false | true | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/lib/src/clkXingRtl.vhd | 3 | 6,586 | -------------------------------------------------------------------------------
--! @file clkXingRtl.vhd
--
--! @brief Clock Crossing Bus converter
--
--! @details Used to transfer a faster slave interface to a slower one.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
entity clkXing is
generic (
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
--fast
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oFastRdAck : out std_logic;
--slow
iSlowClk : in std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
iSlowRdAck : in std_logic
);
end entity;
architecture rtl of clkXing is
signal slowCs : std_logic_vector(gCsNum-1 downto 0);
signal anyCs : std_logic;
signal slowRnw : std_logic;
signal wr, wr_s, wr_rising : std_logic;
signal rd, rd_s, rd_rising : std_logic;
signal readRegister : std_logic_vector(gDataWidth-1 downto 0);
signal fastWrAck, fastRdAck, fastAnyAck, slowAnyAck : std_logic;
begin
-- WELCOME TO SLOW CLOCK DOMAIN --
genThoseCs : for i in slowCs'range generate
begin
theSyncCs : entity work.sync
port map (
rst => iArst,
clk => iSlowClk,
din => iFastCs(i),
dout => slowCs(i)
);
end generate;
anyCs <= OR_REDUCE(slowCs);
wr_s <= anyCs and not(slowRnw) and not slowAnyAck;
rd_s <= anyCs and slowRnw and not slowAnyAck;
process(iArst, iSlowClk)
begin
if iArst = '1' then
readRegister <= (others => '0');
wr <= '0';
rd <= '0';
elsif rising_edge(iSlowClk) then
if rd = '1' and iSlowRdAck = '1' then
readRegister <= iSlowReaddata;
end if;
if iSlowWrAck = '1' then
wr <= '0';
elsif wr_rising = '1' then
wr <= '1';
end if;
if iSlowRdAck = '1' then
rd <= '0';
elsif rd_rising = '1' then
rd <= '1';
end if;
end if;
end process;
oSlowCs <= slowCs when wr = '1' or rd = '1' else (others => '0');
oSlowRNW <= rd;
theWriteEdge : entity work.edgeDet
port map (
rst => iArst,
clk => iSlowClk,
din => wr_s,
any => open,
rising => wr_rising,
falling => open
);
theReadEdge : entity work.edgeDet
port map (
rst => iArst,
clk => iSlowClk,
din => rd_s,
any => open,
rising => rd_rising,
falling => open
);
theSyncRnw : entity work.sync
port map (
rst => iArst,
clk => iSlowClk,
din => iFastRNW,
dout => slowRnw
);
theSyncAnyAck : entity work.slow2fastSync
port map (
rstDst => iArst,
clkDst => iSlowClk,
rstSrc => iArst,
clkSrc => iFastClk,
dataSrc => fastAnyAck,
dataDst => slowAnyAck
);
-- WELCOME TO FAST CLOCK DOMAIN --
process(iArst, iFastClk)
begin
if iArst = '1' then
fastAnyAck <= '0';
elsif rising_edge(iFastClk) then
fastAnyAck <= fastWrAck or fastRdAck;
end if;
end process;
theSyncWrAck : entity work.slow2fastSync
port map (
rstDst => iArst,
clkDst => iFastClk,
rstSrc => iArst,
clkSrc => iSlowClk,
dataSrc => iSlowWrAck,
dataDst => fastWrAck
);
oFastWrAck <= fastWrAck;
theSyncRdAck : entity work.slow2fastSync
port map (
rstDst => iArst,
clkDst => iFastClk,
rstSrc => iArst,
clkSrc => iSlowClk,
dataSrc => iSlowRdAck,
dataDst => fastRdAck
);
oFastRdAck <= fastRdAck;
genThoseRdq : for i in readRegister'range generate
begin
theSyncRdq : entity work.sync
port map (
rst => iArst,
clk => iFastClk,
din => readRegister(i),
dout => oFastReaddata(i)
);
end generate;
end architecture;
| gpl-2.0 | 7cfc008ac322d96f270c7f63e45fa556 | 0.546159 | 4.517147 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/SFL.vhd | 2 | 2,984 | -- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: SFL.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SFL IS
PORT
(
noe_in : IN STD_LOGIC
);
END SFL;
ARCHITECTURE SYN OF sfl IS
COMPONENT altserial_flash_loader
GENERIC (
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_shared_access => "OFF",
enhanced_mode => 0,
intended_device_family => "Arria GX",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | 1882cb2846b6516addb0f0a639862e7c | 0.635389 | 3.95756 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_or16b.vhd | 2 | 3,274 | -- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: gl_or16b.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY gl_or16b IS
PORT
(
data : IN STD_LOGIC_2D (15 DOWNTO 0, 0 DOWNTO 0);
result : OUT STD_LOGIC
);
END gl_or16b;
ARCHITECTURE SYN OF gl_or16b IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
BEGIN
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
lpm_or_component : lpm_or
GENERIC MAP (
lpm_size => 16,
lpm_type => "LPM_OR",
lpm_width => 1
)
PORT MAP (
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "1"
-- Retrieval info: PRIVATE: nInput NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: data 16 0 1 0 INPUT NODEFVAL data[15..0][0..0]
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
-- Retrieval info: CONNECT: @data 16 0 1 0 data 16 0 1 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or16b.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or16b.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or16b.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or16b.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or16b_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 572f922b80d500743d029b6868292d92 | 0.63653 | 3.741714 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/xilinx/library/pcores/plb_powerlink_v0_30_a/hdl/vhdl/plb_powerlink.vhd | 3 | 96,325 | -------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx PLB V4.6.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.global.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library PLBV46_MASTER_BURST_V1_01_A;
library PLBV46_SLAVE_SINGLE_V1_01_A;
entity plb_powerlink is
generic(
C_FAMILY : string := "spartan6";
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_PLB_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
C_MAC_GEN_SECOND_TIMER : boolean := false;
--pdi
C_PDI_REV : integer := 0;
C_PCP_SYS_ID : integer := 0;
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- sync IRQ pulse width
C_USE_PULSE_2nd_CMP_TIMER : boolean := true;
C_PULSE_WIDTH_2nd_CMP_TIMER : integer := 9;
-- PDI AP PLB Slave
C_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_AP_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_AWIDTH : INTEGER := 32;
C_PDI_AP_PLB_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_AP_PLB_P2P : INTEGER := 0;
C_PDI_AP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI AP PLB Slave
C_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_SMP_PCP_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_AWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_SMP_PCP_PLB_P2P : INTEGER := 0;
C_SMP_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI PCP PLB Slave
C_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_PCP_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_AWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_PCP_PLB_P2P : INTEGER := 0;
C_PDI_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC CMP PLB Slave
C_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_MAC_PKT_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_AWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_PKT_PLB_P2P : INTEGER := 0;
C_MAC_PKT_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC DMA PLB Master
C_MAC_DMA_PLB_AWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_DWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC REG PLB Slave
C_MAC_REG_BASEADDR : std_logic_vector := X"00000000";
C_MAC_REG_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_CMP_BASEADDR : std_logic_vector := X"00000000";
C_MAC_CMP_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_REG_BUS2CORE_CLK_RATIO : integer := 2;
C_MAC_REG_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_AWIDTH : INTEGER := 32;
C_MAC_REG_PLB_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_REG_PLB_P2P : INTEGER := 0;
C_MAC_REG_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_SUPPORT_BURSTS : INTEGER := 0
);
port(
MAC_DMA_Clk : in std_logic;
MAC_DMA_MAddrAck : in std_logic;
MAC_DMA_MBusy : in std_logic;
MAC_DMA_MIRQ : in std_logic;
MAC_DMA_MRdBTerm : in std_logic;
MAC_DMA_MRdDAck : in std_logic;
MAC_DMA_MRdErr : in std_logic;
MAC_DMA_MRearbitrate : in std_logic;
MAC_DMA_MTimeout : in std_logic;
MAC_DMA_MWrBTerm : in std_logic;
MAC_DMA_MWrDAck : in std_logic;
MAC_DMA_MWrErr : in std_logic;
MAC_DMA_Rst : in std_logic;
MAC_PKT_Clk : in std_logic;
MAC_PKT_PAValid : in std_logic;
MAC_PKT_RNW : in std_logic;
MAC_PKT_Rst : in std_logic;
MAC_PKT_SAValid : in std_logic;
MAC_PKT_abort : in std_logic;
MAC_PKT_busLock : in std_logic;
MAC_PKT_lockErr : in std_logic;
MAC_PKT_rdBurst : in std_logic;
MAC_PKT_rdPendReq : in std_logic;
MAC_PKT_rdPrim : in std_logic;
MAC_PKT_wrBurst : in std_logic;
MAC_PKT_wrPendReq : in std_logic;
MAC_PKT_wrPrim : in std_logic;
MAC_REG_Clk : in std_logic;
MAC_REG_PAValid : in std_logic;
MAC_REG_RNW : in std_logic;
MAC_REG_Rst : in std_logic;
MAC_REG_SAValid : in std_logic;
MAC_REG_abort : in std_logic;
MAC_REG_busLock : in std_logic;
MAC_REG_lockErr : in std_logic;
MAC_REG_rdBurst : in std_logic;
MAC_REG_rdPendReq : in std_logic;
MAC_REG_rdPrim : in std_logic;
MAC_REG_wrBurst : in std_logic;
MAC_REG_wrPendReq : in std_logic;
MAC_REG_wrPrim : in std_logic;
PDI_AP_Clk : in std_logic;
PDI_AP_PAValid : in std_logic;
PDI_AP_RNW : in std_logic;
PDI_AP_Rst : in std_logic;
PDI_AP_SAValid : in std_logic;
PDI_AP_abort : in std_logic;
PDI_AP_busLock : in std_logic;
PDI_AP_lockErr : in std_logic;
PDI_AP_rdBurst : in std_logic;
PDI_AP_rdPendReq : in std_logic;
PDI_AP_rdPrim : in std_logic;
PDI_AP_wrBurst : in std_logic;
PDI_AP_wrPendReq : in std_logic;
PDI_AP_wrPrim : in std_logic;
PDI_PCP_Clk : in std_logic;
PDI_PCP_PAValid : in std_logic;
PDI_PCP_RNW : in std_logic;
PDI_PCP_Rst : in std_logic;
PDI_PCP_SAValid : in std_logic;
PDI_PCP_abort : in std_logic;
PDI_PCP_busLock : in std_logic;
PDI_PCP_lockErr : in std_logic;
PDI_PCP_rdBurst : in std_logic;
PDI_PCP_rdPendReq : in std_logic;
PDI_PCP_rdPrim : in std_logic;
PDI_PCP_wrBurst : in std_logic;
PDI_PCP_wrPendReq : in std_logic;
PDI_PCP_wrPrim : in std_logic;
SMP_PCP_Clk : in std_logic;
SMP_PCP_PAValid : in std_logic;
SMP_PCP_RNW : in std_logic;
SMP_PCP_Rst : in std_logic;
SMP_PCP_SAValid : in std_logic;
SMP_PCP_abort : in std_logic;
SMP_PCP_busLock : in std_logic;
SMP_PCP_lockErr : in std_logic;
SMP_PCP_rdBurst : in std_logic;
SMP_PCP_rdPendReq : in std_logic;
SMP_PCP_rdPrim : in std_logic;
SMP_PCP_wrBurst : in std_logic;
SMP_PCP_wrPendReq : in std_logic;
SMP_PCP_wrPrim : in std_logic;
clk100 : in std_logic;
clk50 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
MAC_DMA_MRdDBus : in std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_DMA_MRdWdAddr : in std_logic_vector(0 to 3);
MAC_DMA_MSSize : in std_logic_vector(0 to 1);
MAC_PKT_ABus : in std_logic_vector(0 to 31);
MAC_PKT_BE : in std_logic_vector(0 to (C_MAC_PKT_PLB_DWIDTH/8)-1);
MAC_PKT_MSize : in std_logic_vector(0 to 1);
MAC_PKT_TAttribute : in std_logic_vector(0 to 15);
MAC_PKT_UABus : in std_logic_vector(0 to 31);
MAC_PKT_masterID : in std_logic_vector(0 to C_MAC_PKT_PLB_MID_WIDTH-1);
MAC_PKT_rdPendPri : in std_logic_vector(0 to 1);
MAC_PKT_reqPri : in std_logic_vector(0 to 1);
MAC_PKT_size : in std_logic_vector(0 to 3);
MAC_PKT_type : in std_logic_vector(0 to 2);
MAC_PKT_wrDBus : in std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_wrPendPri : in std_logic_vector(0 to 1);
MAC_REG_ABus : in std_logic_vector(0 to 31);
MAC_REG_BE : in std_logic_vector(0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1);
MAC_REG_MSize : in std_logic_vector(0 to 1);
MAC_REG_TAttribute : in std_logic_vector(0 to 15);
MAC_REG_UABus : in std_logic_vector(0 to 31);
MAC_REG_masterID : in std_logic_vector(0 to C_MAC_REG_PLB_MID_WIDTH - 1);
MAC_REG_rdPendPri : in std_logic_vector(0 to 1);
MAC_REG_reqPri : in std_logic_vector(0 to 1);
MAC_REG_size : in std_logic_vector(0 to 3);
MAC_REG_type : in std_logic_vector(0 to 2);
MAC_REG_wrDBus : in std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH - 1);
MAC_REG_wrPendPri : in std_logic_vector(0 to 1);
PDI_AP_ABus : in std_logic_vector(0 to 31);
PDI_AP_BE : in std_logic_vector(0 to (C_PDI_AP_PLB_DWIDTH/8)-1);
PDI_AP_MSize : in std_logic_vector(0 to 1);
PDI_AP_TAttribute : in std_logic_vector(0 to 15);
PDI_AP_UABus : in std_logic_vector(0 to 31);
PDI_AP_masterID : in std_logic_vector(0 to C_PDI_AP_PLB_MID_WIDTH-1);
PDI_AP_rdPendPri : in std_logic_vector(0 to 1);
PDI_AP_reqPri : in std_logic_vector(0 to 1);
PDI_AP_size : in std_logic_vector(0 to 3);
PDI_AP_type : in std_logic_vector(0 to 2);
PDI_AP_wrDBus : in std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_wrPendPri : in std_logic_vector(0 to 1);
PDI_PCP_ABus : in std_logic_vector(0 to 31);
PDI_PCP_BE : in std_logic_vector(0 to (C_PDI_PCP_PLB_DWIDTH/8)-1);
PDI_PCP_MSize : in std_logic_vector(0 to 1);
PDI_PCP_TAttribute : in std_logic_vector(0 to 15);
PDI_PCP_UABus : in std_logic_vector(0 to 31);
PDI_PCP_masterID : in std_logic_vector(0 to C_PDI_PCP_PLB_MID_WIDTH-1);
PDI_PCP_rdPendPri : in std_logic_vector(0 to 1);
PDI_PCP_reqPri : in std_logic_vector(0 to 1);
PDI_PCP_size : in std_logic_vector(0 to 3);
PDI_PCP_type : in std_logic_vector(0 to 2);
PDI_PCP_wrDBus : in std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_wrPendPri : in std_logic_vector(0 to 1);
SMP_PCP_ABus : in std_logic_vector(0 to 31);
SMP_PCP_BE : in std_logic_vector(0 to (C_SMP_PCP_PLB_DWIDTH/8)-1);
SMP_PCP_MSize : in std_logic_vector(0 to 1);
SMP_PCP_TAttribute : in std_logic_vector(0 to 15);
SMP_PCP_UABus : in std_logic_vector(0 to 31);
SMP_PCP_masterID : in std_logic_vector(0 to C_SMP_PCP_PLB_MID_WIDTH-1);
SMP_PCP_rdPendPri : in std_logic_vector(0 to 1);
SMP_PCP_reqPri : in std_logic_vector(0 to 1);
SMP_PCP_size : in std_logic_vector(0 to 3);
SMP_PCP_type : in std_logic_vector(0 to 2);
SMP_PCP_wrDBus : in std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_wrPendPri : in std_logic_vector(0 to 1);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
MAC_DMA_RNW : out std_logic;
MAC_DMA_abort : out std_logic;
MAC_DMA_busLock : out std_logic;
MAC_DMA_error : out std_logic;
MAC_DMA_lockErr : out std_logic;
MAC_DMA_rdBurst : out std_logic;
MAC_DMA_request : out std_logic;
MAC_DMA_wrBurst : out std_logic;
MAC_PKT_addrAck : out std_logic;
MAC_PKT_rdBTerm : out std_logic;
MAC_PKT_rdComp : out std_logic;
MAC_PKT_rdDAck : out std_logic;
MAC_PKT_rearbitrate : out std_logic;
MAC_PKT_wait : out std_logic;
MAC_PKT_wrBTerm : out std_logic;
MAC_PKT_wrComp : out std_logic;
MAC_PKT_wrDAck : out std_logic;
MAC_REG_addrAck : out std_logic;
MAC_REG_rdBTerm : out std_logic;
MAC_REG_rdComp : out std_logic;
MAC_REG_rdDAck : out std_logic;
MAC_REG_rearbitrate : out std_logic;
MAC_REG_wait : out std_logic;
MAC_REG_wrBTerm : out std_logic;
MAC_REG_wrComp : out std_logic;
MAC_REG_wrDAck : out std_logic;
PDI_AP_addrAck : out std_logic;
PDI_AP_rdBTerm : out std_logic;
PDI_AP_rdComp : out std_logic;
PDI_AP_rdDAck : out std_logic;
PDI_AP_rearbitrate : out std_logic;
PDI_AP_wait : out std_logic;
PDI_AP_wrBTerm : out std_logic;
PDI_AP_wrComp : out std_logic;
PDI_AP_wrDAck : out std_logic;
PDI_PCP_addrAck : out std_logic;
PDI_PCP_rdBTerm : out std_logic;
PDI_PCP_rdComp : out std_logic;
PDI_PCP_rdDAck : out std_logic;
PDI_PCP_rearbitrate : out std_logic;
PDI_PCP_wait : out std_logic;
PDI_PCP_wrBTerm : out std_logic;
PDI_PCP_wrComp : out std_logic;
PDI_PCP_wrDAck : out std_logic;
SMP_PCP_addrAck : out std_logic;
SMP_PCP_rdBTerm : out std_logic;
SMP_PCP_rdComp : out std_logic;
SMP_PCP_rdDAck : out std_logic;
SMP_PCP_rearbitrate : out std_logic;
SMP_PCP_wait : out std_logic;
SMP_PCP_wrBTerm : out std_logic;
SMP_PCP_wrComp : out std_logic;
SMP_PCP_wrDAck : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
MAC_DMA_ABus : out std_logic_vector(0 to 31);
MAC_DMA_BE : out std_logic_vector(0 to (C_MAC_DMA_PLB_DWIDTH/8)-1);
MAC_DMA_MSize : out std_logic_vector(0 to 1);
MAC_DMA_TAttribute : out std_logic_vector(0 to 15);
MAC_DMA_UABus : out std_logic_vector(0 to 31);
MAC_DMA_priority : out std_logic_vector(0 to 1);
MAC_DMA_size : out std_logic_vector(0 to 3);
MAC_DMA_type : out std_logic_vector(0 to 2);
MAC_DMA_wrDBus : out std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_PKT_MBusy : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MIRQ : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MRdErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MWrErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_SSize : out std_logic_vector(0 to 1);
MAC_PKT_rdDBus : out std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_rdWdAddr : out std_logic_vector(0 to 3);
MAC_REG_MBusy : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MIRQ : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MRdErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MWrErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_SSize : out std_logic_vector(0 to 1);
MAC_REG_rdDBus : out std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH-1);
MAC_REG_rdWdAddr : out std_logic_vector(0 to 3);
PDI_AP_MBusy : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MIRQ : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MRdErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MWrErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_SSize : out std_logic_vector(0 to 1);
PDI_AP_rdDBus : out std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_rdWdAddr : out std_logic_vector(0 to 3);
PDI_PCP_MBusy : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MIRQ : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MRdErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MWrErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_SSize : out std_logic_vector(0 to 1);
PDI_PCP_rdDBus : out std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_rdWdAddr : out std_logic_vector(0 to 3);
SMP_PCP_MBusy : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MIRQ : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MRdErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MWrErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_SSize : out std_logic_vector(0 to 1);
SMP_PCP_rdDBus : out std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_rdWdAddr : out std_logic_vector(0 to 3);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of MAC_DMA_Clk : signal is "Clk";
attribute SIGIS of MAC_DMA_Rst : signal is "Rst";
attribute SIGIS of MAC_PKT_Clk : signal is "Clk";
attribute SIGIS of MAC_PKT_Rst : signal is "Rst";
attribute SIGIS of MAC_REG_Clk : signal is "Clk";
attribute SIGIS of MAC_REG_Rst : signal is "Rst";
attribute SIGIS of PDI_AP_Clk : signal is "Clk";
attribute SIGIS of PDI_AP_Rst : signal is "Rst";
attribute SIGIS of PDI_PCP_Clk : signal is "Clk";
attribute SIGIS of PDI_PCP_Rst : signal is "Rst";
attribute SIGIS of SMP_PCP_Clk : signal is "Clk";
attribute SIGIS of SMP_PCP_Rst : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of clk50 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end plb_powerlink;
architecture struct of plb_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : integer := 0;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : integer := 1;
genABuf2_g : integer := 1;
genEvent_g : integer := 0;
genInternalAp_g : integer := 1;
genIoBuf_g : integer := 1;
genLedGadget_g : integer := 0;
genOnePdiClkDomain_g : integer := 0;
genPdi_g : integer := 1;
genSimpleIO_g : integer := 0;
genSmiIO : integer := 1;
genSpiAp_g : integer := 0;
genTimeSync_g : integer := 0;
gen_dma_observer_g : integer := 1;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : integer := 1;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : integer := 0;
papDataWidth_g : integer := 8;
papLowAct_g : integer := 0;
pcpSysId : integer := 1;
pioValLen_g : integer := 50;
spiBigEnd_g : integer := 0;
spiCPHA_g : integer := 0;
spiCPOL_g : integer := 0;
use2ndCmpTimer_g : integer := 1;
usePulse2ndCmpTimer_g : integer := 1;
pulseWidth2ndCmpTimer_g : integer := 9;
use2ndPhy_g : integer := 1;
useIntPacketBuf_g : integer := 1;
useRmii_g : integer := 1;
useRxIntPacketBuf_g : integer := 1
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(31 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component plbv46_master_burst
generic(
C_FAMILY : string := "virtex5";
C_INHIBIT_CC_BLE_INCLUSION : integer range 0 to 1 := 0;
C_MPLB_AWIDTH : integer range 32 to 36 := 32;
C_MPLB_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_NATIVE_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_SMALLEST_SLAVE : integer range 32 to 128 := 32
);
port (
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_rem : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_BE : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
IP2Bus_Mst_Type : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdErr : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrErr : in std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_rem : out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
MD_Error : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8)-1);
M_MSize : out std_logic_vector(0 to 1);
M_RNW : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_abort : out std_logic;
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1)
);
end component;
component plbv46_slave_single
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (1,8);
C_BUS2CORE_CLK_RATIO : integer range 1 to 2 := 1;
C_FAMILY : string := "virtex4";
C_INCLUDE_DPHASE_TIMER : integer range 0 to 1 := 1;
C_SIPIF_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_AWIDTH : integer range 32 to 32 := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 2;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 8;
C_SPLB_P2P : integer range 0 to 1 := 0
);
port (
IP2Bus_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_rdBurst : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_rdPendReq : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_wrPendReq : in std_logic;
PLB_wrPrim : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Bus2IP_Addr : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
Bus2IP_CS : out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Reset : out std_logic;
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic
);
end component;
---- Architecture declarations -----
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_HIGHADDR;
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal Bus2MAC_CMP_Reset : std_logic;
signal Bus2MAC_DMA_MstRd_eof_n : std_logic;
signal Bus2MAC_DMA_MstRd_sof_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_dsc_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_rdy_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_dsc_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_rdy_n : std_logic;
signal Bus2MAC_DMA_Mst_CmdAck : std_logic;
signal Bus2MAC_DMA_Mst_Cmd_Timeout : std_logic;
signal Bus2MAC_DMA_Mst_Cmplt : std_logic;
signal Bus2MAC_DMA_Mst_Error : std_logic;
signal Bus2MAC_DMA_Mst_Rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2Bus_MstRd_dst_dsc_n : std_logic;
signal MAC_DMA2Bus_MstRd_dst_rdy_n : std_logic;
signal MAC_DMA2Bus_MstRd_Req : std_logic;
signal MAC_DMA2Bus_MstWr_eof_n : std_logic;
signal MAC_DMA2Bus_MstWr_Req : std_logic;
signal MAC_DMA2Bus_MstWr_sof_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_dsc_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_rdy_n : std_logic;
signal MAC_DMA2Bus_Mst_Lock : std_logic;
signal MAC_DMA2Bus_Mst_Reset : std_logic;
signal MAC_DMA2Bus_Mst_Type : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET118078 : std_ulogic;
signal NET118214 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic;
signal rstAp : std_logic;
signal rstPcp : std_logic;
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal Bus2MAC_DMA_MstRd_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_MAC_PKT_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_BE_s : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_PDI_AP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_PDI_AP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_PDI_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_SMP_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_address : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Addr : std_logic_vector (0 to C_MAC_DMA_PLB_AWIDTH-1);
signal MAC_DMA2Bus_Mst_BE : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Length : std_logic_vector (0 to 11);
signal MAC_PKT2Bus_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_REG2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (31 downto 0);
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s(C_MAC_REG_PLB_DWIDTH-1 downto 0) <= MAC_REG2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "10",
MAC_CMP2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "01",
(others => '0') when others;
with Bus2MAC_REG_CS select
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck when "10",
MAC_CMP2Bus_WrAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck when "10",
MAC_CMP2Bus_RdAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_Error_s <= MAC_REG2Bus_Error when "10",
MAC_CMP2Bus_Error when "01",
'0' when others;
Bus2MAC_REG_BE_s <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
Bus2MAC_REG_Data_s <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
MAC_REG2Bus_Data <=
MAC_REG2Bus_Data_s(7 downto 0) & MAC_REG2Bus_Data_s(15 downto 8) &
MAC_REG2Bus_Data_s(23 downto 16) & MAC_REG2Bus_Data_s(31 downto 24);
--test_port
test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
test_port(178) <= mac_waitrequest;
test_port(177 downto 176) <= mac_byteenable;
test_port(171 downto 160) <= mac_address(11 downto 0);
test_port(159 downto 144) <= mac_writedata;
test_port(143 downto 128) <= mac_readdata;
test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
test_port(99 downto 96) <= Bus2MAC_REG_BE;
test_port(95 downto 64) <= Bus2MAC_REG_Addr;
test_port(63 downto 32) <= Bus2MAC_REG_Data;
test_port(31 downto 0) <= IP2Bus_Data_s;
--test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
--test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
--test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
--test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
--test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
--test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
--test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
--test_port(95 downto 64) <= m_address;
--test_port(63 downto 32) <= m_writedata;
--test_port(31 downto 0) <= m_readdata;
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <=
tcp_readdata(7 downto 0) & tcp_readdata(15 downto 8) &
tcp_readdata(23 downto 16) & tcp_readdata(31 downto 24);
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
mbf_writedata <=
Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <=
Bus2MAC_PKT_BE(0) & Bus2MAC_PKT_BE(1) &
Bus2MAC_PKT_BE(2) & Bus2MAC_PKT_BE(3);
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <=
mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_MAC_REG_PLB_AWIDTH,
gEndian => "big"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE_s( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
clk => clk50,
rst => rst,
s_address => mac_address( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1, 1),
C_BUS2CORE_CLK_RATIO => C_MAC_REG_BUS2CORE_CLK_RATIO,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_REG_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_REG_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_REG_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_REG_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_Reset => Bus2MAC_REG_Reset,
IP2Bus_Data => IP2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
PLB_ABus => MAC_REG_ABus,
PLB_BE => MAC_REG_BE( 0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1 ),
PLB_MSize => MAC_REG_MSize,
PLB_PAValid => MAC_REG_PAValid,
PLB_RNW => MAC_REG_RNW,
PLB_SAValid => MAC_REG_SAValid,
PLB_TAttribute => MAC_REG_TAttribute,
PLB_UABus => MAC_REG_UABus,
PLB_abort => MAC_REG_abort,
PLB_busLock => MAC_REG_busLock,
PLB_lockErr => MAC_REG_lockErr,
PLB_masterID => MAC_REG_masterID( 0 to C_MAC_REG_PLB_MID_WIDTH - 1 ),
PLB_rdBurst => MAC_REG_rdBurst,
PLB_rdPendPri => MAC_REG_rdPendPri,
PLB_rdPendReq => MAC_REG_rdPendReq,
PLB_rdPrim => MAC_REG_rdPrim,
PLB_reqPri => MAC_REG_reqPri,
PLB_size => MAC_REG_size,
PLB_type => MAC_REG_type,
PLB_wrBurst => MAC_REG_wrBurst,
PLB_wrDBus => MAC_REG_wrDBus( 0 to C_MAC_REG_PLB_DWIDTH - 1 ),
PLB_wrPendPri => MAC_REG_wrPendPri,
PLB_wrPendReq => MAC_REG_wrPendReq,
PLB_wrPrim => MAC_REG_wrPrim,
SPLB_Clk => MAC_REG_Clk,
SPLB_Rst => MAC_REG_Rst,
Sl_MBusy => MAC_REG_MBusy( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_REG_MIRQ( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_REG_MRdErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_REG_MWrErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_SSize => MAC_REG_SSize,
Sl_addrAck => MAC_REG_addrAck,
Sl_rdBTerm => MAC_REG_rdBTerm,
Sl_rdComp => MAC_REG_rdComp,
Sl_rdDAck => MAC_REG_rdDAck,
Sl_rdDBus => MAC_REG_rdDBus( 0 to C_MAC_REG_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_REG_rdWdAddr,
Sl_rearbitrate => MAC_REG_rearbitrate,
Sl_wait => MAC_REG_wait,
Sl_wrBTerm => MAC_REG_wrBTerm,
Sl_wrComp => MAC_REG_wrComp,
Sl_wrDAck => MAC_REG_wrDAck
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => booleanToInteger(false),
endian_g => "big",
gNumSmi => C_NUM_SMI,
genABuf1_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_0),
genABuf2_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_1),
genEvent_g => booleanToInteger(C_PDI_GEN_EVENT),
genInternalAp_g => booleanToInteger(C_GEN_PLB_BUS_IF),
genIoBuf_g => booleanToInteger(false),
genLedGadget_g => booleanToInteger(C_PDI_GEN_LED),
genOnePdiClkDomain_g => booleanToInteger(false),
genPdi_g => booleanToInteger(C_GEN_PDI),
genSimpleIO_g => booleanToInteger(C_GEN_SIMPLE_IO),
genSmiIO => booleanToInteger(false),
genSpiAp_g => booleanToInteger(C_GEN_SPI_IF),
genTimeSync_g => booleanToInteger(C_PDI_GEN_TIME_SYNC),
gen_dma_observer_g => booleanToInteger(C_OBSERVER_ENABLE),
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => C_PDI_REV,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => booleanToInteger(true),
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => booleanToInteger(false),
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => booleanToInteger(C_PAP_LOW_ACT),
pcpSysId => C_PCP_SYS_ID,
pioValLen_g => C_PIO_VAL_LENGTH,
pulseWidth2ndCmpTimer_g => C_PULSE_WIDTH_2nd_CMP_TIMER,
spiBigEnd_g => booleanToInteger(false),
spiCPHA_g => booleanToInteger(C_SPI_CPHA),
spiCPOL_g => booleanToInteger(C_SPI_CPOL),
use2ndCmpTimer_g => booleanToInteger(C_MAC_GEN_SECOND_TIMER),
use2ndPhy_g => booleanToInteger(C_USE_2ND_PHY),
useIntPacketBuf_g => booleanToInteger(C_MAC_PKT_EN),
usePulse2ndCmpTimer_g => booleanToInteger(C_USE_PULSE_2nd_CMP_TIMER),
useRmii_g => booleanToInteger(C_USE_RMII),
useRxIntPacketBuf_g => booleanToInteger(C_MAC_PKT_RX_EN)
)
port map(
mac_address(0) => mac_address(0),
mac_address(1) => mac_address(1),
mac_address(2) => mac_address(2),
mac_address(3) => mac_address(3),
mac_address(4) => mac_address(4),
mac_address(5) => mac_address(5),
mac_address(6) => mac_address(6),
mac_address(7) => mac_address(7),
mac_address(8) => mac_address(8),
mac_address(9) => mac_address(9),
mac_address(10) => mac_address(10),
mac_address(11) => mac_address(11),
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_address => m_address,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
rst <= Bus2MAC_REG_Reset or Bus2MAC_CMP_Reset or MAC_DMA_RST or Bus2MAC_PKT_Reset;
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
GND <= GND_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_PLB_BURST_MASTER : plbv46_master_burst
generic map (
C_FAMILY => C_FAMILY,
C_INHIBIT_CC_BLE_INCLUSION => 1,
C_MPLB_AWIDTH => C_MAC_DMA_PLB_AWIDTH,
C_MPLB_DWIDTH => C_MAC_DMA_PLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MAC_DMA_PLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => 32
)
port map(
Bus2IP_MstRd_d => Bus2MAC_DMA_MstRd_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2IP_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2IP_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2IP_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2IP_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2IP_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2IP_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2IP_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2IP_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
IP2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
IP2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
IP2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
IP2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
IP2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
IP2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
IP2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
IP2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
IP2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
IP2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
IP2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
IP2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
IP2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MD_Error => MAC_DMA_error,
MPLB_Clk => MAC_DMA_Clk,
MPLB_Rst => MAC_DMA_Rst,
M_ABus => MAC_DMA_ABus,
M_BE => MAC_DMA_BE( 0 to (C_MAC_DMA_PLB_DWIDTH/8)-1 ),
M_MSize => MAC_DMA_MSize,
M_RNW => MAC_DMA_RNW,
M_TAttribute => MAC_DMA_TAttribute,
M_UABus => MAC_DMA_UABus,
M_abort => MAC_DMA_abort,
M_busLock => MAC_DMA_busLock,
M_lockErr => MAC_DMA_lockErr,
M_priority => MAC_DMA_priority,
M_rdBurst => MAC_DMA_rdBurst,
M_request => MAC_DMA_request,
M_size => MAC_DMA_size,
M_type => MAC_DMA_type,
M_wrBurst => MAC_DMA_wrBurst,
M_wrDBus => MAC_DMA_wrDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MAddrAck => MAC_DMA_MAddrAck,
PLB_MBusy => MAC_DMA_MBusy,
PLB_MIRQ => MAC_DMA_MIRQ,
PLB_MRdBTerm => MAC_DMA_MRdBTerm,
PLB_MRdDAck => MAC_DMA_MRdDAck,
PLB_MRdDBus => MAC_DMA_MRdDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MRdErr => MAC_DMA_MRdErr,
PLB_MRdWdAddr => MAC_DMA_MRdWdAddr,
PLB_MRearbitrate => MAC_DMA_MRearbitrate,
PLB_MSSize => MAC_DMA_MSSize,
PLB_MTimeout => MAC_DMA_MTimeout,
PLB_MWrBTerm => MAC_DMA_MWrBTerm,
PLB_MWrDAck => MAC_DMA_MWrDAck,
PLB_MWrErr => MAC_DMA_MWrErr
);
end generate genMacDmaPlbBurst;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U4 : ODDR2
port map(
C0 => clk50,
C1 => NET118078,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
NET118078 <= not(clk50);
U6 : ODDR2
port map(
C0 => clk50,
C1 => NET118214,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET118214 <= not(clk50);
end generate oddr2_1;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => Bus2MAC_DMA_MstRd_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2MAC_DMA_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2MAC_DMA_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2MAC_DMA_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2MAC_DMA_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2MAC_DMA_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2MAC_DMA_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
MAC_DMA2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MAC_DMA_CLK => MAC_DMA_CLK,
MAC_DMA_Rst => MAC_DMA_Rst,
m_address => m_address( 31 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
Bus2MAC_DMA_MstRd_d_s <= Bus2MAC_DMA_MstRd_d(7 downto 0) & Bus2MAC_DMA_MstRd_d(15 downto 8) &
Bus2MAC_DMA_MstRd_d(23 downto 16) & Bus2MAC_DMA_MstRd_d(31 downto 24);
MAC_DMA2Bus_MstWr_d <= MAC_DMA2Bus_MstWr_d_s(7 downto 0) & MAC_DMA2Bus_MstWr_d_s(15 downto 8) &
MAC_DMA2Bus_MstWr_d_s(23 downto 16) & MAC_DMA2Bus_MstWr_d_s(31 downto 24);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_PKT_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_PKT_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_PKT_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_PKT_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_MAC_PKT_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_Reset => Bus2MAC_PKT_Reset,
IP2Bus_Data => MAC_PKT2Bus_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
PLB_ABus => MAC_PKT_ABus,
PLB_BE => MAC_PKT_BE( 0 to (C_MAC_PKT_PLB_DWIDTH/8)-1 ),
PLB_MSize => MAC_PKT_MSize,
PLB_PAValid => MAC_PKT_PAValid,
PLB_RNW => MAC_PKT_RNW,
PLB_SAValid => MAC_PKT_SAValid,
PLB_TAttribute => MAC_PKT_TAttribute,
PLB_UABus => MAC_PKT_UABus,
PLB_abort => MAC_PKT_abort,
PLB_busLock => MAC_PKT_busLock,
PLB_lockErr => MAC_PKT_lockErr,
PLB_masterID => MAC_PKT_masterID( 0 to C_MAC_PKT_PLB_MID_WIDTH-1 ),
PLB_rdBurst => MAC_PKT_rdBurst,
PLB_rdPendPri => MAC_PKT_rdPendPri,
PLB_rdPendReq => MAC_PKT_rdPendReq,
PLB_rdPrim => MAC_PKT_rdPrim,
PLB_reqPri => MAC_PKT_reqPri,
PLB_size => MAC_PKT_size,
PLB_type => MAC_PKT_type,
PLB_wrBurst => MAC_PKT_wrBurst,
PLB_wrDBus => MAC_PKT_wrDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
PLB_wrPendPri => MAC_PKT_wrPendPri,
PLB_wrPendReq => MAC_PKT_wrPendReq,
PLB_wrPrim => MAC_PKT_wrPrim,
SPLB_Clk => MAC_PKT_Clk,
SPLB_Rst => MAC_PKT_Rst,
Sl_MBusy => MAC_PKT_MBusy( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_PKT_MIRQ( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_PKT_MRdErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_PKT_MWrErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_SSize => MAC_PKT_SSize,
Sl_addrAck => MAC_PKT_addrAck,
Sl_rdBTerm => MAC_PKT_rdBTerm,
Sl_rdComp => MAC_PKT_rdComp,
Sl_rdDAck => MAC_PKT_rdDAck,
Sl_rdDBus => MAC_PKT_rdDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_PKT_rdWdAddr,
Sl_rearbitrate => MAC_PKT_rearbitrate,
Sl_wait => MAC_PKT_wait,
Sl_wrBTerm => MAC_PKT_wrBTerm,
Sl_wrComp => MAC_PKT_wrComp,
Sl_wrDAck => MAC_PKT_wrDAck
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_PDI_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_Reset => Bus2PDI_PCP_Reset,
IP2Bus_Data => PDI_PCP2Bus_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
PLB_ABus => PDI_PCP_ABus,
PLB_BE => PDI_PCP_BE( 0 to (C_PDI_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_PCP_MSize,
PLB_PAValid => PDI_PCP_PAValid,
PLB_RNW => PDI_PCP_RNW,
PLB_SAValid => PDI_PCP_SAValid,
PLB_TAttribute => PDI_PCP_TAttribute,
PLB_UABus => PDI_PCP_UABus,
PLB_abort => PDI_PCP_abort,
PLB_busLock => PDI_PCP_busLock,
PLB_lockErr => PDI_PCP_lockErr,
PLB_masterID => PDI_PCP_masterID( 0 to C_PDI_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_PCP_rdBurst,
PLB_rdPendPri => PDI_PCP_rdPendPri,
PLB_rdPendReq => PDI_PCP_rdPendReq,
PLB_rdPrim => PDI_PCP_rdPrim,
PLB_reqPri => PDI_PCP_reqPri,
PLB_size => PDI_PCP_size,
PLB_type => PDI_PCP_type,
PLB_wrBurst => PDI_PCP_wrBurst,
PLB_wrDBus => PDI_PCP_wrDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_PCP_wrPendPri,
PLB_wrPendReq => PDI_PCP_wrPendReq,
PLB_wrPrim => PDI_PCP_wrPrim,
SPLB_Clk => PDI_PCP_Clk,
SPLB_Rst => PDI_PCP_Rst,
Sl_MBusy => PDI_PCP_MBusy( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_PCP_MIRQ( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_PCP_MRdErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_PCP_MWrErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_SSize => PDI_PCP_SSize,
Sl_addrAck => PDI_PCP_addrAck,
Sl_rdBTerm => PDI_PCP_rdBTerm,
Sl_rdComp => PDI_PCP_rdComp,
Sl_rdDAck => PDI_PCP_rdDAck,
Sl_rdDBus => PDI_PCP_rdDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_PCP_rdWdAddr,
Sl_rearbitrate => PDI_PCP_rearbitrate,
Sl_wait => PDI_PCP_wait,
Sl_wrBTerm => PDI_PCP_wrBTerm,
Sl_wrComp => PDI_PCP_wrComp,
Sl_wrDAck => PDI_PCP_wrDAck
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
rstPcp <= Bus2PDI_PCP_Reset;
--pcp_writedata <= Bus2PDI_PCP_Data;
pcp_writedata <= Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(23 downto 16) & Bus2PDI_PCP_Data(31 downto 24);
--pcp_writedata <= Bus2PDI_PCP_Data(15 downto 0) & Bus2PDI_PCP_Data(31 downto 16) when Bus2PDI_PCP_BE = "1100" or Bus2PDI_PCP_BE = "0011" else
-- Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(31 downto 24) & Bus2PDI_PCP_Data(23 downto 16) when Bus2PDI_PCP_BE = "1000" or Bus2PDI_PCP_BE = "0100" or Bus2PDI_PCP_BE = "0010" or Bus2PDI_PCP_BE = "0001" else
-- Bus2PDI_PCP_Data;
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
--pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_byteenable <= Bus2PDI_PCP_BE(0) & Bus2PDI_PCP_BE(1) & Bus2PDI_PCP_BE(2) & Bus2PDI_PCP_BE(3);
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
--PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_Data <= pcp_readdata(7 downto 0) & pcp_readdata(15 downto 8) & pcp_readdata(23 downto 16) & pcp_readdata(31 downto 24);
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_PLB_BUS_IF) generate
begin
PDI_AP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_AP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_AP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_AP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_AP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_PDI_AP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_PDI_AP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_Reset => Bus2PDI_AP_Reset,
IP2Bus_Data => PDI_AP2Bus_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
PLB_ABus => PDI_AP_ABus,
PLB_BE => PDI_AP_BE( 0 to (C_PDI_AP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_AP_MSize,
PLB_PAValid => PDI_AP_PAValid,
PLB_RNW => PDI_AP_RNW,
PLB_SAValid => PDI_AP_SAValid,
PLB_TAttribute => PDI_AP_TAttribute,
PLB_UABus => PDI_AP_UABus,
PLB_abort => PDI_AP_abort,
PLB_busLock => PDI_AP_busLock,
PLB_lockErr => PDI_AP_lockErr,
PLB_masterID => PDI_AP_masterID( 0 to C_PDI_AP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_AP_rdBurst,
PLB_rdPendPri => PDI_AP_rdPendPri,
PLB_rdPendReq => PDI_AP_rdPendReq,
PLB_rdPrim => PDI_AP_rdPrim,
PLB_reqPri => PDI_AP_reqPri,
PLB_size => PDI_AP_size,
PLB_type => PDI_AP_type,
PLB_wrBurst => PDI_AP_wrBurst,
PLB_wrDBus => PDI_AP_wrDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_AP_wrPendPri,
PLB_wrPendReq => PDI_AP_wrPendReq,
PLB_wrPrim => PDI_AP_wrPrim,
SPLB_Clk => PDI_AP_Clk,
SPLB_Rst => PDI_AP_Rst,
Sl_MBusy => PDI_AP_MBusy( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_AP_MIRQ( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_AP_MRdErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_AP_MWrErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_SSize => PDI_AP_SSize,
Sl_addrAck => PDI_AP_addrAck,
Sl_rdBTerm => PDI_AP_rdBTerm,
Sl_rdComp => PDI_AP_rdComp,
Sl_rdDAck => PDI_AP_rdDAck,
Sl_rdDBus => PDI_AP_rdDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_AP_rdWdAddr,
Sl_rearbitrate => PDI_AP_rearbitrate,
Sl_wait => PDI_AP_wait,
Sl_wrBTerm => PDI_AP_wrBTerm,
Sl_wrComp => PDI_AP_wrComp,
Sl_wrDAck => PDI_AP_wrDAck
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
rstAp <= Bus2PDI_AP_Reset;
--ap_writedata <= Bus2PDI_AP_Data;
ap_writedata <= Bus2PDI_AP_Data(7 downto 0) & Bus2PDI_AP_Data(15 downto 8) & Bus2PDI_AP_Data(23 downto 16) & Bus2PDI_AP_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
--ap_byteenable <= Bus2PDI_AP_BE;
ap_byteenable <= Bus2PDI_AP_BE(0) & Bus2PDI_AP_BE(1) & Bus2PDI_AP_BE(2) & Bus2PDI_AP_BE(3);
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
--PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_Data <= ap_readdata(7 downto 0) & ap_readdata(15 downto 8) & ap_readdata(23 downto 16) & ap_readdata(31 downto 24);
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
rstPcp <= Bus2SMP_PCP_Reset;
--smp_writedata <= Bus2SMP_PCP_Data;
smp_writedata <= Bus2SMP_PCP_Data(7 downto 0) & Bus2SMP_PCP_Data(15 downto 8) & Bus2SMP_PCP_Data(23 downto 16) & Bus2SMP_PCP_Data(31 downto 24);
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
--smp_byteenable <= Bus2SMP_PCP_BE;
smp_byteenable <= Bus2SMP_PCP_BE(0) & Bus2SMP_PCP_BE(1) & Bus2SMP_PCP_BE(2) & Bus2SMP_PCP_BE(3);
smp_address <= Bus2SMP_PCP_Addr(2);
--SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_Data <= smp_readdata(7 downto 0) & smp_readdata(15 downto 8) & smp_readdata(23 downto 16) & smp_readdata(31 downto 24);
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_SMP_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_SMP_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SMP_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_SMP_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_SMP_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_Reset => Bus2SMP_PCP_Reset,
IP2Bus_Data => SMP_PCP2Bus_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
PLB_ABus => SMP_PCP_ABus,
PLB_BE => SMP_PCP_BE( 0 to (C_SMP_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => SMP_PCP_MSize,
PLB_PAValid => SMP_PCP_PAValid,
PLB_RNW => SMP_PCP_RNW,
PLB_SAValid => SMP_PCP_SAValid,
PLB_TAttribute => SMP_PCP_TAttribute,
PLB_UABus => SMP_PCP_UABus,
PLB_abort => SMP_PCP_abort,
PLB_busLock => SMP_PCP_busLock,
PLB_lockErr => SMP_PCP_lockErr,
PLB_masterID => SMP_PCP_masterID( 0 to C_SMP_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => SMP_PCP_rdBurst,
PLB_rdPendPri => SMP_PCP_rdPendPri,
PLB_rdPendReq => SMP_PCP_rdPendReq,
PLB_rdPrim => SMP_PCP_rdPrim,
PLB_reqPri => SMP_PCP_reqPri,
PLB_size => SMP_PCP_size,
PLB_type => SMP_PCP_type,
PLB_wrBurst => SMP_PCP_wrBurst,
PLB_wrDBus => SMP_PCP_wrDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => SMP_PCP_wrPendPri,
PLB_wrPendReq => SMP_PCP_wrPendReq,
PLB_wrPrim => SMP_PCP_wrPrim,
SPLB_Clk => SMP_PCP_Clk,
SPLB_Rst => SMP_PCP_Rst,
Sl_MBusy => SMP_PCP_MBusy( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => SMP_PCP_MIRQ( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => SMP_PCP_MRdErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => SMP_PCP_MWrErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_SSize => SMP_PCP_SSize,
Sl_addrAck => SMP_PCP_addrAck,
Sl_rdBTerm => SMP_PCP_rdBTerm,
Sl_rdComp => SMP_PCP_rdComp,
Sl_rdDAck => SMP_PCP_rdDAck,
Sl_rdDBus => SMP_PCP_rdDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => SMP_PCP_rdWdAddr,
Sl_rearbitrate => SMP_PCP_rearbitrate,
Sl_wait => SMP_PCP_wait,
Sl_wrBTerm => SMP_PCP_wrBTerm,
Sl_wrComp => SMP_PCP_wrComp,
Sl_wrDAck => SMP_PCP_wrDAck
);
end generate genSmpIo;
end struct;
| gpl-2.0 | 07cfd09c28d089147efdfcb75fd8a5a2 | 0.608938 | 3.005742 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/Form_FSM.vhd | 2 | 10,891 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PXData_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
PX_start_i : in std_logic;
PX_present_i : in std_logic;
PX_data_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
PXwen_o : out std_logic);
end PXData_FSM;
architecture rtl of PXData_FSM is
type t_state is (waiting,
check_bus_busy,
send_START,
send_A7,
send_A6,
send_A5,
send_A4,
send_A3,
send_A2,
send_A1,
send_RW,
read_A_ACK,
send_D7,
send_D6,
send_D5,
send_D4,
send_D3,
send_D2,
send_D1,
send_D0,
read_D_ACK,
read_D7,
read_D6,
read_D5,
read_D4,
read_D3,
read_D2,
read_D1,
read_D0,
send_NOACK,
send_ACK,
restart_READ,
restart_DATA,
send_STOPCLKRD,
send_STOPCLK,
send_STOP,
write_sda);
signal s_state : t_state;
signal s_sdadir : std_logic; -- Signal buffer for sdadir_o !!
signal s_sda_response : std_logic;
signal s_count : unsigned(3 downto 0);
signal s_timeout: unsigned(4 downto 0);
signal s_d_serin : std_logic_vector(7 downto 0);
signal s_addrw : std_logic_vector(7 downto 0);
signal s_nbytes : unsigned(7 downto 0);
signal s_bytecount : unsigned(7 downto 0);
signal s_rwq : std_logic;
begin
p_format: process (clk_i, reset_n_i)
begin -- process p_serin
if (reset_n_i = '0') then -- asynchronous reset (active low)
s_state <= waiting;
s_count <= conv_unsigned(0,4);
s_d_serin <= "00000000";
pd_o <= "00000000";
error_o <= "00000000";
sclen_o <= '0';
readen_o <= '0';
sda_o <= '1';
sdadir_o <= '0'; s_sdadir <= '0';
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when check_bus_busy =>
if ( sda_i = '1' AND scl_i = '1' ) then
-- bus is free
s_state <= send_START;
else
-- bus isn't free
s_timeout <= s_timeout - conv_unsigned(1,1); -- decrement s_timeout
if (s_timeout = 0) then
error_o <= "00000001";
s_state <= waiting;
end if;
end if;
-------------------------------------------------------------------------
when send_START =>
sdadir_o <= '1'; s_sdadir <= '0';
sclen_o <= '1';
readen_o <= '0';
sda_o <= '0';
s_bytecount <= conv_unsigned(0,8);
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
s_state <= send_A7 ;
-------------------------------------------------------------------------
when send_A7 =>
sda_o <= s_addrw(7);
s_state <= send_A6;
-------------------------------------------------------------------------
when send_A6 =>
sda_o <= s_addrw(6);
s_state <= send_A5;
-------------------------------------------------------------------------
when send_A5 =>
sda_o <= s_addrw(5);
s_state <= send_A4;
-------------------------------------------------------------------------
when send_A4 =>
sda_o <= s_addrw(4);
s_state <= send_A3;
-------------------------------------------------------------------------
when send_A3 =>
sda_o <= s_addrw(3);
s_state <= send_A2;
-------------------------------------------------------------------------
when send_A2 =>
sda_o <= s_addrw(2);
s_state <= send_A1;
-------------------------------------------------------------------------
when send_A1 =>
sda_o <= s_addrw(1);
s_state <= send_RW;
-----------------------------------------------------------------------
when send_RW =>
sda_o <= s_addrw(0);
s_state <= read_A_ACK;
-------------------------------------------------------------------------
when read_A_ACK =>
sda_o <= '0';
sdadir_o <= '0'; s_sdadir <= '0';
s_state <= send_D7;
if ( s_rwq = '1') then -- read
s_state <= read_D7;
else -- write
s_state <= send_D7;
end if;
-------------------------------------------------------------------------
when send_D7 =>
sdadir_o <= '1'; s_sdadir <= '0';
if(s_sda_response = '0') then
-- ADDRESS acknowledged
sda_o <= data_i(7);
s_state <= send_D6;
else
-- A_ACK ERROR
error_o <= "00000010";
sda_o <= '1';
sclen_o <= '0';
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when send_D6 =>
sda_o <= data_i(6);
s_bytecount <= s_bytecount + conv_unsigned(1,8);
s_state <= send_D5;
-------------------------------------------------------------------------
when send_D5 =>
sda_o <= data_i(5);
s_state <= send_D4;
-------------------------------------------------------------------------
when send_D4 =>
sda_o <= data_i(4);
s_state <= send_D3;
-------------------------------------------------------------------------
when send_D3 =>
sda_o <= data_i(3);
s_state <= send_D2;
-------------------------------------------------------------------------
when send_D2 =>
sda_o <= data_i(2);
s_state <= send_D1;
-------------------------------------------------------------------------
when send_D1 =>
sda_o <= data_i(1);
s_state <= send_D0;
-----------------------------------------------------------------------
when send_D0 =>
sda_o <= data_i(0);
s_state <= read_D_ACK;
-------------------------------------------------------------------------
when read_D_ACK =>
sda_o <= '0';
sdadir_o <= '0'; s_sdadir <= '0';
if(s_nbytes = s_bytecount) then
s_state <= send_STOPCLK;
else
s_state <= restart_DATA;
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
end if;
-------------------------------------------------------------------------
when read_D7 =>
if(s_sda_response = '0') then
-- ADDRESS acknowledged
s_state <= read_D6;
else
-- A_ACK ERROR
sdadir_o <= '1'; s_sdadir <= '0';
error_o <= "00000010";
sda_o <= '1';
sclen_o <= '0';
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when read_D6 =>
readen_o <= '0';
s_d_serin(7)<= s_sda_response;
s_bytecount <= s_bytecount + conv_unsigned(1,8);
next_b <= CONV_STD_LOGIC_VECTOR(s_bytecount,2);
s_state <= read_D5;
-------------------------------------------------------------------------
when read_D5 =>
s_d_serin(6)<= s_sda_response;
s_state <= read_D4;
-------------------------------------------------------------------------
when read_D4 =>
s_d_serin(5)<= s_sda_response;
s_state <= read_D3;
-------------------------------------------------------------------------
when read_D3 =>
s_d_serin(4)<=s_sda_response;
s_state <= read_D2;
-------------------------------------------------------------------------
when read_D2 =>
s_d_serin(3)<= s_sda_response;
s_state <= read_D1;
-------------------------------------------------------------------------
when read_D1 =>
s_d_serin(2)<= s_sda_response;
s_state <= read_D0;
-------------------------------------------------------------------------
when read_D0 =>
s_d_serin(1)<= s_sda_response;
if(s_nbytes = s_bytecount) then
s_state <= send_NOACK;
else
s_state <= send_ACK;
end if;
-------------------------------------------------------------------------
when send_NOACK =>
s_d_serin(0)<= s_sda_response;
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= '1'; -- NOACK BY MASTER
s_state <= send_STOPCLKRD;
-------------------------------------------------------------------------
when send_ACK =>
s_d_serin(0)<= s_sda_response;
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= '0'; -- DTACK by Master
s_state <= restart_READ;
-------------------------------------------------------------------------
when restart_READ =>
sdadir_o <= '0'; s_sdadir <= '0';
readen_o <= '1';
pd_o <= s_d_serin;
s_d_serin(7)<= s_sda_response;
s_state <= read_D6;
-------------------------------------------------------------------------
when restart_DATA =>
if(s_sda_response = '0') then
-- DATA acknowledged
sdadir_o <= '1'; s_sdadir <= '1';
sda_o <= data_i(7);
s_state <= send_D6;
else
-- D_ACK ERROR
error_o <= "00000100";
s_state <= send_STOP;
end if;
-------------------------------------------------------------------------
when send_STOPCLKRD =>
sda_o <= '0';
sclen_o <= '0';
readen_o <= '1';
pd_o <= s_d_serin;
s_state <= send_STOP;
-------------------------------------------------------------------------
when send_STOPCLK =>
sda_o <= '0';
sclen_o <= '0';
if(s_sda_response = '0') then
-- DATA acknowledged
s_state <= send_STOP;
else
-- D_ACK ERROR
error_o <= "00000100";
s_state <= send_STOP;
end if;
-------------------------------------------------------------------------
when send_STOP =>
sda_o <= '1';
sclen_o <= '0';
readen_o <= '0';
s_state <= waiting;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if sub_i2c_i = '1' then
-- VME Start I2C Cycle command detected.
s_addrw <= addrw_i;
s_nbytes <= nbytes_i;
s_rwq <= addrw_i(0);
s_state <= check_bus_busy;
-- Initialize input counter
s_timeout <= conv_unsigned(10,5);
end if;
end case;
end if;
end process p_format;
end rtl;
| unlicense | 405b9a8d3086d12a2f65a255a0d193bd | 0.335047 | 4.168006 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ram_dq_INST_kb.vhd | 2 | 7,075 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_kb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_kb IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_kb;
ARCHITECTURE SYN OF ram_dq_inst_kb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_kb",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_kb"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_kb"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | 316a15f623409d5dd8d8b2c1e55210f1 | 0.672085 | 3.439475 | false | false | false | false |
scottlbaker/PDP11-SOC | src/soc.vhd | 1 | 17,908 |
--========================================================================
-- soc.vhd :: pdp-11 SOC for Latice experiments
--
-- contains:
--
-- (1) pdp-11 core
-- (1) UART
-- (1) timer
-- (1) random number generator
-- (1) Digital I/O
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity SOC is
port (
-- Output Port A
PORTA : out std_logic_vector(7 downto 0);
-- UART
UART_RXD : in std_logic; -- receive data
UART_TXD : out std_logic; -- transmit data
-- Reset and Clock
SYSRESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end SOC;
architecture BEHAVIORAL of SOC is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
signal ADDR_OUT : std_logic_vector(15 downto 0);
signal DATA_IX : std_logic_vector(15 downto 0);
signal DATA_OX : std_logic_vector(15 downto 0);
signal IMSK_REG : std_logic_vector( 7 downto 0);
signal ISRC : std_logic_vector( 7 downto 0);
signal PHASE : std_logic_vector( 3 downto 0);
signal IO_RESET : std_logic; -- I/O reset (active high)
signal RESET1 : std_logic; -- short reset (active low)
signal RESET : std_logic; -- long reset (active low)
signal RW : std_logic; -- Read/Write (0=write)
signal RDY : std_logic; -- Ready/Wait
signal BYTEOP : std_logic; -- byte operation
signal SYNC : std_logic; -- Opcode fetch status
signal FEN : std_logic; -- clock enable
signal BOOT_RE : std_logic; -- Boot RAM read enable
signal BOOT_WE : std_logic; -- Boot RAM write enable
signal IO_WE : std_logic; -- IO write enable
signal TIMR_IRQ : std_logic; -- Timer interrupt
signal UART_RRQ : std_logic; -- UART receive interrupt
signal UART_TRQ : std_logic; -- UART transmit interrupt
signal UART_RD : std_logic; -- UART read data valid
signal TIMR_DATA : std_logic_vector(15 downto 0);
signal BOOT_DATA : std_logic_vector(15 downto 0);
signal UART_DATA : std_logic_vector( 7 downto 0);
signal PRTA_DATA : std_logic_vector( 7 downto 0);
signal RAND_DATA : std_logic_vector( 7 downto 0);
signal UART_CS : std_logic;
signal TIMR_CS : std_logic;
signal PRTA_CS : std_logic;
signal IMSK_CS : std_logic;
signal RAND_CS : std_logic;
signal IRQ0 : std_logic; -- Interrupt (active-low)
signal IRQ1 : std_logic; -- Interrupt (active-low)
signal IRQ2 : std_logic; -- Interrupt (active-low)
signal IRQ3 : std_logic; -- Interrupt (active-low)
signal DBUG1 : std_logic; -- for debug
signal DBUG2 : std_logic; -- for debug
signal DBUG3 : std_logic; -- for debug
signal DBUG4 : std_logic; -- for debug
signal DBUG5 : std_logic; -- for debug
signal DBUG6 : std_logic; -- for debug
signal DBUG7 : std_logic; -- for debug
--================================================================
-- Constant definition section
--================================================================
-- $0000 -> $1FFF Boot RAM (8k)
constant BOOT_SEL : std_logic_vector(15 downto 14) := "00";
-- $F000 -> $F006 UART registers
constant UART_SEL : std_logic_vector(15 downto 3) := "1111000000000";
-- $F008 -> $F00A Timer registers
constant TIMR_SEL : std_logic_vector(15 downto 2) := "11110000000010";
-- $F00C Output Register
constant PRTA_SEL : std_logic_vector(15 downto 0) := "1111000000001100";
-- $F00E Interrupt mask register
constant IMSK_SEL : std_logic_vector(15 downto 0) := "1111000000001110";
-- $F010 -> $F012 Random number generator
constant RAND_SEL : std_logic_vector(15 downto 2) := "11110000000100";
-- $F014 Interrupt source register
constant ISRC_SEL : std_logic_vector(15 downto 0) := "1111000000010100";
--================================================================
-- Component definition section
--================================================================
--==================================
-- pdp-11
--==================================
component IP_PDP11
port (
ADDR_OUT : out std_logic_vector(15 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
R_W : out std_logic; -- 1==read 0==write
BYTE : out std_logic; -- byte memory operation
SYNC : out std_logic; -- Opcode fetch status
IRQ0 : in std_logic; -- Interrupt (active-low)
IRQ1 : in std_logic; -- Interrupt (active-low)
IRQ2 : in std_logic; -- Interrupt (active-low)
IRQ3 : in std_logic; -- Interrupt (active-low)
RDY : in std_logic; -- Ready input
RESET : in std_logic; -- Reset input (active-low)
FEN : in std_logic; -- clock enable
CLK : in std_logic; -- System Clock
DBUG7 : out std_logic; -- for debug
DBUG6 : out std_logic; -- for debug
DBUG5 : out std_logic; -- for debug
DBUG4 : out std_logic; -- for debug
DBUG3 : out std_logic; -- for debug
DBUG2 : out std_logic; -- for debug
DBUG1 : out std_logic -- for debug
);
end component;
--===============================
-- UART (no handshake lines)
--===============================
component UART
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
BYTE_SEL : in std_logic; -- byte select
REG_SEL : in std_logic_vector( 1 downto 0); -- register select
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector( 7 downto 0); -- read data
RX_IRQ : out std_logic; -- RX interrupt req
TX_IRQ : out std_logic; -- TX interrupt req
RXD : in std_logic; -- received data
TXD : out std_logic; -- transmit data
RESET : in std_logic; -- system reset
RDV : in std_logic; -- read data valid
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Timer
--==============================
component TIMER
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector(15 downto 0); -- read data
IRQ : out std_logic; -- DMA Interrupt
SEL_IC : in std_logic; -- select initial count
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Random Number Generator
--==============================
component RAND8
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic; -- register select
WR_DATA : in std_logic_vector(7 downto 0); -- write data
RD_DATA : out std_logic_vector(7 downto 0); -- read data
RESET : in std_logic; -- system reset
FEN : in std_logic; -- clock enable
FCLK : in std_logic -- fast clock
);
end component;
--==============================
-- Output Port
--==============================
component OUTPORT
port (
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(7 downto 0); -- data in
RD_DATA : out std_logic_vector(7 downto 0); -- data out
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--=========================================
-- Boot RAM (8kx16)
--=========================================
component RAM
port (
RADDR : in std_logic_vector(12 downto 0);
WADDR : in std_logic_vector(12 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
BYTEOP : in std_logic; -- byte operation
REN : in std_logic; -- read enable
WEN : in std_logic; -- write enable
WCLK : in std_logic;
RCLK : in std_logic
);
end component;
--=========================================
-- Debounce and Sync Reset
--=========================================
component XRESET
port (
RST_OUT1 : out std_logic;
RST_OUT2 : out std_logic;
RST_IN : in std_logic;
CLK : in std_logic
);
end component;
begin
--=============================================
-- Clock Phase Divider (divide by 4)
-- S0=000 S1=001 S2=010 S3=100
--=============================================
CLOCK_PHASE_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- count
PHASE <= PHASE(2 downto 0) & PHASE(3);
-- reset state
if (RESET1 = '0') then
PHASE <= "0001";
end if;
end if;
end process;
--==========================================================
-- System Clock Enable
--==========================================================
SYSTEM_CLOCK_ENABLE:
process(FCLK)
begin
if (FCLK = '1' and FCLK'event) then
FEN <= PHASE(3);
end if;
end process;
--==========================================================
-- Address Decoder
--==========================================================
ADDRESS_DECODER:
process(ADDR_OUT, UART_DATA, TIMR_DATA, PRTA_DATA,
IMSK_REG, ISRC, RAND_DATA, BOOT_DATA, PHASE, RW)
begin
UART_CS <= '0';
TIMR_CS <= '0';
PRTA_CS <= '0';
IMSK_CS <= '0';
RAND_CS <= '0';
BOOT_RE <= '0';
BOOT_WE <= '0';
IO_WE <= '0';
UART_RD <= '0';
DATA_IX <= BOOT_DATA;
-- Boot RAM
if (ADDR_OUT(15 downto 14) = BOOT_SEL) then
BOOT_RE <= PHASE(0) and RW;
BOOT_WE <= PHASE(3) and not RW;
end if;
-- UART registers
if (ADDR_OUT(15 downto 3) = UART_SEL) then
UART_CS <= '1';
DATA_IX <= "00000000" & UART_DATA;
UART_RD <= PHASE(3) and RW;
IO_WE <= PHASE(3) and not RW;
end if;
-- Timer registers
if (ADDR_OUT(15 downto 2) = TIMR_SEL) then
TIMR_CS <= '1';
DATA_IX <= TIMR_DATA;
IO_WE <= PHASE(3) and not RW;
end if;
-- output Port
if (ADDR_OUT(15 downto 0) = PRTA_SEL) then
PRTA_CS <= '1';
DATA_IX <= "00000000" & PRTA_DATA;
IO_WE <= PHASE(3) and not RW;
end if;
-- Interrupt Mask register
if (ADDR_OUT(15 downto 0) = IMSK_SEL) then
IMSK_CS <= '1';
DATA_IX <= "00000000" & IMSK_REG;
IO_WE <= PHASE(3) and not RW;
end if;
-- Interrupt Source register
if (ADDR_OUT(15 downto 0) = ISRC_SEL) then
DATA_IX <= "00000000" & ISRC;
IO_WE <= PHASE(3) and not RW;
end if;
-- Random Number registers
if (ADDR_OUT(15 downto 2) = RAND_SEL) then
RAND_CS <= '1';
DATA_IX <= "00000000" & RAND_DATA;
IO_WE <= PHASE(3) and not RW;
end if;
end process;
RDY <= '1'; -- Ready
IO_RESET <= not RESET;
PORTA <= PRTA_DATA;
--================================================
-- Interrupt mask register
--================================================
INTERRUPT_MASK_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((IMSK_CS = '1') and (IO_WE = '1')) then
IMSK_REG <= DATA_OX(7 downto 0);
end if;
-- reset state
if (RESET = '0') then
IMSK_REG <= (others => '0');
end if;
end if;
end process;
--================================================
-- Interrupt Source
--================================================
ISRC <= "00000" & UART_TRQ & UART_RRQ & TIMR_IRQ;
IRQ0 <= not ((IMSK_REG(7) and ISRC(7)) or
(IMSK_REG(6) and ISRC(6)) or
(IMSK_REG(5) and ISRC(5)) or
(IMSK_REG(4) and ISRC(4)) or
(IMSK_REG(3) and ISRC(3)) or
(IMSK_REG(2) and ISRC(2)) or
(IMSK_REG(1) and ISRC(1)) or
(IMSK_REG(0) and ISRC(0)));
IRQ1 <= '1'; -- Interrupt 1
IRQ2 <= '1'; -- Interrupt 2
IRQ3 <= '1'; -- Interrupt 3
--=========================================
-- Instantiate the pdp-11
--=========================================
UPROC:
IP_PDP11 port map (
ADDR_OUT => ADDR_OUT,
DATA_IN => DATA_IX,
DATA_OUT => DATA_OX,
R_W => RW,
BYTE => BYTEOP,
SYNC => SYNC,
IRQ0 => IRQ0,
IRQ1 => IRQ1,
IRQ2 => IRQ2,
IRQ3 => IRQ3,
RDY => RDY,
RESET => RESET,
FEN => FEN,
CLK => FCLK,
DBUG7 => DBUG7,
DBUG6 => DBUG6,
DBUG5 => DBUG5,
DBUG4 => DBUG4,
DBUG3 => DBUG3,
DBUG2 => DBUG2,
DBUG1 => DBUG1
);
--===========================================
-- Instantiate the UART
--===========================================
UART1:
UART port map (
CS => UART_CS,
WE => IO_WE,
BYTE_SEL => ADDR_OUT(0),
REG_SEL => ADDR_OUT(2 downto 1),
WR_DATA => DATA_OX,
RD_DATA => UART_DATA,
RX_IRQ => UART_RRQ,
TX_IRQ => UART_TRQ,
RXD => UART_RXD,
TXD => UART_TXD,
RESET => IO_RESET,
RDV => UART_RD,
FCLK => FCLK
);
--===========================================
-- Instantiate the TIMER
--===========================================
TIMER1:
TIMER port map (
CS => TIMR_CS,
WE => IO_WE,
WR_DATA => DATA_OX,
RD_DATA => TIMR_DATA,
IRQ => TIMR_IRQ,
SEL_IC => ADDR_OUT(1),
RESET => IO_RESET,
FCLK => FCLK
);
--===========================================
-- Instantiate the OUTPORT
--===========================================
PORT1:
OUTPORT port map (
CS => PRTA_CS,
WE => IO_WE,
WR_DATA => DATA_OX(7 downto 0),
RD_DATA => PRTA_DATA,
RESET => IO_RESET,
FCLK => FCLK
);
--===========================================
-- Instantiate the RAND generator
--===========================================
RAND8X:
RAND8 port map (
CS => RAND_CS,
WE => IO_WE,
REG_SEL => ADDR_OUT(1),
WR_DATA => DATA_OX(7 downto 0),
RD_DATA => RAND_DATA,
RESET => IO_RESET,
FEN => FEN,
FCLK => FCLK
);
--===========================================
-- Instantiate the BOOT RAM
--===========================================
BOOTRAM:
RAM port map (
RADDR => ADDR_OUT(12 downto 0),
WADDR => ADDR_OUT(12 downto 0),
DATA_IN => DATA_OX,
DATA_OUT => BOOT_DATA,
BYTEOP => BYTEOP,
REN => BOOT_RE,
WEN => BOOT_WE,
WCLK => FCLK,
RCLK => FCLK
);
--=========================================
-- Instantiate the Reset Sync
--=========================================
SDRESET:
XRESET port map (
RST_OUT1 => RESET1, -- short reset
RST_OUT2 => RESET, -- long reset
RST_IN => SYSRESET,
CLK => FCLK
);
end BEHAVIORAL;
| gpl-3.0 | 1bd092064529d987e789d8dcae5a498d | 0.400212 | 4.303773 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part4/bcd_adder.vhd | 1 | 1,285 | library ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd_adder IS
PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END bcd_adder;
ARCHITECTURE Behavior OF bcd_adder IS
SIGNAL cin: STD_LOGIC;
SIGNAL co1, co2, co3, co4, co5, co6: STD_LOGIC;
SIGNAL s0, s1, s2, s3, s4, s5, s6: STD_LOGIC;
SIGNAL a1, a2: STD_LOGIC;
SIGNAL cout: STD_LOGIC;
SIGNAL hold_low: STD_LOGIC;
COMPONENT adder
PORT (b : IN STD_LOGIC;
a : IN STD_LOGIC;
ci : IN STD_LOGIC;
co : OUT STD_LOGIC;
s : OUT STD_LOGIC) ; END COMPONENT;
BEGIN
FA3: adder PORT MAP (b=> b_in(3), a=> a_in(3), ci=>co3, co=>co4, s=>s3);
FA2: adder PORT MAP (b=> b_in(2), a=> a_in(2), ci=>co2, co=>co3, s=>s2);
FA1: adder PORT MAP (b=> b_in(1), a=> a_in(1), ci=>co1, co=>co2, s=>s1);
FA0: adder PORT MAP (b=> b_in(0), a=> a_in(0), ci=>cin, co=>co1, s=>s0);
hold_low <= '0';
cout <= co4 or a1 or a2;
s6 <= co6 xor s3;
a1 <= s3 and s2;
a2 <= s3 and s1;
FA5: adder PORT MAP (b=> s2, a=> cout, ci=>co5, co=>co6, s=>s5);
FA4: adder PORT MAP (b=> s1, a=> cout, ci=>hold_low, co=>co5, s=>s4);
s_out(0) <= s0;
s_out(1) <= s4;
s_out(2) <= s5;
s_out(3) <= s6;
c_out <= cout;
END Behavior; | unlicense | 2be6e5e4be2ee99aaf83fb32bb2e6b20 | 0.592218 | 2.166948 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/PhaseSel.vhd | 2 | 3,193 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PhaseSel is
port (IN_Xor : in std_logic_vector(5 downto 0) ;
OUT_sel : out std_logic_vector(1 downto 0) );
end PhaseSel;
architecture Behaviorial of PhaseSel is
begin
-- 1 => bar
OUT_sel <= "01" when IN_Xor ="000000" else
"01" when IN_Xor ="000001" else
"01" when IN_Xor ="000010" else
"01" when IN_Xor ="000011" else
"01" when IN_Xor ="000100" else
"01" when IN_Xor ="000101" else
"01" when IN_Xor ="000110" else
"01" when IN_Xor ="000111" else
"01" when IN_Xor ="001000" else
"01" when IN_Xor ="001001" else
"01" when IN_Xor ="001010" else
"01" when IN_Xor ="001011" else
"01" when IN_Xor ="001100" else
"01" when IN_Xor ="001101" else
"01" when IN_Xor ="001110" else
"01" when IN_Xor ="001111" else
"01" when IN_Xor ="010000" else
"01" when IN_Xor ="010001" else
"01" when IN_Xor ="010010" else
"01" when IN_Xor ="010011" else
"01" when IN_Xor ="010100" else
"01" when IN_Xor ="010101" else
"01" when IN_Xor ="010110" else
"01" when IN_Xor ="010111" else
"01" when IN_Xor ="011000" else
"01" when IN_Xor ="011001" else
"01" when IN_Xor ="011010" else
"01" when IN_Xor ="011011" else
"01" when IN_Xor ="011100" else
"01" when IN_Xor ="011101" else
"01" when IN_Xor ="011110" else
"01" when IN_Xor ="011111" else
"01" when IN_Xor ="100000" else
"10" when IN_Xor ="100001" else --
"01" when IN_Xor ="100010" else
"00" when IN_Xor ="100011" else
"01" when IN_Xor ="100100" else
"01" when IN_Xor ="100101" else
"01" when IN_Xor ="100110" else
"01" when IN_Xor ="100111" else
"01" when IN_Xor ="101000" else
"01" when IN_Xor ="101001" else
"01" when IN_Xor ="101010" else
"01" when IN_Xor ="101011" else
"01" when IN_Xor ="101100" else
"01" when IN_Xor ="101101" else
"01" when IN_Xor ="101110" else
"01" when IN_Xor ="101111" else
"10" when IN_Xor ="110000" else
"00" when IN_Xor ="110001" else --
"01" when IN_Xor ="110010" else
"01" when IN_Xor ="110011" else
"01" when IN_Xor ="110100" else
"01" when IN_Xor ="110101" else
"01" when IN_Xor ="110110" else
"01" when IN_Xor ="110111" else
"01" when IN_Xor ="111000" else
"01" when IN_Xor ="111001" else
"01" when IN_Xor ="111010" else
"01" when IN_Xor ="111011" else
"01" when IN_Xor ="111100" else
"01" when IN_Xor ="111101" else
"01" when IN_Xor ="111110" else
"01" when IN_Xor ="111111" ;
end Behaviorial;
| unlicense | 41b04539a7edec36ee2936b767221020 | 0.48575 | 3.624291 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_dff4m.vhd | 2 | 3,907 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff4m.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_dff4m IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gl_dff4m;
ARCHITECTURE SYN OF gl_dff4m IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 4
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | c8b462fafc8fdb8ff851188cf04baa0e | 0.637318 | 3.594296 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part6/DE1_disp.vhd | 4 | 843 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DE1_disp IS
PORT ( HEX0, HEX1, HEX2, HEX3: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END DE1_disp;
ARCHITECTURE Behavior OF DE1_disp IS
COMPONENT sweep
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(2 downto 0));
END COMPONENT;
SIGNAL M : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN -- Behavior
S0: sweep PORT MAP (clk,M);
HEX <= HEX0 WHEN M = "000" ELSE
HEX1 WHEN M = "010" ELSE
HEX2 WHEN M = "100" ELSE
HEX3 WHEN M = "110" ELSE
"1111111";
DISPn <= "1110" WHEN M = "000" ELSE
"1101" WHEN M = "010" ELSE
"1011" WHEN M = "100" ELSE
"0111" WHEN M = "110" ELSE
"1111";
END Behavior; | unlicense | df810aebdd00d6bd292f3b4afe38c6cf | 0.591934 | 3.076642 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_counter1.vhd | 2 | 4,880 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter1 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_counter1;
ARCHITECTURE SYN OF lpm_counter1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(3 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_hint => "CBX_MODULE_PREFIX=lpm_counter1",
lpm_modulus => 10,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 4
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "10"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
-- Retrieval info: CBX_MODULE_PREFIX: ON
| unlicense | f3250022280e730138b27f4a61360784 | 0.655328 | 3.601476 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part6/part6_code.vhd | 1 | 1,675 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part6_code IS
PORT(
BUTTONS : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clk_in : IN STD_LOGIC
);
END part6_code;
ARCHITECTURE Behaviour of part6_code IS
SIGNAL HEX_0, HEX_1, LED_1, LED_2, LED_3, LED_4: STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL SW_1, SW_2, SW_3, SW_4: STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT;
COMPONENT bin2bcd_12bit Port ( binIN : in STD_LOGIC_VECTOR (11 downto 0);
ones : out STD_LOGIC_VECTOR (3 downto 0);
tens : out STD_LOGIC_VECTOR (3 downto 0);
hundreds : out STD_LOGIC_VECTOR (3 downto 0);
thousands : out STD_LOGIC_VECTOR (3 downto 0)
); END COMPONENT;
BEGIN
seg1 : segseven PORT MAP (SW=>SW_1, LEDSEG=>LED_1);
seg2 : segseven PORT MAP (SW=>SW_2, LEDSEG=>LED_2);
seg3 : segseven PORT MAP (SW=>SW_3, LEDSEG=>LED_3);
seg4 : segseven PORT MAP (SW=>SW_4, LEDSEG=>LED_4);
convert: bin2bcd_12bit PORT MAP (binIN=> BUTTONS, ones => SW_1, tens =>SW_2, hundreds => SW_3, thousands => SW_4);
DE1: DE1_disp PORT MAP (HEX0=>LED_1, HEX1=>LED_2, HEX2=>LED_3, HEX3=>LED_4, clk=>clk_in, HEX=>LED, DISPn=>DISP);
END Behaviour; | unlicense | 56aa809cc9f9ce8110ad35ba332db99a | 0.609552 | 2.98574 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ROC_H_FSM.vhd | 2 | 2,237 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ROC_H_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
ROC_start_i : in std_logic;
serdat_i : in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end ROC_H_FSM;
architecture rtl of ROC_H_FSM is
type t_state is (waiting,
tick_RB3,
tick_RB2,
tick_RB1,
tick_RB0);
signal s_state : t_state;
--signal s_count : unsigned(3 downto 0);
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_RB3 =>
wen_o <= '0';
payload_o(3)<=serdat_i;
s_state <= tick_RB2;
-------------------------------------------------------------------------
when tick_RB2 =>
payload_o(2)<=serdat_i;
s_state <= tick_RB1;
-------------------------------------------------------------------------
when tick_RB1 =>
payload_o(1)<=serdat_i;
s_state <= tick_RB0;
-------------------------------------------------------------------------
when tick_RB0 =>
payload_o(0)<=serdat_i;
type_o <= "0111";
wen_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if ROC_start_i = '1' then
wen_o <= '0';
payload_o <= "0000";
s_state <= tick_RB3;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
| unlicense | 1622a81046c1845b936cc01549e4ef4a | 0.362539 | 4.082117 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/TBM_T_FSMold.vhd | 2 | 3,966 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TBM_T_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
TBM_T_start_i : in std_logic;
serdat_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end TBM_T_FSM;
architecture rtl of TBM_T_FSM is
type t_state is (waiting,
tick_X1,
tick_EW7,
tick_EW6,
tick_X2,
tick_EW5,
tick_EW4,
tick_EW3,
tick_EW2,
tick_X3,
tick_EW1,
tick_EW0,
tick_X4);
signal s_state : t_state;
signal s_payload : std_logic_vector(7 downto 0);--unsigned(3 downto 0);
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_X1 =>
wen_o <= '0';
s_state <= tick_EW7;
-------------------------------------------------------------------------
when tick_EW7 =>
s_payload(7)<=serdat_i;
s_state <= tick_EW6 ;
-------------------------------------------------------------------------
when tick_EW6 =>
s_payload(6)<=serdat_i;
s_state <= tick_X2 ;
-------------------------------------------------------------------------
when tick_X2 =>
s_state <= tick_EW5 ;
-------------------------------------------------------------------------
when tick_EW5 =>
s_payload(5)<=serdat_i;
s_state <= tick_EW4 ;
-------------------------------------------------------------------------
when tick_EW4 =>
s_payload(4)<=serdat_i;
s_state <= tick_EW3 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_EW3 =>
s_payload(3)<=serdat_i;
s_state <= tick_EW2 ;
-------------------------------------------------------------------------
when tick_EW2 =>
s_payload(2)<=serdat_i;
payload_o(3)<=s_payload(7);
payload_o(2)<=s_payload(6);
payload_o(1)<=s_payload(5);
payload_o(0)<=s_payload(4);
wen_o <= '1';
type_o <= "1011";
s_state <= tick_X3 ;
-------------------------------------------------------------------------
when tick_X3 =>
wen_o <= '0';
s_state <= tick_EW1 ;
-------------------------------------------------------------------------
when tick_EW1 =>
s_payload(1)<=serdat_i;
s_state <= tick_EW0 ;
-------------------------------------------------------------------------
when tick_EW0 =>
s_payload(0)<=serdat_i;
s_state <= tick_X4 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_X4 =>
payload_o(3)<=s_payload(3);
payload_o(2)<=s_payload(2);
payload_o(1)<=s_payload(1);
payload_o(0)<=s_payload(0);
wen_o <= '1';
type_o <= "1100";
s_state <= waiting ;
-------------------------------------------------------------------------
when others =>
if TBM_T_start_i = '1' then
wen_o <= '0';
s_state <= tick_X1;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
| unlicense | c5159d533c680c9c7d03599dd376cb54 | 0.32476 | 4.306189 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/TBM_T_FSM.vhd | 2 | 4,519 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TBM_T_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
TBM_T_start_i : in std_logic;
serdat_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end TBM_T_FSM;
architecture rtl of TBM_T_FSM is
type t_state is (waiting,
tick_NTP,
tick_RTB,
tick_RER,
tick_SER,
tick_STR,
tick_CTC,
tick_CAL,
tick_STF,
tick_DI1,
tick_DI0,
tick_D5,
tick_D4,
tick_D3,
tick_D2,
tick_D1,
tick_D0);
signal s_state : t_state;
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_NTP =>
wen_o <= '0';
payload_o(3)<=serdat_i;
s_state <= tick_RTB;
-------------------------------------------------------------------------
when tick_RTB =>
payload_o(2)<=serdat_i;
s_state <= tick_RER ;
-------------------------------------------------------------------------
when tick_RER =>
payload_o(1)<=serdat_i;
s_state <= tick_SER ;
-------------------------------------------------------------------------
when tick_SER =>
payload_o(0)<=serdat_i;
type_o <= "1100";
wen_o <= '1';
s_state <= tick_STR ;
-------------------------------------------------------------------------
when tick_STR =>
payload_o(3)<=serdat_i;
wen_o <= '0';
s_state <= tick_CTC ;
-------------------------------------------------------------------------
when tick_CTC =>
payload_o(2)<=serdat_i;
s_state <= tick_CAL ;
-------------------------------------------------------------------------
when tick_CAL =>
payload_o(1)<=serdat_i;
s_state <= tick_STF ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_STF =>
payload_o(0)<=serdat_i;
type_o <= "1101";
wen_o <= '1';
s_state <= tick_DI1 ;
-------------------------------------------------------------------------
when tick_DI1 =>
payload_o(3)<=serdat_i;
wen_o <= '0';
s_state <= tick_DI0 ;
-------------------------------------------------------------------------
when tick_DI0 =>
payload_o(2)<=serdat_i;
s_state <= tick_D5 ;
-------------------------------------------------------------------------
when tick_D5 =>
payload_o(1)<=serdat_i;
s_state <= tick_D4 ;
-------------------------------------------------------------------------
when tick_D4 =>
payload_o(0)<=serdat_i;
type_o <= "1110";
wen_o <= '1';
s_state <= tick_D3 ;
-------------------------------------------------------------------------
when tick_D3 =>
payload_o(3)<=serdat_i;
wen_o <= '0';
s_state <= tick_D2 ;
-------------------------------------------------------------------------
when tick_D2 =>
payload_o(2)<=serdat_i;
s_state <= tick_D1 ;
-------------------------------------------------------------------------
when tick_D1 =>
payload_o(1)<=serdat_i;
s_state <= tick_D0 ;
-------------------------------------------------------------------------
when tick_D0 =>
payload_o(0)<=serdat_i;
type_o <= "1111";
wen_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
when others =>
if TBM_T_start_i = '1' then
wen_o <= '0';
s_state <= tick_NTP;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
| unlicense | 65c0c88fc57e8afe8271dcdf0cfd4719 | 0.304492 | 4.492048 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part6/lpm_constant1.vhd | 1 | 3,515 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant1 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_constant1;
ARCHITECTURE SYN OF lpm_constant1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(3 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 4,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE",
lpm_type => "LPM_CONSTANT",
lpm_width => 4
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "4"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 66c39aa6d3c50fa01350d2adcbb3aa2a | 0.646942 | 3.820652 | false | false | false | false |
notti/dis_lu | test/tb_debounce.vhd | 1 | 1,707 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_debounce is
end tb_debounce;
architecture behav of tb_debounce is
signal clk : std_logic := '0';
signal io_i : std_logic := '0';
signal io_o : std_logic := '0';
signal noise : std_logic := '0';
signal fixed : std_logic := '0';
signal toggling : std_logic := '0';
signal riseedge : std_logic := '0';
signal falledge: std_logic := '0';
begin
process
begin
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
VARIABLE seed1: positive := 1;
VARIABLE seed2: positive := 1;
VARIABLE rand: real;
VARIABLE t_rand: time;
begin
noise <= not noise;
UNIFORM(seed1, seed2, rand);
t_rand := (rand*100.0)*1 ns;
wait for t_rand;
end process;
process
begin
wait for 1400 ns;
toggling <= '1';
wait for 600 ns;
toggling <= '0';
fixed <= '1';
wait for 2000 ns;
toggling <= '1';
fixed <= '0';
wait for 1000 ns;
toggling <= '0';
wait for 3000 ns;
assert false report "done" severity failure;
wait;
end process;
io_i <= noise when toggling = '1' else
fixed;
debounce : entity work.debounce
generic map(
CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns
)
port map(
clk => clk,
input => io_i,
output => io_o,
riseedge => riseedge,
falledge => falledge
);
end behav;
| mit | a294f74163de3fcc8031d64b5ba7d711 | 0.525483 | 3.751648 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_decode0.vhd | 1 | 5,934 | -- megafunction wizard: %LPM_DECODE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_DECODE
-- ============================================================
-- File Name: lpm_decode0.vhd
-- Megafunction Name(s):
-- LPM_DECODE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_decode0 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
eq0 : OUT STD_LOGIC ;
eq1 : OUT STD_LOGIC ;
eq2 : OUT STD_LOGIC ;
eq3 : OUT STD_LOGIC ;
eq4 : OUT STD_LOGIC ;
eq5 : OUT STD_LOGIC ;
eq6 : OUT STD_LOGIC ;
eq7 : OUT STD_LOGIC
);
END lpm_decode0;
ARCHITECTURE SYN OF lpm_decode0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
COMPONENT lpm_decode
GENERIC (
lpm_decodes : NATURAL;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
eq : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire8 <= sub_wire0(4);
sub_wire7 <= sub_wire0(0);
sub_wire6 <= sub_wire0(7);
sub_wire5 <= sub_wire0(5);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(1);
sub_wire2 <= sub_wire0(6);
sub_wire1 <= sub_wire0(2);
eq2 <= sub_wire1;
eq6 <= sub_wire2;
eq1 <= sub_wire3;
eq3 <= sub_wire4;
eq5 <= sub_wire5;
eq7 <= sub_wire6;
eq0 <= sub_wire7;
eq4 <= sub_wire8;
LPM_DECODE_component : LPM_DECODE
GENERIC MAP (
lpm_decodes => 8,
lpm_pipeline => 1,
lpm_type => "LPM_DECODE",
lpm_width => 3
)
PORT MAP (
clock => clock,
data => data,
eq => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BaseDec NUMERIC "1"
-- Retrieval info: PRIVATE: EnableInput NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: eq0 NUMERIC "1"
-- Retrieval info: PRIVATE: eq1 NUMERIC "1"
-- Retrieval info: PRIVATE: eq2 NUMERIC "1"
-- Retrieval info: PRIVATE: eq3 NUMERIC "1"
-- Retrieval info: PRIVATE: eq4 NUMERIC "1"
-- Retrieval info: PRIVATE: eq5 NUMERIC "1"
-- Retrieval info: PRIVATE: eq6 NUMERIC "1"
-- Retrieval info: PRIVATE: eq7 NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DECODES NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DECODE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: @eq 0 0 8 0 OUTPUT NODEFVAL "@eq[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL "data[2..0]"
-- Retrieval info: USED_PORT: eq0 0 0 0 0 OUTPUT NODEFVAL "eq0"
-- Retrieval info: USED_PORT: eq1 0 0 0 0 OUTPUT NODEFVAL "eq1"
-- Retrieval info: USED_PORT: eq2 0 0 0 0 OUTPUT NODEFVAL "eq2"
-- Retrieval info: USED_PORT: eq3 0 0 0 0 OUTPUT NODEFVAL "eq3"
-- Retrieval info: USED_PORT: eq4 0 0 0 0 OUTPUT NODEFVAL "eq4"
-- Retrieval info: USED_PORT: eq5 0 0 0 0 OUTPUT NODEFVAL "eq5"
-- Retrieval info: USED_PORT: eq6 0 0 0 0 OUTPUT NODEFVAL "eq6"
-- Retrieval info: USED_PORT: eq7 0 0 0 0 OUTPUT NODEFVAL "eq7"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: eq0 0 0 0 0 @eq 0 0 1 0
-- Retrieval info: CONNECT: eq1 0 0 0 0 @eq 0 0 1 1
-- Retrieval info: CONNECT: eq2 0 0 0 0 @eq 0 0 1 2
-- Retrieval info: CONNECT: eq3 0 0 0 0 @eq 0 0 1 3
-- Retrieval info: CONNECT: eq4 0 0 0 0 @eq 0 0 1 4
-- Retrieval info: CONNECT: eq5 0 0 0 0 @eq 0 0 1 5
-- Retrieval info: CONNECT: eq6 0 0 0 0 @eq 0 0 1 6
-- Retrieval info: CONNECT: eq7 0 0 0 0 @eq 0 0 1 7
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 07e3115ad147446225d88ddfda4b0b72 | 0.641557 | 3.214518 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part6/lpm_constant0.vhd | 1 | 3,513 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(5 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=BIN",
lpm_type => "LPM_CONSTANT",
lpm_width => 6
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "BIN"
-- Retrieval info: PRIVATE: Radix NUMERIC "16"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=BIN"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: result 0 0 6 0 OUTPUT NODEFVAL "result[5..0]"
-- Retrieval info: CONNECT: result 0 0 6 0 @result 0 0 6 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 2be6ed45d3720c964571aea7eaf7ae78 | 0.646741 | 3.818478 | false | false | false | false |
amethystek/VHDL_SPACE_INVADER | player.vhd | 1 | 1,580 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity player is
port(MOVE_CLK:in std_logic;
HCount :in std_logic_vector(10 downto 0);
VCount :in std_logic_vector(10 downto 0);
PLAYER_BUTTON_A:in std_logic;
PLAYER_BUTTON_B:in std_logic;
PLAYER_H :out std_logic_vector(10 downto 0);--send to missile
VGA_PLAYER_EN :out std_logic);--whether show on screen
end player;
architecture behave of player is
signal POS_H :std_logic_vector(10 downto 0):="00110010000";--to make it at the middlie of screen
signal MOV_DIR :std_logic_vector(1 downto 0):="00";
signal MOV_DIR_COUNT:std_logic_vector(2 downto 0):="000";
begin
PLAYER_H<=POS_H;
MOV_DIR<=PLAYER_BUTTON_A&PLAYER_BUTTON_B;
-------------------------------------------------------------------
process(MOVE_CLK)
begin
if(MOV_DIR_COUNT/="111")then
MOV_DIR_COUNT<=MOV_DIR_COUNT+1;
else
MOV_DIR_COUNT<="010";
if(MOV_DIR="01")then
if(POS_H>33)then
POS_H<=POS_H-16;
end if;
elsif(MOV_DIR="10")then
if(POS_H<730)then
POS_H<=POS_H+16;
end if;
end if;
end if;
end process;
---------------------------------------------------------
PLAYER_SHOW:process(HCount,VCount)
begin
vga_player_en<='0';
if(VCount>549 and VCount<559)then
if(HCount>(POS_H+8-1) and Hcount<(POS_H+16+1))then
vga_player_en<='1';
end if;
elsif(VCount>558 and VCount<563)then
if(HCount>(POS_H-1) and HCount<(POS_H+24+1))then
vga_player_en<='1';
end if;
end if;
end process PLAYER_SHOW;
end behave; | bsd-2-clause | 9ba09003e2475bb77b209dae5cfc105a | 0.614557 | 3.015267 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/altera/openmac/src/openMAC_DMAFifo.vhd | 3 | 7,255 | -------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity openMAC_DMAfifo is
generic (
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port
(
aclr : in std_logic;
rd_clk : in std_logic;
wr_clk : in std_logic;
--read port
rd_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
--write port
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end openMAC_DMAfifo;
architecture struct of openMAC_DMAfifo is
component dcfifo
generic (
lpm_width : natural; --width of data and q ports (input/output)
lpm_widthu : natural; --width of wrusedw and rdusedw
lpm_numwords : natural; --depth of fifo
lpm_showahead : string; --fifo showahead off/on (rdreq works as req/ack)
lpm_type : string; --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking : string; --protection circuit for wrreq
underflow_checking : string; --protection circuit for rdreq
rdsync_delaypipe : natural; --number of sync from wr to rd
wrsync_delaypipe : natural; --number of sync from rd to wr
use_eab : string; --construct fifo as LE/RAM (off/on)
write_aclr_synch : string; --sync async. clear to wr clk (avoids race cond.)
intended_device_family : string --specifies the intended device for functional simulation
);
port (
wrclk : in std_logic; --clock for wr port
rdclk : in std_logic; --clock for rd port
data : in std_logic_vector(fifo_data_width_g-1 downto 0); --data to be written
wrreq : in std_logic; --write request
rdreq : in std_logic; --read request
aclr : in std_logic; --asynchronous clear fifo
q : out std_logic_vector(fifo_data_width_g-1 downto 0); --read data
wrfull : out std_logic; --fifo is full on wr port
rdfull : out std_logic; --fifo is full on rd port
wrempty : out std_logic; --fifo is empty on wr port
rdempty : out std_logic; --fifo is empty on rd port
wrusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --number of words stored on wr port
rdusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) --number of words stored on rd port
);
end component;
constant fifo_useRam_c : string := "ON";
constant fifo_words_c : natural := fifo_word_size_g; --e.g. 32
constant fifo_usedw_c : natural := fifo_word_size_log2_g; --e.g. log2(32) = 5
--constant fifo_rd_usedw_c : natural := 5;
--constant fifo_wr_usedw_c : natural := 5;
constant fifo_data_width_c : natural := fifo_data_width_g;
--constant fifo_rd_data_width_c : natural := 16;
--constant fifo_wr_data_width_c : natural := 16;
begin
dcfifo_inst : dcfifo
generic map (
lpm_width => fifo_data_width_c, --width of data and q ports (input/output)
lpm_widthu => fifo_usedw_c, --width of wrusedw and rdusedw
lpm_numwords => fifo_words_c, --depth of fifo
lpm_showahead => "OFF", --fifo showahead off/on (rdreq works as req/ack)
lpm_type => "DCFIFO", --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking => "ON", --protection circuit for wrreq
underflow_checking => "ON", --protection circuit for rdreq
rdsync_delaypipe => 4, --number of sync from wr to rd
wrsync_delaypipe => 4, --number of sync from rd to wr
use_eab => fifo_useRam_c, --construct fifo as LE/RAM (off/on)
write_aclr_synch => "ON", --sync async. clear to wr clk (avoids race cond.)
intended_device_family => "Cyclone IV" --specifies the intended device for functional simulation
)
port map (
wrclk => wr_clk, --clock for wr port
rdclk => rd_clk, --clock for rd port
data => wr_data, --data to be written
wrreq => wr_req, --write request
rdreq => rd_req, --read request
aclr => aclr, --asynchronous clear fifo
q => rd_data, --read data
wrfull => wr_full, --fifo is full on wr port
rdfull => rd_full, --fifo is full on rd port
wrempty => wr_empty, --fifo is empty on wr port
rdempty => rd_empty, --fifo is empty on rd port
wrusedw => wr_usedw, --number of words stored on wr port
rdusedw => rd_usedw --number of words stored on rd port
);
end struct;
| gpl-2.0 | c7d5430e6aae180a846d41f46a7d33d3 | 0.579187 | 4.124503 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part4/lpm_constant2.vhd | 1 | 3,515 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I1",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I1"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 4322792d4fdfd3a175e125e5b331ac46 | 0.646657 | 3.804113 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | bmax10/Bemicro_m10_embedded_lab_14_0/bemicro_m10_embedded_lab_14_0/bemicro_m10_nios2_top.vhd | 1 | 9,399 | -- top.vhd
-- this VHDL design instatiates a Qsys system with a Nios II processor that has access to the many diffent peripherals
-- on the BeMicro Max 10 board.
--
-- There are many different software examples included in the software folder.
library ieee;
use ieee.std_logic_1164.all;
-- The following is the entity declaration section of this VHDL block.
-- An entity declaraction defines the pins of the block and is analogous to
-- a schematic symbol.
--
-- Since the bemicro_m10_nios2_top entity is the top level entity of our FPGA design,
-- the ports listed below are the pins of our MAX 10 FPGA device.
--
entity bemicro_m10_nios2_top is
port
(
SYS_CLK : in std_logic := 'X'; -- clk
USER_CLK : in std_logic;
PB : in std_logic_vector(4 downto 1) := (others => 'X'); -- export
USER_LED : out std_logic_vector(8 downto 1); -- export
SDRAM_A : out std_logic_vector(12 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_CASN : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSN : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQM : out std_logic_vector(1 downto 0);
SDRAM_RASN : out std_logic;
SDRAM_WEN : out std_logic;
SDRAM_CLK : out std_logic;
ADXL362_MISO : in std_logic;
ADXL362_MOSI : out std_logic;
ADXL362_SCLK : out std_logic;
ADXL362_CSn : out std_logic;
ADXL362_INT1 : in std_logic;
ADXL362_INT2 : in std_logic;
ADT7420_SCL : inout std_logic;
ADT7420_SDA : inout std_logic;
SFLASH_DCLK : out std_logic;
SFLASH_CSn : out std_logic;
SFLASH_DATA : in std_logic; -- input data from spi flash
SFLASH_ASDI : out std_logic; -- this feeds out to the data input of the spi flash
AD5681R_LDACn : out std_logic;
AD5681R_RSTn : out std_logic;
AD5681R_SCL : out std_logic;
AD5681R_SDA : out std_logic;
AD5681R_SYNCn : out std_logic
);
end entity;
-- The following is the architecture section of the bemicro_m10_nios2_top entity declared
-- above. The architecture section is the actual design of the VHDL block and is analogous
-- to the contents of a schematic sheet.
--
-- The architecture of bemicro_m10_nios2_top contains primarily one large block, which is
-- the nios2_bemicro_system block generated by QSys. This ports of this block are mapped
-- to the pins of the device. There is a small amount of additional logic to tie off others
-- signals and to generate resets.
--
architecture rtl of bemicro_m10_nios2_top is
-- VHDL component declaration for the QSys sytem. This is copy/pasted from the generated
-- file nios2_bemicro_system/nios2_bemicro_system_inst.vhd
component nios2_bemicro_system is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
led_pio_external_export : out std_logic_vector(7 downto 0); -- export
button_pio_external_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
i2c_temp_sense_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
i2c_temp_sense_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
sdram_addr : out std_logic_vector(11 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
serial_flash_dclk : out std_logic; -- dclk
serial_flash_sce : out std_logic; -- sce
serial_flash_sdo : out std_logic; -- sdo
serial_flash_data0 : in std_logic := 'X'; -- data0
sdram_pll_areset_conduit_export : in std_logic := 'X'; -- export
sdram_pll_locked_conduit_export : out std_logic; -- export
sdram_pll_phasedone_conduit_export : out std_logic; -- export
adc_pll_areset_conduit_export : in std_logic := 'X'; -- export
adc_pll_phasedone_conduit_export : out std_logic; -- export
spi_accelerometer_MISO : in std_logic := 'X'; -- MISO
spi_accelerometer_MOSI : out std_logic; -- MOSI
spi_accelerometer_SCLK : out std_logic; -- SCLK
spi_accelerometer_SS_n : out std_logic; -- SS_n
spi_dac_MISO : in std_logic := 'X'; -- MISO
spi_dac_MOSI : out std_logic; -- MOSI
spi_dac_SCLK : out std_logic; -- SCLK
spi_dac_SS_n : out std_logic; -- SS_n
sdram_pll_80shift_clk : out std_logic -- clk
);
end component nios2_bemicro_system;
signal async_reset_n : std_logic;
signal reset_n : std_logic;
signal pll_areset : std_logic;
signal reset_sync_n : std_logic_vector(1 downto 0);
signal led_export : std_logic_vector(8 downto 1);
begin
-- push_buttons are active low
-- reset the Nios when PB4 and PB1 are pushed simultaneously
async_reset_n <= '0' when PB(4) = '0' and PB(1) = '0' else '1';
--reset synchronizer
-- this logic will asynchronously reset the whole system, yet
-- will synchronously release reset
process(SYS_CLK)
begin
if(async_reset_n = '0') then
reset_sync_n <= "00"; -- clear 2-bit reset sync register
else
if rising_edge(SYS_CLK) then
reset_sync_n(0) <= '1';
reset_sync_n(1) <= reset_sync_n(0);
end if;
end if;
end process;
reset_n <= reset_sync_n(1);
pll_areset <= not reset_sync_n(1);
-- VHDL port mapping of the QSys system's ports to signals in the top level. A port mapping
-- template is found in the generated file nios2_bemicro_system/nios2_bemicro_system_inst.vhd
u0 : component nios2_bemicro_system
port map (
clk_clk => SYS_CLK,
reset_reset_n => reset_n,
button_pio_external_export => PB,
led_pio_external_export => led_export,
i2c_temp_sense_scl_pad_io => ADT7420_SCL,
i2c_temp_sense_sda_pad_io => ADT7420_SDA,
sdram_addr => SDRAM_A(11 downto 0),
sdram_ba => SDRAM_BA,
sdram_cas_n => SDRAM_CASN,
sdram_cke => SDRAM_CKE,
sdram_cs_n => SDRAM_CSN,
sdram_dq => SDRAM_DQ,
sdram_dqm => SDRAM_DQM,
sdram_ras_n => SDRAM_RASN,
sdram_we_n => SDRAM_WEN,
sdram_pll_80shift_clk => SDRAM_CLK,
sdram_pll_areset_conduit_export => pll_areset,
sdram_pll_locked_conduit_export => open,
sdram_pll_phasedone_conduit_export => open,
adc_pll_areset_conduit_export => pll_areset,
adc_pll_phasedone_conduit_export => open,
serial_flash_dclk => SFLASH_DCLK,
serial_flash_sce => SFLASH_CSn,
serial_flash_sdo => SFLASH_ASDI,
serial_flash_data0 => SFLASH_DATA,
spi_accelerometer_MISO => ADXL362_MISO,
spi_accelerometer_MOSI => ADXL362_MOSI,
spi_accelerometer_SCLK => ADXL362_SCLK,
spi_accelerometer_SS_n => ADXL362_CSn,
spi_dac_MISO => '1',
spi_dac_MOSI => AD5681R_SDA,
spi_dac_SCLK => AD5681R_SCL,
spi_dac_SS_n => AD5681R_SYNCn
);
SDRAM_a(12) <= '0'; --extra address bit used for larger SDRAM devices
--the leds are active low, need to invert
USER_LED(8 downto 1) <= not led_export(8 downto 1);
AD5681R_LDACn <= '1'; -- LDAC is used to transfer data from the DAC register to the output generating vout. this can also be done in sw
AD5681R_RSTn <= reset_n;
end rtl;
| unlicense | ddb16db98039d0b45a99b235080d1876 | 0.509097 | 3.576484 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ram_init_inst.vhd | 2 | 205 | ram_init_inst : ram_init PORT MAP (
clock => clock_sig,
init => init_sig,
dataout => dataout_sig,
init_busy => init_busy_sig,
ram_address => ram_address_sig,
ram_wren => ram_wren_sig
);
| unlicense | cd6d90d1c67b334ffac86b298407a19f | 0.609756 | 2.530864 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ip/spi_master/spi_master_if.vhd | 3 | 5,140 | --*****************************************************************************
--* Copyright (C) 2012 by Michael Fischer
--*
--* All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permission.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 26.08.2012 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity spi_master_if is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end entity spi_master_if;
--*****************************************************************************
--* DEFINE: Architecture *
--*****************************************************************************
architecture syn of spi_master_if is
--
-- Define all constants here
--
--
-- Define all components which are included here
--
component spi_master_core is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end component spi_master_core;
--
-- Define all local signals (like static data) here
--
begin
inst_spi : spi_master_core
port map (
clk => clk,
reset => reset,
chipselect => chipselect,
address => address,
write => write,
writedata => writedata,
read => read,
readdata => readdata,
cs => cs,
sclk => sclk,
mosi => mosi,
miso => miso
);
end architecture syn;
-- *** EOF ***
| unlicense | ab845e4b963a767b5bebb1ac53c66117 | 0.447276 | 5.024438 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part3/part3.vhd | 1 | 907 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- simple 3-to-1 multiplexer module
-- based on labs from Altera
-- ftp://ftp.altera.com/up/pub/Altera_Material/11.1/Laboratory_Exercises/Digital_Logic/DE1/vhdl/lab1_VHDL.pdf
ENTITY part3 IS
PORT ( S1: IN STD_LOGIC;
S0: IN STD_LOGIC;
U: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
V: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
W: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
M: OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END part3;
ARCHITECTURE Behavior OF part3 IS
SIGNAL SEL : STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
--SEL(0) <= S0;
--SEL(1) <= S1;
--WITH SEL SELECT
--M <= U WHEN "00",
--V WHEN "01",
--W WHEN "10",
--W WHEN OTHERS;
M(0) <= (S1 AND W(0)) OR ((NOT S1) AND (NOT S0) AND U(0)) OR ((NOT S1) AND S0 AND V(0));
M(1) <= (S1 AND W(1)) OR ((NOT S1) AND (NOT S0) AND U(1)) OR ((NOT S1) AND S0 AND V(1));
END Behavior; | unlicense | 0f8137047ca0300c5c0a51b408b1800d | 0.598677 | 2.659824 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ram_dq_PHASE_k.vhd | 2 | 7,072 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_k.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_k IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_k;
ARCHITECTURE SYN OF ram_dq_phase_k IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_K",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_K"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_K"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_k.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_k.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_k.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_k.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_k_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | f2c020b338bcd5281b8a3a78bb817415 | 0.671946 | 3.438017 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part3/lpm_constant2.vhd | 1 | 3,509 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I2",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I2"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 225e2ec0d003ed7b616f976af5697488 | 0.646338 | 3.801733 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/decode_5b4b.vhd | 2 | 1,206 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity DECODE_5b4b is
port (IN_5b_i : in std_logic_vector(4 downto 0) ;
clk: in std_logic;
OUT_4b_o : out std_logic_vector(3 downto 0) );
end DECODE_5b4b;
architecture Behaviorial of DECODE_5b4b is
signal q_4b: std_logic_vector(3 downto 0);
begin
q_4b <= "0000" when IN_5b_i ="11110" else
"0001" when IN_5b_i ="01001" else
"0010" when IN_5b_i ="10100" else
"0011" when IN_5b_i ="10101" else
"0100" when IN_5b_i ="01010" else
"0101" when IN_5b_i ="01011" else
"0110" when IN_5b_i ="01110" else
"0111" when IN_5b_i ="01111" else
"1000" when IN_5b_i ="10010" else
"1001" when IN_5b_i ="10011" else
"1010" when IN_5b_i ="10110" else
"1011" when IN_5b_i ="10111" else
"1100" when IN_5b_i ="11010" else
"1101" when IN_5b_i ="11011" else
"1110" when IN_5b_i ="11100" else
"1111" when IN_5b_i ="11101" else
"0000";
process (clk)
begin
if (rising_edge(clk)) then
OUT_4b_o<=q_4b;
end if;
end process;
end Behaviorial;
| unlicense | 818cf9e6239258cc19acfacb79231218 | 0.553897 | 2.644737 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ip/delay_out/prbs31x3.vhd | 3 | 2,639 | -- pseudo random bit sequence with 31-bit register
-- CLK: max speed given by 2 random bits each clock cycle
-- RESET: reset the internal register all to 1
-- SPEED: the speed of the output
-- "11" output each clock cycle two random bits on Y
-- "10" output each clock cycle the same random bit on Y
-- "01" output every second clock cycle the same random bit on Y
-- "00" output every fourth clock cycle the same random bit on Y
-------------------------------------------------------------------
entity PRBS31 is
port (CLK: in bit;
RESET: in bit;
EN: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit_vector(1 downto 0));
end PRBS31;
entity DIVIDER_FSM is
port (CLK: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit);
end DIVIDER_FSM;
architecture PRBS31_ARCH of PRBS31 is
signal CIN: bit; -- Internal FF enable signal for Shift register
component DIVIDER_FSM is port(CLK: in bit; SPEED: in bit_vector(1 downto 0); Y: out bit); end component;
begin
-- CLOCK DIVIDER FSM
I0: DIVIDER_FSM port map(CLK,SPEED,CIN);
process(CLK,RESET)
variable REG: bit_vector(30 downto 0) := (others => '1');
begin
if RESET='1' then
REG := (others => '1');
elsif CLK'event and CLK='1' then
if EN='0' then
REG := (others => '1');
elsif CIN='1' then
if SPEED="11" then
REG := REG(28 downto 0) & (REG(30) xor REG(27)) & (REG(29) xor REG(26));
else
REG := REG(29 downto 0) & (REG(30) xor REG(27));
end if;
end if;
end if;
case SPEED is
when "11" => Y <= REG(30 downto 29);
when others => Y <= REG(30) & REG(30);
end case;
end process;
end PRBS31_ARCH;
architecture DIVIDER_FSM_ARCH of DIVIDER_FSM is
begin
FSM: process(CLK)
variable STATE: bit_vector(1 downto 0) := (others => '0');
variable DECISION: bit_vector(3 downto 0);
begin
-- change state
if CLK'event and CLK='1' then
DECISION := STATE & SPEED;
case DECISION is
when "1100" => STATE := "00";
when "0000" | "1101" => STATE := "01";
when "0001" | "0100" => STATE := "10";
when others => STATE := "11";
end case;
end if;
-- output depending on state
case STATE is
when "11" => Y <= '1';
when others => Y <= '0';
end case;
end process FSM;
end DIVIDER_FSM_ARCH;
| unlicense | f418b9baf6f5cf47766a7de386aabde5 | 0.523683 | 3.921248 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/altera/pdi/src/pdi_dpr.vhd | 3 | 6,559 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 | 0954e525b98a8d15e70d1e4aaf29ea3c | 0.540631 | 3.874188 | false | false | false | false |
Alix82/mip32vhdl | constants.vhd | 1 | 2,694 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mips_constants is
constant ZERO : std_logic_vector(31 downto 0):=
"00000000000000000000000000000000";
constant LINK_RET : integer := 1;
constant REG_DEST : integer := 11;
constant REG2OPERATION : integer := 2;
constant ALUSRC : integer := 4;
constant MEM_TO_REG : integer := 7;
constant MEM_READ : integer := 8;
constant MEM_WRITE : integer := 5;
constant REG_WRITE : integer := 3;
constant BRANCH_BIT : integer := 9;
constant JUMP_BIT : integer := 10;
constant JUMPTOREG_BIT : integer := 0;
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
end mips_constants;
package body mips_constants is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
end;
| bsd-2-clause | d6467517ee1511bdf2a6988b3d13fcc7 | 0.62435 | 3.359102 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_compare2.vhd | 2 | 4,515 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare2.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare2 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
AeB : OUT STD_LOGIC
);
END lpm_compare2;
ARCHITECTURE SYN OF lpm_compare2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
AeB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire1_bv(3 DOWNTO 0) <= "0101";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
AeB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 4
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
AeB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "5"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: AeB 0 0 0 0 OUTPUT NODEFVAL AeB
-- Retrieval info: USED_PORT: dataa 0 0 4 0 INPUT NODEFVAL dataa[3..0]
-- Retrieval info: CONNECT: AeB 0 0 0 0 @AeB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 4 0 dataa 0 0 4 0
-- Retrieval info: CONNECT: @datab 0 0 4 0 5 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | cd105f376bbc8ecf33414830257bffda | 0.657586 | 3.682708 | false | false | false | false |
scottlbaker/PDP11-SOC | src/pdp11.vhd | 1 | 91,640 |
--======================================================================
-- pdp11.vhd :: PDP-11 instruction-set compatible microprocessor
--======================================================================
--
-- The PDP-11 series was an extremely successful and influential
-- family of machines designed at Digital Equipment Corporation (DEC)
-- The first PDP-11 (/20) was designed in the early 1970's and the
-- PDP-11 family prospered for over two decades through the mid 1990s.
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_types.all;
entity IP_PDP11 is
port (
ADDR_OUT : out std_logic_vector(15 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
R_W : out std_logic; -- 1==read 0==write
BYTE : out std_logic; -- Byte memory operation
SYNC : out std_logic; -- Opcode fetch status
IRQ0 : in std_logic; -- Interrupt (active-low)
IRQ1 : in std_logic; -- Interrupt (active-low)
IRQ2 : in std_logic; -- Interrupt (active-low)
IRQ3 : in std_logic; -- Interrupt (active-low)
RDY : in std_logic; -- Ready input
RESET : in std_logic; -- Reset input (active-low)
FEN : in std_logic; -- clock enable
CLK : in std_logic; -- system clock
DBUG7 : out std_logic; -- for debug
DBUG6 : out std_logic; -- for debug
DBUG5 : out std_logic; -- for debug
DBUG4 : out std_logic; -- for debug
DBUG3 : out std_logic; -- for debug
DBUG2 : out std_logic; -- for debug
DBUG1 : out std_logic -- for debug
);
end IP_PDP11;
architecture BEHAVIORAL of IP_PDP11 is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
signal STATE : UCODE_STATE_TYPE;
signal NEXT_STATE : UCODE_STATE_TYPE;
signal C_OPCODE : CNT_OP_TYPE; -- count register micro-op
signal T_OPCODE : REG_OP_TYPE; -- temp register micro-op
signal S_OPCODE : REG_OP_TYPE; -- src operand micro-op
signal D_OPCODE : REG_OP_TYPE; -- dst operand micro-op
signal SA_OPCODE : REG_OP_TYPE; -- src address micro-op
signal DA_OPCODE : REG_OP_TYPE; -- dst address micro-op
signal ALU_OPCODE : ALU_OP_TYPE; -- ALU micro-op
signal SX_OPCODE : SX_OP_TYPE; -- Address micro-op
signal R0_OPCODE : PC_OP_TYPE; -- R0 micro-op
signal R1_OPCODE : PC_OP_TYPE; -- R1 micro-op
signal R2_OPCODE : PC_OP_TYPE; -- R2 micro-op
signal R3_OPCODE : PC_OP_TYPE; -- R3 micro-op
signal R4_OPCODE : PC_OP_TYPE; -- R4 micro-op
signal R5_OPCODE : PC_OP_TYPE; -- R5 micro-op
signal SP_OPCODE : REG_OP_TYPE; -- SP micro-op
signal PC_OPCODE : PC_OP_TYPE; -- PC micro-op
-- Internal busses
signal ABUS : std_logic_vector(15 downto 0); -- ALU operand A bus
signal BBUS : std_logic_vector(15 downto 0); -- ALU operand B bus
signal RBUS : std_logic_vector(15 downto 0); -- ALU result bus
signal SX : std_logic_vector(15 downto 0); -- Addr result bus
signal ADDR_OX : std_logic_vector(15 downto 0); -- Internal addr bus
signal DATA_OX : std_logic_vector(15 downto 0); -- Internal data bus
signal BYTE_DATA : std_logic_vector(15 downto 0); -- Byte_op data
signal ASEL : ASEL_TYPE;
signal BSEL : BSEL_TYPE;
-- Address Decoding
signal MACRO_OP : MACRO_OP_TYPE; -- macro opcode
signal BYTE_OP : std_logic;
signal BYTE_ALU : std_logic;
signal FORMAT_OP : std_logic_vector( 2 downto 0);
signal FORMAT : std_logic_vector( 2 downto 0);
signal SRC_MODE : std_logic_vector( 2 downto 0);
signal SRC_RSEL : std_logic_vector( 2 downto 0);
signal SRC_LOAD : std_logic;
signal DST_MODE : std_logic_vector( 2 downto 0);
signal DST_RSEL : std_logic_vector( 2 downto 0);
signal DST_LOAD : std_logic;
-- Architectural registers
signal R0 : std_logic_vector(15 downto 0); -- register 0
signal R1 : std_logic_vector(15 downto 0); -- register 1
signal R2 : std_logic_vector(15 downto 0); -- register 2
signal R3 : std_logic_vector(15 downto 0); -- register 3
signal R4 : std_logic_vector(15 downto 0); -- register 4
signal R5 : std_logic_vector(15 downto 0); -- register 5
signal SP : std_logic_vector(15 downto 0); -- stack pointer
signal PC : std_logic_vector(15 downto 0); -- program counter
signal PSW : std_logic_vector( 3 downto 0); -- status word
signal T : std_logic_vector(15 downto 0); -- temp register
signal SA : std_logic_vector(15 downto 0); -- src address
signal DA : std_logic_vector(15 downto 0); -- dst address
signal S : std_logic_vector(15 downto 0); -- src operand
signal D : std_logic_vector(15 downto 0); -- dst operand
signal SMUX : std_logic_vector(15 downto 0); -- src operand
signal DMUX : std_logic_vector(15 downto 0); -- dst operand
signal OPREG : std_logic_vector(15 downto 0); -- opcode reg
-- Status flag update
signal UPDATE_N : std_logic; -- update sign flag
signal UPDATE_Z : std_logic; -- update zero flag
signal UPDATE_V : std_logic; -- update overflow flag
signal UPDATE_C : std_logic; -- update carry flag
signal UPDATE_XC : std_logic; -- update aux carry flag
signal SET_N : std_logic; -- set N flag
signal SET_C : std_logic; -- set C flag
signal SET_V : std_logic; -- set V flag
signal SET_Z : std_logic; -- set Z flag
signal CLR_N : std_logic; -- clear N flag
signal CLR_C : std_logic; -- clear C flag
signal CLR_V : std_logic; -- clear V flag
signal CLR_Z : std_logic; -- clear Z flag
signal CCC_OP : std_logic; -- conditional clear
signal SCC_OP : std_logic; -- conditional set
-- Arithmetic Status
signal CARRY : std_logic; -- ALU carry-out
signal ZERO : std_logic; -- ALU Zero status
signal OVERFLOW : std_logic; -- ALU overflow
signal SIGNBIT : std_logic; -- ALU sign bit
signal XC : std_logic; -- ALU carry-out
-- Interrupt Status flip-flops
signal IRQ_FF : std_logic; -- IRQ flip-flop
signal CLR_IRQ : std_logic; -- clear IRQ flip-flop
signal IRQ_MASK : std_logic_vector( 3 downto 0);
signal IRQ_VEC : std_logic_vector( 3 downto 0);
-- Misc
signal MY_RESET : std_logic; -- active high reset
signal FETCH_FF : std_logic; -- fetch cycle flag
signal READING : std_logic; -- R/W status
signal CONDITION : std_logic; -- branch condition
signal INT_OK : std_logic; -- interrupt level OK
signal INIT_MPY : std_logic; -- for multiply
signal MPY_STEP : std_logic; -- for multiply
signal INIT_DIV : std_logic; -- for divide
signal DIV_STEP : std_logic; -- for divide
signal DIV_LAST : std_logic; -- for divide
signal DIV_OP : std_logic; -- for divide
signal SA_SBIT : std_logic; -- for divide
signal DIV_SBIT : std_logic; -- for divide
signal D_SBIT : std_logic; -- for divide
signal BYTE_FF : std_logic; -- byte flag
signal SET_BYTE_FF : std_logic; -- set byte flag
signal CLR_BYTE_FF : std_logic; -- clr byte flag
signal DEST_FF : std_logic; -- dest flag
signal SET_DEST_FF : std_logic; -- set dest flag
signal CLR_DEST_FF : std_logic; -- clr dest flag
signal C : std_logic_vector( 3 downto 0);
signal JSE : std_logic_vector( 6 downto 0);
signal BRANCH_OP : std_logic_vector( 3 downto 0);
--================================================================
-- Constant definition section
--================================================================
--================================================================
-- Component definition section
--================================================================
--==========================
-- instruction decoder
--==========================
component DECODE
port (
MACRO_OP : out MACRO_OP_TYPE; -- opcode
BYTE_OP : out std_logic; -- byte/word
FORMAT : out std_logic_vector( 2 downto 0); -- format
IR : in std_logic_vector(15 downto 0) -- inst reg
);
end component;
--==============================
-- 16-bit ALU
--==============================
component ALU
port (
COUT : out std_logic; -- carry out
ZERO : out std_logic; -- zero
OVFL : out std_logic; -- overflow
SIGN : out std_logic; -- sign
RBUS : out std_logic_vector(15 downto 0); -- result bus
A : in std_logic_vector(15 downto 0); -- operand A
B : in std_logic_vector(15 downto 0); -- operand B
OP : in ALU_OP_TYPE; -- micro op
BYTE_OP : in std_logic; -- byte op
DIV_OP : in std_logic; -- divide op
DIV_SBIT : in std_logic; -- divide sign bit
CIN : in std_logic -- carry in
);
end component;
--==============================
-- 16-bit Address Adder
--==============================
component ADDR
port (
SX : out std_logic_vector(15 downto 0); -- result bus
BX : in std_logic_vector(15 downto 0); -- operand bus
DISP : in std_logic_vector( 7 downto 0); -- displacement
OP : in SX_OP_TYPE -- micro op
);
end component;
--==============================
-- 4-bit Comparator
--==============================
component CMPR
port (
A_LE_B : out std_logic; -- A <= B
A : in std_logic_vector(3 downto 0); -- operand A
B : in std_logic_vector(3 downto 0) -- operand B
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
--================================================================
-- Start of the behavioral description
--================================================================
MY_RESET <= not RESET;
--================================================================
-- Microcode state machine
--================================================================
MICROCODE_STATE_MACHINE:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if ((FEN = '1') and (RDY = '1')) then
STATE <= NEXT_STATE;
-- reset state
if (MY_RESET = '1') then
STATE <= RST_1;
end if;
end if;
end if;
end process;
--================================================================
-- Signals for Debug
--================================================================
DBUG1 <= '1';
DBUG2 <= '1';
DBUG3 <= '1';
DBUG4 <= '1';
DBUG5 <= '1';
DBUG6 <= '1';
DBUG7 <= MY_RESET;
--================================================================
-- Register IRQ (active-low) inputs
--================================================================
INTERRUPT_STATUS_REGISTERS:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
-- Only set the IRQ flip-flop if the interrupt level
-- is less than or equal to the interrupt mask
if ((IRQ0 = '0') and (INT_OK = '1')) then
IRQ_FF <= '1';
end if;
if (CLR_IRQ = '1') then
IRQ_FF <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
IRQ_FF <= '0';
IRQ_VEC <= (others => '0');
IRQ_MASK <= (others => '0');
end if;
end process;
--================================================================
-- Opcode Register
--================================================================
OPCODE_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (STATE = FETCH_OPCODE) then
OPREG <= DATA_IN;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
OPREG <= (others => '0');
end if;
end process;
--================================================================
-- Fetch cycle flag
--================================================================
FETCH_CYCLE_FLAG:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
FETCH_FF <= '0';
if (NEXT_STATE = FETCH_OPCODE) then
FETCH_FF <= '1';
end if;
end if;
end if;
end process;
--================================================================
-- byte flag
--================================================================
BYTE_FLAG:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (SET_BYTE_FF = '1') then
BYTE_FF <= '1';
end if;
if (CLR_BYTE_FF = '1') then
BYTE_FF <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
BYTE_FF <= '0';
end if;
end process;
BYTE <= BYTE_FF;
--================================================================
-- dest flag
--================================================================
DEST_FLAG:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (SET_DEST_FF = '1') then
DEST_FF <= '1';
end if;
if (CLR_DEST_FF = '1') then
DEST_FF <= '0';
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
DEST_FF <= '0';
end if;
end process;
--================================================================
-- modify format to reuse code
--================================================================
MODIFY_FORMAT:
process(FORMAT_OP, DEST_FF)
begin
FORMAT <= FORMAT_OP;
-- force TWO_OPERAND to become ONE_OPERAND
if (DEST_FF = '1') then
FORMAT(0) <= '0';
end if;
end process;
SYNC <= FETCH_FF;
ADDR_OUT <= ADDR_OX;
BRANCH_OP <= OPREG(15) & OPREG(10 downto 8);
SRC_MODE <= OPREG(11 downto 9);
SRC_RSEL <= OPREG( 8 downto 6);
DST_MODE <= OPREG( 5 downto 3);
DST_RSEL <= OPREG( 2 downto 0);
--================================================================
-- Micro-operation and next-state generation
--================================================================
MICRO_OP_AND_NEXT_STATE_GENERATION:
process(MACRO_OP, FORMAT, STATE, PC, SP, SA, DA, T, XC, C, PSW,
SRC_MODE, SRC_RSEL, DST_MODE, DST_RSEL, RBUS, DMUX, SMUX,
SA_SBIT, D_SBIT, BYTE_OP, BYTE_FF, IRQ_FF, CONDITION,
SRC_LOAD, DST_LOAD)
begin
-- default micro-ops
R0_OPCODE <= HOLD;
R1_OPCODE <= HOLD;
R2_OPCODE <= HOLD;
R3_OPCODE <= HOLD;
R4_OPCODE <= HOLD;
R5_OPCODE <= HOLD;
SP_OPCODE <= HOLD;
PC_OPCODE <= HOLD;
SA_OPCODE <= HOLD;
DA_OPCODE <= HOLD;
S_OPCODE <= HOLD;
D_OPCODE <= HOLD;
C_OPCODE <= HOLD;
T_OPCODE <= HOLD;
ALU_OPCODE <= OP_INCA1;
SX_OPCODE <= OP_INC2;
-- default flag control
UPDATE_N <= '0'; -- update sign flag
UPDATE_Z <= '0'; -- update zero flag
UPDATE_V <= '0'; -- update overflow flag
UPDATE_C <= '0'; -- update carry flag
UPDATE_XC <= '0'; -- update carry flag
CLR_IRQ <= '0'; -- clear IRQ_FF
SET_N <= '0'; -- set N flag
SET_C <= '0'; -- set C flag
SET_V <= '0'; -- set V flag
SET_Z <= '0'; -- set Z flag
CLR_N <= '0'; -- clear N flag
CLR_C <= '0'; -- clear C flag
CLR_V <= '0'; -- clear V flag
CLR_Z <= '0'; -- clear Z flag
CCC_OP <= '0'; -- conditional clear
SCC_OP <= '0'; -- conditional set
BYTE_ALU <= '0'; -- ALU byte operation
NEXT_STATE <= FETCH_OPCODE;
DATA_OX <= RBUS;
ADDR_OX <= PC;
DST_LOAD <= '0';
SRC_LOAD <= '0';
READING <= '1';
ASEL <= SEL_PC;
BSEL <= SEL_D;
SET_BYTE_FF <= '0';
CLR_BYTE_FF <= '0';
SET_DEST_FF <= '0';
CLR_DEST_FF <= '0';
INIT_MPY <= '0';
INIT_DIV <= '0';
MPY_STEP <= '0';
DIV_STEP <= '0';
DIV_LAST <= '0';
DIV_SBIT <= D_SBIT;
case STATE is
--============================================
-- Reset startup sequence
--============================================
when RST_1 =>
-- Stay here until reset is de-bounced
NEXT_STATE <= FETCH_OPCODE;
when IRQ_1 =>
-- fix me !!!!
-- lot's of stuff missing here
ALU_OPCODE <= OP_TA;
T_OPCODE <= LOAD_FROM_ALU;
CLR_IRQ <= '1';
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Fetch Opcode State
--============================================
when FETCH_OPCODE =>
if (IRQ_FF = '1') then
-- handle the interrupt
NEXT_STATE <= IRQ_1;
else
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
NEXT_STATE <= GOT_OPCODE;
end if;
CLR_BYTE_FF <= '1';
--============================================
-- Opcode register contains an opcode
--============================================
when GOT_OPCODE =>
if (BYTE_OP = '1') then
SET_BYTE_FF <= '1';
else
CLR_BYTE_FF <= '1';
end if;
case FORMAT is
--=================================
-- One operand Instruction Format
--=================================
when ONE_OPERAND =>
-- destination address mode calculations
case DST_MODE(2 downto 1) is
-- register
when "00" =>
-- check deferred bit
if (DST_MODE(0) = '0') then
-- load from register
D_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
DA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= DST_RI1;
end if;
-- post-increment
when "01" =>
ADDR_OX <= DMUX;
-- check deferred bit
if (DST_MODE(0) = '0') then
D_OPCODE <= LOAD_FROM_MEM;
DA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= DST_PI1;
else
-- deferred
DA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_PI2;
end if;
-- pre-decrement
when "10" =>
ASEL <= SEL_DMUX;
ALU_OPCODE <= OP_DECA2;
if (BYTE_OP = '1') then
ALU_OPCODE <= OP_DECA1;
end if;
DST_LOAD <= '1';
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DST_PD1;
-- indexed ("11")
when others =>
-- get the next word
ADDR_OX <= PC;
D_OPCODE <= LOAD_FROM_MEM;
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
NEXT_STATE <= DST_X1;
end case;
--=======================================================
-- Two operands instruction Format
--=======================================================
when TWO_OPERAND =>
-- allow dest code reuse
SET_DEST_FF <= '1';
-- source address mode calculations
case SRC_MODE(2 downto 1) is
-- register
when "00" =>
if (SRC_MODE(0) = '0') then
-- load from register
S_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= GOT_OPCODE;
else
-- deferred
SA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= SRC_RI1;
end if;
-- post-increment
when "01" =>
ADDR_OX <= SMUX;
-- check deferred bit
if (SRC_MODE(0) = '0') then
S_OPCODE <= LOAD_FROM_MEM;
SA_OPCODE <= LOAD_FROM_REG;
NEXT_STATE <= SRC_PI1;
else
-- deferred
SA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_PI2;
end if;
-- pre-decrement
when "10" =>
ASEL <= SEL_SMUX;
ALU_OPCODE <= OP_DECA2;
if (BYTE_OP = '1') then
ALU_OPCODE <= OP_DECA1;
end if;
SRC_LOAD <= '1';
SA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= SRC_PD1;
-- indexed ("11")
when others =>
-- get the next word
ADDR_OX <= PC;
S_OPCODE <= LOAD_FROM_MEM;
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
NEXT_STATE <= SRC_X1;
end case;
--=================================
-- Branch Instruction Format
--=================================
when BRA_FORMAT =>
SX_OPCODE <= OP_REL;
if (CONDITION = '1') then
PC_OPCODE <= LOAD_FROM_SX;
end if;
NEXT_STATE <= FETCH_OPCODE;
--======================================
-- Floating Point Instruction Format
--======================================
when FLOAT =>
-- not implemented
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
--======================================
-- Implied-Operand Instruction Format
--======================================
when others =>
case MACRO_OP is
when MOP_HALT =>
-- halt processor
NEXT_STATE <= HALT_1;
when MOP_WAIT =>
-- wait for interrupt
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_RESET =>
-- reset bus
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_RTS =>
-- return from subroutine
-- load the PC from the link reg
ASEL <= SEL_DMUX;
ALU_OPCODE <= OP_TA;
PC_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= RTS_1;
-- special case when PC is link reg
if (DST_RSEL = "111") then
-- load the PC from the stack
ADDR_OX <= SP;
PC_OPCODE <= LOAD_FROM_MEM;
-- post-increment the stack pointer
ASEL <= SEL_SP;
ALU_OPCODE <= OP_INCA2;
SP_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= FETCH_OPCODE;
end if;
when MOP_RTI =>
-- return from interrupt
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_RTT =>
-- return from interrupt
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_MARK =>
-- mark stack
NEXT_STATE <= FETCH_OPCODE;
when MOP_TRAP =>
-- SW trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_BPT =>
-- breakpoint trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_IOT =>
-- I/O trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_EMT =>
-- emulator trap
-- not implemented yet !!!
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEN =>
-- set N flag
SET_N <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEC =>
-- set C flag
SET_C <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEV =>
-- set V flag
SET_V <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SEZ =>
-- set Z flag
SET_Z <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLN =>
-- clear N flag
CLR_N <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLC =>
-- clear C flag
CLR_C <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLV =>
-- clear V flag
CLR_V <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CLZ =>
-- clear Z flag
CLR_Z <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CCC =>
-- clear condition codes
CCC_OP <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_SCC =>
-- set condition codes
SCC_OP <= '1';
NEXT_STATE <= FETCH_OPCODE;
when MOP_CSM =>
-- call supervisor mode
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPT =>
-- move from processor type
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPI =>
-- move from prev I-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MTPI =>
-- move to prev I-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPD =>
-- move to prev D-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MTPD =>
-- move to prev D-space
NEXT_STATE <= FETCH_OPCODE;
when MOP_MTPS =>
-- move to processor status
NEXT_STATE <= FETCH_OPCODE;
when MOP_MFPS =>
-- move from processor status
NEXT_STATE <= FETCH_OPCODE;
when others =>
-- unimplemented instruction
NEXT_STATE <= FETCH_OPCODE;
end case;
end case; -- end of instruction format case
--====================================================
-- We have the operands, now execute the instruction
--====================================================
when EXEC_OPCODE =>
CLR_DEST_FF <= '1';
BYTE_ALU <= BYTE_OP;
case MACRO_OP is
--=================================
-- Jump Instructions
--=================================
-- Jump
when MOP_JMP =>
PC_OPCODE <= LOAD_FROM_DA;
NEXT_STATE <= FETCH_OPCODE;
-- Jump to Subroutine
when MOP_JSR =>
-- pre-decrement the stack pointer
ASEL <= SEL_SP;
ALU_OPCODE <= OP_DECA2;
SP_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= JSR_1;
--=================================
-- One-operand Instructions
--=================================
-- Test
when MOP_TST =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_TA;
D_OPCODE <= HOLD;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
CLR_C <= '1'; -- clear carry flag
NEXT_STATE <= FETCH_OPCODE;
-- Bit Test
when MOP_BIT =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_AND;
D_OPCODE <= HOLD;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
NEXT_STATE <= FETCH_OPCODE;
-- Clear
when MOP_CLR =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ZERO;
D_OPCODE <= LOAD_FROM_ALU;
CLR_N <= '1'; -- clear sign flag
SET_Z <= '1'; -- set zero flag
CLR_V <= '1'; -- clear overflow flag
CLR_C <= '1'; -- clear carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Sign Extend
when MOP_SXT =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ZERO;
-- check the sign bit
if (PSW(3) = '1') then
ALU_OPCODE <= OP_ONES;
end if;
D_OPCODE <= LOAD_FROM_ALU;
CLR_N <= '1'; -- clear sign flag
SET_Z <= '1'; -- set zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Ones Complement
when MOP_COM =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_INV;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
SET_C <= '1'; -- set carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Decrement by 1
when MOP_DEC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_DECA1;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Increment by 1
when MOP_INC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_INCA1;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Negate
when MOP_NEG =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_NEG;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Swap Bytes
when MOP_SWAB =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_SWP;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
CLR_C <= '1'; -- clear carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Rotate Right
when MOP_ROR =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ROR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Rotate Left
when MOP_ROL =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ROL;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Shift Right
when MOP_ASR =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ASR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Shift Left
when MOP_ASL =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ASL;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
--=================================
-- Two-operand Instructions
--=================================
-- Add
when MOP_ADD =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_ADD;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Add Carry
when MOP_ADC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_ADC;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Subtract
when MOP_SUB =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_SUBA;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Subtract Carry
when MOP_SBC =>
ASEL <= SEL_D;
ALU_OPCODE <= OP_SBC;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Compare
when MOP_CMP =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_SUBA;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
UPDATE_V <= '1'; -- update overflow flag
UPDATE_C <= '1'; -- update carry flag
NEXT_STATE <= FETCH_OPCODE;
-- Move
when MOP_MOV =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_TA;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Exclusive OR
when MOP_XOR =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_XOR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_Z <= '1'; -- update zero flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Bit Clear
when MOP_BIC =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_BIC;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Bit Set
when MOP_BIS =>
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_OR;
D_OPCODE <= LOAD_FROM_ALU;
UPDATE_N <= '1'; -- update sign flag
UPDATE_Z <= '1'; -- update zero flag
CLR_V <= '1'; -- clear overflow flag
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Multiply
when MOP_MUL =>
-- multiplicand is in D
-- multiplier is in S
-- accumulate product in T:SA
-- clear T and SA
-- load C with the MPY count
INIT_MPY <= '1';
if (DST_MODE = "000") then
-- store to register
DST_LOAD <= '1';
NEXT_STATE <= FETCH_OPCODE;
else
-- store to destination address
NEXT_STATE <= STORE_D;
end if;
-- Divide
when MOP_DIV =>
-- the divisor is in S
-- the dividend is in D:T
-- the quotient will be in T
-- the remainder will be left in D
-- compare D and S
ASEL <= SEL_S;
BSEL <= SEL_D;
ALU_OPCODE <= OP_SUBA;
INIT_DIV <= '1';
UPDATE_XC <= '1'; -- update aux carry flag
SA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_1;
when others =>
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
end case; -- end of MACRO_OP case
--============================================
-- Complete destination register indirect
--============================================
when DST_RI1 =>
ADDR_OX <= DA;
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
--============================================
-- Complete source register indirect
--============================================
when SRC_RI1 =>
ADDR_OX <= SA;
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= GOT_OPCODE;
--============================================
-- Complete destination post increment
--============================================
when DST_PI1 =>
if (DST_RSEL = "111") then
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
else
-- post-increment the register
ASEL <= SEL_DMUX;
ALU_OPCODE <= OP_INCA2;
if (BYTE_FF = '1') then
ALU_OPCODE <= OP_INCA1;
end if;
DST_LOAD <= '1';
end if;
NEXT_STATE <= EXEC_OPCODE;
--============================================
-- Complete destination post indirect
--============================================
when DST_PI2 =>
ADDR_OX <= DA;
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_PI1;
--============================================
-- Complete source post increment
--============================================
when SRC_PI1 =>
if (SRC_RSEL = "111") then
-- increment the PC
SX_OPCODE <= OP_INC2;
PC_OPCODE <= LOAD_FROM_SX;
else
-- post-increment the register
ASEL <= SEL_SMUX;
ALU_OPCODE <= OP_INCA2;
if (BYTE_FF = '1') then
ALU_OPCODE <= OP_INCA1;
end if;
SRC_LOAD <= '1';
end if;
NEXT_STATE <= GOT_OPCODE;
--============================================
-- Complete source post indirect
--============================================
when SRC_PI2 =>
ADDR_OX <= SA;
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_PI1;
--============================================
-- Complete destination pre decrement
--============================================
when DST_PD1 =>
ADDR_OX <= DA;
-- check deferred bit
if (DST_MODE(0) = '0') then
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
DA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_RI1;
end if;
--============================================
-- Complete source pre decrement
--============================================
when SRC_PD1 =>
ADDR_OX <= SA;
-- check deferred bit
if (DST_MODE(0) = '0') then
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= GOT_OPCODE;
else
-- deferred
SA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_RI1;
end if;
--============================================
-- Complete destination indexed address
--============================================
when DST_X1 =>
-- add D + R
ASEL <= SEL_D; -- D
BSEL <= SEL_DMUX; -- R
ALU_OPCODE <= OP_ADD;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DST_X2;
--============================================
-- Complete destination indexed address
--============================================
when DST_X2 =>
ADDR_OX <= DA;
-- check deferred bit
if (DST_MODE(0) = '0') then
D_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
DA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= DST_RI1;
end if;
--============================================
-- Complete source indexed address
--============================================
when SRC_X1 =>
-- add S + R
ASEL <= SEL_S; -- S
BSEL <= SEL_SMUX; -- R
ALU_OPCODE <= OP_ADD;
SA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= SRC_X2;
--============================================
-- Complete source indexed address
--============================================
when SRC_X2 =>
ADDR_OX <= SA;
-- check deferred bit
if (SRC_MODE(0) = '0') then
S_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= EXEC_OPCODE;
else
-- deferred
SA_OPCODE <= LOAD_FROM_MEM;
NEXT_STATE <= SRC_RI1;
end if;
--============================================
-- Store the result
--============================================
when STORE_D =>
-- store to the destination address
ADDR_OX <= DA;
ASEL <= SEL_D;
ALU_OPCODE <= OP_TA;
READING <= '0';
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Halt the processor
-- requires reboot or operator console input
--============================================
when HALT_1 =>
PC_OPCODE <= HOLD;
NEXT_STATE <= HALT_1;
--============================================
-- Complete the JSR instruction
--============================================
when JSR_1 =>
-- store the source register
-- onto the stack
ADDR_OX <= SP;
READING <= '0';
ASEL <= SEL_SMUX;
ALU_OPCODE <= OP_TA;
NEXT_STATE <= JSR_2;
-- special case when PC is link reg
if (SRC_RSEL = "111") then
-- load the PC with the dest address
PC_OPCODE <= LOAD_FROM_DA;
NEXT_STATE <= FETCH_OPCODE;
end if;
when JSR_2 =>
-- copy the PC to the source register
ASEL <= SEL_PC;
ALU_OPCODE <= OP_TA;
SRC_LOAD <= '1';
-- load the PC with the dest address
PC_OPCODE <= LOAD_FROM_DA;
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Complete the RTS instruction
--============================================
when RTS_1 =>
-- load the PC from the stack
ADDR_OX <= SP;
PC_OPCODE <= LOAD_FROM_MEM;
-- post-increment the stack pointer
ASEL <= SEL_SP;
ALU_OPCODE <= OP_INCA2;
SP_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Complete the multiply instruction
--============================================
when MPY_1 =>
-- if the multiplier bit is a 1
-- then add the multiplicand to the product
-- and shift product and multiplier right
ASEL <= SEL_D;
BSEL <= SEL_T;
ALU_OPCODE <= OP_ADD;
MPY_STEP <= '1';
-- decrement the loop count
C_OPCODE <= DEC;
NEXT_STATE <= MPY_1;
-- Check if we are done
if (C = "0000") then
NEXT_STATE <= MPY_2;
end if;
when MPY_2 =>
-- store the upper product
ADDR_OX <= DA;
DATA_OX <= T;
READING <= '0';
-- increment DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_INCA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= MPY_3;
when MPY_3 =>
-- store the lower product
ADDR_OX <= DA;
ASEL <= SEL_SA;
ALU_OPCODE <= OP_TA;
READING <= '0';
NEXT_STATE <= FETCH_OPCODE;
--============================================
-- Complete the divide instruction
--============================================
when DIV_1 =>
-- increment DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_INCA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_2;
-- if D > S then abort
if (XC = '1') then
NEXT_STATE <= FETCH_OPCODE;
end if;
when DIV_2 =>
-- get the lower dividend
ADDR_OX <= DA;
T_OPCODE <= LOAD_FROM_MEM;
-- decrement DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_DECA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_3;
when DIV_3 =>
-- compare D and S
ASEL <= SEL_S;
BSEL <= SEL_D;
-- Check if we need to restore
if (XC = '1') then
DIV_SBIT <= SA_SBIT;
BSEL <= SEL_SA;
end if;
ALU_OPCODE <= OP_SUBA;
UPDATE_XC <= '1'; -- update aux carry flag
DIV_STEP <= '1';
C_OPCODE <= DEC;
NEXT_STATE <= DIV_3;
-- Check if we are done
if (C = "0000") then
NEXT_STATE <= DIV_4;
end if;
when DIV_4 =>
-- compare D and S
ASEL <= SEL_S;
BSEL <= SEL_D;
-- Check if we need to restore
if (XC = '1') then
DIV_SBIT <= SA_SBIT;
BSEL <= SEL_SA;
end if;
ALU_OPCODE <= OP_SUBA;
UPDATE_XC <= '1'; -- update aux carry flag
DIV_LAST <= '1';
C_OPCODE <= DEC;
NEXT_STATE <= DIV_5;
when DIV_5 =>
-- store the quotient
ADDR_OX <= DA;
DATA_OX <= T;
READING <= '0';
-- increment DA
ASEL <= SEL_DA;
ALU_OPCODE <= OP_INCA2;
DA_OPCODE <= LOAD_FROM_ALU;
NEXT_STATE <= DIV_6;
when DIV_6 =>
-- store the remainder
ADDR_OX <= DA;
ASEL <= SEL_D;
-- Check if we need to restore
if (XC = '1') then
ASEL <= SEL_SA;
end if;
ALU_OPCODE <= OP_TA;
READING <= '0';
NEXT_STATE <= FETCH_OPCODE;
--=========================================
-- Unimplemented Opcodes
--=========================================
when others =>
PC_OPCODE <= HOLD;
NEXT_STATE <= UII_1;
end case; -- end of STATE case
--=============================================
-- Load Source register
--=============================================
if (SRC_LOAD = '1') then
-- select register to load
case SRC_RSEL is
when "000" =>
R0_OPCODE <= LOAD_FROM_ALU;
when "001" =>
R1_OPCODE <= LOAD_FROM_ALU;
when "010" =>
R2_OPCODE <= LOAD_FROM_ALU;
when "011" =>
R3_OPCODE <= LOAD_FROM_ALU;
when "100" =>
R4_OPCODE <= LOAD_FROM_ALU;
when "101" =>
R5_OPCODE <= LOAD_FROM_ALU;
when "110" =>
SP_OPCODE <= LOAD_FROM_ALU;
when "111" =>
PC_OPCODE <= LOAD_FROM_ALU;
when others =>
end case;
end if;
--=============================================
-- Load Destination register
--=============================================
if (DST_LOAD = '1') then
-- select register to load
case DST_RSEL is
when "000" =>
R0_OPCODE <= LOAD_FROM_ALU;
when "001" =>
R1_OPCODE <= LOAD_FROM_ALU;
when "010" =>
R2_OPCODE <= LOAD_FROM_ALU;
when "011" =>
R3_OPCODE <= LOAD_FROM_ALU;
when "100" =>
R4_OPCODE <= LOAD_FROM_ALU;
when "101" =>
R5_OPCODE <= LOAD_FROM_ALU;
when "110" =>
SP_OPCODE <= LOAD_FROM_ALU;
when "111" =>
PC_OPCODE <= LOAD_FROM_ALU;
when others =>
end case;
end if;
end process;
--================================================
-- Destination register select
--================================================
DEST_REG_SELECT:
process(DST_RSEL, R0, R1, R2, R3, R4, R5, SP, PC)
begin
case DST_RSEL is
when "000" =>
DMUX <= R0;
when "001" =>
DMUX <= R1;
when "010" =>
DMUX <= R2;
when "011" =>
DMUX <= R3;
when "100" =>
DMUX <= R4;
when "101" =>
DMUX <= R5;
when "110" =>
DMUX <= SP;
when others =>
DMUX <= PC;
end case;
end process;
--================================================
-- Source register select
--================================================
SRC_RSEL_SELECT:
process(SRC_RSEL, R0, R1, R2, R3, R4, R5, SP, PC)
begin
case SRC_RSEL is
when "000" =>
SMUX <= R0;
when "001" =>
SMUX <= R1;
when "010" =>
SMUX <= R2;
when "011" =>
SMUX <= R3;
when "100" =>
SMUX <= R4;
when "101" =>
SMUX <= R5;
when "110" =>
SMUX <= SP;
when others =>
SMUX <= PC;
end case;
end process;
--============================================
-- Branch Condition Select
--============================================
BRANCH_CONDITION_SELECT:
process(BRANCH_OP, PSW)
begin
CONDITION <= '0';
case BRANCH_OP is
when "0001" =>
-- BR :: Unconditional
CONDITION <= '1';
when "0010" =>
-- BNE :: Not Equal
-- Zero = 0
CONDITION <= not PSW(2);
when "0011" =>
-- BEQ :: Equal
-- Zero = 1
CONDITION <= PSW(2);
when "0100" =>
-- BGE :: Greater Than of Equal
-- (Sign xor Overflow) = 0
CONDITION <= not (PSW(3) xor PSW(1));
when "0101" =>
-- BLT :: Less Than
-- (Sign xor Overflow) = 1
CONDITION <= PSW(3) xor PSW(1);
when "0110" =>
-- BGT :: Greater Than
-- (zero and (Sign xor Overflow)) = 0
CONDITION <= not(PSW(2) or (PSW(3) xor PSW(1)));
when "0111" =>
-- BLE :: Less Than or Equal
-- (zero and (Sign xor Overflow)) = 1
CONDITION <= PSW(2) or (PSW(3) xor PSW(1));
when "1000" =>
-- BPL :: Plus
-- Sign = 0
CONDITION <= not PSW(3);
when "1001" =>
-- BMI :: Minus
-- Sign = 1
CONDITION <= PSW(3);
when "1010" =>
-- BHI :: Higher
-- (Carry or Zero) = 0
CONDITION <= not(PSW(2) or PSW(0));
when "1011" =>
-- BLOS :: Lower or same
-- (Carry or Zero) = 1
CONDITION <= PSW(2) or PSW(0);
when "1100" =>
-- BVC :: Overflow Clear
-- Overflow = 0
CONDITION <= not PSW(1);
when "1101" =>
-- BVS :: Overflow Set
-- Overflow = 1
CONDITION <= PSW(1);
when "1110" =>
-- BCC :: Carry clear
-- Carry = 0
CONDITION <= not PSW(0);
when "1111" =>
-- BCS :: Carry set
-- Carry = 1
CONDITION <= PSW(0);
when others =>
-- Never
CONDITION <= '0';
end case;
end process;
--==================================================
-- A Mux
--==================================================
AMUX:
process(ASEL, SA, DA, S, D, DMUX, SMUX, PSW, SP, PC)
begin
case ASEL is
when SEL_SA =>
ABUS <= SA;
when SEL_DA =>
ABUS <= DA;
when SEL_S =>
ABUS <= S;
when SEL_D =>
ABUS <= D;
when SEL_DMUX =>
ABUS <= DMUX;
when SEL_SMUX =>
ABUS <= SMUX;
when SEL_PSW =>
ABUS <= "000000000000" & PSW;
when SEL_SP =>
ABUS <= SP;
when others =>
ABUS <= PC;
end case;
end process;
JSE <= (others => OPREG(7));
--=========================================================
-- B Mux
--=========================================================
BMUX:
process(BSEL, SA, DMUX, SMUX, T, D)
begin
case BSEL is
when SEL_SA =>
BBUS <= SA;
when SEL_DMUX =>
BBUS <= DMUX;
when SEL_SMUX =>
BBUS <= SMUX;
when SEL_T =>
BBUS <= T;
when others =>
BBUS <= D;
end case;
end process;
--=============================================
-- Byte input data (swap memory data byte)
--=============================================
MEM_BYTE_DATA_IN:
process (ADDR_OX(0), DATA_IN)
begin
BYTE_DATA <= "00000000" & DATA_IN(7 downto 0);
if (ADDR_OX(0) = '1') then
BYTE_DATA <= "00000000" & DATA_IN(15 downto 8);
end if;
end process;
--=============================================
-- Byte output data (swap memory data byte)
--=============================================
MEM_BYTE_DATA_OUT:
process (BYTE_OP, ADDR_OX(0), DATA_OX)
begin
DATA_OUT <= DATA_OX;
if ((BYTE_OP = '1') and (ADDR_OX(0) = '1')) then
DATA_OUT(15 downto 8) <= DATA_OX(7 downto 0);
end if;
end process;
--=======================================================
-- External RAM Write Enable
--=======================================================
R_W <= READING;
--=================================================
-- Processor Status Register
--=================================================
PSW_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
--===== Sign ========
if (UPDATE_N = '1') then
PSW(3) <= RBUS(15);
end if;
if (SET_N = '1') then
PSW(3) <= '1';
end if;
if (CLR_N = '1') then
PSW(3) <= '0';
end if;
if (CCC_OP = '1') then
PSW(3) <= PSW(3) and not OPREG(3);
end if;
if (SCC_OP = '1') then
PSW(3) <= PSW(3) or OPREG(3);
end if;
--===== Zero ========
if (UPDATE_Z = '1') then
PSW(2) <= ZERO;
end if;
if (SET_Z = '1') then
PSW(2) <= '1';
end if;
if (CLR_Z = '1') then
PSW(2) <= '0';
end if;
if (CCC_OP = '1') then
PSW(2) <= PSW(2) and not OPREG(2);
end if;
if (SCC_OP = '1') then
PSW(2) <= PSW(2) or OPREG(2);
end if;
--===== Overflow ========
if (UPDATE_V = '1') then
PSW(1) <= OVERFLOW;
end if;
if (SET_V = '1') then
PSW(1) <= '1';
end if;
if (CLR_V = '1') then
PSW(1) <= '0';
end if;
if (CCC_OP = '1') then
PSW(1) <= PSW(1) and not OPREG(1);
end if;
if (SCC_OP = '1') then
PSW(1) <= PSW(1) or OPREG(1);
end if;
--===== Carry ========
if (UPDATE_C = '1') then
PSW(0) <= CARRY;
end if;
if (SET_C = '1') then
PSW(0) <= '1';
end if;
if (CLR_C = '1') then
PSW(0) <= '0';
end if;
if (CCC_OP = '1') then
PSW(0) <= PSW(0) and not OPREG(0);
end if;
if (SCC_OP = '1') then
PSW(0) <= PSW(0) or OPREG(0);
end if;
--===== Aux Carry ========
if (UPDATE_XC = '1') then
XC <= CARRY;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
PSW <= (others => '0');
XC <= '0';
end if;
end process;
--=======================
-- Register R0
--=======================
REGISTER_R0:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R0_OPCODE is
when LOAD_FROM_ALU =>
R0 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R0 <= (others => '0');
end if;
end process;
--=======================
-- Register R1
--=======================
REGISTER_R1:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R1_OPCODE is
when LOAD_FROM_ALU =>
R1 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R1 <= (others => '0');
end if;
end process;
--=======================
-- Register R2
--=======================
REGISTER_R2:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R2_OPCODE is
when LOAD_FROM_ALU =>
R2 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R2 <= (others => '0');
end if;
end process;
--=======================
-- Register R3
--=======================
REGISTER_R3:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R3_OPCODE is
when LOAD_FROM_ALU =>
R3 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R3 <= (others => '0');
end if;
end process;
--=======================
-- Register R4
--=======================
REGISTER_R4:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R4_OPCODE is
when LOAD_FROM_ALU =>
R4 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R4 <= (others => '0');
end if;
end process;
--=======================
-- Register R5
--=======================
REGISTER_R5:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case R5_OPCODE is
when LOAD_FROM_ALU =>
R5 <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
R5 <= (others => '0');
end if;
end process;
--=======================
-- Stack Pointer
--=======================
STACK_POINTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case SP_OPCODE is
when LOAD_FROM_ALU =>
SP <= RBUS;
when others =>
-- hold
end case;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
SP <= (others => '0');
end if;
end process;
--=======================
-- Program Counter
--=======================
PROGRAM_COUNTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case PC_OPCODE is
when LOAD_FROM_SX =>
PC <= SX;
when LOAD_FROM_ALU =>
PC <= RBUS;
when LOAD_FROM_MEM =>
PC <= DATA_IN;
when LOAD_FROM_DA =>
PC <= DA;
when others =>
-- hold
end case;
PC(0) <= '0'; -- PC is always even !!
end if;
end if;
-- reset state
if (MY_RESET = '1') then
PC <= (others => '0');
end if;
end process;
--===================================
-- Source operand Register
--===================================
S_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case S_OPCODE is
when LOAD_FROM_ALU =>
S <= RBUS;
when LOAD_FROM_REG =>
S <= SMUX;
when LOAD_FROM_MEM =>
S <= DATA_IN;
if (BYTE_OP = '1') then
S <= BYTE_DATA;
end if;
when others =>
-- hold
end case;
-- MPY step (shift multipier)
if (MPY_STEP = '1') then
S <= '0' & S(15 downto 1);
end if;
end if;
end if;
end process;
--===================================
-- Destination operand Register
--===================================
D_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
D_SBIT <= '0';
case D_OPCODE is
when LOAD_FROM_ALU =>
D <= RBUS;
when LOAD_FROM_REG =>
D <= DMUX;
when LOAD_FROM_MEM =>
D <= DATA_IN;
if (BYTE_OP = '1') then
D <= BYTE_DATA;
end if;
when others =>
-- hold
end case;
-- DIV step shift
if (DIV_STEP = '1') then
if (XC = '1') then
-- subtract and shift
D <= SA(14 downto 0) & T(15);
D_SBIT <= SA(15);
else
-- shift
D <= D(14 downto 0) & T(15);
D_SBIT <= D(15);
end if;
end if;
-- last DIV step
if (DIV_LAST = '1') then
if (XC = '1') then
-- subtract with no shift
D <= SA;
end if;
end if;
end if;
end if;
end process;
--===================================
-- Source Address Register
--===================================
SA_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
SA_SBIT <= '0';
case SA_OPCODE is
when LOAD_FROM_ALU =>
SA <= RBUS;
when LOAD_FROM_REG =>
SA <= SMUX;
when LOAD_FROM_MEM =>
SA <= DATA_IN;
when others =>
-- hold
end case;
-- initialize to zero for MPY
if (INIT_MPY = '1') then
SA <= (others => '0');
end if;
-- MPY step (add and shift)
if (MPY_STEP = '1') then
if (S(0) = '1') then
-- add and shift
SA <= RBUS(0) & SA(15 downto 1);
else
-- shift
SA <= T(0) & SA(15 downto 1);
end if;
end if;
-- DIV step (sub and shift)
if (DIV_STEP = '1') then
SA <= RBUS(14 downto 0) & T(15);
SA_SBIT <= RBUS(15);
end if;
-- last DIV step (sub with no shift)
if (DIV_LAST = '1') then
SA <= RBUS(15 downto 0);
end if;
end if;
end if;
end process;
--===================================
-- Destination Address Register
--===================================
DA_REGISTER:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case DA_OPCODE is
when LOAD_FROM_ALU =>
DA <= RBUS;
when LOAD_FROM_REG =>
DA <= DMUX;
when LOAD_FROM_MEM =>
DA <= DATA_IN;
when others =>
-- hold
end case;
end if;
end if;
end process;
--===================================
-- Temporary Register
--===================================
T_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case T_OPCODE is
when LOAD_FROM_ALU =>
T <= RBUS;
when LOAD_FROM_MEM =>
T <= DATA_IN;
when others =>
-- hold
end case;
-- init to zero for MPY
if (INIT_MPY = '1') then
T <= (others => '0');
end if;
-- MPY step shift
if (MPY_STEP = '1') then
if (S(0) = '1') then
-- add and shift
T <= CARRY & RBUS(15 downto 1);
else
-- shift
T <= '0' & T(15 downto 1);
end if;
end if;
-- DIV step shift
if ((DIV_STEP = '1') or (DIV_LAST = '1')) then
T <= T(14 downto 0) & CARRY;
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
T <= (others => '0');
end if;
end process;
--===================================
-- Count Register
--===================================
C_REGISTER:
process(CLK, MY_RESET)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
case C_OPCODE is
when LOAD_COUNT =>
-- load count from opcode
C <= OPREG(7 downto 4);
when DEC =>
-- decrement
C <= C - 1;
when others =>
-- hold
end case;
-- initialize with MPY count
if (INIT_MPY = '1') then
C <= (others => '1');
end if;
-- initialize with DIV count
if (INIT_DIV = '1') then
C <= (others => '1');
end if;
end if;
end if;
-- reset state
if (MY_RESET = '1') then
C <= (others => '0');
end if;
end process;
DIV_OP <= DIV_STEP or DIV_LAST;
--===================================
-- Instantiate the ALU
--===================================
ALU1:
ALU port map (
COUT => CARRY,
ZERO => ZERO,
OVFL => OVERFLOW,
SIGN => SIGNBIT,
RBUS => RBUS,
A => ABUS,
B => BBUS,
OP => ALU_OPCODE,
BYTE_OP => BYTE_ALU,
DIV_OP => DIV_OP,
DIV_SBIT => DIV_SBIT,
CIN => PSW(0)
);
--===================================
-- Instantiate the Address adder
--===================================
ADDR1:
ADDR port map (
SX => SX,
BX => PC,
DISP => OPREG(7 downto 0),
OP => SX_OPCODE
);
--=========================================
-- Instantiate the instruction decoder
--=========================================
DECODER:
DECODE port map (
MACRO_OP => MACRO_OP,
BYTE_OP => BYTE_OP,
FORMAT => FORMAT_OP,
IR => OPREG
);
--================================================
-- Instantiate the interrupt priority comparator
--================================================
PRIORITY:
CMPR port map (
A_LE_B => INT_OK,
A => "0000",
B => "1111"
);
end BEHAVIORAL;
| gpl-3.0 | 3c6a57f55df44be8ae210430837ee783 | 0.318605 | 5.33442 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ram_dq_INST_lb.vhd | 2 | 7,075 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_lb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_lb IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_lb;
ARCHITECTURE SYN OF ram_dq_inst_lb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_lb",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_lb"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_lb"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_lb.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_lb.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_lb.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_lb.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_lb_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | df91ea7ead1daf953ca09bcc1c4753ce | 0.672085 | 3.439475 | false | false | false | false |
Alix82/mip32vhdl | pc-next.vhd | 1 | 3,184 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mips_constants.all;
Entity PC_NEXT is
Port (clk : in std_logic;
reset : in std_logic;
i_instrext : in std_logic_vector(31 downto 0);
i_alu_result : in std_logic_vector(31 downto 0);
pause : in std_logic;
aluzero : in std_logic;
jump : in std_logic;
branch : in std_logic;
jumptoreg : in std_logic;
discard : out std_logic;
pcnext : out std_logic_vector(31 downto 0)
);
End;
Architecture rtl of PC_NEXT is
signal pccounter : std_logic_vector(31 downto 0) := X"00000000";--X"00400580";
signal debug_pcnext_alu_res : std_logic_vector(31 downto 0) := (others => '0');
signal debug_jump : std_logic;
signal debug_branch : std_logic;
signal debug_jumptoreg : std_logic;
signal debug_aluzero : std_logic;
signal debug_pcnext_pause : std_logic;
begin
pcnext <= pccounter;
process (clk)
Variable tmp1 : std_logic_vector (31 downto 0);
Variable tmp2 : std_logic_vector (31 downto 0);
Variable pcplus4 : std_logic_vector (31 downto 0);
begin
if rising_edge(clk) then
if reset = '1' then
pccounter <= (others => '0');
else
if pause = '0' then
tmp1 := "00000000000000000000000000000000";
tmp2 := "00000000000000000000000000000000";
if jumptoreg = '1' then
pccounter <= i_alu_result;
elsif branch = '1' and aluzero = '1' then
tmp1(31 downto 2) := i_instrext(29 downto 0);
tmp2 := tmp1 + pccounter;
pccounter <= tmp2 - 4;
elsif jump = '1' then
tmp1(25 downto 2) := i_instrext(23 downto 0);
pccounter <= ((pccounter and X"F0000000") or tmp1);
else
pccounter <= pccounter + 4;
end if;
debug_jump <= jump;
debug_branch <= branch;
debug_jumptoreg <= jumptoreg;
debug_aluzero <= aluzero;
--debug_pcnext_alu_res <= i_alu_result;
end if;
end if;
end if;
end process;
process (branch, aluzero, jump, jumptoreg)
begin
if jump = '1' then
discard <= '1';
elsif branch = '1' and aluzero ='1' then
discard <= '1';
elsif jumptoreg = '1' then
discard <= '1';
else
discard <= '0';
end if;
end process;
end;
| bsd-2-clause | 6fc7a617fb410f2f4a1c7e75955acda1 | 0.437186 | 4.661786 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/xilinx/pdi/src/pdi_dpr.vhd | 3 | 3,448 | -------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
architecture struct of pdi_dpr is
constant cActivated : std_logic := '1';
begin
abuseMacDpr : entity work.dc_dpr_be
generic map (
gDoInit => true,
WIDTH => data_a'length,
ADDRWIDTH => LOG2_NUM_WORDS
)
port map (
clkA => clock_a, clkB => clock_b,
enA => cActivated, enB => cActivated,
addrA => address_a, addrB => address_b,
diA => data_a, diB => data_b,
doA => q_a, doB => q_b,
weA => wren_a, weB => wren_b,
beA => byteena_a, beB => byteena_b
);
end architecture struct;
| gpl-2.0 | daee34359b96874153b4a29371fc64fc | 0.584687 | 4.109654 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openMAC_PHYMI.vhd | 3 | 6,117 | -------------------------------------------------------------------------------
-- Phy Management Interface for OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenMAC_MII IS
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Addr : IN std_logic_vector( 2 DOWNTO 0);
Sel : IN std_logic;
nBe : IN std_logic_vector( 1 DOWNTO 0);
nWr : IN std_logic;
Data_In : IN std_logic_vector(15 DOWNTO 0);
Data_Out : OUT std_logic_vector(15 DOWNTO 0);
Mii_Clk : OUT std_logic;
Mii_Di : IN std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic; --'1' ... Input / '0' ... Output!!!
nResetOut : OUT std_logic
);
END ENTITY OpenMAC_MII;
ARCHITECTURE struct OF OpenMAC_MII IS
SIGNAL ShiftReg : std_logic_vector (31 DOWNTO 0);
SIGNAL iMiiClk : std_logic;
SIGNAL ClkDiv : std_logic_vector (4 DOWNTO 0);
ALIAS Shift : std_logic IS ClkDiv(ClkDiv'high);
SIGNAL BitCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL BytCnt : std_logic_vector (2 DOWNTO 0);
SIGNAL Run, SrBusy, nReset : std_logic;
SIGNAL M_Dout, M_Oe : std_logic;
BEGIN
Data_Out <= x"00" & nReset & x"0" & "00" & SrBusy WHEN Addr(0) = '0' ELSE
ShiftReg(15 DOWNTO 0);
Mii_Clk <= iMiiClk;
Mii_Do <= M_Dout;
Mii_Doe <= not M_Oe;
nresetout <= nReset;
p_Mii: PROCESS (Clk, Rst)
BEGIN
IF Rst = '1' THEN
iMiiClk <= '0'; Run <= '0'; SrBusy <= '0'; M_Oe <= '1'; M_Dout <= '1'; nReset <= '0';
BitCnt <= (OTHERS => '0'); BytCnt <= (OTHERS => '0');
ShiftReg <= x"0000ABCD"; ClkDiv <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Shift = '1' THEN ClkDiv <= conv_std_logic_vector( 8, ClkDiv'high + 1);
iMiiClk <= NOT iMiiClk;
ELSE ClkDiv <= ClkDiv - 1;
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '1' AND nBE(0) = '0' THEN nReset <= Data_In(7);
END IF;
IF Sel = '1' AND nWr = '0' AND SrBusy = '0' AND Addr(1) = '0' THEN
IF Addr(0) = '0' THEN
IF nBE(1) = '0' THEN ShiftReg(31 DOWNTO 24) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg(23 DOWNTO 16) <= Data_In( 7 DOWNTO 0);
SrBusy <= '1';
END IF;
ELSE
IF nBE(1) = '0' THEN ShiftReg(15 DOWNTO 8) <= Data_In(15 DOWNTO 8);
END IF;
IF nBE(0) = '0' THEN ShiftReg( 7 DOWNTO 0) <= Data_In( 7 DOWNTO 0);
END IF;
END IF;
ELSE
IF Shift = '1' AND iMiiClk = '1' THEN
IF Run = '0' AND SrBusy = '1' THEN
Run <= '1';
BytCnt <= "111";
BitCnt <= "111";
ELSE
IF BytCnt(2) = '0' AND SrBusy = '1' THEN
M_Dout <= ShiftReg(31);
ShiftReg <= ShiftReg(30 DOWNTO 0) & Mii_Di; -- & Mii_Dio;
END IF;
BitCnt <= BitCnt - 1;
IF BitCnt = 0 THEN
BytCnt <= BytCnt - 1;
IF BytCnt = 0 THEN
SrBusy <= '0';
Run <= '0';
END IF;
END IF;
IF BytCnt = 2 AND BitCnt = 1 AND ShiftReg(31) = '0' THEN
M_Oe <= '0';
END IF;
END IF;
IF SrBusy = '0' OR Run = '0' THEN
M_Dout <= '1';
M_Oe <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS p_Mii;
END struct; | gpl-2.0 | ca9db61bfc70b8a2c039885a4cda0737 | 0.479156 | 4.155571 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_or7x16.vhd | 2 | 9,353 | -- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: gl_or7x16.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY gl_or7x16 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END gl_or7x16;
ARCHITECTURE SYN OF gl_or7x16 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (6 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
sub_wire8 <= data0x(15 DOWNTO 0);
sub_wire7 <= data1x(15 DOWNTO 0);
sub_wire6 <= data2x(15 DOWNTO 0);
sub_wire5 <= data3x(15 DOWNTO 0);
sub_wire4 <= data4x(15 DOWNTO 0);
sub_wire3 <= data5x(15 DOWNTO 0);
result <= sub_wire0(15 DOWNTO 0);
sub_wire1 <= data6x(15 DOWNTO 0);
sub_wire2(6, 0) <= sub_wire1(0);
sub_wire2(6, 1) <= sub_wire1(1);
sub_wire2(6, 2) <= sub_wire1(2);
sub_wire2(6, 3) <= sub_wire1(3);
sub_wire2(6, 4) <= sub_wire1(4);
sub_wire2(6, 5) <= sub_wire1(5);
sub_wire2(6, 6) <= sub_wire1(6);
sub_wire2(6, 7) <= sub_wire1(7);
sub_wire2(6, 8) <= sub_wire1(8);
sub_wire2(6, 9) <= sub_wire1(9);
sub_wire2(6, 10) <= sub_wire1(10);
sub_wire2(6, 11) <= sub_wire1(11);
sub_wire2(6, 12) <= sub_wire1(12);
sub_wire2(6, 13) <= sub_wire1(13);
sub_wire2(6, 14) <= sub_wire1(14);
sub_wire2(6, 15) <= sub_wire1(15);
sub_wire2(5, 0) <= sub_wire3(0);
sub_wire2(5, 1) <= sub_wire3(1);
sub_wire2(5, 2) <= sub_wire3(2);
sub_wire2(5, 3) <= sub_wire3(3);
sub_wire2(5, 4) <= sub_wire3(4);
sub_wire2(5, 5) <= sub_wire3(5);
sub_wire2(5, 6) <= sub_wire3(6);
sub_wire2(5, 7) <= sub_wire3(7);
sub_wire2(5, 8) <= sub_wire3(8);
sub_wire2(5, 9) <= sub_wire3(9);
sub_wire2(5, 10) <= sub_wire3(10);
sub_wire2(5, 11) <= sub_wire3(11);
sub_wire2(5, 12) <= sub_wire3(12);
sub_wire2(5, 13) <= sub_wire3(13);
sub_wire2(5, 14) <= sub_wire3(14);
sub_wire2(5, 15) <= sub_wire3(15);
sub_wire2(4, 0) <= sub_wire4(0);
sub_wire2(4, 1) <= sub_wire4(1);
sub_wire2(4, 2) <= sub_wire4(2);
sub_wire2(4, 3) <= sub_wire4(3);
sub_wire2(4, 4) <= sub_wire4(4);
sub_wire2(4, 5) <= sub_wire4(5);
sub_wire2(4, 6) <= sub_wire4(6);
sub_wire2(4, 7) <= sub_wire4(7);
sub_wire2(4, 8) <= sub_wire4(8);
sub_wire2(4, 9) <= sub_wire4(9);
sub_wire2(4, 10) <= sub_wire4(10);
sub_wire2(4, 11) <= sub_wire4(11);
sub_wire2(4, 12) <= sub_wire4(12);
sub_wire2(4, 13) <= sub_wire4(13);
sub_wire2(4, 14) <= sub_wire4(14);
sub_wire2(4, 15) <= sub_wire4(15);
sub_wire2(3, 0) <= sub_wire5(0);
sub_wire2(3, 1) <= sub_wire5(1);
sub_wire2(3, 2) <= sub_wire5(2);
sub_wire2(3, 3) <= sub_wire5(3);
sub_wire2(3, 4) <= sub_wire5(4);
sub_wire2(3, 5) <= sub_wire5(5);
sub_wire2(3, 6) <= sub_wire5(6);
sub_wire2(3, 7) <= sub_wire5(7);
sub_wire2(3, 8) <= sub_wire5(8);
sub_wire2(3, 9) <= sub_wire5(9);
sub_wire2(3, 10) <= sub_wire5(10);
sub_wire2(3, 11) <= sub_wire5(11);
sub_wire2(3, 12) <= sub_wire5(12);
sub_wire2(3, 13) <= sub_wire5(13);
sub_wire2(3, 14) <= sub_wire5(14);
sub_wire2(3, 15) <= sub_wire5(15);
sub_wire2(2, 0) <= sub_wire6(0);
sub_wire2(2, 1) <= sub_wire6(1);
sub_wire2(2, 2) <= sub_wire6(2);
sub_wire2(2, 3) <= sub_wire6(3);
sub_wire2(2, 4) <= sub_wire6(4);
sub_wire2(2, 5) <= sub_wire6(5);
sub_wire2(2, 6) <= sub_wire6(6);
sub_wire2(2, 7) <= sub_wire6(7);
sub_wire2(2, 8) <= sub_wire6(8);
sub_wire2(2, 9) <= sub_wire6(9);
sub_wire2(2, 10) <= sub_wire6(10);
sub_wire2(2, 11) <= sub_wire6(11);
sub_wire2(2, 12) <= sub_wire6(12);
sub_wire2(2, 13) <= sub_wire6(13);
sub_wire2(2, 14) <= sub_wire6(14);
sub_wire2(2, 15) <= sub_wire6(15);
sub_wire2(1, 0) <= sub_wire7(0);
sub_wire2(1, 1) <= sub_wire7(1);
sub_wire2(1, 2) <= sub_wire7(2);
sub_wire2(1, 3) <= sub_wire7(3);
sub_wire2(1, 4) <= sub_wire7(4);
sub_wire2(1, 5) <= sub_wire7(5);
sub_wire2(1, 6) <= sub_wire7(6);
sub_wire2(1, 7) <= sub_wire7(7);
sub_wire2(1, 8) <= sub_wire7(8);
sub_wire2(1, 9) <= sub_wire7(9);
sub_wire2(1, 10) <= sub_wire7(10);
sub_wire2(1, 11) <= sub_wire7(11);
sub_wire2(1, 12) <= sub_wire7(12);
sub_wire2(1, 13) <= sub_wire7(13);
sub_wire2(1, 14) <= sub_wire7(14);
sub_wire2(1, 15) <= sub_wire7(15);
sub_wire2(0, 0) <= sub_wire8(0);
sub_wire2(0, 1) <= sub_wire8(1);
sub_wire2(0, 2) <= sub_wire8(2);
sub_wire2(0, 3) <= sub_wire8(3);
sub_wire2(0, 4) <= sub_wire8(4);
sub_wire2(0, 5) <= sub_wire8(5);
sub_wire2(0, 6) <= sub_wire8(6);
sub_wire2(0, 7) <= sub_wire8(7);
sub_wire2(0, 8) <= sub_wire8(8);
sub_wire2(0, 9) <= sub_wire8(9);
sub_wire2(0, 10) <= sub_wire8(10);
sub_wire2(0, 11) <= sub_wire8(11);
sub_wire2(0, 12) <= sub_wire8(12);
sub_wire2(0, 13) <= sub_wire8(13);
sub_wire2(0, 14) <= sub_wire8(14);
sub_wire2(0, 15) <= sub_wire8(15);
lpm_or_component : lpm_or
GENERIC MAP (
lpm_size => 7,
lpm_type => "LPM_OR",
lpm_width => 16
)
PORT MAP (
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "16"
-- Retrieval info: PRIVATE: nInput NUMERIC "7"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "7"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or7x16.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or7x16.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or7x16.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or7x16.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_or7x16_inst.vhd TRUE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 179359f5d6c31e3b1018b8f4f783b9db | 0.595638 | 2.461316 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part2/part2.vhd | 1 | 2,172 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part2 IS
PORT(
BUTTONS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clk_in : IN STD_LOGIC
);
END part2;
ARCHITECTURE Behaviour of part2 IS
SIGNAL s_m: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL HOLD_LOW, s_z : STD_LOGIC;
SIGNAL s_ao, s_ai: STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL HEX_0, HEX_1, BLANK: STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT circuita PORT ( INPUT : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END COMPONENT;
COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT circuitb PORT ( SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT comparator PORT ( INPUT : IN STD_LOGIC_VECTOR (3 DOWNTO 0); OUTPUT : OUT STD_LOGIC ); END COMPONENT;
COMPONENT mplex PORT ( V : IN STD_LOGIC_VECTOR (1 DOWNTO 0); M : OUT STD_LOGIC; Z : IN STD_LOGIC ); END COMPONENT;
COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT;
BEGIN
HOLD_LOW <='0';
BLANK <= "1111111";
S0 : segseven PORT MAP (SW=>s_m, LEDSEG=>HEX_0);
S1 : circuitb PORT MAP (SW=>s_z, LEDSEG=>HEX_1);
DE1: DE1_disp PORT MAP (HEX0=>HEX_0, HEX1=>HEX_1, HEX2=>BLANK, HEX3=>BLANK, clk=>clk_in,HEX=>LED,DISPn=>DISP);
C0 : comparator PORT MAP (INPUT=>BUTTONS,OUTPUT=>s_z);
C1 : circuita PORT MAP (INPUT(2)=>BUTTONS(2),INPUT(1)=>BUTTONS(1),INPUT(0)=>BUTTONS(0),OUTPUT=>s_ao);
M3 : mplex PORT MAP (V(0) =>BUTTONS(3), V(1)=> HOLD_LOW, M=>s_m(3), Z=>s_z);
M2 : mplex PORT MAP (V(0) =>BUTTONS(2), V(1)=> s_ao(2), M=>s_m(2), Z=>s_z);
M1 : mplex PORT MAP (V(0) =>BUTTONS(1), V(1)=> s_ao(1), M=>s_m(1), Z=>s_z);
M0 : mplex PORT MAP (V(0) =>BUTTONS(0), V(1)=> s_ao(0), M=>s_m(0), Z=>s_z);
END Behaviour; | unlicense | 9b8d1c2e00c25d0c95807aacc473003f | 0.603591 | 2.850394 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/PriorEncoder1.vhd | 2 | 739 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PriorEncode is
port (IN_Xor : in std_logic_vector(7 downto 0) ;
OUT_sel : out std_logic_vector(2 downto 0) );
end PriorEncode;
architecture Behaviorial of PriorEncode is
begin
OUT_sel <= "000" when IN_Xor(0) ="00000001" else
"001" when IN_Xor ="00000010" else
"010" when IN_Xor ="00000100" else
"011" when IN_Xor ="00001000" else
"100" when IN_Xor ="00010000" else
"101" when IN_Xor ="00100000" else
"110" when IN_Xor ="01000000" else
"111" when IN_Xor ="10000000" ;
end Behaviorial;
| unlicense | 5db3d02a66bb50d7dd5542224f845931 | 0.548038 | 3.604878 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openMAC_Ethernet.vhd | 3 | 38,357 | -------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
genPulse2ndCmpTimer_g : boolean := true;
pulseWidth2ndCmpTimer_g : integer := 9;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0) := (others => '0');
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Rd_Len : out std_logic_vector(11 downto 0);
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : BOOLEAN := false;
genPulse2ndCmpTimer_g : BOOLEAN := false;
mac_time_width_g : INTEGER := 32;
pulseWidth2ndCmpTimer_g : INTEGER := 9
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal dma_rd_len : std_logic_vector (11 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
signal t_readdata_s : std_logic_vector (31 downto 0);
signal t_writedata_s : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
--endian conversion
t_writedata_s <= t_writedata(7 downto 0) & t_writedata(15 downto 8) &
t_writedata(23 downto 16) & t_writedata(31 downto 24) when endian_g = "big" else
t_writedata;
t_readdata <= t_readdata_s(7 downto 0) & t_readdata_s(15 downto 8) &
t_readdata_s(23 downto 16) & t_readdata_s(31 downto 24) when endian_g = "big" else
t_readdata_s;
--assign address bus and be to openMA
mac_addr <= s_address(9 downto 0);
mac_be <= s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" and s_byteenable /= "11" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else --and s_byteenable = "11"
smi_dout when smi_sel = '1' and endian_g = "little" else
smi_dout when smi_sel = '1' and endian_g = "big" and s_byteenable /= "11" else
smi_dout(7 downto 0) & smi_dout(15 downto 8) when smi_sel = '1' and endian_g = "big" else --and s_byteenable = "11"
irqTable when irqTable_sel = '1' and endian_g = "little" else
irqTable(7 downto 0) & irqTable(15 downto 8) when irqTable_sel = '1' and endian_g = "big" else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' and endian_g = "little" else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' and endian_g = "big" else
(others => '0');
--assign writedata to input data
mac_din <= s_writedata when endian_g = "little" or (endian_g = "big" and s_byteenable /= "11") else
s_writedata(7 downto 0) & s_writedata(15 downto 8); --when endian_g = "big" and s_byteenable = "11"
smi_din <= s_writedata when endian_g = "little" or (endian_g = "big" and s_byteenable /= "11") else
s_writedata(7 downto 0) & s_writedata(15 downto 8); --when endian_g = "big" and s_byteenable = "11"
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
genPulse2ndCmpTimer_g => genPulse2ndCmpTimer_g,
mac_time_width_g => 32,
pulseWidth2ndCmpTimer_g => pulseWidth2ndCmpTimer_g
)
port map(
addr => t_address,
clk => clk,
din => t_writedata_s,
dout => t_readdata_s,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Rd_Len => dma_rd_len,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <= dma_dout;
dma_din <= dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <= dma_addr(iPktBufSizeLog2_g-1 downto 1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
| gpl-2.0 | 3f3c229b372b42ccbf34f818f1bc9051 | 0.588106 | 3.094554 | false | false | false | false |
Alix82/mip32vhdl | alu.vhd | 1 | 15,179 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mips_constants.all;
Entity alu is
port(clk : in std_logic;
reset : in std_logic;
pcF : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(5 downto 0);
func : in std_logic_vector(5 downto 0);
shamt : in std_logic_vector(4 downto 0);
InstReg1 : in std_logic_vector(4 downto 0);
InstReg2 : in std_logic_vector(4 downto 0);
InstReg3 : in std_logic_vector(4 downto 0);
instructionExt : in std_logic_vector(31 downto 0);
control : in std_logic_vector(11 downto 0);
fetch : in std_logic;
inwriteregdata : in std_logic_vector(31 downto 0);
inwritereg : in std_logic;
memtoreg : out std_logic;
memread : out std_logic;
memwrite : out std_logic;
outZero : out std_logic;
outAluResult : out std_logic_vector(31 downto 0);
outwriteData : out std_logic_vector(31 downto 0);
alu_pause : out std_logic
);
End alu;
Architecture rtl of alu is
component mult is
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component mult;
type register_array is array(0 to 31) of std_logic_vector(31 downto 0);
signal register_memory: register_array := (
X"00000000", -- $zero 0
X"00000000", -- $at Reserved for Assembler 1
X"00000000", -- $v0 First return value 2
X"00000000", -- $v1 Second return value 3
X"00000000", -- $a0 Function arguments 4
X"00000000", -- $a1 ... 5
X"00000000", -- $a2 ... 6
X"00000000", -- $a3 ... 7
X"00000000", -- $t0 Temp Registers 8
X"00000000", -- $t1 9
X"00000000", -- $t2 10
X"00000000", -- $t3 11
X"00000000", -- $t4 12
X"00000000", -- $t5 13
X"00000000", -- $t6 14
X"00000000", -- $t7 15
X"00000000", -- $s0 Save Registers 16
X"00000000", -- $s1 17
X"00000000", -- $s2 18
X"00000000", -- $s3 19
X"00000000", -- $s4 20
X"00000000", -- $s5 21
X"00000000", -- $s6 22
X"00000000", -- $s7 23
X"00000000", -- $t8 Temp Registers 24
X"00000000", -- $t9 25
X"00000000", -- $k0 Reserved for OS 26
X"00000000", -- $k1 Reserved for OS 27
X"00000000", -- $gp Global Pointer 28
X"7FFFFFFF", -- $sp Stack Pointer 29
X"00000000", -- $fp Frame pointer 30
X"00000000");-- $ra Return address 31
signal alu_actual_func : std_logic_vector(5 downto 0) := (others => '0');
signal alu_actual_op : std_logic_vector(5 downto 0) := (others => '0');
signal debug_nreg1 : std_logic_vector(4 downto 0) := (others => '0');
signal debug_nreg2 : std_logic_vector(4 downto 0) := (others => '0');
signal debug_reg1data : std_logic_vector(31 downto 0) := (others => '0');
signal debug_reg2data : std_logic_vector(31 downto 0) := (others => '0');
signal debug_write_res : std_logic_vector(31 downto 0) := (others => '0');
signal debug_write_reg : std_logic_vector(4 downto 0) := (others => '0');
signal debug_control : std_logic_vector(11 downto 0) := (others => '0');
signal debug_alu_pc : std_logic_vector(31 downto 0) := (others => '0');
signal req_bit : std_logic := '0';
signal alu_counter : integer := 0;
signal write_reg_save : std_logic_vector(4 downto 0) := (others => '0');
signal alu_a, alu_b : std_logic_vector(31 downto 0):= (others => '0');
signal alu_mult_func : mult_function_type := (others => '0');
signal alu_mult_res : std_logic_vector(31 downto 0):= (others => '0');
signal alu_mult_pause : std_logic := '0';
begin
MULT0: mult port map (clk, reset, alu_a, alu_b, alu_mult_func, alu_mult_res, alu_mult_pause);
alu_pause <= alu_mult_pause;
process(clk)
Variable Res : std_logic_vector (31 downto 0);
Variable inReg1 : std_logic_vector (31 downto 0);
Variable inReg2 : std_logic_vector (31 downto 0);
Variable Res64 : std_logic_vector (63 downto 0);
Variable Zero : std_logic;
Variable Write_Reg : std_logic_vector(4 downto 0);
Variable Read1 : std_logic_vector(4 downto 0);
Variable Read2 : std_logic_vector(4 downto 0);
begin
if rising_edge(clk) then
debug_alu_pc <= pcF;
if inwritereg = '1' then
register_memory(to_integer(unsigned(write_reg_save))) <= inwriteregdata;
end if;
if alu_mult_pause = '1' then
alu_mult_func <= MULT_NOTHING;
elsif fetch = '1' then
Read1 := "00000";
Read2 := "00000";
inReg1 := X"00000000";
inReg2 := X"00000000";
debug_control <= control;
inReg1 := inwriteregdata;
Read1 := InstReg1;
if inwritereg = '1' and Read1 = write_reg_save then
inReg1 := inwriteregdata;
else
inReg1 := register_memory(to_integer(unsigned(Read1)));
end if;
if control(REG2OPERATION) = '0' then
if control(ALUSRC) = '1' then
inReg2 := instructionExt;
else
Read2 := InstReg2;
if inwritereg = '1' and Read2 = write_reg_save then
inReg2 := inwriteregdata;
else
inReg2 := register_memory(to_integer(unsigned(Read2)));
end if;
end if;
else
inReg2(4 downto 0) := InstReg2;
inReg2(31 downto 5) := ( others => '0');
end if;
--inReg2 := inReg1;
Res := "00000000000000000000000000000000";
Res64 := "0000000000000000000000000000000000000000000000000000000000000000";
Zero := '0';
debug_nreg1 <= Read1;
debug_nreg2 <= Read2;
debug_reg1data <= inReg1;
debug_reg2data <= inReg2;
alu_actual_func <= func;
alu_actual_op <= opcode;
case opcode is
when "000000" =>
case func is
when "001000" => Res := inReg1;
-- R-TYPE
when "100000" => Res := inReg1 + inReg2; -- add FIXME_ Trap
when "100001" => Res := inReg1 + inReg2; -- addu
when "100100" => Res := inReg1 and inReg2; -- and
when "100010" => Res := inReg1 - inReg2; -- sub
when "100011" => Res := inReg1 - inReg2; -- subu
when "100110" => Res := inReg1 xor inReg2;
-- SHIFTS
-- SLL
when "000000" => Res(31 downto to_integer(unsigned(shamt))) := inReg2(31 - to_integer(unsigned(shamt)) downto 0);
-- SRL
when "000010" => Res(31 - to_integer(unsigned(shamt)) downto 0) := inReg2(31 downto to_integer(unsigned(shamt)));
-- SLLV
when "000100" => Res(31 downto to_integer(unsigned(inReg1))) := inReg2(31 - to_integer(unsigned(inReg1)) downto 0);
-- SRLV
when "000110" => Res(31 - to_integer(unsigned(inReg1)) downto 0) := inReg2(31 downto to_integer(unsigned(inReg1)));
-- SRA
when "000011" =>
Res(31 - to_integer(unsigned(shamt)) downto 0) := inReg2(31 downto to_integer(unsigned(shamt)));
Res(0) := inReg2(31);
when "011011" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_DIVIDE;
when "011010" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_SIGNED_DIVIDE;
when "011000" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_SIGNED_MULT;
when "011001" =>
alu_a <= inReg1;
alu_b <= inReg2;
alu_mult_func <= MULT_MULT;
when "010000" =>
alu_mult_func <= MULT_READ_HI;
Res := alu_mult_res;
when "010010" =>
alu_mult_func <= MULT_READ_LO;
Res := alu_mult_res;
when others => null;
end case;
-- I-TYPE
when "001000" => Res := inReg1 + inReg2; -- ADDI
when "001001" => Res := inReg1 + inReg2; -- ADDIU
when "101011" => Res := inReg1 + inReg2; -- SW
when "100011" => Res := inReg1 + inReg2; -- LW
when "101000" => Res := inReg1 + inReg2; -- SB
when "100000" => Res := inReg1 + inReg2; -- LB
when "001110" => Res := inReg1 xor inReg2; -- XORI
when "001101" => Res := inReg1 or inReg2; -- ORI
when "001111" => Res(31 downto 16) := inReg2(15 downto 0); -- LUI
--- Branch
when "000100" => -- BEQ
if inReg1 = inReg2 then
Zero := '1';
else
Zero := '0';
end if;
when "000101" => -- BNE
if inReg1 = inReg2 then
Zero := '0';
else
Zero := '1';
end if;
--- inReg2 contains the branch operation to be performed
when "000001" => -- BGEZ/BGEZAL
case inReg2(3 downto 0) is
when "0001" => -- This includes 0 0001(BGEZ) and 1 0001(BGEZAL)
if inReg1 >= 0 then
Zero := '1';
else
Zero := '0';
end if;
when "0000" => -- This includes 1 0000(BLTZAL) and 0 0001(BLTZ)
if inReg1 < 0 then
Zero := '1';
else
Zero := '0';
end if;
when others => null;
end case;
--- BGTZ
when "000111" =>
if inReg1 > 0 then
Zero := '1';
else
Zero := '0';
end if;
--- BLEZ
when "000110" =>
if inReg1 <= 0 then
Zero := '1';
else
Zero := '0';
end if;
when others => null;
end case;
if control(MEM_TO_REG) = '0' then
if control(REG_WRITE) = '1' then
Write_Reg := InstReg2;
debug_write_res <= Res;
debug_write_reg <= Write_Reg;
register_memory(to_integer(unsigned(Write_Reg))) <= Res;
end if;
memtoreg <= '0';
else
memtoreg <= '1';
end if;
memread <= control(MEM_READ);
memwrite <= control(MEM_WRITE);
if control(MEM_READ) = '1' then
if control(REG_DEST) = '0' then
write_reg_save <= InstReg2;
else
write_reg_save <= InstReg3;
end if;
end if;
if control(MEM_WRITE) = '1' then
Read2 := InstReg2;
inReg2 := register_memory(to_integer(unsigned(Read2)));
outwriteData <= inReg2;
else
outwriteData <= (others => '0');
end if;
if control(LINK_RET) = '1' then
register_memory(31) <= pcF + 8;
end if;
outAluResult <= Res(31 downto 0);
outZero <= Zero;
else
memtoreg <= '0';
memread <= '0';
memwrite <= '0';
outZero <= '0';
outAluResult <= X"00000000";
alu_actual_func <= (others => '0');
end if;
end if;
end process;
end;
| bsd-2-clause | ea2af179e491244727114e7177e64633 | 0.386784 | 4.840242 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/gl_dff5.vhd | 2 | 3,893 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff5.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_dff5 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END gl_dff5;
ARCHITECTURE SYN OF gl_dff5 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 5
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 6a7cf99a0faa0e36ca5a4f4b65211d3e | 0.636527 | 3.61803 | false | false | false | false |
scottlbaker/PDP11-SOC | src/uart.vhd | 1 | 32,969 |
--======================================================================
-- uart.vhd :: Generic UART
--
-- no hardware handshake
-- 16-deep FIFO
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity UART is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
BYTE_SEL : in std_logic; -- byte select
REG_SEL : in std_logic_vector( 1 downto 0); -- register select
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector( 7 downto 0); -- read data
RX_IRQ : out std_logic; -- RX interrupt request
TX_IRQ : out std_logic; -- TX interrupt request
RXD : in std_logic; -- RX serial data
TXD : out std_logic; -- TX serial data
RESET : in std_logic; -- system reset
RDV : in std_logic; -- read data valid
FCLK : in std_logic -- fast clock
);
end UART;
architecture BEHAVIORAL of UART is
--=================================================================
-- Signal definitions
--=================================================================
signal PARITY_MODE : std_logic_vector(1 downto 0);
signal FRAMING_ERR : std_logic;
signal PARITY_ERR : std_logic;
signal OVERRUN_ERR : std_logic;
signal STATUS_CLR : std_logic; -- clear status register
signal TX_STATE : std_logic_vector(3 downto 0); -- TX state
signal TX_NSTATE : std_logic_vector(3 downto 0); -- TX next state
signal TX_SHIFT_REG : std_logic_vector(7 downto 0); -- TX shift reg
signal TX_COUNT : std_logic_vector(3 downto 0); -- TX shift counter
signal TX_FIFO_DATA : std_logic_vector(7 downto 0); -- TX FIFO out
signal TX_FIFO_IN : std_logic_vector(7 downto 0); -- TX FIFO in
signal TX_FIFO_OVFL : std_logic; -- TX FIFO overflow flag
signal TX_FIFO_FULL : std_logic; -- TX FIFO full flag
signal TX_FIFO_EMPTY : std_logic; -- TX FIFO empty flag
signal TX_FIFO_OP : std_logic; -- TX FIFO 1==push 0== pop
signal TX_FIFO_CKEN : std_logic; -- TX FIFO clock enable
signal TX_SHIFT_LD : std_logic; -- TX shift reg load
signal TX_EN : std_logic; -- TX enabled
signal TX_CLK_EN : std_logic; -- TX clock enable
signal TX_PARITY : std_logic; -- TX parity
signal TX_SHIFT_EN : std_logic; -- TX shift reg enable
signal TX_SHIFT_EN1 : std_logic; -- TX shift reg enable delayed
signal TX_BCLK : std_logic; -- TX baud clock
signal TX_BCLK_DLY : std_logic; -- TX baud clock delayed
signal RX_STATE : std_logic_vector(3 downto 0); -- RX state
signal RX_NSTATE : std_logic_vector(3 downto 0); -- RX next state
signal RX_COUNT : std_logic_vector(2 downto 0); -- RX shift counter
signal RX_SHIFT_REG : std_logic_vector(7 downto 0); -- RX shift register
signal RX_FIFO_DATA : std_logic_vector(7 downto 0); -- RX FIFO data
signal RX_FIFO_OVFL : std_logic; -- RX FIFO overflow flag
signal RX_FIFO_STOP : std_logic; -- RX FIFO stop flag
signal RX_FIFO_FULL : std_logic; -- RX FIFO full flag
signal RX_FIFO_EMPTY : std_logic; -- RX FIFO empty flag
signal RX_FIFO_OP : std_logic; -- RX FIFO 1==push 0== pop
signal RX_FIFO_CKEN : std_logic; -- RX FIFO clock enable
signal RX_EN : std_logic; -- RX enable
signal RX_ACCEPT : std_logic; -- receiver has accepted frame
signal RXD_SYNC : std_logic; -- synchronize received data
signal RXD_SYNC1 : std_logic; -- synchronize received data
signal RX_CLK_EN : std_logic; -- receiver clock enable
signal RX_SHIFT_EN : std_logic; -- receiver shift enable
signal RX_PARITY : std_logic; -- calculated receiver parity
signal RX_START : std_logic; -- testing start bit
signal RX_BCLK : std_logic; -- receiver baud clock
signal RX_BCLK_DLY : std_logic; -- receiver baud clock delayed
signal RXDI : std_logic; -- receive data
signal TXDI : std_logic; -- transmit data
signal PRELOAD : std_logic_vector(15 downto 0); -- baud rate preload
signal RX_BAUD : std_logic_vector(15 downto 0); -- RX baud counter
signal TX_BAUD : std_logic_vector(15 downto 0); -- TX baud counter
-- Registers
signal CNTL_REG : std_logic_vector( 3 downto 0); -- control
signal BRSR_REG : std_logic_vector(15 downto 0); -- baud rate select
signal STAT_REG : std_logic_vector( 7 downto 0); -- status
signal MASK_REG : std_logic_vector( 1 downto 0); -- interrupt mask
-- Register addresses
constant CNTL_ADDR : std_logic_vector(1 downto 0) := "00"; -- control
constant STAT_ADDR : std_logic_vector(1 downto 0) := "00"; -- status
constant BRSR_ADDR : std_logic_vector(1 downto 0) := "01"; -- baud rate
constant MASK_ADDR : std_logic_vector(1 downto 0) := "10"; -- irq mask
constant HOLD_ADDR : std_logic_vector(1 downto 0) := "11"; -- hold reg
-- parity modes
constant NONE : std_logic_vector(1 downto 0) := "00";
constant EVEN : std_logic_vector(1 downto 0) := "01";
constant ODD : std_logic_vector(1 downto 0) := "10";
-- State Constants
constant IDLE : std_logic_vector(3 downto 0) := "1000";
constant LOAD : std_logic_vector(3 downto 0) := "0010";
constant D7 : std_logic_vector(3 downto 0) := "0010";
constant SHIFT : std_logic_vector(3 downto 0) := "0100";
constant PRTY : std_logic_vector(3 downto 0) := "0000";
constant STOP : std_logic_vector(3 downto 0) := "0001";
-- Misc
constant CKDIV_TC : std_logic_vector(9 downto 0) := "0000000000";
constant TX_INIT : std_logic_vector(3 downto 0) := "0011";
constant TX_TC : std_logic_vector(3 downto 0) := "0000";
constant RX_INIT : std_logic_vector(2 downto 0) := "000";
constant RX_TC : std_logic_vector(2 downto 0) := "100";
--================================================================
-- component definitions
--================================================================
component FIFO
port (
FIFO_OUT : out std_logic_vector(7 downto 0);
FIFO_IN : in std_logic_vector(7 downto 0);
OVFL : out std_logic; -- overflow
LAST : out std_logic; -- nearly full
EMPTY : out std_logic; -- empty
FIFO_OP : in std_logic; -- 1==push 0==pop
CKEN : in std_logic; -- clock enable
CLK : in std_logic; -- clock
RESET : in std_logic -- Reset
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
--=============================================
-- Register Writes
--=============================================
REGISTER_WRITES:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
STATUS_CLR <= '0';
if ((CS = '1') and (WE = '1')) then
case REG_SEL is
when CNTL_ADDR =>
if (WR_DATA(4) = '1') then
STATUS_CLR <= '1';
else
CNTL_REG <= WR_DATA(3 downto 0);
end if;
when BRSR_ADDR =>
BRSR_REG <= WR_DATA;
when MASK_ADDR =>
MASK_REG <= WR_DATA(1 downto 0);
when others =>
end case;
end if;
-- reset state
if (RESET = '1') then
CNTL_REG <= (others => '0');
BRSR_REG <= (others => '0');
MASK_REG <= (others => '0');
STATUS_CLR <= '1';
end if;
end if;
end process;
--=============================================
-- TX FIFO Control
--=============================================
TX_FIFO_CONTROL:
process (CS, WE, REG_SEL, TX_EN, TX_SHIFT_LD)
begin
TX_FIFO_CKEN <= '0';
TX_FIFO_OP <= '0';
-- push tx FIFO
if ((CS = '1') and (WE = '1') and (REG_SEL = HOLD_ADDR)) then
if (TX_EN = '1') then
TX_FIFO_OP <= '1';
TX_FIFO_CKEN <= '1';
end if;
end if;
-- pop TX FIFO
if (TX_SHIFT_LD = '1') then
TX_FIFO_CKEN <= '1';
end if;
end process;
--=============================================
-- Status Register
--=============================================
STATUS_REGISTER:
process (FRAMING_ERR, PARITY_ERR, OVERRUN_ERR,
TX_FIFO_FULL, TX_FIFO_EMPTY, RX_FIFO_FULL, RX_FIFO_EMPTY)
begin
STAT_REG(7) <= '0';
STAT_REG(6) <= FRAMING_ERR;
STAT_REG(5) <= PARITY_ERR;
STAT_REG(4) <= OVERRUN_ERR;
STAT_REG(3) <= TX_FIFO_EMPTY; -- TX FIFO is empty
STAT_REG(2) <= not TX_FIFO_FULL; -- TX FIFO is not full
STAT_REG(1) <= RX_FIFO_FULL; -- RX FIFO is full
STAT_REG(0) <= not RX_FIFO_EMPTY; -- RX FIFO is not empty
end process;
--=============================================
-- Control Register Outputs
--=============================================
PRELOAD <= BRSR_REG; -- baud rate select constant
PARITY_MODE <= CNTL_REG(3 downto 2); -- parity mode (even/odd/none)
RX_EN <= CNTL_REG(1); -- receiver enable
TX_EN <= CNTL_REG(0); -- transmit enable
--=============================================
-- Register Reads
--=============================================
REGISTER_READS:
process (CS, REG_SEL, RX_FIFO_DATA, STAT_REG)
begin
RD_DATA <= RX_FIFO_DATA;
if (CS = '1') then
case REG_SEL is
when STAT_ADDR => -- status register
RD_DATA <= STAT_REG;
when others =>
end case;
end if;
end process;
--=========================================================================
-- RX Interrupt Generation Logic
--
-- Generated RX_IRQ if: Data is ready in the receiver reg
-- and the RX IRQ is not masked.
--=========================================================================
RX_IRQ_GENERATION:
process (RX_FIFO_FULL, MASK_REG)
begin
RX_IRQ <= '0';
if ((RX_FIFO_FULL = '1') and (MASK_REG(0)= '1')) then
RX_IRQ <= '1';
end if;
end process;
--=========================================================================
-- TX Interrupt Generation Logic
--
-- Generated TX_IRQ if: The transmitter is empty and the TX IRQ
-- is not masked and the transmitter is enabled
-- Note: The transmit interrupt can only be cleared by writing new data
-- to the transmit hold register or by disabling the transmitter.
--=========================================================================
TX_IRQ_GENERATION:
process (TX_FIFO_EMPTY, MASK_REG, TX_EN)
begin
TX_IRQ <= '0';
if ((TX_FIFO_EMPTY = '1') and (MASK_REG(1) = '1') and
(TX_EN = '1')) then
TX_IRQ <= '1';
end if;
end process;
TXD <= TXDI; -- transmit data from tx shift reg
RXDI <= RXD; -- receive data from pin
--================================================
-- Transmit state machine
--================================================
TRANSMIT_STATE_MACHINE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (TX_CLK_EN = '1') then
TX_STATE <= TX_NSTATE;
end if;
-- reset state
if (RESET = '1') then
TX_STATE <= IDLE;
end if;
end if;
end process;
--================================================
-- Transmit shift counter
--
-- 0) 0011 3) 1011 6) 1100
-- 1) 0110 4) 0111 7) 1000
-- 2) 1101 5) 1110 8) 0000 <- TC
--
--================================================
TRANSMIT_SHIFT_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((TX_STATE = SHIFT) and (TX_CLK_EN = '1')) then
TX_COUNT <= TX_COUNT(2 downto 0) &
not(TX_COUNT(0) xor TX_COUNT(3));
end if;
if (TX_STATE = IDLE) then
TX_COUNT <= TX_INIT;
end if;
end if;
end process;
--================================================
-- Transmit state machine next state logic
--================================================
TRANSMIT_NEXT_STATE_LOGIC:
process (TX_STATE, TX_SHIFT_EN, TX_CLK_EN,
TX_COUNT, PARITY_MODE)
begin
case TX_STATE is
when IDLE =>
-- detect the leading edge of the transmit shift enable
if (TX_SHIFT_EN = '1') then
TX_NSTATE <= LOAD;
else
TX_NSTATE <= IDLE;
end if;
when LOAD =>
-- detect the first transmit clock enable
if (TX_CLK_EN = '1') then
TX_NSTATE <= SHIFT;
else
TX_NSTATE <= LOAD;
end if;
when SHIFT =>
if ((TX_CLK_EN = '1') and (TX_COUNT = TX_TC)) then
if (PARITY_MODE = NONE) then
TX_NSTATE <= STOP;
else
TX_NSTATE <= PRTY;
end if;
else
TX_NSTATE <= SHIFT;
end if;
when PRTY =>
if (TX_CLK_EN = '1') then
TX_NSTATE <= STOP;
else
TX_NSTATE <= PRTY;
end if;
when STOP =>
if (TX_CLK_EN = '1') then
TX_NSTATE <= IDLE;
else
TX_NSTATE <= STOP;
end if;
when others =>
TX_NSTATE <= IDLE;
end case;
end process;
--================================================
-- Transmit Shift Enable
--================================================
TRANSMIT_SHIFT_ENABLE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- TX_SHIFT_EN is active if:
-- the previous shift has finished (TX_STATE=IDLE) and
-- the FIFO has data (TX_FIFO_EMPTY=0) and
-- the transmitter is enabled (TX_EN=1)
if ((TX_STATE = IDLE) and (TX_FIFO_EMPTY = '0') and
(TX_EN = '1')) then
TX_SHIFT_EN <= '1';
elsif ((TX_STATE = STOP) and (TX_CLK_EN = '1')) then
TX_SHIFT_EN <= '0';
end if;
-- delay for edge detection
TX_SHIFT_EN1 <= TX_SHIFT_EN;
-- reset state
if ((RESET = '1') or (TX_EN = '0')) then
TX_SHIFT_EN <= '0';
TX_SHIFT_EN1 <= '0';
end if;
end if;
end process;
--=============================================
-- Transmit baud-rate clock divider
--=============================================
TRANSMIT_BAUD_CLK_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- delayed baud clock for edge detection
TX_BCLK_DLY <= TX_BCLK;
if (TX_SHIFT_EN = '1') then
-- count
TX_BAUD <= TX_BAUD(14 downto 0) &
not(TX_BAUD(2) xor TX_BAUD(15));
-- reload at terminal count
if (TX_BAUD = CKDIV_TC) then
TX_BAUD <= PRELOAD;
TX_BCLK <= not TX_BCLK;
end if;
end if;
-- load the initial count on reset or
-- when we start to send a new frame
if ((RESET = '1') or
((TX_SHIFT_EN = '1') and (TX_SHIFT_EN1 = '0'))) then
TX_BAUD <= PRELOAD;
TX_BCLK <= '0';
end if;
end if;
end process;
--==========================================
-- Transmit Clock Enable
--==========================================
TRANSMIT_CLOCK_ENABLE:
process (TX_BCLK, TX_BCLK_DLY)
begin
if ((TX_BCLK = '0') and (TX_BCLK_DLY = '1')) then
-- center TX clock in the middle of the data
-- at the falling edge of TX_BCLK
TX_CLK_EN <= '1';
else
TX_CLK_EN <= '0';
end if;
end process;
--==========================================
-- Transmit Parity Generation
--==========================================
TRANSMITTER_PARITY_GENERATION:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (TX_STATE = IDLE) then
-- for odd parity init TX_PARITY to 1
-- for even parity init TX_PARITY to 0
TX_PARITY <= PARITY_MODE(0);
end if;
if ((TX_CLK_EN = '1') and (TX_STATE = SHIFT)) then
-- calculate parity during shift
TX_PARITY <= TX_PARITY xor TX_SHIFT_REG(0);
end if;
end if;
end process;
--==========================================
-- Transmit Shift Register
--==========================================
TRANSMIT_SHIFT_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
TX_SHIFT_LD <= '0';
-- load from the hold register
if (TX_SHIFT_EN = '1' and TX_SHIFT_EN1 = '0') then
TX_SHIFT_REG <= TX_FIFO_DATA;
TX_SHIFT_LD <= '1';
end if;
-- shift
if ((TX_CLK_EN = '1') and (TX_STATE = SHIFT)) then
TX_SHIFT_REG <= '1' & TX_SHIFT_REG(7 downto 1);
end if;
-- reset state
if (RESET = '1') then
TX_SHIFT_REG <= (others => '0');
end if;
end if;
end process;
--==========================================
-- Transmit Data
--==========================================
TRANSMIT_DATA:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (TX_CLK_EN = '1') then
TXDI <= '1'; -- mark bit
if (TX_STATE = LOAD) then
TXDI <= '0'; -- start bit
end if;
if (TX_STATE = SHIFT) then
TXDI <= TX_SHIFT_REG(0); -- data bit
end if;
if (TX_NSTATE = PRTY) then
TXDI <= TX_PARITY; -- parity bit
end if;
end if;
-- reset state
if (RESET = '1') then
TXDI <= '1';
end if;
end if;
end process;
--================================================
-- Receiver shift enable
--================================================
RECEIVER_SHIFT_ENABLE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- RX_SHIFT_EN is active if the start bit is OK
-- and the shift register is not full.
-- It is only hi during data bits
if ((RX_STATE = IDLE) and (RX_START = '1') and
(RX_FIFO_STOP = '0')) then
RX_SHIFT_EN <= '1';
end if;
-- clear the RX shift enable
if ((RX_CLK_EN = '1') and (RX_STATE = D7)) then
RX_SHIFT_EN <= '0';
end if;
-- reset state
if ((RESET = '1') or (RX_EN = '0')) then
RX_SHIFT_EN <= '0';
end if;
end if;
end process;
--=============================================
-- Receiver baud-rate clock divider
--=============================================
RECEIVER_BAUD_CLK_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- delayed baud clock for edge detection
RX_BCLK_DLY <= RX_BCLK;
if ((RX_SHIFT_EN = '1') or (RX_STATE /= IDLE)) then
-- count
RX_BAUD <= RX_BAUD(14 downto 0) &
not(RX_BAUD(2) xor RX_BAUD(15));
-- reload at terminal count
if (RX_BAUD = CKDIV_TC) then
RX_BAUD <= PRELOAD;
RX_BCLK <= not RX_BCLK;
end if;
end if;
-- load the initial count on Reset or
-- when we start to receive a new frame
if ((RESET = '1') or (RX_START = '1')) then
RX_BAUD <= PRELOAD;
RX_BCLK <= '0';
end if;
end if;
end process;
--==========================================
-- Receiver Clock Enable
--==========================================
RECEIVER_CLOCK_ENABLE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((RX_BCLK_DLY = '0') and (RX_BCLK = '1')) then
-- center RX clock in the middle of the data
-- at the rising edge of RX_BCLK
RX_CLK_EN <= '1';
else
RX_CLK_EN <= '0';
end if;
end if;
end process;
--==========================================
-- Receive start of frame
--==========================================
RECEIVE_START_OF_FRAME:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- find the falling edge of the start bit
if ((RX_STATE = IDLE) and
((RXD_SYNC1 = '0') and (RXD_SYNC = '1'))) then
RX_START <= '1';
else
RX_START <= '0';
end if;
-- reset state
if (RESET= '1') then
RX_START <= '0';
end if;
end if;
end process;
--================================================
-- Receiver shift counter
--
-- 0) 000 3) 101 6) 100 <- TC
-- 1) 001 4) 011
-- 2) 010 5) 110
--
--================================================
RECEIVER_SHIFT_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((RX_STATE = SHIFT) and (RX_CLK_EN = '1')) then
RX_COUNT <= RX_COUNT(1 downto 0) &
not(RX_COUNT(0) xor RX_COUNT(2));
end if;
if (RX_STATE = IDLE) then
RX_COUNT <= RX_INIT;
end if;
end if;
end process;
--================================================
-- Receiver state machine
--================================================
RECEIVER_STATE_MACHINE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (RX_CLK_EN = '1') then
RX_STATE <= RX_NSTATE;
end if;
-- reset state
if (RESET = '1') then
RX_STATE <= IDLE;
end if;
end if;
end process;
--=============================================================
-- Receiver state machine next state logic
--=============================================================
RECEIVER_NEXT_STATE_LOGIC:
process (RX_STATE, RX_ACCEPT, RX_COUNT, PARITY_MODE)
begin
case RX_STATE is
when IDLE =>
if (RX_ACCEPT = '1') then
RX_NSTATE <= SHIFT; -- accept data
else
RX_NSTATE <= IDLE; -- wait
end if;
when SHIFT =>
if (RX_COUNT = RX_TC) then
RX_NSTATE <= D7;
else
RX_NSTATE <= SHIFT;
end if;
when D7 =>
if (PARITY_MODE = NONE) then
RX_NSTATE <= STOP; -- skip parity
else
RX_NSTATE <= PRTY; -- get parity
end if;
when PRTY =>
RX_NSTATE <= STOP;
when STOP =>
RX_NSTATE <= IDLE;
when others =>
RX_NSTATE <= IDLE;
end case;
end process;
--================================================
-- Receiver shift register accept data
--================================================
RECEIVER_SHIFT_ACCEPT_DATA:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- RX_ACCEPT goes hi if start bit is OK & there's room
-- It stays hi until the data has been received
if ((RX_STATE = IDLE) and (RX_START = '1') and
(RX_FIFO_STOP = '0')) then
RX_ACCEPT<= '1';
end if;
if (RX_STATE = D7) then
RX_ACCEPT<= '0';
end if;
-- reset state
if ((RESET = '1') or (RX_EN = '0')) then
RX_ACCEPT <= '0';
end if;
end if;
end process;
--================================================
-- Receiver shift register
--================================================
RECEIVER_SHIFT_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- synchronize the received data
RXD_SYNC1 <= RXDI;
RXD_SYNC <= RXD_SYNC1;
-- shift in the data
if ((RX_CLK_EN = '1') and (RX_SHIFT_EN = '1')) then
RX_SHIFT_REG <= RXD_SYNC & RX_SHIFT_REG(7 downto 1);
end if;
end if;
end process;
--================================================
-- RX FIFO control
--================================================
RX_FIFO_CONTROL:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
RX_FIFO_OP <= '0';
RX_FIFO_CKEN <= '0';
-- push the RX FIFO when data received
if ((RX_CLK_EN = '1') and (RX_STATE = STOP)) then
RX_FIFO_OP <= '1';
RX_FIFO_CKEN <= '1';
end if;
-- RX FIFO on a uP read
if (RDV = '1') then
if ((CS = '1') and (REG_SEL = HOLD_ADDR)) then
RX_FIFO_OP <= '0';
RX_FIFO_CKEN <= '1';
end if;
end if;
end if;
end process;
--================================================
-- Receiver parity generation
--================================================
RECEIVER_PARITY_GENERATION:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((RX_STATE = IDLE) and (RX_ACCEPT = '0')) then
-- for odd parity init RX_PARITY to 1
-- for even parity init RX_PARITY to 0
RX_PARITY <= PARITY_MODE(0);
else
if (RX_CLK_EN = '1') then
-- calculate parity during shift
RX_PARITY <= RX_PARITY xor RXD_SYNC;
end if;
end if;
end if;
end process;
--================================================
-- Receiver error flags
--================================================
RECEIVER_ERROR_FLAGS:
process (FCLK)
begin
-- PARITY_ERR is set when the calculated parity doesn't match
-- the received parity. It stays set until a character
-- without a parity error is received.
-- FRAMING_ERR is set if the stop bit=0. It stays set until
-- a character without a frame error is received.
-- OVERRUN_ERR set if a new start bit is seen but there's no room
-- for more data. It stays set until explicitly cleared.
if (FCLK = '0' and FCLK'event) then
if (RX_CLK_EN = '1') then
-- check for framing sync
if (RX_STATE = STOP) then
FRAMING_ERR <= not RXD_SYNC;
end if;
-- check parity
if ((RX_STATE = STOP) and (PARITY_MODE /= NONE)) then
PARITY_ERR <= RX_PARITY;
end if;
end if;
-- check for FIFO overrun
if ((RX_FIFO_STOP = '1') and (RX_STATE = IDLE) and
(RX_START = '1')) then
OVERRUN_ERR <= '1';
end if;
-- Clear framing error
if ((RX_EN = '0') or (STATUS_CLR = '1')) then
FRAMING_ERR <= '0';
end if;
-- Clear parity error
if ((RX_EN = '0') or (PARITY_MODE = NONE) or
(STATUS_CLR = '1')) then
PARITY_ERR <= '0';
end if;
-- Clear overrun error
if ((RX_EN = '0') or (STATUS_CLR = '1')) then
OVERRUN_ERR <= '0';
end if;
end if;
end process;
--================================================
-- RX FIFO flags
--================================================
RX_FIFO_FLAGS:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- set overflow
if (RX_FIFO_OVFL = '1') then
RX_FIFO_STOP <= '1';
end if;
-- reset state
if ((RESET = '1') or (STATUS_CLR = '1')) then
RX_FIFO_STOP <= '0';
end if;
end if;
end process;
--================================================
-- TX FIFO input byte select
--================================================
TX_BYTE_SELECT:
process (BYTE_SEL, WR_DATA)
begin
if (BYTE_SEL = '0') then
TX_FIFO_IN <= WR_DATA(7 downto 0);
else
TX_FIFO_IN <= WR_DATA(15 downto 8);
end if;
end process;
--============================================
-- Instantiate the RX FIFO
--============================================
RX_FIFO: FIFO port map (
FIFO_OUT => RX_FIFO_DATA,
FIFO_IN => RX_SHIFT_REG,
OVFL => RX_FIFO_OVFL,
LAST => RX_FIFO_FULL,
EMPTY => RX_FIFO_EMPTY,
FIFO_OP => RX_FIFO_OP,
CKEN => RX_FIFO_CKEN,
CLK => FCLK,
RESET => RESET
);
--============================================
-- Instantiate the TX FIFO
--============================================
TX_FIFO: FIFO port map (
FIFO_OUT => TX_FIFO_DATA,
FIFO_IN => TX_FIFO_IN,
OVFL => TX_FIFO_OVFL,
LAST => TX_FIFO_FULL,
EMPTY => TX_FIFO_EMPTY,
FIFO_OP => TX_FIFO_OP,
CKEN => TX_FIFO_CKEN,
CLK => FCLK,
RESET => RESET
);
end BEHAVIORAL;
| gpl-3.0 | 769eb060599236d050d44ab60e41d1fe | 0.39619 | 4.566343 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/spi/src/spi.vhd | 3 | 6,854 | -------------------------------------------------------------------------------
-- SPI Slave IP-Core
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity spi is
generic (
frameSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false
);
port (
-- Control Interface
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(frameSize_g-1 downto 0);
load : in std_logic; --load din
dout : out std_logic_vector(frameSize_g-1 downto 0);
valid : out std_logic; --dout is valid
-- SPI
sck : in std_logic;
ss : in std_logic;
miso : out std_logic;
mosi : in std_logic
);
end spi;
architecture rtl of spi is
--pulse generation out of spi clock (sck)
signal sckL : std_logic;
signal sckRising : std_logic;
signal sckFalling : std_logic;
signal capPulse : std_logic; --pulse to capture data
signal setPulse : std_logic; --pulse to change data
--capture data
signal capMosi : std_logic;
signal capDout : std_logic_vector(frameSize_g-1 downto 0);
--frame counter
signal cnt : integer range 0 to frameSize_g;
signal tc : std_logic;
signal miso_s : std_logic;
signal din_s : std_logic_vector(frameSize_g-1 downto 0);
begin
miso <= miso_s when ss = '1' else 'Z'; --set miso to high if slave isn't selected!
spiClkShiftReg : process(clk, rst)
begin
if rst = '1' then
if cpol_g = false then
sckL <= '0';
else
sckL <= '1';
end if;
elsif clk = '1' and clk'event then
sckL <= sck;
end if;
end process;
--generate sck rising falling edge pulse
sckRising <= '1' when sckL = '0' and sck = '1' else '0';
sckFalling <= '1' when sckL = '1' and sck = '0' else '0';
capPulse <= '0' when (ss /= '1') else
sckRising when (cpha_g = false and cpol_g = false) else
sckFalling when (cpha_g = false and cpol_g = true) else
sckFalling when (cpha_g = true and cpol_g = false) else
sckRising when (cpha_g = true and cpol_g = true) else
'0';
setPulse <= '0' when (ss /= '1') else
sckFalling when (cpha_g = false and cpol_g = false) else
sckRising when (cpha_g = false and cpol_g = true) else
sckRising when (cpha_g = true and cpol_g = false) else
sckFalling when (cpha_g = true and cpol_g = true) else
'0';
theCapLatch : process(clk, rst)
begin
if rst = '1' then
capMosi <= '0';
elsif clk = '1' and clk'event then
if capPulse = '1' then
--capture mosi data
capMosi <= mosi;
elsif load = '1' and cpha_g = true then
capMosi <= din(0);
end if;
end if;
end process;
theFrameCnt : process(clk, rst)
begin
if rst = '1' then
cnt <= 0;
elsif clk = '1' and clk'event then
if tc = '1' or ss = '0' then
cnt <= 0;
elsif capPulse = '1' and cpha_g = true then
cnt <= cnt + 1;
elsif setPulse = '1' and cpha_g = false then
cnt <= cnt + 1;
end if;
end if;
end process;
tc <= '1' when cnt = frameSize_g else '0';
theDoutLatch : process(clk, rst)
begin
if rst = '1' then
dout <= (others => '0');
elsif clk = '1' and clk'event then
valid <= '0';
if tc = '1' then
if cpha_g = false then
dout <= capDout;
else
dout <= capDout(capDout'left-1 downto 0) & capMosi;
end if;
valid <= '1';
end if;
end if;
end process;
dinGenPhaF : if cpha_g = false generate
din_s <= din;
end generate;
dinGenPhaT : if cpha_g = true generate
din_s <= '0' & din(din'left downto 1);
end generate;
theShiftRegister : entity work.spi_sreg
generic map (
size_g => frameSize_g
)
port map (
clk => clk,
rst => rst,
shift => setPulse,
load => load,
din => din_s,
dout => capDout,
sin => capMosi,
sout => miso_s
);
end rtl;
| gpl-2.0 | 48f05aae4205096a8b160985e23710f4 | 0.505107 | 4.207489 | false | false | false | false |
amethystek/VHDL_SPACE_INVADER | vga.vhd | 1 | 62,191 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity vga is
port(RST: in std_logic;--KEY0
CLK: in std_logic;
BUTTON_A:in std_logic;--KEY3--move left
BUTTON_B:in std_logic;--KEY2--missile out
BUTTON_C:in std_logic;--KEY1--move right
VGA_CLK: out std_logic;
RV: out std_logic_vector(9 downto 0);
GV: out std_logic_vector(9 downto 0);
BV: out std_logic_vector(9 downto 0);
VS: out std_logic;--Vertical Sync
HS: out std_logic;--Horizontal Sync
BLANK: out std_logic;
SYNC: out std_logic);
end vga;
---------------------------------------------------------------------
architecture behave of vga is
component random
port(CLK: in std_logic;
D_IN: in std_logic;
Q_OUT:out std_logic_vector(2 downto 0));
end component;
component alien
port(MOVE_CLK: in std_logic;
MISSILE_POS_H:in std_logic_vector(10 downto 0);
MISSILE_POS_V:in std_logic_vector(10 downto 0);
HCount: in std_logic_vector(10 downto 0);
VCount: in std_logic_vector(10 downto 0);
INIT_POS_H: in std_logic_vector(10 downto 0);--decide where an alien appear after be resetted
ALIEN_HIT: out std_logic;--if alien was hit, send 1 to missile
VGA_ALIEN_EN: out std_logic;--whether show on screen
ALIEN_WON: out std_logic:='0');--if a alien touch the bottom, game over
end component;
component player
port(MOVE_CLK:in std_logic;
HCount: in std_logic_vector(10 downto 0);
VCount: in std_logic_vector(10 downto 0);
PLAYER_BUTTON_A:in std_logic;
PLAYER_BUTTON_B:in std_logic;
PLAYER_H: out std_logic_vector(10 downto 0);--send to missile
VGA_PLAYER_EN: out std_logic);--whether show on screen
end component;
component missile
port(MOVE_CLK: in std_logic;
HCount: in std_logic_vector(10 downto 0);
VCount: in std_logic_vector(10 downto 0);
MISSILE_BUTTON:in std_logic;
ALIEN_HIT: in std_logic_vector(2 downto 0);
PLAYER_POS_H: in std_logic_vector(10 downto 0);--get from player
MISSILE_OUT: out std_logic;--send to alien
MISSILE_POS_H: out std_logic_vector(10 downto 0);--send to alien
MISSILE_POS_V: out std_logic_vector(10 downto 0);--send to alien
VGA_MISSILE_EN:out std_logic);--whether show on screen
end component;
------------------------------800X600,72Hz,50MHz-------------------------------
constant H_PIXELS :integer:=800;
constant H_FRONTPORCH:integer:=56;
constant H_SYNCTIME :integer:=120;
constant H_BACKPROCH :integer:=64;
constant H_SYNCSTART :integer:=H_PIXELS+H_FRONTPORCH;
constant H_SYNCEND :integer:=H_SYNCSTART+H_SYNCTIME;
constant H_PERIOD :integer:=H_SYNCEND+H_BACKPROCH;
constant V_LINES :integer:=600;
constant V_FRONTPORCH:integer:=37;
constant V_SYNCTIME :integer:=6;
constant V_BACKPROCH :integer:=23;
constant V_SYNCSTART :integer:=V_LINES+V_FRONTPORCH;
constant V_SYNCEND :integer:=V_SYNCSTART+V_SYNCTIME;
constant V_PERIOD :integer:=V_SYNCEND+V_BACKPROCH;
signal HSync :std_logic;
signal VSync :std_logic;
signal HCount :std_logic_vector(10 downto 0);
signal VCount :std_logic_vector(10 downto 0);
signal HEnable:std_logic;
signal VEnable:std_logic;
signal ColorR :std_logic_vector(9 downto 0);
signal ColorG :std_logic_vector(9 downto 0);
signal ColorB :std_logic_vector(9 downto 0);
---------------------------------------------------------------------
--player
signal player_pos_h :std_logic_vector(10 downto 0);
signal vga_player_en :std_logic;
signal PLAYER_LIFE :std_logic_vector(10 downto 0):="01100011111";--=>hp=799
signal vga_player_life_en:std_logic;
---------------------------------------------------------------------
--game logic
signal gameover_en :std_logic:='0';
signal vga_gameover_en:std_logic:='0';
---------------------------------------------------------------------
--random_gen
signal rand1_val:std_logic_vector(2 downto 0);
signal rand2_val:std_logic_vector(2 downto 0);
signal rand3_val:std_logic_vector(2 downto 0);
signal rand4_val:std_logic_vector(2 downto 0);
---------------------------------------------------------------------
--another random_gen
signal random_count_gen :std_logic_vector(10 downto 0);
signal random_count_gen_mode:std_logic:='0';
---------------------------------------------------------------------
--screen framework of game
signal vga_framework_en:std_logic;
---------------------------------------------------------------------
--alien
signal vga_alien_en:std_logic_vector(2 downto 0);
signal alien_won :std_logic_vector(2 downto 0);
signal alien_hit_state :std_logic_vector(2 downto 0);
signal alien_init_pos_1:std_logic_vector(10 downto 0):="00000000100";
signal alien_init_pos_2:std_logic_vector(10 downto 0):="00001000000";
signal alien_init_pos_3:std_logic_vector(10 downto 0):="00011111000";
signal if_alien_goal :std_logic;
---------------------------------------------------------------------
--star
signal vga_star_en:std_logic;
---------------------------------------------------------------------
--game logic clock
signal move_clk_count:std_logic_vector(4 downto 0);
signal move_clk :std_logic;
---------------------------------------------------------------------
--missile
signal missile_en :std_logic:='0';
signal missile_pos_h :std_logic_vector(10 downto 0);
signal missile_pos_v :std_logic_vector(10 downto 0);
signal vga_missile_en:std_logic;
---------------------------------------------------------------------
begin
rand1:random port map(HSync,CLK,rand1_val);
rand2:random port map(HSync,CLK,rand2_val);
rand3:random port map(HSync,CLK,rand3_val);
rand4:random port map(HSync,CLK,rand4_val);
alien_1:alien port map(move_clk,missile_pos_h,missile_pos_v,
HCount,VCount,alien_init_pos_1,alien_hit_state(0),
vga_alien_en(0),alien_won(0));
alien_2:alien port map(move_clk,missile_pos_h,missile_pos_v,
HCount,VCount,alien_init_pos_2,alien_hit_state(1),
vga_alien_en(1),alien_won(1));
alien_3:alien port map(move_clk,missile_pos_h,missile_pos_v,
HCount,VCount,alien_init_pos_3,alien_hit_state(2),
vga_alien_en(2),alien_won(2));
missile_1:missile port map(move_clk,HCount,VCount,BUTTON_B,alien_hit_state,
player_pos_h,missile_en,missile_pos_h,
missile_pos_v,vga_missile_en);
player_1:player port map(move_clk,HCount,VCount,BUTTON_A,BUTTON_C,
player_pos_h,vga_player_en);
---------------------------------------------------------------------
RV<=ColorR;
GV<=ColorG;
BV<=ColorB;
VGA_CLK<=CLK;
BLANK<='1';
SYNC<='0';
---------------------------------------------------------------------
MOVE_CLOCK:process(VSync)
begin
if rising_edge(VSync)then
if(move_clk_count<1)then--test speed=1, normal speed=15
move_clk<='0';
move_clk_count<=move_clk_count+1;
else
move_clk_count<=(others=>'0');
move_clk<='1';
end if;
end if;
end process MOVE_CLOCK;
RAND_GEN:process(VSync)
begin
if rising_edge(VSync)then
if(random_count_gen_mode='0')then
if(random_count_gen<"11111111110")then
random_count_gen<=random_count_gen+1;
else
random_count_gen<="11111111110";
random_count_gen_mode<='1';
end if;
else
if(random_count_gen>"00000000001")then
random_count_gen<=random_count_gen-1;
else
random_count_gen<="00000000000";
random_count_gen_mode<='0';
end if;
end if;
end if;
end process RAND_GEN;
H_SYNC_SIG:process(RST,CLK)
begin
if RST='0' then
HCount<=(OTHERS=>'0');
HSync<='0';
elsif rising_edge(CLK) then
if HCount<H_PERIOD then
HCount<=HCount+1;
HSync<='0';
else
HCount<=(OTHERS=>'0');
HSync<='1';
end if;
end if;
end process H_SYNC_SIG;
V_SYNC_SIG:process(RST,HSync)
begin
if RST='0' then
VCount<=(OTHERS=>'0');
VSync<='0';
elsif rising_edge(HSync) then
if VCount<V_PERIOD then
VCount<=Vcount+1;
VSync<='0';
else
VCount<=(OTHERS=>'0');
VSync<='1';
end if;
end if;
end process V_SYNC_SIG;
H_SYNC_OUT:process(RST,CLK)
begin
if RST='0' then
HS<='1';
elsif rising_edge(CLK) then
if (HCount>=(H_PIXELS+H_FRONTPORCH) and HCount<
(H_PIXELS+H_FRONTPORCH+H_SYNCTIME)) then
HS<='0';
else
HS<='1';
end if;
end if;
end process H_SYNC_OUT;
V_SYNC_OUT:process(RST,HSync)
begin
if RST='0' then
VS<='1';
elsif rising_edge(HSync) then
if (VCount>=(V_LINES+V_FRONTPORCH) and VCount<
(V_LINES+V_FRONTPORCH+V_SYNCTIME)) then
VS<='0';
else
VS<='1';
end if;
end if;
end process V_SYNC_OUT;
H_EN:process(RST,CLK,HCount)
begin
if rising_edge(CLK) then
if RST='0' then
HEnable<='0';
elsif HCount>=H_PIXELS then
HEnable<='0';
else
HEnable<='1';
end if;
end if;
end process H_EN;
V_EN:process(RST,CLK,VCount)
begin
if rising_edge(CLK) then
if RST='0' then
VEnable<='0';
elsif VCount>=V_LINES then
VEnable<='0';
else
VEnable<='1';
end if;
end if;
end process V_EN;
-----------------------------screen----------------------------------
FRAMEWORK:process(HCount,VCount)
begin
vga_framework_en<='0';
if(VCount=26)then
if((HCount>59 and Hcount<66)or(HCount>202 and Hcount<209)or
(HCount>271 and Hcount<271)or(HCount>682 and Hcount<686))then
vga_framework_en<='1';
end if;
elsif(VCount=27)then
if((HCount>55 and Hcount<70)or(HCount>89 and Hcount<117)or
(HCount>149 and Hcount<161)or(HCount>198 and Hcount<214)or
(HCount>234 and Hcount<271)or(HCount>295 and Hcount<306)or
(HCount>314 and Hcount<326)or(HCount>347 and Hcount<357)or
(HCount>363 and Hcount<376)or(HCount>396 and Hcount<408)or
(HCount>427 and Hcount<439)or(HCount>462 and Hcount<488)or
(HCount>512 and Hcount<549)or(HCount>557 and Hcount<586)or
(HCount>617 and Hcount<630)or(HCount>650 and Hcount<662)or
(HCount>678 and Hcount<690)or(HCount>741 and Hcount<752))then
vga_framework_en<='1';
end if;
elsif(VCount=28)then
if((HCount>53 and Hcount<73)or(HCount>90 and Hcount<121)or
(HCount>150 and Hcount<160)or(HCount>195 and Hcount<216)or
(HCount>235 and Hcount<271)or(HCount>296 and Hcount<304)or
(HCount>315 and Hcount<325)or(HCount>349 and Hcount<356)or
(HCount>365 and Hcount<374)or(HCount>398 and Hcount<406)or
(HCount>428 and Hcount<438)or(HCount>463 and Hcount<493)or
(HCount>513 and Hcount<549)or(HCount>558 and Hcount<590)or
(HCount>619 and Hcount<628)or(HCount>652 and Hcount<660)or
(HCount>676 and Hcount<692)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=29)then
if((HCount>51 and Hcount<76)or(HCount>91 and Hcount<123)or
(HCount>150 and Hcount<159)or(HCount>193 and Hcount<218)or
(HCount>236 and Hcount<271)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<325)or(HCount>349 and Hcount<355)or
(HCount>366 and Hcount<374)or(HCount>398 and Hcount<405)or
(HCount>428 and Hcount<437)or(HCount>464 and Hcount<495)or
(HCount>514 and Hcount<549)or(HCount>559 and Hcount<592)or
(HCount>620 and Hcount<628)or(HCount>652 and Hcount<659)or
(HCount>674 and Hcount<694)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=30)then
if((HCount>50 and Hcount<78)or(HCount>91 and Hcount<124)or
(HCount>150 and Hcount<159)or(HCount>191 and Hcount<220)or
(HCount>236 and Hcount<271)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<325)or(HCount>349 and Hcount<355)or
(HCount>366 and Hcount<374)or(HCount>398 and Hcount<405)or
(HCount>428 and Hcount<437)or(HCount>464 and Hcount<497)or
(HCount>514 and Hcount<549)or(HCount>559 and Hcount<593)or
(HCount>620 and Hcount<628)or(HCount>652 and Hcount<659)or
(HCount>673 and Hcount<695)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=31)then
if((HCount>49 and Hcount<81)or(HCount>91 and Hcount<125)or
(HCount>150 and Hcount<160)or(HCount>190 and Hcount<222)or
(HCount>236 and Hcount<271)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<326)or(HCount>349 and Hcount<355)or
(HCount>367 and Hcount<374)or(HCount>398 and Hcount<404)or
(HCount>428 and Hcount<438)or(HCount>464 and Hcount<498)or
(HCount>514 and Hcount<549)or(HCount>559 and Hcount<594)or
(HCount>621 and Hcount<628)or(HCount>652 and Hcount<658)or
(HCount>672 and Hcount<696)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=32)then
if((HCount>48 and Hcount<80)or(HCount>91 and Hcount<126)or
(HCount>150 and Hcount<160)or(HCount>189 and Hcount<226)or
(HCount>236 and Hcount<271)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<327)or(HCount>349 and Hcount<355)or
(HCount>367 and Hcount<374)or(HCount>397 and Hcount<404)or
(HCount>428 and Hcount<438)or(HCount>464 and Hcount<499)or
(HCount>514 and Hcount<549)or(HCount>559 and Hcount<595)or
(HCount>621 and Hcount<628)or(HCount>651 and Hcount<658)or
(HCount>671 and Hcount<697)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=33)then
if((HCount>48 and Hcount<56)or(HCount>70 and Hcount<80)or
(HCount>91 and Hcount<127)or(HCount>149 and Hcount<160)or
(HCount>188 and Hcount<200)or(HCount>214 and Hcount<225)or
(HCount>236 and Hcount<271)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<328)or(HCount>349 and Hcount<355)or
(HCount>368 and Hcount<375)or(HCount>397 and Hcount<404)or
(HCount>427 and Hcount<438)or(HCount>464 and Hcount<500)or
(HCount>514 and Hcount<549)or(HCount>559 and Hcount<595)or
(HCount>622 and Hcount<629)or(HCount>651 and Hcount<658)or
(HCount>670 and Hcount<679)or(HCount>688 and Hcount<698)or
(HCount>737 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=34)then
if((HCount>47 and Hcount<54)or(HCount>73 and Hcount<79)or
(HCount>91 and Hcount<98)or(HCount>118 and Hcount<127)or
(HCount>149 and Hcount<161)or(HCount>187 and Hcount<198)or
(HCount>217 and Hcount<225)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<329)or
(HCount>349 and Hcount<355)or(HCount>368 and Hcount<375)or
(HCount>396 and Hcount<403)or(HCount>427 and Hcount<439)or
(HCount>464 and Hcount<471)or(HCount>490 and Hcount<501)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>587 and Hcount<596)or(HCount>622 and Hcount<629)or
(HCount>650 and Hcount<657)or(HCount>669 and Hcount<678)or
(HCount>690 and Hcount<698)or(HCount>737 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=35)then
if((HCount>47 and Hcount<53)or(HCount>75 and Hcount<79)or
(HCount>91 and Hcount<98)or(HCount>120 and Hcount<127)or
(HCount>148 and Hcount<161)or(HCount>187 and Hcount<196)or
(HCount>219 and Hcount<224)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<330)or
(HCount>349 and Hcount<355)or(HCount>369 and Hcount<376)or
(HCount>396 and Hcount<403)or(HCount>426 and Hcount<439)or
(HCount>464 and Hcount<471)or(HCount>492 and Hcount<501)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>589 and Hcount<596)or(HCount>623 and Hcount<630)or
(HCount>650 and Hcount<657)or(HCount>669 and Hcount<677)or
(HCount>691 and Hcount<699)or(HCount>737 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=36)then
if((HCount>47 and Hcount<53)or(HCount>76 and Hcount<78)or
(HCount>91 and Hcount<98)or(HCount>120 and Hcount<128)or
(HCount>148 and Hcount<162)or(HCount>186 and Hcount<195)or
(HCount>220 and Hcount<223)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<330)or
(HCount>349 and Hcount<355)or(HCount>369 and Hcount<376)or
(HCount>395 and Hcount<402)or(HCount>426 and Hcount<440)or
(HCount>464 and Hcount<471)or(HCount>493 and Hcount<502)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>589 and Hcount<596)or(HCount>623 and Hcount<630)or
(HCount>649 and Hcount<656)or(HCount>668 and Hcount<676)or
(HCount>692 and Hcount<700)or(HCount>737 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=37)then
if((HCount>46 and Hcount<53)or(HCount>77 and Hcount<78)or
(HCount>91 and Hcount<98)or(HCount>121 and Hcount<128)or
(HCount>147 and Hcount<153)or(HCount>156 and Hcount<162)or
(HCount>185 and Hcount<194)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<331)or
(HCount>349 and Hcount<355)or(HCount>369 and Hcount<377)or
(HCount>395 and Hcount<402)or(HCount>425 and Hcount<431)or
(HCount>434 and Hcount<440)or(HCount>464 and Hcount<471)or
(HCount>494 and Hcount<502)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>590 and Hcount<597)or
(HCount>623 and Hcount<631)or(HCount>649 and Hcount<656)or
(HCount>668 and Hcount<675)or(HCount>693 and Hcount<700)or
(HCount>737 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=38)then
if((HCount>46 and Hcount<53)or(HCount>91 and Hcount<98)or
(HCount>121 and Hcount<128)or(HCount>147 and Hcount<153)or
(HCount>156 and Hcount<163)or(HCount>185 and Hcount<193)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<332)or(HCount>349 and Hcount<355)or
(HCount>370 and Hcount<377)or(HCount>395 and Hcount<401)or
(HCount>425 and Hcount<431)or(HCount>434 and Hcount<441)or
(HCount>464 and Hcount<471)or(HCount>495 and Hcount<503)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>590 and Hcount<597)or(HCount>624 and Hcount<631)or
(HCount>649 and Hcount<655)or(HCount>667 and Hcount<675)or
(HCount>693 and Hcount<700)or(HCount>737 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=39)then
if((HCount>46 and Hcount<53)or(HCount>91 and Hcount<98)or
(HCount>121 and Hcount<128)or(HCount>146 and Hcount<152)or
(HCount>156 and Hcount<163)or(HCount>184 and Hcount<192)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>324 and Hcount<333)or
(HCount>349 and Hcount<355)or(HCount>370 and Hcount<378)or
(HCount>394 and Hcount<401)or(HCount>424 and Hcount<430)or
(HCount>434 and Hcount<441)or(HCount>464 and Hcount<471)or
(HCount>496 and Hcount<503)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>590 and Hcount<597)or
(HCount>624 and Hcount<632)or(HCount>648 and Hcount<655)or
(HCount>667 and Hcount<674)or(HCount>694 and Hcount<701)or
(HCount>737 and Hcount<740)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=40)then
if((HCount>46 and Hcount<53)or(HCount>91 and Hcount<98)or
(HCount>121 and Hcount<128)or(HCount>146 and Hcount<152)or
(HCount>157 and Hcount<164)or(HCount>184 and Hcount<192)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>325 and Hcount<334)or
(HCount>349 and Hcount<355)or(HCount>371 and Hcount<378)or
(HCount>394 and Hcount<400)or(HCount>424 and Hcount<430)or
(HCount>435 and Hcount<442)or(HCount>464 and Hcount<471)or
(HCount>496 and Hcount<503)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>590 and Hcount<597)or
(HCount>625 and Hcount<632)or(HCount>648 and Hcount<654)or
(HCount>667 and Hcount<674)or(HCount>694 and Hcount<701)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=41)then
if((HCount>47 and Hcount<55)or(HCount>91 and Hcount<98)or
(HCount>120 and Hcount<128)or(HCount>145 and Hcount<151)or
(HCount>157 and Hcount<164)or(HCount>184 and Hcount<191)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>326 and Hcount<335)or
(HCount>349 and Hcount<355)or(HCount>371 and Hcount<379)or
(HCount>393 and Hcount<400)or(HCount>423 and Hcount<429)or
(HCount>435 and Hcount<442)or(HCount>464 and Hcount<471)or
(HCount>496 and Hcount<504)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>589 and Hcount<596)or
(HCount>625 and Hcount<633)or(HCount>647 and Hcount<654)or
(HCount>666 and Hcount<674)or(HCount>694 and Hcount<701)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=42)then
if((HCount>47 and Hcount<63)or(HCount>91 and Hcount<98)or
(HCount>120 and Hcount<127)or(HCount>145 and Hcount<151)or
(HCount>158 and Hcount<165)or(HCount>184 and Hcount<191)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>327 and Hcount<336)or
(HCount>349 and Hcount<355)or(HCount>372 and Hcount<379)or
(HCount>393 and Hcount<399)or(HCount>423 and Hcount<429)or
(HCount>436 and Hcount<443)or(HCount>464 and Hcount<471)or
(HCount>497 and Hcount<504)or(HCount>514 and Hcount<521)or
(HCount>540 and Hcount<540)or(HCount>559 and Hcount<566)or
(HCount>589 and Hcount<596)or(HCount>626 and Hcount<633)or
(HCount>647 and Hcount<653)or(HCount>666 and Hcount<673)or
(HCount>694 and Hcount<701)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=43)then
if((HCount>47 and Hcount<70)or(HCount>91 and Hcount<98)or
(HCount>118 and Hcount<127)or(HCount>144 and Hcount<150)or
(HCount>158 and Hcount<165)or(HCount>183 and Hcount<190)or
(HCount>236 and Hcount<262)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>328 and Hcount<337)or
(HCount>349 and Hcount<355)or(HCount>372 and Hcount<379)or
(HCount>392 and Hcount<399)or(HCount>422 and Hcount<428)or
(HCount>436 and Hcount<443)or(HCount>464 and Hcount<471)or
(HCount>497 and Hcount<504)or(HCount>514 and Hcount<540)or
(HCount>559 and Hcount<566)or(HCount>587 and Hcount<596)or
(HCount>626 and Hcount<633)or(HCount>646 and Hcount<653)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=44)then
if((HCount>48 and Hcount<74)or(HCount>91 and Hcount<127)or
(HCount>144 and Hcount<150)or(HCount>159 and Hcount<166)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<262)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>329 and Hcount<338)or(HCount>349 and Hcount<355)or
(HCount>373 and Hcount<380)or(HCount>392 and Hcount<398)or
(HCount>422 and Hcount<428)or(HCount>437 and Hcount<444)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<540)or(HCount>559 and Hcount<596)or
(HCount>627 and Hcount<634)or(HCount>646 and Hcount<652)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=45)then
if((HCount>48 and Hcount<76)or(HCount>91 and Hcount<126)or
(HCount>143 and Hcount<149)or(HCount>159 and Hcount<166)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<262)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>330 and Hcount<339)or(HCount>349 and Hcount<355)or
(HCount>373 and Hcount<380)or(HCount>391 and Hcount<398)or
(HCount>421 and Hcount<427)or(HCount>437 and Hcount<444)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<540)or(HCount>559 and Hcount<595)or
(HCount>627 and Hcount<634)or(HCount>645 and Hcount<652)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=46)then
if((HCount>49 and Hcount<77)or(HCount>91 and Hcount<125)or
(HCount>143 and Hcount<149)or(HCount>160 and Hcount<167)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<262)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>331 and Hcount<340)or(HCount>349 and Hcount<355)or
(HCount>374 and Hcount<381)or(HCount>391 and Hcount<398)or
(HCount>421 and Hcount<427)or(HCount>438 and Hcount<445)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<540)or(HCount>559 and Hcount<594)or
(HCount>628 and Hcount<635)or(HCount>645 and Hcount<652)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=47)then
if((HCount>50 and Hcount<78)or(HCount>91 and Hcount<124)or
(HCount>142 and Hcount<149)or(HCount>160 and Hcount<167)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<262)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>332 and Hcount<341)or(HCount>349 and Hcount<355)or
(HCount>374 and Hcount<381)or(HCount>390 and Hcount<397)or
(HCount>420 and Hcount<427)or(HCount>438 and Hcount<445)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<540)or(HCount>559 and Hcount<593)or
(HCount>628 and Hcount<635)or(HCount>644 and Hcount<651)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=48)then
if((HCount>52 and Hcount<79)or(HCount>91 and Hcount<123)or
(HCount>142 and Hcount<148)or(HCount>161 and Hcount<168)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<262)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>333 and Hcount<342)or(HCount>349 and Hcount<355)or
(HCount>375 and Hcount<382)or(HCount>390 and Hcount<397)or
(HCount>420 and Hcount<426)or(HCount>439 and Hcount<446)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<540)or(HCount>559 and Hcount<592)or
(HCount>629 and Hcount<636)or(HCount>644 and Hcount<651)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=49)then
if((HCount>54 and Hcount<80)or(HCount>91 and Hcount<121)or
(HCount>141 and Hcount<148)or(HCount>161 and Hcount<168)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<262)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>334 and Hcount<343)or(HCount>349 and Hcount<355)or
(HCount>375 and Hcount<382)or(HCount>390 and Hcount<396)or
(HCount>419 and Hcount<426)or(HCount>439 and Hcount<446)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<540)or(HCount>559 and Hcount<590)or
(HCount>629 and Hcount<636)or(HCount>644 and Hcount<650)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=50)then
if((HCount>59 and Hcount<80)or(HCount>91 and Hcount<117)or
(HCount>141 and Hcount<147)or(HCount>162 and Hcount<169)or
(HCount>183 and Hcount<190)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>335 and Hcount<344)or(HCount>349 and Hcount<355)or
(HCount>375 and Hcount<383)or(HCount>389 and Hcount<396)or
(HCount>419 and Hcount<425)or(HCount>440 and Hcount<447)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<587)or
(HCount>629 and Hcount<637)or(HCount>643 and Hcount<650)or
(HCount>666 and Hcount<673)or(HCount>695 and Hcount<702)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=51)then
if((HCount>68 and Hcount<81)or(HCount>91 and Hcount<98)or
(HCount>140 and Hcount<169)or(HCount>184 and Hcount<191)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>336 and Hcount<345)or
(HCount>349 and Hcount<355)or(HCount>376 and Hcount<383)or
(HCount>389 and Hcount<395)or(HCount>418 and Hcount<447)or
(HCount>464 and Hcount<471)or(HCount>497 and Hcount<504)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>578 and Hcount<586)or(HCount>630 and Hcount<637)or
(HCount>643 and Hcount<649)or(HCount>666 and Hcount<673)or
(HCount>694 and Hcount<701)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=52)then
if((HCount>73 and Hcount<81)or(HCount>91 and Hcount<98)or
(HCount>140 and Hcount<170)or(HCount>184 and Hcount<191)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>337 and Hcount<346)or
(HCount>349 and Hcount<355)or(HCount>376 and Hcount<383)or
(HCount>388 and Hcount<395)or(HCount>418 and Hcount<448)or
(HCount>464 and Hcount<471)or(HCount>496 and Hcount<504)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>579 and Hcount<587)or(HCount>630 and Hcount<637)or
(HCount>642 and Hcount<649)or(HCount>667 and Hcount<674)or
(HCount>694 and Hcount<701)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=53)then
if((HCount>74 and Hcount<81)or(HCount>91 and Hcount<98)or
(HCount>139 and Hcount<170)or(HCount>184 and Hcount<192)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>338 and Hcount<347)or
(HCount>349 and Hcount<355)or(HCount>377 and Hcount<384)or
(HCount>388 and Hcount<394)or(HCount>417 and Hcount<448)or
(HCount>464 and Hcount<471)or(HCount>496 and Hcount<503)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>580 and Hcount<587)or(HCount>631 and Hcount<638)or
(HCount>642 and Hcount<648)or(HCount>667 and Hcount<674)or
(HCount>694 and Hcount<701)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=54)then
if((HCount>75 and Hcount<81)or(HCount>91 and Hcount<98)or
(HCount>139 and Hcount<171)or(HCount>184 and Hcount<192)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>339 and Hcount<355)or
(HCount>377 and Hcount<384)or(HCount>387 and Hcount<394)or
(HCount>417 and Hcount<449)or(HCount>464 and Hcount<471)or
(HCount>496 and Hcount<503)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>581 and Hcount<588)or
(HCount>631 and Hcount<638)or(HCount>641 and Hcount<648)or
(HCount>667 and Hcount<674)or(HCount>694 and Hcount<701)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=55)then
if((HCount>75 and Hcount<81)or(HCount>91 and Hcount<98)or
(HCount>138 and Hcount<171)or(HCount>185 and Hcount<193)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>340 and Hcount<355)or
(HCount>378 and Hcount<385)or(HCount>387 and Hcount<393)or
(HCount>416 and Hcount<449)or(HCount>464 and Hcount<471)or
(HCount>495 and Hcount<503)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>581 and Hcount<589)or
(HCount>632 and Hcount<639)or(HCount>641 and Hcount<647)or
(HCount>667 and Hcount<675)or(HCount>693 and Hcount<700)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=56)then
if((HCount>75 and Hcount<81)or(HCount>91 and Hcount<98)or
(HCount>138 and Hcount<144)or(HCount>164 and Hcount<172)or
(HCount>185 and Hcount<194)or(HCount>221 and Hcount<223)or
(HCount>236 and Hcount<243)or(HCount>297 and Hcount<304)or
(HCount>316 and Hcount<322)or(HCount>341 and Hcount<355)or
(HCount>378 and Hcount<393)or(HCount>416 and Hcount<422)or
(HCount>442 and Hcount<450)or(HCount>464 and Hcount<471)or
(HCount>494 and Hcount<502)or(HCount>514 and Hcount<521)or
(HCount>559 and Hcount<566)or(HCount>582 and Hcount<590)or
(HCount>632 and Hcount<647)or(HCount>668 and Hcount<675)or
(HCount>693 and Hcount<700)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=57)then
if((HCount>48 and Hcount<50)or(HCount>74 and Hcount<81)or
(HCount>91 and Hcount<98)or(HCount>138 and Hcount<144)or
(HCount>165 and Hcount<172)or(HCount>186 and Hcount<195)or
(HCount>220 and Hcount<224)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>341 and Hcount<355)or(HCount>379 and Hcount<392)or
(HCount>416 and Hcount<422)or(HCount>443 and Hcount<450)or
(HCount>464 and Hcount<471)or(HCount>493 and Hcount<502)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>583 and Hcount<590)or(HCount>633 and Hcount<646)or
(HCount>668 and Hcount<676)or(HCount>692 and Hcount<700)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=58)then
if((HCount>47 and Hcount<51)or(HCount>73 and Hcount<81)or
(HCount>91 and Hcount<98)or(HCount>137 and Hcount<143)or
(HCount>165 and Hcount<173)or(HCount>187 and Hcount<196)or
(HCount>218 and Hcount<224)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>342 and Hcount<355)or(HCount>379 and Hcount<392)or
(HCount>415 and Hcount<421)or(HCount>443 and Hcount<451)or
(HCount>464 and Hcount<471)or(HCount>492 and Hcount<501)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>584 and Hcount<591)or(HCount>633 and Hcount<646)or
(HCount>669 and Hcount<677)or(HCount>691 and Hcount<699)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=59)then
if((HCount>47 and Hcount<54)or(HCount>72 and Hcount<80)or
(HCount>91 and Hcount<98)or(HCount>137 and Hcount<143)or
(HCount>166 and Hcount<173)or(HCount>187 and Hcount<198)or
(HCount>216 and Hcount<225)or(HCount>236 and Hcount<243)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>343 and Hcount<355)or(HCount>380 and Hcount<391)or
(HCount>415 and Hcount<421)or(HCount>444 and Hcount<451)or
(HCount>464 and Hcount<471)or(HCount>490 and Hcount<501)or
(HCount>514 and Hcount<521)or(HCount>559 and Hcount<566)or
(HCount>584 and Hcount<592)or(HCount>634 and Hcount<645)or
(HCount>669 and Hcount<678)or(HCount>690 and Hcount<698)or
(HCount>712 and Hcount<717)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=60)then
if((HCount>46 and Hcount<57)or(HCount>70 and Hcount<80)or
(HCount>91 and Hcount<98)or(HCount>136 and Hcount<142)or
(HCount>166 and Hcount<174)or(HCount>188 and Hcount<200)or
(HCount>213 and Hcount<226)or(HCount>236 and Hcount<272)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>344 and Hcount<355)or(HCount>380 and Hcount<391)or
(HCount>414 and Hcount<420)or(HCount>444 and Hcount<452)or
(HCount>464 and Hcount<500)or(HCount>514 and Hcount<550)or
(HCount>559 and Hcount<566)or(HCount>585 and Hcount<593)or
(HCount>634 and Hcount<645)or(HCount>670 and Hcount<679)or
(HCount>688 and Hcount<698)or(HCount>712 and Hcount<718)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=61)then
if((HCount>46 and Hcount<79)or(HCount>91 and Hcount<98)or
(HCount>136 and Hcount<142)or(HCount>167 and Hcount<174)or
(HCount>189 and Hcount<223)or(HCount>236 and Hcount<272)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>345 and Hcount<355)or(HCount>381 and Hcount<391)or
(HCount>414 and Hcount<420)or(HCount>445 and Hcount<452)or
(HCount>464 and Hcount<499)or(HCount>514 and Hcount<550)or
(HCount>559 and Hcount<566)or(HCount>586 and Hcount<593)or
(HCount>635 and Hcount<645)or(HCount>671 and Hcount<697)or
(HCount>711 and Hcount<718)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=62)then
if((HCount>45 and Hcount<78)or(HCount>91 and Hcount<98)or
(HCount>135 and Hcount<141)or(HCount>167 and Hcount<175)or
(HCount>190 and Hcount<221)or(HCount>236 and Hcount<272)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>346 and Hcount<355)or(HCount>381 and Hcount<390)or
(HCount>413 and Hcount<419)or(HCount>445 and Hcount<453)or
(HCount>464 and Hcount<498)or(HCount>514 and Hcount<550)or
(HCount>559 and Hcount<566)or(HCount>586 and Hcount<594)or
(HCount>635 and Hcount<644)or(HCount>672 and Hcount<696)or
(HCount>711 and Hcount<719)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=63)then
if((HCount>48 and Hcount<77)or(HCount>91 and Hcount<98)or
(HCount>135 and Hcount<141)or(HCount>168 and Hcount<175)or
(HCount>191 and Hcount<220)or(HCount>236 and Hcount<272)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>347 and Hcount<355)or(HCount>381 and Hcount<390)or
(HCount>413 and Hcount<419)or(HCount>446 and Hcount<453)or
(HCount>464 and Hcount<497)or(HCount>514 and Hcount<550)or
(HCount>559 and Hcount<566)or(HCount>587 and Hcount<595)or
(HCount>635 and Hcount<644)or(HCount>673 and Hcount<695)or
(HCount>711 and Hcount<719)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=64)then
if((HCount>50 and Hcount<76)or(HCount>91 and Hcount<98)or
(HCount>134 and Hcount<141)or(HCount>168 and Hcount<176)or
(HCount>193 and Hcount<218)or(HCount>236 and Hcount<272)or
(HCount>297 and Hcount<304)or(HCount>316 and Hcount<322)or
(HCount>348 and Hcount<355)or(HCount>381 and Hcount<390)or
(HCount>412 and Hcount<419)or(HCount>446 and Hcount<454)or
(HCount>464 and Hcount<495)or(HCount>514 and Hcount<550)or
(HCount>559 and Hcount<566)or(HCount>588 and Hcount<596)or
(HCount>635 and Hcount<644)or(HCount>674 and Hcount<694)or
(HCount>711 and Hcount<718)or(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=65)then
if((HCount>53 and Hcount<74)or(HCount>90 and Hcount<98)or
(HCount>133 and Hcount<141)or(HCount>167 and Hcount<177)or
(HCount>195 and Hcount<216)or(HCount>235 and Hcount<272)or
(HCount>296 and Hcount<304)or(HCount>315 and Hcount<322)or
(HCount>348 and Hcount<356)or(HCount>381 and Hcount<390)or
(HCount>411 and Hcount<419)or(HCount>463 and Hcount<492)or
(HCount>513 and Hcount<550)or(HCount>558 and Hcount<566)or
(HCount>588 and Hcount<597)or(HCount>635 and Hcount<644)or
(HCount>676 and Hcount<692)or(HCount>712 and Hcount<718)or
(HCount>743 and Hcount<750))then
vga_framework_en<='1';
end if;
elsif(VCount=66)then
if((HCount>56 and Hcount<71)or(HCount>89 and Hcount<100)or
(HCount>132 and Hcount<143)or(HCount>166 and Hcount<179)or
(HCount>198 and Hcount<213)or(HCount>234 and Hcount<272)or
(HCount>295 and Hcount<306)or(HCount>314 and Hcount<324)or
(HCount>346 and Hcount<357)or(HCount>380 and Hcount<392)or
(HCount>410 and Hcount<421)or(HCount>444 and Hcount<457)or
(HCount>462 and Hcount<488)or(HCount>512 and Hcount<550)or
(HCount>557 and Hcount<568)or(HCount>586 and Hcount<599)or
(HCount>634 and Hcount<646)or(HCount>678 and Hcount<690)or
(HCount>712 and Hcount<717)or(HCount>741 and Hcount<752))then
vga_framework_en<='1';
end if;
elsif(VCount=67)then
if((HCount>60 and Hcount<67)or(HCount>202 and Hcount<209)or(HCount>681 and Hcount<686))then
vga_framework_en<='1';
end if;
elsif((VCount>94 and VCount<108)or(VCount>169 and VCount<183)or(VCount>496 and VCount<500))then
vga_framework_en<='1';
end if;
end process FRAMEWORK;
--------------------------game over----------------------------------
GAMEOVER:process(HCount,VCount)
begin
vga_gameover_en<='0';
if(VCount=202)then
if((HCount>217 and Hcount<224)or(HCount>450 and Hcount<456))then
vga_gameover_en<='1';
end if;
elsif(VCount=203)then
if((HCount>212 and Hcount<229)or(HCount>264 and Hcount<276)or
(HCount>299 and Hcount<313)or(HCount>335 and Hcount<348)or
(HCount>357 and Hcount<394)or(HCount>445 and Hcount<461)or
(HCount>480 and Hcount<493)or(HCount>513 and Hcount<525)or
(HCount>530 and Hcount<567)or(HCount>575 and Hcount<604))then
vga_gameover_en<='1';
end if;
elsif(VCount=204)then
if((HCount>209 and Hcount<232)or(HCount>265 and Hcount<275)or
(HCount>300 and Hcount<311)or(HCount>336 and Hcount<346)or
(HCount>358 and Hcount<394)or(HCount>443 and Hcount<464)or
(HCount>482 and Hcount<491)or(HCount>515 and Hcount<523)or
(HCount>531 and Hcount<567)or(HCount>576 and Hcount<608))then
vga_gameover_en<='1';
end if;
elsif(VCount=205)then
if((HCount>207 and Hcount<237)or(HCount>265 and Hcount<274)or
(HCount>301 and Hcount<311)or(HCount>336 and Hcount<346)or
(HCount>359 and Hcount<394)or(HCount>441 and Hcount<465)or
(HCount>483 and Hcount<491)or(HCount>515 and Hcount<522)or
(HCount>532 and Hcount<567)or(HCount>577 and Hcount<610))then
vga_gameover_en<='1';
end if;
elsif(VCount=206)then
if((HCount>206 and Hcount<237)or(HCount>265 and Hcount<274)or
(HCount>301 and Hcount<311)or(HCount>336 and Hcount<346)or
(HCount>359 and Hcount<394)or(HCount>439 and Hcount<467)or
(HCount>483 and Hcount<491)or(HCount>515 and Hcount<522)or
(HCount>532 and Hcount<567)or(HCount>577 and Hcount<611))then
vga_gameover_en<='1';
end if;
elsif(VCount=207)then
if((HCount>204 and Hcount<236)or(HCount>265 and Hcount<275)or
(HCount>301 and Hcount<312)or(HCount>335 and Hcount<346)or
(HCount>359 and Hcount<394)or(HCount>438 and Hcount<468)or
(HCount>484 and Hcount<491)or(HCount>515 and Hcount<521)or
(HCount>532 and Hcount<567)or(HCount>577 and Hcount<612))then
vga_gameover_en<='1';
end if;
elsif(VCount=208)then
if((HCount>203 and Hcount<236)or(HCount>265 and Hcount<275)or
(HCount>301 and Hcount<312)or(HCount>335 and Hcount<346)or
(HCount>359 and Hcount<394)or(HCount>437 and Hcount<469)or
(HCount>484 and Hcount<491)or(HCount>514 and Hcount<521)or
(HCount>532 and Hcount<567)or(HCount>577 and Hcount<613))then
vga_gameover_en<='1';
end if;
elsif(VCount=209)then
if((HCount>202 and Hcount<214)or(HCount>227 and Hcount<235)or
(HCount>264 and Hcount<275)or(HCount>301 and Hcount<313)or
(HCount>334 and Hcount<346)or(HCount>359 and Hcount<394)or
(HCount>436 and Hcount<447)or(HCount>459 and Hcount<470)or
(HCount>485 and Hcount<492)or(HCount>514 and Hcount<521)or
(HCount>532 and Hcount<567)or(HCount>577 and Hcount<613))then
vga_gameover_en<='1';
end if;
elsif(VCount=210)then
if((HCount>201 and Hcount<211)or(HCount>230 and Hcount<235)or
(HCount>264 and Hcount<276)or(HCount>301 and Hcount<313)or
(HCount>334 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>435 and Hcount<445)or(HCount>461 and Hcount<471)or
(HCount>485 and Hcount<492)or(HCount>513 and Hcount<520)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>605 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=211)then
if((HCount>200 and Hcount<210)or(HCount>232 and Hcount<234)or
(HCount>263 and Hcount<276)or(HCount>301 and Hcount<314)or
(HCount>333 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>435 and Hcount<443)or(HCount>463 and Hcount<472)or
(HCount>486 and Hcount<493)or(HCount>513 and Hcount<520)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>607 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=212)then
if((HCount>200 and Hcount<209)or(HCount>263 and Hcount<277)or
(HCount>301 and Hcount<314)or(HCount>333 and Hcount<346)or
(HCount>359 and Hcount<366)or(HCount>434 and Hcount<442)or
(HCount>464 and Hcount<472)or(HCount>486 and Hcount<493)or
(HCount>512 and Hcount<519)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>607 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=213)then
if((HCount>199 and Hcount<208)or(HCount>262 and Hcount<268)or
(HCount>271 and Hcount<277)or(HCount>301 and Hcount<315)or
(HCount>332 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>433 and Hcount<441)or(HCount>465 and Hcount<473)or
(HCount>486 and Hcount<494)or(HCount>512 and Hcount<519)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>608 and Hcount<615))then
vga_gameover_en<='1';
end if;
elsif(VCount=214)then
if((HCount>199 and Hcount<207)or(HCount>262 and Hcount<268)or
(HCount>271 and Hcount<278)or(HCount>301 and Hcount<315)or
(HCount>332 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>433 and Hcount<441)or(HCount>466 and Hcount<473)or
(HCount>487 and Hcount<494)or(HCount>512 and Hcount<518)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>608 and Hcount<615))then
vga_gameover_en<='1';
end if;
elsif(VCount=215)then
if((HCount>198 and Hcount<206)or(HCount>261 and Hcount<267)or
(HCount>271 and Hcount<278)or(HCount>301 and Hcount<307)or
(HCount>309 and Hcount<316)or(HCount>331 and Hcount<337)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>432 and Hcount<440)or(HCount>466 and Hcount<474)or
(HCount>487 and Hcount<495)or(HCount>511 and Hcount<518)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>608 and Hcount<615))then
vga_gameover_en<='1';
end if;
elsif(VCount=216)then
if((HCount>198 and Hcount<206)or(HCount>261 and Hcount<267)or
(HCount>272 and Hcount<279)or(HCount>301 and Hcount<307)or
(HCount>310 and Hcount<317)or(HCount>331 and Hcount<337)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>432 and Hcount<439)or(HCount>467 and Hcount<474)or
(HCount>488 and Hcount<495)or(HCount>511 and Hcount<517)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>608 and Hcount<615))then
vga_gameover_en<='1';
end if;
elsif(VCount=217)then
if((HCount>198 and Hcount<205)or(HCount>260 and Hcount<266)or
(HCount>272 and Hcount<279)or(HCount>301 and Hcount<307)or
(HCount>310 and Hcount<317)or(HCount>330 and Hcount<336)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>432 and Hcount<439)or(HCount>467 and Hcount<474)or
(HCount>488 and Hcount<496)or(HCount>510 and Hcount<517)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>607 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=218)then
if((HCount>198 and Hcount<205)or(HCount>260 and Hcount<266)or
(HCount>273 and Hcount<280)or(HCount>301 and Hcount<307)or
(HCount>311 and Hcount<318)or(HCount>329 and Hcount<335)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>432 and Hcount<439)or(HCount>468 and Hcount<475)or
(HCount>489 and Hcount<496)or(HCount>510 and Hcount<516)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>607 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=219)then
if((HCount>197 and Hcount<204)or(HCount>259 and Hcount<265)or
(HCount>273 and Hcount<280)or(HCount>301 and Hcount<307)or
(HCount>311 and Hcount<318)or(HCount>329 and Hcount<335)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<385)or
(HCount>431 and Hcount<438)or(HCount>468 and Hcount<475)or
(HCount>489 and Hcount<496)or(HCount>509 and Hcount<516)or
(HCount>532 and Hcount<558)or(HCount>577 and Hcount<584)or
(HCount>605 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=220)then
if((HCount>197 and Hcount<204)or(HCount>259 and Hcount<265)or
(HCount>274 and Hcount<281)or(HCount>301 and Hcount<307)or
(HCount>312 and Hcount<319)or(HCount>328 and Hcount<334)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<385)or
(HCount>431 and Hcount<438)or(HCount>468 and Hcount<475)or
(HCount>490 and Hcount<497)or(HCount>509 and Hcount<515)or
(HCount>532 and Hcount<558)or(HCount>577 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=221)then
if((HCount>197 and Hcount<204)or(HCount>258 and Hcount<264)or
(HCount>274 and Hcount<281)or(HCount>301 and Hcount<307)or
(HCount>312 and Hcount<319)or(HCount>328 and Hcount<334)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<385)or
(HCount>431 and Hcount<438)or(HCount>468 and Hcount<475)or
(HCount>490 and Hcount<497)or(HCount>508 and Hcount<515)or
(HCount>532 and Hcount<558)or(HCount>577 and Hcount<613))then
vga_gameover_en<='1';
end if;
elsif(VCount=222)then
if((HCount>197 and Hcount<204)or(HCount>258 and Hcount<264)or
(HCount>275 and Hcount<282)or(HCount>301 and Hcount<307)or
(HCount>313 and Hcount<320)or(HCount>327 and Hcount<333)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<385)or
(HCount>431 and Hcount<438)or(HCount>468 and Hcount<475)or
(HCount>491 and Hcount<498)or(HCount>508 and Hcount<515)or
(HCount>532 and Hcount<558)or(HCount>577 and Hcount<612))then
vga_gameover_en<='1';
end if;
elsif(VCount=223)then
if((HCount>197 and Hcount<204)or(HCount>221 and Hcount<241)or
(HCount>257 and Hcount<264)or(HCount>275 and Hcount<282)or
(HCount>301 and Hcount<307)or(HCount>313 and Hcount<320)or
(HCount>327 and Hcount<333)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<385)or(HCount>431 and Hcount<438)or
(HCount>468 and Hcount<475)or(HCount>491 and Hcount<498)or
(HCount>507 and Hcount<514)or(HCount>532 and Hcount<558)or
(HCount>577 and Hcount<611))then
vga_gameover_en<='1';
end if;
elsif(VCount=224)then
if((HCount>197 and Hcount<204)or(HCount>221 and Hcount<239)or
(HCount>257 and Hcount<263)or(HCount>276 and Hcount<283)or
(HCount>301 and Hcount<307)or(HCount>314 and Hcount<321)or
(HCount>326 and Hcount<332)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<385)or(HCount>431 and Hcount<438)or
(HCount>468 and Hcount<475)or(HCount>492 and Hcount<499)or
(HCount>507 and Hcount<514)or(HCount>532 and Hcount<558)or
(HCount>577 and Hcount<610))then
vga_gameover_en<='1';
end if;
elsif(VCount=225)then
if((HCount>197 and Hcount<204)or(HCount>221 and Hcount<239)or
(HCount>256 and Hcount<263)or(HCount>276 and Hcount<283)or
(HCount>301 and Hcount<307)or(HCount>314 and Hcount<321)or
(HCount>326 and Hcount<331)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<385)or(HCount>431 and Hcount<438)or
(HCount>468 and Hcount<475)or(HCount>492 and Hcount<499)or
(HCount>507 and Hcount<513)or(HCount>532 and Hcount<558)or
(HCount>577 and Hcount<608))then
vga_gameover_en<='1';
end if;
elsif(VCount=226)then
if((HCount>197 and Hcount<204)or(HCount>221 and Hcount<239)or
(HCount>256 and Hcount<262)or(HCount>277 and Hcount<284)or
(HCount>301 and Hcount<307)or(HCount>315 and Hcount<322)or
(HCount>325 and Hcount<331)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<366)or(HCount>431 and Hcount<438)or
(HCount>468 and Hcount<475)or(HCount>492 and Hcount<500)or
(HCount>506 and Hcount<513)or(HCount>532 and Hcount<539)or
(HCount>558 and Hcount<558)or(HCount>577 and Hcount<605))then
vga_gameover_en<='1';
end if;
elsif(VCount=227)then
if((HCount>198 and Hcount<205)or(HCount>221 and Hcount<239)or
(HCount>255 and Hcount<284)or(HCount>301 and Hcount<307)or
(HCount>316 and Hcount<322)or(HCount>325 and Hcount<330)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>432 and Hcount<439)or(HCount>468 and Hcount<475)or
(HCount>493 and Hcount<500)or(HCount>506 and Hcount<512)or
(HCount>532 and Hcount<539)or(HCount>577 and Hcount<584)or
(HCount>596 and Hcount<604))then
vga_gameover_en<='1';
end if;
elsif(VCount=228)then
if((HCount>198 and Hcount<205)or(HCount>221 and Hcount<239)or
(HCount>255 and Hcount<285)or(HCount>301 and Hcount<307)or
(HCount>316 and Hcount<330)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<366)or(HCount>432 and Hcount<439)or
(HCount>467 and Hcount<474)or(HCount>493 and Hcount<500)or
(HCount>505 and Hcount<512)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>597 and Hcount<605))then
vga_gameover_en<='1';
end if;
elsif(VCount=229)then
if((HCount>198 and Hcount<205)or(HCount>221 and Hcount<239)or
(HCount>254 and Hcount<285)or(HCount>301 and Hcount<307)or
(HCount>317 and Hcount<329)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<366)or(HCount>432 and Hcount<439)or
(HCount>467 and Hcount<474)or(HCount>494 and Hcount<501)or
(HCount>505 and Hcount<511)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>598 and Hcount<605))then
vga_gameover_en<='1';
end if;
elsif(VCount=230)then
if((HCount>198 and Hcount<206)or(HCount>234 and Hcount<239)or
(HCount>254 and Hcount<286)or(HCount>301 and Hcount<307)or
(HCount>317 and Hcount<329)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<366)or(HCount>433 and Hcount<440)or
(HCount>466 and Hcount<474)or(HCount>494 and Hcount<501)or
(HCount>504 and Hcount<511)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>599 and Hcount<606))then
vga_gameover_en<='1';
end if;
elsif(VCount=231)then
if((HCount>199 and Hcount<207)or(HCount>234 and Hcount<239)or
(HCount>253 and Hcount<286)or(HCount>301 and Hcount<307)or
(HCount>318 and Hcount<328)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<366)or(HCount>433 and Hcount<441)or
(HCount>466 and Hcount<473)or(HCount>495 and Hcount<502)or
(HCount>504 and Hcount<510)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>599 and Hcount<607))then
vga_gameover_en<='1';
end if;
elsif(VCount=232)then
if((HCount>199 and Hcount<207)or(HCount>234 and Hcount<239)or
(HCount>253 and Hcount<259)or(HCount>279 and Hcount<287)or
(HCount>301 and Hcount<307)or(HCount>318 and Hcount<328)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>433 and Hcount<441)or(HCount>465 and Hcount<473)or
(HCount>495 and Hcount<510)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>600 and Hcount<608))then
vga_gameover_en<='1';
end if;
elsif(VCount=233)then
if((HCount>200 and Hcount<209)or(HCount>234 and Hcount<239)or
(HCount>253 and Hcount<259)or(HCount>280 and Hcount<287)or
(HCount>301 and Hcount<307)or(HCount>319 and Hcount<327)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>434 and Hcount<442)or(HCount>464 and Hcount<472)or
(HCount>496 and Hcount<509)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>601 and Hcount<608))then
vga_gameover_en<='1';
end if;
elsif(VCount=234)then
if((HCount>200 and Hcount<210)or(HCount>234 and Hcount<239)or
(HCount>252 and Hcount<258)or(HCount>280 and Hcount<288)or
(HCount>301 and Hcount<307)or(HCount>319 and Hcount<326)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>435 and Hcount<443)or(HCount>463 and Hcount<472)or
(HCount>496 and Hcount<509)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>602 and Hcount<609))then
vga_gameover_en<='1';
end if;
elsif(VCount=235)then
if((HCount>201 and Hcount<211)or(HCount>232 and Hcount<239)or
(HCount>252 and Hcount<258)or(HCount>281 and Hcount<288)or
(HCount>301 and Hcount<307)or(HCount>320 and Hcount<326)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<366)or
(HCount>435 and Hcount<445)or(HCount>461 and Hcount<471)or
(HCount>497 and Hcount<508)or(HCount>532 and Hcount<539)or
(HCount>577 and Hcount<584)or(HCount>602 and Hcount<610))then
vga_gameover_en<='1';
end if;
elsif(VCount=236)then
if((HCount>202 and Hcount<214)or(HCount>229 and Hcount<241)or
(HCount>251 and Hcount<257)or(HCount>281 and Hcount<289)or
(HCount>301 and Hcount<307)or(HCount>320 and Hcount<325)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<395)or
(HCount>436 and Hcount<447)or(HCount>459 and Hcount<470)or
(HCount>497 and Hcount<508)or(HCount>532 and Hcount<568)or
(HCount>577 and Hcount<584)or(HCount>603 and Hcount<611))then
vga_gameover_en<='1';
end if;
elsif(VCount=237)then
if((HCount>203 and Hcount<240)or(HCount>251 and Hcount<257)or
(HCount>282 and Hcount<289)or(HCount>301 and Hcount<307)or
(HCount>321 and Hcount<325)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<395)or(HCount>437 and Hcount<469)or
(HCount>498 and Hcount<508)or(HCount>532 and Hcount<568)or
(HCount>577 and Hcount<584)or(HCount>604 and Hcount<611))then
vga_gameover_en<='1';
end if;
elsif(VCount=238)then
if((HCount>204 and Hcount<238)or(HCount>250 and Hcount<256)or
(HCount>282 and Hcount<290)or(HCount>301 and Hcount<307)or
(HCount>321 and Hcount<324)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<395)or(HCount>438 and Hcount<468)or
(HCount>498 and Hcount<507)or(HCount>532 and Hcount<568)or
(HCount>577 and Hcount<584)or(HCount>604 and Hcount<612))then
vga_gameover_en<='1';
end if;
elsif(VCount=239)then
if((HCount>205 and Hcount<236)or(HCount>250 and Hcount<256)or
(HCount>283 and Hcount<290)or(HCount>301 and Hcount<307)or
(HCount>322 and Hcount<324)or(HCount>339 and Hcount<346)or
(HCount>359 and Hcount<395)or(HCount>439 and Hcount<467)or
(HCount>498 and Hcount<507)or(HCount>532 and Hcount<568)or
(HCount>577 and Hcount<584)or(HCount>605 and Hcount<613))then
vga_gameover_en<='1';
end if;
elsif(VCount=240)then
if((HCount>207 and Hcount<234)or(HCount>249 and Hcount<256)or
(HCount>283 and Hcount<291)or(HCount>301 and Hcount<307)or
(HCount>339 and Hcount<346)or(HCount>359 and Hcount<395)or
(HCount>441 and Hcount<466)or(HCount>498 and Hcount<507)or
(HCount>532 and Hcount<568)or(HCount>577 and Hcount<584)or
(HCount>606 and Hcount<614))then
vga_gameover_en<='1';
end if;
elsif(VCount=241)then
if((HCount>209 and Hcount<231)or(HCount>248 and Hcount<256)or
(HCount>282 and Hcount<292)or(HCount>300 and Hcount<307)or
(HCount>339 and Hcount<346)or(HCount>358 and Hcount<395)or
(HCount>443 and Hcount<464)or(HCount>498 and Hcount<507)or
(HCount>531 and Hcount<568)or(HCount>576 and Hcount<584)or
(HCount>606 and Hcount<615))then
vga_gameover_en<='1';
end if;
elsif(VCount=242)then
if((HCount>212 and Hcount<228)or(HCount>247 and Hcount<258)or
(HCount>281 and Hcount<294)or(HCount>299 and Hcount<309)or
(HCount>337 and Hcount<348)or(HCount>357 and Hcount<395)or
(HCount>445 and Hcount<461)or(HCount>497 and Hcount<509)or
(HCount>530 and Hcount<568)or(HCount>575 and Hcount<586)or
(HCount>604 and Hcount<617))then
vga_gameover_en<='1';
end if;
elsif(VCount=243)then
if((HCount>216 and Hcount<223)or(HCount>450 and Hcount<456))then
vga_gameover_en<='1';
end if;
end if;
end process GAMEOVER;
---------------------player life-------------------------------------
PLAYER_STATUS:process(HCount,VCount)
begin
vga_player_life_en<='0';
if(VCount>115 and VCount<162)then
if(HCount<801 and HCount<PLAYER_LIFE)then
vga_player_life_en<='1';
end if;
end if;
end process PLAYER_STATUS;
---------------------------------------------------------------------
SCREEN:process(HCount,VCount,HEnable,VEnable)
begin
if (HEnable='1' and VEnable='1') then
if(vga_framework_en='1')then
ColorR<=(others=>'1');
ColorG<=(others=>'1');
ColorB<=(others=>'1');
elsif(gameover_en='1')then
if(VCount>60)then
if(vga_gameover_en='1')then
ColorR<=(others=>'0');
ColorG<=(others=>'0');
ColorB<=(others=>'0');
else
ColorR<=(others=>'1');
ColorG<=(others=>'1');
ColorB<=(others=>'1');
end if;
end if;
elsif(vga_player_life_en='1')then
ColorR<=(others=>'1');
ColorG<=(others=>'1');
ColorB<=(others=>'1');
elsif(vga_alien_en(0)='1' or vga_alien_en(1)='1' or vga_alien_en(2)='1')then
ColorR<=(others=>'1');
ColorG<=(others=>'1');
ColorB<=(others=>'1');
elsif(vga_missile_en='1')then
ColorR<=(others=>'1');
ColorG<=(others=>'1');
ColorB<=(others=>'1');
elsif(vga_player_en='1')then
ColorR<=(others=>'1');
ColorG<=(others=>'1');
ColorB<=(others=>'1');
else
ColorR<=(others=>'0');
ColorG<=(others=>'0');
ColorB<=(others=>'0');
end if;
else
ColorR<=(others=>'0');
ColorG<=(others=>'0');
ColorB<=(others=>'0');
end if;
end process SCREEN;
end behave; | bsd-2-clause | cb1274a043227ab049dc4397963a78e2 | 0.680774 | 3.108307 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_rom1.vhd | 2 | 6,226 | -- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom1 IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_rom1;
ARCHITECTURE SYN OF lpm_rom1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "PhaseSelectErr.mif",
intended_device_family => "Arria GX",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PhSe",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 8,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PhSe"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "PhaseSelectErr.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "PhaseSelectErr.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PhSe"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | 24224514a14f149ad0e30c9a9c5745df | 0.672342 | 3.541524 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openMAC_cmp.vhd | 3 | 5,908 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openMAC_cmp is
generic(
mac_time_width_g : integer := 32;
gen2ndCmpTimer_g : boolean := false;
pulseWidth2ndCmpTimer_g : integer := 9;
genPulse2ndCmpTimer_g : boolean := false
);
port(
clk : in std_logic;
rst : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end openMAC_cmp;
architecture rtl of openMAC_cmp is
signal cmp_enable, tog_enable : std_logic;
signal cmp_value, tog_value : std_logic_vector(mac_time'range);
signal tog_counter_value : std_logic_vector(pulseWidth2ndCmpTimer_g-1 downto 0);
signal tog_counter_preset : std_logic_vector(pulseWidth2ndCmpTimer_g-1 downto 0);
signal irq_s, toggle_s : std_logic;
begin
irq <= irq_s;
toggle <= toggle_s;
process(clk, rst)
begin
if rst = '1' then
cmp_enable <= '0'; cmp_value <= (others => '0'); irq_s <= '0';
if gen2ndCmpTimer_g = TRUE then
tog_enable <= '0'; tog_value <= (others => '0'); toggle_s <= '0';
if genPulse2ndCmpTimer_g = TRUE then
tog_counter_value <= (others => '0');
tog_counter_preset <= (others => '0');
end if;
end if;
elsif clk = '1' and clk'event then
--cmp
if cmp_enable = '1' and mac_time = cmp_value then
irq_s <= '1';
end if;
--tog
if tog_enable = '1' and mac_time = tog_value and gen2ndCmpTimer_g = TRUE then
toggle_s <= not toggle_s;
if genPulse2ndCmpTimer_g = TRUE then
tog_counter_value <= tog_counter_preset;
end if;
end if;
if tog_enable = '1' and toggle_s = '1'
and (not (tog_counter_value = conv_std_logic_vector(0, tog_counter_value'length)))
and gen2ndCmpTimer_g = TRUE
and genPulse2ndCmpTimer_g = TRUE then
tog_counter_value <= tog_counter_value - 1;
if tog_counter_value = conv_std_logic_vector(1, tog_counter_value'length) then
toggle_s <= '0';
end if;
end if;
--memory mapping
if wr = '1' then
case addr is
when "00" =>
cmp_value <= din;
irq_s <= '0';
when "01" =>
cmp_enable <= din(0);
when "10" =>
if gen2ndCmpTimer_g = TRUE then
tog_value <= din;
end if;
when "11" =>
if gen2ndCmpTimer_g = TRUE then
tog_enable <= din(0);
if genPulse2ndCmpTimer_g = TRUE then
tog_counter_preset <= din(pulseWidth2ndCmpTimer_g downto 1);
end if;
end if;
when others =>
--go and get a coffee...
end case;
end if;
end if;
end process;
dout <=
mac_time when addr = "00" else
x"000000" & "00" & "00" & "00" & irq_s & cmp_enable when addr = "01" else
tog_value when addr = "10" and gen2ndCmpTimer_g = TRUE else
x"000000" & "00" & "00" & "00" & toggle_s & tog_enable when addr = "11" and gen2ndCmpTimer_g = TRUE else
mac_time; --otherwise give me the current time...
end rtl;
| gpl-2.0 | a63435629f5f6edefa0ab2cc7c56b4d9 | 0.527759 | 4.340926 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part5/M21EDAversion/char_7seg.vhd | 1 | 474 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;
ARCHITECTURE Behavior OF char_7seg IS
BEGIN -- Behavior
-- from our truth table
-- B=C(0), A=C(1)
Display(0) <= NOT(C(0)) OR C(1);
Display(1) <= C(0);
Display(2) <= C(0);
Display(3) <= C(1);
Display(4) <= C(1);
Display(5) <= NOT(C(0)) OR C(1);
Display(6) <= C(1);
END Behavior; | unlicense | a2540c2d5563110d613a21347768a020 | 0.590717 | 2.494737 | false | false | false | false |
Voveky/WSIAUSB | wsiaUSBlib/wsiaDescriptors.vhd | 1 | 10,230 | --wsiaDescriptors
--a library required by wsiaUSB DE2 ISP1362 USB firmware by Tony Slagle
library ieee, wsiaUSBlib;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use wsiaUSBlib.wsiaUseful.all;
package wsiaDescriptors is
--=-=-=-=-=-TYPE DECLARATIONS-=-=-=-=-=--
type deviceDescriptor is
record
bLength : byte;--:=x"12";
bDescriptorType : byte;--:=x"01";
bcdUSB : word;--:=x"0200";
bDeviceClass : byte;--:=x"FF";
bDeviceSubClass : byte;--:=x"FF";
bDeviceProtocol : byte;--:=x"FF";
bMaxPacketSize0 : byte;--:=x"40";
idVendor : word;--:=x"7777";
idProduct : word;--:=x"7777";
bcdDevice : word;--:=x"0010";
iManufacturer : byte;--:=x"01";
iProduct : byte;--:=x"02";
iSerialNumber : byte;--:=x"00";
bNumConfigs : byte;--:=x"01";
end record;
type configurationDescriptor is
record
bLength : byte;--:=x"09";
bDescriptorType : byte;--:=x"02";
wTotalLength : word;--:=std_logic_vector(unsigned(9+)); --FIXMEFIXMEFIXME
bNumInterfaces : byte;--:=x"02";
bConfigValue : byte;--:=x"01";
iConfiguration : byte;--:=x"00";
bmAttributes : byte;--:=x"C0";
bMaxPower : byte;--:=x"00";
end record;
type interfaceDescriptor is
record
bLength : byte;--:=x"09";
bDescriptorType : byte;--:=x"04";
bInterfaceNumber : byte;--:=x"00";
bAlternateSetting : byte;--;
bNumEndpoints : byte;--;
bInterfaceClass : byte;--:=x"FF";
bInterfaceSubClass : byte;--:=x"FF";
bInterfaceProtocol : byte;--:=x"FF";
iInterface : byte;--:=x"00";
end record;
type endpointDescriptor is
record
bLength : byte;--:=x"07";
bDescriptorType : byte;--:=x"05";
bEndpointAddress: byte;
bmAttributes : byte;
wMaxPacketSize : word;
bInterval : byte;--:=x"01";
end record;
--constant assembled_configuration_descriptor : std_logic_vector(0 to 8*(9 + 2*9 + 5*7)-1):=dizzy_indian(cfgDesc & intDesc1 & intDesc2 & ep1Desc & ep2Desc & ep3Desc & ep4Desc & ep5Desc);
--=-=-=-=-=-DESCRIPTOR TYPES-=-=-=-=-=--
constant desc_DEVICE : byte := x"01";
constant desc_CONFIGURATION : byte := x"02";
constant desc_STRING : byte := x"03";
constant desc_INTERFACE : byte := x"04";
constant desc_ENDPOINT : byte := x"05";
constant desc_DEVICE_QUALIFIER : byte := x"06";
constant desc_OTHER_SPEED_CFG : byte := x"07";
constant desc_INTERFACE_POWER : byte := x"08";
constant CRD_devDesc : deviceDescriptor:=(bLength => x"12",
bDescriptorType => desc_DEVICE,
bcdUSB => x"0200",
bDeviceClass => x"FF",
bDeviceSubClass => x"FF",
bDeviceProtocol => x"FF",
bMaxPacketSize0 => x"40",
idVendor => x"7777",
idProduct => x"7777",
bcdDevice => x"0091",
iManufacturer => x"01",
iProduct => x"02",
iSerialNumber => x"00",
bNumConfigs =>x"01");
constant CRD_strDesc_00_Langs : std_logic_vector(0 to (2+2)*8-1) :=x"04030904";
constant CRD_strDesc_01_Vendor : std_logic_vector(0 to (36+2)*8-1) :=x"260354006F006E007900200053006C00610067006C0065002000610074002000410053005500";
constant CRD_strDesc_02_Product : std_logic_vector(0 to (34+2)*8-1) :=x"240350004F00530020005500530042002000430052004400200042006F00610072006400";
constant CRD_strDesc_03_Serial : std_logic_vector(0 to (44+2)*8-1) :=x"2E0300430065007200650061006C0020004E006F00200042003400550032006500610074004E0052006C00610062";
--constant CRD_strDesc_: std_logic_vector(0 to (decimalLength+2)*8-1):=x"hexLength03
constant CRD_cfg1Desc : configurationDescriptor:=(bLength =>x"09",
bDescriptorType =>x"02",
wTotalLength =>to_vec(16,(9+9+7*2)),
bNumInterfaces =>x"01",
bConfigValue =>x"01",
iConfiguration =>x"00",
bmAttributes =>x"C0",
bMaxPower =>x"32");
constant CRD_cfg2Desc : configurationDescriptor:=(bLength =>x"09",
bDescriptorType =>x"02",
wTotalLength =>to_vec(16,(9+9+7*5)),
bNumInterfaces =>x"01",
bConfigValue =>x"02",
iConfiguration =>x"00",
bmAttributes =>x"C0",
bMaxPower =>x"32");
constant CRD_cfgDesc : configurationDescriptor:=(bLength =>x"09",
bDescriptorType =>x"02",
wTotalLength =>to_vec(16,(9+9+9+7*5)),
bNumInterfaces =>x"02",
bConfigValue =>x"01",
iConfiguration =>x"00",
bmAttributes =>x"C0",
bMaxPower =>x"32");
constant CRD_int1Desc : interfaceDescriptor:=(bLength =>x"09",
bDescriptorType =>x"04",
bInterfaceNumber =>x"00",
bAlternateSetting =>x"00",
bNumEndpoints =>x"02",
bInterfaceClass =>x"FF",
bInterfaceSubClass =>x"FF",
bInterfaceProtocol =>x"FF",
iInterface =>x"00");
constant CRD_int2Desc : interfaceDescriptor:=(bLength =>x"09",
bDescriptorType =>x"04",
bInterfaceNumber =>x"00",
bAlternateSetting =>x"01",
bNumEndpoints =>x"05",
bInterfaceClass =>x"FF",
bInterfaceSubClass =>x"FF",
bInterfaceProtocol =>x"FF",
iInterface =>x"00");
constant CRD_endp1Desc : endpointDescriptor:=( bLength =>x"07",
bDescriptorType =>x"05",
bEndpointAddress=>x"01",
bmAttributes =>x"02",
wMaxPacketSize =>x"0040",
bInterval =>x"01");
constant CRD_endp2Desc : endpointDescriptor:=( bLength =>x"07",
bDescriptorType =>x"05",
bEndpointAddress=>x"82",
bmAttributes =>x"02",
wMaxPacketSize =>x"0040",
bInterval =>x"01");
constant CRD_endp3Desc : endpointDescriptor:=( bLength =>x"07",
bDescriptorType =>x"05",
bEndpointAddress=>x"03",
bmAttributes =>x"03",
wMaxPacketSize =>x"0010",
bInterval =>x"01");
constant CRD_endp4Desc : endpointDescriptor:=( bLength =>x"07",
bDescriptorType =>x"05",
bEndpointAddress=>x"84",
bmAttributes =>x"03",
wMaxPacketSize =>x"0010",
bInterval =>x"01");
constant CRD_endp5Desc : endpointDescriptor:=( bLength =>x"07",
bDescriptorType =>x"05",
bEndpointAddress=>x"85",
bmAttributes =>x"01",
wMaxPacketSize =>x"07FF",
bInterval =>x"01");
--not a descriptor, is the endpoint configuration bytes for DcEndpointConfiguration registers
constant DcEndpointConfiguration: byte16:= ("10000011",--ctrlOut
"11000011",--ctrlIn
"10000011",--64b Bulk Out
"11000011",--64b Bulk In
"10000001",--16b Int Out
"11000001",--16b Int In
"11111111",--1023b Iso In (dblBuff)
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
function byte_deviceDescriptor( constant descrip: in deviceDescriptor ) return std_logic_vector;
function byte_configurationDescriptor( constant descrip: in configurationDescriptor ) return std_logic_vector;
function byte_interfaceDescriptor( constant descrip: in interfaceDescriptor ) return std_logic_vector;
function byte_endpointDescriptor( constant descrip: in endpointDescriptor ) return std_logic_vector;
constant CRD_Full_Cfg1_Desc:std_logic_vector(1 to 8*(9+9+7*2)):=(
byte_configurationDescriptor(CRD_cfg1Desc) &
byte_interfaceDescriptor(CRD_int1Desc) &
byte_endpointDescriptor(CRD_endp1Desc) &
byte_endpointDescriptor(CRD_endp2Desc));
constant CRD_Full_Cfg2_Desc:std_logic_vector(1 to 8*(9+9+7*5)):=(
byte_configurationDescriptor(CRD_cfg2Desc) &
byte_interfaceDescriptor(CRD_int2Desc) &
byte_endpointDescriptor(CRD_endp1Desc) &
byte_endpointDescriptor(CRD_endp2Desc) &
byte_endpointDescriptor(CRD_endp3Desc) &
byte_endpointDescriptor(CRD_endp4Desc) &
byte_endpointDescriptor(CRD_endp5Desc));
constant CRD_Full_Cfg_Desc:std_logic_vector(1 to 8*(9+9+9+7*5)):=(
byte_configurationDescriptor(CRD_cfgDesc) &
byte_interfaceDescriptor(CRD_int1Desc) &
byte_interfaceDescriptor(CRD_int2Desc) &
byte_endpointDescriptor(CRD_endp1Desc) &
byte_endpointDescriptor(CRD_endp2Desc) &
byte_endpointDescriptor(CRD_endp3Desc) &
byte_endpointDescriptor(CRD_endp4Desc) &
byte_endpointDescriptor(CRD_endp5Desc));
end wsiaDescriptors;
package body wsiaDescriptors is
function byte_deviceDescriptor( constant d: in deviceDescriptor ) return std_logic_vector is
begin
return( d.bLength &
d.bDescriptorType &
d.bcdUSB(7 downto 0) &
d.bcdUSB(15 downto 8) &
d.bDeviceClass &
d.bDeviceSubClass &
d.bDeviceProtocol &
d.bMaxPacketSize0 &
d.idVendor(7 downto 0) &
d.idVendor(15 downto 8) &
d.idProduct(7 downto 0) &
d.idProduct(15 downto 8) &
d.bcdDevice(7 downto 0) &
d.bcdDevice(15 downto 8) &
d.iManufacturer &
d.iProduct &
d.iSerialNumber &
d.bNumConfigs);
end function byte_deviceDescriptor;
function byte_configurationDescriptor( constant d: in configurationDescriptor ) return std_logic_vector is
begin
return( d.bLength &
d.bDescriptorType &
d.wTotalLength(7 downto 0) &
d.wTotalLength(15 downto 8) &
d.bNumInterfaces &
d.bConfigValue &
d.iConfiguration &
d.bmAttributes &
d.bMaxPower);
end function byte_configurationDescriptor;
function byte_interfaceDescriptor( constant d: in interfaceDescriptor ) return std_logic_vector is
begin
return( d.bLength &
d.bDescriptorType &
d.bInterfaceNumber &
d.bAlternateSetting &
d.bNumEndpoints &
d.bInterfaceClass &
d.bInterfaceSubClass &
d.bInterfaceProtocol &
d.iInterface);
end function byte_interfaceDescriptor;
function byte_endpointDescriptor( constant d: in endpointDescriptor ) return std_logic_vector is
begin
return( d.bLength &
d.bDescriptorType &
d.bEndpointAddress &
d.bmAttributes &
d.wMaxPacketSize(7 downto 0) &
d.wMaxPacketSize(15 downto 8) &
d.bInterval);
end function byte_endpointDescriptor;
end wsiaDescriptors; | mit | 5903625c4f15b9dd9364239fc8b107ad | 0.637439 | 3.361814 | false | true | false | false |
Voveky/WSIAUSB | wsiaUSBlib/wsiaUseful.vhd | 1 | 9,332 | --wsiaUSBlib
--a library required by wsiaUSB DE2 ISP1362 USB firmware by Tony Slagle
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
package wsiaUseful is
--=-=-=-=-=-TYPE DECLARATIONS-=-=-=-=-=--
type enum_state is (default, address, configured);
subtype nibble is std_logic_vector(3 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype dword is std_logic_vector(31 downto 0);
subtype buffer64 is std_logic_vector(0 to 8*64-1);
subtype buffer16 is std_logic_vector(0 to 8*16-1);
subtype descript9 is std_logic_vector(0 to 8*9-1);
subtype descript7 is std_logic_vector(0 to 8*7-1);
type byte8 is array(0 to 7) of byte;
type byte16 is array(0 to 15) of byte;
type byte32 is array(0 to 31) of byte;
type word8 is array(0 to 7) of word;
type word16 is array(0 to 15) of word;
type word32 is array(0 to 31) of word;
type setup_packet_type is
record
bmRequestType : byte;
bRequest : byte;
wValue : word;
wIndex : word;
wLength : word;
end record;
--type worker_states is (settle, idle, send_data, CRread, CRwrite, rd_word, wr_word, wr_cmd, rcv_setup);
type worker_states is (send_data, CRread, CRwrite, rd_word, wr_word, wr_cmd, rcv_setup);
function dizzy_indian ( constant data: in std_logic_vector ) return std_logic_vector;
function to_int ( a: std_logic_vector ) return integer;
function to_vec ( size: integer; val: integer ) return std_logic_vector;
function bigger ( l,r:std_logic_vector ) return std_logic_vector;
function smaller ( l,r:std_logic_vector ) return std_logic_vector;
--=-=-=-=-=-CONSTANT DECLARATIONS-=-=-=-=-=--
constant h0, CtrlOut: std_logic_vector(3 downto 0) := "0000"; constant h1, CtrlIn: std_logic_vector(3 downto 0):= "0001";
constant h2, ep1 : std_logic_vector(3 downto 0) := "0010"; constant h3, ep2 : std_logic_vector(3 downto 0) := "0011";
constant h4, ep3 : std_logic_vector(3 downto 0) := "0100"; constant h5, ep4 : std_logic_vector(3 downto 0) := "0101";
constant h6, ep5 : std_logic_vector(3 downto 0) := "0110"; constant h7, ep6 : std_logic_vector(3 downto 0) := "0111";
constant h8, ep7 : std_logic_vector(3 downto 0) := "1000"; constant h9, ep8 : std_logic_vector(3 downto 0) := "1001";
constant hA, ep9 : std_logic_vector(3 downto 0) := "1010"; constant hB, ep10: std_logic_vector(3 downto 0) := "1011";
constant hC, ep11 : std_logic_vector(3 downto 0) := "1100"; constant hD, ep12: std_logic_vector(3 downto 0) := "1101";
constant hE, ep13 : std_logic_vector(3 downto 0) := "1110"; constant hF, ep14: std_logic_vector(3 downto 0) := "1111";
--=-=-=-=-=-STANDARD REQUESTS-=-=-=-=-=--
constant GET_STATUS : std_logic_vector(7 downto 0) := h0 & h0;
constant CLEAR_FEATURE : std_logic_vector(7 downto 0) := h0 & h1;
constant SET_FEATURE : std_logic_vector(7 downto 0) := h0 & h3;
constant SET_ADDRESS : std_logic_vector(7 downto 0) := h0 & h5;
constant GET_DESCRIPTOR : std_logic_vector(7 downto 0) := h0 & h6;
constant SET_DESCRIPTOR : std_logic_vector(7 downto 0) := h0 & h7;
constant GET_CONFIGURATION : std_logic_vector(7 downto 0) := h0 & h8;
constant SET_CONFIGURATION : std_logic_vector(7 downto 0) := h0 & h9;
constant GET_INTERFACE : std_logic_vector(7 downto 0) := h0 & hA;
constant SET_INTERFACE : std_logic_vector(7 downto 0) := h0 & hB;
constant SYNCH_FRAME_E : std_logic_vector(7 downto 0) := h0 & hC;
constant CFG_DEVICE : std_logic_vector(3 downto 0) := h0;
constant CFG_INTERFACE : std_logic_vector(3 downto 0) := h1;
constant CFG_ENDPOINT : std_logic_vector(3 downto 0) := h2;
--=-=-=-=-=-COMMANDS-=-=-=-=-=--
constant Wr_DcEndpointConfiguration : std_logic_vector(15 downto 4) := h0 & h0 & h2; --20h = control out
constant Rd_DcEndpointConfiguration : std_logic_vector(15 downto 4) := h0 & h0 & h3; --30h = control out
constant Wr_DcAddress : std_logic_vector(15 downto 0) := h0 & h0 & hB & h6; --B6h
constant Rd_DcAddress : std_logic_vector(15 downto 0) := h0 & h0 & hB & h7; --B7h
constant Wr_DcMode : std_logic_vector(15 downto 0) := h0 & h0 & hB & h8; --B8h
constant Rd_DcMode : std_logic_vector(15 downto 0) := h0 & h0 & hB & h9; --B9h
constant Wr_DcHardwareConfiguration : std_logic_vector(15 downto 0) := h0 & h0 & hB & hA; --BAh
constant Rd_DcHardwareConfiguration : std_logic_vector(15 downto 0) := h0 & h0 & hB & hB; --BBh
constant Wr_DcInterruptEnable : std_logic_vector(15 downto 0) := h0 & h0 & hC & h2; --C2h
constant Rd_DcInterruptEnable : std_logic_vector(15 downto 0) := h0 & h0 & hC & h3; --C3h
constant Wr_DcDMAConfiguration : std_logic_vector(15 downto 0) := h0 & h0 & hF & h0; --F0h
constant Rd_DcDMAConfiguration : std_logic_vector(15 downto 0) := h0 & h0 & hF & h1; --F1h
constant Wr_DcDMACounter : std_logic_vector(15 downto 0) := h0 & h0 & hF & h2; --F2h
constant Rd_DcDMACounter : std_logic_vector(15 downto 0) := h0 & h0 & hF & h3; --F3h
constant Reset : std_logic_vector(15 downto 0) := h0 & h0 & hF & h6; --F6h
constant Wr_Buffer : std_logic_vector(15 downto 4) := h0 & h0 & h0; --00h = control out (0 illegal)
constant Rd_Buffer : std_logic_vector(15 downto 4) := h0 & h0 & h1; --10h = control out (1 illegal)
constant Rd_ESR : std_logic_vector(15 downto 4) := h0 & h0 & h5; --50h = control out
constant Stall : std_logic_vector(15 downto 4) := h0 & h0 & h4; --40h = control out
constant Unstall : std_logic_vector(15 downto 4) := h0 & h0 & h8; --80h = control out
constant Validate : std_logic_vector(15 downto 4) := h0 & h0 & h6; --60h = control out (0 illegal)
constant ClearBuffer : std_logic_vector(15 downto 4) := h0 & h0 & h7; --70h = control out (1 illegal)
constant Rd_DcEndpointStatusImage : std_logic_vector(15 downto 4) := h0 & h0 & hD; --D0h = control out
constant AcknowledgeSetup : std_logic_vector(15 downto 0) := h0 & h0 & hF & h4; --F4h (must ack setups sec12.3.6)
constant Rd_ErrorCode : std_logic_vector(15 downto 4) := h0 & h0 & hA; --A0h = control out
constant UnlockDevice : std_logic_vector(15 downto 0) := h0 & h0 & hB & h0; --B0h
constant Wr_DcScratchRegister : std_logic_vector(15 downto 0) := h0 & h0 & hB & h2; --B2h
constant Rd_DcScratchRegister : std_logic_vector(15 downto 0) := h0 & h0 & hB & h3; --B3h
constant Rd_DcFrameNumber : std_logic_vector(15 downto 0) := h0 & h0 & hB & h4; --B4h
constant Rd_DcChipID : std_logic_vector(15 downto 0) := h0 & h0 & hB & h5; --B5h
constant Rd_DcInterrupt : std_logic_vector(15 downto 0) := h0 & h0 & hC & h0; --C0h
end wsiaUseful;
package body wsiaUseful is
function dizzy_indian( constant data: in std_logic_vector ) return std_logic_vector is
--flips byte order s.t. B0 B1 B2 B3 B4 would yield B1 B0 B3 B2 B? B4 where b? is a filler byte
--always returns an even number of bytes
variable num : integer;
variable outval : std_logic_vector(0 to data'LENGTH-1);
begin
for i in 0 to (data'LENGTH)/16-1 loop
outval(i*16 to (i*16)+15):= data(i*16+8 to i*16+15) & data(i*16 to i*16+7);
end loop;
return outval;
end function dizzy_indian;
function to_int (a: std_logic_vector) return integer is
alias av: std_logic_vector (1 to a'length) is a;
variable val: integer := 0;
variable b: integer := 1;
begin
for i in a'length downto 1 loop
if (av(i) = '1') then -- if LSB is '1',
val := val + b; -- add value for current bit position
end if;
b := b * 2; -- Shift left 1 bit
end loop;
return val;
end function to_int;
function to_vec (size: integer; val: integer) return std_logic_vector is
variable vec: std_logic_vector (1 to size);
variable a: integer;
begin
a := val;
for i in size downto 1 loop
if ((a mod 2) = 1) then
vec(i) := '1';
else
vec(i) := '0';
end if;
a := a / 2;
end loop;
return vec;
end function to_vec;
function bigger( l,r:std_logic_vector ) return std_logic_vector is
alias ll :std_logic_vector(l'length-1 downto 0) is l;
alias rr :std_logic_vector(r'length-1 downto 0) is r;
begin
if l'length > r'length then
if to_int(ll(l'length-1 downto r'length))/=0 then
return(ll);
else
if to_int(ll(r'length-1 downto 0)) < to_int(rr) then
return(ll(l'length-1 downto r'length) & rr);
else
return(ll);
end if;
end if;
elsif r'LENGTH > l'LENGTH then
if to_int(rr(r'length-1 downto l'length))/=0 then
return(rr);
else
if to_int(rr(l'length-1 downto 0)) < to_int(ll) then
return(rr(r'length-1 downto l'length) & ll);
else
return(rr);
end if;
end if;
else
if ll > rr then
return(ll);
else
return(rr);
end if;
end if;
end function bigger;
function smaller( l,r:std_logic_vector ) return std_logic_vector is
alias ll :std_logic_vector(l'length-1 downto 0) is l;
alias rr :std_logic_vector(r'length-1 downto 0) is r;
begin
if l'length > r'length then
if to_int(ll) > to_int(rr) then
return(to_vec(l'length,to_int(rr)));
else
return(ll);
end if;
elsif r'length > l'length then
if to_int(rr) > to_int(ll) then
return(to_vec(r'length,to_int(ll)));
else
return(rr);
end if;
else
if ll < rr then
return(ll);
else
return(rr);
end if;
end if;
end function smaller;
end wsiaUseful;
| mit | 7389493e470d349a9de6d289c9c2925f | 0.655165 | 2.671629 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openMAC.vhd | 3 | 66,424 | -------------------------------------------------------------------------------
-- OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY OpenMAC IS
GENERIC( HighAdr : IN integer := 16;
Timer : IN boolean := false;
TxSyncOn : IN boolean := false;
TxDel : IN boolean := false;
Simulate : IN boolean := false
);
PORT ( Rst, Clk : IN std_logic;
-- Processor
s_nWr, Sel_Ram, Sel_Cont : IN std_logic := '0';
S_nBe : IN std_logic_vector( 1 DOWNTO 0);
S_Adr : IN std_logic_vector(10 DOWNTO 1);
S_Din : IN std_logic_vector(15 DOWNTO 0);
S_Dout : OUT std_logic_vector(15 DOWNTO 0);
nTx_Int, nRx_Int : OUT std_logic;
nTx_BegInt : OUT std_logic;
-- DMA
Dma_Rd_Done : OUT std_logic;
Dma_Wr_Done : OUT std_logic;
Dma_Req, Dma_Rw : OUT std_logic;
Dma_Ack : IN std_logic;
Dma_Req_Overflow : OUT std_logic;
Dma_Rd_Len : OUT std_logic_vector(11 downto 0);
Dma_Addr : OUT std_logic_vector(HighAdr DOWNTO 1);
Dma_Dout : OUT std_logic_vector(15 DOWNTO 0);
Dma_Din : IN std_logic_vector(15 DOWNTO 0);
-- RMII
rRx_Dat : IN std_logic_vector( 1 DOWNTO 0);
rCrs_Dv : IN std_logic;
rTx_Dat : OUT std_logic_vector( 1 DOWNTO 0);
rTx_En : OUT std_logic;
Hub_Rx : IN std_logic_vector( 1 DOWNTO 0) := "00";
Mac_Zeit : OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY OpenMAC;
ARCHITECTURE struct OF OpenMAC IS
CONSTANT cInactivated : std_logic := '0';
CONSTANT cActivated : std_logic := '1';
SIGNAL Rx_Dv : std_logic;
SIGNAL R_Req : std_logic;
SIGNAL Auto_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Zeit : std_logic_vector(31 DOWNTO 0);
SIGNAL Tx_Dma_Req, Rx_Dma_Req : std_logic;
SIGNAL Tx_Dma_Ack, Rx_Dma_Ack : std_logic;
SIGNAL Tx_Ram_Dat, Rx_Ram_Dat : std_logic_vector(15 DOWNTO 0);
SIGNAL Tx_Dma_Len : std_logic_vector(11 DOWNTO 0);
SIGNAL Tx_Reg, Rx_Reg : std_logic_vector(15 DOWNTO 0);
SIGNAL Dma_Tx_Addr, Dma_Rx_Addr : std_logic_vector(Dma_Addr'RANGE);
SIGNAL Dma_Req_s, Dma_Rw_s : std_logic;
SIGNAL halfDuplex : std_logic; -- cActivated ... MAC in half-duplex mode
SIGNAL Tx_Active : std_logic; -- cActivated ... TX = Data or CRC
SIGNAL Tx_Dma_Very1stOverflow : std_logic; -- cActivated ... very first TX DMA overflow
SIGNAL Tx_Col : std_logic;
SIGNAL Sel_Tx_Ram, Sel_Tx_Reg : std_logic;
SIGNAL Tx_LatchH, Tx_LatchL : std_logic_vector( 7 DOWNTO 0);
BEGIN
S_Dout <= Tx_Ram_Dat WHEN Sel_Ram = '1' AND Sel_Tx_Ram = '1' ELSE
Rx_Ram_Dat WHEN Sel_Ram = '1' ELSE
Tx_Reg WHEN Sel_Cont = '1' AND Sel_Tx_Reg = '1' ELSE
Rx_Reg;
Mac_Zeit <= Zeit;
Dma_Rd_Len <= Tx_Dma_Len + 4;
b_DmaObserver : block
signal dmaObserverCounter, dmaObserverCounterNext : std_logic_vector(2 downto 0);
constant cDmaObserverCounterHalf : std_logic_vector(dmaObserverCounter'range) := "110"; --every 8th cycle
constant cDmaObserverCounterFull : std_logic_vector(dmaObserverCounter'range) := "010"; --every 4th cycle
begin
process(Clk, Rst)
begin
if Rst = '1' then
dmaObserverCounter <= (others => cInactivated);
elsif rising_edge(Clk) then
dmaObserverCounter <= dmaObserverCounterNext;
end if;
end process;
Dma_Req_Overflow <= --very first TX Dma transfer
Dma_Req_s when Tx_Dma_Very1stOverflow = cActivated and Tx_Active = cInactivated else
--RX Dma transfers and TX Dma transfers without the very first
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterHalf and halfDuplex = cActivated else
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterFull and halfDuplex = cInactivated else
cInactivated;
dmaObserverCounterNext <= --increment counter if DMA Read req (TX) during data and crc
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cActivated
and Tx_Active = cActivated else
--increment counter if DMA Write req (RX)
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cInactivated else
(others => cInactivated); --reset DmaObserverCounter if no Dma_Req
end block;
b_Dma: BLOCK
SIGNAL Rx_Dma, Tx_Dma : std_logic;
BEGIN
Dma_Req <= Dma_Req_s;
Dma_Req_s <= '1' WHEN (Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Rx_Dma_Req = '1' ELSE '0';
Dma_Rw <= Dma_Rw_s;
Dma_Rw_s <= '1' WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE '0';
Dma_Addr <= Dma_Tx_Addr WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE Dma_Rx_Addr;
Rx_Dma_Ack <= '1' WHEN Rx_Dma = '1' AND Dma_Ack = '1' ELSE '0';
pDmaArb: PROCESS( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0';
Tx_LatchH <= (OTHERS => '0'); Tx_LatchL <= (OTHERS => '0');
Zeit <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Timer THEN
Zeit <= Zeit + 1;
END IF;
Sel_Tx_Ram <= s_Adr(8);
Sel_Tx_Reg <= NOT s_Adr(3);
IF Dma_Ack = '0' THEN
IF Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1';
ELSIF Tx_Dma = '0' AND Rx_Dma_Req = '1' THEN Rx_Dma <= '1';
END IF;
ELSE
IF Rx_Dma = '1' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1'; Rx_Dma <= '0';
ELSIF Tx_Dma = '1' AND Rx_Dma_Req = '1' THEN Tx_Dma <= '0'; Rx_Dma <= '1';
ELSE Tx_Dma <= '0'; Rx_Dma <= '0';
END IF;
END IF;
IF Tx_Dma = '1' AND Dma_Ack = '1' THEN Tx_Dma_Ack <= '1';
ELSE Tx_Dma_Ack <= '0';
END IF;
IF Tx_Dma_Ack = '1' THEN Tx_LatchL <= Dma_Din(15 DOWNTO 8);
Tx_LatchH <= Dma_Din( 7 DOWNTO 0);
END IF;
END IF;
END PROCESS pDmaArb;
END BLOCK b_Dma;
b_Full_Tx: BLOCK
TYPE MACTX_TYPE IS ( R_Idl, R_Bop, R_Pre, R_Txd, R_Crc, R_Col, R_Jam );
SIGNAL Sm_Tx : MACTX_TYPE;
SIGNAL Start_Tx, ClrCol, Tx_On : std_logic;
SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0);
SIGNAL F_End, Was_Col, Block_Col : std_logic;
SIGNAL Ipg_Cnt, Tx_Timer : std_logic_vector( 7 DOWNTO 0);
ALIAS Ipg : std_logic IS Ipg_Cnt(7);
ALIAS Tx_Time : std_logic IS Tx_Timer(7);
SIGNAL Tx_Ipg : std_logic_vector( 5 DOWNTO 0);
SIGNAL Tx_Count : std_logic_vector(11 DOWNTO 0);
SIGNAL Tx_En, F_Val, Tx_Half : std_logic;
SIGNAL Tx_Sr, F_TxB : std_logic_vector( 7 DOWNTO 0);
SIGNAL Crc : std_logic_vector(31 DOWNTO 0);
SIGNAL CrcDin, Tx_Dat : std_logic_vector( 1 DOWNTO 0);
SIGNAL Col_Cnt : std_logic_vector( 3 DOWNTO 0);
SIGNAL Auto_Coll : std_logic;
SIGNAL Rnd_Num : std_logic_vector( 9 DOWNTO 0);
SIGNAL Retry_Cnt : std_logic_vector( 9 DOWNTO 0);
SIGNAL Max_Retry : std_logic_vector( 3 DOWNTO 0);
BEGIN
rTx_En <= Tx_En;
rTx_Dat <= Tx_Dat;
halfDuplex <= Tx_Half;
Tx_Active <= cActivated when Sm_Tx = R_Txd or Sm_Tx = R_Crc else cInactivated;
pTxSm: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Sm_Tx <= R_Idl;
ELSIF rising_edge( Clk ) THEN
IF Sm_Tx = R_Idl OR Sm_Tx = R_Bop OR Dibl_Cnt = "11" THEN
CASE Sm_Tx IS
WHEN R_Idl => IF Start_Tx = '1'
AND (Tx_Half = '0' OR Rx_Dv = '0')
AND Ipg = '0' THEN Sm_Tx <= R_Bop; END IF;
WHEN R_Bop => Sm_Tx <= R_Pre;
WHEN R_Pre => IF Tx_Time = '1' THEN Sm_Tx <= R_Txd; END IF;
WHEN R_Txd => IF Was_Col = '1' THEN Sm_Tx <= R_Col;
ELSIF Tx_Count = 0 THEN Sm_Tx <= R_Crc; END IF;
WHEN R_Col => Sm_Tx <= R_Jam;
WHEN R_Jam => IF Tx_Time = '1' THEN Sm_Tx <= R_Idl;
END IF;
WHEN R_Crc => IF Was_Col = '1' THEN Sm_Tx <= R_Col;
ELSIF Tx_Time = '1' THEN Sm_Tx <= R_Idl; END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS pTxSm;
pTxCtl: PROCESS ( Clk, Rst ) IS
VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE);
VARIABLE Load : std_logic;
BEGIN
IF Rst = '1' THEN
Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0';
Ipg_Cnt <= (OTHERS => '0'); Tx_Timer <= (OTHERS => '0'); Tx_Sr <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Sm_Tx = R_Bop THEN Dibl_Cnt <= "00";
ELSE Dibl_Cnt <= Dibl_Cnt + 1;
END IF;
IF Tx_En = '1' THEN Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7);
ELSIF Rx_Dv = '1' AND Tx_Half = '1' THEN Ipg_Cnt <= "10" & Tx_Ipg;
ELSIF Ipg = '1' THEN Ipg_Cnt <= Ipg_Cnt - 1;
END IF;
IF Dibl_Cnt = "11" AND Sm_Tx = R_Crc AND Tx_Time = '1' THEN F_End <= '1';
ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN
IF Col_Cnt = (Max_Retry - 1) THEN F_End <= '1';
ELSIF Col_Cnt < x"E" THEN Tx_Col <= '1';
ELSE F_End <= '1';
END IF;
ELSE F_End <= '0';
Tx_Col <= '0';
END IF;
IF Tx_Half = '1' AND Rx_Dv = '1'
AND (Sm_Tx = R_Pre OR Sm_Tx = R_Txd) THEN Was_Col <= '1';
ELSIF Sm_Tx = R_Col THEN Was_Col <= '0';
END IF;
IF Sm_Tx = R_Col THEN Block_Col <= '1';
ELSIF Auto_Coll = '1' THEN Block_Col <= '0';
ELSIF Retry_Cnt = 0 THEN Block_Col <= '0';
END IF;
IF Dibl_Cnt = "10" AND Sm_Tx = R_Pre AND Tx_Time = '1' THEN F_Val <= '1';
ELSIF Dibl_Cnt = "10" AND Sm_Tx = R_Txd THEN F_Val <= '1';
ELSE F_Val <= '0';
END IF;
Load := '0';
IF Sm_Tx = R_Bop THEN Preload := x"06"; Load := '1';
ELSIF Sm_Tx = R_Txd THEN Preload := x"02"; Load := '1';
ELSIF Sm_Tx = R_Col THEN Preload := x"01"; Load := '1';
ELSIF Tx_Time = '1' THEN Preload := x"3e"; Load := '1';
END IF;
IF Dibl_Cnt = "11" OR Sm_Tx = R_Bop THEN
IF Load = '1' THEN Tx_Timer <= Preload;
ELSE Tx_Timer <= Tx_Timer - 1;
END IF;
END IF;
IF F_Val = '1' THEN Tx_Sr <= F_TxB;
ELSE Tx_Sr <= "00" & Tx_Sr(7 DOWNTO 2);
END IF;
IF Sm_Tx = R_Pre THEN Tx_En <= '1';
ELSIF Sm_Tx = R_Idl OR (Sm_Tx = R_Jam AND Tx_Time = '1') THEN Tx_En <= '0';
END IF;
IF Sm_Tx = R_Pre AND Tx_Time = '1' AND Dibl_Cnt = "11" THEN Tx_Dat <= "11";
ELSIF Sm_Tx = R_Pre THEN Tx_Dat <= "01";
ELSIF Sm_Tx = R_Txd THEN Tx_Dat <= CrcDin;
ELSIF Sm_Tx = R_Crc THEN Tx_Dat <= NOT Crc(30) & NOT Crc(31);
ELSIF Sm_Tx = R_Col OR Sm_Tx = R_Jam THEN Tx_Dat <= "11";
ELSE Tx_Dat <= "00";
END IF;
END IF;
END PROCESS pTxCtl;
pBackDel: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Rnd_Num <= (OTHERS => '0');
Col_Cnt <= (OTHERS => '0');
Retry_Cnt <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
Rnd_Num <= Rnd_Num(8 DOWNTO 0) & (Rnd_Num(9) XOR NOT Rnd_Num(2));
IF ClrCol = '1' THEN Col_Cnt <= x"0";
ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN Col_Cnt <= Col_Cnt + 1;
END IF;
IF Dibl_Cnt = "11" THEN
IF Tx_On = '0' OR Auto_Coll = '1' THEN Retry_Cnt <= (OTHERS => '0');
ELSIF Sm_Tx = R_Col THEN
FOR i IN 0 TO 9 LOOP
IF Col_Cnt >= i THEN Retry_Cnt(i) <= Rnd_Num(i);
ELSE Retry_Cnt(i) <= '0';
END IF;
END LOOP;
ELSIF Sm_Tx /= R_Jam AND Tx_Time = '1' AND Retry_Cnt /= 0 THEN Retry_Cnt <= Retry_Cnt - 1;
END IF;
END IF;
END IF;
END PROCESS pBackDel;
CrcDin <= Tx_Sr(1 DOWNTO 0);
Calc: PROCESS ( Clk, Crc, CrcDin ) IS
VARIABLE H : std_logic_vector(1 DOWNTO 0);
BEGIN
H(0) := Crc(31) XOR CrcDin(0);
H(1) := Crc(30) XOR CrcDin(1);
IF rising_edge( Clk ) THEN
IF Sm_Tx = R_Pre THEN Crc <= x"FFFFFFFF";
ELSIF Sm_Tx = R_Crc THEN Crc <= Crc(29 DOWNTO 0) & "00";
ELSE
Crc( 0) <= H(1);
Crc( 1) <= H(0) XOR H(1);
Crc( 2) <= Crc( 0) XOR H(0) XOR H(1);
Crc( 3) <= Crc( 1) XOR H(0) ;
Crc( 4) <= Crc( 2) XOR H(1);
Crc( 5) <= Crc( 3) XOR H(0) XOR H(1);
Crc( 6) <= Crc( 4) XOR H(0) ;
Crc( 7) <= Crc( 5) XOR H(1);
Crc( 8) <= Crc( 6) XOR H(0) XOR H(1);
Crc( 9) <= Crc( 7) XOR H(0) ;
Crc(10) <= Crc( 8) XOR H(1);
Crc(11) <= Crc( 9) XOR H(0) XOR H(1);
Crc(12) <= Crc(10) XOR H(0) XOR H(1);
Crc(13) <= Crc(11) XOR H(0) ;
Crc(14) <= Crc(12) ;
Crc(15) <= Crc(13) ;
Crc(16) <= Crc(14) XOR H(1);
Crc(17) <= Crc(15) XOR H(0) ;
Crc(18) <= Crc(16) ;
Crc(19) <= Crc(17) ;
Crc(20) <= Crc(18) ;
Crc(21) <= Crc(19) ;
Crc(22) <= Crc(20) XOR H(1);
Crc(23) <= Crc(21) XOR H(0) XOR H(1);
Crc(24) <= Crc(22) XOR H(0) ;
Crc(25) <= Crc(23) ;
Crc(26) <= Crc(24) XOR H(1);
Crc(27) <= Crc(25) XOR H(0) ;
Crc(28) <= Crc(26) ;
Crc(29) <= Crc(27) ;
Crc(30) <= Crc(28) ;
Crc(31) <= Crc(29) ;
END IF;
END IF;
END PROCESS Calc;
bTxDesc: BLOCK
TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sReq, sBegL, sBegH, sDel, sData, sStat, sColl );
SIGNAL Dsm, Tx_Dsm_Next : sDESC;
SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0);
ALIAS TX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0);
ALIAS TX_OWN : std_logic IS DescRam_Out( 8);
ALIAS TX_LAST : std_logic IS DescRam_Out( 9);
ALIAS TX_READY : std_logic IS DescRam_Out(10);
ALIAS TX_BEGDEL : std_logic IS DescRam_Out(12);
ALIAS TX_BEGON : std_logic IS DescRam_Out(13);
ALIAS TX_TIME : std_logic IS DescRam_Out(14);
ALIAS TX_RETRY : std_logic_vector( 3 DOWNTO 0) IS DescRam_Out(3 DOWNTO 0);
SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr, Desc_We : std_logic;
SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0);
SIGNAL Last_Desc : std_logic;
SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0);
SIGNAL Tx_Ie, Tx_Wait : std_logic;
SIGNAL Tx_BegInt, Tx_BegSet, Tx_Early : std_logic;
SIGNAL Tx_Del : std_logic;
SIGNAL Ext_Tx, Ext_Ack : std_logic;
SIGNAL Tx_Desc, Tx_Desc_One, Ext_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Tx_Icnt : std_logic_vector( 4 DOWNTO 0);
SIGNAL Tx_SoftInt : std_logic;
SIGNAL Sel_TxH, Sel_TxL, H_Byte : std_logic;
SIGNAL Tx_Buf : std_logic_vector( 7 DOWNTO 0);
SIGNAL Tx_Idle, TxInt, Tx_Beg, Tx_Sync : std_logic;
SIGNAL Tx_Ident : std_logic_vector( 1 DOWNTO 0);
SIGNAL Tx_Cmp_High : std_logic_vector(15 downto 0);
SIGNAL Start_TxS : std_logic;
SIGNAL Tx_Dma_Out : std_logic;
SIGNAL Tx_Del_Cnt : std_logic_vector(32 downto 0);
ALIAS Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high);
SIGNAL Tx_Del_Run : std_logic;
signal Tx_Done : std_logic;
BEGIN
Dma_Rd_Done <= Tx_Done;
Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0';
Tx_Dma_Very1stOverflow <= cActivated when Dibl_Cnt = "01" and Sm_Tx = R_Pre and Tx_Timer(7) = '1' else cInactivated;
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0';
Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0';
Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0';
DescIdx <= "000" WHEN Desc_We = '0' AND Tx_Dsm_Next = sIdle ELSE
"000" WHEN Desc_We = '1' AND Dsm = sIdle ELSE
"001" WHEN Desc_We = '0' AND Tx_Dsm_Next = sLen ELSE
"001" WHEN Desc_We = '1' AND Dsm = sLen ELSE
"010" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrH ELSE
"010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE
"011" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrL ELSE
"011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE
"100" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegH ELSE
"100" WHEN Desc_We = '1' AND Dsm = sBegH ELSE
"101" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegL ELSE
"101" WHEN Desc_We = '1' AND Dsm = sBegL ELSE
"110" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimH ELSE
"110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE
"111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimL ELSE
"111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE
"111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sData ELSE
"111" WHEN Desc_We = '1' AND Dsm = sData ELSE
"000";
Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH OR Dsm = sStat ELSE '0';
Desc_Addr <= '1' & Tx_Desc & DescIdx WHEN Ext_Tx = '0' ELSE
'1' & Ext_Desc & DescIdx;
gTxTime: IF Timer GENERATE
DescRam_In <= Zeit(15 DOWNTO 0) WHEN Dsm = sTimH ELSE
ZeitL WHEN Dsm = sTimL ELSE
x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
END GENERATE;
gnTxTime: IF NOT Timer GENERATE
DescRam_In <= x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
END GENERATE;
RamH: ENTITY work.Dpr_16_16
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, Enb => cActivated,
BEA => Ram_Be,
WEA => Ram_Wr, WEB => Desc_We,
ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr,
DIA => s_Din, DIB => DescRam_In,
DOA => Tx_Ram_Dat, DOB => DescRam_Out
);
ASSERT NOT( TxSyncOn AND NOT Timer )
REPORT "TxSyncOn needs Timer!"
severity failure;
pTxSm: PROCESS( Rst, Clk, Dsm,
Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait,
Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg, Tx_Half, Tx_Del_End )
BEGIN
Tx_Dsm_Next <= Dsm;
CASE Dsm IS
WHEN sIdle => IF Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN
IF (Ext_Tx = '1' AND Ext_Ack = '0') OR Tx_Wait = '0' THEN
Tx_Dsm_Next <= sAdrH; --sLen;
END IF;
END IF;
WHEN sLen => IF Tx_Sync = '0' THEN Tx_Dsm_Next <= sReq; --sAdrH;
ELSE Tx_Dsm_Next <= sBegH;
END IF;
WHEN sBegH => Tx_Dsm_Next <= sBegL;
WHEN sBegL => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle;
ELSIF Tx_Sync = '0' THEN
if Tx_Del = '1' then Tx_Dsm_Next <= sDel;
elsIF Sm_Tx = R_Pre THEN
Tx_Dsm_Next <= sTimH;
END IF;
ELSIF Tx_Sync = '1' and Tx_Beg = '1' and Tx_Half = '1' and rCrs_Dv = '1' THEN
Tx_Dsm_Next <= sColl;
ELSIF Tx_Beg = '1' THEN Tx_Dsm_Next <= sReq;
END IF;
WHEN sDel => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle; --avoid FSM hang
ELSIF Tx_Del_End = '1' THEN Tx_Dsm_Next <= sTimH;
END IF;
WHEN sAdrH => Tx_Dsm_Next <= sAdrL;
WHEN sAdrL => Tx_Dsm_Next <= sLen; --sReq;
--leaving sAdrL and entering sReq leads to the very first Tx_Dma_Req
-- this enables early dma req at the beginning of IPG (auto-resp)
WHEN sReq => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle;
elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH;
ELSIF Tx_Sync = '0' THEN Tx_Dsm_Next <= sBegL;
ELSIF Sm_Tx = R_Bop THEN Tx_Dsm_Next <= sTimH;
END IF;
WHEN sTimH => Tx_Dsm_Next <= sTimL;
WHEN sTimL => Tx_Dsm_Next <= sData;
WHEN sData => IF F_End = '1' THEN Tx_Dsm_Next <= sStat;
ELSIF Tx_Col = '1' THEN Tx_Dsm_Next <= sColl;
END IF;
WHEN sStat => Tx_Dsm_Next <= sIdle;
WHEN sColl => if sm_tx = r_idl then
if Tx_Sync = '1' then Tx_Dsm_Next <= sStat;
else Tx_Dsm_Next <= sIdle;
end if;
end if;
WHEN OTHERS =>
END CASE;
IF Rst = '1' THEN Dsm <= sIdle;
ELSIF rising_edge( Clk ) THEN Dsm <= Tx_Dsm_Next;
END IF;
END PROCESS pTxSm;
pTxControl: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0';
Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0';
Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (OTHERS => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0');
ZeitL <= (OTHERS => '0'); Tx_Count <= (OTHERS => '0'); Tx_Ident <= "00";
Dma_Tx_Addr <= (OTHERS => '0'); Tx_Cmp_High <= (others => '0');
Tx_Del_Run <= '0';
Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0'); Tx_Dma_Len <= (others => '0');
ELSIF rising_edge( Clk ) THEN
IF TxSyncOn = true THEN
IF Tx_Sync = '1' AND Dsm = sBegL AND (DescRam_Out & Tx_Cmp_High ) = Zeit THEN Tx_Beg <= '1';
ELSE Tx_Beg <= '0';
END IF;
END IF;
IF Dsm = sStat AND Desc_We = '1' THEN ClrCol <= '1';
ELSE ClrCol <= '0';
END IF;
IF Timer THEN
IF Dsm = sTimH THEN ZeitL <= Zeit(31 DOWNTO 16);
END IF;
END IF;
IF Ext_Ack = '0' AND R_Req = '1' THEN Ext_Desc <= Auto_Desc;
Ext_Ack <= '1';
ELSIF Ext_Tx = '1' OR Tx_On = '0' THEN Ext_Ack <= '0';
END IF;
IF Dsm = sIdle AND Ext_Ack = '1' THEN Ext_Tx <= '1';
ELSIF Dsm = sStat OR Tx_Col = '1' OR Tx_On = '0' THEN Ext_Tx <= '0';
END IF;
IF (F_End = '1' OR Tx_On = '0'
OR (Tx_Col = '1' AND Ext_Tx = '1' )
OR dsm = sColl ) THEN Start_TxS <= '0';
Auto_Coll <= Auto_Coll OR (Tx_Col AND Ext_Tx);
ELSIF Dsm = sReq and Tx_Del = '0' THEN Start_TxS <= '1';
ELSIF Dsm = sDel and Tx_Del_End = '1' THEN Start_TxS <= '1';
ELSIF Sm_Tx = R_Idl THEN Auto_Coll <= '0';
END IF;
IF Dsm = sIdle THEN Last_Desc <= TX_LAST;
END IF;
IF Dsm = sLen THEN Tx_Count <= TX_LEN; Tx_Dma_Len <= TX_LEN; --add CRC
ELSIF F_Val = '1' THEN Tx_Count <= Tx_Count - 1;
END IF;
IF Dsm = sBegH THEN Tx_Cmp_High <= DescRam_Out;
END IF;
IF Dsm = sIdle AND Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN
IF Ext_Tx = '1' OR Tx_Wait = '0' THEN
IF TxSyncOn THEN Tx_Sync <= TX_TIME;
ELSE Tx_Sync <= '0';
END IF;
Max_Retry <= TX_RETRY;
Tx_Early <= TX_BEGON;
IF TxDel = true THEN Tx_Del <= TX_BEGDEL;
END IF;
END IF;
ELSIF Dsm = sTimH THEN Tx_BegSet <= Tx_Early;
ELSIF Dsm = sTimL THEN Tx_BegSet <= '0';
ELSIF Dsm = sIdle THEN Tx_Del <= '0';
END IF;
if TxDel = true and Tx_Del = '1' then
if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0';
Tx_Del_Cnt(15 downto 0) <= DescRam_Out;
elsif Dsm = sBegL then Tx_Del_Cnt(31 downto 16) <= DescRam_Out;
elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1;
end if;
if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg
elsif Tx_Del_End = '1' then Tx_Del_Run <= '0';
end if;
end if;
IF Dsm = sAdrL THEN --Dma_Tx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
Tx_Ident <= DescRam_Out(15 DOWNTO 14);
ELSIF Tx_Dma_Ack = '1' THEN Dma_Tx_Addr(15 DOWNTO 1) <= Dma_Tx_Addr(15 DOWNTO 1) + 1;
END IF;
IF Dsm = sAdrH THEN Dma_Tx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
-- Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
-- Tx_Ident <= DescRam_Out(15 DOWNTO 14);
ELSIF Tx_Dma_Ack = '1' AND Dma_Tx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN
Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) + 1;
END IF;
IF DSM = sAdrL
OR (F_Val = '1' AND H_Byte = '0') THEN Tx_Dma_Req <= '1';
ELSIF Tx_Dma_Ack = '1' THEN Tx_Dma_Req <= '0';
END IF;
IF Sm_Tx = R_Bop THEN H_Byte <= '0';
ELSIF F_Val = '1' THEN H_Byte <= NOT H_Byte;
END IF;
IF F_Val = '1' THEN Tx_Buf <= Tx_LatchL;
END IF;
if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1';
elsif Sm_Tx = R_Bop then Tx_Dma_Out <= '0';
end if;
END IF;
END PROCESS pTxControl;
Start_Tx <= '1' WHEN Start_TxS = '1' AND Block_Col = '0' ELSE
'1' WHEN not TxDel and not TxSyncOn and R_Req = '1' ELSE
'0';
F_TxB <= Tx_LatchH WHEN H_Byte = '0' ELSE
Tx_Buf;
nTx_Int <= '1' WHEN (Tx_Icnt = 0 AND Tx_SoftInt = '0') OR Tx_Ie = '0' ELSE '0';
Tx_Idle <= '1' WHEN Sm_Tx = R_Idl AND Dsm = sIdle ELSE '0';
Tx_Reg(15 DOWNTO 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) OR Tx_Icnt(3)) & Tx_Icnt(2 DOWNTO 0)
& Tx_On & Tx_BegInt & Tx_Idle & "0" ;
Tx_Reg( 3 DOWNTO 0) <= Tx_Desc;
Sel_TxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(1) = '1' ELSE '0';
Sel_TxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(0) = '1' ELSE '0';
Tx_Desc <= Tx_Desc_One;
Tx_SoftInt <= '0';
pTxRegs: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; nTx_BegInt <= '0';
Tx_Desc_One <= (OTHERS => '0');
Tx_Icnt <= (OTHERS => '0'); TxInt <= '0'; Tx_BegInt <= '0';
Tx_Ipg <= conv_std_logic_vector( 42, 6);
ELSIF rising_edge( Clk ) THEN
IF Sel_TxL = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_On <= S_Din( 7);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Tx_On <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Tx_On <= '0';
END IF;
END IF;
IF Tx_BegSet = '1' AND Tx_Ie = '1' THEN Tx_BegInt <= '1';
ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "01" AND S_Din( 6) = '1' THEN Tx_BegInt <= '1';
ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 6) = '1' THEN Tx_BegInt <= '0';
END IF;
nTx_BegInt <= NOT Tx_BegInt;
IF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Tx_Desc_One <= S_Din( 3 DOWNTO 0);
ELSIF Dsm = sStat AND Ext_Tx = '0' THEN
IF Last_Desc = '1' THEN Tx_Desc_One <= x"0";
ELSE Tx_Desc_One <= Tx_Desc + 1;
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Ie <= S_Din(15);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Tx_Ie <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Tx_Ie <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Half <= S_Din(13);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(13) = '1' THEN Tx_Half <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(13) = '1' THEN Tx_Half <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Wait <= S_Din(12);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Tx_Wait <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Tx_Wait <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "11" AND S_Din(14) = '1' THEN Tx_Ipg <= S_Din(13 DOWNTO 8);
END IF;
END IF;
IF Tx_Ie = '1' AND Dsm = sStat AND Desc_We = '1' THEN TxInt <= '1';
ELSE TxInt <= '0';
END IF;
IF Sel_TxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1'
AND Tx_Icnt /= 0 THEN Tx_Icnt <= Tx_Icnt - NOT TxInt;
ELSIF TxInt = '1' AND Tx_Icnt /= "11111" THEN Tx_Icnt <= Tx_Icnt + 1;
END IF;
END IF;
END PROCESS pTxRegs;
END BLOCK bTxDesc;
END BLOCK b_Full_Tx;
b_Full_Rx: BLOCK
TYPE MACRX_TYPE IS ( R_Idl, R_Sof, R_Rxd );
SIGNAL Sm_Rx : MACRX_TYPE;
SIGNAL Rx_Dat, Rx_DatL : std_logic_vector( 1 DOWNTO 0);
SIGNAL Tx_Timer : std_logic_vector( 7 DOWNTO 0);
SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0);
SIGNAL Crc, nCrc : std_logic_vector(31 DOWNTO 0);
SIGNAL CrcDin : std_logic_vector( 1 DOWNTO 0);
SIGNAL F_Err, P_Err, N_Err, A_Err : std_logic;
SIGNAL F_End, F_Val, Rx_Beg : std_logic;
SIGNAL Rx_Sr : std_logic_vector( 7 DOWNTO 0);
SIGNAL nCrc_Ok, Crc_Ok : std_logic;
SIGNAL WrDescStat : std_logic;
SIGNAL PreCount : std_logic_vector( 4 DOWNTO 0);
SIGNAL PreBeg, PreErr : std_logic;
SIGNAL Rx_DvL : std_logic;
SIGNAL Diag : std_logic;
BEGIN
Rx_Beg <= '1' WHEN Rx_Dv = '1' AND Sm_Rx = R_SOF AND Rx_Dat = "11" ELSE '0';
nCrc_Ok <= '1' WHEN nCrc = x"C704DD7B" ELSE '0';
rxsm: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Sm_Rx <= R_Idl;
ELSIF rising_edge( Clk ) THEN
IF Sm_Rx = R_Idl OR Sm_Rx = R_Rxd OR Sm_Rx = R_Sof OR Dibl_Cnt = "11" THEN
CASE Sm_Rx IS
WHEN R_Idl => IF Rx_Dv = '1' THEN Sm_Rx <= R_Sof; END IF;
WHEN R_Sof => IF Rx_Dat = "11" THEN Sm_Rx <= R_Rxd;
ELSIF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF;
WHEN R_Rxd => IF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS rxsm;
pRxCtl: PROCESS ( Clk, Rst ) IS
VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE);
VARIABLE Load : std_logic;
BEGIN
IF Rst = '1' THEN
Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (OTHERS => '0');
F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0';
A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0';
ELSIF rising_edge( Clk ) THEN
Rx_DatL <= rRx_Dat;
Rx_Dat <= Rx_DatL;
IF Rx_Dv = '0' AND rCrs_Dv = '1' THEN Rx_Dv <= '1';
ELSIF Rx_Dv = '1' AND rCrs_Dv = '0' AND Dibl_Cnt(0) = '1' THEN Rx_Dv <= '0';
END IF;
IF Rx_Beg = '1' THEN Dibl_Cnt <= "00";
ELSE Dibl_Cnt <= Dibl_Cnt + 1;
END IF;
Crc_Ok <= nCrc_Ok;
IF (Sm_Rx = R_Rxd AND Rx_Dv = '0') THEN F_End <= '1';
F_Err <= NOT Crc_Ok;
ELSE F_End <= '0';
END IF;
IF Dibl_Cnt = "11" AND Sm_Rx = R_Rxd THEN F_Val <= '1';
ELSE F_Val <= '0';
END IF;
IF WrDescStat = '1' THEN A_Err <= '0';
ELSIF F_End = '1' AND Dibl_Cnt /= 1 THEN A_Err <= '1';
END IF;
IF Rx_Dv = '0' OR Rx_Dat(0) = '0' THEN PreCount <= (OTHERS => '1');
ELSE PreCount <= PreCount - 1;
END IF;
IF Rx_Dv = '0' THEN PreBeg <= '0';
ELSIF Rx_Dat = "01" THEN PreBeg <= '1';
END IF;
IF WrDescStat = '1' THEN N_Err <= '0';
ELSIF Sm_Rx = R_Sof AND Rx_Dv = '0' THEN N_Err <= '1';
END IF;
IF Rx_DvL = '0' THEN PreErr <= '0';
ELSIF PreBeg = '0' AND (Rx_Dat = "10" OR Rx_Dat = "11") THEN PreErr <= '1';
ELSIF PreBeg = '1' AND (Rx_Dat = "10" OR Rx_Dat = "00") THEN PreErr <= '1';
END IF;
IF WrDescStat = '1' THEN P_Err <= '0';
ELSIF Rx_Beg = '1' AND PreErr = '1' THEN P_Err <= '1';
ELSIF Rx_Beg = '1' AND PreCount /= 0 THEN P_Err <= '1';
END IF;
Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 DOWNTO 2);
Rx_DvL <= Rx_Dv;
END IF;
END PROCESS pRxCtl;
CrcDin <= Rx_Dat;
Calc: PROCESS ( Clk, Crc, nCrc, CrcDin, Sm_Rx ) IS
VARIABLE H : std_logic_vector(1 DOWNTO 0);
BEGIN
H(0) := Crc(31) XOR CrcDin(0);
H(1) := Crc(30) XOR CrcDin(1);
IF Sm_Rx = R_Sof THEN nCrc <= x"FFFFFFFF";
ELSE
nCrc( 0) <= H(1);
nCrc( 1) <= H(0) XOR H(1);
nCrc( 2) <= Crc( 0) XOR H(0) XOR H(1);
nCrc( 3) <= Crc( 1) XOR H(0) ;
nCrc( 4) <= Crc( 2) XOR H(1);
nCrc( 5) <= Crc( 3) XOR H(0) XOR H(1);
nCrc( 6) <= Crc( 4) XOR H(0) ;
nCrc( 7) <= Crc( 5) XOR H(1);
nCrc( 8) <= Crc( 6) XOR H(0) XOR H(1);
nCrc( 9) <= Crc( 7) XOR H(0) ;
nCrc(10) <= Crc( 8) XOR H(1);
nCrc(11) <= Crc( 9) XOR H(0) XOR H(1);
nCrc(12) <= Crc(10) XOR H(0) XOR H(1);
nCrc(13) <= Crc(11) XOR H(0) ;
nCrc(14) <= Crc(12) ;
nCrc(15) <= Crc(13) ;
nCrc(16) <= Crc(14) XOR H(1);
nCrc(17) <= Crc(15) XOR H(0) ;
nCrc(18) <= Crc(16) ;
nCrc(19) <= Crc(17) ;
nCrc(20) <= Crc(18) ;
nCrc(21) <= Crc(19) ;
nCrc(22) <= Crc(20) XOR H(1);
nCrc(23) <= Crc(21) XOR H(0) XOR H(1);
nCrc(24) <= Crc(22) XOR H(0) ;
nCrc(25) <= Crc(23) ;
nCrc(26) <= Crc(24) XOR H(1);
nCrc(27) <= Crc(25) XOR H(0) ;
nCrc(28) <= Crc(26) ;
nCrc(29) <= Crc(27) ;
nCrc(30) <= Crc(28) ;
nCrc(31) <= Crc(29) ;
END IF;
IF rising_edge( Clk ) THEN
Crc <= nCrc;
END IF;
END PROCESS Calc;
bRxDesc: BLOCK
TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sData, sOdd, sStat, sLenW );
SIGNAL Dsm, Rx_Dsm_Next : sDESC;
SIGNAL Rx_Buf, Rx_LatchH, Rx_LatchL : std_logic_vector( 7 DOWNTO 0);
SIGNAL Rx_Ovr : std_logic;
SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0);
ALIAS RX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0);
ALIAS RX_OWN : std_logic IS DescRam_Out( 8);
ALIAS RX_LAST : std_logic IS DescRam_Out( 9);
SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr, Desc_We : std_logic;
SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0);
SIGNAL Rx_On, Rx_Ie, Sel_RxH, Sel_RxL : std_logic;
SIGNAL Rx_Desc, Match_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Rx_Icnt : std_logic_vector( 4 DOWNTO 0);
SIGNAL Rx_Lost, Last_Desc, Answer_Tx : std_logic;
SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0);
SIGNAL Rx_Count, Rx_Limit : std_logic_vector(11 DOWNTO 0);
SIGNAL Match, Filt_Cmp : std_logic;
SIGNAL Rx_Idle, RxInt : std_logic;
SIGNAL Hub_Rx_L : std_logic_vector( 1 DOWNTO 0);
SIGNAL Rx_Dma_Out : std_logic;
signal Rx_Done : std_logic;
BEGIN
process(rst, clk)
variable doPulse : std_logic;
begin
if rst = cActivated then
Rx_Done <= cInactivated;
doPulse := cInactivated;
elsif rising_edge(clk) then
Rx_Done <= cInactivated;
if Dsm /= sIdle and Rx_Dsm_Next = sIdle then
-- RX is done
doPulse := cActivated;
end if;
if doPulse = cActivated and Rx_Dma_Req = cInactivated and Rx_Count = 0 then
-- RX is done and there is no dma request
Rx_Done <= cActivated;
doPulse := cInactivated;
end if;
end if;
end process;
Dma_Wr_Done <= Rx_Done;
WrDescStat <= '1' WHEN Dsm = sStat ELSE '0';
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0';
Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0';
Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0';
DescIdx <= "001" WHEN Desc_We = '0' AND (Rx_Dsm_Next = sLen OR Rx_Dsm_Next = sLenW) ELSE
"001" WHEN Desc_We = '1' AND (Dsm = sLen OR Dsm = sLenW) ELSE
"010" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrH ELSE
"010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE
"011" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrL ELSE
"011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE
"110" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimH ELSE
"110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE
"111" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimL ELSE
"111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE
"000";
Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH ELSE
'1' WHEN (Dsm = sLenW OR Dsm = sStat) AND Match = '1' ELSE '0';
Desc_Addr <= "0" & Rx_Desc & DescIdx;
gRxTime: IF timer GENERATE
DescRam_In <= Zeit(15 DOWNTO 0) WHEN Dsm = sTimH ELSE
ZeitL WHEN Dsm = sTimL ELSE
x"0" & Rx_Count WHEN Dsm = sLenW ELSE
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
END GENERATE;
ngRxTime: IF NOT timer GENERATE
DescRam_In <= x"0" & Rx_Count WHEN Dsm = sLenW ELSE
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
END GENERATE;
RxRam: ENTITY work.Dpr_16_16
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, Enb => cActivated,
BEA => Ram_Be,
WEA => Ram_Wr, WEB => Desc_We,
ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr,
DIA => s_Din, DIB => DescRam_In,
DOA => Rx_Ram_Dat, DOB => DescRam_Out
);
pRxSm: PROCESS( Rst, Clk, Dsm,
Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count )
BEGIN
Rx_Dsm_Next <= Dsm;
CASE Dsm IS
WHEN sIdle => IF Rx_Beg = '1' AND Rx_On = '1' AND RX_OWN = '1' THEN
Rx_Dsm_Next <= sLen;
END IF;
WHEN sLen => Rx_Dsm_Next <= sAdrH;
WHEN sAdrH => Rx_Dsm_Next <= sAdrL;
WHEN sAdrL => Rx_Dsm_Next <= sTimH;
WHEN sTimH => Rx_Dsm_Next <= sTimL;
WHEN sTimL => Rx_Dsm_Next <= sData;
WHEN sData => IF F_End = '1' THEN
IF F_Err = '0'
OR Diag = '1' THEN Rx_Dsm_Next <= sStat;
ELSE Rx_Dsm_Next <= sIdle;
END IF;
END IF;
WHEN sStat => Rx_Dsm_Next <= sLenW;
WHEN sLenW => IF Rx_Count(0) = '0' THEN
Rx_Dsm_Next <= sIdle;
ELSE Rx_Dsm_Next <= sOdd;
END IF;
WHEN sOdd => Rx_Dsm_Next <= sIdle;
WHEN OTHERS =>
END CASE;
IF Rst = '1' THEN Dsm <= sIdle;
ELSIF rising_edge( Clk ) THEN Dsm <= Rx_Dsm_Next;
END IF;
END PROCESS pRxSm;
pRxControl: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0';
Rx_Count <= (OTHERS => '0');
Rx_Buf <= (OTHERS => '0'); Rx_LatchL <= (OTHERS => '0'); Rx_LatchH <= (OTHERS => '0');
Dma_Rx_Addr <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Timer THEN
IF Dsm = sTimH THEN ZeitL <= Zeit(31 DOWNTO 16);
END IF;
END IF;
IF Dsm = sIdle THEN Rx_Count <= (OTHERS => '0');
Last_Desc <= RX_LAST;
ELSIF F_Val = '1' THEN Rx_Count <= Rx_Count + 1;
END IF;
IF Dsm = sLen THEN Rx_Limit <= RX_LEN;
Hub_Rx_L <= Hub_Rx;
END IF;
IF F_Val = '1' THEN Rx_Buf <= Rx_Sr;
END IF;
IF (F_Val = '1' AND Rx_Count(0) = '1') OR Dsm = sStat THEN Rx_LatchH <= Rx_Buf;
Rx_LatchL <= Rx_Sr;
IF Rx_Dma_Req = '1' AND Sm_Rx /= R_Idl THEN Rx_Dma_Out <= '1';
END IF;
ELSIF Dsm = sLen THEN Rx_Dma_Out <= '0';
END IF;
IF Dsm = sLen THEN Rx_Ovr <= '0';
ELSIF F_Val = '1' AND Rx_Limit = Rx_Count THEN Rx_Ovr <= '1';
END IF;
IF Dsm = sAdrL THEN --Dma_Rx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
ELSIF Rx_Dma_Ack = '1' THEN Dma_Rx_Addr(15 DOWNTO 1) <= Dma_Rx_Addr(15 DOWNTO 1) + 1;
END IF;
IF Dsm = sAdrH THEN Dma_Rx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
--Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
ELSIF Rx_Dma_Ack = '1' AND Dma_Rx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN
Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) + 1;
END IF;
IF Filt_Cmp = '0' AND Match ='0' THEN Rx_Dma_Req <= '0';
ELSIF (Dsm = sOdd AND Rx_Ovr = '0')
OR (Dsm = sData AND Rx_Ovr = '0' AND F_Val = '1' AND Rx_Count(0) = '1') THEN Rx_Dma_Req <= '1';
ELSIF Rx_Dma_Ack = '1' THEN Rx_Dma_Req <= '0';
END IF;
END IF;
END PROCESS pRxControl;
Dma_Dout <= Rx_LatchL & Rx_LatchH; --Rx_LatchH & Rx_LatchL;
nRx_Int <= '1' WHEN Rx_Icnt = 0 OR Rx_Ie = '0' ELSE '0';
Rx_Idle <= '1' WHEN Sm_Rx = R_Idl ELSE '0';
Rx_Reg(15 DOWNTO 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) OR Rx_Icnt(3)) & Rx_Icnt(2 DOWNTO 0)
& Rx_On & "0" & Rx_Idle & Rx_Lost;
Rx_Reg( 3 DOWNTO 0) <= Rx_Desc;
bFilter: BLOCK
SIGNAL Ram_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL Ram_BeH, Ram_BeL : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr : std_logic;
SIGNAL Filter_Addr : std_logic_vector( 6 DOWNTO 0);
SIGNAL Filter_Out_H, Filter_Out_L : std_logic_vector(31 DOWNTO 0);
ALIAS DIRON_0 : std_logic IS Filter_Out_H( 11);
ALIAS DIRON_1 : std_logic IS Filter_Out_H( 27);
ALIAS DIRON_2 : std_logic IS Filter_Out_L( 11);
ALIAS DIRON_3 : std_logic IS Filter_Out_L( 27);
ALIAS TX_0 : std_logic IS Filter_Out_H( 7);
ALIAS TX_1 : std_logic IS Filter_Out_H(23);
ALIAS TX_2 : std_logic IS Filter_Out_L( 7);
ALIAS TX_3 : std_logic IS Filter_Out_L(23);
ALIAS ON_0 : std_logic IS Filter_Out_H( 6);
ALIAS ON_1 : std_logic IS Filter_Out_H(22);
ALIAS ON_2 : std_logic IS Filter_Out_L( 6);
ALIAS ON_3 : std_logic IS Filter_Out_L(22);
ALIAS DESC_0 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H( 3 DOWNTO 0);
ALIAS DESC_1 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H(19 DOWNTO 16);
ALIAS DESC_2 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L( 3 DOWNTO 0);
ALIAS DESC_3 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L(19 DOWNTO 16);
SIGNAL Byte_Cnt : std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
SIGNAL Erg0, Erg1, Erg2, Erg3 : std_logic_vector( 7 DOWNTO 0);
SIGNAL Mat_Reg : std_logic_vector(15 DOWNTO 0);
SIGNAL Filt_Idx : std_logic_vector( 1 DOWNTO 0);
SIGNAL Mat_Sel : std_logic_vector( 3 DOWNTO 0);
SIGNAL M_Prio : std_logic_vector( 2 DOWNTO 0);
ALIAS Found : std_logic IS M_Prio(2);
BEGIN
Ram_Addr <= s_Adr(9 DOWNTO 8) & s_Adr(5 DOWNTO 1) & s_Adr(6);
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '0' ELSE '0';
Ram_BeH(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '0') ELSE '0';
Ram_BeH(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '0') ELSE '0';
Ram_BeL(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '1') ELSE '0';
Ram_BeL(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '1') ELSE '0';
Filter_Addr <= Dibl_Cnt & Byte_Cnt;
FiltRamH: ENTITY work.Dpr_16_32
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, EnB => cActivated,
BEA => Ram_BeH,
WEA => Ram_Wr,
ADDRA => Ram_Addr, ADDRB => Filter_Addr,
DIA => s_Din, DOB => Filter_Out_H
);
FiltRamL: ENTITY work.Dpr_16_32
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, EnB => cActivated,
BEA => Ram_BeL,
WEA => Ram_Wr,
ADDRA => Ram_Addr, ADDRB => Filter_Addr,
DIA => s_Din, DOB => Filter_Out_L
);
Erg0 <= (Rx_Buf XOR Filter_Out_H( 7 DOWNTO 0)) AND Filter_Out_H(15 DOWNTO 8);
Erg1 <= (Rx_Buf XOR Filter_Out_H(23 DOWNTO 16)) AND Filter_Out_H(31 DOWNTO 24);
Erg2 <= (Rx_Buf XOR Filter_Out_L( 7 DOWNTO 0)) AND Filter_Out_L(15 DOWNTO 8);
Erg3 <= (Rx_Buf XOR Filter_Out_L(23 DOWNTO 16)) AND Filter_Out_L(31 DOWNTO 24);
genMatSel: FOR i IN 0 TO 3 GENERATE
Mat_Sel(i) <= Mat_Reg( 0 + i) WHEN Filt_Idx = "00" ELSE
Mat_Reg( 4 + i) WHEN Filt_Idx = "01" ELSE
Mat_Reg( 8 + i) WHEN Filt_Idx = "10" ELSE
Mat_Reg(12 + i); -- WHEN Filt_Idx = "11";
END GENERATE;
M_Prio <= "000" WHEN Filt_Cmp = '0' OR Match = '1' ELSE
"100" WHEN Mat_Sel(0) = '1' AND On_0 = '1' AND (DIRON_0 = '0') ELSE
"101" WHEN Mat_Sel(1) = '1' AND On_1 = '1' AND (DIRON_1 = '0') ELSE
"110" WHEN Mat_Sel(2) = '1' AND On_2 = '1' AND (DIRON_2 = '0') ELSE
"111" WHEN Mat_Sel(3) = '1' AND On_3 = '1' AND (DIRON_3 = '0') ELSE
"000";
pFilter: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Filt_Idx <= "00"; Match <= '0';
Filt_Cmp <= '0'; Mat_Reg <= (OTHERS => '0'); Byte_Cnt <= (OTHERS =>'0');
Match_Desc <= (OTHERS => '0');Auto_Desc <= (OTHERS =>'0'); Answer_Tx <= '0';
ELSIF rising_edge( Clk ) THEN
Filt_Idx <= Dibl_Cnt;
IF Dibl_Cnt = "11" AND Rx_Count(5) = '0' THEN Byte_Cnt <= Rx_Count(Byte_Cnt'RANGE);
END IF;
IF Dsm = sTiml THEN Filt_Cmp <= '1';
ELSIF Rx_Dv = '0' OR (F_Val = '1' AND Rx_Count(5) = '1') THEN Filt_Cmp <= '0';
END IF;
IF Dsm = sTimL THEN Mat_Reg <= (OTHERS => '1');
ELSE
FOR i IN 0 TO 3 LOOP
IF Erg0 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 0) <= '0'; END IF;
IF Erg1 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 1) <= '0'; END IF;
IF Erg2 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 2) <= '0'; END IF;
IF Erg3 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 3) <= '0'; END IF;
END LOOP;
END IF;
IF Dsm = sTimL THEN Match <= '0';
ELSIF Found = '1' THEN Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 DOWNTO 0);
IF M_Prio(1 DOWNTO 0) = "00" THEN Answer_Tx <= TX_0; Auto_Desc <= DESC_0;
ELSIF M_Prio(1 DOWNTO 0) = "01" THEN Answer_Tx <= TX_1; Auto_Desc <= DESC_1;
ELSIF M_Prio(1 DOWNTO 0) = "10" THEN Answer_Tx <= TX_2; Auto_Desc <= DESC_2;
ELSIF M_Prio(1 DOWNTO 0) = "11" THEN Answer_Tx <= TX_3; Auto_Desc <= DESC_3;
END IF;
ELSIF F_End = '1' THEN Answer_Tx <= '0';
END IF;
END IF;
END PROCESS pFilter;
R_Req <= Answer_Tx WHEN F_End = '1' AND F_Err = '0' ELSE '0';
END BLOCK bFilter;
Sel_RxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(1) = '0' ELSE '0';
Sel_RxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(0) = '0' ELSE '0';
pRxRegs: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Rx_Desc <= (OTHERS => '0'); Rx_On <= '0';
Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (OTHERS => '0'); RxInt <= '0'; Diag <= '0';
ELSIF rising_edge( Clk ) THEN
IF Sel_RxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_Ie <= S_Din(15);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Rx_Ie <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Rx_Ie <= '0';
END IF;
END IF;
IF Sel_RxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Diag <= S_Din(12);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Diag <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Diag <= '0';
END IF;
END IF;
IF Sel_RxL = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_On <= S_Din( 7);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Rx_On <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Rx_On <= '0';
END IF;
END IF;
IF Rx_Beg = '1' AND (RX_OWN = '0' OR Rx_On = '0') THEN Rx_Lost <= '1';
ELSIF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 4) = '1' THEN Rx_Lost <= '0';
END IF;
IF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Rx_Desc <= S_Din( 3 DOWNTO 0);
ELSIF Dsm = sLenW AND Desc_We = '1' THEN
IF Last_Desc = '1' THEN Rx_Desc <= x"0";
ELSE Rx_Desc <= Rx_Desc + 1;
END IF;
END IF;
IF Rx_Ie = '1' AND Desc_We = '1' AND Dsm = sStat THEN RxInt <= '1';
ELSE RxInt <= '0';
END IF;
IF Sel_RxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1'
AND Rx_Icnt /= 0 THEN Rx_Icnt <= Rx_Icnt - NOT RxInt;
ELSIF RxInt = '1' AND Rx_Icnt /= "11111" THEN Rx_Icnt <= Rx_Icnt + 1;
END IF;
END IF;
END PROCESS pRxRegs;
END BLOCK bRxDesc;
END BLOCK b_Full_Rx;
END ARCHITECTURE struct; | gpl-2.0 | 6cb23db5830b9f50d9d46c5d724936a8 | 0.400518 | 3.593594 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_ram_dq0.vhd | 2 | 6,990 | -- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Arria GX",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=nib1",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "nib1"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=nib1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | a8f18cdf953b4eb84654eab138a00f20 | 0.674106 | 3.479343 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part6a/lpm_constant0.vhd | 2 | 3,518 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 228,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=VAL",
lpm_type => "LPM_CONSTANT",
lpm_width => 8
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "VAL"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "228"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "228"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=VAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | cda0fc887b6e8c3ea7cf3fea7ddb2c36 | 0.647243 | 3.823913 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_counter4.vhd | 2 | 4,424 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter4.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter4 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter4;
ARCHITECTURE SYN OF lpm_counter4 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
sclr => sclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 1ea2b777ca4617d358ecd7692a3de447 | 0.654385 | 3.695906 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/mod12counter.vhd | 2 | 4,774 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: mod12counter.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mod12counter IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END mod12counter;
ARCHITECTURE SYN OF mod12counter IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(3 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 12,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 4
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "12"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | dbd87a67d0b443fe82d5ead92150eae7 | 0.656891 | 3.655436 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part6a/DE1_disp.vhd | 1 | 1,283 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DE1_disp IS
PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END DE1_disp;
ARCHITECTURE Behavior OF DE1_disp IS
COMPONENT sweep
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
END COMPONENT;
SIGNAL M0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL M1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN -- Behavior
S0: sweep PORT MAP (clk,M0);
DISPProcess: process (M0) is
begin
CASE M0 IS
WHEN "00" => DISPn <= "1110";
WHEN "01" => DISPn <= "1101";
WHEN "10" => DISPn <= "1011";
WHEN "11" => DISPn <= "0111";
WHEN OTHERS => NULL;
END CASE;
end process DISPProcess;
HEXProcess: process (M1) is
begin
CASE M1 IS
WHEN "00" => HEX <= HEX0;
WHEN "01" => HEX <= HEX1 ;
WHEN "10" => HEX <= HEX2 ;
WHEN "11" => HEX <= HEX3 ;
WHEN OTHERS => NULL;
END CASE;
end process HEXProcess;
CLKProcess: process (clk) is
begin
if falling_edge(clk) then
M1 <= M0 after 25ps;
end if;
end process CLKProcess;
END Behavior; | unlicense | 32aea91699244dd1c8684b96c76e57aa | 0.571317 | 3.199501 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ip/spi_master/spi_master_core.vhd | 3 | 10,589 | --*****************************************************************************
--* Copyright (C) 2012 by Michael Fischer
--*
--* All rights reserved.
--*
--* Many thanks to Lothar Miller who has provided the basic example of
-- the SPI device:
--* http://www.lothar-miller.de/s9y/archives/50-Einfacher-SPI-Master-Mode-0.html
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permission.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 26.08.2012 mifi First Version,
--* based on the basic SPI device from Lothar Miller.
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity spi_master_core is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end entity spi_master_core;
--*****************************************************************************
--* DEFINE: Architecture *
--*****************************************************************************
architecture syn of spi_master_core is
--
-- Define all constants here
--
constant ADDR_TXDATA : integer := 0; -- Write
constant ADDR_RXDATA : integer := 1; -- Read
constant ADDR_CTRL_1 : integer := 2; -- Read / Write
constant ADDR_STATUS : integer := 3; -- Read
--
-- Define all components which are included here
--
--
-- Define all local signals (like static data) here
--
-- Read Multiplexer
signal read_mux : std_logic_vector(15 downto 0) := (others => '0');
-- Register File
signal tx_data : std_logic_vector(15 downto 0) := (others => '0');
signal rx_data : std_logic_vector(15 downto 0) := (others => '0');
signal control_1 : std_logic_vector(15 downto 0) := std_logic_vector'(x"FFFF");
signal status : std_logic_vector(15 downto 0) := (others => '0');
-- Prescale counter
signal pre_cnt : integer range 0 to (2**8)-1 := 0;
signal pre_cnt_max : integer range 0 to (2**8)-1 := 0;
-- Bit counter
signal bit_cnt : integer range 0 to 16 := 0;
signal bit_cnt_max : integer range 0 to 16 := 0;
-- Some control_1 values
signal ssel : std_logic; -- Slave select
signal bit16 : std_logic; -- Bit count: 0 = 8 / 1 = 16
signal loop_enable : std_logic; -- Loopback: 0 = disable / 1 = enable
-- Possible SPI states
type spitx_states is (spi_stx,spi_txactive,spi_etx);
signal spitxstate : spitx_states := spi_stx;
-- SPI clock and last clock
signal spiclk : std_logic;
signal spiclklast : std_logic;
-- TX and RX value
signal tx_reg : std_logic_vector(15 downto 0) := (others=>'0');
signal rx_reg : std_logic_vector(15 downto 0) := (others=>'0');
-- Some internal SPI signals
signal tx_done : std_logic := '0';
signal tx_start : std_logic := '0';
signal write_s1 : std_logic := '0';
signal mosi_int : std_logic := '0';
signal miso_int : std_logic := '0';
begin
----------------------------------------------
-- Register File
----------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if (write = '1') then
if (ADDR_TXDATA = unsigned(address)) then -- ADDR_TXDATA
tx_data <= writedata;
end if;
if (ADDR_CTRL_1 = unsigned(address)) then -- ADDR_CTRL_1
control_1 <= writedata;
end if;
end if;
end if;
end process;
----------------------------------------------
-- Read Multiplexer
----------------------------------------------
read_mux <= rx_data when (ADDR_RXDATA = unsigned(address)) else
control_1 when (ADDR_CTRL_1 = unsigned(address)) else
status when (ADDR_STATUS = unsigned(address)) else (others => '0');
process (clk)
begin
if rising_edge(clk) then
if (read = '1') then
readdata <= read_mux;
end if;
end if;
end process;
----------------------------------------------
-- Decode control_1 register
----------------------------------------------
ssel <= control_1(0);
bit16 <= control_1(1);
loop_enable <= control_1(2);
pre_cnt_max <= to_integer(unsigned(control_1(15 downto 8)));
bit_cnt_max <= 16 when (bit16 = '1') else 8;
----------------------------------------------
-- Generate tx_start
----------------------------------------------
process (clk)
begin
if rising_edge(clk) then
write_s1 <= write;
if (ADDR_TXDATA = unsigned(address)) then
-- Check rising edge write
if (write_s1 = '0') and (write = '1') then
tx_start <= '0';
end if;
-- Check falling edge write
if (write_s1 = '1') and (write = '0') then
tx_start <= '1';
end if;
end if;
end if;
end process;
----------------------------------------------
-- SPI generation
----------------------------------------------
process (clk)
begin
if rising_edge(clk) then
--
-- Clock prescaler
-- SPI clock = clk / ((pre_cnt_max+1)*2)
--
if (pre_cnt > 0) then
pre_cnt <= pre_cnt - 1;
else
pre_cnt <= pre_cnt_max;
end if;
-- Generate SPI signals
spiclklast <= spiclk;
case spitxstate is
when spi_stx =>
bit_cnt <= bit_cnt_max;
spiclk <= '0';
if (tx_start = '1') then
spitxstate <= spi_txactive;
pre_cnt <= pre_cnt_max;
end if;
when spi_txactive => -- Data phase
if (pre_cnt = 0) then -- Shift if pre_cnt is 0
spiclk <= not spiclk;
if (bit_cnt = 0) then -- All bits was transfered?
spiclk <= '0';
spitxstate <= spi_etx;
end if;
if (spiclk = '1') then
bit_cnt <= bit_cnt - 1;
end if;
end if;
when spi_etx =>
tx_done <= '1';
if (tx_start = '0') then -- Done was set, wait for next start
tx_done <= '0';
spitxstate <= spi_stx;
end if;
end case;
end if;
end process;
--
-- RX shift register
--
process (clk)
begin
if rising_edge(clk) then
if (spiclk = '1' and spiclklast = '0') then
rx_reg <= rx_reg(14 downto 0) & miso_int;
end if;
end if;
end process;
--
-- TX shift register
--
process (clk)
begin
if rising_edge(clk) then
if (spitxstate = spi_stx) then
tx_reg <= tx_data;
end if;
if (spiclk = '0') and (spiclklast='1') then
tx_reg <= tx_reg(14 downto 0) & tx_reg(0);
end if;
end if;
end process;
status(0) <= tx_done;
rx_data <= rx_reg;
mosi_int <= tx_reg(bit_cnt_max-1);
----------------------------------------------
-- External bus
----------------------------------------------
cs <= ssel when (loop_enable = '0') else '1';
sclk <= spiclk when (loop_enable = '0') else '0';
mosi <= mosi_int when (loop_enable = '0') else '0';
miso_int <= miso when (loop_enable = '0') else mosi_int;
end architecture syn;
-- *** EOF ***
| unlicense | 50e4b78984a5aa85efdc82af6af56837 | 0.454528 | 4.402911 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/inSystemRAM.vhd | 2 | 6,976 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: inSystemRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY inSystemRAM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END inSystemRAM;
ARCHITECTURE SYN OF insystemram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Arria GX",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CHb",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "CHb"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CHb"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL inSystemRAM_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | ab2fbc92cf13f02e0cfefe8115ee3600 | 0.676462 | 3.568286 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/xilinx/openmac/src/openMAC_DPR.vhd | 3 | 12,638 | -------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
constant SIZE : natural := 2**ADDRWIDTH;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
gDoInit : boolean := false; -- if dpr is used in pdi init state field with invalid state
WIDTH : integer := 16;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
constant SIZE : natural := 2**ADDRWIDTH;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
function InitRam return ramType is
variable RAM : ramType := (others => (others => '0'));
begin
if gDoInit = true then
for i in ramType'range loop
RAM(i) := X"00000000";
if i = 4 then -- init state field with invalid state
RAM(i) := X"00EEFFFF";
end if;
end loop;
end if;
return RAM;
end function;
shared variable ram : ramType := InitRam;
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 16,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
| gpl-2.0 | a89f478fb68b51800c37e8d4860c8ac1 | 0.520177 | 3.618093 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/pdi/src/pdi_simpleReg.vhd | 3 | 4,047 | -------------------------------------------------------------------------------
-- Process Data Interface (PDI) simple register
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdiSimpleReg is
generic (
iAddrWidth_g : integer := 10; --only use effective addr range (e.g. 2kB leads to iAddrWidth_g := 10)
iBaseMap2_g : integer := 0; --base address in dpr
iDprAddrWidth_g : integer := 12
);
port (
--memory mapped interface
sel : in std_logic;
wr : in std_logic;
rd : in std_logic;
addr : in std_logic_vector(iAddrWidth_g-1 downto 0);
be : in std_logic_vector(3 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
--dpr interface (from PCP/AP to DPR)
dprAddrOff : out std_logic_vector(iDprAddrWidth_g downto 0);
dprDin : out std_logic_vector(31 downto 0);
dprDout : in std_logic_vector(31 downto 0);
dprBe : out std_logic_vector(3 downto 0);
dprWr : out std_logic
);
end entity pdiSimpleReg;
architecture rtl of pdiSimpleReg is
signal addrRes : std_logic_vector(dprAddrOff'range);
begin
--assign content to dpr
dprDin <= din;
dprBe <= be;
dprWr <= wr when sel = '1' else
'0';
dout <= dprDout when sel = '1' else
(others => '0');
dprAddrOff <= addrRes when sel = '1' else
(others => '0');
--address conversion
---map external address mapping into dpr
addrRes <= '0' & conv_std_logic_vector(iBaseMap2_g, addrRes'length - 1);
end architecture rtl; | gpl-2.0 | 4e1c2df19405ab6b822efc31ed63e003 | 0.542377 | 4.761176 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_counter3.vhd | 2 | 4,425 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | a7f44b80307d6636cff1e741b11d718c | 0.654463 | 3.696742 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/PhSeROM.vhd | 1 | 5,796 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: PhSeROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY PhSeROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
rden : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END PhSeROM;
ARCHITECTURE SYN OF phserom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "PhaseSelectErr.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 8,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "PhaseSelectErr.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "PhaseSelectErr.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | d4441a09bc70e8ae3441b809b5bd0229 | 0.67236 | 3.720154 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/openmac/src/openMAC_rmii2mii.vhd | 3 | 10,437 | -------------------------------------------------------------------------------
-- RMII to MII converter
-- ex: openMAC - openHUB - RMII2MII - MII PHY
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rmii2mii is
port (
clk50 : in std_logic; --used by RMII as well!!!
rst : in std_logic;
--RMII (MAC)
rTxEn : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxEr : out std_logic;
--MII (PHY)
mTxEn : out std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxClk : in std_logic;
mRxDv : in std_logic;
mRxEr : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxClk : in std_logic
);
end rmii2mii;
architecture rtl of rmii2mii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, fifo_valid_l, fifo_wrempty : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout, fifo_dout_l : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(rTxDat'range);
begin
fifo_din <= rTxDat & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
fifo_din_reg <= (others => '0');
elsif clk50 = '1' and clk50'event then
if rTxEn = '1' then
sel_dibit <= not sel_dibit;
if sel_dibit = '0' then
fifo_din_reg <= rTxDat;
end if;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
mTxDat <= fifo_dout_l;
mTxEn <= fifo_valid_l;
process(mTxClk, rst)
begin
if rst = '1' then
fifo_rd <= '0';
fifo_valid <= '0';
fifo_dout_l <= (others => '0');
fifo_valid_l <= '0';
elsif mTxClk = '1' and mTxClk'event then
fifo_dout_l <= fifo_dout;
fifo_valid_l <= fifo_valid;
if fifo_rd = '0' and fifo_half = '1' then
fifo_rd <= '1';
elsif fifo_rd = '1' and fifo_empty = '1' then
fifo_rd <= '0';
end if;
if fifo_rd = '1' and fifo_rdUsedWord > conv_std_logic_vector(1, fifo_rdUsedWord'length) then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theRMII2MII_TXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => aclr,
rd_clk => mTxClk,
wr_clk => clk50,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => fifo_wrempty,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(clk50, rst)
begin
if rst = '1' then
aclr <= '1'; --reset fifo
rTxEn_l <= '0';
elsif clk50 = '1' and clk50'event then
rTxEn_l <= rTxEn;
aclr <= '0'; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = '1' and rTxEn_l = '1' and rTxEn = '0' then
aclr <= '1';
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
process(mRxClk, rst)
begin
if rst = '1' then
fifo_din <= (others => '0');
fifo_wr <= '0';
elsif mRxClk = '1' and mRxClk'event then
fifo_din <= mRxDat;
fifo_wr <= mRxDv and not mRxEr;
end if;
end process;
rRxDat <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = '1' else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
rRxDv <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(clk50, rst)
begin
if rst = '1' then
sel_dibit <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '1' or fifo_valid = '1' then
sel_dibit <= not sel_dibit;
else
sel_dibit <= '0';
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
rRxEr <= '0';
process(clk50, rst)
begin
if rst = '1' then
fifo_rd_s <= '0';
fifo_valid <= '0';
elsif clk50 = '1' and clk50'event then
if fifo_rd_s = '0' and fifo_half = '1' then
fifo_rd_s <= '1';
elsif fifo_rd_s = '1' and fifo_empty = '1' then
fifo_rd_s <= '0';
end if;
if fifo_rd_s = '1' then
fifo_valid <= '1';
else
fifo_valid <= '0';
end if;
end if;
end process;
--abuse openMAC's DMA FIFO
theMII2RMII_RXFifo : entity work.openMAC_DMAfifo
generic map (
fifo_data_width_g => NIBBLE_SIZE,
fifo_word_size_g => 2**FIFO_NIBBLES_LOG2,
fifo_word_size_log2_g => FIFO_NIBBLES_LOG2
)
port map (
aclr => rst,
rd_clk => clk50,
wr_clk => mRxClk,
--read port
rd_req => fifo_rd,
rd_data => fifo_dout,
rd_empty => fifo_empty,
rd_full => open,
rd_usedw => fifo_rdUsedWord,
--write port
wr_req => fifo_wr,
wr_data => fifo_din,
wr_empty => open,
wr_full => fifo_full,
wr_usedw => fifo_wrUsedWord
);
end block;
end rtl;
| gpl-2.0 | cbc93035772f85a39586d9ef913f8884 | 0.485676 | 4.143311 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/lib/src/sync.vhd | 3 | 2,543 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
| gpl-2.0 | 815a1561204f9b6f72f82b9ff907d382 | 0.626425 | 4.399654 | false | false | false | false |
scottlbaker/PDP11-SOC | src/sim.vhd | 1 | 2,313 |
--======================================================================
-- sim.vhd :: SOC simulation testbench
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity TEST_TOP is
end TEST_TOP;
architecture BEHAVIORAL of TEST_TOP is
--================================================================
-- Signal and component definition section
--================================================================
-- Output Port A
signal PORTA : std_logic_vector(7 downto 0);
-- UART
signal UART_RXD : std_logic; -- receive data
signal UART_TXD : std_logic; -- transmit data
-- reset and clock
signal RESET : std_logic; -- system reset
signal FCLK : std_logic; -- fast clock
component SOC
port (
-- Output Port A
PORTA : out std_logic_vector(7 downto 0);
-- UART
UART_RXD : in std_logic; -- receive data
UART_TXD : out std_logic; -- transmit data
-- reset and clock
SYSRESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
MAKE_FCLK:
process(FCLK)
begin
if (FCLK = '1') then
FCLK <= '0' after 1 ns;
else
FCLK <= '1' after 1 ns;
end if;
end process;
MAKE_RESET:
process
begin
-- System Reset (active low)
RESET <= '0' after 0 ns, '1' after 10 ns;
wait;
end process;
UART_RXD <= '0';
--============================================
-- Instantiate the SOC
--============================================
MYSOC:
SOC port map (
PORTA => PORTA,
UART_RXD => UART_RXD,
UART_TXD => UART_TXD,
SYSRESET => RESET,
FCLK => FCLK
);
end BEHAVIORAL;
| gpl-3.0 | 6259110c14b37cd5f4f29bb5506c4d2a | 0.38262 | 5.117257 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part5/DE1version/char_7seg.vhd | 1 | 426 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;
ARCHITECTURE Behavior OF char_7seg IS
BEGIN -- Behavior
Display(0) <= C(0);
Display(1) <= NOT(C(1)) OR C(0);
Display(2) <= C(0);
Display(3) <= C(0);
Display(4) <= C(1);
Display(5) <= C(1);
Display(6) <= NOT(C(1)) OR C(0);
END Behavior; | unlicense | cee2dd67a57672f821c1092f64301749 | 0.603286 | 2.505882 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_shiftreg12.vhd | 2 | 4,155 | -- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: lpm_shiftreg12.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_shiftreg12 IS
PORT
(
clock : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC
);
END lpm_shiftreg12;
ARCHITECTURE SYN OF lpm_shiftreg12 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC ;
shiftin : IN STD_LOGIC
);
END COMPONENT;
BEGIN
shiftout <= sub_wire0;
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 12
)
PORT MAP (
clock => clock,
shiftin => shiftin,
shiftout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg12.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg12.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg12.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg12.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg12_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 14e007baf80ae4f58e0494eb56ba9794 | 0.658002 | 3.865116 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/xilinx/openmac/src/n_synchronizer.vhd | 3 | 3,037 | -------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the n sychronizer.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_g is
generic(N: natural);
port(
clk, reset: in std_logic;
in_async: in std_logic_vector(N-1 downto 0);
out_sync: out std_logic_vector(N-1 downto 0)
);
end synchronizer_g;
architecture two_ff_arch of synchronizer_g is
signal meta_reg, sync_reg, sync_reg1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal meta_next, sync_next, sync_next1 : std_logic_vector(N-1 downto 0) := (others => '0');
begin
-- two registers
process(clk)--,reset)
begin
-- if (reset='1') then
-- meta_reg <= (others=>'0');
-- sync_reg <= (others=>'0');
-- sync_reg1 <= (others => '0');
if (clk'event and clk='1') then
meta_reg <= meta_next;
sync_reg <= sync_next;
sync_reg1 <= sync_next1;
end if;
end process;
-- next-state logic
meta_next <= in_async;
sync_next <= meta_reg;
sync_next1 <= sync_reg;
-- output
out_sync <= sync_reg1;
end two_ff_arch; | gpl-2.0 | 40a2355d0272255510735b988e6881cc | 0.636813 | 4.087483 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/pdi/src/pdi_spi.vhd | 3 | 13,652 | -------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_spi is
generic (
spiSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false;
spiBigEnd_g : boolean := false
);
port (
-- SPI
spi_clk : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic;
spi_mosi : in std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0)
);
end entity pdi_spi;
architecture rtl of pdi_spi is
--wake up command
constant cmdWakeUp : std_logic_vector(7 downto 0) := x"03"; --0b00000011
constant cmdWakeUp1 : std_logic_vector(7 downto 0) := x"0A"; --0b00001010
constant cmdWakeUp2 : std_logic_vector(7 downto 0) := x"0C"; --0b00001100
constant cmdWakeUp3 : std_logic_vector(7 downto 0) := x"0F"; --0b00001111
--spi frame constants
constant cmdHighaddr_c : std_logic_vector(2 downto 0) := "100";
constant cmdMidaddr_c : std_logic_vector(2 downto 0) := "101";
constant cmdWr_c : std_logic_vector(2 downto 0) := "110";
constant cmdRd_c : std_logic_vector(2 downto 0) := "111";
constant cmdWRSQ_c : std_logic_vector(2 downto 0) := "001";
constant cmdRDSQ_c : std_logic_vector(2 downto 0) := "010";
constant cmdLowaddr_c : std_logic_vector(2 downto 0) := "011";
constant cmdIdle_c : std_logic_vector(2 downto 0) := "000";
--pdi_spi control signals
type fsm_t is (reset, reset1, reset2, reset3, idle, decode, waitwr, waitrd, wr, rd);
signal fsm : fsm_t;
signal addrReg : std_logic_vector(ap_address'left+2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal highPriorLoad : std_logic;
signal highPriorLoadVal : std_logic_vector(spiSize_g-1 downto 0);
--spi core signals
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector(spiSize_g-1 downto 0);
signal load : std_logic;
signal dout : std_logic_vector(spiSize_g-1 downto 0);
signal valid : std_logic;
--
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
begin
clk <= ap_clk;
rst <= ap_reset;
ap_chipselect <= '1' when fsm = wr or fsm = rd or fsm = waitrd else '0';
ap_write <= '1' when fsm = wr else '0';
ap_read <= '1' when fsm = waitrd or fsm = rd else '0';
ap_address <= addrReg(addrReg'left downto 2);
ap_byteenable <= ap_byteenable_s;
ap_byteenable_s <= --little endian
"0001" when addrReg(1 downto 0) = "00" and spiBigEnd_g = false else
"0010" when addrReg(1 downto 0) = "01" and spiBigEnd_g = false else
"0100" when addrReg(1 downto 0) = "10" and spiBigEnd_g = false else
"1000" when addrReg(1 downto 0) = "11" and spiBigEnd_g = false else
--big endian
--"0001" when addrReg(1 downto 0) = "11" and spiBigEnd_g = true else
--"0010" when addrReg(1 downto 0) = "10" and spiBigEnd_g = true else
--"0100" when addrReg(1 downto 0) = "01" and spiBigEnd_g = true else
--"1000" when addrReg(1 downto 0) = "00" and spiBigEnd_g = true else
"0000";
ap_writedata <= (dout & dout & dout & dout);
din <= highPriorLoadVal when highPriorLoad = '1' else --load value that was just received
ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
load <= '1' when highPriorLoad = '1' else --load value that was just received
'1' when fsm = rd else --load data from pdi to spi shift register
'0';
cmd <= dout(dout'left downto dout'left-2); --get cmd pattern
highPriorLoadVal <= not dout; --create inverse of received pattern
thePdiSpiFsm : process(clk, rst)
variable timeout : integer range 0 to 3;
variable writes : integer range 0 to 32;
variable reads : integer range 0 to 32;
begin
if rst = '1' then
fsm <= reset;
timeout := 0;
writes := 0; reads := 0;
addrReg <= (others => '0');
highPriorLoad <= '0';
elsif clk = '1' and clk'event then
--default assignment
highPriorLoad <= '0';
case fsm is
when reset =>
fsm <= reset;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp then
--wake up command (1/4) received
fsm <= reset1;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset1 =>
fsm <= reset1;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp1 then
--wake up command (2/4) sequence was correctly decoded!
fsm <= reset2;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset2 =>
fsm <= reset2;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp2 then
--wake up command (3/4) sequence was correctly decoded!
fsm <= reset3;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset3 =>
fsm <= reset3;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp3 then
--wake up command (4/4) sequence was correctly decoded!
fsm <= idle;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when idle =>
if writes /= 0 then
fsm <= waitwr;
elsif reads /= 0 and valid = '1' then
fsm <= waitrd;
elsif valid = '1' then
fsm <= decode;
else
fsm <= idle;
end if;
when decode =>
fsm <= idle; --default
case cmd is
when cmdHighaddr_c =>
addrReg(addrReg'left downto addrReg'left-4) <= dout(spiSize_g-4 downto 0);
when cmdMidaddr_c =>
addrReg(addrReg'left-5 downto addrReg'left-9) <= dout(spiSize_g-4 downto 0);
when cmdLowaddr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
when cmdWr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitwr;
writes := 1;
when cmdRd_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitrd;
reads := 1;
when cmdWRSQ_c =>
fsm <= waitwr;
writes := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are written
when cmdRDSQ_c =>
fsm <= waitrd;
reads := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are read
when cmdIdle_c =>
--don't interpret the command, inverse pattern and goto idle
when others =>
--error, goto idle
end case;
when waitwr =>
--wait for data from spi master
if valid = '1' then
fsm <= wr;
else
fsm <= waitwr;
end if;
when waitrd =>
--spi master wants to read
--wait for dpr to read
if timeout = 3 then
fsm <= rd;
timeout := 0;
else
timeout := timeout + 1;
fsm <= waitrd;
end if;
when wr =>
fsm <= idle;
writes := writes - 1;
addrReg <= addrReg + 1;
when rd =>
fsm <= idle;
reads := reads - 1;
addrReg <= addrReg + 1;
end case;
end if;
end process;
theSpiCore : entity work.spi
generic map (
frameSize_g => spiSize_g,
cpol_g => cpol_g,
cpha_g => cpha_g
)
port map (
-- Control Interface
clk => clk,
rst => rst,
din => din,
load => load,
dout => dout,
valid => valid,
-- SPI
sck => spi_clk,
ss => spi_sel,
miso => spi_miso,
mosi => spi_mosi
);
end architecture rtl;
| gpl-2.0 | d83de3fff008b86140ebdd0eaf7911f7 | 0.451582 | 4.825733 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part5/circuitb.vhd | 3 | 723 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY circuitb IS
PORT (SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END circuitb;
ARCHITECTURE Behavior OF circuitb IS
BEGIN
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= SW;
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= '0';
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= '0';
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= SW;
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= SW;
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= SW;
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= '1';
END Behavior; | unlicense | 1732aea1e345c8ca7981df0b10e7b69f | 0.4426 | 2.224615 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/blockPHfinding.vhd | 2 | 1,793 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity blockPHfinding is
port (clk_i : in std_logic;
reset_i : in std_logic;
framing_i : in std_logic;
block_o : out std_logic);
end blockPHfinding;
architecture rtl of blockPHfinding is
type t_state is (waiting,
tick1,
tick2,
tick3,
tick4);
signal s_state : t_state;
begin
p_monoflop: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
block_o <= '0';
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick1 =>
block_o <= '1';
s_state <= tick2 ;
-------------------------------------------------------------------------
when tick2 =>
block_o <= '1';
s_state <= tick3 ;
-------------------------------------------------------------------------
when tick3 =>
block_o <= '1';
s_state <= tick4 ;
-------------------------------------------------------------------------
when tick4 =>
block_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if framing_i = '1' then
s_state <= tick1;
else
block_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_monoflop;
end rtl;
| unlicense | 09d82ad5b436d3855300a0c27ee3c827 | 0.343001 | 4.706037 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/PXData_FSM.vhd | 2 | 6,728 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PXData_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
PX_start_i : in std_logic;
PX_present_i : in std_logic;
PX_data_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
PXwen_o : out std_logic);
end PXData_FSM;
architecture rtl of PXData_FSM is
type t_state is (waiting,
tick_C5,
tick_C4,
tick_C3,
tick_C2,
tick_C1,
tick_C0,
tick_R8,
tick_R7,
tick_R6,
tick_R5,
tick_R4,
tick_R3,
tick_R2,
tick_R1,
tick_R0,
tick_P7,
tick_P6,
tick_P5,
tick_P4,
tick_0,
tick_P3,
tick_P2,
tick_P1,
tick_P0);
signal s_state : t_state;
--signal s_count : unsigned(3 downto 0);
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
PXwen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_C5 =>
if ( PX_present_i= '1' ) then
-- pxl data present
PXwen_o <= '0';
type_o <= "0000";
payload_o(3)<=PX_data_i;
s_state <= tick_C4;
else
PXwen_o <= '0';
type_o <= "0000";
s_state <= waiting;
end if;
-------------------------------------------------------------------------
when tick_C4 =>
payload_o(2)<=PX_data_i;
s_state <= tick_C3 ;
-------------------------------------------------------------------------
when tick_C3 =>
payload_o(1)<=PX_data_i;
s_state <= tick_C2 ;
-------------------------------------------------------------------------
when tick_C2 =>
payload_o(0)<=PX_data_i;
PXwen_o <= '1';
type_o <= "0001";
s_state <= tick_C1 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_C1 =>
payload_o(3)<=PX_data_i;
PXwen_o <= '0';
s_state <= tick_C0 ;
-------------------------------------------------------------------------
when tick_C0 =>
payload_o(2)<=PX_data_i;
s_state <= tick_R8 ;
-------------------------------------------------------------------------
when tick_R8 =>
payload_o(1)<=PX_data_i;
s_state <= tick_R7 ;
-------------------------------------------------------------------------
when tick_R7 =>
payload_o(0)<=PX_data_i;
PXwen_o <= '1';
type_o <= "0010";
s_state <= tick_R6 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_R6 =>
payload_o(3)<=PX_data_i;
PXwen_o <= '0';
s_state <= tick_R5 ;
-----------------------------------------------------------------------
when tick_R5 =>
payload_o(2)<=PX_data_i;
s_state <= tick_R4 ;
-------------------------------------------------------------------------
when tick_R4 =>
payload_o(1)<=PX_data_i;
s_state <= tick_R3 ;
-------------------------------------------------------------------------
when tick_R3 =>
payload_o(0)<=PX_data_i;
PXwen_o <= '1';
type_o <= "0011";
s_state <= tick_R2 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_R2 =>
payload_o(3)<=PX_data_i;
PXwen_o <= '0';
s_state <= tick_R1 ;
-------------------------------------------------------------------------
when tick_R1 =>
payload_o(2)<=PX_data_i;
s_state <= tick_R0 ;
-------------------------------------------------------------------------
when tick_R0 =>
payload_o(1)<=PX_data_i;
s_state <= tick_P7 ;
-------------------------------------------------------------------------
when tick_P7 =>
payload_o(0)<=PX_data_i;
PXwen_o <= '1';
type_o <= "0100";
s_state <= tick_P6 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_P6 =>
payload_o(3)<=PX_data_i;
PXwen_o <= '0';
s_state <= tick_P5 ;
-------------------------------------------------------------------------
when tick_P5 =>
payload_o(2)<=PX_data_i;
s_state <= tick_P4 ;
-----------------------------------------------------------------------
when tick_P4 =>
payload_o(1)<=PX_data_i;
s_state <= tick_0 ;
-------------------------------------------------------------------------
when tick_0 =>
payload_o(0)<=PX_data_i;
PXwen_o <= '1';
type_o <= "0101";
s_state <= tick_P3 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when tick_P3 =>
payload_o(3)<=PX_data_i;
PXwen_o <= '0';
s_state <= tick_P2 ;
-------------------------------------------------------------------------
when tick_P2 =>
payload_o(2)<=PX_data_i;
s_state <= tick_P1 ;
-------------------------------------------------------------------------
when tick_P1 =>
payload_o(1)<=PX_data_i;
s_state <= tick_P0 ;
-------------------------------------------------------------------------
when tick_P0 =>
payload_o(0)<=PX_data_i;
PXwen_o <= '1';
type_o <= "0110";
s_state <= tick_C5 ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if PX_start_i = '1' then
s_state <= tick_C5;
else
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
| unlicense | 869afb4f4395531831ea899fe538f561 | 0.279132 | 4.533693 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part6/bin2bcd_12bit.vhd | 1 | 2,142 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity bin2bcd_12bit is
Port ( binIN : in STD_LOGIC_VECTOR (11 downto 0);
ones : out STD_LOGIC_VECTOR (3 downto 0);
tens : out STD_LOGIC_VECTOR (3 downto 0);
hundreds : out STD_LOGIC_VECTOR (3 downto 0);
thousands : out STD_LOGIC_VECTOR (3 downto 0)
);
end bin2bcd_12bit;
architecture Behavioral of bin2bcd_12bit is
begin
bcd1: process(binIN)
-- temporary variable
variable temp : STD_LOGIC_VECTOR (11 downto 0);
-- variable to store the output BCD number
-- organized as follows
-- thousands = bcd(15 downto 12)
-- hundreds = bcd(11 downto 8)
-- tens = bcd(7 downto 4)
-- units = bcd(3 downto 0)
variable bcd : UNSIGNED (15 downto 0) := (others => '0');
-- by
-- https://en.wikipedia.org/wiki/Double_dabble
begin
-- zero the bcd variable
bcd := (others => '0');
-- read input into temp variable
temp(11 downto 0) := binIN;
-- cycle 12 times as we have 12 input bits
-- this could be optimized, we dont need to check and add 3 for the
-- first 3 iterations as the number can never be >4
for i in 0 to 11 loop
if bcd(3 downto 0) > 4 then
bcd(3 downto 0) := bcd(3 downto 0) + 3;
end if;
if bcd(7 downto 4) > 4 then
bcd(7 downto 4) := bcd(7 downto 4) + 3;
end if;
if bcd(11 downto 8) > 4 then
bcd(11 downto 8) := bcd(11 downto 8) + 3;
end if;
-- thousands can't be >4 for a 12-bit input number
-- so don't need to do anything to upper 4 bits of bcd
-- shift bcd left by 1 bit, copy MSB of temp into LSB of bcd
bcd := bcd(14 downto 0) & temp(11);
-- shift temp left by 1 bit
temp := temp(10 downto 0) & '0';
end loop;
-- set outputs
ones <= STD_LOGIC_VECTOR(bcd(3 downto 0));
tens <= STD_LOGIC_VECTOR(bcd(7 downto 4));
hundreds <= STD_LOGIC_VECTOR(bcd(11 downto 8));
thousands <= STD_LOGIC_VECTOR(bcd(15 downto 12));
end process bcd1;
end Behavioral;
| unlicense | 904e555d994d5f74b9688a7dfe864d2b | 0.584967 | 3.57596 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/altera/openmac/src/openMAC_DPR.vhd | 3 | 10,368 | -------------------------------------------------------------------------------
-- OpenMAC - DPR for Altera FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 16 / 16 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "BIDIR_DUAL_PORT", INIT_FILE => "dpr_16_16.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 16, WIDTHAD_B => 8, NUMWORDS_B => 256, WIDTH_BYTEENA_B => 2
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA, wren_b => WeB,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA, byteena_b => BeB,
address_a => AddrA, address_b => AddrB,
data_a => DiA, data_b => DiB,
q_a => DoA, q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- 16 / 32 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "DUAL_PORT", INIT_FILE => "dpr_16_32.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 32, WIDTHAD_B => 7, NUMWORDS_B => 128
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA,
address_a => AddrA, address_b => AddrB,
data_a => DiA,
q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- Packet buffer
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
ARCHITECTURE SYN OF openmac_dprpackets IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
rden_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rden_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => memSize_g/2,
numwords_b => memSize_g/4,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => memSizeLOG2_g-1,
widthad_b => memSizeLOG2_g-2,
width_a => 16,
width_b => 32,
width_byteena_a => 2,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
rden_a => rden_a,
rden_b => rden_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 | 6fbdee30608103f78aef7594a79f934c | 0.511381 | 3.724138 | false | false | false | false |
Alix82/mip32vhdl | mips.vhd | 1 | 7,830 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mips_constants.all;
Entity mips is
port(inInstruction : in std_logic_vector(31 downto 0);
Clk : in std_logic;
reset : in std_logic;
O_Fetch : out std_logic;
O_PCNext : out std_logic_vector(31 downto 0);
outMemAddr : out std_logic_vector(31 downto 0);
outMemRead : out std_logic;
inMemReadData : in std_logic_vector(31 downto 0);
inMemRead : in std_logic;
outMemWrite : out std_logic;
outMemWriteData : out std_logic_vector(31 downto 0)
--error_control : out std_logic
);
End mips;
Architecture rtl of mips is
component DECODER is
port(
clk : in std_logic;
instruction : in std_logic_vector(31 downto 0);
pcD : in std_logic_vector(31 downto 0);
discard : in std_logic;
decoded : out std_logic_vector(11 downto 0);
opcode : out std_logic_vector(5 downto 0);
func : out std_logic_vector(5 downto 0);
shamt : out std_logic_vector(4 downto 0);
pcF : out std_logic_vector(31 downto 0);
Reg1 : out std_logic_vector(4 downto 0);
Reg2 : out std_logic_vector(4 downto 0);
Reg3 : out std_logic_vector(4 downto 0);
Fetch : out std_logic
);
end component DECODER;
component ALU is
port(clk : in std_logic;
reset : in std_logic;
pcF : in std_logic_vector(31 downto 0);
opcode : in std_logic_vector(5 downto 0);
func : in std_logic_vector(5 downto 0);
shamt : in std_logic_vector(4 downto 0);
InstReg1 : in std_logic_vector(4 downto 0);
InstReg2 : in std_logic_vector(4 downto 0);
InstReg3 : in std_logic_vector(4 downto 0);
instructionExt : in std_logic_vector(31 downto 0);
control : in std_logic_vector(11 downto 0);
fetch : in std_logic;
inwriteregdata : in std_logic_vector(31 downto 0);
inwritereg : in std_logic;
memtoreg : out std_logic;
memread : out std_logic;
memwrite : out std_logic;
outZero : out std_logic;
outAluResult : out std_logic_vector(31 downto 0);
outwriteData : out std_logic_vector(31 downto 0);
alu_pause : out std_logic
);
end component ALU;
component MEMORY_RW is
Port (clk : in std_logic;
inaluresult : in std_logic_vector(31 downto 0);
memwritedata : in std_logic_vector(31 downto 0);
memtoreg : in std_logic;
memread : in std_logic;
memwrite : in std_logic;
o_memaddr : out std_logic_vector(31 downto 0);
o_read : out std_logic;
o_write : out std_logic;
o_writedata : out std_logic_vector(31 downto 0)
);
end component MEMORY_RW;
component SIGNEXTEND is
Port (
clk : in std_logic;
in16 : in std_logic_vector(15 downto 0);
out32 : out std_logic_vector(31 downto 0)
);
end component SIGNEXTEND;
component PC_BRIDGE is
Port (clk : in std_logic;
i_operation : in std_logic_vector(11 downto 0);
i_instrext : in std_logic_vector(31 downto 0);
o_instrext : out std_logic_vector(31 downto 0);
jump : out std_logic;
branch : out std_logic;
jumptoreg : out std_logic
);
end component;
component PC_NEXT is
Port (clk : in std_logic;
reset : in std_logic;
i_instrext : in std_logic_vector(31 downto 0);
i_alu_result : in std_logic_vector(31 downto 0);
pause : in std_logic;
aluzero : in std_logic;
jump : in std_logic;
branch : in std_logic;
jumptoreg : in std_logic;
discard : out std_logic;
pcnext : out std_logic_vector(31 downto 0)
);
end component;
signal fetch : std_logic := '1';
signal alu_pause : std_logic := '0';
signal operationD : std_logic_vector (11 downto 0) := (others => '0');
signal pcnext : std_logic_vector(31 downto 0) := (others => '0');
signal pcF : std_logic_vector(31 downto 0) := (others => '0');
signal instructionExtended : std_logic_vector(31 downto 0) := (others => '0');
signal instructionExtPC : std_logic_vector(31 downto 0) := (others => '0');
signal alu_zero : std_logic := '0';
signal alu_result : std_logic_vector(31 downto 0) := (others => '0');
signal alu_mem_write : std_logic_vector(31 downto 0) := (others => '0');
signal alu_opcode : std_logic_vector(5 downto 0) := (others => '0');
signal alu_func : std_logic_vector(5 downto 0) := (others => '0');
signal alu_shamt : std_logic_vector(4 downto 0) := (others => '0');
signal InstReg1 : std_logic_vector(4 downto 0) := (others => '0');
signal InstReg2 : std_logic_vector(4 downto 0) := (others => '0');
signal InstReg3 : std_logic_vector(4 downto 0) := (others => '0');
signal memtoreg : std_logic := '0';
signal memread : std_logic := '0';
signal memwrite : std_logic := '0';
signal jump : std_logic := '0';
signal jumptoreg : std_logic := '0';
signal branch : std_logic := '0';
signal discard : std_logic := '0';
signal clk_counter : integer := 0;
begin
O_PCNext <= pcnext;
O_Fetch <= not alu_pause;
process(clk) begin
if rising_edge(clk) then
clk_counter <= clk_counter +1;
end if;
end process;
--------------------------------------------------------------------
-- STAGE 1 FETCH/DECODE
--------------------------------------------------------------------
DECODER0: DECODER port map (clk, ininstruction, pcnext,
discard, operationD, alu_opcode, alu_func, alu_shamt,
pcF,
InstReg1, InstReg2, InstReg3, fetch);
SIGNEXTEND0: SIGNEXTEND port map (clk, ininstruction(15 downto 0), instructionExtended);
--------------------------------------------------------------------
-- STAGE 2
--------------------------------------------------------------------
ALU0: ALU port map (clk, reset, pcF,
alu_opcode, alu_func, alu_shamt,
InstReg1, InstReg2, InstReg3,
instructionExtended, operationD, fetch, inMemReadData, inMemRead, memtoreg, memread, memwrite,
alu_zero, alu_result, alu_mem_write, alu_pause);
PC_BRIDGE0: PC_BRIDGE port map (clk, operationD, instructionExtended, instructionExtPC, jump, branch, jumptoreg);
--------------------------------------------------------------------
-- STAGE 3 Memory
--------------------------------------------------------------------
MEMORY_RW0: MEMORY_RW port map (clk, alu_result, alu_mem_write,
memtoreg, memread, memwrite, outMemAddr, outMemRead, outMemWrite, outMemWriteData);
PC_NEXT0: PC_NEXT port map (clk, reset, instructionExtPC, alu_result, alu_pause, alu_zero, jump, branch, jumptoreg, discard, pcnext);
end rtl;
| bsd-2-clause | 9db2c701d89e84fa61789122d7c588f4 | 0.507918 | 4.101624 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part6a/sweep2.vhd | 2 | 550 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sweep is
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
end sweep;
architecture arch of sweep is
signal q: std_logic_vector(9 downto 0);
begin
--clock divider
process(mclk)
begin
if q = "1111111111" then
q <= "0000000000";
elsif mclk'event and mclk = '1' then
q <= std_logic_vector(unsigned(q)+1);
end if;
end process;
sweep_out <= q(9)&q(8);
end arch; | unlicense | bc13b49b8f7b356105715de797f21d19 | 0.590909 | 3.374233 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/PriorEncoder.vhd | 2 | 736 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PriorEncode is
port (IN_Xor : in std_logic_vector(7 downto 0) ;
OUT_sel : out std_logic_vector(2 downto 0) );
end PriorEncode;
architecture Behaviorial of PriorEncode is
begin
OUT_sel <= "000" when IN_Xor ="00000001" else
"001" when IN_Xor ="00000010" else
"010" when IN_Xor ="00000100" else
"011" when IN_Xor ="00001000" else
"100" when IN_Xor ="00010000" else
"101" when IN_Xor ="00100000" else
"110" when IN_Xor ="01000000" else
"111" when IN_Xor ="10000000" ;
end Behaviorial;
| unlicense | 792047530616cd3bb4bbef35f668072a | 0.548913 | 3.643564 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/TSR1.vhd | 2 | 4,082 | -- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: TSR1.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY TSR1 IS
PORT
(
clock : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END TSR1;
ARCHITECTURE SYN OF tsr1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
shiftin : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 10
)
PORT MAP (
clock => clock,
shiftin => shiftin,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL TSR1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL TSR1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL TSR1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL TSR1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL TSR1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 9e2301ae3d275b69310a110fd048711e | 0.648947 | 3.76916 | false | false | false | false |
systec-dk/openPOWERLINK_systec | Examples/ipcore/common/pdi/src/pdi_tripleVBufLogic.vhd | 3 | 13,800 | -------------------------------------------------------------------------------
-- Triple Buffer Control Logic
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- This logic implements the virtual triple buffers, by selecting the
-- appropriate address offset. The output address offset has to be added to the
-- input address. The trigger signal switches to the next available buffer.
-- The switch mechanism is implemented in the PCP's clock domain. Thus the
-- switch over on the PCP side is performed without delay. An AP switch over
-- crosses from AP to PCP clock domain (2x pcpClk) and back from PCP to AP
-- (2x apClk).
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY tripleVBufLogic IS
GENERIC(
genOnePdiClkDomain_g : boolean := false;
--base address of virtual buffers in DPR
iVirtualBufferBase_g : INTEGER := 0;
--size of one virtual buffer in DPR (must be aligned!!!)
iVirtualBufferSize_g : INTEGER := 1024;
--out address width
iOutAddrWidth_g : INTEGER := 13;
--in address width
iInAddrWidth_g : INTEGER := 11;
--ap is producer
bApIsProducer : BOOLEAN := FALSE
);
PORT (
pcpClk : IN STD_LOGIC;
pcpReset : IN STD_LOGIC;
pcpTrigger : IN STD_LOGIC; --trigger virtual buffer change
--pcpInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
pcpOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
pcpOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer (one-hot coded)
apClk : IN STD_LOGIC;
apReset : IN STD_LOGIC;
apTrigger : IN STD_LOGIC; --trigger virtual buffer change
--apInAddr : IN STD_LOGIC_VECTOR(iInAddrWidth_g-1 DOWNTO 0);
apOutAddrOff : OUT STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
apOutSelVBuf : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) --selected virtual buffer (one-hot coded)
);
END ENTITY tripleVBufLogic;
ARCHITECTURE rtl OF tripleVBufLogic IS
--constants
---virtual buffer base address
CONSTANT iVirtualBufferBase0_c : INTEGER := 0*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase1_c : INTEGER := 1*iVirtualBufferSize_g + iVirtualBufferBase_g;
CONSTANT iVirtualBufferBase2_c : INTEGER := 2*iVirtualBufferSize_g + iVirtualBufferBase_g;
---one hot code
constant cOneHotVirtualBuffer0 : std_logic_vector(2 downto 0) := "001";
constant cOneHotVirtualBuffer1 : std_logic_vector(2 downto 0) := "010";
constant cOneHotVirtualBuffer2 : std_logic_vector(2 downto 0) := "100";
---triple buffer mechanism
----initial states
CONSTANT initialValid_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer0;
CONSTANT initialLocked_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer1;
CONSTANT initialCurrent_c : STD_LOGIC_VECTOR(2 DOWNTO 0) := cOneHotVirtualBuffer2;
--signals
---PCP and AP selected virtual buffer
SIGNAL pcpSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by producer
SIGNAL apSelVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --selected virtual buffer by consumer
SIGNAL lockedVBuf_s : STD_LOGIC_VECTOR(2 DOWNTO 0); --locked virtual buffer in producer clk domain
BEGIN
pcpOutSelVBuf <= pcpSelVBuf_s;
apOutSelVBuf <= apSelVBuf_s;
theAddrCalcer : BLOCK
--depending on the selected virtual buffer (???SelVBuf_s), the output address is calculated (???OutAddr)
-- ???SelVBuf_s | ???OutAddr
-- -------------------------
-- "001" | ???InAddr + iVirtualBufferBase0_c
-- "010" | ???InAddr + iVirtualBufferBase1_c
-- "100" | ???InAddr + iVirtualBufferBase2_c
SIGNAL pcpAddrOffset, apAddrOffset: STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
--SIGNAL pcpSum, apSum : STD_LOGIC_VECTOR(iOutAddrWidth_g DOWNTO 0);
BEGIN
--select address offset
pcpAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, pcpAddrOffset'LENGTH) WHEN pcpSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
pcpOutAddrOff <= pcpAddrOffset;
--calculate address for dpr, leading zero is a sign!
--pcpSum <= ('0' & conv_std_logic_vector(conv_integer(pcpInAddr), iOutAddrWidth_g-1)) + ('0' & pcpAddrOffset);
--pcpOutAddr <= pcpSum(pcpOutAddr'RANGE);
--select address offset
apAddrOffset <= CONV_STD_LOGIC_VECTOR(iVirtualBufferBase0_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer0 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase1_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer1 ELSE
CONV_STD_LOGIC_VECTOR(iVirtualBufferBase2_c, apAddrOffset'LENGTH) WHEN apSelVBuf_s = cOneHotVirtualBuffer2 ELSE
(OTHERS => '0');
apOutAddrOff <= apAddrOffset;
--calculate address for dpr, leading zero is a sign!
--apSum <= ('0' & conv_std_logic_vector(conv_integer(apInAddr), iOutAddrWidth_g-1)) + ('0' & apAddrOffset);
--apOutAddr <= apSum(apOutAddr'RANGE);
END BLOCK theAddrCalcer;
theLockSync : block
constant cBinLockWidth : integer := 2;
constant cBinLock0 : std_logic_vector(cBinLockWidth-1 downto 0) := "01";
constant cBinLock1 : std_logic_vector(cBinLockWidth-1 downto 0) := "11";
constant cBinLock2 : std_logic_vector(cBinLockWidth-1 downto 0) := "10";
signal binLockedVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
signal binApSelVBuf : std_logic_vector(cBinLockWidth-1 downto 0);
begin
--conSelVBuf_s is in the PCP clock domain, thus the lockedVBuf_s signal must be
-- synchronized from PCP clock- to AP clock domain!
--In addition the one hot approach is transformed to save one line
binLockedVBuf <= cBinLock0 when lockedVBuf_s = cOneHotVirtualBuffer0 else
cBinLock1 when lockedVBuf_s = cOneHotVirtualBuffer1 else
cBinLock2;
apSelVBuf_s <= cOneHotVirtualBuffer0 when binApSelVBuf = cBinLock0 else
cOneHotVirtualBuffer1 when binApSelVBuf = cBinLock1 else
cOneHotVirtualBuffer2;
vectorSync : FOR i in cBinLockWidth-1 DOWNTO 0 GENERATE
theLockedSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => binLockedVBuf(i),
dout => binApSelVBuf(i),
clk => apClk,
rst => apReset
);
END GENERATE;
end block;
theTripleBufferLogic : BLOCK
--The PCP triggers with triggerA and sets buffers to valid.
--The AP triggers with triggerB and locks buffers for reading.
SIGNAL clk, rst : STD_LOGIC;
SIGNAL triggerA : STD_LOGIC;
SIGNAL triggerB, triggerB_s : STD_LOGIC; --triggerB is in AP clock domain!
SIGNAL toggleB, toggleBsync : STD_LOGIC; --toggleB is toggled by AP and synced to PCP
SIGNAL toggleEdge : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL locked : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL currentA : STD_LOGIC_VECTOR(2 DOWNTO 0); --current selected buffer by PCP
-- SIGNAL valid : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
--triple buffer logic is implemented in PCP clock domain!
clk <= pcpClk;
rst <= pcpReset;
--triggerA is the producer's trigger
triggerA <= pcpTrigger when bApIsProducer = false else triggerB_s;
--conTrigger pulse is in AP clock domain, thus different clock rates will produce more or less pulses!
---thus a toggling signal crosses the clock domain
genToggleB : PROCESS(apClk, apReset)
BEGIN
IF apReset = '1' THEN
toggleB <= '0';
ELSIF apClk = '1' AND apClk'EVENT THEN --CAUTION: AP clock is used!
IF apTrigger = '1' THEN
toggleB <= not toggleB;
END IF;
END IF;
END PROCESS genToggleB;
theToggleSync : ENTITY work.sync
generic map (
doSync_g => not genOnePdiClkDomain_g
)
PORT MAP
(
din => toggleB,
dout => toggleBsync,
clk => clk,
rst => rst
);
toggleShiftReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
toggleEdge <= (OTHERS => '0');
ELSIF clk = '1' AND clk'event THEN
--shift register
toggleEdge <= toggleEdge(0) & toggleBsync;
END IF;
END PROCESS toggleShiftReg;
triggerB_s <= toggleEdge(1) xor toggleEdge(0);
--triggerB is the consumer's trigger
triggerB <= triggerB_s when bApIsProducer = false else pcpTrigger;
--currentA is set by PCP (currently used buffer by PCP)
pcpSelVBuf_s <= currentA when bApIsProducer = false else locked;
--locked virtual buffer in PCP clock domain
lockedVBuf_s <= locked when bApIsProducer = false else currentA;
tripleBufMechanism : PROCESS(clk, rst)
VARIABLE valid_v : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF rst = '1' THEN
--initial state:
---buffer "001" is valid
valid_v := initialValid_c;
---buffer "010" is locked
locked <= initialLocked_c;
---buffer "100" is currently used by PCP
currentA <= initialCurrent_c;
ELSIF clk = '1' AND clk'EVENT THEN
IF triggerA = '1' THEN
--PCP triggers buffer change
---set valid to current selected buffer
---search for free buffer (not locked and valid)
valid_v := currentA;
--free buffer search ex.:
-- locked "001"
-- valid "010"
-- ============
-- free "100"
currentA <= not locked and not valid_v;
END IF;
IF triggerB = '1' THEN
--AP triggers buffer change
---change AP to valid buffer
locked <= valid_v;
END IF;
END IF;
END PROCESS tripleBufMechanism;
END BLOCK theTripleBufferLogic;
END ARCHITECTURE rtl;
| gpl-2.0 | ee626392ed1ec7e4c4694ceed977e7e8 | 0.563841 | 4.775087 | false | false | false | false |
Alix82/mip32vhdl | mult.vhd | 1 | 7,426 | ---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- To reduce space, compile your code using the flag "-mno-mul" which
-- will use software base routines in math.c if USE_SW_MULT is defined.
-- Then remove references to the entity mult in mlite_cpu.vhd.
--
-- MULTIPLICATION
-- long64 answer = 0;
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
library work;
use work.mips_constants.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0) := (others => '0');
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO
and negate_reg = '1' else
upper_reg when mult_func = MULT_READ_HI else
ZERO;
pause_out <= '1' when (count_reg /= "000000") else '0';
-- and
-- (mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
--multiplication/division unit
mult_proc: process(clk, reset_in, a, b, mult_func,
a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
variable count : std_logic_vector(2 downto 0);
begin
count := "001";
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
elsif rising_edge(clk) then
case mult_func is
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
else
aa_reg <= a_neg;
bb_reg <= b_neg;
end if;
sign_reg <= a(31) xor b(31);
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
when others =>
if count_reg /= "000000" then
if mode_reg = MODE_MULT then
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
-- count_reg(5 downto 2) /= "0000" then
-- upper_reg <= "0000" & upper_reg(31 downto 4);
-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
-- count := "100";
-- bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
else
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
count_reg <= count_reg - count;
end if; --count
end case;
end if;
end process;
end; --architecture logic
| bsd-2-clause | b78480f1a5617ebb13a62c43042f9c53 | 0.444923 | 3.713 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/lpm_counter5.vhd | 2 | 4,358 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter5.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter5 IS
PORT
(
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_counter5;
ARCHITECTURE SYN OF lpm_counter5 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 5
)
PORT MAP (
clock => clock,
cnt_en => cnt_en,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 036edb4c20c3fa803edcc58d85d1725c | 0.650298 | 3.662185 | false | false | false | false |
kgallspark/Dexter | azido_to_axi_v1_00_a/hdl/vhdl/azido_to_axi.vhd | 1 | 19,423 | ------------------------------------------------------------------------------
-- azido_to_axi.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: azido_to_axi.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Jan 16 14:53:26 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library azido_to_axi_v1_00_a;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_M_AXI_ADDR_WIDTH -- Master-Intf address bus width
-- C_M_AXI_DATA_WIDTH -- Master-Intf data bus width
-- C_MAX_BURST_LEN -- Max no. of data-beats allowed in burst
-- C_NATIVE_DATA_WIDTH -- Internal bus width on user-side
-- C_LENGTH_WIDTH -- Master interface data bus width
-- C_ADDR_PIPE_DEPTH -- Depth of Address pipelining
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
-- m_axi_aclk -- AXI4 master: Clock
-- m_axi_aresetn -- AXI4 master: Reset
-- md_error -- AXI4 master: Error
-- m_axi_arready -- AXI4 master: read address ready
-- m_axi_arvalid -- AXI4 master: read address valid
-- m_axi_araddr -- AXI4 master: read address
-- m_axi_arlen -- AXI4 master: read adress length
-- m_axi_arsize -- AXI4 master: read address size
-- m_axi_arburst -- AXI4 master: read address burst
-- m_axi_arprot -- AXI4 master: read address protection
-- m_axi_arcache -- AXI4 master: read adddress cache
-- m_axi_rready -- AXI4 master: read data ready
-- m_axi_rvalid -- AXI4 master: read data valid
-- m_axi_rdata -- AXI4 master: read data
-- m_axi_rresp -- AXI4 master: read data response
-- m_axi_rlast -- AXI4 master: read data last
-- m_axi_awready -- AXI4 master: write address ready
-- m_axi_awvalid -- AXI4 master: write address valid
-- m_axi_awaddr -- AXI4 master: write address
-- m_axi_awlen -- AXI4 master: write address length
-- m_axi_awsize -- AXI4 master: write address size
-- m_axi_awburst -- AXI4 master: write address burst
-- m_axi_awprot -- AXI4 master: write address protection
-- m_axi_awcache -- AXI4 master: write address cache
-- m_axi_wready -- AXI4 master: write data ready
-- m_axi_wvalid -- AXI4 master: write data valid
-- m_axi_wdata -- AXI4 master: write data
-- m_axi_wstrb -- AXI4 master: write data strobe
-- m_axi_wlast -- AXI4 master: write data last
-- m_axi_bready -- AXI4 master: read response ready
-- m_axi_bvalid -- AXI4 master: read response valid
-- m_axi_bresp -- AXI4 master: read response
------------------------------------------------------------------------------
entity azido_to_axi is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
md_error : out std_logic;
m_axi_arready : in std_logic;
m_axi_arvalid : out std_logic;
m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_rready : out std_logic;
m_axi_rvalid : in std_logic;
m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic;
m_axi_awready : in std_logic;
m_axi_awvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_wready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH)/8 - 1 downto 0);
m_axi_wlast : out std_logic;
m_axi_bready : out std_logic;
m_axi_bvalid : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute MAX_FANOUT of m_axi_aclk : signal is "10000";
attribute MAX_FANOUT of m_axi_aresetn : signal is "10000";
attribute SIGIS of m_axi_aclk : signal is "Clk";
attribute SIGIS of m_axi_aresetn : signal is "Rst";
end entity azido_to_axi;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of azido_to_axi is
component AXI_TO_AZIDO_HWHW_Elements_C_PE1PE1
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
md_error : out std_logic;
m_axi_arready : in std_logic;
m_axi_arvalid : out std_logic;
m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_rready : out std_logic;
m_axi_rvalid : in std_logic;
m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic;
m_axi_awready : in std_logic;
m_axi_awvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_wready : in std_logic;
m_axi_wvalid : out std_logic;
m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH)/8 - 1 downto 0);
m_axi_wlast : out std_logic;
m_axi_bready : out std_logic;
m_axi_bvalid : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0)
);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of AXI_TO_AZIDO_HWHW_Elements_C_PE1PE1 : component is true;
begin
--instance Azido black box
bb_Azido_component : AXI_TO_AZIDO_HWHW_Elements_C_PE1PE1
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID =>S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
m_axi_aclk => m_axi_aclk,
m_axi_aresetn => m_axi_aresetn,
md_error => md_error,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arprot => m_axi_arprot,
m_axi_arcache => m_axi_arcache,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awprot => m_axi_awprot,
m_axi_awcache => m_axi_awcache,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
m_axi_bresp => m_axi_bresp
);
end IMP;
| gpl-3.0 | 8f3826e41b0ba8edaecc5885d84aeb37 | 0.475313 | 3.838538 | false | false | false | false |
simonspa/pixel-dtb-firmware | dtb/ram.vhd | 2 | 6,884 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Arria GX",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=NONE"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense | 4ca2f57cf1f17d6a8bb8625c2296dcb3 | 0.6733 | 3.535696 | false | false | false | false |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part3/lpm_constant0.vhd | 1 | 3,509 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I3",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I3"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I3"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense | 64360505e3233f91acf074a42d5ad92a | 0.646338 | 3.801733 | false | false | false | false |
Subsets and Splits