repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
tgingold/ghdl | testsuite/gna/issue50/vector.d/w_split4.vhd | 2 | 1,359 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split4 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split4;
architecture augh of w_split4 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | b2a7ae05ded7c0a70635787fe2b451a1 | 0.66961 | 2.843096 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd | 4 | 22,544 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : inductor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Inductor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity inductor is
generic (
ind : inductance; -- Nominal inductance
i_ic : real := real'low); -- Initial current (use IF statement below
-- to activate)
port (
terminal p1, p2 : electrical);
end entity inductor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = L * di/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal;
architecture ideal2 of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal2;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_constant.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Constant Voltage Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_constant is
generic (
level : voltage; -- Constant voltage value [Volts]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_constant;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = constant)
-------------------------------------------------------------------------------
architecture ideal of v_constant is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
v == level;
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1);
port (terminal c, p1, p2 : electrical);
end entity sw_LoopCtrl_wa;
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1*i1;
v2 == r2*i2;
end architecture ideal;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity pwl_load_wa is
generic (
load_enable: string := "yes";
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time);
port (terminal p1, p2 : electrical);
end entity pwl_load_wa;
architecture ideal of pwl_load_wa is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
if load_enable = "yes" use
if domain = quiescent_domain or domain = frequency_domain use
v == i*res_init;
else
v == i*res_signal'ramp(1.0e-6, 1.0e-6);
end use;
else
i == 0.0;
end use;
-- purpose: Create Events to change resistance at specified times
-- type : combinational
-- inputs :
-- outputs: res
CreateEvent: process is
begin -- process CreateEvent
wait for t1;
res_signal <= res1;
wait for (t2-t1);
res_signal <= res2;
wait;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity buck_sw is
generic (
Vd : voltage := 0.7; -- Diode Voltage
Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
port (terminal input, output, ref, ctrl: electrical);
end entity buck_sw;
architecture average of buck_sw is
quantity Vout across Iout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin
Vout + Vd == Vctrl * Vin / Vramp; -- Averaged equation
end architecture average;
library IEEE;
library IEEE_proposed;
use ieee.math_real.all;
use IEEE_proposed.electrical_systems.all;
entity comp_2p2z is
generic (
gain : real := 100.0; -- High DC gain for good load regulation
fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
fp2 : real := 531.0e3;-- Pole location to cancel effect of ESR
fz1 : real := 403.0; -- Zero locations to cancel LC filter poles
fz2 : real := 403.0);
port (terminal input, output, ref : electrical);
end entity comp_2p2z;
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi*fp2;
constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi*fz2;
constant num : real_vector := (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
constant den : real_vector := (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
begin
vout == -1.0*gain*vin'ltf(num, den);
end architecture ltf;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS3_BuckConverter_average is
end TB_CS3_BuckConverter_average;
architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
-- Component declarations
-- Signal declarations
terminal vcomp_out : electrical;
terminal vctrl : electrical;
terminal vctrl_init : electrical;
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
terminal vref : electrical;
begin
-- Signal assignments
-- Component instances
L1 : entity work.inductor(ideal)
generic map(
ind => 6.5e-3
)
port map(
p1 => vmid,
p2 => vout
);
C1 : entity work.capacitor(ESR)
generic map(
cap => 6.0e-6,
r_esr => 50.0e-3
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vctrl_1 : entity work.v_constant(ideal)
generic map(
level => 0.327
)
port map(
pos => vctrl_init,
neg => ELECTRICAL_REF
);
Vref_1 : entity work.v_constant(ideal)
generic map(
level => 4.8
)
port map(
pos => vref,
neg => ELECTRICAL_REF
);
sw2 : entity work.sw_LoopCtrl_wa(ideal)
generic map(
sw_state => 1
)
port map(
p2 => vctrl_init,
c => vctrl,
p1 => vcomp_out
);
Electrical_Load6 : entity work.pwl_load_wa(ideal)
generic map(
t2 => 30 ms,
res2 => 5.0,
t1 => 5ms,
res1 => 1.0,
res_init => 2.4,
load_enable => "yes"
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vin_1 : entity work.v_pulse(ideal)
generic map(
initial => 42.0,
pulse => 42.0,
delay => 10ms,
width => 100ms,
period => 1000ms
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
buck_sw2 : entity work.buck_sw(average)
port map(
ctrl => vctrl,
input => vin,
ref => ELECTRICAL_REF,
output => vmid
);
comp_2p2z4 : entity work.comp_2p2z(ltf)
generic map(
fz1 => 403.0,
fz2 => 403.0,
gain => 100.0
)
port map(
input => vout,
output => vcomp_out,
ref => vref
);
end TB_CS3_BuckConverter_average;
--
| gpl-2.0 | 63df33310afac99d9d083b2a42014d19 | 0.57807 | 4.441292 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/ram9.vhdl | 1 | 3,029 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram3 is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diA : in std_logic_vector(WIDTHA-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doA : out std_logic_vector(WIDTHA-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end ram3;
architecture behavioral of ram3 is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE : integer := max(SIZEA,SIZEB);
constant RATIO : integer := maxWIDTH / minWIDTH;
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(to_integer(unsigned(addrA))) := diA;
end if;
readA <= ram(to_integer(unsigned(addrA)));
end if;
regA <= readA;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(to_integer(unsigned(addrB)&"00")) := diB(minWIDTH-1 downto 0);
ram(to_integer(unsigned(addrB)&"01")) := diB(2*minWIDTH-1 downto minWIDTH);
ram(to_integer(unsigned(addrB)&"10")) := diB(3*minWIDTH-1 downto 2*minWIDTH);
ram(to_integer(unsigned(addrB)&"11")) := diB(4*minWIDTH-1 downto 3*minWIDTH);
end if;
readB(minWIDTH-1 downto 0) <= ram(to_integer(unsigned(addrB)&"00"));
readB(2*minWIDTH-1 downto minWIDTH) <= ram(to_integer(unsigned(addrB)&"01"));
readB(3*minWIDTH-1 downto 2*minWIDTH) <= ram(to_integer(unsigned(addrB)&"10"));
readB(4*minWIDTH-1 downto 3*minWIDTH) <= ram(to_integer(unsigned(addrB)&"11"));
end if;
regB <= readB;
end if;
end process;
doA <= regA;
doB <= regB;
end behavioral;
| gpl-2.0 | be2990105bbcb7aec450093ad17d4dbb | 0.585012 | 3.43424 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue794/example.vhdl | 1 | 3,324 | use std.textio.all;
-- Original Source: https://github.com/ricardo-jasinski/vhdl-csv-file-reader/
-- Original Author: Ricardo Jasinski
-- Define operations to read formatted data from a comma-separated-values file
-- (CSV file). To use this package:
-- 1. Create a csv_file_reader: variable csv: csv_file_reader_type;
-- 2. Open a csv file: csv.initialize("c:\file.csv");
-- 3. Read one line at a time: csv.readline;
-- 4. Start reading values: my_integer := csv.read_integer;
-- 5. To read more values in the same line, call any of the read_* functions
-- 6. To move to the next line, call csv.readline() again
package crashExample is
type csv_file_reader_type is protected
-- Open the CSV text file to be used for subsequent read operations
procedure initialize(file_pathname: string);
-- True when the end of the CSV file was reached
impure function end_of_file return boolean;
-- Release (close) the associated CSV file
procedure dispose;
-- Read one line from the csv file, and keep it in the cache
procedure readline;
-- Read a string from the csv file, until a separator character ',' is found
impure function read_string return string;
end protected;
end;
package body crashExample is
type csv_file_reader_type is protected body
file my_csv_file: text;
-- cache one line at a time for read operations
variable current_line: line;
-- true when end of file was reached and there are no more lines to read
variable end_of_file_reached: boolean;
-- Maximum string length for read operations
constant LINE_LENGTH_MAX: integer := 256;
-- Open the CSV text file to be used for subsequent read operations
procedure initialize(file_pathname: string) is begin
file_open(my_csv_file, file_pathname, READ_MODE);
end_of_file_reached := false;
end;
-- True when the end of the CSV file was reached
impure function end_of_file return boolean is begin
return end_of_file_reached;
end;
-- Release (close) the associated CSV file
procedure dispose is begin
file_close(my_csv_file);
end;
-- Read one line from the csv file, and keep it in the cache
procedure readline is begin
readline(my_csv_file, current_line);
end_of_file_reached := endfile(my_csv_file);
end;
-- Read a string from the csv file, until a separator character ',' is found
impure function read_string return string is
variable return_string: string(1 to LINE_LENGTH_MAX);
variable read_char: character;
variable read_ok: boolean := true;
variable index: integer := 1;
begin
read(current_line, read_char, read_ok);
while read_ok loop
if read_char = ',' then
return return_string;
else
return_string(index) := read_char;
index := index + 1;
end if;
read(current_line, read_char, read_ok);
end loop;
end;
end protected body;
end;
| gpl-2.0 | 1f7d2c78ff8be8fc23fea0a34b4f4828 | 0.608303 | 4.328125 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem2d01/tb_dpram2r.vhdl | 1 | 1,369 | entity tb_dpram2r is
end tb_dpram2r;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram2r is
signal raddr : natural range 0 to 3;
signal rnib : natural range 0 to 1;
signal rdat : std_logic_vector (3 downto 0);
signal waddr : natural range 0 to 3;
signal wdat : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
dut: entity work.dpram2r
port map (raddr => raddr, rnib => rnib, rdat => rdat,
waddr => waddr, wdat => wdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
raddr <= 0;
rnib <= 0;
waddr <= 1;
wdat <= x"e1";
pulse;
raddr <= 1;
rnib <= 0;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = x"1" severity failure;
raddr <= 1;
rnib <= 1;
waddr <= 2;
wdat <= x"d2";
pulse;
assert rdat = x"e" severity failure;
raddr <= 2;
rnib <= 1;
waddr <= 3;
wdat <= x"c3";
pulse;
assert rdat = x"d" severity failure;
raddr <= 3;
rnib <= 0;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = x"3" severity failure;
raddr <= 3;
rnib <= 1;
waddr <= 0;
wdat <= x"f0";
pulse;
assert rdat = x"c" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 3dfafe0cc9d0a463cdcf61913f469e58 | 0.536888 | 3.3309 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue332/repro_rec2.vhdl | 1 | 445 | entity repro_rec is
end;
architecture behav of repro_rec is
type my_rec is record
s : natural;
b : bit_vector;
end record;
signal r : my_rec (b (1 to 3));
signal a : bit_vector (0 to 1);
begin
process
begin
r.s <= 1;
r.b <= "010";
wait for 1 ns;
r.b <= "101";
wait;
end process;
blk: block
port (r1: my_rec; a1 : bit_vector);
port map (r1 => r, a1 => a);
begin
end block;
end;
| gpl-2.0 | af69b3a298b6de05116014c47de648e2 | 0.54382 | 2.88961 | false | false | false | false |
nickg/nvc | test/regress/file3.vhd | 1 | 848 | entity file3 is
end entity;
architecture a of file3 is
begin
main : process
constant file_name : string := "output.raw";
type binary_file is file of character;
file fptr : binary_file;
variable fstatus : file_open_status;
variable tmp, tmp2 : character;
begin
assert character'pos(character'low) = 0;
assert character'pos(character'high) = 255;
file_open(fstatus, fptr, file_name, write_mode);
assert fstatus = open_ok;
for i in 0 to 255 loop
write(fptr, character'val(i));
end loop;
file_close(fptr);
file_open(fstatus, fptr, file_name, read_mode);
assert fstatus = open_ok;
for i in 0 to 255 loop
read(fptr, tmp);
assert character'pos(tmp) = i;
end loop;
assert endfile(fptr);
file_close(fptr);
report "Success";
wait;
end process;
end;
| gpl-3.0 | bd238622f47deb12586af8d581f9856c | 0.643868 | 3.504132 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/func03.vhdl | 1 | 499 | library ieee;
use ieee.std_logic_1164.all;
entity func03 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end func03;
architecture behav of func03 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (len - 1 downto 0);
begin
res := (0 => '1', others => '0');
return res;
end gen_mask;
constant mask : std_logic_vector(7 downto 0) := gen_mask (8);
begin
b <= a and mask;
end behav;
| gpl-2.0 | a135cab30919e49ab2b8f4ea167c0fbb | 0.639279 | 3.178344 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd | 4 | 1,429 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_16 is
end entity inline_16;
----------------------------------------------------------------
architecture test of inline_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 271aa05b31c5ea2ee5949a5acfffdaab | 0.63261 | 4.178363 | false | false | false | false |
nickg/nvc | test/simp/ffold.vhd | 1 | 8,335 | package pack is
function add4(x : in integer) return integer;
function add1(x : in integer) return integer;
function log2(x : in integer) return integer;
function case1(x : in integer) return integer;
function adddef(x, y : in integer := 5) return integer;
function chain1(x : string) return boolean;
function chain2(x, y : string) return boolean;
function flip(x : bit_vector(3 downto 0)) return bit_vector;
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real;
function get_bitvec(x, y : integer) return bit_vector;
function approx(x, y : real; t : real := 0.001) return boolean;
function get_string(x : integer) return string;
function get_string(x : real) return string;
function get_string(x : character) return string;
function get_string(x : time) return string;
function needs_heap(x : integer) return integer;
function sum_left_right(x : bit_vector) return integer;
procedure p5(x : in integer; y : out integer);
function call_proc(x : in integer) return integer;
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec;
function min(x, y : integer) return integer;
function get_left(x : bit_vector) return bit;
function test_alloc_proc(a, b, c : string) return boolean;
function test_logic(x, y : bit) return bit;
function test_div(x, y : integer) return integer;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
function flip(x : bit_vector(3 downto 0)) return bit_vector is
variable r : bit_vector(3 downto 0);
begin
r(0) := x(3);
r(1) := x(2);
r(2) := x(1);
r(3) := x(0);
return r;
end function;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
end function;
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
function get_string(x : integer) return string is
begin
return integer'image(x);
end function;
function get_string(x : real) return string is
begin
return real'image(x);
end function;
function get_string(x : character) return string is
begin
return character'image(x);
end function;
function get_string(x : time) return string is
begin
return time'image(x);
end function;
function needs_heap(x : integer) return integer is
begin
if integer'image(x)'length = 2 then
return x * 2;
else
return x / 2;
end if;
end function;
function sum_left_right(x : bit_vector) return integer is
begin
return x'left + x'right;
end function;
procedure p5(x : in integer; y : out integer) is
variable k : integer := x + 1;
begin
y := k;
end procedure;
function call_proc(x : in integer) return integer is
variable y : integer;
begin
p5(x, y);
return y;
end function;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
function min(x, y : integer) return integer is
begin
if x > y then
return y;
else
return x;
end if;
end function;
function get_left(x : bit_vector) return bit is
constant l : integer := x'left;
variable v : bit_vector(1 to x'right);
constant m : integer := min(x'length, v'length) + 1;
begin
return x(l);
end function;
type line is access string;
procedure cat_str(x : inout line; s : in string) is
variable tmp : line := x;
variable len : integer := 0;
begin
if x /= null then
len := x.all'length;
end if;
x := new string(1 to s'length + len);
if tmp /= null then
x.all(1 to len) := tmp.all;
end if;
x.all(1 + len to s'length + len) := s;
if tmp /= null then
deallocate(tmp);
end if;
end procedure;
function test_alloc_proc(a, b, c : string) return boolean is
variable l : line;
variable r : boolean;
begin
cat_str(l, a);
cat_str(l, b);
r := l.all = c;
deallocate(l);
return r;
end function;
function test_logic(x, y : bit) return bit is
begin
return (x and y) xor (x or y) xor (x nand y)
xor (x nor y) xor (x xnor y);
end function;
function test_div(x, y : integer) return integer is
begin
return x / y; -- Need to evaluate zero check
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
begin
b1: block is
signal s0 : integer := add1(5);
signal s1 : integer := add4(1);
signal s2 : integer := log2(11);
signal s3 : integer := log2(integer(real'(5.5)));
signal s4 : integer := case1(1);
signal s5 : integer := case1(7);
signal s6 : integer := adddef;
signal s7 : boolean := chain2("foo", "hello");
signal s8 : boolean := flip("1010") = "0101";
signal s9 : boolean := flip("1010") = "0111";
signal s10 : real := lookup(0); -- 0.62;
signal s11 : real := lookup(2); -- 71.7;
signal s12 : boolean := get_bitvec(1, 2) = "00";
signal s13 : boolean := approx(1.0000, 1.0001);
signal s14 : boolean := approx(1.0000, 1.01);
signal s15 : boolean := get_string(5) = "5";
signal s16 : boolean := get_string(2.5) = "2.5";
signal s17 : boolean := get_string('F') = "'F'";
signal s18 : boolean := get_string(1 fs) = "1 fs";
signal s19 : integer := needs_heap(40);
signal s20 : integer := sum_left_right("101010");
signal s21 : integer := call_proc(1);
signal s22 : boolean := make_rec("010", 20).y = 20;
signal s23 : boolean := get_left("1010") = '1';
signal s24 : boolean := make_rec("010", 4).x = "010";
signal s25 : boolean := test_alloc_proc("hello", "world", "helloworld");
signal s26 : boolean := test_alloc_proc("hello", "moo", "hellomoowee");
signal s27 : bit := test_logic('1', '0');
signal s28 : integer := test_div(5, 2);
begin
end block;
end architecture;
| gpl-3.0 | e764237f882b8ee6c36ab3bde89724f9 | 0.545291 | 3.727639 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd | 4 | 2,033 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_lpf_dot_ltf_ztf is
end tb_lpf_dot_ltf_ztf;
architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
RC1 : entity work.lowpass(RC)
port map(
input => in_src,
output => out_RC
);
dot1 : entity work.lowpass(dot)
port map(
input => in_src,
output => out_dot
);
ltf1 : entity work.lowpass(ltf)
port map(
input => in_src,
output => out_ltf
);
ztf1 : entity work.lowpass(ztf)
port map(
input => in_src,
output => out_ztf1
);
ztf4 : entity work.lowpass(z_minus_1)
port map(
input => in_src,
output => out_ztf4
);
end TB_lpf_dot_ltf_ztf;
| gpl-2.0 | 827a47b8d89d80e750b8d6a12d33ea24 | 0.629611 | 3.696364 | false | false | false | false |
nickg/nvc | test/eopt/map1.vhd | 1 | 843 | entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity map1 is
end entity;
architecture test of map1 is
signal a : bit_vector(1 downto 0);
signal b : bit_vector(5 downto 0);
signal c : bit_vector(5 downto 2);
signal d : bit_vector(3 downto 0);
begin
sub1_i: entity work.sub
port map (
i(1 downto 0) => a,
i(7 downto 2) => b,
o(3 downto 0) => c,
o(7 downto 4) => d );
sub2_i: entity work.sub
port map (
i(1 downto 0) => a,
i(7 downto 2) => "000000",
o => open );
end architecture;
| gpl-3.0 | 92bb73b55a9790ac6444c69694ee8dd2 | 0.476868 | 3.665217 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1100/tb_repro.vhdl | 1 | 727 | entity tb_repro is
end tb_repro;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro is
signal val : std_logic_vector (63 downto 0);
signal iperm : std_logic_vector (3*8 - 1 downto 0) := (others => '0');
signal en : std_ulogic;
signal res : std_logic_vector (63 downto 0);
begin
dut: entity work.repro
port map (val, iperm, en, res);
process
begin
val <= x"01_23_45_67_89_ab_cd_ef";
en <= '1';
iperm <= o"76543210";
wait for 1 ns;
assert res = x"01_23_45_67_89_ab_cd_ef"severity failure;
iperm <= o"01234567";
wait for 1 ns;
assert res = x"ef_cd_ab_89_67_45_23_01"
report to_hstring(res) severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1cbb136727fcd8c5c3e1e91c540e6902 | 0.628611 | 2.873518 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem01/tb_sram05.vhdl | 1 | 1,663 | entity tb_sram05 is
end tb_sram05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram05 is
signal rst : std_logic;
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram05
port map (rst => rst, clk_i => clk,
addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '0';
-- [0] := x03
addr <= "0000";
wdat <= x"03";
wen <= '1';
pulse;
assert rdat = x"03" severity failure;
-- [0] := x41
wdat <= x"41";
pulse;
assert rdat = x"41" severity failure;
-- [4] := x07
addr <= "0100";
wdat <= x"07";
wait for 1 ns;
pulse;
assert rdat = x"07" severity failure;
-- Not en.
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"41" severity failure;
-- [4] := x23
wen <= '1';
addr <= "0100";
wdat <= x"23";
wait for 1 ns;
pulse;
assert rdat = x"23" severity failure;
-- Reset
rst <= '1';
addr <= "0100";
wdat <= x"ff";
wait for 1 ns;
pulse;
assert rdat = x"23" severity failure;
-- None
rst <= '0';
wen <= '0';
addr <= "0000";
wdat <= x"c5";
pulse;
assert rdat = x"41" severity failure;
-- None
addr <= "0100";
pulse;
assert rdat = x"23" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 0ced13d49493b865b87d8f84b1d84af0 | 0.516536 | 3.216634 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | RCA/32bits/RCA/Reg32Bit.vhd | 4 | 566 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg32Bit is
port(
valIn: in std_logic_vector(31 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(31 downto 0)
);
end Reg32Bit;
architecture strc_Reg32Bit of Reg32Bit is
signal Temp: std_logic_vector(31 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "00000000000000000000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg32Bit; | mit | c9e2114d8e5bb340219b592a679a0e37 | 0.696113 | 2.902564 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/float_generic_pkg.vhdl | 2 | 51,264 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Floating-point package (Generic package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.fixed_float_types.all;
package float_generic_pkg is
generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
float_exponent_width : NATURAL := 8;
float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (<>) );
-- Author David Bishop ([email protected])
constant CopyRightNotice : STRING :=
"Copyright IEEE P1076 WG. Licensed Apache 2.0";
use fixed_pkg.all;
-- Note that this is "INTEGER range <>", thus if you use a literal, then the
-- default range will be (INTEGER'low to INTEGER'low + X)
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
alias U_float is UNRESOLVED_float;
subtype float is (resolved) UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNRESOLVED_UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : UNRESOLVED_SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNRESOLVED_SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_UNSIGNED;
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNRESOLVED_ufixed; -- a number between 1.0 and 2.0
expon : out UNRESOLVED_SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_UNSIGNED; -- fraction, unnormalized
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNRESOLVED_UNSIGNED; -- unsigned
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNRESOLVED_ufixed; -- unsigned fixed point
expon : UNRESOLVED_SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "?=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function "?=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function "?=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?/=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?>=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?<=" (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function "?=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?/=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?>=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function "?<=" (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function "and" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nand" (l : UNRESOLVED_float) return STD_ULOGIC;
function "or" (l : UNRESOLVED_float) return STD_ULOGIC;
function "nor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xor" (l : UNRESOLVED_float) return STD_ULOGIC;
function "xnor" (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : UNRESOLVED_SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return UNRESOLVED_SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_float];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_float, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_float];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_float, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_float];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_float return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_float return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is to_hstring [UNRESOLVED_float return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is to_ostring [UNRESOLVED_float return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
end package float_generic_pkg;
| gpl-2.0 | 8c348e41fa39f2a9f4e21bfbe45eacff | 0.627048 | 4.404502 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec07.vhdl | 1 | 489 | entity tb_rec07 is
end tb_rec07;
library ieee;
use ieee.std_logic_1164.all;
use work.rec07_pkg.all;
architecture behav of tb_rec07 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec07
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a => "0001", b => '0') severity failure;
inp <= '0';
wait for 1 ns;
assert r = (a => "1000", b => '1') severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 3732e66aeb143660b138c1dc4ff6ed5d | 0.595092 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd | 4 | 1,942 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_analog_switch is
end tb_analog_switch;
architecture TB_analog_switch of tb_analog_switch is
-- Component declarations
-- Signal declarations
terminal in_ana_src : electrical;
terminal in_switch : electrical;
signal clock_out : std_logic;
begin
-- Signal assignments
-- Component instances
vdc1 : entity work.v_constant(ideal)
generic map(
level => 1.0
)
port map(
pos => in_ana_src,
neg => ELECTRICAL_REF
);
Clk1 : entity work.clock(ideal)
generic map(
period => 10.0ms
)
port map(
clk_out => clock_out
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_ana_src,
p2 => in_switch
);
swtch : entity work.analog_switch(ideal)
port map(
n1 => in_switch,
n2 => ELECTRICAL_REF,
control => clock_out
);
end TB_analog_switch;
| gpl-2.0 | 5aa775582f6d2b91add201ec75d06580 | 0.630278 | 4.045833 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/huffbuff.vhd | 2 | 1,453 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huffbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(7 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(7 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huffbuff;
architecture augh of huffbuff is
-- Embedded RAM
type ram_type is array (0 to 191) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 192 else (others => '-');
end architecture;
| gpl-2.0 | 0f9a8cfa4be27222684d85037f91d514 | 0.671714 | 2.917671 | false | false | false | false |
nickg/nvc | test/regress/record34.vhd | 1 | 648 | entity record34 is
end entity;
architecture test of record34 is
type rec is record
x : bit_vector;
y : natural;
end record;
type rec_array is array (natural range <>) of rec;
type wrapper is record
f : rec_array(1 to 3)(x(1 to 2));
end record;
signal s : wrapper;
begin
p1: process is
begin
s.f(1) <= (x => "10", y => 1);
wait for 1 ns;
assert s.f = (1 => ("10", 1), 2 to 3 => ("00", 0));
s.f(2).x(1) <= '1';
wait for 1 ns;
assert s.f = (1 => ("10", 1), 2 => ("10", 0), 3 => ("00", 0));
wait;
end process;
end architecture;
| gpl-3.0 | 61d8218f8839385448c1fa29b5fb4666 | 0.484568 | 3.207921 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_afifo_autord.vhd | 3 | 17,241 | -------------------------------------------------------------------------------
-- axi_datamover_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_datamover_afifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 16;
-- Sets the depth of the FIFO
C_CNT_WIDTH : Integer := 5;
-- Sets the width of the FIFO Data Count output
C_USE_BLKMEM : Integer := 1 ;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs --------------------------------------------------------------
AFIFO_Ainit : In std_logic; --
AFIFO_Ainit_Rd_clk : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
----------------------------------------------------------------------------
-- FIFO Outputs --------------------------------------------------------------
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
-----------------------------------------------------------------------------
);
end entity axi_datamover_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant MTBF_STAGES : integer := 4;
constant C_FIFO_MTBF : integer := 4;
-- Constant declarations
-- none
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : natural := 0;
signal rd_count_int_corr : natural := 0;
signal rd_count_int_corr_minus1 : natural := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
signal AFIFO_Ainit_d2_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
AFIFO_Empty <= corrected_empty;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
C_ALLOW_2N_DEPTH => 1 ,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_EN_SAFETY_CKT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF,
C_USE_EMBEDDED_REG => 0 -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
-- ored_ack_ff_reset <= fifo_read_enable or
-- AFIFO_Ainit_Rd_clk or
-- AFIFO_Clr_Rd_Data_Valid;
--
-- sig_rddata_valid <= hold_ff_q or
-- sig_wrfifo_rdack;
--
ored_ack_ff_reset <= '1'
when (fifo_read_enable = '1' or
AFIFO_Ainit_Rd_clk = '1' or
AFIFO_Clr_Rd_Data_Valid = '1')
Else '0';
sig_rddata_valid <= '1'
when (hold_ff_q = '1' or
sig_wrfifo_rdack = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
--IMP_SYNC_FLOP : entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_VECTOR_WIDTH => 32,
-- C_MTBF_STAGES => MTBF_STAGES
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => AFIFO_Ainit,
-- prmry_vect_in => (others => '0'),
-- scndry_aclk => AFIFO_Rd_clk,
-- scndry_resetn => '0',
-- scndry_out => AFIFO_Ainit_d2,
-- scndry_vect_out => open
-- );
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d2_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d2_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty ,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 | 08c997d1adff32c2b2d2ca5b28d817f7 | 0.439592 | 4.475857 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_spi/adc16dx370_ctrl.vhd | 1 | 17,578 | -------------------------------------------------------------------------------------
-- FILE NAME : fmc408_lmk04828_ctrl.vhd
--
-- AUTHOR : Fearghal Rudden
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc408_lmk04828_ctrl
-- architecture - fmc408_lmk04828_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- 1-bit R/W, 2-bit multi-byte field (W1, W0), 13-bit address field (A12-A0), 8-bit data
-- Clocked in MSB first (R/W), and LSB (D0) last
-- Serial data is clocked in on the rising edge of SCK
-- fmc408_lmk04828_ctrl
-- Notes: fmc408_lmk04828_ctrl
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
-- Library declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity adc16dx370_ctrl is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";--x"0005400";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"--x"00073FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
-- Spi interface
trig_n_cs : out std_logic;
trig_sclk : out std_logic;
trig_sdo : out std_logic;
trig_clksel0 : in std_logic;
debug : out std_logic_vector(63 downto 0)
);
end adc16dx370_ctrl;
architecture Behavioural of adc16dx370_ctrl is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0001FFF";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0001FFF";
attribute keep : string;
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
type sh_states is (idle, instruct, data_wait, data_io, data_valid, update, update_instruct, update_data_io);
signal sh_state : sh_states;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal sclk_prebuf : std_logic;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal trig_sdi : std_logic;
signal trig_sdi_in : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(12 downto 0); --IMPORTANT
signal data_reg : std_logic_vector(7 downto 0); -- IMPORTANT
signal shifting : std_logic;
signal shift_reg : std_logic_vector(23 downto 0); -- IMPORTANT
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_write_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal ncs_trig : std_logic;
--signal ncs_int_w : std_logic;
signal busy : std_logic;
signal out_mailbox_data_sig : std_logic_vector(31 downto 0);
-- debug
--signal out_cmd_t : std_logic_vector(63 downto 0);
-- signal probe0 : std_logic_vector(127 downto 0);
-- attribute keep of shift_reg : signal is "true";
--attribute keep of inst_val : signal is "true";
--attribute keep of data_read : signal is "true";
--attribute keep of data_read_val : signal is "true";
--*****************************************************************************************************
begin
--*****************************************************************************************************
--ila_inst0: entity work.ila_0
--PORT MAP (
-- clk => clk_cmd,
-- probe0 => probe0
--);
--
--
--probe0(23 downto 0) <= shift_reg(23 downto 0);
--probe0(24) <= inst_val;
--probe0(64 downto 25) <= (others=>'0');
--probe0(72 downto 65) <= data_read;
--probe0(73) <= data_read_val;
--probe0(127 downto 74) <= (others=>'0');
debug(23 downto 0) <= shift_reg(23 downto 0);
debug(24) <= inst_val;
debug(32 downto 25) <= data_read(7 downto 0);
debug(33) <= data_read_val;
debug(63 downto 34) <= (others=>'0');
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 25MHz)
----------------------------------------------------------------------------------------------------
--process (clk)
-- -- Divide by 2^4 = 16, CLKmax = 16 x 25MHz = 400MHz
-- variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
--begin
-- if (rising_edge(clk)) then
-- clk_div := clk_div + '1';
-- -- The slave samples the data on the rising edge of SCLK.
-- -- therefore we make sure the external clock is slightly
-- -- after the internal clock.
-- sclk_ext <= clk_div(clk_div'length-1);
-- sclk_prebuf <= sclk_ext;
-- end if;
--end process;
--bufg_sclk : bufg
--port map (
-- i => sclk_prebuf,
-- o => serial_clk
--);
serial_clk <= clk;
sclk_ext <= serial_clk;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc408_stellar_cmd_inst : entity work.fmc408_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd, --LM clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_out_reg => out_mailbox_data_sig,
mbx_out_val => open,
mbx_in_reg => (others=>'0'),
mbx_in_val => '0'
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd) --LM clk
begin
if (rst = '1') then
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
--data_read <= (others=> '0');
elsif (rising_edge(clk_cmd)) then -- LM clk
if (in_reg_addr <= ADDR_MAX_RD) then --(in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
-- read from serial if when address is within device range
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(12 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within LMK04828 range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(12 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
sh_state <= idle;
sh_counter <= 0;
read_n_write <= '0';
--ncs_int_r <= '1';
--ncs_int_w <= '1';
ncs_int <= '1';
shifting <= '0';
elsif (rising_edge(serial_clk)) then
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1') then
shifting <= '1';
read_n_write <= inst_rw; -- 0 = write, 1 = read
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid; -- read
else
sh_state <= data_wait; -- write
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid => -- read
sh_state <= idle;
when data_wait => -- write
sh_state <= idle;
-- when update =>
-- shifting <= '0';
-- ncs_int_r <= '1';
-- sh_state <= data_valid;
-- when update_instruct =>
-- if (sh_counter = 0) then
-- sh_counter <= 32;
-- sh_state <= update_data_io;
-- else
-- sh_counter <= sh_counter - 1;
-- end if;
-- when update_data_io =>
-- if (sh_counter = 0) then
-- sh_counter <= shift_reg'length-32-1; --total length minus one data reg
-- ncs_int <= '1';
-- sh_state <= idle;
-- else
-- sh_counter <= sh_counter - 1;
-- end if;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle) else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (inst_reg_val = '1' and read_n_write = '0') then -- write
shift_reg <= inst_rw & "00" & inst_reg & data_reg;
elsif (inst_reg_val = '1' and read_n_write = '1') then -- read
shift_reg <= inst_rw & "00" & inst_reg & data_reg;
end if;
if (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length-2 downto 0) & trig_sdi_in;
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk_cmd, -- LM clk
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk_cmd, --LM clk
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
trig_sdi_in <= trig_clksel0;
end if;
end process;
--------------------------------------------------------------------------------
-- Outputs
--------------------------------------------------------------------------------
--spi_io_t <= '1' when (sh_state = data_io and read_n_write = '1') else '0'; -- 0 = output, 1 = input
trig_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);--shift_reg(shift_reg'length - 1) when ncs_int = '0' else 'Z';
trig_n_cs <= ncs_int;
trig_sclk <= not sclk_ext when ncs_int = '0' else '0';
-- ncs_trig <= ncs_int when read_n_write = '0' else ncs_int_w;
--------------------------------------------------------------------------------
-- Output buffer
--------------------------------------------------------------------------------
--iobuf_trig : iobuf
--port map (
-- I => data_write_val,
-- O => trig_sdi,
-- IO => trig_sdo,
-- T => ncs_trig
--);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end Behavioural;
| mit | d220827d6ac39b1914315058f10392d1 | 0.423996 | 4.192225 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd | 3 | 41,585 | ----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
Use axi_datamover_v5_1_10.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
| gpl-3.0 | 88b3478669a50d69e160696740ba38ae | 0.394541 | 4.970715 | false | false | false | false |
nickg/nvc | test/regress/attr4.vhd | 5 | 397 | entity attr4 is
end entity;
architecture test of attr4 is
begin
process is
variable b : boolean;
begin
assert boolean'pos(false) = 0;
assert boolean'pos(true) = 1;
b := true;
wait for 1 ns;
assert boolean'pos(b) = 1;
assert boolean'val(0) = false;
assert bit'val(1) = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 949188614a35a52de71e33aa2059fb59 | 0.561713 | 3.642202 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispin01/tb_rec06.vhdl | 1 | 707 | entity tb_rec06 is
end tb_rec06;
library ieee;
use ieee.std_logic_1164.all;
use work.rec06_pkg.all;
architecture behav of tb_rec06 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec06
port map (inp => inp, o => r);
process
begin
inp.a <= (2, "0000");
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= (2, "0110");
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= (3, "1001");
inp.b <= '0';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= (3, "0001");
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | ef90ac86092d163ac8018a811f79c2cc | 0.55587 | 2.909465 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue810/nullrng.vhdl | 1 | 309 | package nullrng is
type my_time is range -integer'low to integer'high units
fs; ps= 1000 fs; ns= 1000 ps; us= 1000 ns; -- very short
ms= 1000 us; sec= 1000 ms; min= 60 sec; hr= 60 min; -- longer
end units;
type my_empty_range is range -(-8) to 7;
type my_small_range is range -8 to 7;
end;
| gpl-2.0 | defb13aa60cbe73e49c34bd07b7e461e | 0.644013 | 2.971154 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue886/ent.vhdl | 1 | 2,897 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pong_pkg is
subtype short is signed(16 downto 0);
type direction is (UP, DOWN, NONE);
type dimension is record
w : short;
h : short;
end record;
constant SCREEN_SIZE : dimension := ( w => to_signed(640, short'length),
h => to_signed(480, short'length) );
type location is record
r : short;
c : short;
end record;
type paddle is record
loc : location;
dir : direction;
end record;
component paddle_mover is
generic(
paddle_size : dimension;
screen_size : dimension;
reset_loc : location
);
port(
clk : in std_logic;
en : in std_logic;
rst : in std_logic;
dir : in direction;
q : in paddle;
d : out paddle
);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pong_pkg.all;
entity paddle_mover is
generic(
paddle_size : dimension := (w => to_signed(1, short'length), h => to_signed(1 short'length));
screen_size : dimension := (w => to_signed(1, short'length), h => to_signed(1 short'length));
reset_loc : location := (r => to_signed(1, short'length), c => to_signed(1 short'length))
);
port(
clk : in std_logic;
en : in std_logic;
rst : in std_logic;
dir : in direction;
q : in paddle;
d : out paddle
);
end entity;
architecture beh of paddle_mover is
constant velocity : short := to_signed(1, short'length);
signal next_candidate :paddle := (dir => NONE, loc => (others => 1));
signal next_paddle : paddle := (dir => NONE, loc => (others => 1));
signal next_moves : std_logic := '0';
signal off_bottom : std_logic := '0';
signal off_top : std_logic := '0';
begin
next_candidate.dir <= q.dir;
next_candidate.loc.c <= q.loc.c;
next_candidate.loc.r <= q.loc.r + velocity when dir = DOWN else
q.loc.r - velocity when dir = UP else
q.loc.r;
off_bottom <= (next_candidate.loc.r + paddle_size.h) >= screen_size.h;
off_top <= next_candidate.loc.r <= to_unsigned(0, short'length);
next_moves <= off_bottom nor off_top;
next_paddle.dir <= next_candidate.dir;
next_paddle.loc.c <= next_candidate.loc.c;
next_paddle.loc.r <= next_candidate.loc.r when next_moves = '1' else q.loc.r;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
d.loc <= reset_loc;
elsif en = '1' then
d <= next_paddle;
end if;
end if;
end process;
end architecture;
| gpl-2.0 | 4533171922d4f6d6e5addc71612c6418 | 0.538833 | 3.572133 | false | false | false | false |
nickg/nvc | test/sem/static.vhd | 1 | 2,614 | entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
sub2_i: entity work.sub
generic map ( N => N )
port map (
x(N downto 0) => x ); -- Error
process is
type rec is record
f1, f2 : integer;
end record;
subtype rs is rec; -- OK
constant rc : rs := (0, 0); -- OK
constant i : integer := rc.f1; -- OK
begin
end process;
p1: process is
constant t : time := -5 ns; -- OK, globally static
begin
end process;
p2: process is
constant n : integer := bad_func(2); -- Error
subtype t is integer range 0 to n - 1; -- Crash in sem_locally_static
begin
end process;
end architecture;
| gpl-3.0 | 738d7aeb3861cbbeda017a7f6dea5099 | 0.439939 | 4.327815 | false | false | false | false |
nickg/nvc | test/regress/assign7.vhd | 1 | 543 | entity assign7 is
end entity;
architecture test of assign7 is
begin
main: process is
variable x : integer_vector(4 downto 0);
variable y : integer_vector(1 downto 0);
variable z : integer_vector(2 downto 0);
variable i0, i1 : integer;
begin
x := (1, 2, 3, 4, 5);
(y, z) := x;
assert y = (1, 2);
assert z = (3, 4, 5);
(i0, z, i1) := x;
assert i0 = 1;
assert z = (2, 3, 4);
assert i1 = 5;
wait;
end process;
end architecture;
| gpl-3.0 | 8f2a7a980d2c4a56523e62bf508bb510 | 0.504604 | 3.290909 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ILC/ghrd_10as066n2_ILC_inst.vhd | 1 | 1,317 | component ghrd_10as066n2_ILC is
port (
avmm_addr : in std_logic_vector(5 downto 0) := (others => 'X'); -- address
avmm_wrdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avmm_write : in std_logic := 'X'; -- write
avmm_read : in std_logic := 'X'; -- read
avmm_rddata : out std_logic_vector(31 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
irq : in std_logic_vector(1 downto 0) := (others => 'X'); -- irq
reset_n : in std_logic := 'X' -- reset_n
);
end component ghrd_10as066n2_ILC;
u0 : component ghrd_10as066n2_ILC
port map (
avmm_addr => CONNECTED_TO_avmm_addr, -- avalon_slave.address
avmm_wrdata => CONNECTED_TO_avmm_wrdata, -- .writedata
avmm_write => CONNECTED_TO_avmm_write, -- .write
avmm_read => CONNECTED_TO_avmm_read, -- .read
avmm_rddata => CONNECTED_TO_avmm_rddata, -- .readdata
clk => CONNECTED_TO_clk, -- clk.clk
irq => CONNECTED_TO_irq, -- irq.irq
reset_n => CONNECTED_TO_reset_n -- reset_n.reset_n
);
| mit | c827783276768890efd1bdf1f6b09586 | 0.477601 | 3.325758 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl | 4 | 821 | entity forty_two is
port (
int_out : out integer);
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
int_out <= 42;
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two
port (
int_out : out integer);
end component;
for ft0 : forty_two
use entity work.forty_two(only)
port map ( int_out => int_out );
signal int_signal : integer;
begin -- only
ft0 : component forty_two
port map (
int_out => int_signal );
test: process
begin -- process test
wait for 1 ms;
assert int_signal = 42 report "TEST FAILED" severity ERROR;
assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
| gpl-2.0 | feeb5f02a3befcf24c6879fed3d98a46 | 0.640682 | 3.523605 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd | 4 | 6,565 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1361.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01361ent IS
END c08s05b00x00p03n01i01361ent;
ARCHITECTURE c08s05b00x00p03n01i01361arch OF c08s05b00x00p03n01i01361ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01361"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01361 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01361arch;
| gpl-2.0 | 313cd78f5893136628e89b6eaacabaeb | 0.583549 | 2.942627 | false | false | false | false |
nickg/nvc | test/regress/stdenv1.vhd | 1 | 1,098 | entity stdenv1 is
end entity;
use std.env.all;
use std.textio.all;
architecture test of stdenv1 is
begin
p1: process is -- GETENV
variable l : line;
begin
report getenv("PATH");
report getenv("HOME");
assert getenv("FOO") = "123";
l := getenv("FOO");
assert l.all = "123";
wait;
end process;
p2: process is -- VHDL_VERSION, etc.
begin
assert vhdl_version = "2019";
assert tool_type = "SIMULATION";
report tool_version;
wait;
end process;
p3: process is -- EPOCH, time functions
variable tr : time_record;
begin
report "time: " & to_string(epoch);
assert epoch > 1660068924.0; -- 9th August 2022
assert epoch < 4294967396.0; -- 19th January 2038
tr := localtime;
report to_string(tr);
assert tr.year >= 2022;
tr := gmtime;
report to_string(tr, 3);
assert tr.year >= 2022;
wait;
end process;
end architecture;
| gpl-3.0 | 56f8e5cbc470974835c7af5a84512290 | 0.521858 | 3.935484 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd | 4 | 3,363 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture std_cell of inline_08 is
attribute cell_name : string;
attribute pin_number : positive;
attribute max_wire_delay : delay_length;
attribute encoding : bit_vector;
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
type built_in_type is (bv_incr, std_incr);
attribute built_in : built_in_type;
signal enable, clk : bit;
type state_type is (idle_state, other_state);
type speed_range is (high, other_speed);
type coolant_level is (high, other_level);
attribute representation : string;
function increment ( vector : in bit_vector ) return bit_vector is
begin
end;
function increment ( vector : in std_logic_vector ) return std_logic_vector is
begin
end;
attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
attribute pin_number of enable : signal is 14;
attribute max_wire_delay of clk : signal is 50 ps;
attribute encoding of idle_state : literal is b"0000";
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
attribute built_in of
increment [ bit_vector return bit_vector ] : function is bv_incr;
attribute built_in of
increment [ std_logic_vector return std_logic_vector ] : function is std_incr;
attribute representation of high [ return speed_range ] : literal is "byte";
attribute representation of high [ return coolant_level ] : literal is "word";
begin
the_fpu : block is
begin
end block the_fpu;
process is
variable v1 : string(1 to 11);
variable v2 : positive;
variable v3 : time;
variable v4 : bit_vector(0 to 3);
variable v5 : coordinate;
variable v6, v7 : built_in_type;
variable v8, v9 : string(1 to 4);
begin
-- code from book included...
v1 := std_cell'cell_name ;
v2 := enable'pin_number ;
v3 := clk'max_wire_delay ;
v4 := idle_state'encoding ;
v5 := the_fpu'cell_position ;
v6 := increment [ bit_vector return bit_vector ] 'built_in ;
v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ;
v8 := high [ return speed_range ] 'representation ;
v9 := high [ return coolant_level ] 'representation ;
-- end code from book
wait;
end process;
end architecture std_cell;
| gpl-2.0 | 480b1e9d36e73244a0257f8cb4df4f68 | 0.677074 | 3.812925 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_rddata_cntl.vhd | 7 | 79,652 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_rdmux;
-------------------------------------------------------------------------------
entity axi_sg_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_sg_rddata_cntl;
architecture implementation of axi_sg_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
-- coverage off
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal mm2s_rlast_del : std_logic;
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
-- mm2s_rready <= '1'; --sig_data2mmap_ready;
-- Read Status Block interface
data2rsc_valid <= mm2s_rlast_del; --sig_coelsc_reg_full ;
data2rsc_cmd_cmplt <= mm2s_rlast_del;
-- data2rsc_valid <= sig_coelsc_reg_full ;
mm2s_strm_wvalid <= mm2s_rvalid;-- and sig_data2mmap_ready;
mm2s_strm_wlast <= mm2s_rlast; -- and sig_data2mmap_ready;
mm2s_strm_wstrb <= (others => '1');
mm2s_strm_wdata <= mm2s_rdata;
-- Adding a register for rready as OVC error out during reset
RREADY_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rready <= '0';
Else
mm2s_rready <= '1';
end if;
end if;
end process RREADY_REG;
STATUS_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' ) then
mm2s_rlast_del <= '0';
Else
mm2s_rlast_del <= mm2s_rlast and mm2s_rvalid;
end if;
end if;
end process STATUS_REG;
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
rsc2data_ready = '0') then -- and -- Added more qualification here for simultaneus
-- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
Elsif (mm2s_rvalid = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr );
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
--
-- -- AXI MM2S Stream Channel Port assignments
---- mm2s_strm_wvalid <= (mm2s_rvalid and
---- sig_advance_pipe) or
---- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error
--
--
--
---- mm2s_strm_wlast <= (mm2s_rlast and
-- -- sig_next_eof_reg) or
-- -- (sig_halt_reg and -- Force tvalid high on a Halt and
-- -- sig_dqual_reg_full and -- a transfer is scheduled and
-- -- not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
-- -- not(sig_calc_error_reg)); -- not a calc error;
--
--
-- -- Generate the Write Strobes for the Stream interface
---- mm2s_strm_wstrb <= (others => '1')
---- When (sig_halt_reg = '1') -- Force tstrb high on a Halt
-- -- else sig_strt_strb_reg
-- -- When (sig_first_dbeat = '1')
-- -- Else sig_last_strb_reg
-- -- When (sig_last_dbeat = '1')
-- -- Else (others => '1');
--
--
--
--
--
-- -- MM2S Supplimental Controls
-- mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
-- sig_next_cmd_cmplt_reg) or
-- (sig_halt_reg and
-- sig_dqual_reg_full and
-- not(sig_no_posted_cmds) and
-- not(sig_calc_error_reg));
--
--
--
--
--
--
-- -- Address Channel Controller synchro pulse input
-- sig_addr_posted <= addr2data_addr_posted;
--
--
--
-- -- Request to halt the Address Channel Controller
data2skid_halt <= '0';
data2all_dcntlr_halted <= '0';
data2mstr_cmd_ready <= '0';
mm2s_data2sf_cmd_cmplt <= '0';
data2addr_stop_req <= sig_halt_reg;
data2rst_stop_cmplt <= '0';
mm2s_rd_xfer_cmplt <= '0';
--
--
-- -- Halted flag to the reset module
-- data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
-- sig_no_posted_cmds and
-- not(sig_calc_error_reg)) or
-- (sig_halt_reg_dly3 and -- Shutdown after error trap
-- sig_calc_error_reg);
--
--
--
-- -- Read Transfer Completed Status output
-- mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
--
--
--
-- -- Internal logic ------------------------------
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_RD_CMPLT_FLAG
-- --
-- -- Process Description:
-- -- Implements the status flag indicating that a read data
-- -- transfer has completed. This is an echo of a rlast assertion
-- -- and a qualified data beat on the AXI4 Read Data Channel
-- -- inputs.
-- --
-- -------------------------------------------------------------
-- IMP_RD_CMPLT_FLAG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_rd_xfer_cmplt <= '0';
--
-- else
--
-- sig_rd_xfer_cmplt <= sig_mmap2data_last and
-- sig_good_mmap_dbeat;
--
-- end if;
-- end if;
-- end process IMP_RD_CMPLT_FLAG;
--
--
--
--
--
-- -- General flag for advancing the MMap Read and the Stream
-- -- data pipelines
-- sig_advance_pipe <= sig_addr_chan_rdy and
-- sig_dqual_rdy and
-- not(sig_coelsc_reg_full) and -- new status back-pressure term
-- not(sig_calc_error_reg);
--
--
-- -- test for Kevin's status throttle case
-- sig_data2mmap_ready <= (mm2s_strm_wready or
-- sig_halt_reg) and -- Ignore the Stream ready on a Halt request
-- sig_advance_pipe;
--
--
--
-- sig_good_mmap_dbeat <= sig_data2mmap_ready and
-- sig_mmap2data_valid;
--
--
-- sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
-- sig_mmap2data_last;
--
--
-- sig_get_next_dqual <= sig_last_mmap_dbeat;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_READ_MUX
-- --
-- -- Description:
-- -- Instance of the MM2S Read Data Channel Read Mux
-- --
-- ------------------------------------------------------------
-- I_READ_MUX : entity axi_sg_v4_1_2.axi_sg_rdmux
-- generic map (
--
-- C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
-- C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
-- C_STREAM_DWIDTH => C_STREAM_DWIDTH
--
-- )
-- port map (
--
-- mmap_read_data_in => mm2s_rdata ,
-- mux_data_out => open, --mm2s_strm_wdata ,
-- mstr2data_saddr_lsb => sig_addr_lsb_reg
--
-- );
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: REG_LAST_DBEAT
-- --
-- -- Process Description:
-- -- This implements a FLOP that creates a pulse
-- -- indicating the LAST signal for an incoming read data channel
-- -- has been received. Note that it is possible to have back to
-- -- back LAST databeats.
-- --
-- -------------------------------------------------------------
-- REG_LAST_DBEAT : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_last_mmap_dbeat_reg <= '0';
--
-- else
--
-- sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
--
-- end if;
-- end if;
-- end process REG_LAST_DBEAT;
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Omits the input data control FIFO if the requested FIFO
-- -- depth is 1. The Data Qualifier Register serves as a
-- -- 1 deep FIFO by itself.
-- --
-- ------------------------------------------------------------
-- GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
--
-- begin
--
-- -- Command Calculator Handshake output
-- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
--
-- sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
--
--
--
-- -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- -- pre 13.1 -- no calculation error being propagated
--
-- sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
--
--
--
--
-- sig_fifo_next_tag <= mstr2data_tag ;
-- sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
-- sig_fifo_next_len <= mstr2data_len ;
-- sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
-- sig_fifo_next_last_strb <= mstr2data_last_strb ;
-- sig_fifo_next_drr <= mstr2data_drr ;
-- sig_fifo_next_eof <= mstr2data_eof ;
-- sig_fifo_next_sequential <= mstr2data_sequential ;
-- sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
-- sig_fifo_next_calc_error <= mstr2data_calc_error ;
--
-- sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
-- sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
--
--
--
-- end generate GEN_NO_DATA_CNTL_FIFO;
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_DATA_CNTL_FIFO
-- --
-- -- If Generate Description:
-- -- Includes the input data control FIFO if the requested
-- -- FIFO depth is more than 1.
-- --
-- ------------------------------------------------------------
---- GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
----
---- begin
----
----
---- -- Command Calculator Handshake output
---- data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
----
---- sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
----
----
---- sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
----
----
----
----
----
---- -- Format the input fifo data word
---- sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
---- mstr2data_dre_src_align &
---- mstr2data_calc_error &
---- mstr2data_cmd_cmplt &
---- mstr2data_sequential &
---- mstr2data_eof &
---- mstr2data_drr &
---- mstr2data_last_strb &
---- mstr2data_strt_strb &
---- mstr2data_len &
---- mstr2data_saddr_lsb &
---- mstr2data_tag ;
----
----
---- -- Rip the output fifo data word
---- sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
---- TAG_STRT_INDEX);
---- sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
---- SADDR_LSB_STRT_INDEX);
---- sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
---- LEN_STRT_INDEX);
---- sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- STRT_STRB_STRT_INDEX);
---- sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
---- LAST_STRB_STRT_INDEX);
---- sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
---- sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
---- sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
---- sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
---- sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
----
---- sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_SRC_STRT_INDEX);
---- sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
---- DRE_DEST_STRT_INDEX);
----
----
----
----
---- ------------------------------------------------------------
---- -- Instance: I_DATA_CNTL_FIFO
---- --
---- -- Description:
---- -- Instance for the Command Qualifier FIFO
---- --
---- ------------------------------------------------------------
---- I_DATA_CNTL_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
---- generic map (
----
---- C_DWIDTH => DCTL_FIFO_WIDTH ,
---- C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
---- C_IS_ASYNC => USE_SYNC_FIFO ,
---- C_PRIM_TYPE => FIFO_PRIM_TYPE ,
---- C_FAMILY => C_FAMILY
----
---- )
---- port map (
----
---- -- Write Clock and reset
---- fifo_wr_reset => mmap_reset ,
---- fifo_wr_clk => primary_aclk ,
----
---- -- Write Side
---- fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
---- fifo_wr_tready => sig_fifo_wr_cmd_ready ,
---- fifo_wr_tdata => sig_cmd_fifo_data_in ,
---- fifo_wr_full => open ,
----
---- -- Read Clock and reset
---- fifo_async_rd_reset => mmap_reset ,
---- fifo_async_rd_clk => primary_aclk ,
----
---- -- Read Side
---- fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
---- fifo_rd_tready => sig_fifo_rd_cmd_ready ,
---- fifo_rd_tdata => sig_cmd_fifo_data_out ,
---- fifo_rd_empty => sig_cmd_fifo_empty
----
---- );
----
----
---- end generate GEN_DATA_CNTL_FIFO;
----
--
--
--
--
--
--
--
--
-- -- Data Qualifier Register ------------------------------------
--
-- sig_ld_new_cmd <= sig_push_dqual_reg ;
-- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
-- sig_dqual_rdy <= sig_dqual_reg_full ;
-- sig_strt_strb_reg <= sig_next_strt_strb_reg ;
-- sig_last_strb_reg <= sig_next_last_strb_reg ;
-- sig_tag_reg <= sig_next_tag_reg ;
-- sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
-- sig_calc_error_reg <= sig_next_calc_error_reg ;
--
--
-- -- Flag indicating that there are no posted commands to AXI
-- sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
--
--
--
-- -- new for no bubbles between child requests
-- sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
-- sig_last_dbeat and -- last data beat of transfer
-- sig_next_sequential_reg;-- next queued command is sequential
-- -- to the current command
--
--
-- -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- -- pre 13.1 sig_dqual_reg_empty) and
-- -- pre 13.1 sig_fifo_rd_cmd_valid and
-- -- pre 13.1 sig_aposted_cntr_ready and
-- -- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
-- sig_push_dqual_reg <= (sig_sequential_push or
-- sig_dqual_reg_empty) and
-- sig_fifo_rd_cmd_valid and
-- sig_aposted_cntr_ready and
-- not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
-- not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- -- stalling the command execution pipe
--
--
-- sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
-- sig_get_next_dqual and
-- sig_dqual_reg_full ;
--
--
-- -- new for no bubbles between child requests
-- sig_clr_dqual_reg <= mmap_reset or
-- (sig_pop_dqual_reg and
-- not(sig_push_dqual_reg));
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_DQUAL_REG
-- --
-- -- Process Description:
-- -- This process implements a register for the Data
-- -- Control and qualifiers. It operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_DQUAL_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (sig_clr_dqual_reg = '1') then
--
-- sig_next_tag_reg <= (others => '0');
-- sig_next_strt_strb_reg <= (others => '0');
-- sig_next_last_strb_reg <= (others => '0');
-- sig_next_eof_reg <= '0';
-- sig_next_cmd_cmplt_reg <= '0';
-- sig_next_sequential_reg <= '0';
-- sig_next_calc_error_reg <= '0';
-- sig_next_dre_src_align_reg <= (others => '0');
-- sig_next_dre_dest_align_reg <= (others => '0');
--
-- sig_dqual_reg_empty <= '1';
-- sig_dqual_reg_full <= '0';
--
-- elsif (sig_push_dqual_reg = '1') then
--
-- sig_next_tag_reg <= sig_fifo_next_tag ;
-- sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
-- sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
-- sig_next_eof_reg <= sig_fifo_next_eof ;
-- sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
-- sig_next_sequential_reg <= sig_fifo_next_sequential ;
-- sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
-- sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
-- sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
--
-- sig_dqual_reg_empty <= '0';
-- sig_dqual_reg_full <= '1';
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_DQUAL_REG;
--
--
--
--
--
--
--
-- -- Address LS Cntr logic --------------------------
--
-- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
-- sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
-- sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_ADDR_LSB_CNTR
-- --
-- -- Process Description:
-- -- Implements the LS Address Counter used for controlling
-- -- the Read Data Mux during Burst transfers
-- --
-- -------------------------------------------------------------
-- DO_ADDR_LSB_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- (sig_pop_dqual_reg = '1' and
-- sig_push_dqual_reg = '0')) then -- Clear the Counter
--
-- sig_ls_addr_cntr <= (others => '0');
--
-- elsif (sig_push_dqual_reg = '1') then -- Load the Counter
--
-- sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
--
-- elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
--
-- sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
--
-- else
-- null; -- Hold Current value
-- end if;
-- end if;
-- end process DO_ADDR_LSB_CNTR;
--
--
--
--
--
--
--
--
--
--
--
--
-- ----- Address posted Counter logic --------------------------------
--
-- sig_incr_addr_posted_cntr <= sig_addr_posted ;
--
--
-- sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
--
--
-- sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
--
-- sig_addr_posted_cntr_eq_0 <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
-- Else '0';
--
-- sig_addr_posted_cntr_max <= '1'
-- when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
-- Else '0';
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_ADDR_POSTED_FIFO_CNTR
-- --
-- -- Process Description:
-- -- This process implements a register for the Address
-- -- Posted FIFO that operates like a 1 deep Sync FIFO.
-- --
-- -------------------------------------------------------------
-- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
--
-- elsif (sig_incr_addr_posted_cntr = '1' and
-- sig_decr_addr_posted_cntr = '0' and
-- sig_addr_posted_cntr_max = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
--
-- elsif (sig_incr_addr_posted_cntr = '0' and
-- sig_decr_addr_posted_cntr = '1' and
-- sig_addr_posted_cntr_eq_0 = '0') then
--
-- sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
--
-- else
-- null; -- don't change state
-- end if;
-- end if;
-- end process IMP_ADDR_POSTED_FIFO_CNTR;
--
--
--
--
--
--
--
--
-- ------- First/Middle/Last Dbeat detirmination -------------------
--
-- sig_new_len_eq_0 <= '1'
-- When (sig_fifo_next_len = LEN_OF_ZERO)
-- else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_FIRST_MID_LAST
-- --
-- -- Process Description:
-- -- Implements the detection of the First/Mid/Last databeat of
-- -- a transfer.
-- --
-- -------------------------------------------------------------
-- DO_FIRST_MID_LAST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- elsif (sig_ld_new_cmd = '1') then
--
-- sig_first_dbeat <= not(sig_new_len_eq_0);
-- sig_last_dbeat <= sig_new_len_eq_0;
--
-- Elsif (sig_dbeat_cntr_eq_1 = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '1';
--
-- Elsif (sig_dbeat_cntr_eq_0 = '0' and
-- sig_dbeat_cntr_eq_1 = '0' and
-- sig_good_mmap_dbeat = '1') Then
--
-- sig_first_dbeat <= '0';
-- sig_last_dbeat <= '0';
--
-- else
-- null; -- hols current state
-- end if;
-- end if;
-- end process DO_FIRST_MID_LAST;
--
--
--
--
--
-- ------- Data Controller Halted Indication -------------------------------
--
--
-- data2all_dcntlr_halted <= sig_no_posted_cmds and
-- (sig_calc_error_reg or
-- rst2data_stop_request);
--
--
--
--
-- ------- Data Beat counter logic -------------------------------
-- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
--
-- sig_dbeat_cntr_eq_0 <= '1'
-- when (sig_dbeat_cntr_int = 0)
-- Else '0';
--
-- sig_dbeat_cntr_eq_1 <= '1'
-- when (sig_dbeat_cntr_int = 1)
-- Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: DO_DBEAT_CNTR
-- --
-- -- Process Description:
-- --
-- --
-- -------------------------------------------------------------
-- DO_DBEAT_CNTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
-- sig_dbeat_cntr <= (others => '0');
-- elsif (sig_ld_new_cmd = '1') then
-- sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
-- Elsif (sig_good_mmap_dbeat = '1' and
-- sig_dbeat_cntr_eq_0 = '0') Then
-- sig_dbeat_cntr <= sig_dbeat_cntr-1;
-- else
-- null; -- Hold current state
-- end if;
-- end if;
-- end process DO_DBEAT_CNTR;
--
--
--
--
--
--
-- ------ Read Response Status Logic ------------------------------
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: LD_NEW_CMD_PULSE
-- --
-- -- Process Description:
-- -- Generate a 1 Clock wide pulse when a new command has been
-- -- loaded into the Command Register
-- --
-- -------------------------------------------------------------
-- LD_NEW_CMD_PULSE : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_ld_new_cmd_reg = '1') then
-- sig_ld_new_cmd_reg <= '0';
-- elsif (sig_ld_new_cmd = '1') then
-- sig_ld_new_cmd_reg <= '1';
-- else
-- null; -- hold State
-- end if;
-- end if;
-- end process LD_NEW_CMD_PULSE;
--
--
--
-- sig_pop_coelsc_reg <= sig_coelsc_reg_full and
-- sig_rsc2data_ready ;
--
-- sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
-- not(sig_coelsc_reg_full)) or
-- (sig_ld_new_cmd_reg and
-- sig_calc_error_reg) ;
--
-- sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
-- sig_calc_error_reg;
--
--
--
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: RD_RESP_COELESC_REG
-- --
-- -- Process Description:
-- -- Implement the Read error/status coelescing register.
-- -- Once a bit is set it will remain set until the overall
-- -- status is written to the Status Controller.
-- -- Tag bits are just registered at each valid dbeat.
-- --
-- -------------------------------------------------------------
---- STATUS_COELESC_REG : process (primary_aclk)
---- begin
---- if (primary_aclk'event and primary_aclk = '1') then
---- if (mmap_reset = '1' or
---- (sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
---- sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
----
---- sig_coelsc_tag_reg <= (others => '0');
---- sig_coelsc_cmd_cmplt_reg <= '0';
---- sig_coelsc_interr_reg <= '0';
---- sig_coelsc_decerr_reg <= '0';
---- sig_coelsc_slverr_reg <= '0';
---- sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
----
---- sig_coelsc_reg_full <= '0';
---- sig_coelsc_reg_empty <= '1';
----
----
----
---- Elsif (sig_push_coelsc_reg = '1') Then
----
---- sig_coelsc_tag_reg <= sig_tag_reg;
---- sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_interr_reg <= sig_calc_error_reg or
---- sig_coelsc_interr_reg;
---- sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
---- sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
---- sig_coelsc_okay_reg <= not(sig_decerr or
---- sig_slverr or
---- sig_calc_error_reg );
----
---- sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
---- sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
----
----
---- else
----
---- null; -- hold current state
----
---- end if;
---- end if;
---- end process STATUS_COELESC_REG;
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_NO_DRE
-- --
-- -- If Generate Description:
-- -- Ties off DRE Control signals to logic low when DRE is
-- -- omitted from the MM2S functionality.
-- --
-- --
-- ------------------------------------------------------------
-- GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
--
-- begin
--
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
--
-- end generate GEN_NO_DRE;
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------------------------------------------------------------
-- -- If Generate
-- --
-- -- Label: GEN_INCLUDE_DRE_CNTLS
-- --
-- -- If Generate Description:
-- -- Implements the DRE Control logic when MM2S DRE is enabled.
-- --
-- -- - The DRE needs to have forced alignment at a SOF assertion
-- --
-- --
-- ------------------------------------------------------------
-- GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
--
-- -- local signals
-- signal lsig_s_h_dre_autodest : std_logic := '0';
-- signal lsig_s_h_dre_new_align : std_logic := '0';
--
-- begin
--
--
-- mm2s_dre_new_align <= lsig_s_h_dre_new_align;
--
--
--
--
-- -- Autodest is asserted on a new parent command and the
-- -- previous parent command was not delimited with a EOF
-- mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
--
--
--
--
-- -- Assign the DRE Source and Destination Alignments
-- -- Only used when mm2s_dre_new_align is asserted
-- mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
-- mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
--
--
-- -- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- -- asserted and the next transfer is not sequential and not the last
-- -- transfer of a packet.
-- mm2s_dre_flush <= mm2s_rlast and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_NEW_ALIGN
-- --
-- -- Process Description:
-- -- Generates the new alignment command flag to the DRE.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_NEW_ALIGN : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_new_align <= '1';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_new_align <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_NEW_ALIGN;
--
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_S_H_AUTODEST
-- --
-- -- Process Description:
-- -- Generates the control for the DRE indicating whether the
-- -- DRE destination alignment should be derived from the write
-- -- strobe stat of the last completed data-beat to the AXI
-- -- stream output.
-- --
-- -------------------------------------------------------------
-- IMP_S_H_AUTODEST : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- Elsif (sig_push_dqual_reg = '1' and
-- sig_fifo_next_drr = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
-- elsif (sig_pop_dqual_reg = '1') then
--
-- lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
-- not(sig_next_sequential_reg) and
-- not(sig_next_eof_reg);
--
-- Elsif (lsig_s_h_dre_new_align = '1' and
-- sig_good_mmap_dbeat = '1') Then
--
-- lsig_s_h_dre_autodest <= '0';
--
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_S_H_AUTODEST;
--
--
--
--
-- end generate GEN_INCLUDE_DRE_CNTLS;
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- ------- Soft Shutdown Logic -------------------------------
--
--
-- -- Assign the output port skid buf control
-- data2skid_halt <= sig_data2skid_halt;
--
-- -- Create a 1 clock wide pulse to tell the output
-- -- stream skid buffer to shut down its outputs
-- sig_data2skid_halt <= sig_halt_reg_dly2 and
-- not(sig_halt_reg_dly3);
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG
-- --
-- -- Process Description:
-- -- Implements the flop for capturing the Halt request from
-- -- the Reset module.
-- --
-- -------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_HALT_REQ_REG_DLY
-- --
-- -- Process Description:
-- -- Implements the flops for delaying the halt request by 3
-- -- clocks to allow the Address Controller to halt before the
-- -- Data Contoller can safely indicate it has exhausted all
-- -- transfers committed to the AXI Address Channel by the Address
-- -- Controller.
-- --
-- -------------------------------------------------------------
-- IMP_HALT_REQ_REG_DLY : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- sig_halt_reg_dly1 <= '0';
-- sig_halt_reg_dly2 <= '0';
-- sig_halt_reg_dly3 <= '0';
--
-- else
--
-- sig_halt_reg_dly1 <= sig_halt_reg;
-- sig_halt_reg_dly2 <= sig_halt_reg_dly1;
-- sig_halt_reg_dly3 <= sig_halt_reg_dly2;
--
-- end if;
-- end if;
-- end process IMP_HALT_REQ_REG_DLY;
--
--
--
--
--
--
--
--
--
end implementation;
| gpl-3.0 | e0910bac33b651104ff6fc8b3ac4cdf7 | 0.390536 | 4.438921 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/tb_var03.vhdl | 1 | 808 | entity tb_var03 is
end tb_var03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var03 is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal a, b : std_logic_vector (15 downto 0);
signal res : std_logic_vector (15 downto 0);
begin
dut: entity work.var03
port map (
mask => mask,
a => a,
b => b,
res => res);
process
begin
mask <= "11";
a <= x"12_34";
b <= x"aa_bb";
wait for 1 ns;
assert res = x"aa_bb" severity failure;
mask <= "00";
a <= x"aa_bb";
b <= x"12_34";
wait for 1 ns;
assert res = x"aa_bb" severity failure;
mask <= "10";
a <= x"aa_bb";
b <= x"12_34";
wait for 1 ns;
assert res = x"12_bb" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 55ea106d5de834469a5746640fbd51c1 | 0.558168 | 2.98155 | false | false | false | false |
nickg/nvc | test/regress/alias13.vhd | 1 | 521 | entity alias13 is
end entity;
architecture test of alias13 is
type mat2d is array (natural range <>, natural range <>) of integer;
signal s1 : mat2d(1 to 2, 1 to 2);
alias a : mat2d is s1; -- OK (2008)
begin
main: process is
begin
s1 <= ((1, 2), (3, 4));
wait for 1 ns;
assert a = ((1, 2), (3, 4));
assert a(1, 1) = 1;
a(2, 2) <= 66;
wait for 1 ns;
assert s1 = ((1, 2), (3, 66));
wait;
end process;
end architecture;
| gpl-3.0 | 6caa8a07f528093792062371072ad1ed | 0.497121 | 3.157576 | false | false | false | false |
nickg/nvc | test/regress/issue460.vhd | 1 | 691 | entity issue460 is
end entity;
architecture test of issue460 is
signal a, b : bit;
signal x : natural;
begin
p1: process (a, b) is
begin
case bit_vector'(a & b) is
when "10" =>
x <= 1;
when "01" =>
x <= 2;
when others =>
x <= 3;
end case;
end process;
check: process is
begin
wait for 0 ns;
assert x = 3;
a <= '1';
wait for 1 ns;
assert x = 1;
b <= '1';
wait for 1 ns;
assert x = 3;
a <= '0';
wait for 1 ns;
assert x = 2;
wait;
end process;
end architecture;
| gpl-3.0 | 2623d2b249e1cb93b2334f439a8c07e9 | 0.418234 | 3.81768 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd | 4 | 2,477 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_ch_04_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_04_07 is
end entity ch_04_07;
----------------------------------------------------------------
architecture test of ch_04_07 is
begin
process_04_3_a : process is
-- code from book:
subtype pixel_row is bit_vector (0 to 15);
variable current_row, mask : pixel_row;
-- end of code from book
begin
current_row := "0000000011111111";
mask := "0000111111110000";
-- code from book:
current_row := current_row and not mask;
current_row := current_row xor X"FFFF";
-- end of code from book
-- code from book (conditions only):
assert B"10001010" sll 3 = B"01010000";
assert B"10001010" sll -2 = B"00100010";
assert B"10010111" srl 2 = B"00100101";
assert B"10010111" srl -6 = B"11000000";
assert B"01001011" sra 3 = B"00001001";
assert B"10010111" sra 3 = B"11110010";
assert B"00001100" sla 2 = B"00110000";
assert B"00010001" sla 2 = B"01000111";
assert B"00010001" sra -2 = B"01000111";
assert B"00110000" sla -2 = B"00001100";
assert B"10010011" rol 1 = B"00100111";
assert B"10010011" ror 1 = B"11001001";
assert "abc" & 'd' = "abcd";
assert 'w' & "xyz" = "wxyz";
assert 'a' & 'b' = "ab";
-- end of code from book
wait;
end process process_04_3_a;
end architecture test;
| gpl-2.0 | b1eb43daebb742113aeeae7b37b8952a | 0.56843 | 3.846273 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/axi_stream_send.vhd | 1 | 4,712 | -------------------------------------------------------------------------------------
-- FILE NAME : .vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture -
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Simple AXI-Stream Master to generate data. Output COUNT worth of data by sequentially reading
-- a block ROM COUNT times. Loop around the block ROM if COUNT is greater than the address range
-- of the block ROM.
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity axi_stream_send is
generic (
COUNT : std_logic_vector(31 downto 0) := x"00000100"
);
port (
clk : in std_logic;
rstn : in std_logic;
tdata : out std_logic_vector(63 downto 0);
tvalid : out std_logic;
enable : in std_logic
);
end axi_stream_send;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of axi_stream_send is
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal state : std_logic_vector(3 downto 0);
signal rst : std_logic;
signal tdata_r : std_logic_vector(63 downto 0);
signal tvalid_r : std_logic;
signal rom_addr : std_logic_vector(1 downto 0);
signal rom_data : std_logic_vector(63 downto 0);
signal rom_en : std_logic;
signal counter : std_logic_vector(63 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
tdata <= tdata_r;
tvalid <= tvalid_r;
-------------------------------------------------------------------------------------
-- Local Reset
-------------------------------------------------------------------------------------
process (clk) is
begin
if rising_edge(clk) then
rst <= not rstn;
end if;
end process;
-------------------------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= x"0";
rom_en <= '0';
rom_addr <= (others=>'0');
counter <= (others =>'0');
else
rom_en <= '0';
rom_addr <= (others=>'0');
case state is
when x"0" =>
if enable = '1' then
state <= x"1";
end if;
when x"1" =>
if counter /= COUNT then
counter <= counter + 1;
rom_en <= '1';
rom_addr <= rom_addr + 1;
else
counter <= (others=>'0');
state <= x"0";
end if;
when others =>
state <= x"0";
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------------
-- Block ROM Instance
-------------------------------------------------------------------------------------
inst_rom:
entity work.rom
generic map(
DATA_WIDTH => 64,
ADDR_WIDTH => 2
)
port map (
CLK => clk,
ADDR => rom_addr,
EN => rom_en,
DO => tdata_r,
VAL => tvalid_r
);
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 221ac5295d098860cc9b9150d135f461 | 0.298175 | 5.817284 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/convolution_2D/solution1/syn/vhdl/doImgProc_CRTL_BUS_s_axi.vhd | 4 | 12,615 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doImgProc_CRTL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity doImgProc_CRTL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doImgProc_CRTL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#10#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_operation : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | 244dd3eaff38565fef9b006730e874d9 | 0.450575 | 3.869632 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd | 4 | 1,631 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity amp_lim is
port ( terminal ps : electrical; -- positive supply terminal
terminal input, output : electrical );
end entity amp_lim;
----------------------------------------------------------------
architecture simple of amp_lim is
quantity v_pwr across i_pwr through ps to electrical_ref;
quantity vin across iin through input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity v_amplified : voltage ;
constant gain : real := 1.0;
begin
v_amplified == gain * vin;
if v_amplified'above(v_pwr) use
vout == v_pwr;
else
vout == v_amplified;
end use;
break on v_amplified'above(v_pwr);
-- ignore loading effects
i_pwr == 0.0;
iin == 0.0;
end architecture simple;
| gpl-2.0 | 620c7ed1a5366103ad55448302e70e53 | 0.686082 | 4.139594 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_206.vhd | 2 | 1,730 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_206 is
port (
gt : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_206;
architecture augh of sub_206 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
| gpl-2.0 | aa675e6241ae757c95929b797c4e64ce | 0.624277 | 2.578241 | false | false | false | false |
nickg/nvc | test/regress/record18.vhd | 1 | 1,130 | package pack is
type rec is record
x : integer;
y : integer;
z : boolean;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( r : rec );
port (
i : in bit_vector(1 to r.y);
o : out bit );
end entity;
architecture test of sub is
begin
g1: if r.z generate
o <= i(r.x);
end generate;
g2: if not r.z generate
o <= '1';
end generate;
end architecture;
-------------------------------------------------------------------------------
entity record18 is
end entity;
use work.pack.all;
architecture test of record18 is
constant r1 : rec := (1, 2, true);
constant r2 : rec := (0, 0, false);
signal o1, o2 : bit;
begin
sub1_i: entity work.sub
generic map (r1) port map ( "10", o1 );
sub2_i: entity work.sub
generic map (r2) port map ( (others => '0'), o2 );
process is
begin
wait for 1 ns;
assert o1 = '1';
assert o2 = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 150393f01851d17a0188a3146af22086 | 0.467257 | 3.729373 | false | false | false | false |
snow4life/PipelinedDLX | alu/alu.vhd | 1 | 3,508 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity ALU is
port( A: in std_logic_vector(31 downto 0);
B: in std_logic_vector(31 downto 0);
ALU_SEL: in std_logic_vector(1 downto 0);
COMPARATOR_CW: in std_logic_vector(5 downto 0);
LOGIC_CW: in std_logic_vector(3 downto 0);
SHIFTER_CW: in std_logic_vector(2 downto 0);
ADD_SUB: in std_logic;
ALU_OUT: out std_logic_vector(31 downto 0);
ZERO: out std_logic;
OVERFLOW: out std_logic);
end entity ALU;
architecture STRUCTURAL of ALU is
constant N: integer := 32;
signal ADDER_OUT: std_logic_vector(N-1 downto 0);
signal COMPARATOR_OUT: std_logic_vector(N-1 downto 0);
signal LOGIC_OUT: std_logic_vector(N-1 downto 0);
signal SHIFTER_OUT: std_logic_vector(N-1 downto 0);
signal INTERNAL_B: std_logic_vector(N-1 downto 0);
signal CARRY_OUT: std_logic;
signal NOT_ADD_SUB: std_logic;
component CARRY_SELECT_ADDER
port( A: in std_logic_vector(31 downto 0);
B: in std_logic_vector(31 downto 0);
S: out std_logic_vector(31 downto 0);
Ci: in std_logic;
Co: out std_logic
);
end component CARRY_SELECT_ADDER;
component COMPARATOR_GENERIC
generic(N: integer);
port( SUB: in std_logic_vector(N-1 downto 0);
CARRY: in std_logic;
EQUAL: in std_logic;
NOT_EQUAL: in std_logic;
GREATER: in std_logic;
GREATER_EQUAL: in std_logic;
LOWER: in std_logic;
LOWER_EQUAL: in std_logic;
COMPARATOR_OUT: out std_logic_vector(N-1 downto 0);
ZERO: out std_logic
);
end component COMPARATOR_GENERIC;
component LOGIC_GENERIC
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
S: in std_logic_vector(3 downto 0);
LOGIC_OUT: out std_logic_vector(N-1 downto 0)
);
end component LOGIC_GENERIC;
component SHIFTER_GENERIC
generic(N: integer);
port( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(4 downto 0);
LOGIC_ARITH: in std_logic; -- 1 = logic, 0 = arith
LEFT_RIGHT: in std_logic; -- 1 = left, 0 = right
SHIFT_ROTATE: in std_logic; -- 1 = shift, 0 = rotate
OUTPUT: out std_logic_vector(N-1 downto 0)
);
end component SHIFTER_GENERIC;
begin
CARRY_SELECT_ADDER_I : CARRY_SELECT_ADDER
port map ( A => A,
B => INTERNAL_B,
S => ADDER_OUT,
Ci => NOT_ADD_SUB,
Co => CARRY_OUT
);
COMPARATOR_GENERIC_I : COMPARATOR_GENERIC
generic map (N => N)
port map ( SUB => ADDER_OUT,
CARRY => CARRY_OUT,
EQUAL => COMPARATOR_CW(0),
NOT_EQUAL => COMPARATOR_CW(1),
GREATER => COMPARATOR_CW(2),
GREATER_EQUAL => COMPARATOR_CW(3),
LOWER => COMPARATOR_CW(4),
LOWER_EQUAL => COMPARATOR_CW(5),
COMPARATOR_OUT => COMPARATOR_OUT,
ZERO => ZERO
);
LOGIC_GENERIC_I : LOGIC_GENERIC
generic map (N => N)
port map ( A => A,
B => B,
S => LOGIC_CW,
LOGIC_OUT => LOGIC_OUT
);
SHIFTER_GENERIC_I : SHIFTER_GENERIC
generic map (N => N)
port map ( A => A,
B => B(4 downto 0),
LOGIC_ARITH => SHIFTER_CW(0),
LEFT_RIGHT => SHIFTER_CW(1),
SHIFT_ROTATE => SHIFTER_CW(2),
OUTPUT => SHIFTER_OUT
);
NOT_ADD_SUB <= (not ADD_SUB);
INTERNAL_B <= B xor (31 downto 0 => NOT_ADD_SUB);
OVERFLOW <= CARRY_OUT;
ALU_OUT <= ADDER_OUT when ALU_SEL = "00" else
COMPARATOR_OUT when ALU_SEL = "01" else
LOGIC_OUT when ALU_SEL = "10" else
SHIFTER_OUT when ALU_SEL = "11";
end architecture STRUCTURAL; | lgpl-2.1 | 8d99735521b1481e04ef2b470de76c7e | 0.643101 | 2.70679 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_pb_lwh2f/ghrd_10as066n2_pb_lwh2f_inst.vhd | 1 | 4,648 | component ghrd_10as066n2_pb_lwh2f is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component ghrd_10as066n2_pb_lwh2f;
u0 : component ghrd_10as066n2_pb_lwh2f
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
| mit | d58d352315befbbd7927e3de8d83b3f1 | 0.493115 | 3.748387 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | BSA/32bits/BSA32bits/BSA32bits.vhd | 1 | 1,602 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY BSA32bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC
);
END BSA32bits;
architecture strc_BSA32bits of BSA32bits is
SIGNAL Cin_temp, Cout_temp, Cout_sig, done: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(31 DOWNTO 0);
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg32Bit
PORT (
valIn: in std_logic_vector(31 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(31 downto 0)
);
end component;
begin
Reg_A: Reg32Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg32Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cin_temp,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg32Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
process(clk,rst,done)
variable counter: integer range 0 to 32 := 0;
begin
if rst = '1' then
Cin_temp <= '0';
elsif (clk='1' and clk'event) then
Out_sig(counter) <= (A_sig(counter) XOR B_sig(counter)) XOR Cin_temp;
Cin_temp <= (A_sig(counter) AND B_sig(counter)) OR (Cin_temp AND A_sig(counter)) OR (Cin_temp AND B_sig(counter));
counter := counter + 1;
end if;
end process;
end strc_BSA32bits; | mit | 76a4265e14da3d22d7cbf11d81d19e20 | 0.661673 | 2.600649 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_hps_m/ghrd_10as066n2_hps_m_inst.vhd | 1 | 2,096 | component ghrd_10as066n2_hps_m is
port (
clk_clk : in std_logic := 'X'; -- clk
clk_reset_reset : in std_logic := 'X'; -- reset
master_address : out std_logic_vector(31 downto 0); -- address
master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
master_read : out std_logic; -- read
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(31 downto 0); -- writedata
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_readdatavalid : in std_logic := 'X'; -- readdatavalid
master_byteenable : out std_logic_vector(3 downto 0); -- byteenable
master_reset_reset : out std_logic -- reset
);
end component ghrd_10as066n2_hps_m;
u0 : component ghrd_10as066n2_hps_m
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clk_reset_reset => CONNECTED_TO_clk_reset_reset, -- clk_reset.reset
master_address => CONNECTED_TO_master_address, -- master.address
master_readdata => CONNECTED_TO_master_readdata, -- .readdata
master_read => CONNECTED_TO_master_read, -- .read
master_write => CONNECTED_TO_master_write, -- .write
master_writedata => CONNECTED_TO_master_writedata, -- .writedata
master_waitrequest => CONNECTED_TO_master_waitrequest, -- .waitrequest
master_readdatavalid => CONNECTED_TO_master_readdatavalid, -- .readdatavalid
master_byteenable => CONNECTED_TO_master_byteenable, -- .byteenable
master_reset_reset => CONNECTED_TO_master_reset_reset -- master_reset.reset
);
| mit | 8b437efb00beacf6bcc659cd313f6c6d | 0.49666 | 4.08577 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/src/common/vectors.vhdl | 4 | 29,645 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
package vectors is
-- ==========================================================================
-- Type declarations
-- ==========================================================================
-- STD_LOGIC_VECTORs
subtype T_SLV_2 is STD_LOGIC_VECTOR(1 downto 0);
subtype T_SLV_3 is STD_LOGIC_VECTOR(2 downto 0);
subtype T_SLV_4 is STD_LOGIC_VECTOR(3 downto 0);
subtype T_SLV_8 is STD_LOGIC_VECTOR(7 downto 0);
subtype T_SLV_12 is STD_LOGIC_VECTOR(11 downto 0);
subtype T_SLV_16 is STD_LOGIC_VECTOR(15 downto 0);
subtype T_SLV_24 is STD_LOGIC_VECTOR(23 downto 0);
subtype T_SLV_32 is STD_LOGIC_VECTOR(31 downto 0);
subtype T_SLV_48 is STD_LOGIC_VECTOR(47 downto 0);
subtype T_SLV_64 is STD_LOGIC_VECTOR(63 downto 0);
subtype T_SLV_96 is STD_LOGIC_VECTOR(95 downto 0);
subtype T_SLV_128 is STD_LOGIC_VECTOR(127 downto 0);
subtype T_SLV_256 is STD_LOGIC_VECTOR(255 downto 0);
subtype T_SLV_512 is STD_LOGIC_VECTOR(511 downto 0);
-- STD_LOGIC_VECTOR_VECTORs
-- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx
type T_SLVV_2 is array(NATURAL range <>) of T_SLV_2;
type T_SLVV_3 is array(NATURAL range <>) of T_SLV_3;
type T_SLVV_4 is array(NATURAL range <>) of T_SLV_4;
type T_SLVV_8 is array(NATURAL range <>) of T_SLV_8;
type T_SLVV_12 is array(NATURAL range <>) of T_SLV_12;
type T_SLVV_16 is array(NATURAL range <>) of T_SLV_16;
type T_SLVV_24 is array(NATURAL range <>) of T_SLV_24;
type T_SLVV_32 is array(NATURAL range <>) of T_SLV_32;
type T_SLVV_48 is array(NATURAL range <>) of T_SLV_48;
type T_SLVV_64 is array(NATURAL range <>) of T_SLV_64;
type T_SLVV_128 is array(NATURAL range <>) of T_SLV_128;
type T_SLVV_256 is array(NATURAL range <>) of T_SLV_256;
type T_SLVV_512 is array(NATURAL range <>) of T_SLV_512;
-- STD_LOGIC_MATRIXs
type T_SLM is array(NATURAL range <>, NATURAL range <>) of STD_LOGIC;
-- ATTENTION:
-- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
-- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
-- 2. Xilinx iSIM work-around: DON'T use myMatrix'range(n) for n >= 2
-- because: myMatrix'range(2) returns always myMatrix'range(1); tested with ISE/iSIM 14.2
-- USAGE NOTES:
-- dimmension 1 => rows - e.g. Words
-- dimmension 2 => columns - e.g. Bits/Bytes in a word
-- ==========================================================================
-- Function declarations
-- ==========================================================================
-- slicing boundary calulations
function low (lenvec : T_POSVEC; index : NATURAL) return NATURAL;
function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL;
-- Assign procedures: assign_*
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL); -- assign vector to complete row
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL); -- assign short vector to row starting at position
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL); -- assign short vector to row in range high:low
procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL); -- assign vector to complete column
-- ATTENTION: see T_SLM definition for further details and work-arounds
-- Matrix to matrix conversion: slm_slice*
function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width
function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM; -- get submatrix / all columns in ColIndex range high:low
-- Matrix to vector conversion: get_*
function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix column
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR; -- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR; -- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR; -- get a sub vector of a matrix row at high:low
-- Convert to vector: to_slv
function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR; -- convert vector-vector to flatten vector
-- Convert flat vector to avector-vector: to_slvv_*
function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4; --
function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8; --
function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12; --
function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16; --
function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32; --
function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64; --
function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128; --
function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256; --
function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512; --
-- Convert matrix to avector-vector: to_slvv_*
function to_slvv_4(slm : T_SLM) return T_SLVV_4; --
function to_slvv_8(slm : T_SLM) return T_SLVV_8; --
function to_slvv_12(slm : T_SLM) return T_SLVV_12; --
function to_slvv_16(slm : T_SLM) return T_SLVV_16; --
function to_slvv_32(slm : T_SLM) return T_SLVV_32; --
function to_slvv_64(slm : T_SLM) return T_SLVV_64; --
function to_slvv_128(slm : T_SLM) return T_SLVV_128; --
function to_slvv_256(slm : T_SLM) return T_SLVV_256; --
function to_slvv_512(slm : T_SLM) return T_SLVV_512; --
-- Convert vector-vector to matrix: to_slm
function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector
-- Change vector direction
function dir(slvv : T_SLVV_8) return T_SLVV_8;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4;
function rev(slvv : T_SLVV_8) return T_SLVV_8;
function rev(slvv : T_SLVV_12) return T_SLVV_12;
function rev(slvv : T_SLVV_16) return T_SLVV_16;
function rev(slvv : T_SLVV_32) return T_SLVV_32;
function rev(slvv : T_SLVV_64) return T_SLVV_64;
function rev(slvv : T_SLVV_128) return T_SLVV_128;
function rev(slvv : T_SLVV_256) return T_SLVV_256;
function rev(slvv : T_SLVV_512) return T_SLVV_512;
-- TODO:
function resize(slm : T_SLM; size : POSITIVE) return T_SLM;
-- to_string
function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING;
end package vectors;
package body vectors is
-- slicing boundary calulations
-- ==========================================================================
function low(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
variable pos : NATURAL := 0;
begin
for i in lenvec'low to index - 1 loop
pos := pos + lenvec(i);
end loop;
return pos;
end function;
function high(lenvec : T_POSVEC; index : NATURAL) return NATURAL is
variable pos : NATURAL := 0;
begin
for i in lenvec'low to index loop
pos := pos + lenvec(i);
end loop;
return pos - 1;
end function;
-- Assign procedures: assign_*
-- ==========================================================================
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); tested with ISE/iSIM 14.2
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; Position : NATURAL) is
variable temp : STD_LOGIC_VECTOR(Position + slv'length - 1 downto Position);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant RowIndex : NATURAL; High : NATURAL; Low : NATURAL) is
variable temp : STD_LOGIC_VECTOR(High downto Low);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_col(signal slm : out T_SLM; slv : STD_LOGIC_VECTOR; constant ColIndex : NATURAL) is
variable temp : STD_LOGIC_VECTOR(slm'range(1));
begin
temp := slv;
for i in temp'range loop
slm(i, ColIndex) <= temp(i);
end loop;
end procedure;
-- Matrix to matrix conversion: slm_slice*
-- ==========================================================================
function slm_slice(slm : T_SLM; RowIndex : NATURAL; ColIndex : NATURAL; Height : NATURAL; Width : NATURAL) return T_SLM is
variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to Height - 1 loop
for j in 0 to Width - 1 loop
Result(i, j) := slm(RowIndex + i, ColIndex + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_cols(slm : T_SLM; High : NATURAL; Low : NATURAL) return T_SLM is
variable Result : T_SLM(slm'range(1), High - Low downto 0) := (others => (others => '0'));
begin
for i in slm'range(1) loop
for j in 0 to High - Low loop
Result(i, j) := slm(i, low + j);
end loop;
end loop;
return Result;
end function;
-- Matrix to vector conversion: get_*
-- ==========================================================================
-- get a matrix column
function get_col(slm : T_SLM; ColIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
-- get a matrix row
function get_row(slm : T_SLM; RowIndex : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(slm'high(2) downto slm'low(2)); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : NATURAL; Length : POSITIVE) return STD_LOGIC_VECTOR is
begin
return get_row(slm, RowIndex, (Length - 1), 0);
end function;
-- get a sub vector of a matrix row at high:low
function get_row(slm : T_SLM; RowIndex : NATURAL; High : NATURAL; Low : NATURAL) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR(High downto Low); -- Xilinx iSIM work-around, because 'range(2) = 'range(1); tested with ISE/iSIM 14.2
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_8) return STD_LOGIC_VECTOR is
variable slv : STD_LOGIC_VECTOR((slvv'length * 8) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 8) + 7 downto (i * 8)) := slvv(i);
end loop;
return slv;
end function;
-- Convert flat vector to a vector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from vector (4 bit)
function to_slvv_4(slv : STD_LOGIC_VECTOR) return T_SLVV_4 is
variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0);
begin
if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 4) + 3 downto (i * 4));
end loop;
return Result;
end function;
-- create vector-vector from vector (8 bit)
function to_slvv_8(slv : STD_LOGIC_VECTOR) return T_SLVV_8 is
variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0);
begin
if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 8) + 7 downto (i * 8));
end loop;
return Result;
end function;
-- create vector-vector from vector (12 bit)
function to_slvv_12(slv : STD_LOGIC_VECTOR) return T_SLVV_12 is
variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0);
begin
if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 12) + 11 downto (i * 12));
end loop;
return Result;
end function;
-- create vector-vector from vector (16 bit)
function to_slvv_16(slv : STD_LOGIC_VECTOR) return T_SLVV_16 is
variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0);
begin
if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 16) + 15 downto (i * 16));
end loop;
return Result;
end function;
-- create vector-vector from vector (32 bit)
function to_slvv_32(slv : STD_LOGIC_VECTOR) return T_SLVV_32 is
variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0);
begin
if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 32) + 31 downto (i * 32));
end loop;
return Result;
end function;
-- create vector-vector from vector (64 bit)
function to_slvv_64(slv : STD_LOGIC_VECTOR) return T_SLVV_64 is
variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0);
begin
if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 64) + 63 downto (i * 64));
end loop;
return Result;
end function;
-- create vector-vector from vector (128 bit)
function to_slvv_128(slv : STD_LOGIC_VECTOR) return T_SLVV_128 is
variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0);
begin
if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 128) + 127 downto (i * 128));
end loop;
return Result;
end function;
-- create vector-vector from vector (256 bit)
function to_slvv_256(slv : STD_LOGIC_VECTOR) return T_SLVV_256 is
variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0);
begin
if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 256) + 255 downto (i * 256));
end loop;
return Result;
end function;
-- create vector-vector from vector (512 bit)
function to_slvv_512(slv : STD_LOGIC_VECTOR) return T_SLVV_512 is
variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0);
begin
if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 512) + 511 downto (i * 512));
end loop;
return Result;
end function;
-- Convert matrix to avector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from matrix (4 bit)
function to_slvv_4(slm : T_SLM) return T_SLVV_4 is
variable Result : T_SLVV_4(slm'range(1));
begin
if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (8 bit)
function to_slvv_8(slm : T_SLM) return T_SLVV_8 is
variable Result : T_SLVV_8(slm'range(1));
begin
if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (12 bit)
function to_slvv_12(slm : T_SLM) return T_SLVV_12 is
variable Result : T_SLVV_12(slm'range(1));
begin
if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (16 bit)
function to_slvv_16(slm : T_SLM) return T_SLVV_16 is
variable Result : T_SLVV_16(slm'range(1));
begin
if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (32 bit)
function to_slvv_32(slm : T_SLM) return T_SLVV_32 is
variable Result : T_SLVV_32(slm'range(1));
begin
if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (64 bit)
function to_slvv_64(slm : T_SLM) return T_SLVV_64 is
variable Result : T_SLVV_64(slm'range(1));
begin
if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (128 bit)
function to_slvv_128(slm : T_SLM) return T_SLVV_128 is
variable Result : T_SLVV_128(slm'range(1));
begin
if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (256 bit)
function to_slvv_256(slm : T_SLM) return T_SLVV_256 is
variable Result : T_SLVV_256(slm'range);
begin
if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (512 bit)
function to_slvv_512(slm : T_SLM) return T_SLVV_512 is
variable Result : T_SLVV_512(slm'range(1));
begin
if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & INTEGER'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- Convert vector-vector to matrix: to_slm
-- ==========================================================================
-- create matrix from vector-vector
function to_slm(slvv : T_SLVV_4) return T_SLM is
variable slm : T_SLM(slvv'range, 3 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_4'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_8) return T_SLM is
-- variable test : STD_LOGIC_VECTOR(T_SLV_8'range);
-- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down
-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimmension 2
variable slm : T_SLM(slvv'range, 7 downto 0);
begin
-- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE;
-- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE;
-- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE;
for i in slvv'range loop
for j in T_SLV_8'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_12) return T_SLM is
variable slm : T_SLM(slvv'range, 11 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_12'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_16) return T_SLM is
variable slm : T_SLM(slvv'range, 15 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_16'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_32) return T_SLM is
variable slm : T_SLM(slvv'range, 31 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_32'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_48) return T_SLM is
variable slm : T_SLM(slvv'range, 47 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_48'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_64) return T_SLM is
variable slm : T_SLM(slvv'range, 63 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_64'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_128) return T_SLM is
variable slm : T_SLM(slvv'range, 127 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_128'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_256) return T_SLM is
variable slm : T_SLM(slvv'range, 255 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_256'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_512) return T_SLM is
variable slm : T_SLM(slvv'range, 511 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_512'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
-- Change vector direction
-- ==========================================================================
function dir(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'reverse_range);
begin
Result := slvv;
return Result;
end function;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4 is
variable Result : T_SLVV_4(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_12) return T_SLVV_12 is
variable Result : T_SLVV_12(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_16) return T_SLVV_16 is
variable Result : T_SLVV_16(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_32) return T_SLVV_32 is
variable Result : T_SLVV_32(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_64) return T_SLVV_64 is
variable Result : T_SLVV_64(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_128) return T_SLVV_128 is
variable Result : T_SLVV_128(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_256) return T_SLVV_256 is
variable Result : T_SLVV_256(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_512) return T_SLVV_512 is
variable Result : T_SLVV_512(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
-- Resize functions
-- ==========================================================================
-- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input
-- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for
-- value-preserving resizes of the signed and unsigned data types.
function resize(slm : T_SLM; size : POSITIVE) return T_SLM is
variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0'));
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i, j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_string(slvv : T_SLVV_8; sep : CHARACTER := ':') return STRING is
constant hex_len : POSITIVE := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1);
variable Result : STRING(1 to hex_len) := (others => sep);
variable pos : POSITIVE := 1;
begin
for i in slvv'range loop
Result(pos to pos + 1) := to_string(slvv(i), 'h');
pos := pos + ite((sep = C_POC_NUL), 2, 3);
end loop;
return Result;
end function;
end package body;
| gpl-2.0 | 5038ec6f57bd1f1a2def815526935ee5 | 0.624085 | 3.04301 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_spi/spi_checker.vhd | 1 | 9,576 | -------------------------------------------------------------------------------------
-- FILE NAME : spi_checker.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity spi_checker is
generic (
SIM_ONLY : natural := 0;
CLK_FREQ : natural := 250
);
port (
clk : in std_logic;
sclk : in std_logic;
sdo : out std_logic;
sdi : in std_logic;
cs_n : in std_logic;
reg0 : out std_logic_vector(31 downto 0)
);
end spi_checker;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of spi_checker is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant DEBUG_ENABLE : boolean := FALSE;
attribute keep : string;
attribute S : string;
type cmd_state_machine is (HOLD_CMD, BYTE0_CMD, BYTE1_CMD, BYTE2_CMD, BYTE3_CMD, BYTE4_CMD,
BYTE5_CMD, BYTE6_CMD, BYTE7_CMD, BYTE8_CMD, BYTE9_CMD, BYTE10_CMD,
BYTE11_CMD, BYTE12_CMD, BYTE13_CMD, BYTE14_CMD, BYTE15_CMD);
type bus04 is array(natural range <>) of std_logic_vector( 3 downto 0);
constant WR_BIT : std_logic := '0'; -- 0 means write
constant RD_BIT : std_logic := '1'; -- 1 means read
constant FULL_WIDTH : natural := 24;
constant ADDR_WIDTH : natural := 8;
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal clock_count : std_logic_vector(7 downto 0);
signal write_cmd : std_logic;
signal sdi_reg : std_logic_vector(31 downto 0);
signal sdo_reg : std_logic_vector(31 downto 0);
signal captured : std_logic_vector(31 downto 0) := (others=>'0');
--***********************************************************************************
begin
--***********************************************************************************
process (clk, cs_n)
begin
if rising_edge(clk) then
if cs_n = '1' then
clock_count <= (others => '0');
write_cmd <= '0';
sdi_reg <= (others=>'0');
-- sdo_reg <= x"AAAAAAAA"; -- data to shift out
-- sdo <= '0';
else
-- count clock cycles received
clock_count <= clock_count + 1;
-- shift in data
sdi_reg <= sdi_reg(30 downto 0) & sdi;
if clock_count = 0 and sdi = WR_BIT then
write_cmd <= '1';
end if;
-- shift out data
-- if write_cmd = '0' and clock_count > 15 then
-- sdo_reg <= '0' & sdo_reg(31 downto 1);
-- sdo <= sdo_reg(0);
-- else
-- sdo <= '0';
-- end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clock_count = FULL_WIDTH and write_cmd = '1' then
captured <= sdi_reg;
end if;
end if;
end process;
reg0 <= captured;
process (clk)
begin
if rising_edge(clk) then
if cs_n = '1' then
sdo_reg <= x"AAAAAAAA";
sdo <= '0';
else
if write_cmd = '0' and clock_count > 12 then
sdo_reg <= '0' & sdo_reg(31 downto 1);
sdo <= sdo_reg(0);
else
sdo <= '0';
end if;
end if;
end if;
end process;
--process(clk, rst)
--begin
-- if rising_edge(clk) then
--
-- if rst = '1' then
-- recv_sm_reg <= HOLD_CMD;
-- commad <= (others=>'0');
-- cmd_valid <= '0';
--
-- else
--
-- --default
-- cmd_valid <= '0';
--
-- case recv_sm_reg is
-- when HOLD_CMD =>
-- if in_accept = '1' then
-- recv_sm_reg <= BYTE0_CMD;
-- end if;
--
-- when BYTE0_CMD => -- data
-- if in_val = '1' then
-- commad(7 downto 0) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE1_CMD;
-- end if;
-- when BYTE1_CMD =>
-- if in_val = '1' then
-- commad(15 downto 8) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE2_CMD;
-- end if;
-- when BYTE2_CMD =>
-- if in_val = '1' then
-- commad(23 downto 16) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE3_CMD;
-- end if;
-- when BYTE3_CMD =>
-- if in_val = '1' then
-- commad(31 downto 24) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE4_CMD;
-- end if;
--
-- when BYTE4_CMD => -- address
-- if in_val = '1' then
-- commad(39 downto 32) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE5_CMD;
-- end if;
-- when BYTE5_CMD =>
-- if in_val = '1' then
-- commad(47 downto 40) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE6_CMD;
-- end if;
-- when BYTE6_CMD =>
-- if in_val = '1' then
-- commad(55 downto 48) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE7_CMD;
-- end if;
-- when BYTE7_CMD =>
-- if in_val = '1' then
-- commad(63 downto 56) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE8_CMD;
-- end if;
--
-- when BYTE8_CMD => -- cmd
-- if in_val = '1' then
-- commad(71 downto 64) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE9_CMD;
-- end if;
-- when BYTE9_CMD =>
-- if in_val = '1' then
-- commad(79 downto 72) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE10_CMD;
-- end if;
-- when BYTE10_CMD =>
-- if in_val = '1' then
-- commad(87 downto 80) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE11_CMD;
-- end if;
-- when BYTE11_CMD =>
-- if in_val = '1' then
-- commad(95 downto 88) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE12_CMD;
-- end if;
--
-- when BYTE12_CMD => -- size
-- if in_val = '1' then
-- commad(103 downto 96) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE13_CMD;
-- end if;
-- when BYTE13_CMD =>
-- if in_val = '1' then
-- commad(111 downto 104) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE14_CMD;
-- end if;
-- when BYTE14_CMD =>
-- if in_val = '1' then
-- commad(119 downto 112) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE15_CMD;
-- end if;
-- when BYTE15_CMD =>
-- if in_val = '1' then
-- commad(127 downto 120) <= in_dat(7 downto 0);
-- recv_sm_reg <= HOLD_CMD;
-- cmd_valid <= '1';
-- end if;
--
-- when others =>
-- recv_sm_reg <= HOLD_CMD;
--
-- end case;
--
-- end if;
--
-- end if;
--end process;
--
-------------------------------------------------------------------------------------
-- Counter process
-------------------------------------------------------------------------------------
--process(clk, rst)
--begin
-- if rising_edge(clk) then
-- if rst = '1' then
--
-- else
--
--
-- end if;
-- end if;
--end process;
-------------------------------------------------------------------------------------
-- Component Instance
-------------------------------------------------------------------------------------
--inst0_vp680_nnn_lx130t:
--entity work.vp680_nnn_lx130t
--generic map (
-- DEBUG => FALSE,
-- ADDRESS => "00010111111"
--)
--port map (
-- gpio_led_8 => ,
-- sys_clk_p_8 => ,
-- sys_clk_n_8 => ,
-- sys_reset_n_8 => ,
-- pci_exp_rxn_8 => ,
-- pci_exp_rxp_8 => ,
-- pci_exp_txn_8 => ,
-- pci_exp_txp_8 => ,
-- fp_cp_8 => ,
-- host_if_i2c_scl_8 =>
--);
-------------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------------
--generate_debug:
--if (DEBUG_ENABLE = TRUE) generate
--begin
--
--end generate;
--generate_add_loop:
--for I in 0 to 7 generate
-- SUM(I) <= A(I) xor B(I) xor C(I);
-- C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
--end generate;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 4315c7f48365aec8c1f19a27a49178ca | 0.381266 | 3.496166 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd | 4 | 1,281 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
| gpl-2.0 | 7ddf4de845082505cb42d77b60e28f79 | 0.654957 | 4.053797 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug019/repro1.vhdl | 2 | 1,029 | entity repro1 is
end repro1;
architecture arch of repro1 is
type wf_el is record
t : time;
v : bit;
end record;
type wf_arr is array (natural range <>) of wf_el;
function get_wf (bv : bit_vector; p : time) return wf_arr is
variable res : wf_arr (bv'range);
variable t : time;
begin
t := 0 ns;
for i in bv'range loop
res (i) := (t => t, v => bv (i));
t := t + p;
end loop;
return res;
end get_wf;
procedure play_wf (signal s : out bit; wf : wf_arr; init : bit) is
begin
s <= init;
for i in wf'range loop
wait for wf (i).t;
s <= wf (i).v;
end loop;
wait;
end play_wf;
function get_str (l : natural; c : character) return string is
begin
return string'(1 to l => c);
end get_str;
signal o : bit;
begin
play_wf (o, get_wf (b"0110100", 2 ns), '1');
process
begin
for i in 1 to 8 loop
report get_str (32 + 4 * i, character'val (64 + i));
wait for 2 ns;
end loop;
wait;
end process;
end arch;
| gpl-2.0 | 3de27a7aa39aa2dc60ad899054eaa40b | 0.559767 | 3.080838 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd | 4 | 1,879 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee, ieee_proposed;
use ieee.math_real.all;
use ieee_proposed.energy_systems.all;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.thermal_systems.all;
entity diode is
port ( terminal p, m : electrical;
terminal j : thermal );
end entity diode;
----------------------------------------------------------------
architecture one of diode is
constant area : real := 1.0e-3;
constant Dn : real := 30.0; -- electron diffusion coefficient
constant Dp : real := 15.0; -- hole diffusion coefficient
constant np : real := 6.77e-5; -- minority charge density
constant pn : real := 6.77e-6; -- minority charge density
constant Ln : real := 5.47e-6; -- diffusion length for electrons
constant Lp : real := 12.25e-6; -- diffusion length for holes
quantity v across id through p to m;
quantity vt : voltage := 1.0; -- threshold voltage
quantity temp across power through j;
begin
vt == temp * K / Q;
id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0);
power == v * id;
end architecture one;
| gpl-2.0 | e730cdb0edae2cf43898e1260eaa49cb | 0.668441 | 3.728175 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/hdl/vhdl/coregen_comp_defs.vhd | 2 | 13,834 | -------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_3_2
-- Component declaration for blk_mem_gen_v8_3_2 pulled from the blk_mem_gen_v8_3_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_3_2
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_3_2
END coregen_comp_defs;
| gpl-3.0 | e16dfd9c030c3fb32e74586110c18104 | 0.429521 | 4.482826 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue382/demo.vhd | 1 | 1,243 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity demo is
port (
clk,reset: in std_logic;
load: in std_logic;
load_val: in unsigned(7 downto 0);
qout: out unsigned(7 downto 0);
is5: out std_logic
);
end entity;
architecture v1 of demo is
signal q: unsigned(7 downto 0);
begin
qout<=q;
-- is5<='1' when q=x"05" else '0';
process(clk, reset)
begin
if reset='1' then
q<=(others=>'0');
is5<='0';
elsif rising_edge(clk) then
is5<='0';
if q=x"04" then
is5<='1';
end if;
if load='1' then
q<=load_val;
if load_val=x"05" then
is5<='1';
end if;
else
q<=q+1;
end if;
end if;
end process;
end v1;
| gpl-2.0 | 7a124a29e706e9bbb644bda53ce9b8b1 | 0.329043 | 4.799228 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd | 4 | 1,837 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity volume_sensor is
port ( terminal flow, minus_ref : electrical;
signal clk, rst : in std_ulogic;
signal full : out std_ulogic );
end entity volume_sensor;
----------------------------------------------------------------
architecture structural of volume_sensor is
terminal minus_volume : electrical;
signal async_full, sync1_full : std_ulogic;
begin
int : entity work.inverting_integrator(structural)
port map ( input => flow, output => minus_volume, rst => rst );
comp : entity work.comparator(hysteresis)
port map ( plus_in => minus_volume, minus_in => minus_ref,
output => async_full );
sync1 : entity work.dff(behav)
port map ( d => async_full, clk => clk, q => sync1_full );
sync2 : entity work.dff(behav)
port map ( d => sync1_full, clk => clk, q => full );
end architecture structural;
| gpl-2.0 | ff4e917b76700fdde8d60f831c176089 | 0.655416 | 4.18451 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue328/repro.vhdl | 1 | 640 | entity repro is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Test case architecture
architecture func of repro is
signal s : std_logic := 'Z';
procedure write (signal s : inout std_logic) is
begin
null;
end write;
begin
b: block
port (s1 : out std_logic := '0');
port map (s1 => s);
begin
process
begin
wait for 2 ns;
s1 <= 'Z';
wait;
end process;
end block;
process
begin
write(s);
wait for 1 ns;
assert s = '0' severity failure;
wait for 2 ns;
assert s = 'Z' severity failure;
wait;
end process;
end func;
| gpl-2.0 | c28b6b9a4879e198f27e107b1718ac55 | 0.601563 | 3.350785 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2064.vhd | 4 | 2,411 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2064.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02064ent IS
END c07s02b04x00p01n02i02064ent;
ARCHITECTURE c07s02b04x00p01n02i02064arch OF c07s02b04x00p01n02i02064ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER := 0;
variable DISTV : DISTANCE := 1 A;
BEGIN
INTV := INTV + DISTV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02064 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02064arch;
| gpl-2.0 | 737484bec717474f52098a13acb2e796 | 0.577354 | 4.018333 | false | true | false | false |
tgingold/ghdl | testsuite/synth/slice01/slice01.vhdl | 1 | 578 | library ieee;
use ieee.std_logic_1164.all;
entity slice01 is
generic (w: natural := 4);
port (rst : std_logic;
clk : std_logic;
di : std_logic;
do : out std_logic_vector (w - 1 downto 0));
end slice01;
architecture behav of slice01 is
signal r : std_logic_vector (w - 1 downto 0);
begin
do <= r;
process(clk)
begin
if rising_edge (clk) then
if rst = '1' then
r <= (others => '0');
else
r (w - 2 downto 0) <= r (w - 1 downto 1);
r (w - 1) <= di;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 4af3ff79c201c66fb3f451af9f0ca6fd | 0.541522 | 3.124324 | false | false | false | false |
tgingold/ghdl | testsuite/synth/iassoc01/tb_iassoc02.vhdl | 1 | 510 | entity tb_iassoc02 is
end tb_iassoc02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc02 is
signal a : natural;
signal b : natural;
signal v : natural;
begin
dut: entity work.iassoc02
port map (v, a, b);
process
begin
v <= 5;
wait for 1 ns;
assert a = 6 severity failure;
assert b = 7 severity failure;
v <= 203;
wait for 1 ns;
assert a = 204 severity failure;
assert b = 205 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 136a16147651f05e737494a0fc9f2fed | 0.645098 | 3.445946 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue736/repro.vhdl | 1 | 474 | entity repro is
end repro;
architecture behav of repro is
signal a, i, r : bit;
begin
process (all)
begin
r <= a when i = '0' else not a;
end process;
process
begin
i <= '0';
a <= '1';
wait for 1 ns;
assert r = '1' severity failure;
i <= '0';
a <= '0';
wait for 1 ns;
assert r = '0' severity failure;
i <= '1';
a <= '1';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 9fc1d672c0c7a15327d1047cc2caa84c | 0.527426 | 3.139073 | false | false | false | false |
nickg/nvc | test/regress/attr1.vhd | 1 | 869 | entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
process is
variable x : integer;
variable y : my_int;
begin
assert integer'left = -2147483648;
x := integer'right;
wait for 1 ns;
assert x = 2147483647;
assert positive'left = 1;
assert natural'high = integer'high;
assert integer'ascending;
assert not my_int'ascending;
x := 0;
wait for 1 ns;
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
x := 1;
y := 1;
wait for 1 ns;
assert integer'leftof(x) = 0;
assert integer'rightof(x) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
assert my_int'base'left = 10;
wait;
end process;
end architecture;
| gpl-3.0 | 7352e3aca3038ab604006ad1ec0c2e1c | 0.547756 | 3.74569 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue332/irqc_pif.vhd | 1 | 4,206 | --========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end irqc_pif;
architecture rtl of irqc_pif is
signal p2c_i : t_p2c; -- internal version of output
signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
dout_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_IRR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
when C_ADDR_IER =>
dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
when C_ADDR_IPR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
when C_ADDR_IRQ2CPU_ALLOWED =>
dout_i(0) <= c2p.aro_irq2cpu_allowed;
when others =>
null;
end case;
end if;
end process p_read_reg;
dout <= dout_i;
-- Writing to registers that are not functionally manipulated
p_write_reg : process(clk, arst)
begin
if arst = '1' then
p2c_i.rw_ier <= (others => '0');
elsif rising_edge(clk) then
if cs = '1' and wr = '1' then
case to_integer(addr) is
when C_ADDR_IER =>
p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
-- Auxiliary write (below)
when others =>
null;
end case;
end if;
end if;
end process p_write_reg;
-- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
p_aux : process(wr, addr, din)
begin
-- Note that arst is not considered here, but must be considered in any clocked process in the core
-- Default - always to return to these values
p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_irq2cpu_ena <= '0';
p2c_i.awt_irq2cpu_disable <= '0';
if (cs = '1' and wr = '1') then
case to_integer(addr) is
when C_ADDR_ITR =>
p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_ICR =>
p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_IRQ2CPU_ENA =>
p2c_i.awt_irq2cpu_ena <= din(0);
when C_ADDR_IRQ2CPU_DISABLE =>
p2c_i.awt_irq2cpu_disable <= din(0);
when others =>
null;
end case;
end if;
end process p_aux;
end rtl;
| gpl-2.0 | 04ddd063a5044ee9efac496155851495 | 0.531859 | 3.597947 | false | false | false | false |
snow4life/PipelinedDLX | synthesis/DLX_synth.vhdl | 1 | 678,764 |
library IEEE;
use IEEE.std_logic_1164.all;
package CONV_PACK_DLX is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_DLX;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_0_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_0_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_0_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_15_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_15_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_15_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_14_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_14_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_14_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_13_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_13_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_13_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_12_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_12_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_12_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_11_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_11_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_11_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_10_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_10_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_10_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_9_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_9_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_9_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_8_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_8_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_8_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_7_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_7_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_7_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_6_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_6_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_6_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_5_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_5_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_5_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_4_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_4_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_4_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_3_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_3_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_3_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_2_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_2_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_2_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_1_DW01_add_0 is
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end RCA_GENERIC_N4_1_DW01_add_0;
architecture SYN_rpl of RCA_GENERIC_N4_1_DW01_add_0 is
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal carry_3_port, carry_2_port, carry_1_port : std_logic;
begin
U1_0 : ADDFX1 port map( A => A(0), B => B(0), CI => CI, CO => carry_1_port,
S => SUM(0));
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
SUM(4), S => SUM(3));
U1_1 : ADDFX1 port map( A => A(1), B => B(1), CI => carry_1_port, CO =>
carry_2_port, S => SUM(1));
U1_2 : ADDFX1 port map( A => A(2), B => B(2), CI => carry_2_port, CO =>
carry_3_port, S => SUM(2));
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32_DW_rbsh_0 is
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31 downto
0));
end SHIFTER_GENERIC_N32_DW_rbsh_0;
architecture SYN_mx2 of SHIFTER_GENERIC_N32_DW_rbsh_0 is
component BUFX2
port( A : in std_logic; Y : out std_logic);
end component;
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component MX2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
signal MR_int_1_31_port, MR_int_1_30_port, MR_int_1_29_port,
MR_int_1_28_port, MR_int_1_27_port, MR_int_1_26_port, MR_int_1_25_port,
MR_int_1_24_port, MR_int_1_23_port, MR_int_1_22_port, MR_int_1_21_port,
MR_int_1_20_port, MR_int_1_19_port, MR_int_1_18_port, MR_int_1_17_port,
MR_int_1_16_port, MR_int_1_15_port, MR_int_1_14_port, MR_int_1_13_port,
MR_int_1_12_port, MR_int_1_11_port, MR_int_1_10_port, MR_int_1_9_port,
MR_int_1_8_port, MR_int_1_7_port, MR_int_1_6_port, MR_int_1_5_port,
MR_int_1_4_port, MR_int_1_3_port, MR_int_1_2_port, MR_int_1_1_port,
MR_int_1_0_port, MR_int_2_31_port, MR_int_2_30_port, MR_int_2_29_port,
MR_int_2_28_port, MR_int_2_27_port, MR_int_2_26_port, MR_int_2_25_port,
MR_int_2_24_port, MR_int_2_23_port, MR_int_2_22_port, MR_int_2_21_port,
MR_int_2_20_port, MR_int_2_19_port, MR_int_2_18_port, MR_int_2_17_port,
MR_int_2_16_port, MR_int_2_15_port, MR_int_2_14_port, MR_int_2_13_port,
MR_int_2_12_port, MR_int_2_11_port, MR_int_2_10_port, MR_int_2_9_port,
MR_int_2_8_port, MR_int_2_7_port, MR_int_2_6_port, MR_int_2_5_port,
MR_int_2_4_port, MR_int_2_3_port, MR_int_2_2_port, MR_int_2_1_port,
MR_int_2_0_port, MR_int_3_31_port, MR_int_3_30_port, MR_int_3_29_port,
MR_int_3_28_port, MR_int_3_27_port, MR_int_3_26_port, MR_int_3_25_port,
MR_int_3_24_port, MR_int_3_23_port, MR_int_3_22_port, MR_int_3_21_port,
MR_int_3_20_port, MR_int_3_19_port, MR_int_3_18_port, MR_int_3_17_port,
MR_int_3_16_port, MR_int_3_15_port, MR_int_3_14_port, MR_int_3_13_port,
MR_int_3_12_port, MR_int_3_11_port, MR_int_3_10_port, MR_int_3_9_port,
MR_int_3_8_port, MR_int_3_7_port, MR_int_3_6_port, MR_int_3_5_port,
MR_int_3_4_port, MR_int_3_3_port, MR_int_3_2_port, MR_int_3_1_port,
MR_int_3_0_port, MR_int_4_31_port, MR_int_4_30_port, MR_int_4_29_port,
MR_int_4_28_port, MR_int_4_27_port, MR_int_4_26_port, MR_int_4_25_port,
MR_int_4_24_port, MR_int_4_23_port, MR_int_4_22_port, MR_int_4_21_port,
MR_int_4_20_port, MR_int_4_19_port, MR_int_4_18_port, MR_int_4_17_port,
MR_int_4_16_port, MR_int_4_15_port, MR_int_4_14_port, MR_int_4_13_port,
MR_int_4_12_port, MR_int_4_11_port, MR_int_4_10_port, MR_int_4_9_port,
MR_int_4_8_port, MR_int_4_7_port, MR_int_4_6_port, MR_int_4_5_port,
MR_int_4_4_port, MR_int_4_3_port, MR_int_4_2_port, MR_int_4_1_port,
MR_int_4_0_port, n1, n2, n3 : std_logic;
begin
M1_3_31_0 : MX2XL port map( A => MR_int_3_31_port, B => MR_int_3_7_port, S0
=> SH(3), Y => MR_int_4_31_port);
M1_3_15_0 : MX2XL port map( A => MR_int_3_15_port, B => MR_int_3_23_port, S0
=> SH(3), Y => MR_int_4_15_port);
M1_3_30_0 : MX2XL port map( A => MR_int_3_30_port, B => MR_int_3_6_port, S0
=> SH(3), Y => MR_int_4_30_port);
M1_3_14_0 : MX2XL port map( A => MR_int_3_14_port, B => MR_int_3_22_port, S0
=> SH(3), Y => MR_int_4_14_port);
M1_3_29_0 : MX2XL port map( A => MR_int_3_29_port, B => MR_int_3_5_port, S0
=> SH(3), Y => MR_int_4_29_port);
M1_3_13_0 : MX2XL port map( A => MR_int_3_13_port, B => MR_int_3_21_port, S0
=> SH(3), Y => MR_int_4_13_port);
M1_3_28_0 : MX2XL port map( A => MR_int_3_28_port, B => MR_int_3_4_port, S0
=> SH(3), Y => MR_int_4_28_port);
M1_3_12_0 : MX2XL port map( A => MR_int_3_12_port, B => MR_int_3_20_port, S0
=> SH(3), Y => MR_int_4_12_port);
M1_3_27_0 : MX2XL port map( A => MR_int_3_27_port, B => MR_int_3_3_port, S0
=> SH(3), Y => MR_int_4_27_port);
M1_3_11_0 : MX2XL port map( A => MR_int_3_11_port, B => MR_int_3_19_port, S0
=> SH(3), Y => MR_int_4_11_port);
M1_3_26_0 : MX2XL port map( A => MR_int_3_26_port, B => MR_int_3_2_port, S0
=> SH(3), Y => MR_int_4_26_port);
M1_3_10_0 : MX2XL port map( A => MR_int_3_10_port, B => MR_int_3_18_port, S0
=> SH(3), Y => MR_int_4_10_port);
M1_3_25_0 : MX2XL port map( A => MR_int_3_25_port, B => MR_int_3_1_port, S0
=> SH(3), Y => MR_int_4_25_port);
M1_3_9_0 : MX2XL port map( A => MR_int_3_9_port, B => MR_int_3_17_port, S0
=> SH(3), Y => MR_int_4_9_port);
M1_3_24_0 : MX2XL port map( A => MR_int_3_24_port, B => MR_int_3_0_port, S0
=> SH(3), Y => MR_int_4_24_port);
M1_3_8_0 : MX2XL port map( A => MR_int_3_8_port, B => MR_int_3_16_port, S0
=> SH(3), Y => MR_int_4_8_port);
M1_3_23_0 : MX2XL port map( A => MR_int_3_23_port, B => MR_int_3_31_port, S0
=> SH(3), Y => MR_int_4_23_port);
M1_3_7 : MX2XL port map( A => MR_int_3_7_port, B => MR_int_3_15_port, S0 =>
SH(3), Y => MR_int_4_7_port);
M1_3_22_0 : MX2XL port map( A => MR_int_3_22_port, B => MR_int_3_30_port, S0
=> SH(3), Y => MR_int_4_22_port);
M1_3_6 : MX2XL port map( A => MR_int_3_6_port, B => MR_int_3_14_port, S0 =>
SH(3), Y => MR_int_4_6_port);
M1_3_21_0 : MX2XL port map( A => MR_int_3_21_port, B => MR_int_3_29_port, S0
=> SH(3), Y => MR_int_4_21_port);
M1_3_5 : MX2XL port map( A => MR_int_3_5_port, B => MR_int_3_13_port, S0 =>
SH(3), Y => MR_int_4_5_port);
M1_3_20_0 : MX2XL port map( A => MR_int_3_20_port, B => MR_int_3_28_port, S0
=> SH(3), Y => MR_int_4_20_port);
M1_3_4 : MX2XL port map( A => MR_int_3_4_port, B => MR_int_3_12_port, S0 =>
SH(3), Y => MR_int_4_4_port);
M1_3_19_0 : MX2XL port map( A => MR_int_3_19_port, B => MR_int_3_27_port, S0
=> SH(3), Y => MR_int_4_19_port);
M1_3_3 : MX2XL port map( A => MR_int_3_3_port, B => MR_int_3_11_port, S0 =>
SH(3), Y => MR_int_4_3_port);
M1_3_18_0 : MX2XL port map( A => MR_int_3_18_port, B => MR_int_3_26_port, S0
=> SH(3), Y => MR_int_4_18_port);
M1_3_2 : MX2XL port map( A => MR_int_3_2_port, B => MR_int_3_10_port, S0 =>
SH(3), Y => MR_int_4_2_port);
M1_3_17_0 : MX2XL port map( A => MR_int_3_17_port, B => MR_int_3_25_port, S0
=> SH(3), Y => MR_int_4_17_port);
M1_3_1 : MX2XL port map( A => MR_int_3_1_port, B => MR_int_3_9_port, S0 =>
SH(3), Y => MR_int_4_1_port);
M1_3_16_0 : MX2XL port map( A => MR_int_3_16_port, B => MR_int_3_24_port, S0
=> SH(3), Y => MR_int_4_16_port);
M1_3_0 : MX2XL port map( A => MR_int_3_0_port, B => MR_int_3_8_port, S0 =>
SH(3), Y => MR_int_4_0_port);
M1_2_31_0 : MX2XL port map( A => MR_int_2_31_port, B => MR_int_2_3_port, S0
=> SH(2), Y => MR_int_3_31_port);
M1_2_7_0 : MX2XL port map( A => MR_int_2_7_port, B => MR_int_2_11_port, S0
=> SH(2), Y => MR_int_3_7_port);
M1_2_15_0 : MX2XL port map( A => MR_int_2_15_port, B => MR_int_2_19_port, S0
=> SH(2), Y => MR_int_3_15_port);
M1_2_23_0 : MX2XL port map( A => MR_int_2_23_port, B => MR_int_2_27_port, S0
=> SH(2), Y => MR_int_3_23_port);
M1_2_30_0 : MX2XL port map( A => MR_int_2_30_port, B => MR_int_2_2_port, S0
=> SH(2), Y => MR_int_3_30_port);
M1_2_6_0 : MX2XL port map( A => MR_int_2_6_port, B => MR_int_2_10_port, S0
=> SH(2), Y => MR_int_3_6_port);
M1_2_14_0 : MX2XL port map( A => MR_int_2_14_port, B => MR_int_2_18_port, S0
=> SH(2), Y => MR_int_3_14_port);
M1_2_22_0 : MX2XL port map( A => MR_int_2_22_port, B => MR_int_2_26_port, S0
=> SH(2), Y => MR_int_3_22_port);
M1_2_29_0 : MX2XL port map( A => MR_int_2_29_port, B => MR_int_2_1_port, S0
=> SH(2), Y => MR_int_3_29_port);
M1_2_5_0 : MX2XL port map( A => MR_int_2_5_port, B => MR_int_2_9_port, S0 =>
SH(2), Y => MR_int_3_5_port);
M1_2_13_0 : MX2XL port map( A => MR_int_2_13_port, B => MR_int_2_17_port, S0
=> SH(2), Y => MR_int_3_13_port);
M1_2_21_0 : MX2XL port map( A => MR_int_2_21_port, B => MR_int_2_25_port, S0
=> SH(2), Y => MR_int_3_21_port);
M1_2_28_0 : MX2XL port map( A => MR_int_2_28_port, B => MR_int_2_0_port, S0
=> SH(2), Y => MR_int_3_28_port);
M1_2_4_0 : MX2XL port map( A => MR_int_2_4_port, B => MR_int_2_8_port, S0 =>
SH(2), Y => MR_int_3_4_port);
M1_2_12_0 : MX2XL port map( A => MR_int_2_12_port, B => MR_int_2_16_port, S0
=> SH(2), Y => MR_int_3_12_port);
M1_2_20_0 : MX2XL port map( A => MR_int_2_20_port, B => MR_int_2_24_port, S0
=> SH(2), Y => MR_int_3_20_port);
M1_2_27_0 : MX2XL port map( A => MR_int_2_27_port, B => MR_int_2_31_port, S0
=> SH(2), Y => MR_int_3_27_port);
M1_2_3 : MX2XL port map( A => MR_int_2_3_port, B => MR_int_2_7_port, S0 =>
SH(2), Y => MR_int_3_3_port);
M1_2_11_0 : MX2XL port map( A => MR_int_2_11_port, B => MR_int_2_15_port, S0
=> SH(2), Y => MR_int_3_11_port);
M1_2_19_0 : MX2XL port map( A => MR_int_2_19_port, B => MR_int_2_23_port, S0
=> SH(2), Y => MR_int_3_19_port);
M1_2_26_0 : MX2XL port map( A => MR_int_2_26_port, B => MR_int_2_30_port, S0
=> SH(2), Y => MR_int_3_26_port);
M1_2_2 : MX2XL port map( A => MR_int_2_2_port, B => MR_int_2_6_port, S0 =>
SH(2), Y => MR_int_3_2_port);
M1_2_10_0 : MX2XL port map( A => MR_int_2_10_port, B => MR_int_2_14_port, S0
=> SH(2), Y => MR_int_3_10_port);
M1_2_18_0 : MX2XL port map( A => MR_int_2_18_port, B => MR_int_2_22_port, S0
=> SH(2), Y => MR_int_3_18_port);
M1_2_25_0 : MX2XL port map( A => MR_int_2_25_port, B => MR_int_2_29_port, S0
=> SH(2), Y => MR_int_3_25_port);
M1_2_1 : MX2XL port map( A => MR_int_2_1_port, B => MR_int_2_5_port, S0 =>
SH(2), Y => MR_int_3_1_port);
M1_2_9_0 : MX2XL port map( A => MR_int_2_9_port, B => MR_int_2_13_port, S0
=> SH(2), Y => MR_int_3_9_port);
M1_2_17_0 : MX2XL port map( A => MR_int_2_17_port, B => MR_int_2_21_port, S0
=> SH(2), Y => MR_int_3_17_port);
M1_2_24_0 : MX2XL port map( A => MR_int_2_24_port, B => MR_int_2_28_port, S0
=> SH(2), Y => MR_int_3_24_port);
M1_2_0 : MX2XL port map( A => MR_int_2_0_port, B => MR_int_2_4_port, S0 =>
SH(2), Y => MR_int_3_0_port);
M1_2_8_0 : MX2XL port map( A => MR_int_2_8_port, B => MR_int_2_12_port, S0
=> SH(2), Y => MR_int_3_8_port);
M1_2_16_0 : MX2XL port map( A => MR_int_2_16_port, B => MR_int_2_20_port, S0
=> SH(2), Y => MR_int_3_16_port);
M1_0_31_0 : MX2XL port map( A => A(31), B => A(0), S0 => SH(0), Y =>
MR_int_1_31_port);
M1_0_1_0 : MX2XL port map( A => A(1), B => A(2), S0 => SH(0), Y =>
MR_int_1_1_port);
M1_0_3_0 : MX2XL port map( A => A(3), B => A(4), S0 => SH(0), Y =>
MR_int_1_3_port);
M1_0_5_0 : MX2XL port map( A => A(5), B => A(6), S0 => SH(0), Y =>
MR_int_1_5_port);
M1_0_7_0 : MX2XL port map( A => A(7), B => A(8), S0 => SH(0), Y =>
MR_int_1_7_port);
M1_0_9_0 : MX2XL port map( A => A(9), B => A(10), S0 => SH(0), Y =>
MR_int_1_9_port);
M1_0_11_0 : MX2XL port map( A => A(11), B => A(12), S0 => SH(0), Y =>
MR_int_1_11_port);
M1_0_13_0 : MX2XL port map( A => A(13), B => A(14), S0 => SH(0), Y =>
MR_int_1_13_port);
M1_0_15_0 : MX2XL port map( A => A(15), B => A(16), S0 => SH(0), Y =>
MR_int_1_15_port);
M1_0_17_0 : MX2XL port map( A => A(17), B => A(18), S0 => SH(0), Y =>
MR_int_1_17_port);
M1_0_19_0 : MX2XL port map( A => A(19), B => A(20), S0 => SH(0), Y =>
MR_int_1_19_port);
M1_0_21_0 : MX2XL port map( A => A(21), B => A(22), S0 => SH(0), Y =>
MR_int_1_21_port);
M1_0_23_0 : MX2XL port map( A => A(23), B => A(24), S0 => SH(0), Y =>
MR_int_1_23_port);
M1_0_25_0 : MX2XL port map( A => A(25), B => A(26), S0 => SH(0), Y =>
MR_int_1_25_port);
M1_0_27_0 : MX2XL port map( A => A(27), B => A(28), S0 => SH(0), Y =>
MR_int_1_27_port);
M1_0_29_0 : MX2XL port map( A => A(29), B => A(30), S0 => SH(0), Y =>
MR_int_1_29_port);
M1_0_30_0 : MX2XL port map( A => A(30), B => A(31), S0 => SH(0), Y =>
MR_int_1_30_port);
M1_0_0 : MX2XL port map( A => A(0), B => A(1), S0 => SH(0), Y =>
MR_int_1_0_port);
M1_0_2_0 : MX2XL port map( A => A(2), B => A(3), S0 => SH(0), Y =>
MR_int_1_2_port);
M1_0_4_0 : MX2XL port map( A => A(4), B => A(5), S0 => SH(0), Y =>
MR_int_1_4_port);
M1_0_6_0 : MX2XL port map( A => A(6), B => A(7), S0 => SH(0), Y =>
MR_int_1_6_port);
M1_0_8_0 : MX2XL port map( A => A(8), B => A(9), S0 => SH(0), Y =>
MR_int_1_8_port);
M1_0_10_0 : MX2XL port map( A => A(10), B => A(11), S0 => SH(0), Y =>
MR_int_1_10_port);
M1_0_12_0 : MX2XL port map( A => A(12), B => A(13), S0 => SH(0), Y =>
MR_int_1_12_port);
M1_0_14_0 : MX2XL port map( A => A(14), B => A(15), S0 => SH(0), Y =>
MR_int_1_14_port);
M1_0_16_0 : MX2XL port map( A => A(16), B => A(17), S0 => SH(0), Y =>
MR_int_1_16_port);
M1_0_18_0 : MX2XL port map( A => A(18), B => A(19), S0 => SH(0), Y =>
MR_int_1_18_port);
M1_0_20_0 : MX2XL port map( A => A(20), B => A(21), S0 => SH(0), Y =>
MR_int_1_20_port);
M1_0_22_0 : MX2XL port map( A => A(22), B => A(23), S0 => SH(0), Y =>
MR_int_1_22_port);
M1_0_24_0 : MX2XL port map( A => A(24), B => A(25), S0 => SH(0), Y =>
MR_int_1_24_port);
M1_0_26_0 : MX2XL port map( A => A(26), B => A(27), S0 => SH(0), Y =>
MR_int_1_26_port);
M1_0_28_0 : MX2XL port map( A => A(28), B => A(29), S0 => SH(0), Y =>
MR_int_1_28_port);
M1_1_31_0 : MX2XL port map( A => MR_int_1_31_port, B => MR_int_1_1_port, S0
=> SH(1), Y => MR_int_2_31_port);
M1_1_3_0 : MX2XL port map( A => MR_int_1_3_port, B => MR_int_1_5_port, S0 =>
SH(1), Y => MR_int_2_3_port);
M1_1_7_0 : MX2XL port map( A => MR_int_1_7_port, B => MR_int_1_9_port, S0 =>
SH(1), Y => MR_int_2_7_port);
M1_1_11_0 : MX2XL port map( A => MR_int_1_11_port, B => MR_int_1_13_port, S0
=> SH(1), Y => MR_int_2_11_port);
M1_1_15_0 : MX2XL port map( A => MR_int_1_15_port, B => MR_int_1_17_port, S0
=> SH(1), Y => MR_int_2_15_port);
M1_1_19_0 : MX2XL port map( A => MR_int_1_19_port, B => MR_int_1_21_port, S0
=> SH(1), Y => MR_int_2_19_port);
M1_1_23_0 : MX2XL port map( A => MR_int_1_23_port, B => MR_int_1_25_port, S0
=> SH(1), Y => MR_int_2_23_port);
M1_1_27_0 : MX2XL port map( A => MR_int_1_27_port, B => MR_int_1_29_port, S0
=> SH(1), Y => MR_int_2_27_port);
M1_1_30_0 : MX2XL port map( A => MR_int_1_30_port, B => MR_int_1_0_port, S0
=> SH(1), Y => MR_int_2_30_port);
M1_1_2_0 : MX2XL port map( A => MR_int_1_2_port, B => MR_int_1_4_port, S0 =>
SH(1), Y => MR_int_2_2_port);
M1_1_6_0 : MX2XL port map( A => MR_int_1_6_port, B => MR_int_1_8_port, S0 =>
SH(1), Y => MR_int_2_6_port);
M1_1_10_0 : MX2XL port map( A => MR_int_1_10_port, B => MR_int_1_12_port, S0
=> SH(1), Y => MR_int_2_10_port);
M1_1_14_0 : MX2XL port map( A => MR_int_1_14_port, B => MR_int_1_16_port, S0
=> SH(1), Y => MR_int_2_14_port);
M1_1_18_0 : MX2XL port map( A => MR_int_1_18_port, B => MR_int_1_20_port, S0
=> SH(1), Y => MR_int_2_18_port);
M1_1_22_0 : MX2XL port map( A => MR_int_1_22_port, B => MR_int_1_24_port, S0
=> SH(1), Y => MR_int_2_22_port);
M1_1_26_0 : MX2XL port map( A => MR_int_1_26_port, B => MR_int_1_28_port, S0
=> SH(1), Y => MR_int_2_26_port);
M1_1_29_0 : MX2XL port map( A => MR_int_1_29_port, B => MR_int_1_31_port, S0
=> SH(1), Y => MR_int_2_29_port);
M1_1_1 : MX2XL port map( A => MR_int_1_1_port, B => MR_int_1_3_port, S0 =>
SH(1), Y => MR_int_2_1_port);
M1_1_5_0 : MX2XL port map( A => MR_int_1_5_port, B => MR_int_1_7_port, S0 =>
SH(1), Y => MR_int_2_5_port);
M1_1_9_0 : MX2XL port map( A => MR_int_1_9_port, B => MR_int_1_11_port, S0
=> SH(1), Y => MR_int_2_9_port);
M1_1_13_0 : MX2XL port map( A => MR_int_1_13_port, B => MR_int_1_15_port, S0
=> SH(1), Y => MR_int_2_13_port);
M1_1_17_0 : MX2XL port map( A => MR_int_1_17_port, B => MR_int_1_19_port, S0
=> SH(1), Y => MR_int_2_17_port);
M1_1_21_0 : MX2XL port map( A => MR_int_1_21_port, B => MR_int_1_23_port, S0
=> SH(1), Y => MR_int_2_21_port);
M1_1_25_0 : MX2XL port map( A => MR_int_1_25_port, B => MR_int_1_27_port, S0
=> SH(1), Y => MR_int_2_25_port);
M1_1_28_0 : MX2XL port map( A => MR_int_1_28_port, B => MR_int_1_30_port, S0
=> SH(1), Y => MR_int_2_28_port);
M1_1_0 : MX2XL port map( A => MR_int_1_0_port, B => MR_int_1_2_port, S0 =>
SH(1), Y => MR_int_2_0_port);
M1_1_4_0 : MX2XL port map( A => MR_int_1_4_port, B => MR_int_1_6_port, S0 =>
SH(1), Y => MR_int_2_4_port);
M1_1_8_0 : MX2XL port map( A => MR_int_1_8_port, B => MR_int_1_10_port, S0
=> SH(1), Y => MR_int_2_8_port);
M1_1_12_0 : MX2XL port map( A => MR_int_1_12_port, B => MR_int_1_14_port, S0
=> SH(1), Y => MR_int_2_12_port);
M1_1_16_0 : MX2XL port map( A => MR_int_1_16_port, B => MR_int_1_18_port, S0
=> SH(1), Y => MR_int_2_16_port);
M1_1_20_0 : MX2XL port map( A => MR_int_1_20_port, B => MR_int_1_22_port, S0
=> SH(1), Y => MR_int_2_20_port);
M1_1_24_0 : MX2XL port map( A => MR_int_1_24_port, B => MR_int_1_26_port, S0
=> SH(1), Y => MR_int_2_24_port);
M1_4_31 : MX2X1 port map( A => MR_int_4_31_port, B => MR_int_4_15_port, S0
=> n3, Y => B(31));
M1_4_30 : MX2X1 port map( A => MR_int_4_30_port, B => MR_int_4_14_port, S0
=> n3, Y => B(30));
M1_4_29 : MX2X1 port map( A => MR_int_4_29_port, B => MR_int_4_13_port, S0
=> n3, Y => B(29));
M1_4_28 : MX2X1 port map( A => MR_int_4_28_port, B => MR_int_4_12_port, S0
=> n3, Y => B(28));
M1_4_27 : MX2X1 port map( A => MR_int_4_27_port, B => MR_int_4_11_port, S0
=> n3, Y => B(27));
M1_4_26 : MX2X1 port map( A => MR_int_4_26_port, B => MR_int_4_10_port, S0
=> n3, Y => B(26));
M1_4_25 : MX2X1 port map( A => MR_int_4_25_port, B => MR_int_4_9_port, S0 =>
n2, Y => B(25));
M1_4_24 : MX2X1 port map( A => MR_int_4_24_port, B => MR_int_4_8_port, S0 =>
n2, Y => B(24));
M1_4_23 : MX2X1 port map( A => MR_int_4_23_port, B => MR_int_4_7_port, S0 =>
n2, Y => B(23));
M1_4_22 : MX2X1 port map( A => MR_int_4_22_port, B => MR_int_4_6_port, S0 =>
n2, Y => B(22));
M1_4_21 : MX2X1 port map( A => MR_int_4_21_port, B => MR_int_4_5_port, S0 =>
n2, Y => B(21));
M1_4_20 : MX2X1 port map( A => MR_int_4_20_port, B => MR_int_4_4_port, S0 =>
n2, Y => B(20));
M1_4_19 : MX2X1 port map( A => MR_int_4_19_port, B => MR_int_4_3_port, S0 =>
n2, Y => B(19));
M1_4_18 : MX2X1 port map( A => MR_int_4_18_port, B => MR_int_4_2_port, S0 =>
n2, Y => B(18));
M1_4_17 : MX2X1 port map( A => MR_int_4_17_port, B => MR_int_4_1_port, S0 =>
n2, Y => B(17));
M1_4_16 : MX2X1 port map( A => MR_int_4_16_port, B => MR_int_4_0_port, S0 =>
n2, Y => B(16));
M1_4_15 : MX2X1 port map( A => MR_int_4_15_port, B => MR_int_4_31_port, S0
=> n2, Y => B(15));
M1_4_14 : MX2X1 port map( A => MR_int_4_14_port, B => MR_int_4_30_port, S0
=> n2, Y => B(14));
M1_4_13 : MX2X1 port map( A => MR_int_4_13_port, B => MR_int_4_29_port, S0
=> n2, Y => B(13));
M1_4_12 : MX2X1 port map( A => MR_int_4_12_port, B => MR_int_4_28_port, S0
=> n1, Y => B(12));
M1_4_11 : MX2X1 port map( A => MR_int_4_11_port, B => MR_int_4_27_port, S0
=> n1, Y => B(11));
M1_4_10 : MX2X1 port map( A => MR_int_4_10_port, B => MR_int_4_26_port, S0
=> n1, Y => B(10));
M1_4_9 : MX2X1 port map( A => MR_int_4_9_port, B => MR_int_4_25_port, S0 =>
n1, Y => B(9));
M1_4_8 : MX2X1 port map( A => MR_int_4_8_port, B => MR_int_4_24_port, S0 =>
n1, Y => B(8));
M1_4_7 : MX2X1 port map( A => MR_int_4_7_port, B => MR_int_4_23_port, S0 =>
n1, Y => B(7));
M1_4_6 : MX2X1 port map( A => MR_int_4_6_port, B => MR_int_4_22_port, S0 =>
n1, Y => B(6));
M1_4_5 : MX2X1 port map( A => MR_int_4_5_port, B => MR_int_4_21_port, S0 =>
n1, Y => B(5));
M1_4_3 : MX2X1 port map( A => MR_int_4_3_port, B => MR_int_4_19_port, S0 =>
n1, Y => B(3));
M1_4_4 : MX2X1 port map( A => MR_int_4_4_port, B => MR_int_4_20_port, S0 =>
n1, Y => B(4));
M1_4_2 : MX2X1 port map( A => MR_int_4_2_port, B => MR_int_4_18_port, S0 =>
n1, Y => B(2));
M1_4_1 : MX2X1 port map( A => MR_int_4_1_port, B => MR_int_4_17_port, S0 =>
n1, Y => B(1));
M1_4_0 : MX2X1 port map( A => MR_int_4_0_port, B => MR_int_4_16_port, S0 =>
n1, Y => B(0));
U2 : BUFX2 port map( A => SH(4), Y => n1);
U3 : BUFX2 port map( A => SH(4), Y => n2);
U4 : BUFX2 port map( A => SH(4), Y => n3);
end SYN_mx2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32_DW_lbsh_0 is
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31 downto
0));
end SHIFTER_GENERIC_N32_DW_lbsh_0;
architecture SYN_mx2 of SHIFTER_GENERIC_N32_DW_lbsh_0 is
component BUFX2
port( A : in std_logic; Y : out std_logic);
end component;
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component MX2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
signal ML_int_1_31_port, ML_int_1_30_port, ML_int_1_29_port,
ML_int_1_28_port, ML_int_1_27_port, ML_int_1_26_port, ML_int_1_25_port,
ML_int_1_24_port, ML_int_1_23_port, ML_int_1_22_port, ML_int_1_21_port,
ML_int_1_20_port, ML_int_1_19_port, ML_int_1_18_port, ML_int_1_17_port,
ML_int_1_16_port, ML_int_1_15_port, ML_int_1_14_port, ML_int_1_13_port,
ML_int_1_12_port, ML_int_1_11_port, ML_int_1_10_port, ML_int_1_9_port,
ML_int_1_8_port, ML_int_1_7_port, ML_int_1_6_port, ML_int_1_5_port,
ML_int_1_4_port, ML_int_1_3_port, ML_int_1_2_port, ML_int_1_1_port,
ML_int_1_0_port, ML_int_2_31_port, ML_int_2_30_port, ML_int_2_29_port,
ML_int_2_28_port, ML_int_2_27_port, ML_int_2_26_port, ML_int_2_25_port,
ML_int_2_24_port, ML_int_2_23_port, ML_int_2_22_port, ML_int_2_21_port,
ML_int_2_20_port, ML_int_2_19_port, ML_int_2_18_port, ML_int_2_17_port,
ML_int_2_16_port, ML_int_2_15_port, ML_int_2_14_port, ML_int_2_13_port,
ML_int_2_12_port, ML_int_2_11_port, ML_int_2_10_port, ML_int_2_9_port,
ML_int_2_8_port, ML_int_2_7_port, ML_int_2_6_port, ML_int_2_5_port,
ML_int_2_4_port, ML_int_2_3_port, ML_int_2_2_port, ML_int_2_1_port,
ML_int_2_0_port, ML_int_3_31_port, ML_int_3_30_port, ML_int_3_29_port,
ML_int_3_28_port, ML_int_3_27_port, ML_int_3_26_port, ML_int_3_25_port,
ML_int_3_24_port, ML_int_3_23_port, ML_int_3_22_port, ML_int_3_21_port,
ML_int_3_20_port, ML_int_3_19_port, ML_int_3_18_port, ML_int_3_17_port,
ML_int_3_16_port, ML_int_3_15_port, ML_int_3_14_port, ML_int_3_13_port,
ML_int_3_12_port, ML_int_3_11_port, ML_int_3_10_port, ML_int_3_9_port,
ML_int_3_8_port, ML_int_3_7_port, ML_int_3_6_port, ML_int_3_5_port,
ML_int_3_4_port, ML_int_3_3_port, ML_int_3_2_port, ML_int_3_1_port,
ML_int_3_0_port, ML_int_4_31_port, ML_int_4_30_port, ML_int_4_29_port,
ML_int_4_28_port, ML_int_4_27_port, ML_int_4_26_port, ML_int_4_25_port,
ML_int_4_24_port, ML_int_4_23_port, ML_int_4_22_port, ML_int_4_21_port,
ML_int_4_20_port, ML_int_4_19_port, ML_int_4_18_port, ML_int_4_17_port,
ML_int_4_16_port, ML_int_4_15_port, ML_int_4_14_port, ML_int_4_13_port,
ML_int_4_12_port, ML_int_4_11_port, ML_int_4_10_port, ML_int_4_9_port,
ML_int_4_8_port, ML_int_4_7_port, ML_int_4_6_port, ML_int_4_5_port,
ML_int_4_4_port, ML_int_4_3_port, ML_int_4_2_port, ML_int_4_1_port,
ML_int_4_0_port, n1, n2, n3 : std_logic;
begin
M1_3_31 : MX2XL port map( A => ML_int_3_31_port, B => ML_int_3_23_port, S0
=> SH(3), Y => ML_int_4_31_port);
M1_3_15 : MX2XL port map( A => ML_int_3_15_port, B => ML_int_3_7_port, S0 =>
SH(3), Y => ML_int_4_15_port);
M1_3_30 : MX2XL port map( A => ML_int_3_30_port, B => ML_int_3_22_port, S0
=> SH(3), Y => ML_int_4_30_port);
M1_3_14 : MX2XL port map( A => ML_int_3_14_port, B => ML_int_3_6_port, S0 =>
SH(3), Y => ML_int_4_14_port);
M1_3_29 : MX2XL port map( A => ML_int_3_29_port, B => ML_int_3_21_port, S0
=> SH(3), Y => ML_int_4_29_port);
M1_3_13 : MX2XL port map( A => ML_int_3_13_port, B => ML_int_3_5_port, S0 =>
SH(3), Y => ML_int_4_13_port);
M1_3_28 : MX2XL port map( A => ML_int_3_28_port, B => ML_int_3_20_port, S0
=> SH(3), Y => ML_int_4_28_port);
M1_3_12 : MX2XL port map( A => ML_int_3_12_port, B => ML_int_3_4_port, S0 =>
SH(3), Y => ML_int_4_12_port);
M1_3_27 : MX2XL port map( A => ML_int_3_27_port, B => ML_int_3_19_port, S0
=> SH(3), Y => ML_int_4_27_port);
M1_3_11 : MX2XL port map( A => ML_int_3_11_port, B => ML_int_3_3_port, S0 =>
SH(3), Y => ML_int_4_11_port);
M1_3_26 : MX2XL port map( A => ML_int_3_26_port, B => ML_int_3_18_port, S0
=> SH(3), Y => ML_int_4_26_port);
M1_3_10 : MX2XL port map( A => ML_int_3_10_port, B => ML_int_3_2_port, S0 =>
SH(3), Y => ML_int_4_10_port);
M1_3_25 : MX2XL port map( A => ML_int_3_25_port, B => ML_int_3_17_port, S0
=> SH(3), Y => ML_int_4_25_port);
M1_3_9 : MX2XL port map( A => ML_int_3_9_port, B => ML_int_3_1_port, S0 =>
SH(3), Y => ML_int_4_9_port);
M1_3_24 : MX2XL port map( A => ML_int_3_24_port, B => ML_int_3_16_port, S0
=> SH(3), Y => ML_int_4_24_port);
M1_3_8 : MX2XL port map( A => ML_int_3_8_port, B => ML_int_3_0_port, S0 =>
SH(3), Y => ML_int_4_8_port);
M1_3_23 : MX2XL port map( A => ML_int_3_23_port, B => ML_int_3_15_port, S0
=> SH(3), Y => ML_int_4_23_port);
M0_3_7 : MX2XL port map( A => ML_int_3_7_port, B => ML_int_3_31_port, S0 =>
SH(3), Y => ML_int_4_7_port);
M1_3_22 : MX2XL port map( A => ML_int_3_22_port, B => ML_int_3_14_port, S0
=> SH(3), Y => ML_int_4_22_port);
M0_3_6 : MX2XL port map( A => ML_int_3_6_port, B => ML_int_3_30_port, S0 =>
SH(3), Y => ML_int_4_6_port);
M1_3_21 : MX2XL port map( A => ML_int_3_21_port, B => ML_int_3_13_port, S0
=> SH(3), Y => ML_int_4_21_port);
M0_3_5 : MX2XL port map( A => ML_int_3_5_port, B => ML_int_3_29_port, S0 =>
SH(3), Y => ML_int_4_5_port);
M1_3_20 : MX2XL port map( A => ML_int_3_20_port, B => ML_int_3_12_port, S0
=> SH(3), Y => ML_int_4_20_port);
M0_3_4 : MX2XL port map( A => ML_int_3_4_port, B => ML_int_3_28_port, S0 =>
SH(3), Y => ML_int_4_4_port);
M1_3_19 : MX2XL port map( A => ML_int_3_19_port, B => ML_int_3_11_port, S0
=> SH(3), Y => ML_int_4_19_port);
M0_3_3 : MX2XL port map( A => ML_int_3_3_port, B => ML_int_3_27_port, S0 =>
SH(3), Y => ML_int_4_3_port);
M1_3_18 : MX2XL port map( A => ML_int_3_18_port, B => ML_int_3_10_port, S0
=> SH(3), Y => ML_int_4_18_port);
M0_3_2 : MX2XL port map( A => ML_int_3_2_port, B => ML_int_3_26_port, S0 =>
SH(3), Y => ML_int_4_2_port);
M1_3_17 : MX2XL port map( A => ML_int_3_17_port, B => ML_int_3_9_port, S0 =>
SH(3), Y => ML_int_4_17_port);
M0_3_1 : MX2XL port map( A => ML_int_3_1_port, B => ML_int_3_25_port, S0 =>
SH(3), Y => ML_int_4_1_port);
M1_3_16 : MX2XL port map( A => ML_int_3_16_port, B => ML_int_3_8_port, S0 =>
SH(3), Y => ML_int_4_16_port);
M0_3_0 : MX2XL port map( A => ML_int_3_0_port, B => ML_int_3_24_port, S0 =>
SH(3), Y => ML_int_4_0_port);
M1_2_31 : MX2XL port map( A => ML_int_2_31_port, B => ML_int_2_27_port, S0
=> SH(2), Y => ML_int_3_31_port);
M1_2_23 : MX2XL port map( A => ML_int_2_23_port, B => ML_int_2_19_port, S0
=> SH(2), Y => ML_int_3_23_port);
M1_2_15 : MX2XL port map( A => ML_int_2_15_port, B => ML_int_2_11_port, S0
=> SH(2), Y => ML_int_3_15_port);
M1_2_7 : MX2XL port map( A => ML_int_2_7_port, B => ML_int_2_3_port, S0 =>
SH(2), Y => ML_int_3_7_port);
M1_2_30 : MX2XL port map( A => ML_int_2_30_port, B => ML_int_2_26_port, S0
=> SH(2), Y => ML_int_3_30_port);
M1_2_22 : MX2XL port map( A => ML_int_2_22_port, B => ML_int_2_18_port, S0
=> SH(2), Y => ML_int_3_22_port);
M1_2_14 : MX2XL port map( A => ML_int_2_14_port, B => ML_int_2_10_port, S0
=> SH(2), Y => ML_int_3_14_port);
M1_2_6 : MX2XL port map( A => ML_int_2_6_port, B => ML_int_2_2_port, S0 =>
SH(2), Y => ML_int_3_6_port);
M1_2_29 : MX2XL port map( A => ML_int_2_29_port, B => ML_int_2_25_port, S0
=> SH(2), Y => ML_int_3_29_port);
M1_2_21 : MX2XL port map( A => ML_int_2_21_port, B => ML_int_2_17_port, S0
=> SH(2), Y => ML_int_3_21_port);
M1_2_13 : MX2XL port map( A => ML_int_2_13_port, B => ML_int_2_9_port, S0 =>
SH(2), Y => ML_int_3_13_port);
M1_2_5 : MX2XL port map( A => ML_int_2_5_port, B => ML_int_2_1_port, S0 =>
SH(2), Y => ML_int_3_5_port);
M1_2_28 : MX2XL port map( A => ML_int_2_28_port, B => ML_int_2_24_port, S0
=> SH(2), Y => ML_int_3_28_port);
M1_2_20 : MX2XL port map( A => ML_int_2_20_port, B => ML_int_2_16_port, S0
=> SH(2), Y => ML_int_3_20_port);
M1_2_12 : MX2XL port map( A => ML_int_2_12_port, B => ML_int_2_8_port, S0 =>
SH(2), Y => ML_int_3_12_port);
M1_2_4 : MX2XL port map( A => ML_int_2_4_port, B => ML_int_2_0_port, S0 =>
SH(2), Y => ML_int_3_4_port);
M1_2_27 : MX2XL port map( A => ML_int_2_27_port, B => ML_int_2_23_port, S0
=> SH(2), Y => ML_int_3_27_port);
M1_2_19 : MX2XL port map( A => ML_int_2_19_port, B => ML_int_2_15_port, S0
=> SH(2), Y => ML_int_3_19_port);
M1_2_11 : MX2XL port map( A => ML_int_2_11_port, B => ML_int_2_7_port, S0 =>
SH(2), Y => ML_int_3_11_port);
M0_2_3 : MX2XL port map( A => ML_int_2_3_port, B => ML_int_2_31_port, S0 =>
SH(2), Y => ML_int_3_3_port);
M1_2_26 : MX2XL port map( A => ML_int_2_26_port, B => ML_int_2_22_port, S0
=> SH(2), Y => ML_int_3_26_port);
M1_2_18 : MX2XL port map( A => ML_int_2_18_port, B => ML_int_2_14_port, S0
=> SH(2), Y => ML_int_3_18_port);
M1_2_10 : MX2XL port map( A => ML_int_2_10_port, B => ML_int_2_6_port, S0 =>
SH(2), Y => ML_int_3_10_port);
M0_2_2 : MX2XL port map( A => ML_int_2_2_port, B => ML_int_2_30_port, S0 =>
SH(2), Y => ML_int_3_2_port);
M1_2_25 : MX2XL port map( A => ML_int_2_25_port, B => ML_int_2_21_port, S0
=> SH(2), Y => ML_int_3_25_port);
M1_2_17 : MX2XL port map( A => ML_int_2_17_port, B => ML_int_2_13_port, S0
=> SH(2), Y => ML_int_3_17_port);
M1_2_9 : MX2XL port map( A => ML_int_2_9_port, B => ML_int_2_5_port, S0 =>
SH(2), Y => ML_int_3_9_port);
M0_2_1 : MX2XL port map( A => ML_int_2_1_port, B => ML_int_2_29_port, S0 =>
SH(2), Y => ML_int_3_1_port);
M1_2_24 : MX2XL port map( A => ML_int_2_24_port, B => ML_int_2_20_port, S0
=> SH(2), Y => ML_int_3_24_port);
M1_2_16 : MX2XL port map( A => ML_int_2_16_port, B => ML_int_2_12_port, S0
=> SH(2), Y => ML_int_3_16_port);
M1_2_8 : MX2XL port map( A => ML_int_2_8_port, B => ML_int_2_4_port, S0 =>
SH(2), Y => ML_int_3_8_port);
M0_2_0 : MX2XL port map( A => ML_int_2_0_port, B => ML_int_2_28_port, S0 =>
SH(2), Y => ML_int_3_0_port);
M1_0_31 : MX2XL port map( A => A(31), B => A(30), S0 => SH(0), Y =>
ML_int_1_31_port);
M1_0_29 : MX2XL port map( A => A(29), B => A(28), S0 => SH(0), Y =>
ML_int_1_29_port);
M1_0_27 : MX2XL port map( A => A(27), B => A(26), S0 => SH(0), Y =>
ML_int_1_27_port);
M1_0_25 : MX2XL port map( A => A(25), B => A(24), S0 => SH(0), Y =>
ML_int_1_25_port);
M1_0_23 : MX2XL port map( A => A(23), B => A(22), S0 => SH(0), Y =>
ML_int_1_23_port);
M1_0_21 : MX2XL port map( A => A(21), B => A(20), S0 => SH(0), Y =>
ML_int_1_21_port);
M1_0_19 : MX2XL port map( A => A(19), B => A(18), S0 => SH(0), Y =>
ML_int_1_19_port);
M1_0_17 : MX2XL port map( A => A(17), B => A(16), S0 => SH(0), Y =>
ML_int_1_17_port);
M1_0_15 : MX2XL port map( A => A(15), B => A(14), S0 => SH(0), Y =>
ML_int_1_15_port);
M1_0_13 : MX2XL port map( A => A(13), B => A(12), S0 => SH(0), Y =>
ML_int_1_13_port);
M1_0_11 : MX2XL port map( A => A(11), B => A(10), S0 => SH(0), Y =>
ML_int_1_11_port);
M1_0_9 : MX2XL port map( A => A(9), B => A(8), S0 => SH(0), Y =>
ML_int_1_9_port);
M1_0_7 : MX2XL port map( A => A(7), B => A(6), S0 => SH(0), Y =>
ML_int_1_7_port);
M1_0_5 : MX2XL port map( A => A(5), B => A(4), S0 => SH(0), Y =>
ML_int_1_5_port);
M1_0_3 : MX2XL port map( A => A(3), B => A(2), S0 => SH(0), Y =>
ML_int_1_3_port);
M1_0_1 : MX2XL port map( A => A(1), B => A(0), S0 => SH(0), Y =>
ML_int_1_1_port);
M1_0_30 : MX2XL port map( A => A(30), B => A(29), S0 => SH(0), Y =>
ML_int_1_30_port);
M1_0_28 : MX2XL port map( A => A(28), B => A(27), S0 => SH(0), Y =>
ML_int_1_28_port);
M1_0_26 : MX2XL port map( A => A(26), B => A(25), S0 => SH(0), Y =>
ML_int_1_26_port);
M1_0_24 : MX2XL port map( A => A(24), B => A(23), S0 => SH(0), Y =>
ML_int_1_24_port);
M1_0_22 : MX2XL port map( A => A(22), B => A(21), S0 => SH(0), Y =>
ML_int_1_22_port);
M1_0_20 : MX2XL port map( A => A(20), B => A(19), S0 => SH(0), Y =>
ML_int_1_20_port);
M1_0_18 : MX2XL port map( A => A(18), B => A(17), S0 => SH(0), Y =>
ML_int_1_18_port);
M1_0_16 : MX2XL port map( A => A(16), B => A(15), S0 => SH(0), Y =>
ML_int_1_16_port);
M1_0_14 : MX2XL port map( A => A(14), B => A(13), S0 => SH(0), Y =>
ML_int_1_14_port);
M1_0_12 : MX2XL port map( A => A(12), B => A(11), S0 => SH(0), Y =>
ML_int_1_12_port);
M1_0_10 : MX2XL port map( A => A(10), B => A(9), S0 => SH(0), Y =>
ML_int_1_10_port);
M1_0_8 : MX2XL port map( A => A(8), B => A(7), S0 => SH(0), Y =>
ML_int_1_8_port);
M1_0_6 : MX2XL port map( A => A(6), B => A(5), S0 => SH(0), Y =>
ML_int_1_6_port);
M1_0_4 : MX2XL port map( A => A(4), B => A(3), S0 => SH(0), Y =>
ML_int_1_4_port);
M1_0_2 : MX2XL port map( A => A(2), B => A(1), S0 => SH(0), Y =>
ML_int_1_2_port);
M0_0_0 : MX2XL port map( A => A(0), B => A(31), S0 => SH(0), Y =>
ML_int_1_0_port);
M1_1_31 : MX2XL port map( A => ML_int_1_31_port, B => ML_int_1_29_port, S0
=> SH(1), Y => ML_int_2_31_port);
M1_1_27 : MX2XL port map( A => ML_int_1_27_port, B => ML_int_1_25_port, S0
=> SH(1), Y => ML_int_2_27_port);
M1_1_23 : MX2XL port map( A => ML_int_1_23_port, B => ML_int_1_21_port, S0
=> SH(1), Y => ML_int_2_23_port);
M1_1_19 : MX2XL port map( A => ML_int_1_19_port, B => ML_int_1_17_port, S0
=> SH(1), Y => ML_int_2_19_port);
M1_1_15 : MX2XL port map( A => ML_int_1_15_port, B => ML_int_1_13_port, S0
=> SH(1), Y => ML_int_2_15_port);
M1_1_11 : MX2XL port map( A => ML_int_1_11_port, B => ML_int_1_9_port, S0 =>
SH(1), Y => ML_int_2_11_port);
M1_1_7 : MX2XL port map( A => ML_int_1_7_port, B => ML_int_1_5_port, S0 =>
SH(1), Y => ML_int_2_7_port);
M1_1_3 : MX2XL port map( A => ML_int_1_3_port, B => ML_int_1_1_port, S0 =>
SH(1), Y => ML_int_2_3_port);
M1_1_30 : MX2XL port map( A => ML_int_1_30_port, B => ML_int_1_28_port, S0
=> SH(1), Y => ML_int_2_30_port);
M1_1_26 : MX2XL port map( A => ML_int_1_26_port, B => ML_int_1_24_port, S0
=> SH(1), Y => ML_int_2_26_port);
M1_1_22 : MX2XL port map( A => ML_int_1_22_port, B => ML_int_1_20_port, S0
=> SH(1), Y => ML_int_2_22_port);
M1_1_18 : MX2XL port map( A => ML_int_1_18_port, B => ML_int_1_16_port, S0
=> SH(1), Y => ML_int_2_18_port);
M1_1_14 : MX2XL port map( A => ML_int_1_14_port, B => ML_int_1_12_port, S0
=> SH(1), Y => ML_int_2_14_port);
M1_1_10 : MX2XL port map( A => ML_int_1_10_port, B => ML_int_1_8_port, S0 =>
SH(1), Y => ML_int_2_10_port);
M1_1_6 : MX2XL port map( A => ML_int_1_6_port, B => ML_int_1_4_port, S0 =>
SH(1), Y => ML_int_2_6_port);
M1_1_2 : MX2XL port map( A => ML_int_1_2_port, B => ML_int_1_0_port, S0 =>
SH(1), Y => ML_int_2_2_port);
M1_1_29 : MX2XL port map( A => ML_int_1_29_port, B => ML_int_1_27_port, S0
=> SH(1), Y => ML_int_2_29_port);
M1_1_25 : MX2XL port map( A => ML_int_1_25_port, B => ML_int_1_23_port, S0
=> SH(1), Y => ML_int_2_25_port);
M1_1_21 : MX2XL port map( A => ML_int_1_21_port, B => ML_int_1_19_port, S0
=> SH(1), Y => ML_int_2_21_port);
M1_1_17 : MX2XL port map( A => ML_int_1_17_port, B => ML_int_1_15_port, S0
=> SH(1), Y => ML_int_2_17_port);
M1_1_13 : MX2XL port map( A => ML_int_1_13_port, B => ML_int_1_11_port, S0
=> SH(1), Y => ML_int_2_13_port);
M1_1_9 : MX2XL port map( A => ML_int_1_9_port, B => ML_int_1_7_port, S0 =>
SH(1), Y => ML_int_2_9_port);
M1_1_5 : MX2XL port map( A => ML_int_1_5_port, B => ML_int_1_3_port, S0 =>
SH(1), Y => ML_int_2_5_port);
M0_1_1 : MX2XL port map( A => ML_int_1_1_port, B => ML_int_1_31_port, S0 =>
SH(1), Y => ML_int_2_1_port);
M1_1_28 : MX2XL port map( A => ML_int_1_28_port, B => ML_int_1_26_port, S0
=> SH(1), Y => ML_int_2_28_port);
M1_1_24 : MX2XL port map( A => ML_int_1_24_port, B => ML_int_1_22_port, S0
=> SH(1), Y => ML_int_2_24_port);
M1_1_20 : MX2XL port map( A => ML_int_1_20_port, B => ML_int_1_18_port, S0
=> SH(1), Y => ML_int_2_20_port);
M1_1_16 : MX2XL port map( A => ML_int_1_16_port, B => ML_int_1_14_port, S0
=> SH(1), Y => ML_int_2_16_port);
M1_1_12 : MX2XL port map( A => ML_int_1_12_port, B => ML_int_1_10_port, S0
=> SH(1), Y => ML_int_2_12_port);
M1_1_8 : MX2XL port map( A => ML_int_1_8_port, B => ML_int_1_6_port, S0 =>
SH(1), Y => ML_int_2_8_port);
M1_1_4 : MX2XL port map( A => ML_int_1_4_port, B => ML_int_1_2_port, S0 =>
SH(1), Y => ML_int_2_4_port);
M0_1_0 : MX2XL port map( A => ML_int_1_0_port, B => ML_int_1_30_port, S0 =>
SH(1), Y => ML_int_2_0_port);
M1_4_31 : MX2X1 port map( A => ML_int_4_31_port, B => ML_int_4_15_port, S0
=> n3, Y => B(31));
M1_4_30 : MX2X1 port map( A => ML_int_4_30_port, B => ML_int_4_14_port, S0
=> n3, Y => B(30));
M1_4_29 : MX2X1 port map( A => ML_int_4_29_port, B => ML_int_4_13_port, S0
=> n3, Y => B(29));
M1_4_28 : MX2X1 port map( A => ML_int_4_28_port, B => ML_int_4_12_port, S0
=> n3, Y => B(28));
M1_4_27 : MX2X1 port map( A => ML_int_4_27_port, B => ML_int_4_11_port, S0
=> n3, Y => B(27));
M1_4_26 : MX2X1 port map( A => ML_int_4_26_port, B => ML_int_4_10_port, S0
=> n3, Y => B(26));
M1_4_25 : MX2X1 port map( A => ML_int_4_25_port, B => ML_int_4_9_port, S0 =>
n2, Y => B(25));
M1_4_24 : MX2X1 port map( A => ML_int_4_24_port, B => ML_int_4_8_port, S0 =>
n2, Y => B(24));
M1_4_23 : MX2X1 port map( A => ML_int_4_23_port, B => ML_int_4_7_port, S0 =>
n2, Y => B(23));
M1_4_22 : MX2X1 port map( A => ML_int_4_22_port, B => ML_int_4_6_port, S0 =>
n2, Y => B(22));
M1_4_21 : MX2X1 port map( A => ML_int_4_21_port, B => ML_int_4_5_port, S0 =>
n2, Y => B(21));
M1_4_20 : MX2X1 port map( A => ML_int_4_20_port, B => ML_int_4_4_port, S0 =>
n2, Y => B(20));
M1_4_19 : MX2X1 port map( A => ML_int_4_19_port, B => ML_int_4_3_port, S0 =>
n2, Y => B(19));
M1_4_18 : MX2X1 port map( A => ML_int_4_18_port, B => ML_int_4_2_port, S0 =>
n2, Y => B(18));
M1_4_17 : MX2X1 port map( A => ML_int_4_17_port, B => ML_int_4_1_port, S0 =>
n2, Y => B(17));
M1_4_16 : MX2X1 port map( A => ML_int_4_16_port, B => ML_int_4_0_port, S0 =>
n2, Y => B(16));
M0_4_15 : MX2X1 port map( A => ML_int_4_15_port, B => ML_int_4_31_port, S0
=> n2, Y => B(15));
M0_4_14 : MX2X1 port map( A => ML_int_4_14_port, B => ML_int_4_30_port, S0
=> n2, Y => B(14));
M0_4_13 : MX2X1 port map( A => ML_int_4_13_port, B => ML_int_4_29_port, S0
=> n2, Y => B(13));
M0_4_12 : MX2X1 port map( A => ML_int_4_12_port, B => ML_int_4_28_port, S0
=> n1, Y => B(12));
M0_4_11 : MX2X1 port map( A => ML_int_4_11_port, B => ML_int_4_27_port, S0
=> n1, Y => B(11));
M0_4_10 : MX2X1 port map( A => ML_int_4_10_port, B => ML_int_4_26_port, S0
=> n1, Y => B(10));
M0_4_9 : MX2X1 port map( A => ML_int_4_9_port, B => ML_int_4_25_port, S0 =>
n1, Y => B(9));
M0_4_8 : MX2X1 port map( A => ML_int_4_8_port, B => ML_int_4_24_port, S0 =>
n1, Y => B(8));
M0_4_7 : MX2X1 port map( A => ML_int_4_7_port, B => ML_int_4_23_port, S0 =>
n1, Y => B(7));
M0_4_6 : MX2X1 port map( A => ML_int_4_6_port, B => ML_int_4_22_port, S0 =>
n1, Y => B(6));
M0_4_5 : MX2X1 port map( A => ML_int_4_5_port, B => ML_int_4_21_port, S0 =>
n1, Y => B(5));
M0_4_3 : MX2X1 port map( A => ML_int_4_3_port, B => ML_int_4_19_port, S0 =>
n1, Y => B(3));
M0_4_4 : MX2X1 port map( A => ML_int_4_4_port, B => ML_int_4_20_port, S0 =>
n1, Y => B(4));
M0_4_2 : MX2X1 port map( A => ML_int_4_2_port, B => ML_int_4_18_port, S0 =>
n1, Y => B(2));
M0_4_1 : MX2X1 port map( A => ML_int_4_1_port, B => ML_int_4_17_port, S0 =>
n1, Y => B(1));
M0_4_0 : MX2X1 port map( A => ML_int_4_0_port, B => ML_int_4_16_port, S0 =>
n1, Y => B(0));
U2 : BUFX2 port map( A => SH(4), Y => n1);
U3 : BUFX2 port map( A => SH(4), Y => n2);
U4 : BUFX2 port map( A => SH(4), Y => n3);
end SYN_mx2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32_DW_sra_0 is
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31 downto
0));
end SHIFTER_GENERIC_N32_DW_sra_0;
architecture SYN_mx2 of SHIFTER_GENERIC_N32_DW_sra_0 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI2B2X1
port( A1N, A0, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI221X1
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI2BB2X1
port( B0, B1, A0N, A1N : in std_logic; Y : out std_logic);
end component;
component AO22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component MXI2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component OA21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component OAI211XL
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component AND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2BXL
port( AN, B : in std_logic; Y : out std_logic);
end component;
component NAND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component AOI21XL
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component NOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
signal B_30_port, B_29_port, B_28_port, B_27_port, B_26_port, B_25_port,
B_24_port, B_23_port, B_22_port, B_21_port, B_20_port, B_19_port,
B_18_port, B_17_port, B_16_port, B_15_port, B_14_port, B_13_port,
B_12_port, B_11_port, B_10_port, B_9_port, B_8_port, B_7_port, B_6_port,
B_5_port, B_4_port, B_3_port, B_2_port, B_1_port, B_0_port, n1, n2, n3,
n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34
, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63
, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92
, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164 :
std_logic;
begin
B <= ( A(31), B_30_port, B_29_port, B_28_port, B_27_port, B_26_port,
B_25_port, B_24_port, B_23_port, B_22_port, B_21_port, B_20_port,
B_19_port, B_18_port, B_17_port, B_16_port, B_15_port, B_14_port,
B_13_port, B_12_port, B_11_port, B_10_port, B_9_port, B_8_port, B_7_port,
B_6_port, B_5_port, B_4_port, B_3_port, B_2_port, B_1_port, B_0_port );
U2 : NOR2X2 port map( A => SH(0), B => SH(1), Y => n50);
U3 : INVXL port map( A => n50, Y => n64);
U4 : NAND2XL port map( A => SH(1), B => n164, Y => n44);
U5 : NAND2XL port map( A => SH(0), B => SH(1), Y => n46);
U6 : NOR2XL port map( A => SH(2), B => SH(3), Y => n72);
U7 : NOR2XL port map( A => n153, B => SH(3), Y => n70);
U8 : AOI21XL port map( A0 => SH(2), A1 => A(31), B0 => n73, Y => n117);
U9 : INVXL port map( A => SH(2), Y => n153);
U10 : INVXL port map( A => SH(0), Y => n164);
U11 : NAND2XL port map( A => SH(3), B => n153, Y => n80);
U12 : NAND2XL port map( A => SH(2), B => SH(3), Y => n107);
U13 : NAND2XL port map( A => n73, B => SH(2), Y => n81);
U14 : AND2XL port map( A => n152, B => SH(2), Y => n10);
U15 : NOR2BXL port map( AN => SH(3), B => n113, Y => n73);
U16 : AND2XL port map( A => SH(3), B => n1, Y => n152);
U17 : INVX2 port map( A => SH(4), Y => n1);
U18 : OAI221X1 port map( A0 => n2, A1 => n3, B0 => n4, B1 => n1, C0 => n5, Y
=> B_9_port);
U19 : AOI222XL port map( A0 => n6, A1 => n7, B0 => n8, B1 => n9, C0 => n10,
C1 => n11, Y => n5);
U20 : OAI221X1 port map( A0 => n12, A1 => n3, B0 => n13, B1 => n1, C0 => n14
, Y => B_8_port);
U21 : AOI222XL port map( A0 => n6, A1 => n15, B0 => n8, B1 => n16, C0 => n10
, C1 => n17, Y => n14);
U22 : OAI221X1 port map( A0 => n18, A1 => n3, B0 => n19, B1 => n1, C0 => n20
, Y => B_7_port);
U23 : AOI222XL port map( A0 => n6, A1 => n21, B0 => n8, B1 => n22, C0 => n10
, C1 => n23, Y => n20);
U24 : OAI221X1 port map( A0 => n24, A1 => n3, B0 => n25, B1 => n1, C0 => n26
, Y => B_6_port);
U25 : AOI222XL port map( A0 => n6, A1 => n27, B0 => n8, B1 => n28, C0 => n10
, C1 => n29, Y => n26);
U26 : OAI221X1 port map( A0 => n30, A1 => n3, B0 => n31, B1 => n1, C0 => n32
, Y => B_5_port);
U27 : AOI222XL port map( A0 => n6, A1 => n33, B0 => n8, B1 => n7, C0 => n10,
C1 => n9, Y => n32);
U28 : OAI221X1 port map( A0 => n34, A1 => n3, B0 => n35, B1 => n1, C0 => n36
, Y => B_4_port);
U29 : AOI222XL port map( A0 => n6, A1 => n37, B0 => n8, B1 => n15, C0 => n10
, C1 => n16, Y => n36);
U30 : OAI221X1 port map( A0 => n18, A1 => n38, B0 => n39, B1 => n1, C0 =>
n40, Y => B_3_port);
U31 : AOI222XL port map( A0 => n10, A1 => n22, B0 => n41, B1 => n42, C0 =>
n8, C1 => n21, Y => n40);
U32 : CLKINVX1 port map( A => n43, Y => n21);
U33 : OAI221X1 port map( A0 => n44, A1 => n45, B0 => n46, B1 => n47, C0 =>
n48, Y => n42);
U34 : AOI22XL port map( A0 => A(4), A1 => n49, B0 => A(3), B1 => n50, Y =>
n48);
U35 : AOI221XL port map( A0 => n51, A1 => A(9), B0 => n52, B1 => A(10), C0
=> n53, Y => n18);
U36 : AO22X1 port map( A0 => A(8), A1 => n49, B0 => A(7), B1 => n50, Y =>
n53);
U37 : OAI21X1 port map( A0 => SH(4), A1 => n54, B0 => n55, Y => B_30_port);
U38 : OAI221X1 port map( A0 => n24, A1 => n38, B0 => n56, B1 => n1, C0 =>
n57, Y => B_2_port);
U39 : AOI222XL port map( A0 => n10, A1 => n28, B0 => n41, B1 => n58, C0 =>
n8, C1 => n27, Y => n57);
U40 : CLKINVX1 port map( A => n59, Y => n27);
U41 : OAI221X1 port map( A0 => n44, A1 => n60, B0 => n46, B1 => n45, C0 =>
n61, Y => n58);
U42 : AOI22XL port map( A0 => A(3), A1 => n49, B0 => A(2), B1 => n50, Y =>
n61);
U43 : AOI221XL port map( A0 => n51, A1 => A(8), B0 => n52, B1 => A(9), C0 =>
n62, Y => n24);
U44 : OAI2B2X1 port map( A1N => A(7), A0 => n63, B0 => n47, B1 => n64, Y =>
n62);
U45 : OAI21X1 port map( A0 => SH(4), A1 => n65, B0 => n55, Y => B_29_port);
U46 : OAI21X1 port map( A0 => SH(4), A1 => n66, B0 => n55, Y => B_28_port);
U47 : OAI21X1 port map( A0 => SH(4), A1 => n67, B0 => n55, Y => B_27_port);
U48 : OAI21X1 port map( A0 => SH(4), A1 => n68, B0 => n55, Y => B_26_port);
U49 : OAI21X1 port map( A0 => SH(4), A1 => n4, B0 => n55, Y => B_25_port);
U50 : AOI221XL port map( A0 => n69, A1 => n70, B0 => n71, B1 => n72, C0 =>
n73, Y => n4);
U51 : OAI21X1 port map( A0 => SH(4), A1 => n13, B0 => n55, Y => B_24_port);
U52 : AOI221XL port map( A0 => n74, A1 => n70, B0 => n75, B1 => n72, C0 =>
n73, Y => n13);
U53 : OAI21X1 port map( A0 => SH(4), A1 => n19, B0 => n55, Y => B_23_port);
U54 : AOI221XL port map( A0 => n76, A1 => n70, B0 => n77, B1 => n72, C0 =>
n73, Y => n19);
U55 : OAI21X1 port map( A0 => SH(4), A1 => n25, B0 => n55, Y => B_22_port);
U56 : CLKINVX1 port map( A => n78, Y => n25);
U57 : OAI211XL port map( A0 => n79, A1 => n80, B0 => n81, C0 => n82, Y =>
n78);
U58 : AOI22XL port map( A0 => n70, A1 => n83, B0 => n72, B1 => n84, Y => n82
);
U59 : OAI21X1 port map( A0 => SH(4), A1 => n31, B0 => n55, Y => B_21_port);
U60 : CLKINVX1 port map( A => n85, Y => n31);
U61 : OAI211XL port map( A0 => n86, A1 => n80, B0 => n81, C0 => n87, Y =>
n85);
U62 : AOI22XL port map( A0 => n70, A1 => n71, B0 => n72, B1 => n11, Y => n87
);
U63 : OAI21X1 port map( A0 => SH(4), A1 => n35, B0 => n55, Y => B_20_port);
U64 : CLKINVX1 port map( A => n88, Y => n35);
U65 : OAI211XL port map( A0 => n89, A1 => n80, B0 => n81, C0 => n90, Y =>
n88);
U66 : AOI22XL port map( A0 => n70, A1 => n75, B0 => n72, B1 => n17, Y => n90
);
U67 : OAI221X1 port map( A0 => n30, A1 => n38, B0 => n91, B1 => n1, C0 =>
n92, Y => B_1_port);
U68 : AOI222XL port map( A0 => n10, A1 => n7, B0 => n41, B1 => n93, C0 => n8
, C1 => n33, Y => n92);
U69 : CLKINVX1 port map( A => n2, Y => n33);
U70 : AOI221XL port map( A0 => n51, A1 => A(11), B0 => n52, B1 => A(12), C0
=> n94, Y => n2);
U71 : AO22X1 port map( A0 => A(10), A1 => n49, B0 => A(9), B1 => n50, Y =>
n94);
U72 : OAI221X1 port map( A0 => n44, A1 => n95, B0 => n46, B1 => n60, C0 =>
n96, Y => n93);
U73 : AOI22XL port map( A0 => A(2), A1 => n49, B0 => A(1), B1 => n50, Y =>
n96);
U74 : CLKINVX1 port map( A => n97, Y => n7);
U75 : AOI221XL port map( A0 => n51, A1 => A(7), B0 => n52, B1 => A(8), C0 =>
n98, Y => n30);
U76 : OAI22X1 port map( A0 => n47, A1 => n63, B0 => n45, B1 => n64, Y => n98
);
U77 : CLKINVX1 port map( A => A(6), Y => n47);
U78 : OAI21X1 port map( A0 => SH(4), A1 => n39, B0 => n55, Y => B_19_port);
U79 : CLKINVX1 port map( A => n99, Y => n39);
U80 : OAI211XL port map( A0 => n100, A1 => n80, B0 => n81, C0 => n101, Y =>
n99);
U81 : AOI22XL port map( A0 => n70, A1 => n77, B0 => n72, B1 => n23, Y =>
n101);
U82 : OAI21X1 port map( A0 => SH(4), A1 => n56, B0 => n55, Y => B_18_port);
U83 : AOI221XL port map( A0 => n102, A1 => n103, B0 => n83, B1 => n104, C0
=> n105, Y => n56);
U84 : AO22X1 port map( A0 => n70, A1 => n84, B0 => n72, B1 => n29, Y => n105
);
U85 : OAI21X1 port map( A0 => SH(4), A1 => n91, B0 => n55, Y => B_17_port);
U86 : AOI221XL port map( A0 => n69, A1 => n103, B0 => n71, B1 => n104, C0 =>
n106, Y => n91);
U87 : AO22X1 port map( A0 => n70, A1 => n11, B0 => n72, B1 => n9, Y => n106)
;
U88 : CLKINVX1 port map( A => n107, Y => n103);
U89 : CLKINVX1 port map( A => n86, Y => n69);
U90 : OAI21X1 port map( A0 => SH(4), A1 => n108, B0 => n55, Y => B_16_port);
U91 : CLKINVX1 port map( A => n109, Y => n55);
U92 : CLKINVX1 port map( A => n110, Y => B_15_port);
U93 : AOI221XL port map( A0 => n23, A1 => n6, B0 => n22, B1 => n41, C0 =>
n111, Y => n110);
U94 : CLKINVX1 port map( A => n112, Y => n111);
U95 : AOI221XL port map( A0 => n10, A1 => n76, B0 => n8, B1 => n77, C0 =>
n109, Y => n112);
U96 : NOR2X1 port map( A => n1, B => n113, Y => n109);
U97 : OAI221X1 port map( A0 => n114, A1 => n3, B0 => n54, B1 => n1, C0 =>
n115, Y => B_14_port);
U98 : AOI222XL port map( A0 => n6, A1 => n29, B0 => n8, B1 => n84, C0 => n10
, C1 => n83, Y => n115);
U99 : OA21X1 port map( A0 => n79, A1 => n116, B0 => n117, Y => n54);
U100 : OAI221X1 port map( A0 => n97, A1 => n3, B0 => n65, B1 => n1, C0 =>
n118, Y => B_13_port);
U101 : AOI222XL port map( A0 => n6, A1 => n9, B0 => n8, B1 => n11, C0 => n10
, C1 => n71, Y => n118);
U102 : OAI221X1 port map( A0 => n44, A1 => n119, B0 => n46, B1 => n120, C0
=> n121, Y => n71);
U103 : AOI22XL port map( A0 => A(26), A1 => n49, B0 => A(25), B1 => n50, Y
=> n121);
U104 : OAI221X1 port map( A0 => n44, A1 => n122, B0 => n46, B1 => n123, C0
=> n124, Y => n11);
U105 : AOI22XL port map( A0 => A(22), A1 => n49, B0 => A(21), B1 => n50, Y
=> n124);
U106 : CLKINVX1 port map( A => A(23), Y => n122);
U107 : OAI221X1 port map( A0 => n44, A1 => n125, B0 => n46, B1 => n126, C0
=> n127, Y => n9);
U108 : AOI22XL port map( A0 => A(18), A1 => n49, B0 => A(17), B1 => n50, Y
=> n127);
U109 : OA21X1 port map( A0 => n86, A1 => n116, B0 => n117, Y => n65);
U110 : AOI222XL port map( A0 => n50, A1 => A(29), B0 => n49, B1 => A(30), C0
=> SH(1), C1 => A(31), Y => n86);
U111 : AOI221XL port map( A0 => n51, A1 => A(15), B0 => n52, B1 => A(16), C0
=> n128, Y => n97);
U112 : AO22X1 port map( A0 => A(14), A1 => n49, B0 => A(13), B1 => n50, Y =>
n128);
U113 : OAI221X1 port map( A0 => n129, A1 => n3, B0 => n66, B1 => n1, C0 =>
n130, Y => B_12_port);
U114 : AOI222XL port map( A0 => n6, A1 => n16, B0 => n8, B1 => n17, C0 =>
n10, C1 => n75, Y => n130);
U115 : OA21X1 port map( A0 => n89, A1 => n116, B0 => n117, Y => n66);
U116 : OAI221X1 port map( A0 => n43, A1 => n3, B0 => n67, B1 => n1, C0 =>
n131, Y => B_11_port);
U117 : AOI222XL port map( A0 => n6, A1 => n22, B0 => n8, B1 => n23, C0 =>
n10, C1 => n77, Y => n131);
U118 : OAI221X1 port map( A0 => n44, A1 => n132, B0 => n46, B1 => n133, C0
=> n134, Y => n77);
U119 : AOI22XL port map( A0 => A(24), A1 => n49, B0 => A(23), B1 => n50, Y
=> n134);
U120 : OAI221X1 port map( A0 => n126, A1 => n63, B0 => n125, B1 => n64, C0
=> n135, Y => n23);
U121 : AOI22XL port map( A0 => A(21), A1 => n51, B0 => A(22), B1 => n52, Y
=> n135);
U122 : OAI221X1 port map( A0 => n44, A1 => n136, B0 => n46, B1 => n137, C0
=> n138, Y => n22);
U123 : AOI22XL port map( A0 => A(16), A1 => n49, B0 => A(15), B1 => n50, Y
=> n138);
U124 : CLKINVX1 port map( A => A(17), Y => n136);
U125 : OA21X1 port map( A0 => n100, A1 => n116, B0 => n117, Y => n67);
U126 : CLKINVX1 port map( A => n76, Y => n100);
U127 : OAI221X1 port map( A0 => n44, A1 => n139, B0 => n46, B1 => n140, C0
=> n141, Y => n76);
U128 : AOI22XL port map( A0 => A(28), A1 => n49, B0 => A(27), B1 => n50, Y
=> n141);
U129 : AOI221XL port map( A0 => n51, A1 => A(13), B0 => n52, B1 => A(14), C0
=> n142, Y => n43);
U130 : AO22X1 port map( A0 => A(12), A1 => n49, B0 => A(11), B1 => n50, Y =>
n142);
U131 : OAI221X1 port map( A0 => n59, A1 => n3, B0 => n68, B1 => n1, C0 =>
n143, Y => B_10_port);
U132 : AOI222XL port map( A0 => n6, A1 => n28, B0 => n8, B1 => n29, C0 =>
n10, C1 => n84, Y => n143);
U133 : OAI221X1 port map( A0 => n44, A1 => n123, B0 => n46, B1 => n132, C0
=> n144, Y => n84);
U134 : AOI22XL port map( A0 => A(23), A1 => n49, B0 => A(22), B1 => n50, Y
=> n144);
U135 : CLKINVX1 port map( A => A(25), Y => n132);
U136 : CLKINVX1 port map( A => A(24), Y => n123);
U137 : OAI221X1 port map( A0 => n125, A1 => n63, B0 => n137, B1 => n64, C0
=> n145, Y => n29);
U138 : AOI22XL port map( A0 => A(20), A1 => n51, B0 => A(21), B1 => n52, Y
=> n145);
U139 : CLKINVX1 port map( A => n114, Y => n28);
U140 : AOI221XL port map( A0 => n51, A1 => A(16), B0 => n52, B1 => A(17), C0
=> n146, Y => n114);
U141 : AO22X1 port map( A0 => A(15), A1 => n49, B0 => A(14), B1 => n50, Y =>
n146);
U142 : CLKINVX1 port map( A => n38, Y => n6);
U143 : AOI221XL port map( A0 => n102, A1 => n70, B0 => n83, B1 => n72, C0 =>
n73, Y => n68);
U144 : OAI221X1 port map( A0 => n44, A1 => n120, B0 => n46, B1 => n139, C0
=> n147, Y => n83);
U145 : AOI22XL port map( A0 => A(27), A1 => n49, B0 => A(26), B1 => n50, Y
=> n147);
U146 : CLKINVX1 port map( A => A(29), Y => n139);
U147 : CLKINVX1 port map( A => A(28), Y => n120);
U148 : CLKINVX1 port map( A => n79, Y => n102);
U149 : MXI2X1 port map( A => A(30), B => A(31), S0 => n64, Y => n79);
U150 : CLKINVX1 port map( A => n41, Y => n3);
U151 : AOI221XL port map( A0 => n51, A1 => A(12), B0 => n52, B1 => A(13), C0
=> n148, Y => n59);
U152 : AO22X1 port map( A0 => A(11), A1 => n49, B0 => A(10), B1 => n50, Y =>
n148);
U153 : OAI221X1 port map( A0 => n34, A1 => n38, B0 => n108, B1 => n1, C0 =>
n149, Y => B_0_port);
U154 : AOI222XL port map( A0 => n10, A1 => n15, B0 => n41, B1 => n150, C0 =>
n8, C1 => n37, Y => n149);
U155 : CLKINVX1 port map( A => n12, Y => n37);
U156 : AOI221XL port map( A0 => n51, A1 => A(10), B0 => n52, B1 => A(11), C0
=> n151, Y => n12);
U157 : AO22X1 port map( A0 => A(9), A1 => n49, B0 => A(8), B1 => n50, Y =>
n151);
U158 : AND2X1 port map( A => n152, B => n153, Y => n8);
U159 : OAI221X1 port map( A0 => n44, A1 => n154, B0 => n46, B1 => n95, C0 =>
n155, Y => n150);
U160 : AOI22XL port map( A0 => A(1), A1 => n49, B0 => A(0), B1 => n50, Y =>
n155);
U161 : CLKINVX1 port map( A => A(3), Y => n95);
U162 : CLKINVX1 port map( A => A(2), Y => n154);
U163 : NOR2X1 port map( A => n116, B => SH(4), Y => n41);
U164 : CLKINVX1 port map( A => n72, Y => n116);
U165 : CLKINVX1 port map( A => n129, Y => n15);
U166 : AOI221XL port map( A0 => n51, A1 => A(14), B0 => n52, B1 => A(15), C0
=> n156, Y => n129);
U167 : AO22X1 port map( A0 => A(13), A1 => n49, B0 => A(12), B1 => n50, Y =>
n156);
U168 : AOI221XL port map( A0 => n17, A1 => n70, B0 => n16, B1 => n72, C0 =>
n157, Y => n108);
U169 : OAI2BB2X1 port map( B0 => n107, B1 => n89, A0N => n75, A1N => n104, Y
=> n157);
U170 : CLKINVX1 port map( A => n80, Y => n104);
U171 : OAI221X1 port map( A0 => n44, A1 => n133, B0 => n46, B1 => n119, C0
=> n158, Y => n75);
U172 : AOI22XL port map( A0 => A(25), A1 => n49, B0 => A(24), B1 => n50, Y
=> n158);
U173 : CLKINVX1 port map( A => A(27), Y => n119);
U174 : CLKINVX1 port map( A => A(26), Y => n133);
U175 : CLKINVX1 port map( A => n74, Y => n89);
U176 : OAI221X1 port map( A0 => n44, A1 => n140, B0 => n46, B1 => n113, C0
=> n159, Y => n74);
U177 : AOI22XL port map( A0 => A(29), A1 => n49, B0 => A(28), B1 => n50, Y
=> n159);
U178 : CLKINVX1 port map( A => A(31), Y => n113);
U179 : CLKINVX1 port map( A => A(30), Y => n140);
U180 : OAI221X1 port map( A0 => n44, A1 => n137, B0 => n125, B1 => n46, C0
=> n160, Y => n16);
U181 : AOI22XL port map( A0 => A(17), A1 => n49, B0 => A(16), B1 => n50, Y
=> n160);
U182 : CLKINVX1 port map( A => A(19), Y => n125);
U183 : CLKINVX1 port map( A => A(18), Y => n137);
U184 : CLKINVX1 port map( A => n161, Y => n17);
U185 : AOI221XL port map( A0 => n51, A1 => A(22), B0 => n52, B1 => A(23), C0
=> n162, Y => n161);
U186 : OAI2B2X1 port map( A1N => A(21), A0 => n63, B0 => n64, B1 => n126, Y
=> n162);
U187 : CLKINVX1 port map( A => A(20), Y => n126);
U188 : CLKNAND2X2 port map( A => n70, B => n1, Y => n38);
U189 : AOI221XL port map( A0 => n51, A1 => A(6), B0 => n52, B1 => A(7), C0
=> n163, Y => n34);
U190 : OAI22X1 port map( A0 => n45, A1 => n63, B0 => n60, B1 => n64, Y =>
n163);
U191 : CLKINVX1 port map( A => A(4), Y => n60);
U192 : CLKINVX1 port map( A => n49, Y => n63);
U193 : NOR2X1 port map( A => n164, B => SH(1), Y => n49);
U194 : CLKINVX1 port map( A => A(5), Y => n45);
U195 : CLKINVX1 port map( A => n46, Y => n52);
U196 : CLKINVX1 port map( A => n44, Y => n51);
end SYN_mx2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32_DW_rash_0 is
port( A : in std_logic_vector (31 downto 0); DATA_TC : in std_logic; SH :
in std_logic_vector (4 downto 0); SH_TC : in std_logic; B : out
std_logic_vector (31 downto 0));
end SHIFTER_GENERIC_N32_DW_rash_0;
architecture SYN_mx2 of SHIFTER_GENERIC_N32_DW_rash_0 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI221X1
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component AO22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component NOR2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component MXI2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component AOI32XL
port( A0, A1, A2, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI2B11X1
port( A1N, A0, B0, C0 : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component NOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45
, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74
, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164 : std_logic;
begin
U3 : NAND2X1 port map( A => SH(1), B => n164, Y => n45);
U4 : NAND2X1 port map( A => SH(1), B => SH(0), Y => n43);
U5 : NOR2XL port map( A => SH(2), B => SH(3), Y => n69);
U6 : NOR2XL port map( A => n135, B => SH(3), Y => n71);
U7 : NOR2XL port map( A => n131, B => SH(2), Y => n74);
U8 : INVXL port map( A => SH(2), Y => n135);
U9 : INVXL port map( A => SH(3), Y => n131);
U10 : INVXL port map( A => SH(0), Y => n164);
U11 : NAND2XL port map( A => SH(2), B => n153, Y => n122);
U12 : NOR3XL port map( A => n66, B => SH(4), C => SH(3), Y => B(27));
U13 : INVX2 port map( A => SH(4), Y => n1);
U14 : OAI221X1 port map( A0 => n2, A1 => n3, B0 => n4, B1 => n1, C0 => n5, Y
=> B(9));
U15 : AOI222XL port map( A0 => n6, A1 => n7, B0 => n8, B1 => n9, C0 => n10,
C1 => n11, Y => n5);
U16 : CLKINVX1 port map( A => n12, Y => n2);
U17 : OAI221X1 port map( A0 => n13, A1 => n3, B0 => n14, B1 => n1, C0 => n15
, Y => B(8));
U18 : AOI222XL port map( A0 => n6, A1 => n16, B0 => n8, B1 => n17, C0 => n10
, C1 => n18, Y => n15);
U19 : CLKINVX1 port map( A => n19, Y => n13);
U20 : OAI221X1 port map( A0 => n20, A1 => n3, B0 => n21, B1 => n1, C0 => n22
, Y => B(7));
U21 : AOI222XL port map( A0 => n6, A1 => n23, B0 => n8, B1 => n24, C0 => n10
, C1 => n25, Y => n22);
U22 : OAI221X1 port map( A0 => n26, A1 => n3, B0 => n27, B1 => n1, C0 => n28
, Y => B(6));
U23 : AOI222XL port map( A0 => n6, A1 => n29, B0 => n8, B1 => n30, C0 => n10
, C1 => n31, Y => n28);
U24 : OAI221X1 port map( A0 => n32, A1 => n3, B0 => n33, B1 => n1, C0 => n34
, Y => B(5));
U25 : AOI222XL port map( A0 => n6, A1 => n12, B0 => n8, B1 => n7, C0 => n10,
C1 => n9, Y => n34);
U26 : OAI221X1 port map( A0 => n35, A1 => n3, B0 => n36, B1 => n1, C0 => n37
, Y => B(4));
U27 : AOI222XL port map( A0 => n6, A1 => n19, B0 => n8, B1 => n16, C0 => n10
, C1 => n17, Y => n37);
U28 : OAI221X1 port map( A0 => n20, A1 => n38, B0 => n39, B1 => n1, C0 =>
n40, Y => B(3));
U29 : AOI222XL port map( A0 => n10, A1 => n24, B0 => n41, B1 => n42, C0 =>
n8, C1 => n23, Y => n40);
U30 : OAI221X1 port map( A0 => n43, A1 => n44, B0 => n45, B1 => n46, C0 =>
n47, Y => n42);
U31 : AOI22XL port map( A0 => A(4), A1 => n48, B0 => A(3), B1 => n49, Y =>
n47);
U32 : CLKINVX1 port map( A => n50, Y => n20);
U33 : OAI221X1 port map( A0 => n43, A1 => n51, B0 => n45, B1 => n52, C0 =>
n53, Y => n50);
U34 : AOI22XL port map( A0 => A(8), A1 => n48, B0 => A(7), B1 => n49, Y =>
n53);
U35 : AND2X1 port map( A => n54, B => n41, Y => B(31));
U36 : NOR2X1 port map( A => n55, B => n3, Y => B(30));
U37 : OAI221X1 port map( A0 => n26, A1 => n38, B0 => n56, B1 => n1, C0 =>
n57, Y => B(2));
U38 : AOI222XL port map( A0 => n10, A1 => n30, B0 => n41, B1 => n58, C0 =>
n8, C1 => n29, Y => n57);
U39 : OAI221X1 port map( A0 => n43, A1 => n46, B0 => n45, B1 => n59, C0 =>
n60, Y => n58);
U40 : AOI22XL port map( A0 => A(3), A1 => n48, B0 => A(2), B1 => n49, Y =>
n60);
U41 : CLKINVX1 port map( A => A(5), Y => n46);
U42 : CLKINVX1 port map( A => n61, Y => n26);
U43 : OAI221X1 port map( A0 => n43, A1 => n52, B0 => n45, B1 => n62, C0 =>
n63, Y => n61);
U44 : AOI22XL port map( A0 => A(7), A1 => n48, B0 => A(6), B1 => n49, Y =>
n63);
U45 : CLKINVX1 port map( A => A(9), Y => n52);
U46 : NOR2X1 port map( A => n64, B => n3, Y => B(29));
U47 : AND2X1 port map( A => n65, B => n41, Y => B(28));
U48 : NOR2X1 port map( A => SH(4), B => n67, Y => B(26));
U49 : NOR2X1 port map( A => SH(4), B => n4, Y => B(25));
U50 : AOI22XL port map( A0 => n68, A1 => n69, B0 => n70, B1 => n71, Y => n4)
;
U51 : NOR2X1 port map( A => SH(4), B => n14, Y => B(24));
U52 : AOI22XL port map( A0 => n72, A1 => n69, B0 => n65, B1 => n71, Y => n14
);
U53 : NOR2X1 port map( A => SH(4), B => n21, Y => B(23));
U54 : AOI222XL port map( A0 => n73, A1 => n71, B0 => n54, B1 => n74, C0 =>
n75, C1 => n69, Y => n21);
U55 : NOR2X1 port map( A => SH(4), B => n27, Y => B(22));
U56 : AOI222XL port map( A0 => n76, A1 => n71, B0 => n77, B1 => n74, C0 =>
n78, C1 => n69, Y => n27);
U57 : NOR2X1 port map( A => SH(4), B => n33, Y => B(21));
U58 : AOI222XL port map( A0 => n68, A1 => n71, B0 => n70, B1 => n74, C0 =>
n11, C1 => n69, Y => n33);
U59 : NOR2X1 port map( A => SH(4), B => n36, Y => B(20));
U60 : AOI222XL port map( A0 => n72, A1 => n71, B0 => n65, B1 => n74, C0 =>
n18, C1 => n69, Y => n36);
U61 : OAI221X1 port map( A0 => n32, A1 => n38, B0 => n79, B1 => n1, C0 =>
n80, Y => B(1));
U62 : AOI222XL port map( A0 => n10, A1 => n7, B0 => n41, B1 => n81, C0 => n8
, C1 => n12, Y => n80);
U63 : OAI221X1 port map( A0 => n43, A1 => n82, B0 => n45, B1 => n83, C0 =>
n84, Y => n12);
U64 : AOI22XL port map( A0 => A(10), A1 => n48, B0 => A(9), B1 => n49, Y =>
n84);
U65 : OAI221X1 port map( A0 => n43, A1 => n59, B0 => n45, B1 => n85, C0 =>
n86, Y => n81);
U66 : AOI22XL port map( A0 => A(2), A1 => n48, B0 => A(1), B1 => n49, Y =>
n86);
U67 : CLKINVX1 port map( A => A(4), Y => n59);
U68 : CLKINVX1 port map( A => n87, Y => n32);
U69 : OAI221X1 port map( A0 => n43, A1 => n62, B0 => n45, B1 => n88, C0 =>
n89, Y => n87);
U70 : AOI22XL port map( A0 => A(6), A1 => n48, B0 => A(5), B1 => n49, Y =>
n89);
U71 : CLKINVX1 port map( A => A(8), Y => n62);
U72 : NOR2X1 port map( A => SH(4), B => n39, Y => B(19));
U73 : AOI222XL port map( A0 => n25, A1 => n69, B0 => n75, B1 => n71, C0 =>
n90, C1 => SH(3), Y => n39);
U74 : NOR2X1 port map( A => SH(4), B => n56, Y => B(18));
U75 : AOI221XL port map( A0 => n78, A1 => n71, B0 => n31, B1 => n69, C0 =>
n91, Y => n56);
U76 : AO22X1 port map( A0 => n92, A1 => n77, B0 => n74, B1 => n76, Y => n91)
;
U77 : NOR2X1 port map( A => SH(4), B => n79, Y => B(17));
U78 : AOI221XL port map( A0 => n70, A1 => n92, B0 => n68, B1 => n74, C0 =>
n93, Y => n79);
U79 : AO22X1 port map( A0 => n71, A1 => n11, B0 => n69, B1 => n9, Y => n93);
U80 : NOR2X1 port map( A => SH(4), B => n94, Y => B(16));
U81 : CLKINVX1 port map( A => n95, Y => B(15));
U82 : AOI221XL port map( A0 => n25, A1 => n6, B0 => n24, B1 => n41, C0 =>
n96, Y => n95);
U83 : CLKINVX1 port map( A => n97, Y => n96);
U84 : AOI222XL port map( A0 => n10, A1 => n73, B0 => n98, B1 => n54, C0 =>
n8, C1 => n75, Y => n97);
U85 : CLKINVX1 port map( A => n99, Y => B(14));
U86 : AOI221XL port map( A0 => n31, A1 => n6, B0 => n30, B1 => n41, C0 =>
n100, Y => n99);
U87 : CLKINVX1 port map( A => n101, Y => n100);
U88 : AOI222XL port map( A0 => n10, A1 => n76, B0 => n98, B1 => n77, C0 =>
n8, C1 => n78, Y => n101);
U89 : CLKINVX1 port map( A => n102, Y => B(13));
U90 : AOI221XL port map( A0 => n9, A1 => n6, B0 => n7, B1 => n41, C0 => n103
, Y => n102);
U91 : CLKINVX1 port map( A => n104, Y => n103);
U92 : AOI222XL port map( A0 => n10, A1 => n68, B0 => n98, B1 => n70, C0 =>
n8, C1 => n11, Y => n104);
U93 : OAI221X1 port map( A0 => n43, A1 => n105, B0 => n45, B1 => n106, C0 =>
n107, Y => n11);
U94 : AOI22XL port map( A0 => A(22), A1 => n48, B0 => A(21), B1 => n49, Y =>
n107);
U95 : CLKINVX1 port map( A => n64, Y => n70);
U96 : AOI222XL port map( A0 => n48, A1 => A(30), B0 => n108, B1 => A(31), C0
=> n49, C1 => A(29), Y => n64);
U97 : CLKINVX1 port map( A => n45, Y => n108);
U98 : OAI221X1 port map( A0 => n43, A1 => n109, B0 => n45, B1 => n110, C0 =>
n111, Y => n68);
U99 : AOI22XL port map( A0 => A(26), A1 => n48, B0 => A(25), B1 => n49, Y =>
n111);
U100 : OAI221X1 port map( A0 => n43, A1 => n112, B0 => n45, B1 => n113, C0
=> n114, Y => n7);
U101 : AOI22XL port map( A0 => A(14), A1 => n48, B0 => A(13), B1 => n49, Y
=> n114);
U102 : OAI221X1 port map( A0 => n43, A1 => n115, B0 => n45, B1 => n116, C0
=> n117, Y => n9);
U103 : AOI22XL port map( A0 => A(18), A1 => n48, B0 => A(17), B1 => n49, Y
=> n117);
U104 : CLKINVX1 port map( A => n118, Y => B(12));
U105 : AOI221XL port map( A0 => n17, A1 => n6, B0 => n16, B1 => n41, C0 =>
n119, Y => n118);
U106 : CLKINVX1 port map( A => n120, Y => n119);
U107 : AOI222XL port map( A0 => n10, A1 => n72, B0 => n98, B1 => n65, C0 =>
n8, C1 => n18, Y => n120);
U108 : NOR2X1 port map( A => n1, B => n121, Y => n98);
U109 : OAI2B11X1 port map( A1N => n75, A0 => n122, B0 => n123, C0 => n124, Y
=> B(11));
U110 : AOI22XL port map( A0 => n6, A1 => n24, B0 => n41, B1 => n23, Y =>
n124);
U111 : OAI221X1 port map( A0 => n43, A1 => n125, B0 => n45, B1 => n126, C0
=> n127, Y => n23);
U112 : AOI22XL port map( A0 => A(12), A1 => n48, B0 => A(11), B1 => n49, Y
=> n127);
U113 : OAI221X1 port map( A0 => n43, A1 => n128, B0 => n45, B1 => n129, C0
=> n130, Y => n24);
U114 : AOI22XL port map( A0 => A(16), A1 => n48, B0 => A(15), B1 => n49, Y
=> n130);
U115 : AOI32XL port map( A0 => n90, A1 => n131, A2 => SH(4), B0 => n8, B1 =>
n25, Y => n123);
U116 : OAI221X1 port map( A0 => n43, A1 => n132, B0 => n45, B1 => n133, C0
=> n134, Y => n25);
U117 : AOI22XL port map( A0 => n48, A1 => A(20), B0 => n49, B1 => A(19), Y
=> n134);
U118 : CLKINVX1 port map( A => n66, Y => n90);
U119 : MXI2X1 port map( A => n54, B => n73, S0 => n135, Y => n66);
U120 : OAI221X1 port map( A0 => n43, A1 => n136, B0 => n45, B1 => n137, C0
=> n138, Y => n73);
U121 : AOI22XL port map( A0 => A(28), A1 => n48, B0 => A(27), B1 => n49, Y
=> n138);
U122 : NOR2BX1 port map( AN => n49, B => n139, Y => n54);
U123 : OAI221X1 port map( A0 => n43, A1 => n140, B0 => n45, B1 => n141, C0
=> n142, Y => n75);
U124 : AOI22XL port map( A0 => A(24), A1 => n48, B0 => A(23), B1 => n49, Y
=> n142);
U125 : OAI221X1 port map( A0 => n143, A1 => n3, B0 => n67, B1 => n1, C0 =>
n144, Y => B(10));
U126 : AOI222XL port map( A0 => n6, A1 => n30, B0 => n8, B1 => n31, C0 =>
n10, C1 => n78, Y => n144);
U127 : OAI221X1 port map( A0 => n43, A1 => n141, B0 => n45, B1 => n105, C0
=> n145, Y => n78);
U128 : AOI22XL port map( A0 => A(23), A1 => n48, B0 => A(22), B1 => n49, Y
=> n145);
U129 : CLKINVX1 port map( A => A(24), Y => n105);
U130 : CLKINVX1 port map( A => A(25), Y => n141);
U131 : OAI221X1 port map( A0 => n43, A1 => n133, B0 => n115, B1 => n45, C0
=> n146, Y => n31);
U132 : AOI22XL port map( A0 => n48, A1 => A(19), B0 => n49, B1 => A(18), Y
=> n146);
U133 : CLKINVX1 port map( A => A(20), Y => n115);
U134 : CLKINVX1 port map( A => A(21), Y => n133);
U135 : OAI221X1 port map( A0 => n43, A1 => n129, B0 => n45, B1 => n112, C0
=> n147, Y => n30);
U136 : AOI22XL port map( A0 => A(15), A1 => n48, B0 => A(14), B1 => n49, Y
=> n147);
U137 : CLKINVX1 port map( A => A(16), Y => n112);
U138 : CLKINVX1 port map( A => A(17), Y => n129);
U139 : CLKINVX1 port map( A => n38, Y => n6);
U140 : AOI22XL port map( A0 => n76, A1 => n69, B0 => n77, B1 => n71, Y =>
n67);
U141 : CLKINVX1 port map( A => n55, Y => n77);
U142 : AOI22XL port map( A0 => n49, A1 => A(30), B0 => n48, B1 => A(31), Y
=> n55);
U143 : OAI221X1 port map( A0 => n43, A1 => n137, B0 => n45, B1 => n109, C0
=> n148, Y => n76);
U144 : AOI22XL port map( A0 => A(27), A1 => n48, B0 => A(26), B1 => n49, Y
=> n148);
U145 : CLKINVX1 port map( A => A(28), Y => n109);
U146 : CLKINVX1 port map( A => A(29), Y => n137);
U147 : CLKINVX1 port map( A => n41, Y => n3);
U148 : CLKINVX1 port map( A => n29, Y => n143);
U149 : OAI221X1 port map( A0 => n43, A1 => n126, B0 => n45, B1 => n82, C0 =>
n149, Y => n29);
U150 : AOI22XL port map( A0 => A(11), A1 => n48, B0 => A(10), B1 => n49, Y
=> n149);
U151 : CLKINVX1 port map( A => A(12), Y => n82);
U152 : CLKINVX1 port map( A => A(13), Y => n126);
U153 : OAI221X1 port map( A0 => n35, A1 => n38, B0 => n94, B1 => n1, C0 =>
n150, Y => B(0));
U154 : AOI222XL port map( A0 => n10, A1 => n16, B0 => n41, B1 => n151, C0 =>
n8, C1 => n19, Y => n150);
U155 : OAI221X1 port map( A0 => n43, A1 => n83, B0 => n45, B1 => n51, C0 =>
n152, Y => n19);
U156 : AOI22XL port map( A0 => A(9), A1 => n48, B0 => A(8), B1 => n49, Y =>
n152);
U157 : CLKINVX1 port map( A => A(10), Y => n51);
U158 : CLKINVX1 port map( A => A(11), Y => n83);
U159 : AND2X1 port map( A => n153, B => n135, Y => n8);
U160 : OAI221X1 port map( A0 => n43, A1 => n85, B0 => n45, B1 => n154, C0 =>
n155, Y => n151);
U161 : AOI22XL port map( A0 => A(1), A1 => n48, B0 => A(0), B1 => n49, Y =>
n155);
U162 : CLKINVX1 port map( A => A(2), Y => n154);
U163 : CLKINVX1 port map( A => A(3), Y => n85);
U164 : NOR2X1 port map( A => n121, B => SH(4), Y => n41);
U165 : CLKINVX1 port map( A => n69, Y => n121);
U166 : OAI221X1 port map( A0 => n43, A1 => n113, B0 => n45, B1 => n125, C0
=> n156, Y => n16);
U167 : AOI22XL port map( A0 => A(13), A1 => n48, B0 => A(12), B1 => n49, Y
=> n156);
U168 : CLKINVX1 port map( A => A(14), Y => n125);
U169 : CLKINVX1 port map( A => A(15), Y => n113);
U170 : CLKINVX1 port map( A => n122, Y => n10);
U171 : NOR2X1 port map( A => n131, B => SH(4), Y => n153);
U172 : AOI221XL port map( A0 => n18, A1 => n71, B0 => n17, B1 => n69, C0 =>
n157, Y => n94);
U173 : AO22X1 port map( A0 => n92, A1 => n65, B0 => n74, B1 => n72, Y =>
n157);
U174 : OAI221X1 port map( A0 => n43, A1 => n110, B0 => n45, B1 => n140, C0
=> n158, Y => n72);
U175 : AOI22XL port map( A0 => A(25), A1 => n48, B0 => A(24), B1 => n49, Y
=> n158);
U176 : CLKINVX1 port map( A => A(26), Y => n140);
U177 : CLKINVX1 port map( A => A(27), Y => n110);
U178 : OAI221X1 port map( A0 => n43, A1 => n139, B0 => n45, B1 => n136, C0
=> n159, Y => n65);
U179 : AOI22XL port map( A0 => A(29), A1 => n48, B0 => A(28), B1 => n49, Y
=> n159);
U180 : CLKINVX1 port map( A => A(30), Y => n136);
U181 : CLKINVX1 port map( A => A(31), Y => n139);
U182 : NOR2X1 port map( A => n135, B => n131, Y => n92);
U183 : OAI221X1 port map( A0 => n43, A1 => n116, B0 => n45, B1 => n128, C0
=> n160, Y => n17);
U184 : AOI22XL port map( A0 => A(17), A1 => n48, B0 => A(16), B1 => n49, Y
=> n160);
U185 : CLKINVX1 port map( A => A(18), Y => n128);
U186 : CLKINVX1 port map( A => A(19), Y => n116);
U187 : OAI221X1 port map( A0 => n43, A1 => n106, B0 => n45, B1 => n132, C0
=> n161, Y => n18);
U188 : AOI22XL port map( A0 => A(21), A1 => n48, B0 => n49, B1 => A(20), Y
=> n161);
U189 : CLKINVX1 port map( A => A(22), Y => n132);
U190 : CLKINVX1 port map( A => A(23), Y => n106);
U191 : CLKNAND2X2 port map( A => n71, B => n1, Y => n38);
U192 : CLKINVX1 port map( A => n162, Y => n35);
U193 : OAI221X1 port map( A0 => n43, A1 => n88, B0 => n45, B1 => n44, C0 =>
n163, Y => n162);
U194 : AOI22XL port map( A0 => A(5), A1 => n48, B0 => A(4), B1 => n49, Y =>
n163);
U195 : NOR2X1 port map( A => SH(0), B => SH(1), Y => n49);
U196 : NOR2X1 port map( A => n164, B => SH(1), Y => n48);
U197 : CLKINVX1 port map( A => A(6), Y => n44);
U198 : CLKINVX1 port map( A => A(7), Y => n88);
end SYN_mx2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32_DW_sla_0 is
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31 downto
0));
end SHIFTER_GENERIC_N32_DW_sla_0;
architecture SYN_mx2 of SHIFTER_GENERIC_N32_DW_sla_0 is
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component AOI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI221X1
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI211XL
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component MXI2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OA21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component AND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component AOI21XL
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component NAND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
signal B_31_port, B_30_port, B_29_port, B_28_port, B_27_port, B_26_port,
B_25_port, B_24_port, B_23_port, B_22_port, B_21_port, B_20_port,
B_19_port, B_18_port, B_17_port, B_16_port, B_15_port, B_14_port,
B_13_port, B_12_port, B_11_port, B_10_port, B_9_port, B_8_port, B_7_port,
B_6_port, B_5_port, B_4_port, B_3_port, B_2_port, B_1_port, n1, n2, n3,
n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34
, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63
, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92
, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128, n129,
n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179 : std_logic;
begin
B <= ( B_31_port, B_30_port, B_29_port, B_28_port, B_27_port, B_26_port,
B_25_port, B_24_port, B_23_port, B_22_port, B_21_port, B_20_port,
B_19_port, B_18_port, B_17_port, B_16_port, B_15_port, B_14_port,
B_13_port, B_12_port, B_11_port, B_10_port, B_9_port, B_8_port, B_7_port,
B_6_port, B_5_port, B_4_port, B_3_port, B_2_port, B_1_port, A(0) );
U2 : NAND2X1 port map( A => SH(0), B => SH(1), Y => n22);
U3 : NOR2XL port map( A => SH(2), B => SH(3), Y => n75);
U4 : NOR2XL port map( A => n134, B => SH(3), Y => n73);
U5 : NAND2XL port map( A => SH(3), B => n134, Y => n70);
U6 : INVXL port map( A => SH(2), Y => n134);
U7 : NAND2XL port map( A => SH(2), B => n84, Y => n71);
U8 : NAND2XL port map( A => SH(2), B => SH(3), Y => n139);
U9 : AOI21XL port map( A0 => A(0), A1 => SH(2), B0 => n84, Y => n112);
U10 : INVXL port map( A => SH(3), Y => n135);
U11 : AND2XL port map( A => n133, B => SH(2), Y => n14);
U12 : INVX2 port map( A => SH(4), Y => n1);
U13 : OAI21X1 port map( A0 => SH(4), A1 => n2, B0 => n3, Y => B_9_port);
U14 : OAI21X1 port map( A0 => SH(4), A1 => n4, B0 => n3, Y => B_8_port);
U15 : OAI21X1 port map( A0 => SH(4), A1 => n5, B0 => n3, Y => B_7_port);
U16 : OAI21X1 port map( A0 => SH(4), A1 => n6, B0 => n3, Y => B_6_port);
U17 : OAI21X1 port map( A0 => SH(4), A1 => n7, B0 => n3, Y => B_5_port);
U18 : OAI21X1 port map( A0 => SH(4), A1 => n8, B0 => n3, Y => B_4_port);
U19 : OAI21X1 port map( A0 => SH(4), A1 => n9, B0 => n3, Y => B_3_port);
U20 : OAI221X1 port map( A0 => n10, A1 => n11, B0 => n12, B1 => n1, C0 =>
n13, Y => B_31_port);
U21 : AOI222XL port map( A0 => n14, A1 => n15, B0 => n16, B1 => n17, C0 =>
n18, C1 => n19, Y => n13);
U22 : OAI221X1 port map( A0 => n20, A1 => n21, B0 => n22, B1 => n23, C0 =>
n24, Y => n17);
U23 : AOI22XL port map( A0 => A(30), A1 => n25, B0 => A(31), B1 => n26, Y =>
n24);
U24 : CLKINVX1 port map( A => A(29), Y => n21);
U25 : OAI221X1 port map( A0 => n27, A1 => n11, B0 => n28, B1 => n1, C0 =>
n29, Y => B_30_port);
U26 : AOI222XL port map( A0 => n14, A1 => n30, B0 => n16, B1 => n31, C0 =>
n18, C1 => n32, Y => n29);
U27 : OAI221X1 port map( A0 => n20, A1 => n23, B0 => n22, B1 => n33, C0 =>
n34, Y => n31);
U28 : AOI22XL port map( A0 => A(29), A1 => n25, B0 => A(30), B1 => n26, Y =>
n34);
U29 : CLKINVX1 port map( A => A(28), Y => n23);
U30 : OAI21X1 port map( A0 => SH(4), A1 => n35, B0 => n3, Y => B_2_port);
U31 : OAI221X1 port map( A0 => n36, A1 => n11, B0 => n37, B1 => n1, C0 =>
n38, Y => B_29_port);
U32 : AOI222XL port map( A0 => n14, A1 => n39, B0 => n16, B1 => n40, C0 =>
n18, C1 => n41, Y => n38);
U33 : OAI221X1 port map( A0 => n20, A1 => n33, B0 => n22, B1 => n42, C0 =>
n43, Y => n40);
U34 : AOI22XL port map( A0 => A(28), A1 => n25, B0 => A(29), B1 => n26, Y =>
n43);
U35 : CLKINVX1 port map( A => A(27), Y => n33);
U36 : OAI221X1 port map( A0 => n44, A1 => n11, B0 => n45, B1 => n1, C0 =>
n46, Y => B_28_port);
U37 : AOI222XL port map( A0 => n14, A1 => n47, B0 => n16, B1 => n48, C0 =>
n18, C1 => n49, Y => n46);
U38 : OAI221X1 port map( A0 => n20, A1 => n42, B0 => n22, B1 => n50, C0 =>
n51, Y => n48);
U39 : AOI22XL port map( A0 => A(27), A1 => n25, B0 => A(28), B1 => n26, Y =>
n51);
U40 : CLKINVX1 port map( A => A(26), Y => n42);
U41 : OAI221X1 port map( A0 => n10, A1 => n52, B0 => n53, B1 => n1, C0 =>
n54, Y => B_27_port);
U42 : AOI222XL port map( A0 => n55, A1 => n19, B0 => n18, B1 => n15, C0 =>
n14, C1 => n56, Y => n54);
U43 : CLKINVX1 port map( A => n57, Y => n10);
U44 : OAI221X1 port map( A0 => n20, A1 => n50, B0 => n22, B1 => n58, C0 =>
n59, Y => n57);
U45 : AOI22XL port map( A0 => A(26), A1 => n25, B0 => A(27), B1 => n26, Y =>
n59);
U46 : CLKINVX1 port map( A => A(25), Y => n50);
U47 : OAI221X1 port map( A0 => n27, A1 => n52, B0 => n60, B1 => n1, C0 =>
n61, Y => B_26_port);
U48 : AOI222XL port map( A0 => n55, A1 => n32, B0 => n18, B1 => n30, C0 =>
n14, C1 => n62, Y => n61);
U49 : CLKINVX1 port map( A => n63, Y => n27);
U50 : OAI221X1 port map( A0 => n20, A1 => n58, B0 => n22, B1 => n64, C0 =>
n65, Y => n63);
U51 : AOI22XL port map( A0 => A(25), A1 => n25, B0 => A(26), B1 => n26, Y =>
n65);
U52 : CLKINVX1 port map( A => A(24), Y => n58);
U53 : OAI221X1 port map( A0 => n36, A1 => n52, B0 => n2, B1 => n1, C0 => n66
, Y => B_25_port);
U54 : AOI222XL port map( A0 => n55, A1 => n41, B0 => n18, B1 => n39, C0 =>
n14, C1 => n67, Y => n66);
U55 : CLKINVX1 port map( A => n68, Y => n2);
U56 : OAI211XL port map( A0 => n69, A1 => n70, B0 => n71, C0 => n72, Y =>
n68);
U57 : AOI22XL port map( A0 => n73, A1 => n74, B0 => n75, B1 => n76, Y => n72
);
U58 : CLKINVX1 port map( A => n77, Y => n36);
U59 : OAI221X1 port map( A0 => n20, A1 => n64, B0 => n22, B1 => n78, C0 =>
n79, Y => n77);
U60 : AOI22XL port map( A0 => A(24), A1 => n25, B0 => A(25), B1 => n26, Y =>
n79);
U61 : CLKINVX1 port map( A => A(23), Y => n64);
U62 : OAI221X1 port map( A0 => n44, A1 => n52, B0 => n4, B1 => n1, C0 => n80
, Y => B_24_port);
U63 : AOI222XL port map( A0 => n55, A1 => n49, B0 => n18, B1 => n47, C0 =>
n14, C1 => n81, Y => n80);
U64 : AOI221XL port map( A0 => n82, A1 => n73, B0 => n83, B1 => n75, C0 =>
n84, Y => n4);
U65 : CLKINVX1 port map( A => n85, Y => n44);
U66 : OAI221X1 port map( A0 => n20, A1 => n78, B0 => n22, B1 => n86, C0 =>
n87, Y => n85);
U67 : AOI22XL port map( A0 => A(23), A1 => n25, B0 => A(24), B1 => n26, Y =>
n87);
U68 : CLKINVX1 port map( A => A(22), Y => n78);
U69 : OAI221X1 port map( A0 => n88, A1 => n52, B0 => n5, B1 => n1, C0 => n89
, Y => B_23_port);
U70 : AOI222XL port map( A0 => n55, A1 => n15, B0 => n18, B1 => n56, C0 =>
n14, C1 => n90, Y => n89);
U71 : AOI221XL port map( A0 => n91, A1 => n73, B0 => n92, B1 => n75, C0 =>
n84, Y => n5);
U72 : CLKINVX1 port map( A => n19, Y => n88);
U73 : OAI221X1 port map( A0 => n20, A1 => n86, B0 => n22, B1 => n93, C0 =>
n94, Y => n19);
U74 : AOI22XL port map( A0 => A(22), A1 => n25, B0 => A(23), B1 => n26, Y =>
n94);
U75 : CLKINVX1 port map( A => A(21), Y => n86);
U76 : OAI221X1 port map( A0 => n95, A1 => n52, B0 => n6, B1 => n1, C0 => n96
, Y => B_22_port);
U77 : AOI222XL port map( A0 => n55, A1 => n30, B0 => n18, B1 => n62, C0 =>
n14, C1 => n97, Y => n96);
U78 : AOI221XL port map( A0 => n98, A1 => n73, B0 => n99, B1 => n75, C0 =>
n84, Y => n6);
U79 : CLKINVX1 port map( A => n100, Y => n98);
U80 : CLKINVX1 port map( A => n32, Y => n95);
U81 : OAI221X1 port map( A0 => n20, A1 => n93, B0 => n22, B1 => n101, C0 =>
n102, Y => n32);
U82 : AOI22XL port map( A0 => A(21), A1 => n25, B0 => A(22), B1 => n26, Y =>
n102);
U83 : CLKINVX1 port map( A => A(20), Y => n93);
U84 : OAI221X1 port map( A0 => n103, A1 => n52, B0 => n7, B1 => n1, C0 =>
n104, Y => B_21_port);
U85 : AOI222XL port map( A0 => n55, A1 => n39, B0 => n18, B1 => n67, C0 =>
n14, C1 => n76, Y => n104);
U86 : AOI221XL port map( A0 => n105, A1 => n73, B0 => n74, B1 => n75, C0 =>
n84, Y => n7);
U87 : CLKINVX1 port map( A => n41, Y => n103);
U88 : OAI221X1 port map( A0 => n20, A1 => n101, B0 => n22, B1 => n106, C0 =>
n107, Y => n41);
U89 : AOI22XL port map( A0 => A(20), A1 => n25, B0 => A(21), B1 => n26, Y =>
n107);
U90 : CLKINVX1 port map( A => A(19), Y => n101);
U91 : OAI221X1 port map( A0 => n108, A1 => n52, B0 => n8, B1 => n1, C0 =>
n109, Y => B_20_port);
U92 : AOI222XL port map( A0 => n55, A1 => n47, B0 => n18, B1 => n81, C0 =>
n14, C1 => n83, Y => n109);
U93 : OA21X1 port map( A0 => n110, A1 => n111, B0 => n112, Y => n8);
U94 : CLKINVX1 port map( A => n49, Y => n108);
U95 : OAI221X1 port map( A0 => n20, A1 => n106, B0 => n22, B1 => n113, C0 =>
n114, Y => n49);
U96 : AOI22XL port map( A0 => A(19), A1 => n25, B0 => A(20), B1 => n26, Y =>
n114);
U97 : CLKINVX1 port map( A => A(18), Y => n106);
U98 : OAI21X1 port map( A0 => SH(4), A1 => n115, B0 => n3, Y => B_1_port);
U99 : OAI221X1 port map( A0 => n116, A1 => n52, B0 => n9, B1 => n1, C0 =>
n117, Y => B_19_port);
U100 : AOI222XL port map( A0 => n55, A1 => n56, B0 => n18, B1 => n90, C0 =>
n14, C1 => n92, Y => n117);
U101 : OA21X1 port map( A0 => n118, A1 => n111, B0 => n112, Y => n9);
U102 : CLKINVX1 port map( A => n15, Y => n116);
U103 : OAI221X1 port map( A0 => n20, A1 => n113, B0 => n22, B1 => n119, C0
=> n120, Y => n15);
U104 : AOI22XL port map( A0 => A(18), A1 => n25, B0 => A(19), B1 => n26, Y
=> n120);
U105 : CLKINVX1 port map( A => A(17), Y => n113);
U106 : OAI221X1 port map( A0 => n121, A1 => n52, B0 => n35, B1 => n1, C0 =>
n122, Y => B_18_port);
U107 : AOI222XL port map( A0 => n55, A1 => n62, B0 => n18, B1 => n97, C0 =>
n14, C1 => n99, Y => n122);
U108 : OA21X1 port map( A0 => n100, A1 => n111, B0 => n112, Y => n35);
U109 : CLKINVX1 port map( A => n30, Y => n121);
U110 : OAI221X1 port map( A0 => n20, A1 => n119, B0 => n22, B1 => n123, C0
=> n124, Y => n30);
U111 : AOI22XL port map( A0 => A(17), A1 => n25, B0 => A(18), B1 => n26, Y
=> n124);
U112 : CLKINVX1 port map( A => A(16), Y => n119);
U113 : OAI221X1 port map( A0 => n125, A1 => n52, B0 => n115, B1 => n1, C0 =>
n126, Y => B_17_port);
U114 : AOI222XL port map( A0 => n55, A1 => n67, B0 => n18, B1 => n76, C0 =>
n14, C1 => n74, Y => n126);
U115 : OA21X1 port map( A0 => n69, A1 => n111, B0 => n112, Y => n115);
U116 : CLKINVX1 port map( A => n16, Y => n52);
U117 : CLKINVX1 port map( A => n39, Y => n125);
U118 : OAI221X1 port map( A0 => n20, A1 => n123, B0 => n22, B1 => n127, C0
=> n128, Y => n39);
U119 : AOI22XL port map( A0 => A(16), A1 => n25, B0 => A(17), B1 => n26, Y
=> n128);
U120 : CLKINVX1 port map( A => A(15), Y => n123);
U121 : CLKINVX1 port map( A => n129, Y => B_16_port);
U122 : AOI221XL port map( A0 => n81, A1 => n55, B0 => n47, B1 => n16, C0 =>
n130, Y => n129);
U123 : CLKINVX1 port map( A => n131, Y => n130);
U124 : AOI221XL port map( A0 => n14, A1 => n82, B0 => n18, B1 => n83, C0 =>
n132, Y => n131);
U125 : AND2X1 port map( A => n133, B => n134, Y => n18);
U126 : NOR2X1 port map( A => n135, B => SH(4), Y => n133);
U127 : NOR2X1 port map( A => n111, B => SH(4), Y => n16);
U128 : CLKINVX1 port map( A => n75, Y => n111);
U129 : OAI221X1 port map( A0 => n20, A1 => n127, B0 => n22, B1 => n136, C0
=> n137, Y => n47);
U130 : AOI22XL port map( A0 => A(15), A1 => n25, B0 => A(16), B1 => n26, Y
=> n137);
U131 : CLKINVX1 port map( A => A(14), Y => n127);
U132 : CLKINVX1 port map( A => n11, Y => n55);
U133 : CLKNAND2X2 port map( A => n73, B => n1, Y => n11);
U134 : OAI21X1 port map( A0 => SH(4), A1 => n12, B0 => n3, Y => B_15_port);
U135 : CLKINVX1 port map( A => n138, Y => n12);
U136 : OAI221X1 port map( A0 => n118, A1 => n139, B0 => n140, B1 => n70, C0
=> n141, Y => n138);
U137 : AOI22XL port map( A0 => n73, A1 => n90, B0 => n75, B1 => n56, Y =>
n141);
U138 : OAI221X1 port map( A0 => n20, A1 => n136, B0 => n22, B1 => n142, C0
=> n143, Y => n56);
U139 : AOI22XL port map( A0 => A(14), A1 => n25, B0 => A(15), B1 => n26, Y
=> n143);
U140 : CLKINVX1 port map( A => A(13), Y => n136);
U141 : CLKINVX1 port map( A => n92, Y => n140);
U142 : OAI21X1 port map( A0 => SH(4), A1 => n28, B0 => n3, Y => B_14_port);
U143 : CLKINVX1 port map( A => n144, Y => n28);
U144 : OAI221X1 port map( A0 => n100, A1 => n139, B0 => n145, B1 => n70, C0
=> n146, Y => n144);
U145 : AOI22XL port map( A0 => n73, A1 => n97, B0 => n75, B1 => n62, Y =>
n146);
U146 : OAI221X1 port map( A0 => n20, A1 => n142, B0 => n22, B1 => n147, C0
=> n148, Y => n62);
U147 : AOI22XL port map( A0 => A(13), A1 => n25, B0 => A(14), B1 => n26, Y
=> n148);
U148 : CLKINVX1 port map( A => A(12), Y => n142);
U149 : CLKINVX1 port map( A => n99, Y => n145);
U150 : OAI21X1 port map( A0 => SH(4), A1 => n37, B0 => n3, Y => B_13_port);
U151 : CLKINVX1 port map( A => n149, Y => n37);
U152 : OAI221X1 port map( A0 => n69, A1 => n139, B0 => n150, B1 => n70, C0
=> n151, Y => n149);
U153 : AOI22XL port map( A0 => n73, A1 => n76, B0 => n75, B1 => n67, Y =>
n151);
U154 : OAI221X1 port map( A0 => n20, A1 => n147, B0 => n22, B1 => n152, C0
=> n153, Y => n67);
U155 : AOI22XL port map( A0 => A(12), A1 => n25, B0 => A(13), B1 => n26, Y
=> n153);
U156 : CLKINVX1 port map( A => A(11), Y => n147);
U157 : OAI221X1 port map( A0 => n20, A1 => n154, B0 => n22, B1 => n155, C0
=> n156, Y => n76);
U158 : AOI22XL port map( A0 => A(8), A1 => n25, B0 => A(9), B1 => n26, Y =>
n156);
U159 : CLKINVX1 port map( A => n74, Y => n150);
U160 : OAI221X1 port map( A0 => n20, A1 => n157, B0 => n22, B1 => n158, C0
=> n159, Y => n74);
U161 : AOI22XL port map( A0 => A(4), A1 => n25, B0 => A(5), B1 => n26, Y =>
n159);
U162 : CLKINVX1 port map( A => n105, Y => n69);
U163 : MXI2X1 port map( A => n160, B => n161, S0 => n26, Y => n105);
U164 : OAI21X1 port map( A0 => SH(4), A1 => n45, B0 => n3, Y => B_12_port);
U165 : CLKINVX1 port map( A => n162, Y => n45);
U166 : OAI211XL port map( A0 => n110, A1 => n70, B0 => n71, C0 => n163, Y =>
n162);
U167 : AOI22XL port map( A0 => n73, A1 => n83, B0 => n75, B1 => n81, Y =>
n163);
U168 : OAI221X1 port map( A0 => n20, A1 => n152, B0 => n22, B1 => n164, C0
=> n165, Y => n81);
U169 : AOI22XL port map( A0 => A(11), A1 => n25, B0 => A(12), B1 => n26, Y
=> n165);
U170 : CLKINVX1 port map( A => A(10), Y => n152);
U171 : OAI221X1 port map( A0 => n20, A1 => n155, B0 => n22, B1 => n166, C0
=> n167, Y => n83);
U172 : AOI22XL port map( A0 => A(7), A1 => n25, B0 => A(8), B1 => n26, Y =>
n167);
U173 : CLKINVX1 port map( A => A(6), Y => n155);
U174 : CLKINVX1 port map( A => n82, Y => n110);
U175 : OAI221X1 port map( A0 => n20, A1 => n158, B0 => n161, B1 => n22, C0
=> n168, Y => n82);
U176 : AOI22XL port map( A0 => n25, A1 => A(3), B0 => A(4), B1 => n26, Y =>
n168);
U177 : CLKINVX1 port map( A => A(2), Y => n158);
U178 : OAI21X1 port map( A0 => SH(4), A1 => n53, B0 => n3, Y => B_11_port);
U179 : CLKINVX1 port map( A => n169, Y => n53);
U180 : OAI211XL port map( A0 => n118, A1 => n70, B0 => n71, C0 => n170, Y =>
n169);
U181 : AOI22XL port map( A0 => n73, A1 => n92, B0 => n75, B1 => n90, Y =>
n170);
U182 : OAI221X1 port map( A0 => n20, A1 => n164, B0 => n22, B1 => n171, C0
=> n172, Y => n90);
U183 : AOI22XL port map( A0 => A(10), A1 => n25, B0 => A(11), B1 => n26, Y
=> n172);
U184 : CLKINVX1 port map( A => A(9), Y => n164);
U185 : OAI221X1 port map( A0 => n20, A1 => n166, B0 => n22, B1 => n173, C0
=> n174, Y => n92);
U186 : AOI22XL port map( A0 => A(6), A1 => n25, B0 => A(7), B1 => n26, Y =>
n174);
U187 : CLKINVX1 port map( A => A(5), Y => n166);
U188 : CLKINVX1 port map( A => n91, Y => n118);
U189 : OAI221X1 port map( A0 => n161, A1 => n20, B0 => n160, B1 => n22, C0
=> n175, Y => n91);
U190 : AOI22XL port map( A0 => n25, A1 => A(2), B0 => A(3), B1 => n26, Y =>
n175);
U191 : CLKINVX1 port map( A => A(1), Y => n161);
U192 : OAI21X1 port map( A0 => SH(4), A1 => n60, B0 => n3, Y => B_10_port);
U193 : CLKINVX1 port map( A => n132, Y => n3);
U194 : NOR2X1 port map( A => n1, B => n160, Y => n132);
U195 : CLKINVX1 port map( A => n176, Y => n60);
U196 : OAI211XL port map( A0 => n100, A1 => n70, B0 => n71, C0 => n177, Y =>
n176);
U197 : AOI22XL port map( A0 => n73, A1 => n99, B0 => n75, B1 => n97, Y =>
n177);
U198 : OAI221X1 port map( A0 => n20, A1 => n171, B0 => n22, B1 => n154, C0
=> n178, Y => n97);
U199 : AOI22XL port map( A0 => A(9), A1 => n25, B0 => A(10), B1 => n26, Y =>
n178);
U200 : CLKINVX1 port map( A => A(7), Y => n154);
U201 : CLKINVX1 port map( A => A(8), Y => n171);
U202 : OAI221X1 port map( A0 => n20, A1 => n173, B0 => n157, B1 => n22, C0
=> n179, Y => n99);
U203 : AOI22XL port map( A0 => A(5), A1 => n25, B0 => A(6), B1 => n26, Y =>
n179);
U204 : CLKINVX1 port map( A => A(3), Y => n157);
U205 : CLKINVX1 port map( A => A(4), Y => n173);
U206 : NAND2BX1 port map( AN => SH(0), B => SH(1), Y => n20);
U207 : NOR2X1 port map( A => n135, B => n160, Y => n84);
U208 : CLKINVX1 port map( A => A(0), Y => n160);
U209 : AOI222XL port map( A0 => n26, A1 => A(2), B0 => A(1), B1 => n25, C0
=> A(0), C1 => SH(1), Y => n100);
U210 : NOR2BX1 port map( AN => SH(0), B => SH(1), Y => n25);
U211 : NOR2X1 port map( A => SH(0), B => SH(1), Y => n26);
end SYN_mx2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32_DW01_ash_0 is
port( A : in std_logic_vector (31 downto 0); DATA_TC : in std_logic; SH :
in std_logic_vector (4 downto 0); SH_TC : in std_logic; B : out
std_logic_vector (31 downto 0));
end SHIFTER_GENERIC_N32_DW01_ash_0;
architecture SYN_mx2 of SHIFTER_GENERIC_N32_DW01_ash_0 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component MX2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
signal SHMAG_3_port, SHMAG_2_port, SHMAG_1_port, SHMAG_0_port,
ML_int_1_31_port, ML_int_1_30_port, ML_int_1_29_port, ML_int_1_28_port,
ML_int_1_27_port, ML_int_1_26_port, ML_int_1_25_port, ML_int_1_24_port,
ML_int_1_23_port, ML_int_1_22_port, ML_int_1_21_port, ML_int_1_20_port,
ML_int_1_19_port, ML_int_1_18_port, ML_int_1_17_port, ML_int_1_16_port,
ML_int_1_15_port, ML_int_1_14_port, ML_int_1_13_port, ML_int_1_12_port,
ML_int_1_11_port, ML_int_1_10_port, ML_int_1_9_port, ML_int_1_8_port,
ML_int_1_7_port, ML_int_1_6_port, ML_int_1_5_port, ML_int_1_4_port,
ML_int_1_3_port, ML_int_1_2_port, ML_int_1_1_port, ML_int_1_0_port,
ML_int_2_31_port, ML_int_2_30_port, ML_int_2_29_port, ML_int_2_28_port,
ML_int_2_27_port, ML_int_2_26_port, ML_int_2_25_port, ML_int_2_24_port,
ML_int_2_23_port, ML_int_2_22_port, ML_int_2_21_port, ML_int_2_20_port,
ML_int_2_19_port, ML_int_2_18_port, ML_int_2_17_port, ML_int_2_16_port,
ML_int_2_15_port, ML_int_2_14_port, ML_int_2_13_port, ML_int_2_12_port,
ML_int_2_11_port, ML_int_2_10_port, ML_int_2_9_port, ML_int_2_8_port,
ML_int_2_7_port, ML_int_2_6_port, ML_int_2_5_port, ML_int_2_4_port,
ML_int_2_3_port, ML_int_2_2_port, ML_int_2_1_port, ML_int_2_0_port,
ML_int_3_31_port, ML_int_3_30_port, ML_int_3_29_port, ML_int_3_28_port,
ML_int_3_27_port, ML_int_3_26_port, ML_int_3_25_port, ML_int_3_24_port,
ML_int_3_23_port, ML_int_3_22_port, ML_int_3_21_port, ML_int_3_20_port,
ML_int_3_19_port, ML_int_3_18_port, ML_int_3_17_port, ML_int_3_16_port,
ML_int_3_15_port, ML_int_3_14_port, ML_int_3_13_port, ML_int_3_12_port,
ML_int_3_11_port, ML_int_3_10_port, ML_int_3_9_port, ML_int_3_8_port,
ML_int_3_7_port, ML_int_3_6_port, ML_int_3_5_port, ML_int_3_4_port,
ML_int_3_3_port, ML_int_3_2_port, ML_int_3_1_port, ML_int_3_0_port,
ML_int_4_31_port, ML_int_4_30_port, ML_int_4_29_port, ML_int_4_28_port,
ML_int_4_27_port, ML_int_4_26_port, ML_int_4_25_port, ML_int_4_24_port,
ML_int_4_23_port, ML_int_4_22_port, ML_int_4_21_port, ML_int_4_20_port,
ML_int_4_19_port, ML_int_4_18_port, ML_int_4_17_port, ML_int_4_16_port,
ML_int_4_15_port, ML_int_4_14_port, ML_int_4_13_port, ML_int_4_12_port,
ML_int_4_11_port, ML_int_4_10_port, ML_int_4_9_port, ML_int_4_8_port,
ML_int_4_7_port, ML_int_4_6_port, ML_int_4_5_port, ML_int_4_4_port,
ML_int_4_3_port, ML_int_4_2_port, ML_int_4_1_port, ML_int_4_0_port, n1,
n2, n3, n4, n5, n6, n7, n8 : std_logic;
begin
M1_0_31 : MX2XL port map( A => A(31), B => A(30), S0 => SH(0), Y =>
ML_int_1_31_port);
M1_1_31 : MX2XL port map( A => ML_int_1_31_port, B => ML_int_1_29_port, S0
=> SH(1), Y => ML_int_2_31_port);
M1_2_31 : MX2XL port map( A => ML_int_2_31_port, B => ML_int_2_27_port, S0
=> SH(2), Y => ML_int_3_31_port);
M1_3_31 : MX2XL port map( A => ML_int_3_31_port, B => ML_int_3_23_port, S0
=> SH(3), Y => ML_int_4_31_port);
M1_0_30 : MX2XL port map( A => A(30), B => A(29), S0 => SH(0), Y =>
ML_int_1_30_port);
M1_1_30 : MX2XL port map( A => ML_int_1_30_port, B => ML_int_1_28_port, S0
=> SH(1), Y => ML_int_2_30_port);
M1_2_30 : MX2XL port map( A => ML_int_2_30_port, B => ML_int_2_26_port, S0
=> SH(2), Y => ML_int_3_30_port);
M1_3_30 : MX2XL port map( A => ML_int_3_30_port, B => ML_int_3_22_port, S0
=> SH(3), Y => ML_int_4_30_port);
M1_1_29 : MX2XL port map( A => ML_int_1_29_port, B => ML_int_1_27_port, S0
=> SH(1), Y => ML_int_2_29_port);
M1_2_29 : MX2XL port map( A => ML_int_2_29_port, B => ML_int_2_25_port, S0
=> SH(2), Y => ML_int_3_29_port);
M1_3_29 : MX2XL port map( A => ML_int_3_29_port, B => ML_int_3_21_port, S0
=> SH(3), Y => ML_int_4_29_port);
M1_1_28 : MX2XL port map( A => ML_int_1_28_port, B => ML_int_1_26_port, S0
=> SH(1), Y => ML_int_2_28_port);
M1_2_28 : MX2XL port map( A => ML_int_2_28_port, B => ML_int_2_24_port, S0
=> SH(2), Y => ML_int_3_28_port);
M1_3_28 : MX2XL port map( A => ML_int_3_28_port, B => ML_int_3_20_port, S0
=> SH(3), Y => ML_int_4_28_port);
M1_2_27 : MX2XL port map( A => ML_int_2_27_port, B => ML_int_2_23_port, S0
=> SH(2), Y => ML_int_3_27_port);
M1_3_27 : MX2XL port map( A => ML_int_3_27_port, B => ML_int_3_19_port, S0
=> SH(3), Y => ML_int_4_27_port);
M1_2_26 : MX2XL port map( A => ML_int_2_26_port, B => ML_int_2_22_port, S0
=> SH(2), Y => ML_int_3_26_port);
M1_3_26 : MX2XL port map( A => ML_int_3_26_port, B => ML_int_3_18_port, S0
=> SH(3), Y => ML_int_4_26_port);
M1_2_25 : MX2XL port map( A => ML_int_2_25_port, B => ML_int_2_21_port, S0
=> SH(2), Y => ML_int_3_25_port);
M1_3_25 : MX2XL port map( A => ML_int_3_25_port, B => ML_int_3_17_port, S0
=> SH(3), Y => ML_int_4_25_port);
M1_2_24 : MX2XL port map( A => ML_int_2_24_port, B => ML_int_2_20_port, S0
=> SH(2), Y => ML_int_3_24_port);
M1_3_24 : MX2XL port map( A => ML_int_3_24_port, B => ML_int_3_16_port, S0
=> SH(3), Y => ML_int_4_24_port);
M1_3_23 : MX2XL port map( A => ML_int_3_23_port, B => ML_int_3_15_port, S0
=> SH(3), Y => ML_int_4_23_port);
M1_3_22 : MX2XL port map( A => ML_int_3_22_port, B => ML_int_3_14_port, S0
=> SH(3), Y => ML_int_4_22_port);
M1_3_21 : MX2XL port map( A => ML_int_3_21_port, B => ML_int_3_13_port, S0
=> SH(3), Y => ML_int_4_21_port);
M1_3_20 : MX2XL port map( A => ML_int_3_20_port, B => ML_int_3_12_port, S0
=> SH(3), Y => ML_int_4_20_port);
M1_3_19 : MX2XL port map( A => ML_int_3_19_port, B => ML_int_3_11_port, S0
=> SH(3), Y => ML_int_4_19_port);
M1_3_18 : MX2XL port map( A => ML_int_3_18_port, B => ML_int_3_10_port, S0
=> SH(3), Y => ML_int_4_18_port);
M1_3_17 : MX2XL port map( A => ML_int_3_17_port, B => ML_int_3_9_port, S0 =>
SH(3), Y => ML_int_4_17_port);
M1_3_16 : MX2XL port map( A => ML_int_3_16_port, B => ML_int_3_8_port, S0 =>
SH(3), Y => ML_int_4_16_port);
M1_3_15 : MX2XL port map( A => ML_int_3_15_port, B => ML_int_3_7_port, S0 =>
SH(3), Y => ML_int_4_15_port);
M1_3_14 : MX2XL port map( A => ML_int_3_14_port, B => ML_int_3_6_port, S0 =>
SH(3), Y => ML_int_4_14_port);
M1_3_13 : MX2XL port map( A => ML_int_3_13_port, B => ML_int_3_5_port, S0 =>
SH(3), Y => ML_int_4_13_port);
M1_3_12 : MX2XL port map( A => ML_int_3_12_port, B => ML_int_3_4_port, S0 =>
SH(3), Y => ML_int_4_12_port);
M1_3_11 : MX2XL port map( A => ML_int_3_11_port, B => ML_int_3_3_port, S0 =>
SH(3), Y => ML_int_4_11_port);
M1_3_10 : MX2XL port map( A => ML_int_3_10_port, B => ML_int_3_2_port, S0 =>
SH(3), Y => ML_int_4_10_port);
M1_3_9 : MX2XL port map( A => ML_int_3_9_port, B => ML_int_3_1_port, S0 =>
SH(3), Y => ML_int_4_9_port);
M1_3_8 : MX2XL port map( A => ML_int_3_8_port, B => ML_int_3_0_port, S0 =>
SH(3), Y => ML_int_4_8_port);
M1_0_1 : MX2XL port map( A => A(1), B => A(0), S0 => SH(0), Y =>
ML_int_1_1_port);
M1_2_23 : MX2XL port map( A => ML_int_2_23_port, B => ML_int_2_19_port, S0
=> SH(2), Y => ML_int_3_23_port);
M1_2_15 : MX2XL port map( A => ML_int_2_15_port, B => ML_int_2_11_port, S0
=> SH(2), Y => ML_int_3_15_port);
M1_2_22 : MX2XL port map( A => ML_int_2_22_port, B => ML_int_2_18_port, S0
=> SH(2), Y => ML_int_3_22_port);
M1_2_14 : MX2XL port map( A => ML_int_2_14_port, B => ML_int_2_10_port, S0
=> SH(2), Y => ML_int_3_14_port);
M1_2_21 : MX2XL port map( A => ML_int_2_21_port, B => ML_int_2_17_port, S0
=> SH(2), Y => ML_int_3_21_port);
M1_2_13 : MX2XL port map( A => ML_int_2_13_port, B => ML_int_2_9_port, S0 =>
SH(2), Y => ML_int_3_13_port);
M1_2_20 : MX2XL port map( A => ML_int_2_20_port, B => ML_int_2_16_port, S0
=> SH(2), Y => ML_int_3_20_port);
M1_2_12 : MX2XL port map( A => ML_int_2_12_port, B => ML_int_2_8_port, S0 =>
SH(2), Y => ML_int_3_12_port);
M1_2_19 : MX2XL port map( A => ML_int_2_19_port, B => ML_int_2_15_port, S0
=> SH(2), Y => ML_int_3_19_port);
M1_2_11 : MX2XL port map( A => ML_int_2_11_port, B => ML_int_2_7_port, S0 =>
SH(2), Y => ML_int_3_11_port);
M1_2_18 : MX2XL port map( A => ML_int_2_18_port, B => ML_int_2_14_port, S0
=> SH(2), Y => ML_int_3_18_port);
M1_2_10 : MX2XL port map( A => ML_int_2_10_port, B => ML_int_2_6_port, S0 =>
SH(2), Y => ML_int_3_10_port);
M1_2_17 : MX2XL port map( A => ML_int_2_17_port, B => ML_int_2_13_port, S0
=> SH(2), Y => ML_int_3_17_port);
M1_2_9 : MX2XL port map( A => ML_int_2_9_port, B => ML_int_2_5_port, S0 =>
SH(2), Y => ML_int_3_9_port);
M1_2_16 : MX2XL port map( A => ML_int_2_16_port, B => ML_int_2_12_port, S0
=> SH(2), Y => ML_int_3_16_port);
M1_2_8 : MX2XL port map( A => ML_int_2_8_port, B => ML_int_2_4_port, S0 =>
SH(2), Y => ML_int_3_8_port);
M1_2_7 : MX2XL port map( A => ML_int_2_7_port, B => ML_int_2_3_port, S0 =>
SH(2), Y => ML_int_3_7_port);
M1_2_6 : MX2XL port map( A => ML_int_2_6_port, B => ML_int_2_2_port, S0 =>
SH(2), Y => ML_int_3_6_port);
M1_2_5 : MX2XL port map( A => ML_int_2_5_port, B => ML_int_2_1_port, S0 =>
SH(2), Y => ML_int_3_5_port);
M1_2_4 : MX2XL port map( A => ML_int_2_4_port, B => ML_int_2_0_port, S0 =>
SH(2), Y => ML_int_3_4_port);
M1_0_29 : MX2XL port map( A => A(29), B => A(28), S0 => SH(0), Y =>
ML_int_1_29_port);
M1_0_27 : MX2XL port map( A => A(27), B => A(26), S0 => SH(0), Y =>
ML_int_1_27_port);
M1_0_25 : MX2XL port map( A => A(25), B => A(24), S0 => SH(0), Y =>
ML_int_1_25_port);
M1_0_23 : MX2XL port map( A => A(23), B => A(22), S0 => SH(0), Y =>
ML_int_1_23_port);
M1_0_21 : MX2XL port map( A => A(21), B => A(20), S0 => SH(0), Y =>
ML_int_1_21_port);
M1_0_19 : MX2XL port map( A => A(19), B => A(18), S0 => SH(0), Y =>
ML_int_1_19_port);
M1_0_17 : MX2XL port map( A => A(17), B => A(16), S0 => SH(0), Y =>
ML_int_1_17_port);
M1_0_15 : MX2XL port map( A => A(15), B => A(14), S0 => SH(0), Y =>
ML_int_1_15_port);
M1_0_13 : MX2XL port map( A => A(13), B => A(12), S0 => SH(0), Y =>
ML_int_1_13_port);
M1_0_11 : MX2XL port map( A => A(11), B => A(10), S0 => SH(0), Y =>
ML_int_1_11_port);
M1_0_9 : MX2XL port map( A => A(9), B => A(8), S0 => SH(0), Y =>
ML_int_1_9_port);
M1_0_3 : MX2XL port map( A => A(3), B => A(2), S0 => SH(0), Y =>
ML_int_1_3_port);
M1_0_7 : MX2XL port map( A => A(7), B => A(6), S0 => SH(0), Y =>
ML_int_1_7_port);
M1_0_5 : MX2XL port map( A => A(5), B => A(4), S0 => SH(0), Y =>
ML_int_1_5_port);
M1_0_28 : MX2XL port map( A => A(28), B => A(27), S0 => SH(0), Y =>
ML_int_1_28_port);
M1_0_26 : MX2XL port map( A => A(26), B => A(25), S0 => SH(0), Y =>
ML_int_1_26_port);
M1_0_24 : MX2XL port map( A => A(24), B => A(23), S0 => SH(0), Y =>
ML_int_1_24_port);
M1_0_22 : MX2XL port map( A => A(22), B => A(21), S0 => SH(0), Y =>
ML_int_1_22_port);
M1_0_20 : MX2XL port map( A => A(20), B => A(19), S0 => SH(0), Y =>
ML_int_1_20_port);
M1_0_18 : MX2XL port map( A => A(18), B => A(17), S0 => SH(0), Y =>
ML_int_1_18_port);
M1_0_16 : MX2XL port map( A => A(16), B => A(15), S0 => SH(0), Y =>
ML_int_1_16_port);
M1_0_14 : MX2XL port map( A => A(14), B => A(13), S0 => SH(0), Y =>
ML_int_1_14_port);
M1_0_12 : MX2XL port map( A => A(12), B => A(11), S0 => SH(0), Y =>
ML_int_1_12_port);
M1_0_10 : MX2XL port map( A => A(10), B => A(9), S0 => SH(0), Y =>
ML_int_1_10_port);
M1_0_8 : MX2XL port map( A => A(8), B => A(7), S0 => SH(0), Y =>
ML_int_1_8_port);
M1_0_6 : MX2XL port map( A => A(6), B => A(5), S0 => SH(0), Y =>
ML_int_1_6_port);
M1_0_4 : MX2XL port map( A => A(4), B => A(3), S0 => SH(0), Y =>
ML_int_1_4_port);
M1_0_2 : MX2XL port map( A => A(2), B => A(1), S0 => SH(0), Y =>
ML_int_1_2_port);
M1_1_3 : MX2XL port map( A => ML_int_1_3_port, B => ML_int_1_1_port, S0 =>
SH(1), Y => ML_int_2_3_port);
M1_1_2 : MX2XL port map( A => ML_int_1_2_port, B => ML_int_1_0_port, S0 =>
SH(1), Y => ML_int_2_2_port);
M1_1_27 : MX2XL port map( A => ML_int_1_27_port, B => ML_int_1_25_port, S0
=> SH(1), Y => ML_int_2_27_port);
M1_1_23 : MX2XL port map( A => ML_int_1_23_port, B => ML_int_1_21_port, S0
=> SH(1), Y => ML_int_2_23_port);
M1_1_19 : MX2XL port map( A => ML_int_1_19_port, B => ML_int_1_17_port, S0
=> SH(1), Y => ML_int_2_19_port);
M1_1_15 : MX2XL port map( A => ML_int_1_15_port, B => ML_int_1_13_port, S0
=> SH(1), Y => ML_int_2_15_port);
M1_1_11 : MX2XL port map( A => ML_int_1_11_port, B => ML_int_1_9_port, S0 =>
SH(1), Y => ML_int_2_11_port);
M1_1_7 : MX2XL port map( A => ML_int_1_7_port, B => ML_int_1_5_port, S0 =>
SH(1), Y => ML_int_2_7_port);
M1_1_26 : MX2XL port map( A => ML_int_1_26_port, B => ML_int_1_24_port, S0
=> SH(1), Y => ML_int_2_26_port);
M1_1_22 : MX2XL port map( A => ML_int_1_22_port, B => ML_int_1_20_port, S0
=> SH(1), Y => ML_int_2_22_port);
M1_1_18 : MX2XL port map( A => ML_int_1_18_port, B => ML_int_1_16_port, S0
=> SH(1), Y => ML_int_2_18_port);
M1_1_14 : MX2XL port map( A => ML_int_1_14_port, B => ML_int_1_12_port, S0
=> SH(1), Y => ML_int_2_14_port);
M1_1_10 : MX2XL port map( A => ML_int_1_10_port, B => ML_int_1_8_port, S0 =>
SH(1), Y => ML_int_2_10_port);
M1_1_6 : MX2XL port map( A => ML_int_1_6_port, B => ML_int_1_4_port, S0 =>
SH(1), Y => ML_int_2_6_port);
M1_1_25 : MX2XL port map( A => ML_int_1_25_port, B => ML_int_1_23_port, S0
=> SH(1), Y => ML_int_2_25_port);
M1_1_21 : MX2XL port map( A => ML_int_1_21_port, B => ML_int_1_19_port, S0
=> SH(1), Y => ML_int_2_21_port);
M1_1_17 : MX2XL port map( A => ML_int_1_17_port, B => ML_int_1_15_port, S0
=> SH(1), Y => ML_int_2_17_port);
M1_1_13 : MX2XL port map( A => ML_int_1_13_port, B => ML_int_1_11_port, S0
=> SH(1), Y => ML_int_2_13_port);
M1_1_9 : MX2XL port map( A => ML_int_1_9_port, B => ML_int_1_7_port, S0 =>
SH(1), Y => ML_int_2_9_port);
M1_1_5 : MX2XL port map( A => ML_int_1_5_port, B => ML_int_1_3_port, S0 =>
SH(1), Y => ML_int_2_5_port);
M1_1_24 : MX2XL port map( A => ML_int_1_24_port, B => ML_int_1_22_port, S0
=> SH(1), Y => ML_int_2_24_port);
M1_1_20 : MX2XL port map( A => ML_int_1_20_port, B => ML_int_1_18_port, S0
=> SH(1), Y => ML_int_2_20_port);
M1_1_16 : MX2XL port map( A => ML_int_1_16_port, B => ML_int_1_14_port, S0
=> SH(1), Y => ML_int_2_16_port);
M1_1_12 : MX2XL port map( A => ML_int_1_12_port, B => ML_int_1_10_port, S0
=> SH(1), Y => ML_int_2_12_port);
M1_1_8 : MX2XL port map( A => ML_int_1_8_port, B => ML_int_1_6_port, S0 =>
SH(1), Y => ML_int_2_8_port);
M1_1_4 : MX2XL port map( A => ML_int_1_4_port, B => ML_int_1_2_port, S0 =>
SH(1), Y => ML_int_2_4_port);
M1_4_31 : MX2X1 port map( A => ML_int_4_31_port, B => ML_int_4_15_port, S0
=> SH(4), Y => B(31));
M1_4_30 : MX2X1 port map( A => ML_int_4_30_port, B => ML_int_4_14_port, S0
=> SH(4), Y => B(30));
M1_4_29 : MX2X1 port map( A => ML_int_4_29_port, B => ML_int_4_13_port, S0
=> SH(4), Y => B(29));
M1_4_28 : MX2X1 port map( A => ML_int_4_28_port, B => ML_int_4_12_port, S0
=> SH(4), Y => B(28));
M1_4_27 : MX2X1 port map( A => ML_int_4_27_port, B => ML_int_4_11_port, S0
=> SH(4), Y => B(27));
M1_4_26 : MX2X1 port map( A => ML_int_4_26_port, B => ML_int_4_10_port, S0
=> SH(4), Y => B(26));
M1_4_25 : MX2X1 port map( A => ML_int_4_25_port, B => ML_int_4_9_port, S0 =>
SH(4), Y => B(25));
M1_4_24 : MX2X1 port map( A => ML_int_4_24_port, B => ML_int_4_8_port, S0 =>
SH(4), Y => B(24));
M1_4_23 : MX2X1 port map( A => ML_int_4_23_port, B => ML_int_4_7_port, S0 =>
SH(4), Y => B(23));
M1_4_22 : MX2X1 port map( A => ML_int_4_22_port, B => ML_int_4_6_port, S0 =>
SH(4), Y => B(22));
M1_4_21 : MX2X1 port map( A => ML_int_4_21_port, B => ML_int_4_5_port, S0 =>
SH(4), Y => B(21));
M1_4_20 : MX2X1 port map( A => ML_int_4_20_port, B => ML_int_4_4_port, S0 =>
SH(4), Y => B(20));
M1_4_19 : MX2X1 port map( A => ML_int_4_19_port, B => ML_int_4_3_port, S0 =>
SH(4), Y => B(19));
M1_4_18 : MX2X1 port map( A => ML_int_4_18_port, B => ML_int_4_2_port, S0 =>
SH(4), Y => B(18));
M1_4_17 : MX2X1 port map( A => ML_int_4_17_port, B => ML_int_4_1_port, S0 =>
SH(4), Y => B(17));
M1_4_16 : MX2X1 port map( A => ML_int_4_16_port, B => ML_int_4_0_port, S0 =>
SH(4), Y => B(16));
U3 : INVXL port map( A => SH(3), Y => SHMAG_3_port);
U4 : INVXL port map( A => SH(2), Y => SHMAG_2_port);
U5 : INVXL port map( A => SH(1), Y => SHMAG_1_port);
U6 : NOR2BX1 port map( AN => ML_int_4_9_port, B => SH(4), Y => B(9));
U7 : NOR2BX1 port map( AN => ML_int_4_8_port, B => SH(4), Y => B(8));
U8 : NOR2X1 port map( A => SH(4), B => n1, Y => B(7));
U9 : NOR2X1 port map( A => SH(4), B => n2, Y => B(6));
U10 : NOR2X1 port map( A => SH(4), B => n3, Y => B(5));
U11 : NOR2X1 port map( A => SH(4), B => n4, Y => B(4));
U12 : NOR2X1 port map( A => SH(4), B => n5, Y => B(3));
U13 : NOR2X1 port map( A => SH(4), B => n6, Y => B(2));
U14 : NOR2X1 port map( A => SH(4), B => n7, Y => B(1));
U15 : NOR2BX1 port map( AN => ML_int_4_15_port, B => SH(4), Y => B(15));
U16 : NOR2BX1 port map( AN => ML_int_4_14_port, B => SH(4), Y => B(14));
U17 : NOR2BX1 port map( AN => ML_int_4_13_port, B => SH(4), Y => B(13));
U18 : NOR2BX1 port map( AN => ML_int_4_12_port, B => SH(4), Y => B(12));
U19 : NOR2BX1 port map( AN => ML_int_4_11_port, B => SH(4), Y => B(11));
U20 : NOR2BX1 port map( AN => ML_int_4_10_port, B => SH(4), Y => B(10));
U21 : NOR2X1 port map( A => SH(4), B => n8, Y => B(0));
U22 : CLKINVX1 port map( A => n1, Y => ML_int_4_7_port);
U23 : CLKNAND2X2 port map( A => ML_int_3_7_port, B => SHMAG_3_port, Y => n1)
;
U24 : CLKINVX1 port map( A => n2, Y => ML_int_4_6_port);
U25 : CLKNAND2X2 port map( A => ML_int_3_6_port, B => SHMAG_3_port, Y => n2)
;
U26 : CLKINVX1 port map( A => n3, Y => ML_int_4_5_port);
U27 : CLKNAND2X2 port map( A => ML_int_3_5_port, B => SHMAG_3_port, Y => n3)
;
U28 : CLKINVX1 port map( A => n4, Y => ML_int_4_4_port);
U29 : CLKNAND2X2 port map( A => ML_int_3_4_port, B => SHMAG_3_port, Y => n4)
;
U30 : CLKINVX1 port map( A => n5, Y => ML_int_4_3_port);
U31 : CLKNAND2X2 port map( A => ML_int_3_3_port, B => SHMAG_3_port, Y => n5)
;
U32 : CLKINVX1 port map( A => n6, Y => ML_int_4_2_port);
U33 : CLKNAND2X2 port map( A => ML_int_3_2_port, B => SHMAG_3_port, Y => n6)
;
U34 : CLKINVX1 port map( A => n7, Y => ML_int_4_1_port);
U35 : CLKNAND2X2 port map( A => ML_int_3_1_port, B => SHMAG_3_port, Y => n7)
;
U36 : CLKINVX1 port map( A => n8, Y => ML_int_4_0_port);
U37 : CLKNAND2X2 port map( A => ML_int_3_0_port, B => SHMAG_3_port, Y => n8)
;
U38 : AND2X1 port map( A => ML_int_2_3_port, B => SHMAG_2_port, Y =>
ML_int_3_3_port);
U39 : AND2X1 port map( A => ML_int_2_2_port, B => SHMAG_2_port, Y =>
ML_int_3_2_port);
U40 : AND2X1 port map( A => ML_int_2_1_port, B => SHMAG_2_port, Y =>
ML_int_3_1_port);
U41 : AND2X1 port map( A => ML_int_2_0_port, B => SHMAG_2_port, Y =>
ML_int_3_0_port);
U42 : AND2X1 port map( A => ML_int_1_1_port, B => SHMAG_1_port, Y =>
ML_int_2_1_port);
U43 : AND2X1 port map( A => ML_int_1_0_port, B => SHMAG_1_port, Y =>
ML_int_2_0_port);
U44 : AND2X1 port map( A => A(0), B => SHMAG_0_port, Y => ML_int_1_0_port);
U45 : CLKINVX1 port map( A => SH(0), Y => SHMAG_0_port);
end SYN_mx2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_7 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_7;
architecture SYN_rpl of BOOTH_N16_DW01_add_7 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, SUM_3_port, SUM_2_port, carry_31_port,
carry_30_port, carry_29_port, carry_28_port, carry_27_port, carry_26_port
, carry_25_port, carry_24_port, carry_23_port, carry_22_port,
carry_21_port, carry_20_port, carry_19_port, carry_18_port, carry_17_port
, carry_16_port, carry_15_port, carry_14_port, carry_13_port,
carry_12_port, carry_11_port, carry_10_port, carry_9_port, carry_8_port,
carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port :
std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, SUM_3_port, SUM_2_port, A(1), A(0) );
U1_4 : ADDFX1 port map( A => A(4), B => B(4), CI => carry_4_port, CO =>
carry_5_port, S => SUM_4_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_12 : ADDFX1 port map( A => A(12), B => B(12), CI => carry_12_port, CO =>
carry_13_port, S => SUM_12_port);
U1_11 : ADDFX1 port map( A => A(11), B => B(11), CI => carry_11_port, CO =>
carry_12_port, S => SUM_11_port);
U1_10 : ADDFX1 port map( A => A(10), B => B(10), CI => carry_10_port, CO =>
carry_11_port, S => SUM_10_port);
U1_9 : ADDFX1 port map( A => A(9), B => B(9), CI => carry_9_port, CO =>
carry_10_port, S => SUM_9_port);
U1_8 : ADDFX1 port map( A => A(8), B => B(8), CI => carry_8_port, CO =>
carry_9_port, S => SUM_8_port);
U1_7 : ADDFX1 port map( A => A(7), B => B(7), CI => carry_7_port, CO =>
carry_8_port, S => SUM_7_port);
U1_6 : ADDFX1 port map( A => A(6), B => B(6), CI => carry_6_port, CO =>
carry_7_port, S => SUM_6_port);
U1_5 : ADDFX1 port map( A => A(5), B => B(5), CI => carry_5_port, CO =>
carry_6_port, S => SUM_5_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
carry_4_port, S => SUM_3_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1 : AND2X1 port map( A => A(2), B => B(2), Y => carry_3_port);
U2 : XOR2X1 port map( A => B(2), B => A(2), Y => SUM_2_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_6 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_6;
architecture SYN_rpl of BOOTH_N16_DW01_add_6 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
carry_31_port, carry_30_port, carry_29_port, carry_28_port, carry_27_port
, carry_26_port, carry_25_port, carry_24_port, carry_23_port,
carry_22_port, carry_21_port, carry_20_port, carry_19_port, carry_18_port
, carry_17_port, carry_16_port, carry_15_port, carry_14_port,
carry_13_port, carry_12_port, carry_11_port, carry_10_port, carry_9_port,
carry_8_port, carry_7_port, n_1071, n_1072, n_1073, n_1074 : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
A(5), A(4), n_1071, n_1072, n_1073, n_1074 );
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_12 : ADDFX1 port map( A => A(12), B => B(12), CI => carry_12_port, CO =>
carry_13_port, S => SUM_12_port);
U1_11 : ADDFX1 port map( A => A(11), B => B(11), CI => carry_11_port, CO =>
carry_12_port, S => SUM_11_port);
U1_10 : ADDFX1 port map( A => A(10), B => B(10), CI => carry_10_port, CO =>
carry_11_port, S => SUM_10_port);
U1_9 : ADDFX1 port map( A => A(9), B => B(9), CI => carry_9_port, CO =>
carry_10_port, S => SUM_9_port);
U1_8 : ADDFX1 port map( A => A(8), B => B(8), CI => carry_8_port, CO =>
carry_9_port, S => SUM_8_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_7 : ADDFX1 port map( A => A(7), B => B(7), CI => carry_7_port, CO =>
carry_8_port, S => SUM_7_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1 : AND2X1 port map( A => A(6), B => B(6), Y => carry_7_port);
U2 : XOR2X1 port map( A => B(6), B => A(6), Y => SUM_6_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_5 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_5;
architecture SYN_rpl of BOOTH_N16_DW01_add_5 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, carry_31_port, carry_30_port, carry_29_port,
carry_28_port, carry_27_port, carry_26_port, carry_25_port, carry_24_port
, carry_23_port, carry_22_port, carry_21_port, carry_20_port,
carry_19_port, carry_18_port, carry_17_port, carry_16_port, carry_15_port
, carry_14_port, carry_13_port, carry_12_port, carry_11_port, n_1095,
n_1096, n_1097, n_1098, n_1099, n_1100, n_1101, n_1102 : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, A(9), A(8), n_1095, n_1096, n_1097, n_1098,
n_1099, n_1100, n_1101, n_1102 );
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_12 : ADDFX1 port map( A => A(12), B => B(12), CI => carry_12_port, CO =>
carry_13_port, S => SUM_12_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_11 : ADDFX1 port map( A => A(11), B => B(11), CI => carry_11_port, CO =>
carry_12_port, S => SUM_11_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1 : AND2X1 port map( A => A(10), B => B(10), Y => carry_11_port);
U2 : XOR2X1 port map( A => B(10), B => A(10), Y => SUM_10_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_3 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_3;
architecture SYN_rpl of BOOTH_N16_DW01_add_3 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, carry_31_port, carry_30_port, carry_29_port, carry_28_port,
carry_27_port, carry_26_port, carry_25_port, carry_24_port, carry_23_port
, carry_22_port, carry_21_port, carry_20_port, carry_19_port,
carry_18_port, carry_17_port : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, B(15), B(14), B(13), B(12), B(11), B(10), B(9), B(8), B(7),
B(6), B(5), B(4), B(3), B(2), B(1), B(0) );
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1 : AND2X1 port map( A => A(16), B => B(16), Y => carry_17_port);
U2 : XOR2X1 port map( A => B(16), B => A(16), Y => SUM_16_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_2 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_2;
architecture SYN_rpl of BOOTH_N16_DW01_add_2 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, carry_31_port,
carry_30_port, carry_29_port, carry_28_port, carry_27_port, carry_26_port
, carry_25_port, carry_24_port, carry_23_port, carry_22_port,
carry_21_port, carry_20_port, carry_19_port, carry_18_port, carry_17_port
, carry_16_port, carry_15_port, carry_14_port, carry_13_port,
carry_12_port, carry_11_port, carry_10_port, carry_9_port, n_1135, n_1136
, n_1137, n_1138 : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, A(7), A(6), A(5), A(4),
n_1135, n_1136, n_1137, n_1138 );
U1_9 : ADDFX1 port map( A => A(9), B => B(9), CI => carry_9_port, CO =>
carry_10_port, S => SUM_9_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_12 : ADDFX1 port map( A => A(12), B => B(12), CI => carry_12_port, CO =>
carry_13_port, S => SUM_12_port);
U1_11 : ADDFX1 port map( A => A(11), B => B(11), CI => carry_11_port, CO =>
carry_12_port, S => SUM_11_port);
U1_10 : ADDFX1 port map( A => A(10), B => B(10), CI => carry_10_port, CO =>
carry_11_port, S => SUM_10_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1 : AND2X1 port map( A => A(8), B => B(8), Y => carry_9_port);
U2 : XOR2X1 port map( A => B(8), B => A(8), Y => SUM_8_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_1 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_1;
architecture SYN_rpl of BOOTH_N16_DW01_add_1 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
carry_31_port, carry_30_port, carry_29_port, carry_28_port, carry_27_port
, carry_26_port, carry_25_port, carry_24_port, carry_23_port,
carry_22_port, carry_21_port, carry_20_port, carry_19_port, carry_18_port
, carry_17_port, carry_16_port, carry_15_port, carry_14_port,
carry_13_port : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port, B(11),
B(10), B(9), B(8), B(7), B(6), B(5), B(4), B(3), B(2), B(1), B(0) );
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1 : AND2X1 port map( A => A(12), B => B(12), Y => carry_13_port);
U2 : XOR2X1 port map( A => B(12), B => A(12), Y => SUM_12_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16_DW01_add_0 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end BOOTH_N16_DW01_add_0;
architecture SYN_rpl of BOOTH_N16_DW01_add_0 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, carry_31_port, carry_30_port, carry_29_port,
carry_28_port, carry_27_port, carry_26_port, carry_25_port, carry_24_port
, carry_23_port, carry_22_port, carry_21_port, carry_20_port,
carry_19_port, carry_18_port, carry_17_port, carry_16_port, carry_15_port
, carry_14_port, carry_13_port, carry_12_port, carry_11_port,
carry_10_port, carry_9_port, carry_8_port, carry_7_port, carry_6_port,
carry_5_port : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, B(3), B(2), B(1), B(0) );
U1_5 : ADDFX1 port map( A => A(5), B => B(5), CI => carry_5_port, CO =>
carry_6_port, S => SUM_5_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_12 : ADDFX1 port map( A => A(12), B => B(12), CI => carry_12_port, CO =>
carry_13_port, S => SUM_12_port);
U1_11 : ADDFX1 port map( A => A(11), B => B(11), CI => carry_11_port, CO =>
carry_12_port, S => SUM_11_port);
U1_10 : ADDFX1 port map( A => A(10), B => B(10), CI => carry_10_port, CO =>
carry_11_port, S => SUM_10_port);
U1_9 : ADDFX1 port map( A => A(9), B => B(9), CI => carry_9_port, CO =>
carry_10_port, S => SUM_9_port);
U1_8 : ADDFX1 port map( A => A(8), B => B(8), CI => carry_8_port, CO =>
carry_9_port, S => SUM_8_port);
U1_7 : ADDFX1 port map( A => A(7), B => B(7), CI => carry_7_port, CO =>
carry_8_port, S => SUM_7_port);
U1_6 : ADDFX1 port map( A => A(6), B => B(6), CI => carry_6_port, CO =>
carry_7_port, S => SUM_6_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1 : AND2X1 port map( A => A(4), B => B(4), Y => carry_5_port);
U2 : XOR2X1 port map( A => B(4), B => A(4), Y => SUM_4_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity DLX_DW01_add_1 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end DLX_DW01_add_1;
architecture SYN_rpl of DLX_DW01_add_1 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XOR3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component ADDFX1
port( A, B, CI : in std_logic; CO, S : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, SUM_3_port, SUM_2_port, carry_31_port,
carry_30_port, carry_29_port, carry_28_port, carry_27_port, carry_26_port
, carry_25_port, carry_24_port, carry_23_port, carry_22_port,
carry_21_port, carry_20_port, carry_19_port, carry_18_port, carry_17_port
, carry_16_port, carry_15_port, carry_14_port, carry_13_port,
carry_12_port, carry_11_port, carry_10_port, carry_9_port, carry_8_port,
carry_7_port, carry_6_port, carry_5_port, carry_4_port, carry_3_port :
std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, SUM_3_port, SUM_2_port, A(1), A(0) );
U1_30 : ADDFX1 port map( A => A(30), B => B(30), CI => carry_30_port, CO =>
carry_31_port, S => SUM_30_port);
U1_29 : ADDFX1 port map( A => A(29), B => B(29), CI => carry_29_port, CO =>
carry_30_port, S => SUM_29_port);
U1_28 : ADDFX1 port map( A => A(28), B => B(28), CI => carry_28_port, CO =>
carry_29_port, S => SUM_28_port);
U1_27 : ADDFX1 port map( A => A(27), B => B(27), CI => carry_27_port, CO =>
carry_28_port, S => SUM_27_port);
U1_26 : ADDFX1 port map( A => A(26), B => B(26), CI => carry_26_port, CO =>
carry_27_port, S => SUM_26_port);
U1_25 : ADDFX1 port map( A => A(25), B => B(25), CI => carry_25_port, CO =>
carry_26_port, S => SUM_25_port);
U1_24 : ADDFX1 port map( A => A(24), B => B(24), CI => carry_24_port, CO =>
carry_25_port, S => SUM_24_port);
U1_23 : ADDFX1 port map( A => A(23), B => B(23), CI => carry_23_port, CO =>
carry_24_port, S => SUM_23_port);
U1_22 : ADDFX1 port map( A => A(22), B => B(22), CI => carry_22_port, CO =>
carry_23_port, S => SUM_22_port);
U1_21 : ADDFX1 port map( A => A(21), B => B(21), CI => carry_21_port, CO =>
carry_22_port, S => SUM_21_port);
U1_20 : ADDFX1 port map( A => A(20), B => B(20), CI => carry_20_port, CO =>
carry_21_port, S => SUM_20_port);
U1_19 : ADDFX1 port map( A => A(19), B => B(19), CI => carry_19_port, CO =>
carry_20_port, S => SUM_19_port);
U1_18 : ADDFX1 port map( A => A(18), B => B(18), CI => carry_18_port, CO =>
carry_19_port, S => SUM_18_port);
U1_17 : ADDFX1 port map( A => A(17), B => B(17), CI => carry_17_port, CO =>
carry_18_port, S => SUM_17_port);
U1_16 : ADDFX1 port map( A => A(16), B => B(16), CI => carry_16_port, CO =>
carry_17_port, S => SUM_16_port);
U1_15 : ADDFX1 port map( A => A(15), B => B(15), CI => carry_15_port, CO =>
carry_16_port, S => SUM_15_port);
U1_14 : ADDFX1 port map( A => A(14), B => B(14), CI => carry_14_port, CO =>
carry_15_port, S => SUM_14_port);
U1_13 : ADDFX1 port map( A => A(13), B => B(13), CI => carry_13_port, CO =>
carry_14_port, S => SUM_13_port);
U1_12 : ADDFX1 port map( A => A(12), B => B(12), CI => carry_12_port, CO =>
carry_13_port, S => SUM_12_port);
U1_11 : ADDFX1 port map( A => A(11), B => B(11), CI => carry_11_port, CO =>
carry_12_port, S => SUM_11_port);
U1_10 : ADDFX1 port map( A => A(10), B => B(10), CI => carry_10_port, CO =>
carry_11_port, S => SUM_10_port);
U1_9 : ADDFX1 port map( A => A(9), B => B(9), CI => carry_9_port, CO =>
carry_10_port, S => SUM_9_port);
U1_8 : ADDFX1 port map( A => A(8), B => B(8), CI => carry_8_port, CO =>
carry_9_port, S => SUM_8_port);
U1_7 : ADDFX1 port map( A => A(7), B => B(7), CI => carry_7_port, CO =>
carry_8_port, S => SUM_7_port);
U1_6 : ADDFX1 port map( A => A(6), B => B(6), CI => carry_6_port, CO =>
carry_7_port, S => SUM_6_port);
U1_5 : ADDFX1 port map( A => A(5), B => B(5), CI => carry_5_port, CO =>
carry_6_port, S => SUM_5_port);
U1_4 : ADDFX1 port map( A => A(4), B => B(4), CI => carry_4_port, CO =>
carry_5_port, S => SUM_4_port);
U1_3 : ADDFX1 port map( A => A(3), B => B(3), CI => carry_3_port, CO =>
carry_4_port, S => SUM_3_port);
U1_31 : XOR3XL port map( A => A(31), B => B(31), C => carry_31_port, Y =>
SUM_31_port);
U1 : AND2X1 port map( A => A(2), B => B(2), Y => carry_3_port);
U2 : XOR2X1 port map( A => B(2), B => A(2), Y => SUM_2_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity DLX_DW01_add_0 is
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM :
out std_logic_vector (31 downto 0); CO : out std_logic);
end DLX_DW01_add_0;
architecture SYN_rpl of DLX_DW01_add_0 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
signal SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, SUM_3_port, SUM_2_port, carry_31_port,
carry_30_port, carry_29_port, carry_28_port, carry_27_port, carry_26_port
, carry_25_port, carry_24_port, carry_23_port, carry_22_port,
carry_21_port, carry_20_port, carry_19_port, carry_18_port, carry_17_port
, carry_16_port, carry_15_port, carry_14_port, carry_13_port,
carry_12_port, carry_11_port, carry_10_port, carry_9_port, carry_8_port,
carry_7_port, carry_6_port, carry_5_port, carry_4_port : std_logic;
begin
SUM <= ( SUM_31_port, SUM_30_port, SUM_29_port, SUM_28_port, SUM_27_port,
SUM_26_port, SUM_25_port, SUM_24_port, SUM_23_port, SUM_22_port,
SUM_21_port, SUM_20_port, SUM_19_port, SUM_18_port, SUM_17_port,
SUM_16_port, SUM_15_port, SUM_14_port, SUM_13_port, SUM_12_port,
SUM_11_port, SUM_10_port, SUM_9_port, SUM_8_port, SUM_7_port, SUM_6_port,
SUM_5_port, SUM_4_port, SUM_3_port, SUM_2_port, A(1), A(0) );
U1 : XOR2X1 port map( A => A(31), B => carry_31_port, Y => SUM_31_port);
U2 : AND2X1 port map( A => carry_30_port, B => A(30), Y => carry_31_port);
U3 : XOR2X1 port map( A => A(30), B => carry_30_port, Y => SUM_30_port);
U4 : AND2X1 port map( A => carry_29_port, B => A(29), Y => carry_30_port);
U5 : XOR2X1 port map( A => A(29), B => carry_29_port, Y => SUM_29_port);
U6 : AND2X1 port map( A => carry_28_port, B => A(28), Y => carry_29_port);
U7 : XOR2X1 port map( A => A(28), B => carry_28_port, Y => SUM_28_port);
U8 : AND2X1 port map( A => carry_27_port, B => A(27), Y => carry_28_port);
U9 : XOR2X1 port map( A => A(27), B => carry_27_port, Y => SUM_27_port);
U10 : AND2X1 port map( A => carry_26_port, B => A(26), Y => carry_27_port);
U11 : XOR2X1 port map( A => A(26), B => carry_26_port, Y => SUM_26_port);
U12 : AND2X1 port map( A => carry_25_port, B => A(25), Y => carry_26_port);
U13 : XOR2X1 port map( A => A(25), B => carry_25_port, Y => SUM_25_port);
U14 : AND2X1 port map( A => carry_24_port, B => A(24), Y => carry_25_port);
U15 : XOR2X1 port map( A => A(24), B => carry_24_port, Y => SUM_24_port);
U16 : AND2X1 port map( A => carry_23_port, B => A(23), Y => carry_24_port);
U17 : XOR2X1 port map( A => A(23), B => carry_23_port, Y => SUM_23_port);
U18 : AND2X1 port map( A => carry_22_port, B => A(22), Y => carry_23_port);
U19 : XOR2X1 port map( A => A(22), B => carry_22_port, Y => SUM_22_port);
U20 : AND2X1 port map( A => carry_21_port, B => A(21), Y => carry_22_port);
U21 : XOR2X1 port map( A => A(21), B => carry_21_port, Y => SUM_21_port);
U22 : AND2X1 port map( A => carry_20_port, B => A(20), Y => carry_21_port);
U23 : XOR2X1 port map( A => A(20), B => carry_20_port, Y => SUM_20_port);
U24 : AND2X1 port map( A => carry_19_port, B => A(19), Y => carry_20_port);
U25 : XOR2X1 port map( A => A(19), B => carry_19_port, Y => SUM_19_port);
U26 : AND2X1 port map( A => carry_18_port, B => A(18), Y => carry_19_port);
U27 : XOR2X1 port map( A => A(18), B => carry_18_port, Y => SUM_18_port);
U28 : AND2X1 port map( A => carry_17_port, B => A(17), Y => carry_18_port);
U29 : XOR2X1 port map( A => A(17), B => carry_17_port, Y => SUM_17_port);
U30 : AND2X1 port map( A => carry_16_port, B => A(16), Y => carry_17_port);
U31 : XOR2X1 port map( A => A(16), B => carry_16_port, Y => SUM_16_port);
U32 : AND2X1 port map( A => carry_15_port, B => A(15), Y => carry_16_port);
U33 : XOR2X1 port map( A => A(15), B => carry_15_port, Y => SUM_15_port);
U34 : AND2X1 port map( A => carry_14_port, B => A(14), Y => carry_15_port);
U35 : XOR2X1 port map( A => A(14), B => carry_14_port, Y => SUM_14_port);
U36 : AND2X1 port map( A => carry_13_port, B => A(13), Y => carry_14_port);
U37 : XOR2X1 port map( A => A(13), B => carry_13_port, Y => SUM_13_port);
U38 : AND2X1 port map( A => carry_12_port, B => A(12), Y => carry_13_port);
U39 : XOR2X1 port map( A => A(12), B => carry_12_port, Y => SUM_12_port);
U40 : AND2X1 port map( A => carry_11_port, B => A(11), Y => carry_12_port);
U41 : XOR2X1 port map( A => A(11), B => carry_11_port, Y => SUM_11_port);
U42 : AND2X1 port map( A => carry_10_port, B => A(10), Y => carry_11_port);
U43 : XOR2X1 port map( A => A(10), B => carry_10_port, Y => SUM_10_port);
U44 : AND2X1 port map( A => carry_9_port, B => A(9), Y => carry_10_port);
U45 : XOR2X1 port map( A => A(9), B => carry_9_port, Y => SUM_9_port);
U46 : AND2X1 port map( A => carry_8_port, B => A(8), Y => carry_9_port);
U47 : XOR2X1 port map( A => A(8), B => carry_8_port, Y => SUM_8_port);
U48 : AND2X1 port map( A => carry_7_port, B => A(7), Y => carry_8_port);
U49 : XOR2X1 port map( A => A(7), B => carry_7_port, Y => SUM_7_port);
U50 : AND2X1 port map( A => carry_6_port, B => A(6), Y => carry_7_port);
U51 : XOR2X1 port map( A => A(6), B => carry_6_port, Y => SUM_6_port);
U52 : AND2X1 port map( A => carry_5_port, B => A(5), Y => carry_6_port);
U53 : XOR2X1 port map( A => A(5), B => carry_5_port, Y => SUM_5_port);
U54 : AND2X1 port map( A => carry_4_port, B => A(4), Y => carry_5_port);
U55 : XOR2X1 port map( A => A(4), B => carry_4_port, Y => SUM_4_port);
U56 : AND2X1 port map( A => A(2), B => A(3), Y => carry_4_port);
U57 : XOR2X1 port map( A => A(3), B => A(2), Y => SUM_3_port);
U58 : CLKINVX1 port map( A => A(2), Y => SUM_2_port);
end SYN_rpl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_15 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_15;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_15 is
component RCA_GENERIC_N4_15_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93396 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_15_DW01_add_0 port map( A(4) => n2,
A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0) =>
A(0), B(4) => n2, B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), CI => Ci, SUM(4) => Co,
SUM(3) => S(3), SUM(2) => S(2), SUM(1) => S(1),
SUM(0) => S(0), CO => net93396);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_14 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_14;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_14 is
component RCA_GENERIC_N4_14_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93395 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_14_DW01_add_0 port map( A(4) => n2,
A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0) =>
A(0), B(4) => n2, B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), CI => Ci, SUM(4) => Co,
SUM(3) => S(3), SUM(2) => S(2), SUM(1) => S(1),
SUM(0) => S(0), CO => net93395);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_13 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_13;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_13 is
component RCA_GENERIC_N4_13_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93394 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_13_DW01_add_0 port map( A(4) => n2,
A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0) =>
A(0), B(4) => n2, B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), CI => Ci, SUM(4) => Co,
SUM(3) => S(3), SUM(2) => S(2), SUM(1) => S(1),
SUM(0) => S(0), CO => net93394);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_12 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_12;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_12 is
component RCA_GENERIC_N4_12_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93393 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_12_DW01_add_0 port map( A(4) => n2,
A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0) =>
A(0), B(4) => n2, B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), CI => Ci, SUM(4) => Co,
SUM(3) => S(3), SUM(2) => S(2), SUM(1) => S(1),
SUM(0) => S(0), CO => net93393);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_11 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_11;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_11 is
component RCA_GENERIC_N4_11_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93392 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_11_DW01_add_0 port map( A(4) => n2,
A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0) =>
A(0), B(4) => n2, B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), CI => Ci, SUM(4) => Co,
SUM(3) => S(3), SUM(2) => S(2), SUM(1) => S(1),
SUM(0) => S(0), CO => net93392);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_10 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_10;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_10 is
component RCA_GENERIC_N4_10_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93391 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_10_DW01_add_0 port map( A(4) => n2,
A(3) => A(3), A(2) => A(2), A(1) => A(1), A(0) =>
A(0), B(4) => n2, B(3) => B(3), B(2) => B(2), B(1)
=> B(1), B(0) => B(0), CI => Ci, SUM(4) => Co,
SUM(3) => S(3), SUM(2) => S(2), SUM(1) => S(1),
SUM(0) => S(0), CO => net93391);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_9 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_9;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_9 is
component RCA_GENERIC_N4_9_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93390 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_9_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93390);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_8 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_8;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_8 is
component RCA_GENERIC_N4_8_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93389 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_8_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93389);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_7;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_7 is
component RCA_GENERIC_N4_7_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93388 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_7_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93388);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_6;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_6 is
component RCA_GENERIC_N4_6_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93387 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_6_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93387);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_5;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_5 is
component RCA_GENERIC_N4_5_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93386 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_5_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93386);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_4;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_4 is
component RCA_GENERIC_N4_4_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93385 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_4_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93385);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_3;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_3 is
component RCA_GENERIC_N4_3_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93384 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_3_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93384);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_2;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_2 is
component RCA_GENERIC_N4_2_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93383 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_2_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93383);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_1;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_1 is
component RCA_GENERIC_N4_1_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n2, net93382 : std_logic;
begin
n2 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_1_DW01_add_0 port map( A(4) => n2, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n2, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93382);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_7 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_7;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_7 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_13
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_14
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_14 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_13 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_6 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_6;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_6 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_11
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_12
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_12 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_11 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_5 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_5;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_5 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_9
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_10
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_10 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_9 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_4 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_4;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_4 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_8
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_8 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_7 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_3 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_3;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_3 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_6 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_5 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_2 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_2;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_2 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_4 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_3 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_1 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_1;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_1 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_2 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_1 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_14 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_14;
architecture SYN_BEHAVIORAL of register_generic_N32_14 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_13 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_13;
architecture SYN_BEHAVIORAL of register_generic_N32_13 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRX2
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n32);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n31);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n30);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n29);
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n28);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n27);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n26);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n25);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n24);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n19);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n18);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n17);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n11);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n10);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n9);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n8);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n7);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n6);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n5);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n4);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n3);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n2);
Q_reg_15_inst : EDFFTRX2 port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_12 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_12;
architecture SYN_BEHAVIORAL of register_generic_N32_12 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n32);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n31);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n30);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n29);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n28);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n27);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n26);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n25);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n24);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n23);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n22);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n21);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n20);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n19);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n18);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n17);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n16);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n15);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n14);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n13);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n12);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n11);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n10);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n9);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n8);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n7);
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n6);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n5);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n4);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n3);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n2);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_11 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_11;
architecture SYN_BEHAVIORAL of register_generic_N32_11 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_10 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_10;
architecture SYN_BEHAVIORAL of register_generic_N32_10 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n4);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n3);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n2);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_9 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_9;
architecture SYN_BEHAVIORAL of register_generic_N32_9 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n4);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n3);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n2);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_8 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_8;
architecture SYN_BEHAVIORAL of register_generic_N32_8 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_7 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_7;
architecture SYN_BEHAVIORAL of register_generic_N32_7 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n32);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n31);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n30);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n29);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n28);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n27);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n26);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n25);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n24);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n23);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n22);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n21);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n20);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n19);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n18);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n17);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n16);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n15);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n14);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n13);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n12);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n11);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n10);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n9);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n8);
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n7);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n6);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n5);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n4);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n3);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n2);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_6 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_6;
architecture SYN_BEHAVIORAL of register_generic_N32_6 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_5 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_5;
architecture SYN_BEHAVIORAL of register_generic_N32_5 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_4 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_4;
architecture SYN_BEHAVIORAL of register_generic_N32_4 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n32);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n31);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n30);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n29);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n28);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n27);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n26);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n25);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n24);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n23);
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n22);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n21);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n20);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n19);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n18);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n17);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n16);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n15);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n14);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n13);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_3 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_3;
architecture SYN_BEHAVIORAL of register_generic_N32_3 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n16);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n15);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n14);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n13);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n12);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n11);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n10);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n9);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n8);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n7);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n6);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n5);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n4);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n3);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n2);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_2 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_2;
architecture SYN_BEHAVIORAL of register_generic_N32_2 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n31);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n30);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n29);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n28);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n27);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n26);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n25);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n24);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n23);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n22);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n21);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n20);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n19);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n18);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n17);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n16);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n15);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n14);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n13);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n12);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n11);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n10);
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n9);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n8);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n7);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n6);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n5);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n4);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n3);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n2);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_1 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_1;
architecture SYN_BEHAVIORAL of register_generic_N32_1 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n34 : std_logic;
begin
Q_reg_15_inst : EDFFTRXL port map( RN => n34, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n32);
Q_reg_14_inst : EDFFTRXL port map( RN => n34, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n31);
Q_reg_13_inst : EDFFTRXL port map( RN => n34, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n30);
Q_reg_12_inst : EDFFTRXL port map( RN => n34, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n29);
Q_reg_11_inst : EDFFTRXL port map( RN => n34, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n28);
Q_reg_7_inst : EDFFTRXL port map( RN => n34, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n27);
Q_reg_9_inst : EDFFTRXL port map( RN => n34, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n26);
Q_reg_6_inst : EDFFTRXL port map( RN => n34, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n25);
Q_reg_10_inst : EDFFTRXL port map( RN => n34, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n24);
Q_reg_8_inst : EDFFTRXL port map( RN => n34, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n23);
Q_reg_3_inst : EDFFTRXL port map( RN => n34, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n22);
Q_reg_4_inst : EDFFTRXL port map( RN => n34, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n21);
Q_reg_20_inst : EDFFTRXL port map( RN => n34, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n20);
Q_reg_19_inst : EDFFTRXL port map( RN => n34, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n19);
Q_reg_18_inst : EDFFTRXL port map( RN => n34, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n18);
Q_reg_17_inst : EDFFTRXL port map( RN => n34, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n17);
Q_reg_16_inst : EDFFTRXL port map( RN => n34, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n16);
Q_reg_5_inst : EDFFTRXL port map( RN => n34, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n15);
Q_reg_0_inst : EDFFTRXL port map( RN => n34, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n14);
Q_reg_26_inst : EDFFTRXL port map( RN => n34, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n13);
Q_reg_2_inst : EDFFTRXL port map( RN => n34, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n12);
Q_reg_1_inst : EDFFTRXL port map( RN => n34, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n11);
Q_reg_31_inst : EDFFTRXL port map( RN => n34, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n10);
Q_reg_29_inst : EDFFTRXL port map( RN => n34, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n9);
Q_reg_27_inst : EDFFTRXL port map( RN => n34, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n8);
Q_reg_30_inst : EDFFTRXL port map( RN => n34, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n7);
Q_reg_28_inst : EDFFTRXL port map( RN => n34, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n6);
Q_reg_25_inst : EDFFTRXL port map( RN => n34, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n5);
Q_reg_24_inst : EDFFTRXL port map( RN => n34, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n4);
Q_reg_23_inst : EDFFTRXL port map( RN => n34, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n3);
Q_reg_22_inst : EDFFTRXL port map( RN => n34, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n2);
Q_reg_21_inst : EDFFTRXL port map( RN => n34, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n34);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity RCA_GENERIC_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end RCA_GENERIC_N4_0;
architecture SYN_BEHAVIORAL of RCA_GENERIC_N4_0 is
component RCA_GENERIC_N4_0_DW01_add_0
port( A, B : in std_logic_vector (4 downto 0); CI : in std_logic; SUM :
out std_logic_vector (4 downto 0); CO : out std_logic);
end component;
signal n1, net93381 : std_logic;
begin
n1 <= '0';
add_1_root_add_20_2 : RCA_GENERIC_N4_0_DW01_add_0 port map( A(4) => n1, A(3)
=> A(3), A(2) => A(2), A(1) => A(1), A(0) => A(0),
B(4) => n1, B(3) => B(3), B(2) => B(2), B(1) => B(1)
, B(0) => B(0), CI => Ci, SUM(4) => Co, SUM(3) =>
S(3), SUM(2) => S(2), SUM(1) => S(1), SUM(0) => S(0)
, CO => net93381);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_BLOCK_N4_0 is
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out
std_logic_vector (3 downto 0); Co : out std_logic);
end CARRY_SELECT_BLOCK_N4_0;
architecture SYN_STRUCTURAL of CARRY_SELECT_BLOCK_N4_0 is
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component RCA_GENERIC_N4_15
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component RCA_GENERIC_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, S0_3_port, S0_2_port, S0_1_port,
S0_0_port, C0, S1_3_port, S1_2_port, S1_1_port, S1_0_port, C1 : std_logic
;
begin
X_Logic1_port <= '1';
X_Logic0_port <= '0';
RCA0 : RCA_GENERIC_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic0_port, S(3) =>
S0_3_port, S(2) => S0_2_port, S(1) => S0_1_port,
S(0) => S0_0_port, Co => C0);
RCA1 : RCA_GENERIC_N4_15 port map( A(3) => A(3), A(2) => A(2), A(1) => A(1),
A(0) => A(0), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), Ci => X_Logic1_port, S(3) =>
S1_3_port, S(2) => S1_2_port, S(1) => S1_1_port,
S(0) => S1_0_port, Co => C1);
U3 : MX2X1 port map( A => S0_3_port, B => S1_3_port, S0 => Ci, Y => S(3));
U4 : MX2X1 port map( A => S0_2_port, B => S1_2_port, S0 => Ci, Y => S(2));
U5 : MX2X1 port map( A => S0_1_port, B => S1_1_port, S0 => Ci, Y => S(1));
U6 : MX2X1 port map( A => S0_0_port, B => S1_0_port, S0 => Ci, Y => S(0));
U7 : MX2X1 port map( A => C0, B => C1, S0 => Ci, Y => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity SHIFTER_GENERIC_N32 is
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT, SHIFT_ROTATE : in std_logic;
OUTPUT : out std_logic_vector (31 downto 0));
end SHIFTER_GENERIC_N32;
architecture SYN_BEHAVIORAL of SHIFTER_GENERIC_N32 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component CLKBUFX4
port( A : in std_logic; Y : out std_logic);
end component;
component SHIFTER_GENERIC_N32_DW_rbsh_0
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31
downto 0));
end component;
component SHIFTER_GENERIC_N32_DW_lbsh_0
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31
downto 0));
end component;
component SHIFTER_GENERIC_N32_DW_sra_0
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31
downto 0));
end component;
component SHIFTER_GENERIC_N32_DW_rash_0
port( A : in std_logic_vector (31 downto 0); DATA_TC : in std_logic; SH
: in std_logic_vector (4 downto 0); SH_TC : in std_logic; B : out
std_logic_vector (31 downto 0));
end component;
component SHIFTER_GENERIC_N32_DW_sla_0
port( A : in std_logic_vector (31 downto 0); SH : in std_logic_vector (4
downto 0); SH_TC : in std_logic; B : out std_logic_vector (31
downto 0));
end component;
component SHIFTER_GENERIC_N32_DW01_ash_0
port( A : in std_logic_vector (31 downto 0); DATA_TC : in std_logic; SH
: in std_logic_vector (4 downto 0); SH_TC : in std_logic; B : out
std_logic_vector (31 downto 0));
end component;
signal N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20,
N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31, N32, N33, N34, N35
, N36, N37, N38, N39, N40, N41, N42, N43, N44, N45, N46, N47, N48, N49,
N50, N51, N52, N53, N54, N55, N56, N57, N58, N59, N60, N61, N62, N63, N64
, N65, N66, N67, N68, N69, N70, N105, N106, N107, N108, N109, N110, N111,
N112, N113, N114, N115, N116, N117, N118, N119, N120, N121, N122, N123,
N124, N125, N126, N127, N128, N129, N130, N131, N132, N133, N134, N135,
N136, N137, N138, N139, N140, N141, N142, N143, N144, N145, N146, N147,
N148, N149, N150, N151, N152, N153, N154, N155, N156, N157, N158, N159,
N160, N161, N162, N163, N164, N165, N166, N167, N168, N202, N203, N204,
N205, N206, N207, N208, N209, N210, N211, N212, N213, N214, N215, N216,
N217, N218, N219, N220, N221, N222, N223, N224, N225, N226, N227, N228,
N229, N230, N231, N232, N233, N234, N235, N236, N237, N238, N239, N240,
N241, N242, N243, N244, N245, N246, N247, N248, N249, N250, N251, N252,
N253, N254, N255, N256, N257, N258, N259, N260, N261, N262, N263, N264,
N265, n14_port, n15_port, n16_port, n17_port, n18_port, n19_port, n1, n2,
n3, n4, n5, n6, n7_port, n8_port, n9_port, n10_port, n11_port, n12_port,
n13_port, n20_port, n21_port, n22_port, n23_port, n24_port, n25_port,
n26_port, n27_port, n28_port, n29_port, n30_port, n31_port, n32_port,
n33_port, n34_port, n35_port, n36_port, n37_port, n38_port, n39_port,
n40_port, n41_port, n42_port, n43_port, n44_port, n45_port, n46_port,
n47_port, n48_port, n49_port, n50_port, n51_port, n52_port, n53_port,
n54_port, n55_port, n56_port, n57_port, n58_port, n59_port, n60_port,
n61_port, n62_port, n63_port, n64_port, n65_port, n66_port, n67_port,
n68_port, n69_port, n70_port, n71, n72, n73, n74, n75, n76, n77, n78, n79
: std_logic;
begin
n14_port <= '0';
n15_port <= '0';
n16_port <= '0';
n17_port <= '0';
n18_port <= '0';
n19_port <= '0';
C88 : SHIFTER_GENERIC_N32_DW01_ash_0 port map( A(31) => A(31), A(30) =>
A(30), A(29) => A(29), A(28) => A(28), A(27) =>
A(27), A(26) => A(26), A(25) => A(25), A(24) =>
A(24), A(23) => A(23), A(22) => A(22), A(21) =>
A(21), A(20) => A(20), A(19) => A(19), A(18) =>
A(18), A(17) => A(17), A(16) => A(16), A(15) =>
A(15), A(14) => A(14), A(13) => A(13), A(12) =>
A(12), A(11) => A(11), A(10) => A(10), A(9) => A(9),
A(8) => A(8), A(7) => A(7), A(6) => A(6), A(5) =>
A(5), A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1)
=> A(1), A(0) => A(0), DATA_TC => n14_port, SH(4) =>
n1, SH(3) => B(3), SH(2) => B(2), SH(1) => B(1),
SH(0) => B(0), SH_TC => n14_port, B(31) => N265,
B(30) => N264, B(29) => N263, B(28) => N262, B(27)
=> N261, B(26) => N260, B(25) => N259, B(24) => N258
, B(23) => N257, B(22) => N256, B(21) => N255, B(20)
=> N254, B(19) => N253, B(18) => N252, B(17) => N251
, B(16) => N250, B(15) => N249, B(14) => N248, B(13)
=> N247, B(12) => N246, B(11) => N245, B(10) => N244
, B(9) => N243, B(8) => N242, B(7) => N241, B(6) =>
N240, B(5) => N239, B(4) => N238, B(3) => N237, B(2)
=> N236, B(1) => N235, B(0) => N234);
C86 : SHIFTER_GENERIC_N32_DW_sla_0 port map( A(31) => A(31), A(30) => A(30),
A(29) => A(29), A(28) => A(28), A(27) => A(27),
A(26) => A(26), A(25) => A(25), A(24) => A(24),
A(23) => A(23), A(22) => A(22), A(21) => A(21),
A(20) => A(20), A(19) => A(19), A(18) => A(18),
A(17) => A(17), A(16) => A(16), A(15) => A(15),
A(14) => A(14), A(13) => A(13), A(12) => A(12),
A(11) => A(11), A(10) => A(10), A(9) => A(9), A(8)
=> A(8), A(7) => A(7), A(6) => A(6), A(5) => A(5),
A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), SH(4) => n1, SH(3) => B(3),
SH(2) => B(2), SH(1) => B(1), SH(0) => B(0), SH_TC
=> n15_port, B(31) => N233, B(30) => N232, B(29) =>
N231, B(28) => N230, B(27) => N229, B(26) => N228,
B(25) => N227, B(24) => N226, B(23) => N225, B(22)
=> N224, B(21) => N223, B(20) => N222, B(19) => N221
, B(18) => N220, B(17) => N219, B(16) => N218, B(15)
=> N217, B(14) => N216, B(13) => N215, B(12) => N214
, B(11) => N213, B(10) => N212, B(9) => N211, B(8)
=> N210, B(7) => N209, B(6) => N208, B(5) => N207,
B(4) => N206, B(3) => N205, B(2) => N204, B(1) =>
N203, B(0) => N202);
C50 : SHIFTER_GENERIC_N32_DW_rash_0 port map( A(31) => A(31), A(30) => A(30)
, A(29) => A(29), A(28) => A(28), A(27) => A(27),
A(26) => A(26), A(25) => A(25), A(24) => A(24),
A(23) => A(23), A(22) => A(22), A(21) => A(21),
A(20) => A(20), A(19) => A(19), A(18) => A(18),
A(17) => A(17), A(16) => A(16), A(15) => A(15),
A(14) => A(14), A(13) => A(13), A(12) => A(12),
A(11) => A(11), A(10) => A(10), A(9) => A(9), A(8)
=> A(8), A(7) => A(7), A(6) => A(6), A(5) => A(5),
A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), DATA_TC => n16_port, SH(4) => n1
, SH(3) => B(3), SH(2) => B(2), SH(1) => B(1), SH(0)
=> B(0), SH_TC => n16_port, B(31) => N168, B(30) =>
N167, B(29) => N166, B(28) => N165, B(27) => N164,
B(26) => N163, B(25) => N162, B(24) => N161, B(23)
=> N160, B(22) => N159, B(21) => N158, B(20) => N157
, B(19) => N156, B(18) => N155, B(17) => N154, B(16)
=> N153, B(15) => N152, B(14) => N151, B(13) => N150
, B(12) => N149, B(11) => N148, B(10) => N147, B(9)
=> N146, B(8) => N145, B(7) => N144, B(6) => N143,
B(5) => N142, B(4) => N141, B(3) => N140, B(2) =>
N139, B(1) => N138, B(0) => N137);
C48 : SHIFTER_GENERIC_N32_DW_sra_0 port map( A(31) => A(31), A(30) => A(30),
A(29) => A(29), A(28) => A(28), A(27) => A(27),
A(26) => A(26), A(25) => A(25), A(24) => A(24),
A(23) => A(23), A(22) => A(22), A(21) => A(21),
A(20) => A(20), A(19) => A(19), A(18) => A(18),
A(17) => A(17), A(16) => A(16), A(15) => A(15),
A(14) => A(14), A(13) => A(13), A(12) => A(12),
A(11) => A(11), A(10) => A(10), A(9) => A(9), A(8)
=> A(8), A(7) => A(7), A(6) => A(6), A(5) => A(5),
A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), SH(4) => n1, SH(3) => B(3),
SH(2) => B(2), SH(1) => B(1), SH(0) => B(0), SH_TC
=> n17_port, B(31) => N136, B(30) => N135, B(29) =>
N134, B(28) => N133, B(27) => N132, B(26) => N131,
B(25) => N130, B(24) => N129, B(23) => N128, B(22)
=> N127, B(21) => N126, B(20) => N125, B(19) => N124
, B(18) => N123, B(17) => N122, B(16) => N121, B(15)
=> N120, B(14) => N119, B(13) => N118, B(12) => N117
, B(11) => N116, B(10) => N115, B(9) => N114, B(8)
=> N113, B(7) => N112, B(6) => N111, B(5) => N110,
B(4) => N109, B(3) => N108, B(2) => N107, B(1) =>
N106, B(0) => N105);
C10 : SHIFTER_GENERIC_N32_DW_lbsh_0 port map( A(31) => A(31), A(30) => A(30)
, A(29) => A(29), A(28) => A(28), A(27) => A(27),
A(26) => A(26), A(25) => A(25), A(24) => A(24),
A(23) => A(23), A(22) => A(22), A(21) => A(21),
A(20) => A(20), A(19) => A(19), A(18) => A(18),
A(17) => A(17), A(16) => A(16), A(15) => A(15),
A(14) => A(14), A(13) => A(13), A(12) => A(12),
A(11) => A(11), A(10) => A(10), A(9) => A(9), A(8)
=> A(8), A(7) => A(7), A(6) => A(6), A(5) => A(5),
A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), SH(4) => n1, SH(3) => B(3),
SH(2) => B(2), SH(1) => B(1), SH(0) => B(0), SH_TC
=> n18_port, B(31) => N70, B(30) => N69, B(29) =>
N68, B(28) => N67, B(27) => N66, B(26) => N65, B(25)
=> N64, B(24) => N63, B(23) => N62, B(22) => N61,
B(21) => N60, B(20) => N59, B(19) => N58, B(18) =>
N57, B(17) => N56, B(16) => N55, B(15) => N54, B(14)
=> N53, B(13) => N52, B(12) => N51, B(11) => N50,
B(10) => N49, B(9) => N48, B(8) => N47, B(7) => N46,
B(6) => N45, B(5) => N44, B(4) => N43, B(3) => N42,
B(2) => N41, B(1) => N40, B(0) => N39);
C8 : SHIFTER_GENERIC_N32_DW_rbsh_0 port map( A(31) => A(31), A(30) => A(30),
A(29) => A(29), A(28) => A(28), A(27) => A(27),
A(26) => A(26), A(25) => A(25), A(24) => A(24),
A(23) => A(23), A(22) => A(22), A(21) => A(21),
A(20) => A(20), A(19) => A(19), A(18) => A(18),
A(17) => A(17), A(16) => A(16), A(15) => A(15),
A(14) => A(14), A(13) => A(13), A(12) => A(12),
A(11) => A(11), A(10) => A(10), A(9) => A(9), A(8)
=> A(8), A(7) => A(7), A(6) => A(6), A(5) => A(5),
A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), SH(4) => n1, SH(3) => B(3),
SH(2) => B(2), SH(1) => B(1), SH(0) => B(0), SH_TC
=> n19_port, B(31) => N38, B(30) => N37, B(29) =>
N36, B(28) => N35, B(27) => N34, B(26) => N33, B(25)
=> N32, B(24) => N31, B(23) => N30, B(22) => N29,
B(21) => N28, B(20) => N27, B(19) => N26, B(18) =>
N25, B(17) => N24, B(16) => N23, B(15) => N22, B(14)
=> N21, B(13) => N20, B(12) => N19, B(11) => N18,
B(10) => N17, B(9) => N16, B(8) => N15, B(7) => N14,
B(6) => N13, B(5) => N12, B(4) => N11, B(3) => N10,
B(2) => N9, B(1) => N8, B(0) => N7);
U5 : CLKBUFX4 port map( A => B(4), Y => n1);
U6 : CLKNAND2X2 port map( A => n2, B => n3, Y => OUTPUT(9));
U7 : AOI222XL port map( A0 => N211, A1 => n4, B0 => N146, B1 => n5, C0 =>
N114, C1 => n6, Y => n3);
U8 : AOI222XL port map( A0 => N48, A1 => n7_port, B0 => N16, B1 => n8_port,
C0 => N243, C1 => n9_port, Y => n2);
U9 : CLKNAND2X2 port map( A => n10_port, B => n11_port, Y => OUTPUT(8));
U10 : AOI222XL port map( A0 => N210, A1 => n4, B0 => N145, B1 => n5, C0 =>
N113, C1 => n6, Y => n11_port);
U13 : AOI222XL port map( A0 => N47, A1 => n7_port, B0 => N15, B1 => n8_port,
C0 => N242, C1 => n9_port, Y => n10_port);
U14 : CLKNAND2X2 port map( A => n12_port, B => n13_port, Y => OUTPUT(7));
U15 : AOI222XL port map( A0 => N209, A1 => n4, B0 => N144, B1 => n5, C0 =>
N112, C1 => n6, Y => n13_port);
U16 : AOI222XL port map( A0 => N46, A1 => n7_port, B0 => N14, B1 => n8_port,
C0 => N241, C1 => n9_port, Y => n12_port);
U17 : CLKNAND2X2 port map( A => n20_port, B => n21_port, Y => OUTPUT(6));
U18 : AOI222XL port map( A0 => N208, A1 => n4, B0 => N143, B1 => n5, C0 =>
N111, C1 => n6, Y => n21_port);
U19 : AOI222XL port map( A0 => N45, A1 => n7_port, B0 => N13, B1 => n8_port,
C0 => N240, C1 => n9_port, Y => n20_port);
U20 : CLKNAND2X2 port map( A => n22_port, B => n23_port, Y => OUTPUT(5));
U21 : AOI222XL port map( A0 => N207, A1 => n4, B0 => N142, B1 => n5, C0 =>
N110, C1 => n6, Y => n23_port);
U22 : AOI222XL port map( A0 => N44, A1 => n7_port, B0 => N12, B1 => n8_port,
C0 => N239, C1 => n9_port, Y => n22_port);
U23 : CLKNAND2X2 port map( A => n24_port, B => n25_port, Y => OUTPUT(4));
U24 : AOI222XL port map( A0 => N206, A1 => n4, B0 => N141, B1 => n5, C0 =>
N109, C1 => n6, Y => n25_port);
U25 : AOI222XL port map( A0 => N43, A1 => n7_port, B0 => N11, B1 => n8_port,
C0 => N238, C1 => n9_port, Y => n24_port);
U26 : CLKNAND2X2 port map( A => n26_port, B => n27_port, Y => OUTPUT(3));
U27 : AOI222XL port map( A0 => N205, A1 => n4, B0 => N140, B1 => n5, C0 =>
N108, C1 => n6, Y => n27_port);
U28 : AOI222XL port map( A0 => N42, A1 => n7_port, B0 => N10, B1 => n8_port,
C0 => N237, C1 => n9_port, Y => n26_port);
U29 : CLKNAND2X2 port map( A => n28_port, B => n29_port, Y => OUTPUT(31));
U30 : AOI222XL port map( A0 => N233, A1 => n4, B0 => N168, B1 => n5, C0 =>
N136, C1 => n6, Y => n29_port);
U31 : AOI222XL port map( A0 => N70, A1 => n7_port, B0 => N38, B1 => n8_port,
C0 => N265, C1 => n9_port, Y => n28_port);
U32 : CLKNAND2X2 port map( A => n30_port, B => n31_port, Y => OUTPUT(30));
U33 : AOI222XL port map( A0 => N232, A1 => n4, B0 => N167, B1 => n5, C0 =>
N135, C1 => n6, Y => n31_port);
U34 : AOI222XL port map( A0 => N69, A1 => n7_port, B0 => N37, B1 => n8_port,
C0 => N264, C1 => n9_port, Y => n30_port);
U35 : CLKNAND2X2 port map( A => n32_port, B => n33_port, Y => OUTPUT(2));
U36 : AOI222XL port map( A0 => N204, A1 => n4, B0 => N139, B1 => n5, C0 =>
N107, C1 => n6, Y => n33_port);
U37 : AOI222XL port map( A0 => N41, A1 => n7_port, B0 => N9, B1 => n8_port,
C0 => N236, C1 => n9_port, Y => n32_port);
U38 : CLKNAND2X2 port map( A => n34_port, B => n35_port, Y => OUTPUT(29));
U39 : AOI222XL port map( A0 => N231, A1 => n4, B0 => N166, B1 => n5, C0 =>
N134, C1 => n6, Y => n35_port);
U40 : AOI222XL port map( A0 => N68, A1 => n7_port, B0 => N36, B1 => n8_port,
C0 => N263, C1 => n9_port, Y => n34_port);
U41 : CLKNAND2X2 port map( A => n36_port, B => n37_port, Y => OUTPUT(28));
U42 : AOI222XL port map( A0 => N230, A1 => n4, B0 => N165, B1 => n5, C0 =>
N133, C1 => n6, Y => n37_port);
U43 : AOI222XL port map( A0 => N67, A1 => n7_port, B0 => N35, B1 => n8_port,
C0 => N262, C1 => n9_port, Y => n36_port);
U44 : CLKNAND2X2 port map( A => n38_port, B => n39_port, Y => OUTPUT(27));
U45 : AOI222XL port map( A0 => N229, A1 => n4, B0 => N164, B1 => n5, C0 =>
N132, C1 => n6, Y => n39_port);
U46 : AOI222XL port map( A0 => N66, A1 => n7_port, B0 => N34, B1 => n8_port,
C0 => N261, C1 => n9_port, Y => n38_port);
U47 : CLKNAND2X2 port map( A => n40_port, B => n41_port, Y => OUTPUT(26));
U48 : AOI222XL port map( A0 => N228, A1 => n4, B0 => N163, B1 => n5, C0 =>
N131, C1 => n6, Y => n41_port);
U49 : AOI222XL port map( A0 => N65, A1 => n7_port, B0 => N33, B1 => n8_port,
C0 => N260, C1 => n9_port, Y => n40_port);
U50 : CLKNAND2X2 port map( A => n42_port, B => n43_port, Y => OUTPUT(25));
U51 : AOI222XL port map( A0 => N227, A1 => n4, B0 => N162, B1 => n5, C0 =>
N130, C1 => n6, Y => n43_port);
U52 : AOI222XL port map( A0 => N64, A1 => n7_port, B0 => N32, B1 => n8_port,
C0 => N259, C1 => n9_port, Y => n42_port);
U53 : CLKNAND2X2 port map( A => n44_port, B => n45_port, Y => OUTPUT(24));
U54 : AOI222XL port map( A0 => N226, A1 => n4, B0 => N161, B1 => n5, C0 =>
N129, C1 => n6, Y => n45_port);
U55 : AOI222XL port map( A0 => N63, A1 => n7_port, B0 => N31, B1 => n8_port,
C0 => N258, C1 => n9_port, Y => n44_port);
U56 : CLKNAND2X2 port map( A => n46_port, B => n47_port, Y => OUTPUT(23));
U57 : AOI222XL port map( A0 => N225, A1 => n4, B0 => N160, B1 => n5, C0 =>
N128, C1 => n6, Y => n47_port);
U58 : AOI222XL port map( A0 => N62, A1 => n7_port, B0 => N30, B1 => n8_port,
C0 => N257, C1 => n9_port, Y => n46_port);
U59 : CLKNAND2X2 port map( A => n48_port, B => n49_port, Y => OUTPUT(22));
U60 : AOI222XL port map( A0 => N224, A1 => n4, B0 => N159, B1 => n5, C0 =>
N127, C1 => n6, Y => n49_port);
U61 : AOI222XL port map( A0 => N61, A1 => n7_port, B0 => N29, B1 => n8_port,
C0 => N256, C1 => n9_port, Y => n48_port);
U62 : CLKNAND2X2 port map( A => n50_port, B => n51_port, Y => OUTPUT(21));
U63 : AOI222XL port map( A0 => N223, A1 => n4, B0 => N158, B1 => n5, C0 =>
N126, C1 => n6, Y => n51_port);
U64 : AOI222XL port map( A0 => N60, A1 => n7_port, B0 => N28, B1 => n8_port,
C0 => N255, C1 => n9_port, Y => n50_port);
U65 : CLKNAND2X2 port map( A => n52_port, B => n53_port, Y => OUTPUT(20));
U66 : AOI222XL port map( A0 => N222, A1 => n4, B0 => N157, B1 => n5, C0 =>
N125, C1 => n6, Y => n53_port);
U67 : AOI222XL port map( A0 => N59, A1 => n7_port, B0 => N27, B1 => n8_port,
C0 => N254, C1 => n9_port, Y => n52_port);
U68 : CLKNAND2X2 port map( A => n54_port, B => n55_port, Y => OUTPUT(1));
U69 : AOI222XL port map( A0 => N203, A1 => n4, B0 => N138, B1 => n5, C0 =>
N106, C1 => n6, Y => n55_port);
U70 : AOI222XL port map( A0 => N40, A1 => n7_port, B0 => N8, B1 => n8_port,
C0 => N235, C1 => n9_port, Y => n54_port);
U71 : CLKNAND2X2 port map( A => n56_port, B => n57_port, Y => OUTPUT(19));
U72 : AOI222XL port map( A0 => N221, A1 => n4, B0 => N156, B1 => n5, C0 =>
N124, C1 => n6, Y => n57_port);
U73 : AOI222XL port map( A0 => N58, A1 => n7_port, B0 => N26, B1 => n8_port,
C0 => N253, C1 => n9_port, Y => n56_port);
U74 : CLKNAND2X2 port map( A => n58_port, B => n59_port, Y => OUTPUT(18));
U75 : AOI222XL port map( A0 => N220, A1 => n4, B0 => N155, B1 => n5, C0 =>
N123, C1 => n6, Y => n59_port);
U76 : AOI222XL port map( A0 => N57, A1 => n7_port, B0 => N25, B1 => n8_port,
C0 => N252, C1 => n9_port, Y => n58_port);
U77 : CLKNAND2X2 port map( A => n60_port, B => n61_port, Y => OUTPUT(17));
U78 : AOI222XL port map( A0 => N219, A1 => n4, B0 => N154, B1 => n5, C0 =>
N122, C1 => n6, Y => n61_port);
U79 : AOI222XL port map( A0 => N56, A1 => n7_port, B0 => N24, B1 => n8_port,
C0 => N251, C1 => n9_port, Y => n60_port);
U80 : CLKNAND2X2 port map( A => n62_port, B => n63_port, Y => OUTPUT(16));
U81 : AOI222XL port map( A0 => N218, A1 => n4, B0 => N153, B1 => n5, C0 =>
N121, C1 => n6, Y => n63_port);
U82 : AOI222XL port map( A0 => N55, A1 => n7_port, B0 => N23, B1 => n8_port,
C0 => N250, C1 => n9_port, Y => n62_port);
U83 : CLKNAND2X2 port map( A => n64_port, B => n65_port, Y => OUTPUT(15));
U84 : AOI222XL port map( A0 => N217, A1 => n4, B0 => N152, B1 => n5, C0 =>
N120, C1 => n6, Y => n65_port);
U85 : AOI222XL port map( A0 => N54, A1 => n7_port, B0 => N22, B1 => n8_port,
C0 => N249, C1 => n9_port, Y => n64_port);
U86 : CLKNAND2X2 port map( A => n66_port, B => n67_port, Y => OUTPUT(14));
U87 : AOI222XL port map( A0 => N216, A1 => n4, B0 => N151, B1 => n5, C0 =>
N119, C1 => n6, Y => n67_port);
U88 : AOI222XL port map( A0 => N53, A1 => n7_port, B0 => N21, B1 => n8_port,
C0 => N248, C1 => n9_port, Y => n66_port);
U89 : CLKNAND2X2 port map( A => n68_port, B => n69_port, Y => OUTPUT(13));
U90 : AOI222XL port map( A0 => N215, A1 => n4, B0 => N150, B1 => n5, C0 =>
N118, C1 => n6, Y => n69_port);
U91 : AOI222XL port map( A0 => N52, A1 => n7_port, B0 => N20, B1 => n8_port,
C0 => N247, C1 => n9_port, Y => n68_port);
U92 : CLKNAND2X2 port map( A => n70_port, B => n71, Y => OUTPUT(12));
U93 : AOI222XL port map( A0 => N214, A1 => n4, B0 => N149, B1 => n5, C0 =>
N117, C1 => n6, Y => n71);
U94 : AOI222XL port map( A0 => N51, A1 => n7_port, B0 => N19, B1 => n8_port,
C0 => N246, C1 => n9_port, Y => n70_port);
U95 : CLKNAND2X2 port map( A => n72, B => n73, Y => OUTPUT(11));
U96 : AOI222XL port map( A0 => N213, A1 => n4, B0 => N148, B1 => n5, C0 =>
N116, C1 => n6, Y => n73);
U97 : AOI222XL port map( A0 => N50, A1 => n7_port, B0 => N18, B1 => n8_port,
C0 => N245, C1 => n9_port, Y => n72);
U98 : CLKNAND2X2 port map( A => n74, B => n75, Y => OUTPUT(10));
U99 : AOI222XL port map( A0 => N212, A1 => n4, B0 => N147, B1 => n5, C0 =>
N115, C1 => n6, Y => n75);
U100 : AOI222XL port map( A0 => N49, A1 => n7_port, B0 => N17, B1 => n8_port
, C0 => N244, C1 => n9_port, Y => n74);
U101 : CLKNAND2X2 port map( A => n76, B => n77, Y => OUTPUT(0));
U102 : AOI222XL port map( A0 => N202, A1 => n4, B0 => N137, B1 => n5, C0 =>
N105, C1 => n6, Y => n77);
U103 : AND3X1 port map( A => SHIFT_ROTATE, B => n78, C => n79, Y => n6);
U104 : AND3X1 port map( A => SHIFT_ROTATE, B => LOGIC_ARITH, C => n78, Y =>
n5);
U105 : AND3X1 port map( A => SHIFT_ROTATE, B => n79, C => LEFT_RIGHT, Y =>
n4);
U106 : CLKINVX1 port map( A => LOGIC_ARITH, Y => n79);
U107 : AOI222XL port map( A0 => N39, A1 => n7_port, B0 => N7, B1 => n8_port,
C0 => N234, C1 => n9_port, Y => n76);
U108 : AND3X1 port map( A => SHIFT_ROTATE, B => LOGIC_ARITH, C => LEFT_RIGHT
, Y => n9_port);
U109 : NOR2X1 port map( A => LEFT_RIGHT, B => SHIFT_ROTATE, Y => n8_port);
U110 : NOR2X1 port map( A => n78, B => SHIFT_ROTATE, Y => n7_port);
U111 : CLKINVX1 port map( A => LEFT_RIGHT, Y => n78);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity LOGIC_GENERIC_N32 is
port( A, B : in std_logic_vector (31 downto 0); S : in std_logic_vector (3
downto 0); LOGIC_OUT : out std_logic_vector (31 downto 0));
end LOGIC_GENERIC_N32;
architecture SYN_BEHAVIORAL of LOGIC_GENERIC_N32 is
component MX4XL
port( A, B, C, D, S0, S1 : in std_logic; Y : out std_logic);
end component;
begin
U1 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(9),
S1 => A(9), Y => LOGIC_OUT(9));
U2 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(8),
S1 => A(8), Y => LOGIC_OUT(8));
U3 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(7),
S1 => A(7), Y => LOGIC_OUT(7));
U4 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(6),
S1 => A(6), Y => LOGIC_OUT(6));
U5 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(5),
S1 => A(5), Y => LOGIC_OUT(5));
U6 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(4),
S1 => A(4), Y => LOGIC_OUT(4));
U7 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(3),
S1 => A(3), Y => LOGIC_OUT(3));
U8 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(31)
, S1 => A(31), Y => LOGIC_OUT(31));
U9 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(30)
, S1 => A(30), Y => LOGIC_OUT(30));
U10 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(2)
, S1 => A(2), Y => LOGIC_OUT(2));
U11 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(29), S1 => A(29), Y => LOGIC_OUT(29));
U12 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(28), S1 => A(28), Y => LOGIC_OUT(28));
U13 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(27), S1 => A(27), Y => LOGIC_OUT(27));
U14 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(26), S1 => A(26), Y => LOGIC_OUT(26));
U15 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(25), S1 => A(25), Y => LOGIC_OUT(25));
U16 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(24), S1 => A(24), Y => LOGIC_OUT(24));
U17 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(23), S1 => A(23), Y => LOGIC_OUT(23));
U18 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(22), S1 => A(22), Y => LOGIC_OUT(22));
U19 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(21), S1 => A(21), Y => LOGIC_OUT(21));
U20 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(20), S1 => A(20), Y => LOGIC_OUT(20));
U21 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(1)
, S1 => A(1), Y => LOGIC_OUT(1));
U22 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(19), S1 => A(19), Y => LOGIC_OUT(19));
U23 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(18), S1 => A(18), Y => LOGIC_OUT(18));
U24 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(17), S1 => A(17), Y => LOGIC_OUT(17));
U25 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(16), S1 => A(16), Y => LOGIC_OUT(16));
U26 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(15), S1 => A(15), Y => LOGIC_OUT(15));
U27 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(14), S1 => A(14), Y => LOGIC_OUT(14));
U28 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(13), S1 => A(13), Y => LOGIC_OUT(13));
U29 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(12), S1 => A(12), Y => LOGIC_OUT(12));
U30 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(11), S1 => A(11), Y => LOGIC_OUT(11));
U31 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 =>
B(10), S1 => A(10), Y => LOGIC_OUT(10));
U32 : MX4XL port map( A => S(0), B => S(1), C => S(2), D => S(3), S0 => B(0)
, S1 => A(0), Y => LOGIC_OUT(0));
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity COMPARATOR_GENERIC_N32 is
port( SUB : in std_logic_vector (31 downto 0); CARRY, EQUAL, NOT_EQUAL,
GREATER, GREATER_EQUAL, LOWER, LOWER_EQUAL : in std_logic;
COMPARATOR_OUT : out std_logic_vector (31 downto 0); ZERO : out
std_logic);
end COMPARATOR_GENERIC_N32;
architecture SYN_BEHAVIORAL of COMPARATOR_GENERIC_N32 is
component NOR4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NAND4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component MXI2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component NAND3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
signal X_Logic0_port, COMPARATOR_OUT_0_port, ZERO_port, n1, n2, n3, n4, n5,
n6, n7, n8, n9, n10, n11, n12, n13, n14 : std_logic;
begin
COMPARATOR_OUT <= ( X_Logic0_port, X_Logic0_port, X_Logic0_port,
X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port
, X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port,
X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port
, X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port,
X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port
, X_Logic0_port, X_Logic0_port, X_Logic0_port, X_Logic0_port,
X_Logic0_port, COMPARATOR_OUT_0_port );
ZERO <= ZERO_port;
X_Logic0_port <= '0';
U2 : NAND3XL port map( A => n1, B => n2, C => n3, Y => COMPARATOR_OUT_0_port
);
U3 : MXI2X1 port map( A => NOT_EQUAL, B => EQUAL, S0 => ZERO_port, Y => n3);
U4 : MXI2X1 port map( A => LOWER, B => GREATER_EQUAL, S0 => CARRY, Y => n2);
U5 : MXI2X1 port map( A => LOWER_EQUAL, B => GREATER, S0 => n4, Y => n1);
U6 : NOR2BX1 port map( AN => CARRY, B => ZERO_port, Y => n4);
U7 : NOR2X1 port map( A => n5, B => n6, Y => ZERO_port);
U8 : NAND4X1 port map( A => n7, B => n8, C => n9, D => n10, Y => n6);
U9 : NOR4X1 port map( A => SUB(23), B => SUB(22), C => SUB(21), D => SUB(20)
, Y => n10);
U10 : NOR4X1 port map( A => SUB(1), B => SUB(19), C => SUB(18), D => SUB(17)
, Y => n9);
U11 : NOR4X1 port map( A => SUB(16), B => SUB(15), C => SUB(14), D =>
SUB(13), Y => n8);
U12 : NOR4X1 port map( A => SUB(12), B => SUB(11), C => SUB(10), D => SUB(0)
, Y => n7);
U13 : NAND4X1 port map( A => n11, B => n12, C => n13, D => n14, Y => n5);
U14 : NOR4X1 port map( A => SUB(9), B => SUB(8), C => SUB(7), D => SUB(6), Y
=> n14);
U15 : NOR4X1 port map( A => SUB(5), B => SUB(4), C => SUB(3), D => SUB(31),
Y => n13);
U16 : NOR4X1 port map( A => SUB(30), B => SUB(2), C => SUB(29), D => SUB(28)
, Y => n12);
U17 : NOR4X1 port map( A => SUB(27), B => SUB(26), C => SUB(25), D =>
SUB(24), Y => n11);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity CARRY_SELECT_ADDER is
port( A, B : in std_logic_vector (31 downto 0); S : out std_logic_vector
(31 downto 0); Ci : in std_logic; Co : out std_logic);
end CARRY_SELECT_ADDER;
architecture SYN_STRUCTURAL of CARRY_SELECT_ADDER is
component CARRY_SELECT_BLOCK_N4_1
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_2
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_3
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_4
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_5
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_6
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_7
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
component CARRY_SELECT_BLOCK_N4_0
port( A, B : in std_logic_vector (3 downto 0); Ci : in std_logic; S :
out std_logic_vector (3 downto 0); Co : out std_logic);
end component;
signal CARRY_7_port, CARRY_6_port, CARRY_5_port, CARRY_4_port, CARRY_3_port,
CARRY_2_port, CARRY_1_port : std_logic;
begin
CSB_0 : CARRY_SELECT_BLOCK_N4_0 port map( A(3) => A(3), A(2) => A(2), A(1)
=> A(1), A(0) => A(0), B(3) => B(3), B(2) => B(2),
B(1) => B(1), B(0) => B(0), Ci => Ci, S(3) => S(3),
S(2) => S(2), S(1) => S(1), S(0) => S(0), Co =>
CARRY_1_port);
CSB_1 : CARRY_SELECT_BLOCK_N4_7 port map( A(3) => A(7), A(2) => A(6), A(1)
=> A(5), A(0) => A(4), B(3) => B(7), B(2) => B(6),
B(1) => B(5), B(0) => B(4), Ci => CARRY_1_port, S(3)
=> S(7), S(2) => S(6), S(1) => S(5), S(0) => S(4),
Co => CARRY_2_port);
CSB_2 : CARRY_SELECT_BLOCK_N4_6 port map( A(3) => A(11), A(2) => A(10), A(1)
=> A(9), A(0) => A(8), B(3) => B(11), B(2) => B(10),
B(1) => B(9), B(0) => B(8), Ci => CARRY_2_port, S(3)
=> S(11), S(2) => S(10), S(1) => S(9), S(0) => S(8),
Co => CARRY_3_port);
CSB_3 : CARRY_SELECT_BLOCK_N4_5 port map( A(3) => A(15), A(2) => A(14), A(1)
=> A(13), A(0) => A(12), B(3) => B(15), B(2) =>
B(14), B(1) => B(13), B(0) => B(12), Ci =>
CARRY_3_port, S(3) => S(15), S(2) => S(14), S(1) =>
S(13), S(0) => S(12), Co => CARRY_4_port);
CSB_4 : CARRY_SELECT_BLOCK_N4_4 port map( A(3) => A(19), A(2) => A(18), A(1)
=> A(17), A(0) => A(16), B(3) => B(19), B(2) =>
B(18), B(1) => B(17), B(0) => B(16), Ci =>
CARRY_4_port, S(3) => S(19), S(2) => S(18), S(1) =>
S(17), S(0) => S(16), Co => CARRY_5_port);
CSB_5 : CARRY_SELECT_BLOCK_N4_3 port map( A(3) => A(23), A(2) => A(22), A(1)
=> A(21), A(0) => A(20), B(3) => B(23), B(2) =>
B(22), B(1) => B(21), B(0) => B(20), Ci =>
CARRY_5_port, S(3) => S(23), S(2) => S(22), S(1) =>
S(21), S(0) => S(20), Co => CARRY_6_port);
CSB_6 : CARRY_SELECT_BLOCK_N4_2 port map( A(3) => A(27), A(2) => A(26), A(1)
=> A(25), A(0) => A(24), B(3) => B(27), B(2) =>
B(26), B(1) => B(25), B(0) => B(24), Ci =>
CARRY_6_port, S(3) => S(27), S(2) => S(26), S(1) =>
S(25), S(0) => S(24), Co => CARRY_7_port);
CSB_7 : CARRY_SELECT_BLOCK_N4_1 port map( A(3) => A(31), A(2) => A(30), A(1)
=> A(29), A(0) => A(28), B(3) => B(31), B(2) =>
B(30), B(1) => B(29), B(0) => B(28), Ci =>
CARRY_7_port, S(3) => S(31), S(2) => S(30), S(1) =>
S(29), S(0) => S(28), Co => Co);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity flip_flop is
port( CK, RESET, ENABLE, D : in std_logic; Q : out std_logic);
end flip_flop;
architecture SYN_BEHAVIORAL of flip_flop is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n2, n1 : std_logic;
begin
Q_reg : EDFFTRXL port map( RN => n2, D => D, E => ENABLE, CK => CK, Q => Q,
QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n2);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity zero_N32 is
port( INPUT : in std_logic_vector (31 downto 0); ZERO : out std_logic);
end zero_N32;
architecture SYN_BEHAVIORAL of zero_N32 is
component NOR4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NAND4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10 : std_logic;
begin
U1 : NOR2X1 port map( A => n1, B => n2, Y => ZERO);
U2 : NAND4X1 port map( A => n3, B => n4, C => n5, D => n6, Y => n2);
U3 : NOR4X1 port map( A => INPUT(23), B => INPUT(22), C => INPUT(21), D =>
INPUT(20), Y => n6);
U4 : NOR4X1 port map( A => INPUT(1), B => INPUT(19), C => INPUT(18), D =>
INPUT(17), Y => n5);
U5 : NOR4X1 port map( A => INPUT(16), B => INPUT(15), C => INPUT(14), D =>
INPUT(13), Y => n4);
U6 : NOR4X1 port map( A => INPUT(12), B => INPUT(11), C => INPUT(10), D =>
INPUT(0), Y => n3);
U7 : NAND4X1 port map( A => n7, B => n8, C => n9, D => n10, Y => n1);
U8 : NOR4X1 port map( A => INPUT(9), B => INPUT(8), C => INPUT(7), D =>
INPUT(6), Y => n10);
U9 : NOR4X1 port map( A => INPUT(5), B => INPUT(4), C => INPUT(3), D =>
INPUT(31), Y => n9);
U10 : NOR4X1 port map( A => INPUT(30), B => INPUT(2), C => INPUT(29), D =>
INPUT(28), Y => n8);
U11 : NOR4X1 port map( A => INPUT(27), B => INPUT(26), C => INPUT(25), D =>
INPUT(24), Y => n7);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity WB_SIGN_EXT_8 is
port( INPUT : in std_logic_vector (7 downto 0); OUTPUT : out
std_logic_vector (31 downto 0));
end WB_SIGN_EXT_8;
architecture SYN_BEHAVIORAL of WB_SIGN_EXT_8 is
begin
OUTPUT <= ( INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7),
INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7),
INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7),
INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(7), INPUT(6), INPUT(5),
INPUT(4), INPUT(3), INPUT(2), INPUT(1), INPUT(0) );
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity WB_SIGN_EXT_16 is
port( INPUT : in std_logic_vector (15 downto 0); SIGN_EXT_CONTROL : in
std_logic; OUTPUT : out std_logic_vector (31 downto 0));
end WB_SIGN_EXT_16;
architecture SYN_BEHAVIORAL of WB_SIGN_EXT_16 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
signal OUTPUT_30_port, OUTPUT_29_port, OUTPUT_28_port, OUTPUT_27_port,
OUTPUT_26_port, OUTPUT_25_port, OUTPUT_24_port, OUTPUT_23_port,
OUTPUT_22_port, OUTPUT_21_port, OUTPUT_20_port, OUTPUT_19_port,
OUTPUT_18_port, OUTPUT_17_port, OUTPUT_16_port, OUTPUT_15_port,
OUTPUT_14_port, OUTPUT_13_port, OUTPUT_12_port, OUTPUT_11_port,
OUTPUT_10_port, OUTPUT_9_port, OUTPUT_8_port, OUTPUT_7_port,
OUTPUT_6_port, OUTPUT_5_port, OUTPUT_4_port, OUTPUT_3_port, OUTPUT_2_port
, OUTPUT_1_port, OUTPUT_0_port, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11, n12, n13, n14, n15, n16, n17 : std_logic;
begin
OUTPUT <= ( INPUT(15), OUTPUT_30_port, OUTPUT_29_port, OUTPUT_28_port,
OUTPUT_27_port, OUTPUT_26_port, OUTPUT_25_port, OUTPUT_24_port,
OUTPUT_23_port, OUTPUT_22_port, OUTPUT_21_port, OUTPUT_20_port,
OUTPUT_19_port, OUTPUT_18_port, OUTPUT_17_port, OUTPUT_16_port,
OUTPUT_15_port, OUTPUT_14_port, OUTPUT_13_port, OUTPUT_12_port,
OUTPUT_11_port, OUTPUT_10_port, OUTPUT_9_port, OUTPUT_8_port,
OUTPUT_7_port, OUTPUT_6_port, OUTPUT_5_port, OUTPUT_4_port, OUTPUT_3_port
, OUTPUT_2_port, OUTPUT_1_port, OUTPUT_0_port );
U2 : NOR2X1 port map( A => n1, B => n2, Y => OUTPUT_9_port);
U3 : NOR2X1 port map( A => n2, B => n3, Y => OUTPUT_8_port);
U4 : NOR2X1 port map( A => n2, B => n4, Y => OUTPUT_7_port);
U5 : NOR2X1 port map( A => n2, B => n5, Y => OUTPUT_6_port);
U6 : NOR2X1 port map( A => n2, B => n6, Y => OUTPUT_5_port);
U7 : NOR2X1 port map( A => n2, B => n7, Y => OUTPUT_4_port);
U8 : NOR2X1 port map( A => n2, B => n8, Y => OUTPUT_3_port);
U9 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n9, B0 => n10, Y =>
OUTPUT_30_port);
U10 : NOR2X1 port map( A => n2, B => n11, Y => OUTPUT_2_port);
U11 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n12, B0 => n10, Y =>
OUTPUT_29_port);
U12 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n13, B0 => n10, Y =>
OUTPUT_28_port);
U13 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n14, B0 => n10, Y =>
OUTPUT_27_port);
U14 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n15, B0 => n10, Y =>
OUTPUT_26_port);
U15 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n1, B0 => n10, Y =>
OUTPUT_25_port);
U16 : CLKINVX1 port map( A => INPUT(9), Y => n1);
U17 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n3, B0 => n10, Y =>
OUTPUT_24_port);
U18 : CLKINVX1 port map( A => INPUT(8), Y => n3);
U19 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n4, B0 => n10, Y =>
OUTPUT_23_port);
U20 : CLKINVX1 port map( A => INPUT(7), Y => n4);
U21 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n5, B0 => n10, Y =>
OUTPUT_22_port);
U22 : CLKINVX1 port map( A => INPUT(6), Y => n5);
U23 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n6, B0 => n10, Y =>
OUTPUT_21_port);
U24 : CLKINVX1 port map( A => INPUT(5), Y => n6);
U25 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n7, B0 => n10, Y =>
OUTPUT_20_port);
U26 : CLKINVX1 port map( A => INPUT(4), Y => n7);
U27 : NOR2X1 port map( A => n2, B => n16, Y => OUTPUT_1_port);
U28 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n8, B0 => n10, Y =>
OUTPUT_19_port);
U29 : CLKINVX1 port map( A => INPUT(3), Y => n8);
U30 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n11, B0 => n10, Y =>
OUTPUT_18_port);
U31 : CLKINVX1 port map( A => INPUT(2), Y => n11);
U32 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n16, B0 => n10, Y =>
OUTPUT_17_port);
U33 : CLKINVX1 port map( A => INPUT(1), Y => n16);
U34 : OAI21X1 port map( A0 => SIGN_EXT_CONTROL, A1 => n17, B0 => n10, Y =>
OUTPUT_16_port);
U35 : CLKINVX1 port map( A => n10, Y => OUTPUT_15_port);
U36 : CLKNAND2X2 port map( A => INPUT(15), B => SIGN_EXT_CONTROL, Y => n10);
U37 : NOR2X1 port map( A => n2, B => n9, Y => OUTPUT_14_port);
U38 : CLKINVX1 port map( A => INPUT(14), Y => n9);
U39 : NOR2X1 port map( A => n2, B => n12, Y => OUTPUT_13_port);
U40 : CLKINVX1 port map( A => INPUT(13), Y => n12);
U41 : NOR2X1 port map( A => n2, B => n13, Y => OUTPUT_12_port);
U42 : CLKINVX1 port map( A => INPUT(12), Y => n13);
U43 : NOR2X1 port map( A => n2, B => n14, Y => OUTPUT_11_port);
U44 : CLKINVX1 port map( A => INPUT(11), Y => n14);
U45 : NOR2X1 port map( A => n2, B => n15, Y => OUTPUT_10_port);
U46 : CLKINVX1 port map( A => INPUT(10), Y => n15);
U47 : NOR2X1 port map( A => n2, B => n17, Y => OUTPUT_0_port);
U48 : CLKINVX1 port map( A => INPUT(0), Y => n17);
U49 : CLKINVX1 port map( A => SIGN_EXT_CONTROL, Y => n2);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity ID_IMM16_SIGN_EXT is
port( INPUT : in std_logic_vector (15 downto 0); OUTPUT : out
std_logic_vector (31 downto 0));
end ID_IMM16_SIGN_EXT;
architecture SYN_BEHAVIORAL of ID_IMM16_SIGN_EXT is
signal X_Logic0_port : std_logic;
begin
OUTPUT <= ( INPUT(15), INPUT(15), INPUT(15), INPUT(15), INPUT(15), INPUT(15)
, INPUT(15), INPUT(15), INPUT(15), INPUT(15), INPUT(15), INPUT(15),
INPUT(15), INPUT(15), INPUT(15), INPUT(14), INPUT(13), INPUT(12),
INPUT(11), INPUT(10), INPUT(9), INPUT(8), INPUT(7), INPUT(6), INPUT(5),
INPUT(4), INPUT(3), INPUT(2), INPUT(1), INPUT(0), X_Logic0_port,
X_Logic0_port );
X_Logic0_port <= '0';
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity ID_SIGN_EXT is
port( INPUT : in std_logic_vector (15 downto 0); SIGN_EXT_CONTROL : in
std_logic; OUTPUT : out std_logic_vector (31 downto 0));
end ID_SIGN_EXT;
architecture SYN_BEHAVIORAL of ID_SIGN_EXT is
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
signal OUTPUT_16_port : std_logic;
begin
OUTPUT <= ( OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port,
OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port,
OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port,
OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port, OUTPUT_16_port, INPUT(15)
, INPUT(14), INPUT(13), INPUT(12), INPUT(11), INPUT(10), INPUT(9),
INPUT(8), INPUT(7), INPUT(6), INPUT(5), INPUT(4), INPUT(3), INPUT(2),
INPUT(1), INPUT(0) );
U2 : AND2X1 port map( A => SIGN_EXT_CONTROL, B => INPUT(15), Y =>
OUTPUT_16_port);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity register_generic_N32_0 is
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31 downto
0); Q : out std_logic_vector (31 downto 0));
end register_generic_N32_0;
architecture SYN_BEHAVIORAL of register_generic_N32_0 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component EDFFTRXL
port( RN, D, E, CK : in std_logic; Q, QN : out std_logic);
end component;
signal n33, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15
, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29,
n30, n31, n32 : std_logic;
begin
Q_reg_31_inst : EDFFTRXL port map( RN => n33, D => D(31), E => ENABLE, CK =>
CK, Q => Q(31), QN => n32);
Q_reg_1_inst : EDFFTRXL port map( RN => n33, D => D(1), E => ENABLE, CK =>
CK, Q => Q(1), QN => n31);
Q_reg_0_inst : EDFFTRXL port map( RN => n33, D => D(0), E => ENABLE, CK =>
CK, Q => Q(0), QN => n30);
Q_reg_30_inst : EDFFTRXL port map( RN => n33, D => D(30), E => ENABLE, CK =>
CK, Q => Q(30), QN => n29);
Q_reg_29_inst : EDFFTRXL port map( RN => n33, D => D(29), E => ENABLE, CK =>
CK, Q => Q(29), QN => n28);
Q_reg_28_inst : EDFFTRXL port map( RN => n33, D => D(28), E => ENABLE, CK =>
CK, Q => Q(28), QN => n27);
Q_reg_27_inst : EDFFTRXL port map( RN => n33, D => D(27), E => ENABLE, CK =>
CK, Q => Q(27), QN => n26);
Q_reg_26_inst : EDFFTRXL port map( RN => n33, D => D(26), E => ENABLE, CK =>
CK, Q => Q(26), QN => n25);
Q_reg_25_inst : EDFFTRXL port map( RN => n33, D => D(25), E => ENABLE, CK =>
CK, Q => Q(25), QN => n24);
Q_reg_24_inst : EDFFTRXL port map( RN => n33, D => D(24), E => ENABLE, CK =>
CK, Q => Q(24), QN => n23);
Q_reg_23_inst : EDFFTRXL port map( RN => n33, D => D(23), E => ENABLE, CK =>
CK, Q => Q(23), QN => n22);
Q_reg_22_inst : EDFFTRXL port map( RN => n33, D => D(22), E => ENABLE, CK =>
CK, Q => Q(22), QN => n21);
Q_reg_21_inst : EDFFTRXL port map( RN => n33, D => D(21), E => ENABLE, CK =>
CK, Q => Q(21), QN => n20);
Q_reg_20_inst : EDFFTRXL port map( RN => n33, D => D(20), E => ENABLE, CK =>
CK, Q => Q(20), QN => n19);
Q_reg_19_inst : EDFFTRXL port map( RN => n33, D => D(19), E => ENABLE, CK =>
CK, Q => Q(19), QN => n18);
Q_reg_18_inst : EDFFTRXL port map( RN => n33, D => D(18), E => ENABLE, CK =>
CK, Q => Q(18), QN => n17);
Q_reg_17_inst : EDFFTRXL port map( RN => n33, D => D(17), E => ENABLE, CK =>
CK, Q => Q(17), QN => n16);
Q_reg_16_inst : EDFFTRXL port map( RN => n33, D => D(16), E => ENABLE, CK =>
CK, Q => Q(16), QN => n15);
Q_reg_15_inst : EDFFTRXL port map( RN => n33, D => D(15), E => ENABLE, CK =>
CK, Q => Q(15), QN => n14);
Q_reg_14_inst : EDFFTRXL port map( RN => n33, D => D(14), E => ENABLE, CK =>
CK, Q => Q(14), QN => n13);
Q_reg_13_inst : EDFFTRXL port map( RN => n33, D => D(13), E => ENABLE, CK =>
CK, Q => Q(13), QN => n12);
Q_reg_12_inst : EDFFTRXL port map( RN => n33, D => D(12), E => ENABLE, CK =>
CK, Q => Q(12), QN => n11);
Q_reg_11_inst : EDFFTRXL port map( RN => n33, D => D(11), E => ENABLE, CK =>
CK, Q => Q(11), QN => n10);
Q_reg_10_inst : EDFFTRXL port map( RN => n33, D => D(10), E => ENABLE, CK =>
CK, Q => Q(10), QN => n9);
Q_reg_9_inst : EDFFTRXL port map( RN => n33, D => D(9), E => ENABLE, CK =>
CK, Q => Q(9), QN => n8);
Q_reg_8_inst : EDFFTRXL port map( RN => n33, D => D(8), E => ENABLE, CK =>
CK, Q => Q(8), QN => n7);
Q_reg_7_inst : EDFFTRXL port map( RN => n33, D => D(7), E => ENABLE, CK =>
CK, Q => Q(7), QN => n6);
Q_reg_6_inst : EDFFTRXL port map( RN => n33, D => D(6), E => ENABLE, CK =>
CK, Q => Q(6), QN => n5);
Q_reg_5_inst : EDFFTRXL port map( RN => n33, D => D(5), E => ENABLE, CK =>
CK, Q => Q(5), QN => n4);
Q_reg_4_inst : EDFFTRXL port map( RN => n33, D => D(4), E => ENABLE, CK =>
CK, Q => Q(4), QN => n3);
Q_reg_3_inst : EDFFTRXL port map( RN => n33, D => D(3), E => ENABLE, CK =>
CK, Q => Q(3), QN => n2);
Q_reg_2_inst : EDFFTRXL port map( RN => n33, D => D(2), E => ENABLE, CK =>
CK, Q => Q(2), QN => n1);
U3 : CLKINVX1 port map( A => RESET, Y => n33);
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity BOOTH_N16 is
port( A, B : in std_logic_vector (15 downto 0); P : out std_logic_vector
(31 downto 0));
end BOOTH_N16;
architecture SYN_BEHAVIORAL of BOOTH_N16 is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI222X1
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI221X1
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component AOI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI2BB1X1
port( A0N, A1N, B0 : in std_logic; Y : out std_logic);
end component;
component AO2B2X1
port( B0, B1, A0, A1N : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component XOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2BXL
port( AN, B : in std_logic; Y : out std_logic);
end component;
component OAI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component NAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component BOOTH_N16_DW01_add_7
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component BOOTH_N16_DW01_add_6
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component BOOTH_N16_DW01_add_5
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component BOOTH_N16_DW01_add_3
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component BOOTH_N16_DW01_add_2
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component BOOTH_N16_DW01_add_1
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component BOOTH_N16_DW01_add_0
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
signal decoded_0_31_port, decoded_1_31_port, decoded_1_18_port,
decoded_1_17_port, decoded_1_16_port, decoded_1_15_port,
decoded_1_14_port, decoded_1_13_port, decoded_1_12_port,
decoded_1_11_port, decoded_1_10_port, decoded_1_9_port, decoded_1_8_port,
decoded_1_7_port, decoded_1_6_port, decoded_1_5_port, decoded_1_4_port,
decoded_1_3_port, decoded_1_2_port, decoded_1_1_port, decoded_1_0_port,
decoded_2_31_port, decoded_2_20_port, decoded_2_19_port,
decoded_2_18_port, decoded_2_17_port, decoded_2_16_port,
decoded_2_15_port, decoded_2_14_port, decoded_2_13_port,
decoded_2_12_port, decoded_2_11_port, decoded_2_10_port, decoded_2_9_port
, decoded_2_8_port, decoded_2_7_port, decoded_2_6_port, decoded_2_5_port,
decoded_2_4_port, decoded_2_3_port, decoded_2_2_port, decoded_2_1_port,
decoded_2_0_port, decoded_3_31_port, decoded_3_22_port, decoded_3_21_port
, decoded_3_20_port, decoded_3_19_port, decoded_3_18_port,
decoded_3_17_port, decoded_3_16_port, decoded_3_15_port,
decoded_3_14_port, decoded_3_13_port, decoded_3_12_port,
decoded_3_11_port, decoded_3_10_port, decoded_3_9_port, decoded_3_8_port,
decoded_3_7_port, decoded_3_6_port, decoded_3_5_port, decoded_3_4_port,
decoded_3_3_port, decoded_3_2_port, decoded_3_1_port, decoded_3_0_port,
decoded_4_31_port, decoded_4_24_port, decoded_4_23_port,
decoded_4_22_port, decoded_4_21_port, decoded_4_20_port,
decoded_4_19_port, decoded_4_18_port, decoded_4_17_port,
decoded_4_16_port, decoded_4_15_port, decoded_4_14_port,
decoded_4_13_port, decoded_4_12_port, decoded_4_11_port,
decoded_4_10_port, decoded_4_9_port, decoded_4_8_port, decoded_4_7_port,
decoded_4_6_port, decoded_4_5_port, decoded_4_4_port, decoded_4_3_port,
decoded_4_2_port, decoded_4_1_port, decoded_4_0_port, decoded_5_31_port,
decoded_5_26_port, decoded_5_25_port, decoded_5_24_port,
decoded_5_23_port, decoded_5_22_port, decoded_5_21_port,
decoded_5_20_port, decoded_5_19_port, decoded_5_18_port,
decoded_5_17_port, decoded_5_16_port, decoded_5_15_port,
decoded_5_14_port, decoded_5_13_port, decoded_5_12_port,
decoded_5_11_port, decoded_5_10_port, decoded_5_9_port, decoded_5_8_port,
decoded_5_7_port, decoded_5_6_port, decoded_5_5_port, decoded_5_4_port,
decoded_5_3_port, decoded_5_2_port, decoded_5_1_port, decoded_5_0_port,
decoded_8_31_port, decoded_8_30_port, decoded_8_29_port,
decoded_8_28_port, decoded_8_27_port, decoded_8_26_port,
decoded_8_25_port, decoded_8_24_port, decoded_8_23_port,
decoded_8_22_port, decoded_8_21_port, decoded_8_20_port,
decoded_8_19_port, decoded_8_18_port, decoded_8_17_port,
decoded_8_16_port, decoded_8_15_port, decoded_8_14_port,
decoded_8_13_port, decoded_8_12_port, decoded_8_11_port,
decoded_8_10_port, decoded_8_9_port, decoded_8_8_port, decoded_8_7_port,
decoded_8_6_port, decoded_8_5_port, decoded_8_4_port, decoded_8_3_port,
decoded_8_2_port, decoded_8_1_port, decoded_8_0_port,
partial_products_2_31_port, partial_products_2_30_port,
partial_products_2_29_port, partial_products_2_28_port,
partial_products_2_27_port, partial_products_2_26_port,
partial_products_2_25_port, partial_products_2_24_port,
partial_products_2_23_port, partial_products_2_22_port,
partial_products_2_21_port, partial_products_2_20_port,
partial_products_2_19_port, partial_products_2_18_port,
partial_products_2_17_port, partial_products_2_16_port,
partial_products_2_15_port, partial_products_2_14_port,
partial_products_2_13_port, partial_products_2_12_port,
partial_products_2_11_port, partial_products_2_10_port,
partial_products_2_9_port, partial_products_2_8_port,
partial_products_2_7_port, partial_products_2_6_port,
partial_products_2_5_port, partial_products_2_4_port,
partial_products_2_3_port, partial_products_2_2_port,
partial_products_2_1_port, partial_products_2_0_port,
partial_products_3_31_port, partial_products_3_30_port,
partial_products_3_29_port, partial_products_3_28_port,
partial_products_3_27_port, partial_products_3_26_port,
partial_products_3_25_port, partial_products_3_24_port,
partial_products_3_23_port, partial_products_3_22_port,
partial_products_3_21_port, partial_products_3_20_port,
partial_products_3_19_port, partial_products_3_18_port,
partial_products_3_17_port, partial_products_3_16_port,
partial_products_3_15_port, partial_products_3_14_port,
partial_products_3_13_port, partial_products_3_12_port,
partial_products_3_11_port, partial_products_3_10_port,
partial_products_3_9_port, partial_products_3_8_port,
partial_products_3_7_port, partial_products_3_6_port,
partial_products_3_5_port, partial_products_3_4_port,
partial_products_3_3_port, partial_products_3_2_port,
partial_products_3_1_port, partial_products_3_0_port,
partial_products_4_31_port, partial_products_4_30_port,
partial_products_4_29_port, partial_products_4_28_port,
partial_products_4_27_port, partial_products_4_26_port,
partial_products_4_25_port, partial_products_4_24_port,
partial_products_4_23_port, partial_products_4_22_port,
partial_products_4_21_port, partial_products_4_20_port,
partial_products_4_19_port, partial_products_4_18_port,
partial_products_4_17_port, partial_products_4_16_port,
partial_products_4_15_port, partial_products_4_14_port,
partial_products_4_13_port, partial_products_4_12_port,
partial_products_4_11_port, partial_products_4_10_port,
partial_products_4_9_port, partial_products_4_8_port,
partial_products_4_7_port, partial_products_4_6_port,
partial_products_4_5_port, partial_products_4_4_port,
partial_products_4_3_port, partial_products_4_2_port,
partial_products_4_1_port, partial_products_4_0_port,
partial_products_5_31_port, partial_products_5_30_port,
partial_products_5_29_port, partial_products_5_28_port,
partial_products_5_27_port, partial_products_5_26_port,
partial_products_5_25_port, partial_products_5_24_port,
partial_products_5_23_port, partial_products_5_22_port,
partial_products_5_21_port, partial_products_5_20_port,
partial_products_5_19_port, partial_products_5_18_port,
partial_products_5_17_port, partial_products_5_16_port,
partial_products_5_15_port, partial_products_5_14_port,
partial_products_5_13_port, partial_products_5_12_port,
partial_products_5_11_port, partial_products_5_10_port,
partial_products_5_9_port, partial_products_5_8_port,
partial_products_5_7_port, partial_products_5_6_port,
partial_products_5_5_port, partial_products_5_4_port,
partial_products_5_3_port, partial_products_5_2_port,
partial_products_5_1_port, partial_products_5_0_port,
partial_products_6_31_port, partial_products_6_30_port,
partial_products_6_29_port, partial_products_6_28_port,
partial_products_6_27_port, partial_products_6_26_port,
partial_products_6_25_port, partial_products_6_24_port,
partial_products_6_23_port, partial_products_6_22_port,
partial_products_6_21_port, partial_products_6_20_port,
partial_products_6_19_port, partial_products_6_18_port,
partial_products_6_17_port, partial_products_6_16_port,
partial_products_6_15_port, partial_products_6_14_port,
partial_products_6_13_port, partial_products_6_12_port,
partial_products_6_11_port, partial_products_6_10_port,
partial_products_6_9_port, partial_products_6_8_port,
partial_products_6_7_port, partial_products_6_6_port,
partial_products_6_5_port, partial_products_6_4_port,
partial_products_6_3_port, partial_products_6_2_port,
partial_products_6_1_port, partial_products_6_0_port,
partial_products_7_31_port, partial_products_7_30_port,
partial_products_7_29_port, partial_products_7_28_port,
partial_products_7_27_port, partial_products_7_26_port,
partial_products_7_25_port, partial_products_7_24_port,
partial_products_7_23_port, partial_products_7_22_port,
partial_products_7_21_port, partial_products_7_20_port,
partial_products_7_19_port, partial_products_7_18_port,
partial_products_7_17_port, partial_products_7_16_port,
partial_products_7_15_port, partial_products_7_14_port,
partial_products_7_13_port, partial_products_7_12_port,
partial_products_7_11_port, partial_products_7_10_port,
partial_products_7_9_port, partial_products_7_8_port,
partial_products_7_7_port, partial_products_7_6_port,
partial_products_7_5_port, partial_products_7_4_port,
partial_products_7_3_port, partial_products_7_2_port,
partial_products_7_1_port, partial_products_7_0_port,
partial_products_8_31_port, partial_products_8_30_port,
partial_products_8_29_port, partial_products_8_28_port,
partial_products_8_27_port, partial_products_8_26_port,
partial_products_8_25_port, partial_products_8_24_port,
partial_products_8_23_port, partial_products_8_22_port,
partial_products_8_21_port, partial_products_8_20_port,
partial_products_8_19_port, partial_products_8_18_port,
partial_products_8_17_port, partial_products_8_16_port,
partial_products_8_15_port, partial_products_8_14_port,
partial_products_8_13_port, partial_products_8_12_port,
partial_products_8_11_port, partial_products_8_10_port,
partial_products_8_9_port, partial_products_8_8_port,
partial_products_8_7_port, partial_products_8_6_port,
partial_products_8_5_port, partial_products_8_4_port,
partial_products_8_3_port, partial_products_8_2_port,
partial_products_8_1_port, partial_products_8_0_port, N209, N210, N211,
N212, N213, N214, N215, N216, N217, N218, N219, N220, N221, N222, N223,
N224, N225, net68887, net68888, net68889, net68890, net68892, n7,
net68893, n1, n2, n3, n4, n5, n6, n8, n9, n10, n11, n12, n13, n14, n15,
n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30
, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59
, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88
, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102
, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162,
n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198,
n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209_port,
n210_port, n211_port, n212_port, n213_port, n214_port, n215_port,
n216_port, n217_port, n218_port, n219_port, n220_port, n221_port,
n222_port, n223_port, n224_port, n225_port, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242,
n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254,
n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278,
n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314,
n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
net93358, net93359, net93360, net93361, net93362, net93363, net93364,
net93365, net93366, net93367, net93368, net93369, net93370, net93371,
net93372, net93373, net93374, net93375, net93376, net93377, net93378,
net93379, net93380 : std_logic;
begin
net68887 <= '0';
net68888 <= '0';
net68889 <= '0';
net68890 <= '0';
net68892 <= '0';
n7 <= '0';
net68893 <= '0';
decoded_8_0_port <= '0';
decoded_8_1_port <= '0';
decoded_8_2_port <= '0';
decoded_8_3_port <= '0';
decoded_8_4_port <= '0';
decoded_8_5_port <= '0';
decoded_8_6_port <= '0';
decoded_8_7_port <= '0';
decoded_8_8_port <= '0';
decoded_8_9_port <= '0';
decoded_8_10_port <= '0';
decoded_8_11_port <= '0';
decoded_8_12_port <= '0';
decoded_8_13_port <= '0';
decoded_8_14_port <= '0';
decoded_8_15_port <= '0';
decoded_5_0_port <= '0';
decoded_5_1_port <= '0';
decoded_5_2_port <= '0';
decoded_5_3_port <= '0';
decoded_5_4_port <= '0';
decoded_5_5_port <= '0';
decoded_5_6_port <= '0';
decoded_5_7_port <= '0';
decoded_5_8_port <= '0';
decoded_5_9_port <= '0';
decoded_4_0_port <= '0';
decoded_4_1_port <= '0';
decoded_4_2_port <= '0';
decoded_4_3_port <= '0';
decoded_4_4_port <= '0';
decoded_4_5_port <= '0';
decoded_4_6_port <= '0';
decoded_4_7_port <= '0';
decoded_3_0_port <= '0';
decoded_3_1_port <= '0';
decoded_3_2_port <= '0';
decoded_3_3_port <= '0';
decoded_3_4_port <= '0';
decoded_3_5_port <= '0';
decoded_2_0_port <= '0';
decoded_2_1_port <= '0';
decoded_2_2_port <= '0';
decoded_2_3_port <= '0';
decoded_1_0_port <= '0';
decoded_1_1_port <= '0';
add_0_root_add_53_G7 : BOOTH_N16_DW01_add_0 port map( A(31) =>
partial_products_7_31_port, A(30) =>
partial_products_7_30_port, A(29) =>
partial_products_7_29_port, A(28) =>
partial_products_7_28_port, A(27) =>
partial_products_7_27_port, A(26) =>
partial_products_7_26_port, A(25) =>
partial_products_7_25_port, A(24) =>
partial_products_7_24_port, A(23) =>
partial_products_7_23_port, A(22) =>
partial_products_7_22_port, A(21) =>
partial_products_7_21_port, A(20) =>
partial_products_7_20_port, A(19) =>
partial_products_7_19_port, A(18) =>
partial_products_7_18_port, A(17) =>
partial_products_7_17_port, A(16) =>
partial_products_7_16_port, A(15) =>
partial_products_7_15_port, A(14) =>
partial_products_7_14_port, A(13) =>
partial_products_7_13_port, A(12) =>
partial_products_7_12_port, A(11) =>
partial_products_7_11_port, A(10) =>
partial_products_7_10_port, A(9) =>
partial_products_7_9_port, A(8) =>
partial_products_7_8_port, A(7) =>
partial_products_7_7_port, A(6) =>
partial_products_7_6_port, A(5) =>
partial_products_7_5_port, A(4) =>
partial_products_7_4_port, A(3) =>
partial_products_7_3_port, A(2) =>
partial_products_7_2_port, A(1) =>
partial_products_7_1_port, A(0) =>
partial_products_7_0_port, B(31) =>
partial_products_8_31_port, B(30) =>
partial_products_8_30_port, B(29) =>
partial_products_8_29_port, B(28) =>
partial_products_8_28_port, B(27) =>
partial_products_8_27_port, B(26) =>
partial_products_8_26_port, B(25) =>
partial_products_8_25_port, B(24) =>
partial_products_8_24_port, B(23) =>
partial_products_8_23_port, B(22) =>
partial_products_8_22_port, B(21) =>
partial_products_8_21_port, B(20) =>
partial_products_8_20_port, B(19) =>
partial_products_8_19_port, B(18) =>
partial_products_8_18_port, B(17) =>
partial_products_8_17_port, B(16) =>
partial_products_8_16_port, B(15) =>
partial_products_8_15_port, B(14) =>
partial_products_8_14_port, B(13) =>
partial_products_8_13_port, B(12) =>
partial_products_8_12_port, B(11) =>
partial_products_8_11_port, B(10) =>
partial_products_8_10_port, B(9) =>
partial_products_8_9_port, B(8) =>
partial_products_8_8_port, B(7) =>
partial_products_8_7_port, B(6) =>
partial_products_8_6_port, B(5) =>
partial_products_8_5_port, B(4) =>
partial_products_8_4_port, B(3) =>
partial_products_8_3_port, B(2) =>
partial_products_8_2_port, B(1) =>
partial_products_8_1_port, B(0) =>
partial_products_8_0_port, CI => net68887, SUM(31)
=> P(31), SUM(30) => P(30), SUM(29) => P(29),
SUM(28) => P(28), SUM(27) => P(27), SUM(26) => P(26)
, SUM(25) => P(25), SUM(24) => P(24), SUM(23) =>
P(23), SUM(22) => P(22), SUM(21) => P(21), SUM(20)
=> P(20), SUM(19) => P(19), SUM(18) => P(18),
SUM(17) => P(17), SUM(16) => P(16), SUM(15) => P(15)
, SUM(14) => P(14), SUM(13) => P(13), SUM(12) =>
P(12), SUM(11) => P(11), SUM(10) => P(10), SUM(9) =>
P(9), SUM(8) => P(8), SUM(7) => P(7), SUM(6) => P(6)
, SUM(5) => P(5), SUM(4) => P(4), SUM(3) => P(3),
SUM(2) => P(2), SUM(1) => P(1), SUM(0) => P(0), CO
=> net93380);
add_1_root_add_53_G7 : BOOTH_N16_DW01_add_1 port map( A(31) =>
partial_products_5_31_port, A(30) =>
partial_products_5_30_port, A(29) =>
partial_products_5_29_port, A(28) =>
partial_products_5_28_port, A(27) =>
partial_products_5_27_port, A(26) =>
partial_products_5_26_port, A(25) =>
partial_products_5_25_port, A(24) =>
partial_products_5_24_port, A(23) =>
partial_products_5_23_port, A(22) =>
partial_products_5_22_port, A(21) =>
partial_products_5_21_port, A(20) =>
partial_products_5_20_port, A(19) =>
partial_products_5_19_port, A(18) =>
partial_products_5_18_port, A(17) =>
partial_products_5_17_port, A(16) =>
partial_products_5_16_port, A(15) =>
partial_products_5_15_port, A(14) =>
partial_products_5_14_port, A(13) =>
partial_products_5_13_port, A(12) =>
partial_products_5_12_port, A(11) =>
partial_products_5_11_port, A(10) =>
partial_products_5_10_port, A(9) =>
partial_products_5_9_port, A(8) =>
partial_products_5_8_port, A(7) =>
partial_products_5_7_port, A(6) =>
partial_products_5_6_port, A(5) =>
partial_products_5_5_port, A(4) =>
partial_products_5_4_port, A(3) =>
partial_products_5_3_port, A(2) =>
partial_products_5_2_port, A(1) =>
partial_products_5_1_port, A(0) =>
partial_products_5_0_port, B(31) =>
partial_products_6_31_port, B(30) =>
partial_products_6_30_port, B(29) =>
partial_products_6_29_port, B(28) =>
partial_products_6_28_port, B(27) =>
partial_products_6_27_port, B(26) =>
partial_products_6_26_port, B(25) =>
partial_products_6_25_port, B(24) =>
partial_products_6_24_port, B(23) =>
partial_products_6_23_port, B(22) =>
partial_products_6_22_port, B(21) =>
partial_products_6_21_port, B(20) =>
partial_products_6_20_port, B(19) =>
partial_products_6_19_port, B(18) =>
partial_products_6_18_port, B(17) =>
partial_products_6_17_port, B(16) =>
partial_products_6_16_port, B(15) =>
partial_products_6_15_port, B(14) =>
partial_products_6_14_port, B(13) =>
partial_products_6_13_port, B(12) =>
partial_products_6_12_port, B(11) =>
partial_products_6_11_port, B(10) =>
partial_products_6_10_port, B(9) =>
partial_products_6_9_port, B(8) =>
partial_products_6_8_port, B(7) =>
partial_products_6_7_port, B(6) =>
partial_products_6_6_port, B(5) =>
partial_products_6_5_port, B(4) =>
partial_products_6_4_port, B(3) =>
partial_products_6_3_port, B(2) =>
partial_products_6_2_port, B(1) =>
partial_products_6_1_port, B(0) =>
partial_products_6_0_port, CI => net68888, SUM(31)
=> partial_products_8_31_port, SUM(30) =>
partial_products_8_30_port, SUM(29) =>
partial_products_8_29_port, SUM(28) =>
partial_products_8_28_port, SUM(27) =>
partial_products_8_27_port, SUM(26) =>
partial_products_8_26_port, SUM(25) =>
partial_products_8_25_port, SUM(24) =>
partial_products_8_24_port, SUM(23) =>
partial_products_8_23_port, SUM(22) =>
partial_products_8_22_port, SUM(21) =>
partial_products_8_21_port, SUM(20) =>
partial_products_8_20_port, SUM(19) =>
partial_products_8_19_port, SUM(18) =>
partial_products_8_18_port, SUM(17) =>
partial_products_8_17_port, SUM(16) =>
partial_products_8_16_port, SUM(15) =>
partial_products_8_15_port, SUM(14) =>
partial_products_8_14_port, SUM(13) =>
partial_products_8_13_port, SUM(12) =>
partial_products_8_12_port, SUM(11) =>
partial_products_8_11_port, SUM(10) =>
partial_products_8_10_port, SUM(9) =>
partial_products_8_9_port, SUM(8) =>
partial_products_8_8_port, SUM(7) =>
partial_products_8_7_port, SUM(6) =>
partial_products_8_6_port, SUM(5) =>
partial_products_8_5_port, SUM(4) =>
partial_products_8_4_port, SUM(3) =>
partial_products_8_3_port, SUM(2) =>
partial_products_8_2_port, SUM(1) =>
partial_products_8_1_port, SUM(0) =>
partial_products_8_0_port, CO => net93379);
add_2_root_add_53_G7 : BOOTH_N16_DW01_add_2 port map( A(31) =>
partial_products_3_31_port, A(30) =>
partial_products_3_30_port, A(29) =>
partial_products_3_29_port, A(28) =>
partial_products_3_28_port, A(27) =>
partial_products_3_27_port, A(26) =>
partial_products_3_26_port, A(25) =>
partial_products_3_25_port, A(24) =>
partial_products_3_24_port, A(23) =>
partial_products_3_23_port, A(22) =>
partial_products_3_22_port, A(21) =>
partial_products_3_21_port, A(20) =>
partial_products_3_20_port, A(19) =>
partial_products_3_19_port, A(18) =>
partial_products_3_18_port, A(17) =>
partial_products_3_17_port, A(16) =>
partial_products_3_16_port, A(15) =>
partial_products_3_15_port, A(14) =>
partial_products_3_14_port, A(13) =>
partial_products_3_13_port, A(12) =>
partial_products_3_12_port, A(11) =>
partial_products_3_11_port, A(10) =>
partial_products_3_10_port, A(9) =>
partial_products_3_9_port, A(8) =>
partial_products_3_8_port, A(7) =>
partial_products_3_7_port, A(6) =>
partial_products_3_6_port, A(5) =>
partial_products_3_5_port, A(4) =>
partial_products_3_4_port, A(3) =>
partial_products_3_3_port, A(2) =>
partial_products_3_2_port, A(1) =>
partial_products_3_1_port, A(0) =>
partial_products_3_0_port, B(31) =>
partial_products_4_31_port, B(30) =>
partial_products_4_30_port, B(29) =>
partial_products_4_29_port, B(28) =>
partial_products_4_28_port, B(27) =>
partial_products_4_27_port, B(26) =>
partial_products_4_26_port, B(25) =>
partial_products_4_25_port, B(24) =>
partial_products_4_24_port, B(23) =>
partial_products_4_23_port, B(22) =>
partial_products_4_22_port, B(21) =>
partial_products_4_21_port, B(20) =>
partial_products_4_20_port, B(19) =>
partial_products_4_19_port, B(18) =>
partial_products_4_18_port, B(17) =>
partial_products_4_17_port, B(16) =>
partial_products_4_16_port, B(15) =>
partial_products_4_15_port, B(14) =>
partial_products_4_14_port, B(13) =>
partial_products_4_13_port, B(12) =>
partial_products_4_12_port, B(11) =>
partial_products_4_11_port, B(10) =>
partial_products_4_10_port, B(9) =>
partial_products_4_9_port, B(8) =>
partial_products_4_8_port, B(7) =>
partial_products_4_7_port, B(6) =>
partial_products_4_6_port, B(5) =>
partial_products_4_5_port, B(4) =>
partial_products_4_4_port, B(3) =>
partial_products_4_3_port, B(2) =>
partial_products_4_2_port, B(1) =>
partial_products_4_1_port, B(0) =>
partial_products_4_0_port, CI => net68889, SUM(31)
=> partial_products_7_31_port, SUM(30) =>
partial_products_7_30_port, SUM(29) =>
partial_products_7_29_port, SUM(28) =>
partial_products_7_28_port, SUM(27) =>
partial_products_7_27_port, SUM(26) =>
partial_products_7_26_port, SUM(25) =>
partial_products_7_25_port, SUM(24) =>
partial_products_7_24_port, SUM(23) =>
partial_products_7_23_port, SUM(22) =>
partial_products_7_22_port, SUM(21) =>
partial_products_7_21_port, SUM(20) =>
partial_products_7_20_port, SUM(19) =>
partial_products_7_19_port, SUM(18) =>
partial_products_7_18_port, SUM(17) =>
partial_products_7_17_port, SUM(16) =>
partial_products_7_16_port, SUM(15) =>
partial_products_7_15_port, SUM(14) =>
partial_products_7_14_port, SUM(13) =>
partial_products_7_13_port, SUM(12) =>
partial_products_7_12_port, SUM(11) =>
partial_products_7_11_port, SUM(10) =>
partial_products_7_10_port, SUM(9) =>
partial_products_7_9_port, SUM(8) =>
partial_products_7_8_port, SUM(7) =>
partial_products_7_7_port, SUM(6) =>
partial_products_7_6_port, SUM(5) =>
partial_products_7_5_port, SUM(4) =>
partial_products_7_4_port, SUM(3) => net93374,
SUM(2) => net93375, SUM(1) => net93376, SUM(0) =>
net93377, CO => net93378);
add_3_root_add_53_G7 : BOOTH_N16_DW01_add_3 port map( A(31) =>
decoded_8_31_port, A(30) => decoded_8_30_port, A(29)
=> decoded_8_29_port, A(28) => decoded_8_28_port,
A(27) => decoded_8_27_port, A(26) =>
decoded_8_26_port, A(25) => decoded_8_25_port, A(24)
=> decoded_8_24_port, A(23) => decoded_8_23_port,
A(22) => decoded_8_22_port, A(21) =>
decoded_8_21_port, A(20) => decoded_8_20_port, A(19)
=> decoded_8_19_port, A(18) => decoded_8_18_port,
A(17) => decoded_8_17_port, A(16) =>
decoded_8_16_port, A(15) => decoded_8_15_port, A(14)
=> decoded_8_14_port, A(13) => decoded_8_13_port,
A(12) => decoded_8_12_port, A(11) =>
decoded_8_11_port, A(10) => decoded_8_10_port, A(9)
=> decoded_8_9_port, A(8) => decoded_8_8_port, A(7)
=> decoded_8_7_port, A(6) => decoded_8_6_port, A(5)
=> decoded_8_5_port, A(4) => decoded_8_4_port, A(3)
=> decoded_8_3_port, A(2) => decoded_8_2_port, A(1)
=> decoded_8_1_port, A(0) => decoded_8_0_port, B(31)
=> partial_products_2_31_port, B(30) =>
partial_products_2_30_port, B(29) =>
partial_products_2_29_port, B(28) =>
partial_products_2_28_port, B(27) =>
partial_products_2_27_port, B(26) =>
partial_products_2_26_port, B(25) =>
partial_products_2_25_port, B(24) =>
partial_products_2_24_port, B(23) =>
partial_products_2_23_port, B(22) =>
partial_products_2_22_port, B(21) =>
partial_products_2_21_port, B(20) =>
partial_products_2_20_port, B(19) =>
partial_products_2_19_port, B(18) =>
partial_products_2_18_port, B(17) =>
partial_products_2_17_port, B(16) =>
partial_products_2_16_port, B(15) =>
partial_products_2_15_port, B(14) =>
partial_products_2_14_port, B(13) =>
partial_products_2_13_port, B(12) =>
partial_products_2_12_port, B(11) =>
partial_products_2_11_port, B(10) =>
partial_products_2_10_port, B(9) =>
partial_products_2_9_port, B(8) =>
partial_products_2_8_port, B(7) =>
partial_products_2_7_port, B(6) =>
partial_products_2_6_port, B(5) =>
partial_products_2_5_port, B(4) =>
partial_products_2_4_port, B(3) =>
partial_products_2_3_port, B(2) =>
partial_products_2_2_port, B(1) =>
partial_products_2_1_port, B(0) =>
partial_products_2_0_port, CI => net68890, SUM(31)
=> partial_products_6_31_port, SUM(30) =>
partial_products_6_30_port, SUM(29) =>
partial_products_6_29_port, SUM(28) =>
partial_products_6_28_port, SUM(27) =>
partial_products_6_27_port, SUM(26) =>
partial_products_6_26_port, SUM(25) =>
partial_products_6_25_port, SUM(24) =>
partial_products_6_24_port, SUM(23) =>
partial_products_6_23_port, SUM(22) =>
partial_products_6_22_port, SUM(21) =>
partial_products_6_21_port, SUM(20) =>
partial_products_6_20_port, SUM(19) =>
partial_products_6_19_port, SUM(18) =>
partial_products_6_18_port, SUM(17) =>
partial_products_6_17_port, SUM(16) =>
partial_products_6_16_port, SUM(15) =>
partial_products_6_15_port, SUM(14) =>
partial_products_6_14_port, SUM(13) =>
partial_products_6_13_port, SUM(12) =>
partial_products_6_12_port, SUM(11) =>
partial_products_6_11_port, SUM(10) =>
partial_products_6_10_port, SUM(9) =>
partial_products_6_9_port, SUM(8) =>
partial_products_6_8_port, SUM(7) =>
partial_products_6_7_port, SUM(6) =>
partial_products_6_6_port, SUM(5) =>
partial_products_6_5_port, SUM(4) =>
partial_products_6_4_port, SUM(3) =>
partial_products_6_3_port, SUM(2) =>
partial_products_6_2_port, SUM(1) =>
partial_products_6_1_port, SUM(0) =>
partial_products_6_0_port, CO => net93373);
add_5_root_add_53_G7 : BOOTH_N16_DW01_add_5 port map( A(31) =>
decoded_4_31_port, A(30) => decoded_4_31_port, A(29)
=> decoded_4_31_port, A(28) => decoded_4_31_port,
A(27) => decoded_4_31_port, A(26) =>
decoded_4_31_port, A(25) => decoded_4_31_port, A(24)
=> decoded_4_24_port, A(23) => decoded_4_23_port,
A(22) => decoded_4_22_port, A(21) =>
decoded_4_21_port, A(20) => decoded_4_20_port, A(19)
=> decoded_4_19_port, A(18) => decoded_4_18_port,
A(17) => decoded_4_17_port, A(16) =>
decoded_4_16_port, A(15) => decoded_4_15_port, A(14)
=> decoded_4_14_port, A(13) => decoded_4_13_port,
A(12) => decoded_4_12_port, A(11) =>
decoded_4_11_port, A(10) => decoded_4_10_port, A(9)
=> decoded_4_9_port, A(8) => decoded_4_8_port, A(7)
=> decoded_4_7_port, A(6) => decoded_4_6_port, A(5)
=> decoded_4_5_port, A(4) => decoded_4_4_port, A(3)
=> decoded_4_3_port, A(2) => decoded_4_2_port, A(1)
=> decoded_4_1_port, A(0) => decoded_4_0_port, B(31)
=> decoded_5_31_port, B(30) => decoded_5_31_port,
B(29) => decoded_5_31_port, B(28) =>
decoded_5_31_port, B(27) => decoded_5_31_port, B(26)
=> decoded_5_26_port, B(25) => decoded_5_25_port,
B(24) => decoded_5_24_port, B(23) =>
decoded_5_23_port, B(22) => decoded_5_22_port, B(21)
=> decoded_5_21_port, B(20) => decoded_5_20_port,
B(19) => decoded_5_19_port, B(18) =>
decoded_5_18_port, B(17) => decoded_5_17_port, B(16)
=> decoded_5_16_port, B(15) => decoded_5_15_port,
B(14) => decoded_5_14_port, B(13) =>
decoded_5_13_port, B(12) => decoded_5_12_port, B(11)
=> decoded_5_11_port, B(10) => decoded_5_10_port,
B(9) => decoded_5_9_port, B(8) => decoded_5_8_port,
B(7) => decoded_5_7_port, B(6) => decoded_5_6_port,
B(5) => decoded_5_5_port, B(4) => decoded_5_4_port,
B(3) => decoded_5_3_port, B(2) => decoded_5_2_port,
B(1) => decoded_5_1_port, B(0) => decoded_5_0_port,
CI => net68892, SUM(31) =>
partial_products_4_31_port, SUM(30) =>
partial_products_4_30_port, SUM(29) =>
partial_products_4_29_port, SUM(28) =>
partial_products_4_28_port, SUM(27) =>
partial_products_4_27_port, SUM(26) =>
partial_products_4_26_port, SUM(25) =>
partial_products_4_25_port, SUM(24) =>
partial_products_4_24_port, SUM(23) =>
partial_products_4_23_port, SUM(22) =>
partial_products_4_22_port, SUM(21) =>
partial_products_4_21_port, SUM(20) =>
partial_products_4_20_port, SUM(19) =>
partial_products_4_19_port, SUM(18) =>
partial_products_4_18_port, SUM(17) =>
partial_products_4_17_port, SUM(16) =>
partial_products_4_16_port, SUM(15) =>
partial_products_4_15_port, SUM(14) =>
partial_products_4_14_port, SUM(13) =>
partial_products_4_13_port, SUM(12) =>
partial_products_4_12_port, SUM(11) =>
partial_products_4_11_port, SUM(10) =>
partial_products_4_10_port, SUM(9) =>
partial_products_4_9_port, SUM(8) =>
partial_products_4_8_port, SUM(7) => net93364,
SUM(6) => net93365, SUM(5) => net93366, SUM(4) =>
net93367, SUM(3) => net93368, SUM(2) => net93369,
SUM(1) => net93370, SUM(0) => net93371, CO =>
net93372);
add_6_root_add_53_G7 : BOOTH_N16_DW01_add_6 port map( A(31) =>
decoded_2_31_port, A(30) => decoded_2_31_port, A(29)
=> decoded_2_31_port, A(28) => decoded_2_31_port,
A(27) => decoded_2_31_port, A(26) =>
decoded_2_31_port, A(25) => decoded_2_31_port, A(24)
=> decoded_2_31_port, A(23) => decoded_2_31_port,
A(22) => decoded_2_31_port, A(21) =>
decoded_2_31_port, A(20) => decoded_2_20_port, A(19)
=> decoded_2_19_port, A(18) => decoded_2_18_port,
A(17) => decoded_2_17_port, A(16) =>
decoded_2_16_port, A(15) => decoded_2_15_port, A(14)
=> decoded_2_14_port, A(13) => decoded_2_13_port,
A(12) => decoded_2_12_port, A(11) =>
decoded_2_11_port, A(10) => decoded_2_10_port, A(9)
=> decoded_2_9_port, A(8) => decoded_2_8_port, A(7)
=> decoded_2_7_port, A(6) => decoded_2_6_port, A(5)
=> decoded_2_5_port, A(4) => decoded_2_4_port, A(3)
=> decoded_2_3_port, A(2) => decoded_2_2_port, A(1)
=> decoded_2_1_port, A(0) => decoded_2_0_port, B(31)
=> decoded_3_31_port, B(30) => decoded_3_31_port,
B(29) => decoded_3_31_port, B(28) =>
decoded_3_31_port, B(27) => decoded_3_31_port, B(26)
=> decoded_3_31_port, B(25) => decoded_3_31_port,
B(24) => decoded_3_31_port, B(23) =>
decoded_3_31_port, B(22) => decoded_3_22_port, B(21)
=> decoded_3_21_port, B(20) => decoded_3_20_port,
B(19) => decoded_3_19_port, B(18) =>
decoded_3_18_port, B(17) => decoded_3_17_port, B(16)
=> decoded_3_16_port, B(15) => decoded_3_15_port,
B(14) => decoded_3_14_port, B(13) =>
decoded_3_13_port, B(12) => decoded_3_12_port, B(11)
=> decoded_3_11_port, B(10) => decoded_3_10_port,
B(9) => decoded_3_9_port, B(8) => decoded_3_8_port,
B(7) => decoded_3_7_port, B(6) => decoded_3_6_port,
B(5) => decoded_3_5_port, B(4) => decoded_3_4_port,
B(3) => decoded_3_3_port, B(2) => decoded_3_2_port,
B(1) => decoded_3_1_port, B(0) => decoded_3_0_port,
CI => n7, SUM(31) => partial_products_3_31_port,
SUM(30) => partial_products_3_30_port, SUM(29) =>
partial_products_3_29_port, SUM(28) =>
partial_products_3_28_port, SUM(27) =>
partial_products_3_27_port, SUM(26) =>
partial_products_3_26_port, SUM(25) =>
partial_products_3_25_port, SUM(24) =>
partial_products_3_24_port, SUM(23) =>
partial_products_3_23_port, SUM(22) =>
partial_products_3_22_port, SUM(21) =>
partial_products_3_21_port, SUM(20) =>
partial_products_3_20_port, SUM(19) =>
partial_products_3_19_port, SUM(18) =>
partial_products_3_18_port, SUM(17) =>
partial_products_3_17_port, SUM(16) =>
partial_products_3_16_port, SUM(15) =>
partial_products_3_15_port, SUM(14) =>
partial_products_3_14_port, SUM(13) =>
partial_products_3_13_port, SUM(12) =>
partial_products_3_12_port, SUM(11) =>
partial_products_3_11_port, SUM(10) =>
partial_products_3_10_port, SUM(9) =>
partial_products_3_9_port, SUM(8) =>
partial_products_3_8_port, SUM(7) =>
partial_products_3_7_port, SUM(6) =>
partial_products_3_6_port, SUM(5) =>
partial_products_3_5_port, SUM(4) =>
partial_products_3_4_port, SUM(3) => net93359,
SUM(2) => net93360, SUM(1) => net93361, SUM(0) =>
net93362, CO => net93363);
add_7_root_add_53_G7 : BOOTH_N16_DW01_add_7 port map( A(31) =>
decoded_0_31_port, A(30) => decoded_0_31_port, A(29)
=> decoded_0_31_port, A(28) => decoded_0_31_port,
A(27) => decoded_0_31_port, A(26) =>
decoded_0_31_port, A(25) => decoded_0_31_port, A(24)
=> decoded_0_31_port, A(23) => decoded_0_31_port,
A(22) => decoded_0_31_port, A(21) =>
decoded_0_31_port, A(20) => decoded_0_31_port, A(19)
=> decoded_0_31_port, A(18) => decoded_0_31_port,
A(17) => decoded_0_31_port, A(16) => N225, A(15) =>
N224, A(14) => N223, A(13) => N222, A(12) => N221,
A(11) => N220, A(10) => N219, A(9) => N218, A(8) =>
N217, A(7) => N216, A(6) => N215, A(5) => N214, A(4)
=> N213, A(3) => N212, A(2) => N211, A(1) => N210,
A(0) => N209, B(31) => decoded_1_31_port, B(30) =>
decoded_1_31_port, B(29) => decoded_1_31_port, B(28)
=> decoded_1_31_port, B(27) => decoded_1_31_port,
B(26) => decoded_1_31_port, B(25) =>
decoded_1_31_port, B(24) => decoded_1_31_port, B(23)
=> decoded_1_31_port, B(22) => decoded_1_31_port,
B(21) => decoded_1_31_port, B(20) =>
decoded_1_31_port, B(19) => decoded_1_31_port, B(18)
=> decoded_1_18_port, B(17) => decoded_1_17_port,
B(16) => decoded_1_16_port, B(15) =>
decoded_1_15_port, B(14) => decoded_1_14_port, B(13)
=> decoded_1_13_port, B(12) => decoded_1_12_port,
B(11) => decoded_1_11_port, B(10) =>
decoded_1_10_port, B(9) => decoded_1_9_port, B(8) =>
decoded_1_8_port, B(7) => decoded_1_7_port, B(6) =>
decoded_1_6_port, B(5) => decoded_1_5_port, B(4) =>
decoded_1_4_port, B(3) => decoded_1_3_port, B(2) =>
decoded_1_2_port, B(1) => decoded_1_1_port, B(0) =>
decoded_1_0_port, CI => net68893, SUM(31) =>
partial_products_2_31_port, SUM(30) =>
partial_products_2_30_port, SUM(29) =>
partial_products_2_29_port, SUM(28) =>
partial_products_2_28_port, SUM(27) =>
partial_products_2_27_port, SUM(26) =>
partial_products_2_26_port, SUM(25) =>
partial_products_2_25_port, SUM(24) =>
partial_products_2_24_port, SUM(23) =>
partial_products_2_23_port, SUM(22) =>
partial_products_2_22_port, SUM(21) =>
partial_products_2_21_port, SUM(20) =>
partial_products_2_20_port, SUM(19) =>
partial_products_2_19_port, SUM(18) =>
partial_products_2_18_port, SUM(17) =>
partial_products_2_17_port, SUM(16) =>
partial_products_2_16_port, SUM(15) =>
partial_products_2_15_port, SUM(14) =>
partial_products_2_14_port, SUM(13) =>
partial_products_2_13_port, SUM(12) =>
partial_products_2_12_port, SUM(11) =>
partial_products_2_11_port, SUM(10) =>
partial_products_2_10_port, SUM(9) =>
partial_products_2_9_port, SUM(8) =>
partial_products_2_8_port, SUM(7) =>
partial_products_2_7_port, SUM(6) =>
partial_products_2_6_port, SUM(5) =>
partial_products_2_5_port, SUM(4) =>
partial_products_2_4_port, SUM(3) =>
partial_products_2_3_port, SUM(2) =>
partial_products_2_2_port, SUM(1) =>
partial_products_2_1_port, SUM(0) =>
partial_products_2_0_port, CO => net93358);
U3 : OAI222XL port map( A0 => n76, A1 => n309, B0 => n66, B1 => n310, C0 =>
n65, C1 => n312, Y => N220);
U4 : NAND2X2 port map( A => B(0), B => B(1), Y => n310);
U5 : OAI222XL port map( A0 => n156, A1 => n309, B0 => n146, B1 => n310, C0
=> n147, C1 => n312, Y => N211);
U6 : OAI221XL port map( A0 => n156, A1 => n283, B0 => n157, B1 => n284, C0
=> n297, Y => decoded_1_3_port);
U7 : NAND2XL port map( A => B(0), B => n306, Y => n312);
U8 : NAND2BXL port map( AN => B(0), B => B(1), Y => n309);
U9 : NAND2XL port map( A => B(3), B => n308, Y => n283);
U10 : XOR2XL port map( A => B(2), B => B(1), Y => n308);
U11 : INVXL port map( A => B(2), Y => n307);
U12 : XOR2XL port map( A => B(4), B => B(3), Y => n282);
U13 : INVXL port map( A => B(1), Y => n306);
U14 : INVXL port map( A => B(3), Y => n281);
U15 : INVX2 port map( A => B(4), Y => n1);
partial_products_7_0_port <= '0';
partial_products_7_1_port <= '0';
partial_products_7_2_port <= '0';
partial_products_7_3_port <= '0';
U20 : XOR2X1 port map( A => n2, B => n3, Y => partial_products_5_31_port);
U21 : XNOR2X1 port map( A => n4, B => n5, Y => n3);
U22 : AOI21X1 port map( A0 => n6, A1 => n8, B0 => n9, Y => n5);
U23 : OAI21X1 port map( A0 => n10, A1 => n11, B0 => n4, Y => n2);
U24 : XOR2X1 port map( A => n10, B => n12, Y => partial_products_5_30_port);
U25 : XOR2X1 port map( A => n11, B => n4, Y => n12);
U26 : AO2B2X1 port map( B0 => n13, B1 => n4, A0 => n14, A1N => n15, Y => n11
);
U31 : NOR2X1 port map( A => n4, B => n13, Y => n15);
U35 : OAI222X1 port map( A0 => n16, A1 => n17, B0 => n8, B1 => n18, C0 => n9
, C1 => n6, Y => n10);
U36 : XOR2X1 port map( A => n13, B => n19, Y => partial_products_5_29_port);
U37 : XOR2X1 port map( A => n14, B => n4, Y => n19);
U38 : AOI21X1 port map( A0 => n20, A1 => n21, B0 => n9, Y => n4);
U39 : AO2B2X1 port map( B0 => n22, B1 => n23, A0 => n24, A1N => n25, Y =>
n14);
U40 : NOR2X1 port map( A => n23, B => n22, Y => n25);
U41 : OAI221X1 port map( A0 => n26, A1 => n17, B0 => n6, B1 => n18, C0 =>
n27, Y => n13);
U42 : AOI22XL port map( A0 => n28, A1 => n29, B0 => A(14), B1 => n30, Y =>
n27);
U43 : XNOR2X1 port map( A => n31, B => n23, Y => partial_products_5_28_port)
;
U44 : OAI221X1 port map( A0 => n26, A1 => n32, B0 => n6, B1 => n33, C0 =>
n34, Y => n23);
U45 : AOI22XL port map( A0 => n35, A1 => n29, B0 => A(13), B1 => n30, Y =>
n34);
U46 : XNOR2X1 port map( A => n24, B => n22, Y => n31);
U47 : OAI222X1 port map( A0 => n36, A1 => n17, B0 => n20, B1 => n18, C0 =>
n9, C1 => n21, Y => n22);
U48 : CLKINVX1 port map( A => n37, Y => n20);
U49 : AO2B2X1 port map( B0 => n38, B1 => n39, A0 => n40, A1N => n41, Y =>
n24);
U50 : NOR2X1 port map( A => n39, B => n38, Y => n41);
U51 : XNOR2X1 port map( A => n42, B => n39, Y => partial_products_5_27_port)
;
U52 : OAI221X1 port map( A0 => n26, A1 => n43, B0 => n6, B1 => n44, C0 =>
n45, Y => n39);
U53 : AOI22XL port map( A0 => n46, A1 => n29, B0 => A(12), B1 => n30, Y =>
n45);
U54 : XNOR2X1 port map( A => n40, B => n38, Y => n42);
U55 : OAI221X1 port map( A0 => n47, A1 => n17, B0 => n21, B1 => n18, C0 =>
n48, Y => n38);
U56 : AOI22XL port map( A0 => n28, A1 => n37, B0 => A(14), B1 => n49, Y =>
n48);
U57 : AO2B2X1 port map( B0 => n50, B1 => n51, A0 => n52, A1N => n53, Y =>
n40);
U58 : NOR2X1 port map( A => n51, B => n50, Y => n53);
U59 : XNOR2X1 port map( A => n54, B => n51, Y => partial_products_5_26_port)
;
U60 : OAI221X1 port map( A0 => n26, A1 => n55, B0 => n6, B1 => n56, C0 =>
n57, Y => n51);
U61 : AOI22XL port map( A0 => n58, A1 => n29, B0 => A(11), B1 => n30, Y =>
n57);
U62 : XNOR2X1 port map( A => n52, B => n50, Y => n54);
U63 : OAI221X1 port map( A0 => n47, A1 => n32, B0 => n21, B1 => n33, C0 =>
n59, Y => n50);
U64 : AOI22XL port map( A0 => n35, A1 => n37, B0 => A(13), B1 => n49, Y =>
n59);
U65 : AO2B2X1 port map( B0 => n60, B1 => n61, A0 => n62, A1N => n63, Y =>
n52);
U66 : NOR2X1 port map( A => n61, B => n60, Y => n63);
U67 : XNOR2X1 port map( A => n64, B => n61, Y => partial_products_5_25_port)
;
U68 : OAI221X1 port map( A0 => n26, A1 => n65, B0 => n6, B1 => n66, C0 =>
n67, Y => n61);
U69 : AOI22XL port map( A0 => n68, A1 => n29, B0 => A(10), B1 => n30, Y =>
n67);
U70 : XNOR2X1 port map( A => n62, B => n60, Y => n64);
U71 : OAI221X1 port map( A0 => n47, A1 => n43, B0 => n21, B1 => n44, C0 =>
n69, Y => n60);
U72 : AOI22XL port map( A0 => n46, A1 => n37, B0 => A(12), B1 => n49, Y =>
n69);
U73 : AO2B2X1 port map( B0 => n70, B1 => n71, A0 => n72, A1N => n73, Y =>
n62);
U74 : NOR2X1 port map( A => n71, B => n70, Y => n73);
U75 : XNOR2X1 port map( A => n74, B => n71, Y => partial_products_5_24_port)
;
U76 : OAI221X1 port map( A0 => n26, A1 => n75, B0 => n6, B1 => n76, C0 =>
n77, Y => n71);
U77 : AOI22XL port map( A0 => n78, A1 => n29, B0 => A(9), B1 => n30, Y =>
n77);
U78 : XNOR2X1 port map( A => n72, B => n70, Y => n74);
U79 : OAI221X1 port map( A0 => n47, A1 => n55, B0 => n21, B1 => n56, C0 =>
n79, Y => n70);
U80 : AOI22XL port map( A0 => n58, A1 => n37, B0 => A(11), B1 => n49, Y =>
n79);
U81 : AO2B2X1 port map( B0 => n80, B1 => n81, A0 => n82, A1N => n83, Y =>
n72);
U82 : NOR2X1 port map( A => n81, B => n80, Y => n83);
U83 : XNOR2X1 port map( A => n84, B => n81, Y => partial_products_5_23_port)
;
U84 : OAI221X1 port map( A0 => n26, A1 => n85, B0 => n6, B1 => n86, C0 =>
n87, Y => n81);
U85 : AOI22XL port map( A0 => n88, A1 => n29, B0 => A(8), B1 => n30, Y =>
n87);
U86 : XNOR2X1 port map( A => n82, B => n80, Y => n84);
U87 : OAI221X1 port map( A0 => n47, A1 => n65, B0 => n21, B1 => n66, C0 =>
n89, Y => n80);
U88 : AOI22XL port map( A0 => n68, A1 => n37, B0 => A(10), B1 => n49, Y =>
n89);
U89 : AO2B2X1 port map( B0 => n90, B1 => n91, A0 => n92, A1N => n93, Y =>
n82);
U90 : NOR2X1 port map( A => n91, B => n90, Y => n93);
U91 : XNOR2X1 port map( A => n94, B => n91, Y => partial_products_5_22_port)
;
U92 : OAI221X1 port map( A0 => n26, A1 => n95, B0 => n6, B1 => n96, C0 =>
n97, Y => n91);
U93 : AOI22XL port map( A0 => n98, A1 => n29, B0 => A(7), B1 => n30, Y =>
n97);
U94 : XNOR2X1 port map( A => n92, B => n90, Y => n94);
U95 : OAI221X1 port map( A0 => n47, A1 => n75, B0 => n21, B1 => n76, C0 =>
n99, Y => n90);
U96 : AOI22XL port map( A0 => n78, A1 => n37, B0 => A(9), B1 => n49, Y =>
n99);
U97 : AO2B2X1 port map( B0 => n100, B1 => n101, A0 => n102, A1N => n103, Y
=> n92);
U98 : NOR2X1 port map( A => n101, B => n100, Y => n103);
U99 : XNOR2X1 port map( A => n104, B => n101, Y =>
partial_products_5_21_port);
U100 : OAI221X1 port map( A0 => n26, A1 => n105, B0 => n6, B1 => n106, C0 =>
n107, Y => n101);
U101 : AOI22XL port map( A0 => n108, A1 => n29, B0 => A(6), B1 => n30, Y =>
n107);
U102 : XNOR2X1 port map( A => n102, B => n100, Y => n104);
U103 : OAI221X1 port map( A0 => n47, A1 => n85, B0 => n21, B1 => n86, C0 =>
n109, Y => n100);
U104 : AOI22XL port map( A0 => n88, A1 => n37, B0 => A(8), B1 => n49, Y =>
n109);
U105 : AO2B2X1 port map( B0 => n110, B1 => n111, A0 => n112, A1N => n113, Y
=> n102);
U106 : NOR2X1 port map( A => n111, B => n110, Y => n113);
U107 : XNOR2X1 port map( A => n114, B => n111, Y =>
partial_products_5_20_port);
U108 : OAI221X1 port map( A0 => n26, A1 => n115, B0 => n6, B1 => n116, C0 =>
n117, Y => n111);
U109 : AOI22XL port map( A0 => n118, A1 => n29, B0 => A(5), B1 => n30, Y =>
n117);
U110 : XNOR2X1 port map( A => n112, B => n110, Y => n114);
U111 : OAI221X1 port map( A0 => n47, A1 => n95, B0 => n21, B1 => n96, C0 =>
n119, Y => n110);
U112 : AOI22XL port map( A0 => n98, A1 => n37, B0 => A(7), B1 => n49, Y =>
n119);
U113 : AO2B2X1 port map( B0 => n120, B1 => n121, A0 => n122, A1N => n123, Y
=> n112);
U114 : NOR2X1 port map( A => n121, B => n120, Y => n123);
U115 : XNOR2X1 port map( A => n124, B => n121, Y =>
partial_products_5_19_port);
U116 : OAI221X1 port map( A0 => n26, A1 => n125, B0 => n6, B1 => n126, C0 =>
n127, Y => n121);
U117 : AOI22XL port map( A0 => n29, A1 => n128, B0 => n30, B1 => A(4), Y =>
n127);
U118 : CLKINVX1 port map( A => n16, Y => n30);
U119 : CLKINVX1 port map( A => n8, Y => n29);
U120 : XNOR2X1 port map( A => n122, B => n120, Y => n124);
U121 : OAI221X1 port map( A0 => n47, A1 => n105, B0 => n21, B1 => n106, C0
=> n129, Y => n120);
U122 : AOI22XL port map( A0 => n108, A1 => n37, B0 => A(6), B1 => n49, Y =>
n129);
U123 : AO2B2X1 port map( B0 => n130, B1 => n131, A0 => n132, A1N => n133, Y
=> n122);
U124 : NOR2X1 port map( A => n131, B => n130, Y => n133);
U125 : XNOR2X1 port map( A => n134, B => n131, Y =>
partial_products_5_18_port);
U126 : OAI221X1 port map( A0 => n135, A1 => n8, B0 => n136, B1 => n16, C0 =>
n137, Y => n131);
U127 : AOI22XL port map( A0 => A(4), A1 => n138, B0 => n128, B1 => n139, Y
=> n137);
U128 : XNOR2X1 port map( A => n132, B => n130, Y => n134);
U129 : OAI221X1 port map( A0 => n47, A1 => n115, B0 => n21, B1 => n116, C0
=> n140, Y => n130);
U130 : AOI22XL port map( A0 => n118, A1 => n37, B0 => A(5), B1 => n49, Y =>
n140);
U131 : AO2B2X1 port map( B0 => n141, B1 => n142, A0 => n143, A1N => n144, Y
=> n132);
U132 : NOR2X1 port map( A => n142, B => n141, Y => n144);
U133 : XNOR2X1 port map( A => n145, B => n142, Y =>
partial_products_5_17_port);
U134 : OAI221X1 port map( A0 => n146, A1 => n8, B0 => n147, B1 => n16, C0 =>
n148, Y => n142);
U135 : AOI22XL port map( A0 => n138, A1 => A(3), B0 => n139, B1 => n149, Y
=> n148);
U136 : XNOR2X1 port map( A => n143, B => n141, Y => n145);
U137 : OAI221X1 port map( A0 => n47, A1 => n125, B0 => n21, B1 => n126, C0
=> n150, Y => n141);
U138 : AOI22XL port map( A0 => n128, A1 => n37, B0 => A(4), B1 => n49, Y =>
n150);
U139 : OAI2BB1X1 port map( A0N => n151, A1N => n152, B0 => n153, Y => n143);
U140 : OAI21X1 port map( A0 => n152, A1 => n151, B0 => n154, Y => n153);
U141 : XNOR2X1 port map( A => n155, B => n152, Y =>
partial_products_5_16_port);
U142 : OAI221X1 port map( A0 => n156, A1 => n8, B0 => n157, B1 => n16, C0 =>
n158, Y => n152);
U143 : AOI22XL port map( A0 => n138, A1 => A(2), B0 => n139, B1 => n159, Y
=> n158);
U144 : XNOR2X1 port map( A => n154, B => n151, Y => n155);
U145 : OAI221X1 port map( A0 => n47, A1 => n160, B0 => n21, B1 => n161, C0
=> n162, Y => n151);
U146 : AOI22XL port map( A0 => n149, A1 => n37, B0 => A(3), B1 => n49, Y =>
n162);
U147 : OAI21X1 port map( A0 => n163, A1 => n164, B0 => n165, Y => n154);
U148 : OAI2BB1X1 port map( A0N => n164, A1N => n163, B0 => n166, Y => n165);
U149 : XOR2X1 port map( A => n163, B => n167, Y =>
partial_products_5_15_port);
U150 : XOR2X1 port map( A => n164, B => n166, Y => n167);
U151 : OAI221X1 port map( A0 => n47, A1 => n136, B0 => n135, B1 => n21, C0
=> n168, Y => n166);
U152 : AOI22XL port map( A0 => n37, A1 => n159, B0 => n49, B1 => A(2), Y =>
n168);
U153 : CLKNAND2X2 port map( A => n169, B => n170, Y => n164);
U154 : AOI221XL port map( A0 => A(1), A1 => n138, B0 => n171, B1 => n139, C0
=> n172, Y => n163);
U155 : AOI21X1 port map( A0 => n8, A1 => n16, B0 => n173, Y => n172);
U156 : NAND3XL port map( A => B(13), B => n174, C => B(14), Y => n16);
U157 : NAND3XL port map( A => n175, B => n176, C => B(15), Y => n8);
U158 : CLKINVX1 port map( A => B(14), Y => n176);
U159 : CLKINVX1 port map( A => n6, Y => n139);
U160 : CLKINVX1 port map( A => n26, Y => n138);
U161 : XOR2X1 port map( A => n170, B => n169, Y =>
partial_products_5_14_port);
U162 : AOI21X1 port map( A0 => n26, A1 => n6, B0 => n173, Y => n169);
U163 : CLKNAND2X2 port map( A => B(15), B => n177, Y => n6);
U164 : CLKNAND2X2 port map( A => n177, B => n174, Y => n26);
U165 : XOR2X1 port map( A => B(14), B => B(13), Y => n177);
U166 : OAI221X1 port map( A0 => n147, A1 => n47, B0 => n146, B1 => n21, C0
=> n178, Y => n170);
U167 : AOI22XL port map( A0 => n37, A1 => n171, B0 => A(1), B1 => n49, Y =>
n178);
U168 : OAI221X1 port map( A0 => n47, A1 => n157, B0 => n156, B1 => n21, C0
=> n179, Y => partial_products_5_13_port);
U169 : OAI21X1 port map( A0 => n37, A1 => n49, B0 => A(0), Y => n179);
U170 : CLKINVX1 port map( A => n36, Y => n49);
U171 : NAND3XL port map( A => B(12), B => n175, C => B(11), Y => n36);
U172 : NOR3X1 port map( A => B(11), B => B(12), C => n175, Y => n37);
U173 : AOI21X1 port map( A0 => n21, A1 => n47, B0 => n173, Y =>
partial_products_5_12_port);
U174 : CLKNAND2X2 port map( A => n180, B => n175, Y => n47);
U175 : CLKINVX1 port map( A => B(13), Y => n175);
U176 : CLKNAND2X2 port map( A => B(13), B => n180, Y => n21);
U177 : XNOR2X1 port map( A => B(12), B => n181, Y => n180);
U178 : NOR2X1 port map( A => n174, B => n17, Y => decoded_8_31_port);
U179 : NOR2X1 port map( A => n174, B => n32, Y => decoded_8_30_port);
U180 : NOR2X1 port map( A => n174, B => n43, Y => decoded_8_29_port);
U181 : NOR2X1 port map( A => n174, B => n55, Y => decoded_8_28_port);
U182 : NOR2X1 port map( A => n174, B => n65, Y => decoded_8_27_port);
U183 : NOR2X1 port map( A => n174, B => n75, Y => decoded_8_26_port);
U184 : NOR2X1 port map( A => n174, B => n85, Y => decoded_8_25_port);
U185 : NOR2X1 port map( A => n174, B => n95, Y => decoded_8_24_port);
U186 : NOR2X1 port map( A => n174, B => n105, Y => decoded_8_23_port);
U187 : NOR2X1 port map( A => n174, B => n115, Y => decoded_8_22_port);
U188 : NOR2X1 port map( A => n174, B => n125, Y => decoded_8_21_port);
U189 : NOR2X1 port map( A => n174, B => n160, Y => decoded_8_20_port);
U190 : NOR2X1 port map( A => n136, B => n174, Y => decoded_8_19_port);
U191 : NOR2X1 port map( A => n147, B => n174, Y => decoded_8_18_port);
U192 : NOR2X1 port map( A => n174, B => n157, Y => decoded_8_17_port);
U193 : NOR2X1 port map( A => n174, B => n173, Y => decoded_8_16_port);
U194 : CLKINVX1 port map( A => B(15), Y => n174);
U195 : AOI21X1 port map( A0 => n182, A1 => n183, B0 => n9, Y =>
decoded_5_31_port);
U196 : OAI222X1 port map( A0 => n17, A1 => n184, B0 => n18, B1 => n182, C0
=> n9, C1 => n183, Y => decoded_5_26_port);
U197 : OAI221X1 port map( A0 => n17, A1 => n185, B0 => n18, B1 => n183, C0
=> n186, Y => decoded_5_25_port);
U198 : AOI22XL port map( A0 => n187, A1 => n28, B0 => n188, B1 => A(14), Y
=> n186);
U199 : OAI221X1 port map( A0 => n32, A1 => n185, B0 => n33, B1 => n183, C0
=> n189, Y => decoded_5_24_port);
U200 : AOI22XL port map( A0 => n187, A1 => n35, B0 => n188, B1 => A(13), Y
=> n189);
U201 : OAI221X1 port map( A0 => n43, A1 => n185, B0 => n44, B1 => n183, C0
=> n190, Y => decoded_5_23_port);
U202 : AOI22XL port map( A0 => n187, A1 => n46, B0 => n188, B1 => A(12), Y
=> n190);
U203 : OAI221X1 port map( A0 => n55, A1 => n185, B0 => n56, B1 => n183, C0
=> n191, Y => decoded_5_22_port);
U204 : AOI22XL port map( A0 => n187, A1 => n58, B0 => n188, B1 => A(11), Y
=> n191);
U205 : OAI221X1 port map( A0 => n65, A1 => n185, B0 => n66, B1 => n183, C0
=> n192, Y => decoded_5_21_port);
U206 : AOI22XL port map( A0 => n187, A1 => n68, B0 => n188, B1 => A(10), Y
=> n192);
U207 : OAI221X1 port map( A0 => n75, A1 => n185, B0 => n76, B1 => n183, C0
=> n193, Y => decoded_5_20_port);
U208 : AOI22XL port map( A0 => n187, A1 => n78, B0 => n188, B1 => A(9), Y =>
n193);
U209 : OAI221X1 port map( A0 => n85, A1 => n185, B0 => n86, B1 => n183, C0
=> n194, Y => decoded_5_19_port);
U210 : AOI22XL port map( A0 => n187, A1 => n88, B0 => n188, B1 => A(8), Y =>
n194);
U211 : OAI221X1 port map( A0 => n95, A1 => n185, B0 => n96, B1 => n183, C0
=> n195, Y => decoded_5_18_port);
U212 : AOI22XL port map( A0 => n187, A1 => n98, B0 => n188, B1 => A(7), Y =>
n195);
U213 : OAI221X1 port map( A0 => n105, A1 => n185, B0 => n106, B1 => n183, C0
=> n196, Y => decoded_5_17_port);
U214 : AOI22XL port map( A0 => n187, A1 => n108, B0 => n188, B1 => A(6), Y
=> n196);
U215 : OAI221X1 port map( A0 => n115, A1 => n185, B0 => n116, B1 => n183, C0
=> n197, Y => decoded_5_16_port);
U216 : AOI22XL port map( A0 => n187, A1 => n118, B0 => n188, B1 => A(5), Y
=> n197);
U217 : OAI221X1 port map( A0 => n125, A1 => n185, B0 => n126, B1 => n183, C0
=> n198, Y => decoded_5_15_port);
U218 : AOI22XL port map( A0 => n187, A1 => n128, B0 => n188, B1 => A(4), Y
=> n198);
U219 : OAI221X1 port map( A0 => n160, A1 => n185, B0 => n161, B1 => n183, C0
=> n199, Y => decoded_5_14_port);
U220 : AOI22XL port map( A0 => n187, A1 => n149, B0 => n188, B1 => A(3), Y
=> n199);
U221 : OAI221X1 port map( A0 => n146, A1 => n182, B0 => n147, B1 => n184, C0
=> n200, Y => decoded_5_13_port);
U222 : AOI22XL port map( A0 => n201, A1 => A(3), B0 => n202, B1 => n149, Y
=> n200);
U223 : OAI221X1 port map( A0 => n156, A1 => n182, B0 => n157, B1 => n184, C0
=> n203, Y => decoded_5_12_port);
U224 : AOI22XL port map( A0 => n201, A1 => A(2), B0 => n202, B1 => n159, Y
=> n203);
U225 : CLKINVX1 port map( A => n183, Y => n202);
U226 : CLKINVX1 port map( A => n185, Y => n201);
U227 : CLKINVX1 port map( A => n187, Y => n182);
U228 : OAI221X1 port map( A0 => n157, A1 => n185, B0 => n156, B1 => n183, C0
=> n204, Y => decoded_5_11_port);
U229 : OAI21X1 port map( A0 => n187, A1 => n188, B0 => A(0), Y => n204);
U230 : CLKINVX1 port map( A => n184, Y => n188);
U231 : NAND3XL port map( A => B(9), B => n181, C => B(10), Y => n184);
U232 : NOR3X1 port map( A => B(10), B => B(9), C => n181, Y => n187);
U233 : AOI21X1 port map( A0 => n183, A1 => n185, B0 => n173, Y =>
decoded_5_10_port);
U234 : CLKNAND2X2 port map( A => n205, B => n181, Y => n185);
U235 : CLKINVX1 port map( A => B(11), Y => n181);
U236 : CLKNAND2X2 port map( A => B(11), B => n205, Y => n183);
U237 : XNOR2X1 port map( A => B(10), B => n206, Y => n205);
U238 : OAI221X1 port map( A0 => n156, A1 => n207, B0 => n157, B1 => n208, C0
=> n209_port, Y => decoded_4_9_port);
U239 : OAI21X1 port map( A0 => n210_port, A1 => n211_port, B0 => A(0), Y =>
n209_port);
U240 : AOI21X1 port map( A0 => n208, A1 => n207, B0 => n173, Y =>
decoded_4_8_port);
U241 : AOI21X1 port map( A0 => n207, A1 => n212_port, B0 => n9, Y =>
decoded_4_31_port);
U242 : OAI222X1 port map( A0 => n18, A1 => n212_port, B0 => n9, B1 => n207,
C0 => n17, C1 => n213_port, Y => decoded_4_24_port);
U243 : OAI221X1 port map( A0 => n18, A1 => n207, B0 => n17, B1 => n208, C0
=> n214_port, Y => decoded_4_23_port);
U244 : AOI22XL port map( A0 => n210_port, A1 => n28, B0 => n211_port, B1 =>
A(14), Y => n214_port);
U245 : OAI221X1 port map( A0 => n33, A1 => n207, B0 => n32, B1 => n208, C0
=> n215_port, Y => decoded_4_22_port);
U246 : AOI22XL port map( A0 => n210_port, A1 => n35, B0 => n211_port, B1 =>
A(13), Y => n215_port);
U247 : OAI221X1 port map( A0 => n44, A1 => n207, B0 => n43, B1 => n208, C0
=> n216_port, Y => decoded_4_21_port);
U248 : AOI22XL port map( A0 => n210_port, A1 => n46, B0 => n211_port, B1 =>
A(12), Y => n216_port);
U249 : OAI221X1 port map( A0 => n56, A1 => n207, B0 => n55, B1 => n208, C0
=> n217_port, Y => decoded_4_20_port);
U250 : AOI22XL port map( A0 => n210_port, A1 => n58, B0 => n211_port, B1 =>
A(11), Y => n217_port);
U251 : OAI221X1 port map( A0 => n66, A1 => n207, B0 => n65, B1 => n208, C0
=> n218_port, Y => decoded_4_19_port);
U252 : AOI22XL port map( A0 => n210_port, A1 => n68, B0 => n211_port, B1 =>
A(10), Y => n218_port);
U253 : OAI221X1 port map( A0 => n76, A1 => n207, B0 => n75, B1 => n208, C0
=> n219_port, Y => decoded_4_18_port);
U254 : AOI22XL port map( A0 => n210_port, A1 => n78, B0 => n211_port, B1 =>
A(9), Y => n219_port);
U255 : OAI221X1 port map( A0 => n86, A1 => n207, B0 => n85, B1 => n208, C0
=> n220_port, Y => decoded_4_17_port);
U256 : AOI22XL port map( A0 => n210_port, A1 => n88, B0 => n211_port, B1 =>
A(8), Y => n220_port);
U257 : OAI221X1 port map( A0 => n96, A1 => n207, B0 => n95, B1 => n208, C0
=> n221_port, Y => decoded_4_16_port);
U258 : AOI22XL port map( A0 => n210_port, A1 => n98, B0 => n211_port, B1 =>
A(7), Y => n221_port);
U259 : OAI221X1 port map( A0 => n106, A1 => n207, B0 => n105, B1 => n208, C0
=> n222_port, Y => decoded_4_15_port);
U260 : AOI22XL port map( A0 => n210_port, A1 => n108, B0 => n211_port, B1 =>
A(6), Y => n222_port);
U261 : OAI221X1 port map( A0 => n116, A1 => n207, B0 => n115, B1 => n208, C0
=> n223_port, Y => decoded_4_14_port);
U262 : AOI22XL port map( A0 => n210_port, A1 => n118, B0 => n211_port, B1 =>
A(5), Y => n223_port);
U263 : OAI221X1 port map( A0 => n126, A1 => n207, B0 => n125, B1 => n208, C0
=> n224_port, Y => decoded_4_13_port);
U264 : AOI22XL port map( A0 => n210_port, A1 => n128, B0 => n211_port, B1 =>
A(4), Y => n224_port);
U265 : CLKINVX1 port map( A => n213_port, Y => n211_port);
U266 : CLKINVX1 port map( A => n212_port, Y => n210_port);
U267 : OAI221X1 port map( A0 => n135, A1 => n212_port, B0 => n136, B1 =>
n213_port, C0 => n225_port, Y => decoded_4_12_port);
U268 : AOI22XL port map( A0 => n226, A1 => n128, B0 => n227, B1 => A(4), Y
=> n225_port);
U269 : OAI221X1 port map( A0 => n146, A1 => n212_port, B0 => n147, B1 =>
n213_port, C0 => n228, Y => decoded_4_11_port);
U270 : AOI22XL port map( A0 => n226, A1 => n149, B0 => n227, B1 => A(3), Y
=> n228);
U271 : OAI221X1 port map( A0 => n156, A1 => n212_port, B0 => n157, B1 =>
n213_port, C0 => n229, Y => decoded_4_10_port);
U272 : AOI22XL port map( A0 => n226, A1 => n159, B0 => n227, B1 => A(2), Y
=> n229);
U273 : CLKINVX1 port map( A => n208, Y => n227);
U274 : CLKNAND2X2 port map( A => n230, B => n206, Y => n208);
U275 : CLKINVX1 port map( A => n207, Y => n226);
U276 : CLKNAND2X2 port map( A => B(9), B => n230, Y => n207);
U277 : XOR2X1 port map( A => B(8), B => B(7), Y => n230);
U278 : NAND3XL port map( A => B(7), B => n206, C => B(8), Y => n213_port);
U279 : CLKINVX1 port map( A => B(9), Y => n206);
U280 : NAND3XL port map( A => n231, B => n232, C => B(9), Y => n212_port);
U281 : CLKINVX1 port map( A => B(8), Y => n232);
U282 : OAI221X1 port map( A0 => n146, A1 => n233, B0 => n147, B1 => n234, C0
=> n235, Y => decoded_3_9_port);
U283 : AOI22XL port map( A0 => n236, A1 => n149, B0 => n237, B1 => A(3), Y
=> n235);
U284 : OAI221X1 port map( A0 => n156, A1 => n233, B0 => n157, B1 => n234, C0
=> n238, Y => decoded_3_8_port);
U285 : AOI22XL port map( A0 => n236, A1 => n159, B0 => n237, B1 => A(2), Y
=> n238);
U286 : CLKINVX1 port map( A => n239, Y => n237);
U287 : CLKINVX1 port map( A => n240, Y => n236);
U288 : OAI221X1 port map( A0 => n156, A1 => n240, B0 => n157, B1 => n239, C0
=> n241, Y => decoded_3_7_port);
U289 : OAI21X1 port map( A0 => n242, A1 => n243, B0 => A(0), Y => n241);
U290 : AOI21X1 port map( A0 => n239, A1 => n240, B0 => n173, Y =>
decoded_3_6_port);
U291 : AOI21X1 port map( A0 => n240, A1 => n233, B0 => n9, Y =>
decoded_3_31_port);
U292 : OAI222X1 port map( A0 => n18, A1 => n233, B0 => n9, B1 => n240, C0 =>
n17, C1 => n234, Y => decoded_3_22_port);
U293 : CLKINVX1 port map( A => n242, Y => n233);
U294 : OAI221X1 port map( A0 => n18, A1 => n240, B0 => n17, B1 => n239, C0
=> n244, Y => decoded_3_21_port);
U295 : AOI22XL port map( A0 => n242, A1 => n28, B0 => n243, B1 => A(14), Y
=> n244);
U296 : OAI221X1 port map( A0 => n33, A1 => n240, B0 => n32, B1 => n239, C0
=> n245, Y => decoded_3_20_port);
U297 : AOI22XL port map( A0 => n242, A1 => n35, B0 => n243, B1 => A(13), Y
=> n245);
U298 : OAI221X1 port map( A0 => n44, A1 => n240, B0 => n43, B1 => n239, C0
=> n246, Y => decoded_3_19_port);
U299 : AOI22XL port map( A0 => n242, A1 => n46, B0 => n243, B1 => A(12), Y
=> n246);
U300 : OAI221X1 port map( A0 => n56, A1 => n240, B0 => n55, B1 => n239, C0
=> n247, Y => decoded_3_18_port);
U301 : AOI22XL port map( A0 => n242, A1 => n58, B0 => n243, B1 => A(11), Y
=> n247);
U302 : OAI221X1 port map( A0 => n66, A1 => n240, B0 => n65, B1 => n239, C0
=> n248, Y => decoded_3_17_port);
U303 : AOI22XL port map( A0 => n242, A1 => n68, B0 => n243, B1 => A(10), Y
=> n248);
U304 : OAI221X1 port map( A0 => n76, A1 => n240, B0 => n75, B1 => n239, C0
=> n249, Y => decoded_3_16_port);
U305 : AOI22XL port map( A0 => n242, A1 => n78, B0 => n243, B1 => A(9), Y =>
n249);
U306 : OAI221X1 port map( A0 => n86, A1 => n240, B0 => n85, B1 => n239, C0
=> n250, Y => decoded_3_15_port);
U307 : AOI22XL port map( A0 => n242, A1 => n88, B0 => n243, B1 => A(8), Y =>
n250);
U308 : OAI221X1 port map( A0 => n96, A1 => n240, B0 => n95, B1 => n239, C0
=> n251, Y => decoded_3_14_port);
U309 : AOI22XL port map( A0 => n242, A1 => n98, B0 => n243, B1 => A(7), Y =>
n251);
U310 : OAI221X1 port map( A0 => n106, A1 => n240, B0 => n105, B1 => n239, C0
=> n252, Y => decoded_3_13_port);
U311 : AOI22XL port map( A0 => n242, A1 => n108, B0 => n243, B1 => A(6), Y
=> n252);
U312 : OAI221X1 port map( A0 => n116, A1 => n240, B0 => n115, B1 => n239, C0
=> n253, Y => decoded_3_12_port);
U313 : AOI22XL port map( A0 => n242, A1 => n118, B0 => n243, B1 => A(5), Y
=> n253);
U314 : OAI221X1 port map( A0 => n126, A1 => n240, B0 => n125, B1 => n239, C0
=> n254, Y => decoded_3_11_port);
U315 : AOI22XL port map( A0 => n242, A1 => n128, B0 => n243, B1 => A(4), Y
=> n254);
U316 : OAI221X1 port map( A0 => n161, A1 => n240, B0 => n160, B1 => n239, C0
=> n255, Y => decoded_3_10_port);
U317 : AOI22XL port map( A0 => n242, A1 => n149, B0 => n243, B1 => A(3), Y
=> n255);
U318 : CLKINVX1 port map( A => n234, Y => n243);
U319 : NAND3XL port map( A => B(6), B => n231, C => B(5), Y => n234);
U320 : NOR3X1 port map( A => B(5), B => B(6), C => n231, Y => n242);
U321 : CLKNAND2X2 port map( A => n256, B => n231, Y => n239);
U322 : CLKINVX1 port map( A => B(7), Y => n231);
U323 : CLKNAND2X2 port map( A => B(7), B => n256, Y => n240);
U324 : XOR2X1 port map( A => B(6), B => B(5), Y => n256);
U325 : OAI221X1 port map( A0 => n126, A1 => n257, B0 => n125, B1 => n258, C0
=> n259, Y => decoded_2_9_port);
U326 : AOI22XL port map( A0 => n260, A1 => n128, B0 => n261, B1 => A(4), Y
=> n259);
U327 : OAI221X1 port map( A0 => n161, A1 => n257, B0 => n160, B1 => n258, C0
=> n262, Y => decoded_2_8_port);
U328 : AOI22XL port map( A0 => n260, A1 => n149, B0 => n261, B1 => A(3), Y
=> n262);
U329 : OAI221X1 port map( A0 => n146, A1 => n263, B0 => n147, B1 => n264, C0
=> n265, Y => decoded_2_7_port);
U330 : AOI22XL port map( A0 => n266, A1 => n149, B0 => n267, B1 => A(3), Y
=> n265);
U331 : OAI221X1 port map( A0 => n156, A1 => n263, B0 => n157, B1 => n264, C0
=> n268, Y => decoded_2_6_port);
U332 : AOI22XL port map( A0 => n266, A1 => n159, B0 => n267, B1 => A(2), Y
=> n268);
U333 : CLKINVX1 port map( A => n258, Y => n267);
U334 : CLKINVX1 port map( A => n257, Y => n266);
U335 : OAI221X1 port map( A0 => n156, A1 => n257, B0 => n157, B1 => n258, C0
=> n269, Y => decoded_2_5_port);
U336 : OAI21X1 port map( A0 => n260, A1 => n261, B0 => A(0), Y => n269);
U337 : AOI21X1 port map( A0 => n258, A1 => n257, B0 => n173, Y =>
decoded_2_4_port);
U338 : AOI21X1 port map( A0 => n257, A1 => n263, B0 => n9, Y =>
decoded_2_31_port);
U339 : OAI222X1 port map( A0 => n18, A1 => n263, B0 => n9, B1 => n257, C0 =>
n17, C1 => n264, Y => decoded_2_20_port);
U340 : OAI221X1 port map( A0 => n18, A1 => n257, B0 => n17, B1 => n258, C0
=> n270, Y => decoded_2_19_port);
U341 : AOI22XL port map( A0 => n260, A1 => n28, B0 => n261, B1 => A(14), Y
=> n270);
U342 : OAI221X1 port map( A0 => n33, A1 => n257, B0 => n32, B1 => n258, C0
=> n271, Y => decoded_2_18_port);
U343 : AOI22XL port map( A0 => n260, A1 => n35, B0 => n261, B1 => A(13), Y
=> n271);
U344 : OAI221X1 port map( A0 => n44, A1 => n257, B0 => n43, B1 => n258, C0
=> n272, Y => decoded_2_17_port);
U345 : AOI22XL port map( A0 => n260, A1 => n46, B0 => n261, B1 => A(12), Y
=> n272);
U346 : OAI221X1 port map( A0 => n56, A1 => n257, B0 => n55, B1 => n258, C0
=> n273, Y => decoded_2_16_port);
U347 : AOI22XL port map( A0 => n260, A1 => n58, B0 => n261, B1 => A(11), Y
=> n273);
U348 : OAI221X1 port map( A0 => n66, A1 => n257, B0 => n65, B1 => n258, C0
=> n274, Y => decoded_2_15_port);
U349 : AOI22XL port map( A0 => n260, A1 => n68, B0 => n261, B1 => A(10), Y
=> n274);
U350 : OAI221X1 port map( A0 => n76, A1 => n257, B0 => n75, B1 => n258, C0
=> n275, Y => decoded_2_14_port);
U351 : AOI22XL port map( A0 => n260, A1 => n78, B0 => n261, B1 => A(9), Y =>
n275);
U352 : OAI221X1 port map( A0 => n86, A1 => n257, B0 => n85, B1 => n258, C0
=> n276, Y => decoded_2_13_port);
U353 : AOI22XL port map( A0 => n260, A1 => n88, B0 => n261, B1 => A(8), Y =>
n276);
U354 : OAI221X1 port map( A0 => n96, A1 => n257, B0 => n95, B1 => n258, C0
=> n277, Y => decoded_2_12_port);
U355 : AOI22XL port map( A0 => n260, A1 => n98, B0 => n261, B1 => A(7), Y =>
n277);
U356 : OAI221X1 port map( A0 => n106, A1 => n257, B0 => n105, B1 => n258, C0
=> n278, Y => decoded_2_11_port);
U357 : AOI22XL port map( A0 => n260, A1 => n108, B0 => n261, B1 => A(6), Y
=> n278);
U358 : OAI221X1 port map( A0 => n116, A1 => n257, B0 => n115, B1 => n258, C0
=> n279, Y => decoded_2_10_port);
U359 : AOI22XL port map( A0 => n260, A1 => n118, B0 => n261, B1 => A(5), Y
=> n279);
U360 : CLKINVX1 port map( A => n264, Y => n261);
U361 : NAND3XL port map( A => B(4), B => n280, C => B(3), Y => n264);
U362 : CLKINVX1 port map( A => n263, Y => n260);
U363 : NAND3XL port map( A => n281, B => n1, C => B(5), Y => n263);
U364 : CLKNAND2X2 port map( A => n282, B => n280, Y => n258);
U365 : CLKINVX1 port map( A => B(5), Y => n280);
U366 : CLKNAND2X2 port map( A => B(5), B => n282, Y => n257);
U367 : OAI221X1 port map( A0 => n106, A1 => n283, B0 => n105, B1 => n284, C0
=> n285, Y => decoded_1_9_port);
U368 : AOI22XL port map( A0 => n286, A1 => n108, B0 => n287, B1 => A(6), Y
=> n285);
U369 : OAI221X1 port map( A0 => n116, A1 => n283, B0 => n115, B1 => n284, C0
=> n288, Y => decoded_1_8_port);
U370 : AOI22XL port map( A0 => n286, A1 => n118, B0 => n287, B1 => A(5), Y
=> n288);
U371 : OAI221X1 port map( A0 => n126, A1 => n283, B0 => n125, B1 => n284, C0
=> n289, Y => decoded_1_7_port);
U372 : AOI22XL port map( A0 => n286, A1 => n128, B0 => n287, B1 => A(4), Y
=> n289);
U373 : OAI221X1 port map( A0 => n161, A1 => n283, B0 => n160, B1 => n284, C0
=> n290, Y => decoded_1_6_port);
U374 : AOI22XL port map( A0 => n286, A1 => n149, B0 => n287, B1 => A(3), Y
=> n290);
U375 : OAI221X1 port map( A0 => n146, A1 => n291, B0 => n147, B1 => n292, C0
=> n293, Y => decoded_1_5_port);
U376 : AOI22XL port map( A0 => n294, A1 => n149, B0 => n295, B1 => A(3), Y
=> n293);
U377 : OAI221X1 port map( A0 => n156, A1 => n291, B0 => n157, B1 => n292, C0
=> n296, Y => decoded_1_4_port);
U378 : AOI22XL port map( A0 => n294, A1 => n159, B0 => n295, B1 => A(2), Y
=> n296);
U379 : CLKINVX1 port map( A => n284, Y => n295);
U380 : CLKINVX1 port map( A => n283, Y => n294);
U381 : OAI21X1 port map( A0 => n286, A1 => n287, B0 => A(0), Y => n297);
U382 : AOI21X1 port map( A0 => n284, A1 => n283, B0 => n173, Y =>
decoded_1_2_port);
U383 : AOI21X1 port map( A0 => n283, A1 => n291, B0 => n9, Y =>
decoded_1_31_port);
U384 : OAI222X1 port map( A0 => n18, A1 => n291, B0 => n9, B1 => n283, C0 =>
n17, C1 => n292, Y => decoded_1_18_port);
U385 : OAI221X1 port map( A0 => n18, A1 => n283, B0 => n17, B1 => n284, C0
=> n298, Y => decoded_1_17_port);
U386 : AOI22XL port map( A0 => n286, A1 => n28, B0 => n287, B1 => A(14), Y
=> n298);
U387 : OAI221X1 port map( A0 => n33, A1 => n283, B0 => n32, B1 => n284, C0
=> n299, Y => decoded_1_16_port);
U388 : AOI22XL port map( A0 => n286, A1 => n35, B0 => n287, B1 => A(13), Y
=> n299);
U389 : OAI221X1 port map( A0 => n44, A1 => n283, B0 => n43, B1 => n284, C0
=> n300, Y => decoded_1_15_port);
U390 : AOI22XL port map( A0 => n286, A1 => n46, B0 => n287, B1 => A(12), Y
=> n300);
U391 : OAI221X1 port map( A0 => n56, A1 => n283, B0 => n55, B1 => n284, C0
=> n301, Y => decoded_1_14_port);
U392 : AOI22XL port map( A0 => n286, A1 => n58, B0 => n287, B1 => A(11), Y
=> n301);
U393 : OAI221X1 port map( A0 => n66, A1 => n283, B0 => n65, B1 => n284, C0
=> n302, Y => decoded_1_13_port);
U394 : AOI22XL port map( A0 => n286, A1 => n68, B0 => n287, B1 => A(10), Y
=> n302);
U395 : OAI221X1 port map( A0 => n76, A1 => n283, B0 => n75, B1 => n284, C0
=> n303, Y => decoded_1_12_port);
U396 : AOI22XL port map( A0 => n286, A1 => n78, B0 => n287, B1 => A(9), Y =>
n303);
U397 : OAI221X1 port map( A0 => n86, A1 => n283, B0 => n85, B1 => n284, C0
=> n304, Y => decoded_1_11_port);
U398 : AOI22XL port map( A0 => n286, A1 => n88, B0 => n287, B1 => A(8), Y =>
n304);
U399 : OAI221X1 port map( A0 => n96, A1 => n283, B0 => n95, B1 => n284, C0
=> n305, Y => decoded_1_10_port);
U400 : AOI22XL port map( A0 => n286, A1 => n98, B0 => n287, B1 => A(7), Y =>
n305);
U401 : CLKINVX1 port map( A => n292, Y => n287);
U402 : NAND3XL port map( A => B(2), B => n281, C => B(1), Y => n292);
U403 : CLKINVX1 port map( A => n291, Y => n286);
U404 : NAND3XL port map( A => n306, B => n307, C => B(3), Y => n291);
U405 : CLKNAND2X2 port map( A => n308, B => n281, Y => n284);
U406 : AOI21X1 port map( A0 => n309, A1 => n310, B0 => n9, Y =>
decoded_0_31_port);
U407 : OAI22X1 port map( A0 => n9, A1 => n310, B0 => n18, B1 => n309, Y =>
N225);
U408 : AND2X1 port map( A => n311, B => n17, Y => n9);
U409 : OAI222X1 port map( A0 => n33, A1 => n309, B0 => n18, B1 => n310, C0
=> n17, C1 => n312, Y => N224);
U410 : CLKINVX1 port map( A => A(15), Y => n17);
U411 : XOR2X1 port map( A => A(15), B => n311, Y => n18);
U412 : NOR3X1 port map( A => A(13), B => A(14), C => n313, Y => n311);
U413 : OAI222X1 port map( A0 => n44, A1 => n309, B0 => n33, B1 => n310, C0
=> n32, C1 => n312, Y => N223);
U414 : CLKINVX1 port map( A => n28, Y => n33);
U415 : XOR2X1 port map( A => n32, B => n314, Y => n28);
U416 : NOR2X1 port map( A => A(13), B => n313, Y => n314);
U417 : CLKINVX1 port map( A => A(14), Y => n32);
U418 : OAI222X1 port map( A0 => n56, A1 => n309, B0 => n44, B1 => n310, C0
=> n43, C1 => n312, Y => N222);
U419 : CLKINVX1 port map( A => A(13), Y => n43);
U420 : CLKINVX1 port map( A => n35, Y => n44);
U421 : XOR2X1 port map( A => n313, B => A(13), Y => n35);
U422 : NAND3XL port map( A => n65, B => n55, C => n315, Y => n313);
U423 : OAI222X1 port map( A0 => n66, A1 => n309, B0 => n56, B1 => n310, C0
=> n55, C1 => n312, Y => N221);
U424 : CLKINVX1 port map( A => A(12), Y => n55);
U425 : CLKINVX1 port map( A => n46, Y => n56);
U426 : XOR2X1 port map( A => n316, B => A(12), Y => n46);
U427 : CLKNAND2X2 port map( A => n315, B => n65, Y => n316);
U428 : CLKINVX1 port map( A => n58, Y => n66);
U429 : XOR2X1 port map( A => n65, B => n315, Y => n58);
U430 : NOR3X1 port map( A => A(10), B => A(9), C => n317, Y => n315);
U431 : CLKINVX1 port map( A => A(11), Y => n65);
U432 : OAI222X1 port map( A0 => n86, A1 => n309, B0 => n76, B1 => n310, C0
=> n75, C1 => n312, Y => N219);
U433 : CLKINVX1 port map( A => n68, Y => n76);
U434 : XOR2X1 port map( A => n75, B => n318, Y => n68);
U435 : NOR2X1 port map( A => A(9), B => n317, Y => n318);
U436 : CLKINVX1 port map( A => A(10), Y => n75);
U437 : OAI222X1 port map( A0 => n96, A1 => n309, B0 => n86, B1 => n310, C0
=> n85, C1 => n312, Y => N218);
U438 : CLKINVX1 port map( A => A(9), Y => n85);
U455 : CLKINVX1 port map( A => n78, Y => n86);
U456 : XOR2X1 port map( A => n317, B => A(9), Y => n78);
U457 : NAND3XL port map( A => n105, B => n95, C => n319, Y => n317);
U458 : OAI222X1 port map( A0 => n106, A1 => n309, B0 => n96, B1 => n310, C0
=> n95, C1 => n312, Y => N217);
U459 : CLKINVX1 port map( A => A(8), Y => n95);
U460 : CLKINVX1 port map( A => n88, Y => n96);
U461 : XOR2X1 port map( A => n320, B => A(8), Y => n88);
U462 : CLKNAND2X2 port map( A => n319, B => n105, Y => n320);
U463 : OAI222X1 port map( A0 => n116, A1 => n309, B0 => n106, B1 => n310, C0
=> n105, C1 => n312, Y => N216);
U464 : CLKINVX1 port map( A => n98, Y => n106);
U465 : XOR2X1 port map( A => n105, B => n319, Y => n98);
U466 : NOR3X1 port map( A => A(5), B => A(6), C => n321, Y => n319);
U467 : CLKINVX1 port map( A => A(7), Y => n105);
U468 : OAI222X1 port map( A0 => n126, A1 => n309, B0 => n116, B1 => n310, C0
=> n115, C1 => n312, Y => N215);
U469 : CLKINVX1 port map( A => n108, Y => n116);
U470 : XOR2X1 port map( A => n115, B => n322, Y => n108);
U471 : NOR2X1 port map( A => A(5), B => n321, Y => n322);
U472 : CLKINVX1 port map( A => A(6), Y => n115);
U473 : OAI222X1 port map( A0 => n161, A1 => n309, B0 => n126, B1 => n310, C0
=> n125, C1 => n312, Y => N214);
U474 : CLKINVX1 port map( A => A(5), Y => n125);
U475 : CLKINVX1 port map( A => n118, Y => n126);
U476 : XOR2X1 port map( A => n321, B => A(5), Y => n118);
U477 : NAND3XL port map( A => n136, B => n160, C => n323, Y => n321);
U478 : OAI222X1 port map( A0 => n135, A1 => n309, B0 => n161, B1 => n310, C0
=> n160, C1 => n312, Y => N213);
U479 : CLKINVX1 port map( A => A(4), Y => n160);
U480 : CLKINVX1 port map( A => n128, Y => n161);
U511 : XOR2X1 port map( A => n324, B => A(4), Y => n128);
U512 : CLKNAND2X2 port map( A => n323, B => n136, Y => n324);
U513 : OAI222X1 port map( A0 => n146, A1 => n309, B0 => n135, B1 => n310, C0
=> n136, C1 => n312, Y => N212);
U514 : CLKINVX1 port map( A => n149, Y => n135);
U515 : XOR2X1 port map( A => n136, B => n323, Y => n149);
U516 : NOR3X1 port map( A => A(1), B => A(2), C => A(0), Y => n323);
U517 : CLKINVX1 port map( A => A(3), Y => n136);
U518 : CLKINVX1 port map( A => n159, Y => n146);
U519 : XOR2X1 port map( A => n147, B => n325, Y => n159);
U520 : NOR2X1 port map( A => A(0), B => A(1), Y => n325);
U521 : CLKINVX1 port map( A => A(2), Y => n147);
U522 : OAI222X1 port map( A0 => n173, A1 => n309, B0 => n156, B1 => n310, C0
=> n157, C1 => n312, Y => N210);
U523 : CLKINVX1 port map( A => n171, Y => n156);
U524 : XNOR2X1 port map( A => n157, B => A(0), Y => n171);
U525 : CLKINVX1 port map( A => A(1), Y => n157);
U526 : AOI21X1 port map( A0 => n310, A1 => n312, B0 => n173, Y => N209);
U527 : CLKINVX1 port map( A => A(0), Y => n173);
partial_products_5_0_port <= '0';
partial_products_5_1_port <= '0';
partial_products_5_2_port <= '0';
partial_products_5_3_port <= '0';
partial_products_5_4_port <= '0';
partial_products_5_5_port <= '0';
partial_products_5_6_port <= '0';
partial_products_5_7_port <= '0';
partial_products_5_8_port <= '0';
partial_products_5_9_port <= '0';
partial_products_5_10_port <= '0';
partial_products_5_11_port <= '0';
partial_products_4_0_port <= '0';
partial_products_3_0_port <= '0';
partial_products_4_1_port <= '0';
partial_products_3_1_port <= '0';
partial_products_4_2_port <= '0';
partial_products_3_2_port <= '0';
partial_products_4_3_port <= '0';
partial_products_3_3_port <= '0';
partial_products_4_4_port <= '0';
partial_products_4_5_port <= '0';
partial_products_4_6_port <= '0';
partial_products_4_7_port <= '0';
end SYN_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity ALU is
port( A, B : in std_logic_vector (31 downto 0); ALU_SEL : in
std_logic_vector (1 downto 0); COMPARATOR_CW : in std_logic_vector (5
downto 0); LOGIC_CW : in std_logic_vector (3 downto 0); SHIFTER_CW :
in std_logic_vector (2 downto 0); ADD_SUB : in std_logic; ALU_OUT :
out std_logic_vector (31 downto 0); ZERO, OVERFLOW : out std_logic);
end ALU;
architecture SYN_STRUCTURAL of ALU is
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI2BB1X1
port( A0N, A1N, B0 : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI32XL
port( A0, A1, A2, B0, B1 : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component XNOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component SHIFTER_GENERIC_N32
port( A : in std_logic_vector (31 downto 0); B : in std_logic_vector (4
downto 0); LOGIC_ARITH, LEFT_RIGHT, SHIFT_ROTATE : in std_logic;
OUTPUT : out std_logic_vector (31 downto 0));
end component;
component LOGIC_GENERIC_N32
port( A, B : in std_logic_vector (31 downto 0); S : in std_logic_vector
(3 downto 0); LOGIC_OUT : out std_logic_vector (31 downto 0));
end component;
component COMPARATOR_GENERIC_N32
port( SUB : in std_logic_vector (31 downto 0); CARRY, EQUAL, NOT_EQUAL,
GREATER, GREATER_EQUAL, LOWER, LOWER_EQUAL : in std_logic;
COMPARATOR_OUT : out std_logic_vector (31 downto 0); ZERO : out
std_logic);
end component;
component CARRY_SELECT_ADDER
port( A, B : in std_logic_vector (31 downto 0); S : out std_logic_vector
(31 downto 0); Ci : in std_logic; Co : out std_logic);
end component;
signal OVERFLOW_port, INTERNAL_B_31_port, INTERNAL_B_30_port,
INTERNAL_B_29_port, INTERNAL_B_28_port, INTERNAL_B_27_port,
INTERNAL_B_26_port, INTERNAL_B_25_port, INTERNAL_B_24_port,
INTERNAL_B_23_port, INTERNAL_B_22_port, INTERNAL_B_21_port,
INTERNAL_B_20_port, INTERNAL_B_19_port, INTERNAL_B_18_port,
INTERNAL_B_17_port, INTERNAL_B_16_port, INTERNAL_B_15_port,
INTERNAL_B_14_port, INTERNAL_B_13_port, INTERNAL_B_12_port,
INTERNAL_B_11_port, INTERNAL_B_10_port, INTERNAL_B_9_port,
INTERNAL_B_8_port, INTERNAL_B_7_port, INTERNAL_B_6_port,
INTERNAL_B_5_port, INTERNAL_B_4_port, INTERNAL_B_3_port,
INTERNAL_B_2_port, INTERNAL_B_1_port, INTERNAL_B_0_port,
ADDER_OUT_31_port, ADDER_OUT_30_port, ADDER_OUT_29_port,
ADDER_OUT_28_port, ADDER_OUT_27_port, ADDER_OUT_26_port,
ADDER_OUT_25_port, ADDER_OUT_24_port, ADDER_OUT_23_port,
ADDER_OUT_22_port, ADDER_OUT_21_port, ADDER_OUT_20_port,
ADDER_OUT_19_port, ADDER_OUT_18_port, ADDER_OUT_17_port,
ADDER_OUT_16_port, ADDER_OUT_15_port, ADDER_OUT_14_port,
ADDER_OUT_13_port, ADDER_OUT_12_port, ADDER_OUT_11_port,
ADDER_OUT_10_port, ADDER_OUT_9_port, ADDER_OUT_8_port, ADDER_OUT_7_port,
ADDER_OUT_6_port, ADDER_OUT_5_port, ADDER_OUT_4_port, ADDER_OUT_3_port,
ADDER_OUT_2_port, ADDER_OUT_1_port, ADDER_OUT_0_port, NOT_ADD_SUB,
COMPARATOR_OUT_0_port, LOGIC_OUT_31_port, LOGIC_OUT_30_port,
LOGIC_OUT_29_port, LOGIC_OUT_28_port, LOGIC_OUT_27_port,
LOGIC_OUT_26_port, LOGIC_OUT_25_port, LOGIC_OUT_24_port,
LOGIC_OUT_23_port, LOGIC_OUT_22_port, LOGIC_OUT_21_port,
LOGIC_OUT_20_port, LOGIC_OUT_19_port, LOGIC_OUT_18_port,
LOGIC_OUT_17_port, LOGIC_OUT_16_port, LOGIC_OUT_15_port,
LOGIC_OUT_14_port, LOGIC_OUT_13_port, LOGIC_OUT_12_port,
LOGIC_OUT_11_port, LOGIC_OUT_10_port, LOGIC_OUT_9_port, LOGIC_OUT_8_port,
LOGIC_OUT_7_port, LOGIC_OUT_6_port, LOGIC_OUT_5_port, LOGIC_OUT_4_port,
LOGIC_OUT_3_port, LOGIC_OUT_2_port, LOGIC_OUT_1_port, LOGIC_OUT_0_port,
SHIFTER_OUT_31_port, SHIFTER_OUT_30_port, SHIFTER_OUT_29_port,
SHIFTER_OUT_28_port, SHIFTER_OUT_27_port, SHIFTER_OUT_26_port,
SHIFTER_OUT_25_port, SHIFTER_OUT_24_port, SHIFTER_OUT_23_port,
SHIFTER_OUT_22_port, SHIFTER_OUT_21_port, SHIFTER_OUT_20_port,
SHIFTER_OUT_19_port, SHIFTER_OUT_18_port, SHIFTER_OUT_17_port,
SHIFTER_OUT_16_port, SHIFTER_OUT_15_port, SHIFTER_OUT_14_port,
SHIFTER_OUT_13_port, SHIFTER_OUT_12_port, SHIFTER_OUT_11_port,
SHIFTER_OUT_10_port, SHIFTER_OUT_9_port, SHIFTER_OUT_8_port,
SHIFTER_OUT_7_port, SHIFTER_OUT_6_port, SHIFTER_OUT_5_port,
SHIFTER_OUT_4_port, SHIFTER_OUT_3_port, SHIFTER_OUT_2_port,
SHIFTER_OUT_1_port, SHIFTER_OUT_0_port, n1, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
net93327, net93328, net93329, net93330, net93331, net93332, net93333,
net93334, net93335, net93336, net93337, net93338, net93339, net93340,
net93341, net93342, net93343, net93344, net93345, net93346, net93347,
net93348, net93349, net93350, net93351, net93352, net93353, net93354,
net93355, net93356, net93357 : std_logic;
begin
OVERFLOW <= OVERFLOW_port;
CARRY_SELECT_ADDER_I : CARRY_SELECT_ADDER port map( A(31) => A(31), A(30) =>
A(30), A(29) => A(29), A(28) => A(28), A(27) =>
A(27), A(26) => A(26), A(25) => A(25), A(24) =>
A(24), A(23) => A(23), A(22) => A(22), A(21) =>
A(21), A(20) => A(20), A(19) => A(19), A(18) =>
A(18), A(17) => A(17), A(16) => A(16), A(15) =>
A(15), A(14) => A(14), A(13) => A(13), A(12) =>
A(12), A(11) => A(11), A(10) => A(10), A(9) => A(9),
A(8) => A(8), A(7) => A(7), A(6) => A(6), A(5) =>
A(5), A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1)
=> A(1), A(0) => A(0), B(31) => INTERNAL_B_31_port,
B(30) => INTERNAL_B_30_port, B(29) =>
INTERNAL_B_29_port, B(28) => INTERNAL_B_28_port,
B(27) => INTERNAL_B_27_port, B(26) =>
INTERNAL_B_26_port, B(25) => INTERNAL_B_25_port,
B(24) => INTERNAL_B_24_port, B(23) =>
INTERNAL_B_23_port, B(22) => INTERNAL_B_22_port,
B(21) => INTERNAL_B_21_port, B(20) =>
INTERNAL_B_20_port, B(19) => INTERNAL_B_19_port,
B(18) => INTERNAL_B_18_port, B(17) =>
INTERNAL_B_17_port, B(16) => INTERNAL_B_16_port,
B(15) => INTERNAL_B_15_port, B(14) =>
INTERNAL_B_14_port, B(13) => INTERNAL_B_13_port,
B(12) => INTERNAL_B_12_port, B(11) =>
INTERNAL_B_11_port, B(10) => INTERNAL_B_10_port,
B(9) => INTERNAL_B_9_port, B(8) => INTERNAL_B_8_port
, B(7) => INTERNAL_B_7_port, B(6) =>
INTERNAL_B_6_port, B(5) => INTERNAL_B_5_port, B(4)
=> INTERNAL_B_4_port, B(3) => INTERNAL_B_3_port,
B(2) => INTERNAL_B_2_port, B(1) => INTERNAL_B_1_port
, B(0) => INTERNAL_B_0_port, S(31) =>
ADDER_OUT_31_port, S(30) => ADDER_OUT_30_port, S(29)
=> ADDER_OUT_29_port, S(28) => ADDER_OUT_28_port,
S(27) => ADDER_OUT_27_port, S(26) =>
ADDER_OUT_26_port, S(25) => ADDER_OUT_25_port, S(24)
=> ADDER_OUT_24_port, S(23) => ADDER_OUT_23_port,
S(22) => ADDER_OUT_22_port, S(21) =>
ADDER_OUT_21_port, S(20) => ADDER_OUT_20_port, S(19)
=> ADDER_OUT_19_port, S(18) => ADDER_OUT_18_port,
S(17) => ADDER_OUT_17_port, S(16) =>
ADDER_OUT_16_port, S(15) => ADDER_OUT_15_port, S(14)
=> ADDER_OUT_14_port, S(13) => ADDER_OUT_13_port,
S(12) => ADDER_OUT_12_port, S(11) =>
ADDER_OUT_11_port, S(10) => ADDER_OUT_10_port, S(9)
=> ADDER_OUT_9_port, S(8) => ADDER_OUT_8_port, S(7)
=> ADDER_OUT_7_port, S(6) => ADDER_OUT_6_port, S(5)
=> ADDER_OUT_5_port, S(4) => ADDER_OUT_4_port, S(3)
=> ADDER_OUT_3_port, S(2) => ADDER_OUT_2_port, S(1)
=> ADDER_OUT_1_port, S(0) => ADDER_OUT_0_port, Ci =>
NOT_ADD_SUB, Co => OVERFLOW_port);
COMPARATOR_GENERIC_I : COMPARATOR_GENERIC_N32 port map( SUB(31) =>
ADDER_OUT_31_port, SUB(30) => ADDER_OUT_30_port,
SUB(29) => ADDER_OUT_29_port, SUB(28) =>
ADDER_OUT_28_port, SUB(27) => ADDER_OUT_27_port,
SUB(26) => ADDER_OUT_26_port, SUB(25) =>
ADDER_OUT_25_port, SUB(24) => ADDER_OUT_24_port,
SUB(23) => ADDER_OUT_23_port, SUB(22) =>
ADDER_OUT_22_port, SUB(21) => ADDER_OUT_21_port,
SUB(20) => ADDER_OUT_20_port, SUB(19) =>
ADDER_OUT_19_port, SUB(18) => ADDER_OUT_18_port,
SUB(17) => ADDER_OUT_17_port, SUB(16) =>
ADDER_OUT_16_port, SUB(15) => ADDER_OUT_15_port,
SUB(14) => ADDER_OUT_14_port, SUB(13) =>
ADDER_OUT_13_port, SUB(12) => ADDER_OUT_12_port,
SUB(11) => ADDER_OUT_11_port, SUB(10) =>
ADDER_OUT_10_port, SUB(9) => ADDER_OUT_9_port,
SUB(8) => ADDER_OUT_8_port, SUB(7) =>
ADDER_OUT_7_port, SUB(6) => ADDER_OUT_6_port, SUB(5)
=> ADDER_OUT_5_port, SUB(4) => ADDER_OUT_4_port,
SUB(3) => ADDER_OUT_3_port, SUB(2) =>
ADDER_OUT_2_port, SUB(1) => ADDER_OUT_1_port, SUB(0)
=> ADDER_OUT_0_port, CARRY => OVERFLOW_port, EQUAL
=> COMPARATOR_CW(0), NOT_EQUAL => COMPARATOR_CW(1),
GREATER => COMPARATOR_CW(2), GREATER_EQUAL =>
COMPARATOR_CW(3), LOWER => COMPARATOR_CW(4),
LOWER_EQUAL => COMPARATOR_CW(5), COMPARATOR_OUT(31)
=> net93327, COMPARATOR_OUT(30) => net93328,
COMPARATOR_OUT(29) => net93329, COMPARATOR_OUT(28)
=> net93330, COMPARATOR_OUT(27) => net93331,
COMPARATOR_OUT(26) => net93332, COMPARATOR_OUT(25)
=> net93333, COMPARATOR_OUT(24) => net93334,
COMPARATOR_OUT(23) => net93335, COMPARATOR_OUT(22)
=> net93336, COMPARATOR_OUT(21) => net93337,
COMPARATOR_OUT(20) => net93338, COMPARATOR_OUT(19)
=> net93339, COMPARATOR_OUT(18) => net93340,
COMPARATOR_OUT(17) => net93341, COMPARATOR_OUT(16)
=> net93342, COMPARATOR_OUT(15) => net93343,
COMPARATOR_OUT(14) => net93344, COMPARATOR_OUT(13)
=> net93345, COMPARATOR_OUT(12) => net93346,
COMPARATOR_OUT(11) => net93347, COMPARATOR_OUT(10)
=> net93348, COMPARATOR_OUT(9) => net93349,
COMPARATOR_OUT(8) => net93350, COMPARATOR_OUT(7) =>
net93351, COMPARATOR_OUT(6) => net93352,
COMPARATOR_OUT(5) => net93353, COMPARATOR_OUT(4) =>
net93354, COMPARATOR_OUT(3) => net93355,
COMPARATOR_OUT(2) => net93356, COMPARATOR_OUT(1) =>
net93357, COMPARATOR_OUT(0) => COMPARATOR_OUT_0_port
, ZERO => ZERO);
LOGIC_GENERIC_I : LOGIC_GENERIC_N32 port map( A(31) => A(31), A(30) => A(30)
, A(29) => A(29), A(28) => A(28), A(27) => A(27),
A(26) => A(26), A(25) => A(25), A(24) => A(24),
A(23) => A(23), A(22) => A(22), A(21) => A(21),
A(20) => A(20), A(19) => A(19), A(18) => A(18),
A(17) => A(17), A(16) => A(16), A(15) => A(15),
A(14) => A(14), A(13) => A(13), A(12) => A(12),
A(11) => A(11), A(10) => A(10), A(9) => A(9), A(8)
=> A(8), A(7) => A(7), A(6) => A(6), A(5) => A(5),
A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1) =>
A(1), A(0) => A(0), B(31) => B(31), B(30) => B(30),
B(29) => B(29), B(28) => B(28), B(27) => B(27),
B(26) => B(26), B(25) => B(25), B(24) => B(24),
B(23) => B(23), B(22) => B(22), B(21) => B(21),
B(20) => B(20), B(19) => B(19), B(18) => B(18),
B(17) => B(17), B(16) => B(16), B(15) => B(15),
B(14) => B(14), B(13) => B(13), B(12) => B(12),
B(11) => B(11), B(10) => B(10), B(9) => B(9), B(8)
=> B(8), B(7) => B(7), B(6) => B(6), B(5) => B(5),
B(4) => B(4), B(3) => B(3), B(2) => B(2), B(1) =>
B(1), B(0) => B(0), S(3) => LOGIC_CW(3), S(2) =>
LOGIC_CW(2), S(1) => LOGIC_CW(1), S(0) =>
LOGIC_CW(0), LOGIC_OUT(31) => LOGIC_OUT_31_port,
LOGIC_OUT(30) => LOGIC_OUT_30_port, LOGIC_OUT(29) =>
LOGIC_OUT_29_port, LOGIC_OUT(28) =>
LOGIC_OUT_28_port, LOGIC_OUT(27) =>
LOGIC_OUT_27_port, LOGIC_OUT(26) =>
LOGIC_OUT_26_port, LOGIC_OUT(25) =>
LOGIC_OUT_25_port, LOGIC_OUT(24) =>
LOGIC_OUT_24_port, LOGIC_OUT(23) =>
LOGIC_OUT_23_port, LOGIC_OUT(22) =>
LOGIC_OUT_22_port, LOGIC_OUT(21) =>
LOGIC_OUT_21_port, LOGIC_OUT(20) =>
LOGIC_OUT_20_port, LOGIC_OUT(19) =>
LOGIC_OUT_19_port, LOGIC_OUT(18) =>
LOGIC_OUT_18_port, LOGIC_OUT(17) =>
LOGIC_OUT_17_port, LOGIC_OUT(16) =>
LOGIC_OUT_16_port, LOGIC_OUT(15) =>
LOGIC_OUT_15_port, LOGIC_OUT(14) =>
LOGIC_OUT_14_port, LOGIC_OUT(13) =>
LOGIC_OUT_13_port, LOGIC_OUT(12) =>
LOGIC_OUT_12_port, LOGIC_OUT(11) =>
LOGIC_OUT_11_port, LOGIC_OUT(10) =>
LOGIC_OUT_10_port, LOGIC_OUT(9) => LOGIC_OUT_9_port,
LOGIC_OUT(8) => LOGIC_OUT_8_port, LOGIC_OUT(7) =>
LOGIC_OUT_7_port, LOGIC_OUT(6) => LOGIC_OUT_6_port,
LOGIC_OUT(5) => LOGIC_OUT_5_port, LOGIC_OUT(4) =>
LOGIC_OUT_4_port, LOGIC_OUT(3) => LOGIC_OUT_3_port,
LOGIC_OUT(2) => LOGIC_OUT_2_port, LOGIC_OUT(1) =>
LOGIC_OUT_1_port, LOGIC_OUT(0) => LOGIC_OUT_0_port);
SHIFTER_GENERIC_I : SHIFTER_GENERIC_N32 port map( A(31) => A(31), A(30) =>
A(30), A(29) => A(29), A(28) => A(28), A(27) =>
A(27), A(26) => A(26), A(25) => A(25), A(24) =>
A(24), A(23) => A(23), A(22) => A(22), A(21) =>
A(21), A(20) => A(20), A(19) => A(19), A(18) =>
A(18), A(17) => A(17), A(16) => A(16), A(15) =>
A(15), A(14) => A(14), A(13) => A(13), A(12) =>
A(12), A(11) => A(11), A(10) => A(10), A(9) => A(9),
A(8) => A(8), A(7) => A(7), A(6) => A(6), A(5) =>
A(5), A(4) => A(4), A(3) => A(3), A(2) => A(2), A(1)
=> A(1), A(0) => A(0), B(4) => B(4), B(3) => B(3),
B(2) => B(2), B(1) => B(1), B(0) => B(0),
LOGIC_ARITH => SHIFTER_CW(0), LEFT_RIGHT =>
SHIFTER_CW(1), SHIFT_ROTATE => SHIFTER_CW(2),
OUTPUT(31) => SHIFTER_OUT_31_port, OUTPUT(30) =>
SHIFTER_OUT_30_port, OUTPUT(29) =>
SHIFTER_OUT_29_port, OUTPUT(28) =>
SHIFTER_OUT_28_port, OUTPUT(27) =>
SHIFTER_OUT_27_port, OUTPUT(26) =>
SHIFTER_OUT_26_port, OUTPUT(25) =>
SHIFTER_OUT_25_port, OUTPUT(24) =>
SHIFTER_OUT_24_port, OUTPUT(23) =>
SHIFTER_OUT_23_port, OUTPUT(22) =>
SHIFTER_OUT_22_port, OUTPUT(21) =>
SHIFTER_OUT_21_port, OUTPUT(20) =>
SHIFTER_OUT_20_port, OUTPUT(19) =>
SHIFTER_OUT_19_port, OUTPUT(18) =>
SHIFTER_OUT_18_port, OUTPUT(17) =>
SHIFTER_OUT_17_port, OUTPUT(16) =>
SHIFTER_OUT_16_port, OUTPUT(15) =>
SHIFTER_OUT_15_port, OUTPUT(14) =>
SHIFTER_OUT_14_port, OUTPUT(13) =>
SHIFTER_OUT_13_port, OUTPUT(12) =>
SHIFTER_OUT_12_port, OUTPUT(11) =>
SHIFTER_OUT_11_port, OUTPUT(10) =>
SHIFTER_OUT_10_port, OUTPUT(9) => SHIFTER_OUT_9_port
, OUTPUT(8) => SHIFTER_OUT_8_port, OUTPUT(7) =>
SHIFTER_OUT_7_port, OUTPUT(6) => SHIFTER_OUT_6_port,
OUTPUT(5) => SHIFTER_OUT_5_port, OUTPUT(4) =>
SHIFTER_OUT_4_port, OUTPUT(3) => SHIFTER_OUT_3_port,
OUTPUT(2) => SHIFTER_OUT_2_port, OUTPUT(1) =>
SHIFTER_OUT_1_port, OUTPUT(0) => SHIFTER_OUT_0_port)
;
U3 : INVXL port map( A => ADD_SUB, Y => NOT_ADD_SUB);
U4 : XNOR2XL port map( A => ADD_SUB, B => B(4), Y => INTERNAL_B_4_port);
U5 : XNOR2XL port map( A => ADD_SUB, B => B(31), Y => INTERNAL_B_31_port);
U6 : XNOR2XL port map( A => ADD_SUB, B => B(27), Y => INTERNAL_B_27_port);
U7 : XNOR2XL port map( A => ADD_SUB, B => B(30), Y => INTERNAL_B_30_port);
U8 : XNOR2XL port map( A => ADD_SUB, B => B(23), Y => INTERNAL_B_23_port);
U9 : XNOR2XL port map( A => ADD_SUB, B => B(19), Y => INTERNAL_B_19_port);
U10 : XNOR2XL port map( A => ADD_SUB, B => B(26), Y => INTERNAL_B_26_port);
U11 : XNOR2XL port map( A => ADD_SUB, B => B(22), Y => INTERNAL_B_22_port);
U12 : XNOR2XL port map( A => ADD_SUB, B => B(29), Y => INTERNAL_B_29_port);
U13 : XNOR2XL port map( A => ADD_SUB, B => B(21), Y => INTERNAL_B_21_port);
U14 : XNOR2XL port map( A => ADD_SUB, B => B(20), Y => INTERNAL_B_20_port);
U15 : XNOR2XL port map( A => ADD_SUB, B => B(15), Y => INTERNAL_B_15_port);
U16 : XNOR2XL port map( A => ADD_SUB, B => B(18), Y => INTERNAL_B_18_port);
U17 : XNOR2XL port map( A => ADD_SUB, B => B(25), Y => INTERNAL_B_25_port);
U18 : XNOR2XL port map( A => ADD_SUB, B => B(11), Y => INTERNAL_B_11_port);
U19 : XNOR2XL port map( A => ADD_SUB, B => B(28), Y => INTERNAL_B_28_port);
U20 : XNOR2XL port map( A => ADD_SUB, B => B(7), Y => INTERNAL_B_7_port);
U21 : XNOR2XL port map( A => ADD_SUB, B => B(14), Y => INTERNAL_B_14_port);
U22 : XNOR2XL port map( A => ADD_SUB, B => B(17), Y => INTERNAL_B_17_port);
U23 : XNOR2XL port map( A => ADD_SUB, B => B(24), Y => INTERNAL_B_24_port);
U24 : XNOR2XL port map( A => ADD_SUB, B => B(10), Y => INTERNAL_B_10_port);
U25 : XNOR2XL port map( A => ADD_SUB, B => B(6), Y => INTERNAL_B_6_port);
U26 : XNOR2XL port map( A => ADD_SUB, B => B(13), Y => INTERNAL_B_13_port);
U27 : XNOR2XL port map( A => ADD_SUB, B => B(16), Y => INTERNAL_B_16_port);
U28 : XNOR2XL port map( A => ADD_SUB, B => B(9), Y => INTERNAL_B_9_port);
U29 : XNOR2XL port map( A => ADD_SUB, B => B(5), Y => INTERNAL_B_5_port);
U30 : XNOR2XL port map( A => ADD_SUB, B => B(12), Y => INTERNAL_B_12_port);
U31 : XNOR2XL port map( A => ADD_SUB, B => B(8), Y => INTERNAL_B_8_port);
U32 : OAI2BB1X1 port map( A0N => ADDER_OUT_15_port, A1N => n1, B0 => n2, Y
=> ALU_OUT(15));
U33 : AOI22XL port map( A0 => LOGIC_OUT_15_port, A1 => n3, B0 =>
SHIFTER_OUT_15_port, B1 => n4, Y => n2);
U34 : OAI2BB1X1 port map( A0N => ADDER_OUT_14_port, A1N => n1, B0 => n5, Y
=> ALU_OUT(14));
U35 : AOI22XL port map( A0 => LOGIC_OUT_14_port, A1 => n3, B0 =>
SHIFTER_OUT_14_port, B1 => n4, Y => n5);
U36 : OAI2BB1X1 port map( A0N => ADDER_OUT_13_port, A1N => n1, B0 => n6, Y
=> ALU_OUT(13));
U37 : AOI22XL port map( A0 => LOGIC_OUT_13_port, A1 => n3, B0 =>
SHIFTER_OUT_13_port, B1 => n4, Y => n6);
U38 : OAI2BB1X1 port map( A0N => ADDER_OUT_12_port, A1N => n1, B0 => n7, Y
=> ALU_OUT(12));
U39 : AOI22XL port map( A0 => LOGIC_OUT_12_port, A1 => n3, B0 =>
SHIFTER_OUT_12_port, B1 => n4, Y => n7);
U40 : OAI2BB1X1 port map( A0N => ADDER_OUT_11_port, A1N => n1, B0 => n8, Y
=> ALU_OUT(11));
U41 : AOI22XL port map( A0 => LOGIC_OUT_11_port, A1 => n3, B0 =>
SHIFTER_OUT_11_port, B1 => n4, Y => n8);
U42 : OAI2BB1X1 port map( A0N => ADDER_OUT_10_port, A1N => n1, B0 => n9, Y
=> ALU_OUT(10));
U43 : AOI22XL port map( A0 => LOGIC_OUT_10_port, A1 => n3, B0 =>
SHIFTER_OUT_10_port, B1 => n4, Y => n9);
U44 : OAI2BB1X1 port map( A0N => ADDER_OUT_9_port, A1N => n1, B0 => n10, Y
=> ALU_OUT(9));
U45 : AOI22XL port map( A0 => LOGIC_OUT_9_port, A1 => n3, B0 =>
SHIFTER_OUT_9_port, B1 => n4, Y => n10);
U46 : OAI2BB1X1 port map( A0N => ADDER_OUT_8_port, A1N => n1, B0 => n11, Y
=> ALU_OUT(8));
U47 : AOI22XL port map( A0 => LOGIC_OUT_8_port, A1 => n3, B0 =>
SHIFTER_OUT_8_port, B1 => n4, Y => n11);
U48 : OAI2BB1X1 port map( A0N => ADDER_OUT_7_port, A1N => n1, B0 => n12, Y
=> ALU_OUT(7));
U49 : AOI22XL port map( A0 => LOGIC_OUT_7_port, A1 => n3, B0 =>
SHIFTER_OUT_7_port, B1 => n4, Y => n12);
U50 : OAI2BB1X1 port map( A0N => ADDER_OUT_6_port, A1N => n1, B0 => n13, Y
=> ALU_OUT(6));
U51 : AOI22XL port map( A0 => LOGIC_OUT_6_port, A1 => n3, B0 =>
SHIFTER_OUT_6_port, B1 => n4, Y => n13);
U52 : OAI2BB1X1 port map( A0N => ADDER_OUT_5_port, A1N => n1, B0 => n14, Y
=> ALU_OUT(5));
U53 : AOI22XL port map( A0 => LOGIC_OUT_5_port, A1 => n3, B0 =>
SHIFTER_OUT_5_port, B1 => n4, Y => n14);
U54 : OAI2BB1X1 port map( A0N => ADDER_OUT_4_port, A1N => n1, B0 => n15, Y
=> ALU_OUT(4));
U55 : AOI22XL port map( A0 => LOGIC_OUT_4_port, A1 => n3, B0 =>
SHIFTER_OUT_4_port, B1 => n4, Y => n15);
U56 : OAI2BB1X1 port map( A0N => ADDER_OUT_3_port, A1N => n1, B0 => n16, Y
=> ALU_OUT(3));
U57 : AOI22XL port map( A0 => LOGIC_OUT_3_port, A1 => n3, B0 =>
SHIFTER_OUT_3_port, B1 => n4, Y => n16);
U58 : OAI2BB1X1 port map( A0N => ADDER_OUT_2_port, A1N => n1, B0 => n17, Y
=> ALU_OUT(2));
U59 : AOI22XL port map( A0 => LOGIC_OUT_2_port, A1 => n3, B0 =>
SHIFTER_OUT_2_port, B1 => n4, Y => n17);
U60 : OAI2BB1X1 port map( A0N => ADDER_OUT_1_port, A1N => n1, B0 => n18, Y
=> ALU_OUT(1));
U61 : AOI22XL port map( A0 => LOGIC_OUT_1_port, A1 => n3, B0 =>
SHIFTER_OUT_1_port, B1 => n4, Y => n18);
U62 : CLKNAND2X2 port map( A => n19, B => n20, Y => ALU_OUT(0));
U63 : AOI32XL port map( A0 => ALU_SEL(0), A1 => n21, A2 =>
COMPARATOR_OUT_0_port, B0 => LOGIC_OUT_0_port, B1 =>
n3, Y => n20);
U64 : AOI22XL port map( A0 => SHIFTER_OUT_0_port, A1 => n4, B0 =>
ADDER_OUT_0_port, B1 => n1, Y => n19);
U65 : OAI2BB1X1 port map( A0N => ADDER_OUT_30_port, A1N => n1, B0 => n22, Y
=> ALU_OUT(30));
U66 : AOI22XL port map( A0 => LOGIC_OUT_30_port, A1 => n3, B0 =>
SHIFTER_OUT_30_port, B1 => n4, Y => n22);
U67 : OAI2BB1X1 port map( A0N => ADDER_OUT_29_port, A1N => n1, B0 => n23, Y
=> ALU_OUT(29));
U68 : AOI22XL port map( A0 => LOGIC_OUT_29_port, A1 => n3, B0 =>
SHIFTER_OUT_29_port, B1 => n4, Y => n23);
U69 : OAI2BB1X1 port map( A0N => ADDER_OUT_28_port, A1N => n1, B0 => n24, Y
=> ALU_OUT(28));
U70 : AOI22XL port map( A0 => LOGIC_OUT_28_port, A1 => n3, B0 =>
SHIFTER_OUT_28_port, B1 => n4, Y => n24);
U71 : OAI2BB1X1 port map( A0N => ADDER_OUT_27_port, A1N => n1, B0 => n25, Y
=> ALU_OUT(27));
U72 : AOI22XL port map( A0 => LOGIC_OUT_27_port, A1 => n3, B0 =>
SHIFTER_OUT_27_port, B1 => n4, Y => n25);
U73 : OAI2BB1X1 port map( A0N => ADDER_OUT_26_port, A1N => n1, B0 => n26, Y
=> ALU_OUT(26));
U74 : AOI22XL port map( A0 => LOGIC_OUT_26_port, A1 => n3, B0 =>
SHIFTER_OUT_26_port, B1 => n4, Y => n26);
U75 : OAI2BB1X1 port map( A0N => ADDER_OUT_25_port, A1N => n1, B0 => n27, Y
=> ALU_OUT(25));
U76 : AOI22XL port map( A0 => LOGIC_OUT_25_port, A1 => n3, B0 =>
SHIFTER_OUT_25_port, B1 => n4, Y => n27);
U77 : OAI2BB1X1 port map( A0N => ADDER_OUT_24_port, A1N => n1, B0 => n28, Y
=> ALU_OUT(24));
U78 : AOI22XL port map( A0 => LOGIC_OUT_24_port, A1 => n3, B0 =>
SHIFTER_OUT_24_port, B1 => n4, Y => n28);
U79 : OAI2BB1X1 port map( A0N => ADDER_OUT_23_port, A1N => n1, B0 => n29, Y
=> ALU_OUT(23));
U80 : AOI22XL port map( A0 => LOGIC_OUT_23_port, A1 => n3, B0 =>
SHIFTER_OUT_23_port, B1 => n4, Y => n29);
U81 : OAI2BB1X1 port map( A0N => ADDER_OUT_22_port, A1N => n1, B0 => n30, Y
=> ALU_OUT(22));
U82 : AOI22XL port map( A0 => LOGIC_OUT_22_port, A1 => n3, B0 =>
SHIFTER_OUT_22_port, B1 => n4, Y => n30);
U83 : OAI2BB1X1 port map( A0N => ADDER_OUT_21_port, A1N => n1, B0 => n31, Y
=> ALU_OUT(21));
U84 : AOI22XL port map( A0 => LOGIC_OUT_21_port, A1 => n3, B0 =>
SHIFTER_OUT_21_port, B1 => n4, Y => n31);
U85 : OAI2BB1X1 port map( A0N => ADDER_OUT_20_port, A1N => n1, B0 => n32, Y
=> ALU_OUT(20));
U86 : AOI22XL port map( A0 => LOGIC_OUT_20_port, A1 => n3, B0 =>
SHIFTER_OUT_20_port, B1 => n4, Y => n32);
U87 : OAI2BB1X1 port map( A0N => ADDER_OUT_19_port, A1N => n1, B0 => n33, Y
=> ALU_OUT(19));
U88 : AOI22XL port map( A0 => LOGIC_OUT_19_port, A1 => n3, B0 =>
SHIFTER_OUT_19_port, B1 => n4, Y => n33);
U89 : OAI2BB1X1 port map( A0N => ADDER_OUT_18_port, A1N => n1, B0 => n34, Y
=> ALU_OUT(18));
U90 : AOI22XL port map( A0 => LOGIC_OUT_18_port, A1 => n3, B0 =>
SHIFTER_OUT_18_port, B1 => n4, Y => n34);
U91 : OAI2BB1X1 port map( A0N => ADDER_OUT_17_port, A1N => n1, B0 => n35, Y
=> ALU_OUT(17));
U92 : AOI22XL port map( A0 => LOGIC_OUT_17_port, A1 => n3, B0 =>
SHIFTER_OUT_17_port, B1 => n4, Y => n35);
U93 : OAI2BB1X1 port map( A0N => ADDER_OUT_16_port, A1N => n1, B0 => n36, Y
=> ALU_OUT(16));
U94 : AOI22XL port map( A0 => LOGIC_OUT_16_port, A1 => n3, B0 =>
SHIFTER_OUT_16_port, B1 => n4, Y => n36);
U95 : XNOR2X1 port map( A => ADD_SUB, B => B(3), Y => INTERNAL_B_3_port);
U96 : XNOR2X1 port map( A => ADD_SUB, B => B(2), Y => INTERNAL_B_2_port);
U97 : XNOR2X1 port map( A => ADD_SUB, B => B(1), Y => INTERNAL_B_1_port);
U98 : XNOR2X1 port map( A => ADD_SUB, B => B(0), Y => INTERNAL_B_0_port);
U99 : OAI2BB1X1 port map( A0N => ADDER_OUT_31_port, A1N => n1, B0 => n37, Y
=> ALU_OUT(31));
U100 : AOI22XL port map( A0 => LOGIC_OUT_31_port, A1 => n3, B0 =>
SHIFTER_OUT_31_port, B1 => n4, Y => n37);
U101 : AND2X1 port map( A => ALU_SEL(0), B => ALU_SEL(1), Y => n4);
U102 : NOR2X1 port map( A => n21, B => ALU_SEL(0), Y => n3);
U103 : CLKINVX1 port map( A => ALU_SEL(1), Y => n21);
U104 : NOR2X1 port map( A => ALU_SEL(0), B => ALU_SEL(1), Y => n1);
end SYN_STRUCTURAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_DLX.all;
entity DLX is
port( CLOCK, RESET : in std_logic; PORT_PC : out std_logic_vector (31
downto 0); PORT_INSTR_IRAM : in std_logic_vector (31 downto 0);
PORT_REGB, PORT_ALU : out std_logic_vector (31 downto 0);
PORT_DATA_RAM : in std_logic_vector (31 downto 0); PORT_SIZE : out
std_logic_vector (1 downto 0); PORT_R_W, PORT_EN, RF_ENABLE, RF_RD1,
RF_RD2, RF_WR : out std_logic; RF_ADD_WR, RF_ADD_RD1, RF_ADD_RD2 :
out std_logic_vector (4 downto 0); RF_DATAIN : out std_logic_vector
(31 downto 0); RF_OUT1, RF_OUT2 : in std_logic_vector (31 downto 0));
end DLX;
architecture SYN_RTL of DLX is
component CLKINVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component CLKNAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component NAND3XL
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OAI211XL
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component AND4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component AND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI2BB1X1
port( A0N, A1N, B0 : in std_logic; Y : out std_logic);
end component;
component OR3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NOR3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI31X1
port( A0, A1, A2, B0 : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component OAI31X1
port( A0, A1, A2, B0 : in std_logic; Y : out std_logic);
end component;
component AOI33X1
port( A0, A1, A2, B0, B1, B2 : in std_logic; Y : out std_logic);
end component;
component AOI211X1
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component NAND3BX1
port( AN, B, C : in std_logic; Y : out std_logic);
end component;
component AO22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI221XL
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component OAI32XL
port( A0, A1, A2, B0, B1 : in std_logic; Y : out std_logic);
end component;
component MXI2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI32XL
port( A0, A1, A2, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI21BX1
port( A0, A1, B0N : in std_logic; Y : out std_logic);
end component;
component NOR4X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OAI2B11X1
port( A1N, A0, B0, C0 : in std_logic; Y : out std_logic);
end component;
component OAI2BB2X1
port( B0, B1, A0N, A1N : in std_logic; Y : out std_logic);
end component;
component NAND2BX1
port( AN, B : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI2B1X1
port( A1N, A0, B0 : in std_logic; Y : out std_logic);
end component;
component NOR3BX1
port( AN, B, C : in std_logic; Y : out std_logic);
end component;
component OA21X1
port( A0, A1, B0 : in std_logic; Y : out std_logic);
end component;
component NOR4BX1
port( AN, B, C, D : in std_logic; Y : out std_logic);
end component;
component AOI222XL
port( A0, A1, B0, B1, C0, C1 : in std_logic; Y : out std_logic);
end component;
component AOI21BX1
port( A0, A1, B0N : in std_logic; Y : out std_logic);
end component;
component OAI33X1
port( A0, A1, A2, B0, B1, B2 : in std_logic; Y : out std_logic);
end component;
component OAI2B2X1
port( A1N, A0, B0, B1 : in std_logic; Y : out std_logic);
end component;
component OAI22X1
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component AOI22XL
port( A0, A1, B0, B1 : in std_logic; Y : out std_logic);
end component;
component MX2X1
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component OAI221X1
port( A0, A1, B0, B1, C0 : in std_logic; Y : out std_logic);
end component;
component INVX8
port( A : in std_logic; Y : out std_logic);
end component;
component MX2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component MXI2XL
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component CLKAND2X2
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2BX2
port( AN, B : in std_logic; Y : out std_logic);
end component;
component NAND2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3BXL
port( AN, B, C : in std_logic; Y : out std_logic);
end component;
component NOR2XL
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI211XL
port( A0, A1, B0, C0 : in std_logic; Y : out std_logic);
end component;
component INVXL
port( A : in std_logic; Y : out std_logic);
end component;
component INVX6
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X5
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX5
port( A : in std_logic; Y : out std_logic);
end component;
component NOR4X8
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OAI31X4
port( A0, A1, A2, B0 : in std_logic; Y : out std_logic);
end component;
component NOR3X2
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND3X2
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component MXI2X2
port( A, B, S0 : in std_logic; Y : out std_logic);
end component;
component AOI2BB1XL
port( A0N, A1N, B0 : in std_logic; Y : out std_logic);
end component;
component NOR2BX4
port( AN, B : in std_logic; Y : out std_logic);
end component;
component TLATX1
port( G, D : in std_logic; Q, QN : out std_logic);
end component;
component DLX_DW01_add_1
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component DLX_DW01_add_0
port( A, B : in std_logic_vector (31 downto 0); CI : in std_logic; SUM
: out std_logic_vector (31 downto 0); CO : out std_logic);
end component;
component register_generic_N32_1
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_2
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_3
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_4
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_5
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_6
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_7
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_8
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_9
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_10
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_11
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_12
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_13
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_14
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component flip_flop
port( CK, RESET, ENABLE, D : in std_logic; Q : out std_logic);
end component;
component zero_N32
port( INPUT : in std_logic_vector (31 downto 0); ZERO : out std_logic);
end component;
component WB_SIGN_EXT_8
port( INPUT : in std_logic_vector (7 downto 0); OUTPUT : out
std_logic_vector (31 downto 0));
end component;
component WB_SIGN_EXT_16
port( INPUT : in std_logic_vector (15 downto 0); SIGN_EXT_CONTROL : in
std_logic; OUTPUT : out std_logic_vector (31 downto 0));
end component;
component ID_IMM16_SIGN_EXT
port( INPUT : in std_logic_vector (15 downto 0); OUTPUT : out
std_logic_vector (31 downto 0));
end component;
component ID_SIGN_EXT
port( INPUT : in std_logic_vector (15 downto 0); SIGN_EXT_CONTROL : in
std_logic; OUTPUT : out std_logic_vector (31 downto 0));
end component;
component register_generic_N32_0
port( CK, RESET, ENABLE : in std_logic; D : in std_logic_vector (31
downto 0); Q : out std_logic_vector (31 downto 0));
end component;
component BOOTH_N16
port( A, B : in std_logic_vector (15 downto 0); P : out std_logic_vector
(31 downto 0));
end component;
component ALU
port( A, B : in std_logic_vector (31 downto 0); ALU_SEL : in
std_logic_vector (1 downto 0); COMPARATOR_CW : in std_logic_vector
(5 downto 0); LOGIC_CW : in std_logic_vector (3 downto 0);
SHIFTER_CW : in std_logic_vector (2 downto 0); ADD_SUB : in
std_logic; ALU_OUT : out std_logic_vector (31 downto 0); ZERO,
OVERFLOW : out std_logic);
end component;
signal X_Logic1_port, X_Logic0_port, PORT_PC_31_port, PORT_PC_30_port,
PORT_PC_29_port, PORT_PC_28_port, PORT_PC_27_port, PORT_PC_26_port,
PORT_PC_25_port, PORT_PC_24_port, PORT_PC_23_port, PORT_PC_22_port,
PORT_PC_21_port, PORT_PC_20_port, PORT_PC_19_port, PORT_PC_18_port,
PORT_PC_17_port, PORT_PC_16_port, PORT_PC_15_port, PORT_PC_14_port,
PORT_PC_13_port, PORT_PC_12_port, PORT_PC_11_port, PORT_PC_10_port,
PORT_PC_9_port, PORT_PC_8_port, PORT_PC_7_port, PORT_PC_6_port,
PORT_PC_5_port, PORT_PC_4_port, PORT_PC_3_port, PORT_PC_2_port,
PORT_PC_1_port, PORT_PC_0_port, PORT_ALU_31_port, PORT_ALU_30_port,
PORT_ALU_29_port, PORT_ALU_28_port, PORT_ALU_27_port, PORT_ALU_26_port,
PORT_ALU_25_port, PORT_ALU_24_port, PORT_ALU_23_port, PORT_ALU_22_port,
PORT_ALU_21_port, PORT_ALU_20_port, PORT_ALU_19_port, PORT_ALU_18_port,
PORT_ALU_17_port, PORT_ALU_16_port, PORT_ALU_15_port, PORT_ALU_14_port,
PORT_ALU_13_port, PORT_ALU_12_port, PORT_ALU_11_port, PORT_ALU_10_port,
PORT_ALU_9_port, PORT_ALU_8_port, PORT_ALU_7_port, PORT_ALU_6_port,
PORT_ALU_5_port, PORT_ALU_4_port, PORT_ALU_3_port, PORT_ALU_2_port,
PORT_ALU_1_port, PORT_ALU_0_port, RF_WR_port, RF_ADD_WR_4_port,
RF_ADD_WR_3_port, RF_ADD_WR_2_port, RF_ADD_WR_1_port, RF_ADD_WR_0_port,
RF_ADD_RD1_4_port, RF_ADD_RD1_3_port, RF_ADD_RD1_2_port,
RF_ADD_RD1_1_port, RF_ADD_RD1_0_port, RF_ADD_RD2_4_port,
RF_ADD_RD2_3_port, RF_ADD_RD2_2_port, RF_ADD_RD2_1_port,
RF_ADD_RD2_0_port, EX_ALU_B_31_port, EX_ALU_SEL_1_port, EX_ALU_SEL_0_port
, EX_COMPARATOR_CW_5_port, EX_COMPARATOR_CW_4_port,
EX_COMPARATOR_CW_3_port, EX_COMPARATOR_CW_2_port, EX_COMPARATOR_CW_1_port
, EX_COMPARATOR_CW_0_port, EX_LOGIC_CW_3_port, EX_LOGIC_CW_2_port,
EX_SHIFTER_CW_1_port, EX_SHIFTER_CW_0_port, EX_ADD_SUB,
EX_ALU_OUT_31_port, EX_ALU_OUT_30_port, EX_ALU_OUT_29_port,
EX_ALU_OUT_28_port, EX_ALU_OUT_27_port, EX_ALU_OUT_26_port,
EX_ALU_OUT_25_port, EX_ALU_OUT_24_port, EX_ALU_OUT_23_port,
EX_ALU_OUT_22_port, EX_ALU_OUT_21_port, EX_ALU_OUT_20_port,
EX_ALU_OUT_19_port, EX_ALU_OUT_18_port, EX_ALU_OUT_17_port,
EX_ALU_OUT_16_port, EX_ALU_OUT_15_port, EX_ALU_OUT_14_port,
EX_ALU_OUT_13_port, EX_ALU_OUT_12_port, EX_ALU_OUT_11_port,
EX_ALU_OUT_10_port, EX_ALU_OUT_9_port, EX_ALU_OUT_8_port,
EX_ALU_OUT_7_port, EX_ALU_OUT_6_port, EX_ALU_OUT_5_port,
EX_ALU_OUT_4_port, EX_ALU_OUT_3_port, EX_ALU_OUT_2_port,
EX_ALU_OUT_1_port, EX_ALU_OUT_0_port, EX_MULT_OUT_31_port,
EX_MULT_OUT_30_port, EX_MULT_OUT_29_port, EX_MULT_OUT_28_port,
EX_MULT_OUT_27_port, EX_MULT_OUT_26_port, EX_MULT_OUT_25_port,
EX_MULT_OUT_24_port, EX_MULT_OUT_23_port, EX_MULT_OUT_22_port,
EX_MULT_OUT_21_port, EX_MULT_OUT_20_port, EX_MULT_OUT_19_port,
EX_MULT_OUT_18_port, EX_MULT_OUT_17_port, EX_MULT_OUT_16_port,
EX_MULT_OUT_15_port, EX_MULT_OUT_14_port, EX_MULT_OUT_13_port,
EX_MULT_OUT_12_port, EX_MULT_OUT_11_port, EX_MULT_OUT_10_port,
EX_MULT_OUT_9_port, EX_MULT_OUT_8_port, EX_MULT_OUT_7_port,
EX_MULT_OUT_6_port, EX_MULT_OUT_5_port, EX_MULT_OUT_4_port,
EX_MULT_OUT_3_port, EX_MULT_OUT_2_port, EX_MULT_OUT_1_port,
EX_MULT_OUT_0_port, ID_SIGN_EXT_CONTROL, ID_IMM16_EXT_31_port,
ID_IMM16_EXT_30_port, ID_IMM16_EXT_29_port, ID_IMM16_EXT_28_port,
ID_IMM16_EXT_27_port, ID_IMM16_EXT_26_port, ID_IMM16_EXT_25_port,
ID_IMM16_EXT_24_port, ID_IMM16_EXT_23_port, ID_IMM16_EXT_22_port,
ID_IMM16_EXT_21_port, ID_IMM16_EXT_20_port, ID_IMM16_EXT_19_port,
ID_IMM16_EXT_18_port, ID_IMM16_EXT_17_port, ID_IMM16_EXT_16_port,
ID_IMM16_EXT_15_port, ID_IMM16_EXT_14_port, ID_IMM16_EXT_13_port,
ID_IMM16_EXT_12_port, ID_IMM16_EXT_11_port, ID_IMM16_EXT_10_port,
ID_IMM16_EXT_9_port, ID_IMM16_EXT_8_port, ID_IMM16_EXT_7_port,
ID_IMM16_EXT_6_port, ID_IMM16_EXT_5_port, ID_IMM16_EXT_4_port,
ID_IMM16_EXT_3_port, ID_IMM16_EXT_2_port, ID_IMM16_EXT_1_port,
ID_IMM16_EXT_0_port, ID_IMM16_SHL2_31_port, ID_IMM16_SHL2_30_port,
ID_IMM16_SHL2_29_port, ID_IMM16_SHL2_28_port, ID_IMM16_SHL2_27_port,
ID_IMM16_SHL2_26_port, ID_IMM16_SHL2_25_port, ID_IMM16_SHL2_24_port,
ID_IMM16_SHL2_23_port, ID_IMM16_SHL2_22_port, ID_IMM16_SHL2_21_port,
ID_IMM16_SHL2_20_port, ID_IMM16_SHL2_19_port, ID_IMM16_SHL2_18_port,
ID_IMM16_SHL2_17_port, ID_IMM16_SHL2_16_port, ID_IMM16_SHL2_15_port,
ID_IMM16_SHL2_14_port, ID_IMM16_SHL2_13_port, ID_IMM16_SHL2_12_port,
ID_IMM16_SHL2_11_port, ID_IMM16_SHL2_10_port, ID_IMM16_SHL2_9_port,
ID_IMM16_SHL2_8_port, ID_IMM16_SHL2_7_port, ID_IMM16_SHL2_6_port,
ID_IMM16_SHL2_5_port, ID_IMM16_SHL2_4_port, ID_IMM16_SHL2_3_port,
ID_IMM16_SHL2_2_port, ID_IMM16_SHL2_1_port, ID_IMM16_SHL2_0_port,
WB_SIGN_EXT_16_CONTROL, WB_DATA_EXT_16_31_port, WB_DATA_EXT_16_30_port,
WB_DATA_EXT_16_29_port, WB_DATA_EXT_16_28_port, WB_DATA_EXT_16_27_port,
WB_DATA_EXT_16_26_port, WB_DATA_EXT_16_25_port, WB_DATA_EXT_16_24_port,
WB_DATA_EXT_16_23_port, WB_DATA_EXT_16_22_port, WB_DATA_EXT_16_21_port,
WB_DATA_EXT_16_20_port, WB_DATA_EXT_16_19_port, WB_DATA_EXT_16_18_port,
WB_DATA_EXT_16_17_port, WB_DATA_EXT_16_16_port, WB_DATA_EXT_16_15_port,
WB_DATA_EXT_16_14_port, WB_DATA_EXT_16_13_port, WB_DATA_EXT_16_12_port,
WB_DATA_EXT_16_11_port, WB_DATA_EXT_16_10_port, WB_DATA_EXT_16_9_port,
WB_DATA_EXT_16_8_port, WB_DATA_EXT_16_7_port, WB_DATA_EXT_16_6_port,
WB_DATA_EXT_16_5_port, WB_DATA_EXT_16_4_port, WB_DATA_EXT_16_3_port,
WB_DATA_EXT_16_2_port, WB_DATA_EXT_16_1_port, WB_DATA_EXT_16_0_port,
WB_DATA_EXT_8_9_port, WB_DATA_EXT_8_6_port, WB_DATA_EXT_8_5_port,
WB_DATA_EXT_8_4_port, WB_DATA_EXT_8_3_port, WB_DATA_EXT_8_2_port,
WB_DATA_EXT_8_1_port, WB_DATA_EXT_8_0_port, ID_REGA_ZERO, IF_NOT_RESET,
IF_STALL_SEL, IF_PC_INC_31_port, IF_PC_INC_30_port, IF_PC_INC_29_port,
IF_PC_INC_28_port, IF_PC_INC_27_port, IF_PC_INC_26_port,
IF_PC_INC_25_port, IF_PC_INC_24_port, IF_PC_INC_23_port,
IF_PC_INC_22_port, IF_PC_INC_21_port, IF_PC_INC_20_port,
IF_PC_INC_19_port, IF_PC_INC_18_port, IF_PC_INC_17_port,
IF_PC_INC_16_port, IF_PC_INC_15_port, IF_PC_INC_14_port,
IF_PC_INC_13_port, IF_PC_INC_12_port, IF_PC_INC_11_port,
IF_PC_INC_10_port, IF_PC_INC_9_port, IF_PC_INC_8_port, IF_PC_INC_7_port,
IF_PC_INC_6_port, IF_PC_INC_5_port, IF_PC_INC_4_port, IF_PC_INC_3_port,
IF_PC_INC_2_port, IF_PC_INC_1_port, IF_PC_INC_0_port, ID_INSTR_31,
ID_INSTR_30, ID_INSTR_29, ID_INSTR_28, ID_INSTR_27, ID_INSTR_26,
ID_INSTR_15_port, ID_INSTR_14_port, ID_INSTR_13_port, ID_INSTR_12_port,
ID_INSTR_11_port, ID_INSTR_10_port, ID_INSTR_9_port, ID_INSTR_8_port,
ID_INSTR_7_port, ID_INSTR_6_port, ID_INSTR_5_port, ID_INSTR_4_port,
ID_INSTR_3_port, ID_INSTR_2_port, ID_INSTR_1_port, ID_INSTR_0_port,
ID_PC_31_port, ID_PC_30_port, ID_PC_29_port, ID_PC_28_port, ID_PC_27_port
, ID_PC_26_port, ID_PC_25_port, ID_PC_24_port, ID_PC_23_port,
ID_PC_22_port, ID_PC_21_port, ID_PC_20_port, ID_PC_19_port, ID_PC_18_port
, ID_PC_17_port, ID_PC_16_port, ID_PC_15_port, ID_PC_14_port,
ID_PC_13_port, ID_PC_12_port, ID_PC_11_port, ID_PC_10_port, ID_PC_9_port,
ID_PC_8_port, ID_PC_7_port, ID_PC_6_port, ID_PC_5_port, ID_PC_4_port,
ID_PC_3_port, ID_PC_2_port, ID_PC_1_port, ID_PC_0_port, EX_REGA_31_port,
EX_REGA_30_port, EX_REGA_29_port, EX_REGA_28_port, EX_REGA_27_port,
EX_REGA_26_port, EX_REGA_25_port, EX_REGA_24_port, EX_REGA_23_port,
EX_REGA_22_port, EX_REGA_21_port, EX_REGA_20_port, EX_REGA_19_port,
EX_REGA_18_port, EX_REGA_17_port, EX_REGA_16_port, EX_REGA_15_port,
EX_REGA_14_port, EX_REGA_13_port, EX_REGA_12_port, EX_REGA_11_port,
EX_REGA_10_port, EX_REGA_9_port, EX_REGA_8_port, EX_REGA_7_port,
EX_REGA_6_port, EX_REGA_5_port, EX_REGA_4_port, EX_REGA_3_port,
EX_REGA_2_port, EX_REGA_1_port, EX_REGA_0_port, EX_REGB_31_port,
EX_REGB_30_port, EX_REGB_29_port, EX_REGB_28_port, EX_REGB_27_port,
EX_REGB_26_port, EX_REGB_25_port, EX_REGB_24_port, EX_REGB_23_port,
EX_REGB_22_port, EX_REGB_21_port, EX_REGB_20_port, EX_REGB_19_port,
EX_REGB_18_port, EX_REGB_17_port, EX_REGB_16_port, EX_REGB_15_port,
EX_REGB_14_port, EX_REGB_13_port, EX_REGB_12_port, EX_REGB_11_port,
EX_REGB_10_port, EX_REGB_9_port, EX_REGB_8_port, EX_REGB_7_port,
EX_REGB_6_port, EX_REGB_5_port, EX_REGB_4_port, EX_REGB_3_port,
EX_REGB_2_port, EX_REGB_1_port, EX_REGB_0_port, EX_IMM16_EXT_31_port,
EX_IMM16_EXT_30_port, EX_IMM16_EXT_29_port, EX_IMM16_EXT_28_port,
EX_IMM16_EXT_27_port, EX_IMM16_EXT_26_port, EX_IMM16_EXT_25_port,
EX_IMM16_EXT_24_port, EX_IMM16_EXT_23_port, EX_IMM16_EXT_22_port,
EX_IMM16_EXT_21_port, EX_IMM16_EXT_20_port, EX_IMM16_EXT_19_port,
EX_IMM16_EXT_18_port, EX_IMM16_EXT_17_port, EX_IMM16_EXT_16_port,
EX_IMM16_EXT_15_port, EX_IMM16_EXT_14_port, EX_IMM16_EXT_13_port,
EX_IMM16_EXT_12_port, EX_IMM16_EXT_11_port, EX_IMM16_EXT_10_port,
EX_IMM16_EXT_9_port, EX_IMM16_EXT_8_port, EX_IMM16_EXT_7_port,
EX_IMM16_EXT_6_port, EX_IMM16_EXT_5_port, EX_IMM16_EXT_4_port,
EX_IMM16_EXT_3_port, EX_IMM16_EXT_2_port, EX_IMM16_EXT_1_port,
EX_IMM16_EXT_0_port, EX_PC_31_port, EX_PC_30_port, EX_PC_29_port,
EX_PC_28_port, EX_PC_27_port, EX_PC_26_port, EX_PC_25_port, EX_PC_24_port
, EX_PC_23_port, EX_PC_22_port, EX_PC_21_port, EX_PC_20_port,
EX_PC_19_port, EX_PC_18_port, EX_PC_17_port, EX_PC_16_port, EX_PC_15_port
, EX_PC_14_port, EX_PC_13_port, EX_PC_12_port, EX_PC_11_port,
EX_PC_10_port, EX_PC_9_port, EX_PC_8_port, EX_PC_7_port, EX_PC_6_port,
EX_PC_5_port, EX_PC_4_port, EX_PC_3_port, EX_PC_2_port, EX_PC_1_port,
EX_PC_0_port, ID_INSTR_AFTER_CU_31_port, ID_INSTR_AFTER_CU_30_port,
ID_INSTR_AFTER_CU_29_port, ID_INSTR_AFTER_CU_28_port,
ID_INSTR_AFTER_CU_27_port, ID_INSTR_AFTER_CU_26_port,
ID_INSTR_AFTER_CU_25_port, ID_INSTR_AFTER_CU_24_port,
ID_INSTR_AFTER_CU_23_port, ID_INSTR_AFTER_CU_22_port,
ID_INSTR_AFTER_CU_21_port, ID_INSTR_AFTER_CU_20_port,
ID_INSTR_AFTER_CU_19_port, ID_INSTR_AFTER_CU_18_port,
ID_INSTR_AFTER_CU_17_port, ID_INSTR_AFTER_CU_16_port,
ID_INSTR_AFTER_CU_15_port, ID_INSTR_AFTER_CU_14_port,
ID_INSTR_AFTER_CU_13_port, ID_INSTR_AFTER_CU_12_port,
ID_INSTR_AFTER_CU_11_port, ID_INSTR_AFTER_CU_10_port,
ID_INSTR_AFTER_CU_9_port, ID_INSTR_AFTER_CU_8_port,
ID_INSTR_AFTER_CU_7_port, ID_INSTR_AFTER_CU_6_port,
ID_INSTR_AFTER_CU_5_port, ID_INSTR_AFTER_CU_4_port,
ID_INSTR_AFTER_CU_3_port, ID_INSTR_AFTER_CU_2_port,
ID_INSTR_AFTER_CU_1_port, ID_INSTR_AFTER_CU_0_port, EX_INSTR_31_port,
EX_INSTR_30_port, EX_INSTR_29_port, EX_INSTR_28_port, EX_INSTR_27_port,
EX_INSTR_26_port, EX_INSTR_25_port, EX_INSTR_24_port, EX_INSTR_23_port,
EX_INSTR_22_port, EX_INSTR_21_port, EX_INSTR_20_port, EX_INSTR_19_port,
EX_INSTR_18_port, EX_INSTR_17_port, EX_INSTR_16_port, EX_INSTR_15_port,
EX_INSTR_14_port, EX_INSTR_13_port, EX_INSTR_12_port, EX_INSTR_11_port,
EX_INSTR_10_port, EX_INSTR_9_port, EX_INSTR_8_port, EX_INSTR_7_port,
EX_INSTR_6_port, EX_INSTR_5_port, EX_INSTR_4_port, EX_INSTR_3_port,
EX_INSTR_2_port, EX_INSTR_1_port, EX_INSTR_0_port, MEM_INSTR_31_port,
MEM_INSTR_30_port, MEM_INSTR_29_port, MEM_INSTR_28_port,
MEM_INSTR_27_port, MEM_INSTR_26_port, MEM_INSTR_25_port,
MEM_INSTR_24_port, MEM_INSTR_23_port, MEM_INSTR_22_port,
MEM_INSTR_21_port, MEM_INSTR_20_port, MEM_INSTR_19_port,
MEM_INSTR_18_port, MEM_INSTR_17_port, MEM_INSTR_16_port,
MEM_INSTR_15_port, MEM_INSTR_14_port, MEM_INSTR_13_port,
MEM_INSTR_12_port, MEM_INSTR_11_port, MEM_INSTR_10_port, MEM_INSTR_9_port
, MEM_INSTR_8_port, MEM_INSTR_7_port, MEM_INSTR_6_port, MEM_INSTR_5_port,
MEM_INSTR_4_port, MEM_INSTR_3_port, MEM_INSTR_2_port, MEM_INSTR_1_port,
MEM_INSTR_0_port, WB_DATA_RAM_31_port, WB_DATA_RAM_30_port,
WB_DATA_RAM_29_port, WB_DATA_RAM_28_port, WB_DATA_RAM_27_port,
WB_DATA_RAM_26_port, WB_DATA_RAM_25_port, WB_DATA_RAM_24_port,
WB_DATA_RAM_23_port, WB_DATA_RAM_22_port, WB_DATA_RAM_21_port,
WB_DATA_RAM_20_port, WB_DATA_RAM_19_port, WB_DATA_RAM_18_port,
WB_DATA_RAM_17_port, WB_DATA_RAM_16_port, WB_DATA_RAM_15_port,
WB_DATA_RAM_14_port, WB_DATA_RAM_13_port, WB_DATA_RAM_12_port,
WB_DATA_RAM_11_port, WB_DATA_RAM_10_port, WB_DATA_RAM_9_port,
WB_DATA_RAM_8_port, WB_DATA_RAM_7_port, WB_DATA_RAM_6_port,
WB_DATA_RAM_5_port, WB_DATA_RAM_4_port, WB_DATA_RAM_3_port,
WB_DATA_RAM_2_port, WB_DATA_RAM_1_port, WB_DATA_RAM_0_port,
WB_ALU_31_port, WB_ALU_30_port, WB_ALU_29_port, WB_ALU_28_port,
WB_ALU_27_port, WB_ALU_26_port, WB_ALU_25_port, WB_ALU_24_port,
WB_ALU_23_port, WB_ALU_22_port, WB_ALU_21_port, WB_ALU_20_port,
WB_ALU_19_port, WB_ALU_18_port, WB_ALU_17_port, WB_ALU_16_port,
WB_ALU_15_port, WB_ALU_14_port, WB_ALU_13_port, WB_ALU_12_port,
WB_ALU_11_port, WB_ALU_10_port, WB_ALU_9_port, WB_ALU_8_port,
WB_ALU_7_port, WB_ALU_6_port, WB_ALU_5_port, WB_ALU_4_port, WB_ALU_3_port
, WB_ALU_2_port, WB_ALU_1_port, WB_ALU_0_port, WB_INSTR_31, WB_INSTR_30,
WB_INSTR_29, WB_INSTR_28, WB_INSTR_27, WB_INSTR_26, WB_INSTR_20_port,
WB_INSTR_19_port, WB_INSTR_18_port, WB_INSTR_17_port, WB_INSTR_16_port,
WB_INSTR_15_port, WB_INSTR_14_port, WB_INSTR_13_port, WB_INSTR_12_port,
WB_INSTR_11_port, WB_INSTR_10_port, WB_INSTR_9_port, WB_INSTR_8_port,
WB_INSTR_7_port, WB_INSTR_6_port, WB_INSTR_5_port, WB_INSTR_4_port,
WB_INSTR_3_port, WB_INSTR_2_port, WB_INSTR_1_port, WB_INSTR_0_port, N730,
N731, N732, N733, N734, N735, N736, N737, N738, N739, N740, N741, N742,
N743, N744, N745, N746, N747, N748, N749, N750, N751, N752, N753, N754,
N755, N756, N757, N758, N759, N760, N761, N764, N765, N766, N767, N768,
N769, N770, N771, N772, N773, N774, N775, N776, N777, N778, N779, N780,
N781, N782, N783, N784, N785, N786, N787, N788, N789, N790, N791, N792,
N793, N794, N795, ID_PC_SUM_31_port, ID_PC_SUM_30_port, ID_PC_SUM_29_port
, ID_PC_SUM_28_port, ID_PC_SUM_27_port, ID_PC_SUM_26_port,
ID_PC_SUM_25_port, ID_PC_SUM_24_port, ID_PC_SUM_23_port,
ID_PC_SUM_22_port, ID_PC_SUM_21_port, ID_PC_SUM_20_port,
ID_PC_SUM_19_port, ID_PC_SUM_18_port, ID_PC_SUM_17_port,
ID_PC_SUM_16_port, ID_PC_SUM_15_port, ID_PC_SUM_14_port,
ID_PC_SUM_13_port, ID_PC_SUM_12_port, ID_PC_SUM_11_port,
ID_PC_SUM_10_port, ID_PC_SUM_9_port, ID_PC_SUM_8_port, ID_PC_SUM_7_port,
ID_PC_SUM_6_port, ID_PC_SUM_5_port, ID_PC_SUM_4_port, ID_PC_SUM_3_port,
ID_PC_SUM_2_port, ID_PC_SUM_1_port, ID_PC_SUM_0_port, N4708, N4710, N4712
, N4716, N4717, N4718, N4719, N4720, N4721, N4722, N4723, N4724, N4725,
N4726, N4727, N4728, N4729, N4730, N4731, N4732, N4733, N4734, N4735,
N4736, N4737, N4738, N4739, N4740, N4741, N4742, N4743, N4744, N4745,
N4746, N4747, N4748, N4749, N4830, N4831, N4832, N4833, N4834, N4835,
N4836, N4837, N4838, N4839, N4840, N4841, N4842, N4843, N4844, N4845,
N4846, N4847, N4848, N4849, N4850, N4851, N4852, N4853, N4854, N4855,
N4856, N4857, N4860, N4861, N4862, N4863, N4864, N4865, N4866, N4867,
N4868, N4869, N4870, N4871, N4872, N4873, N4874, N4875, N4876, N4877,
N4878, N4879, N4880, N4881, N4882, N4883, N4884, N4885, N4886, N4887,
N4888, N4889, N4890, N4891, N6134, N6135, N6136, N6137, N6138, N6139,
N6140, N6141, N6142, N6143, N6144, N6145, N6146, N6147, N6148, N6149,
net56079, net56080, net56081, net56082, net56083, net56084, net56085,
net56086, net56087, net56088, net56089, net56090, net56091, net56092,
net56093, net56094, net56095, net56096, net56097, net56098, net56099,
net56100, net56101, net56102, net56103, net56104, net56105, net56106,
net56107, net56108, net56109, net56110, net56111, net56112, net56113,
net56114, net56115, net56116, net56117, n25, n26, n319, n320, n321, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730_port, n731_port, n732_port
, n733_port, n734_port, n735_port, n736_port, n737_port, n738_port,
n739_port, n740_port, n741_port, n742_port, n743_port, n744_port,
n745_port, n746_port, n747_port, n748_port, n749_port, n750_port,
n751_port, n752_port, n753_port, n754_port, n755_port, n756_port,
n757_port, n758_port, n759_port, n760_port, n761_port, n762, n763,
n764_port, n765_port, n766_port, n767_port, n768_port, n769_port,
n770_port, n771_port, n772_port, n773_port, n774_port, n775_port,
n776_port, n777_port, n778_port, n779_port, n780_port, n781_port,
n782_port, n783_port, n784_port, n785_port, n786_port, n787_port,
n788_port, n789_port, n790_port, n791_port, n792_port, n793_port,
n794_port, n795_port, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815,
n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839,
n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947,
n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959,
n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, net93299, net93300, net93301, net93302, net93303, net93304,
net93305, net93306, net93307, net93308, net93309, net93310, net93311,
net93312, net93313, net93314, net93315, net93316, net93317, net93318,
net93319, net93320, net93321, net93322, net93323, net93324, net93325,
net93326 : std_logic;
begin
PORT_PC <= ( PORT_PC_31_port, PORT_PC_30_port, PORT_PC_29_port,
PORT_PC_28_port, PORT_PC_27_port, PORT_PC_26_port, PORT_PC_25_port,
PORT_PC_24_port, PORT_PC_23_port, PORT_PC_22_port, PORT_PC_21_port,
PORT_PC_20_port, PORT_PC_19_port, PORT_PC_18_port, PORT_PC_17_port,
PORT_PC_16_port, PORT_PC_15_port, PORT_PC_14_port, PORT_PC_13_port,
PORT_PC_12_port, PORT_PC_11_port, PORT_PC_10_port, PORT_PC_9_port,
PORT_PC_8_port, PORT_PC_7_port, PORT_PC_6_port, PORT_PC_5_port,
PORT_PC_4_port, PORT_PC_3_port, PORT_PC_2_port, PORT_PC_1_port,
PORT_PC_0_port );
PORT_ALU <= ( PORT_ALU_31_port, PORT_ALU_30_port, PORT_ALU_29_port,
PORT_ALU_28_port, PORT_ALU_27_port, PORT_ALU_26_port, PORT_ALU_25_port,
PORT_ALU_24_port, PORT_ALU_23_port, PORT_ALU_22_port, PORT_ALU_21_port,
PORT_ALU_20_port, PORT_ALU_19_port, PORT_ALU_18_port, PORT_ALU_17_port,
PORT_ALU_16_port, PORT_ALU_15_port, PORT_ALU_14_port, PORT_ALU_13_port,
PORT_ALU_12_port, PORT_ALU_11_port, PORT_ALU_10_port, PORT_ALU_9_port,
PORT_ALU_8_port, PORT_ALU_7_port, PORT_ALU_6_port, PORT_ALU_5_port,
PORT_ALU_4_port, PORT_ALU_3_port, PORT_ALU_2_port, PORT_ALU_1_port,
PORT_ALU_0_port );
RF_ENABLE <= X_Logic1_port;
RF_WR <= RF_WR_port;
RF_ADD_WR <= ( RF_ADD_WR_4_port, RF_ADD_WR_3_port, RF_ADD_WR_2_port,
RF_ADD_WR_1_port, RF_ADD_WR_0_port );
RF_ADD_RD1 <= ( RF_ADD_RD1_4_port, RF_ADD_RD1_3_port, RF_ADD_RD1_2_port,
RF_ADD_RD1_1_port, RF_ADD_RD1_0_port );
RF_ADD_RD2 <= ( RF_ADD_RD2_4_port, RF_ADD_RD2_3_port, RF_ADD_RD2_2_port,
RF_ADD_RD2_1_port, RF_ADD_RD2_0_port );
X_Logic1_port <= '1';
X_Logic0_port <= '0';
n25 <= '0';
n26 <= '0';
n686 <= '1';
ALU_instance : ALU port map( A(31) => N4749, A(30) => N4748, A(29) => N4747,
A(28) => N4746, A(27) => N4745, A(26) => N4744,
A(25) => N4743, A(24) => N4742, A(23) => N4741,
A(22) => N4740, A(21) => N4739, A(20) => N4738,
A(19) => N4737, A(18) => N4736, A(17) => N4735,
A(16) => N4734, A(15) => N4733, A(14) => N4732,
A(13) => N4731, A(12) => N4730, A(11) => N4729,
A(10) => N4728, A(9) => N4727, A(8) => N4726, A(7)
=> N4725, A(6) => N4724, A(5) => N4723, A(4) =>
N4722, A(3) => N4721, A(2) => N4720, A(1) => N4719,
A(0) => N4718, B(31) => EX_ALU_B_31_port, B(30) =>
N4857, B(29) => N4856, B(28) => N4855, B(27) =>
N4854, B(26) => N4853, B(25) => N4852, B(24) =>
N4851, B(23) => N4850, B(22) => N4849, B(21) =>
N4848, B(20) => N4847, B(19) => N4846, B(18) =>
N4845, B(17) => N4844, B(16) => N4843, B(15) =>
N4842, B(14) => N4841, B(13) => N4840, B(12) =>
N4839, B(11) => N4838, B(10) => N4837, B(9) => N4836
, B(8) => N4835, B(7) => N4834, B(6) => N4833, B(5)
=> N4832, B(4) => N4831, B(3) => N4830, B(2) => n690
, B(1) => n692, B(0) => n688, ALU_SEL(1) =>
EX_ALU_SEL_1_port, ALU_SEL(0) => EX_ALU_SEL_0_port,
COMPARATOR_CW(5) => EX_COMPARATOR_CW_5_port,
COMPARATOR_CW(4) => EX_COMPARATOR_CW_4_port,
COMPARATOR_CW(3) => EX_COMPARATOR_CW_3_port,
COMPARATOR_CW(2) => EX_COMPARATOR_CW_2_port,
COMPARATOR_CW(1) => EX_COMPARATOR_CW_1_port,
COMPARATOR_CW(0) => EX_COMPARATOR_CW_0_port,
LOGIC_CW(3) => EX_LOGIC_CW_3_port, LOGIC_CW(2) =>
EX_LOGIC_CW_2_port, LOGIC_CW(1) =>
EX_LOGIC_CW_2_port, LOGIC_CW(0) => X_Logic0_port,
SHIFTER_CW(2) => X_Logic1_port, SHIFTER_CW(1) =>
EX_SHIFTER_CW_1_port, SHIFTER_CW(0) =>
EX_SHIFTER_CW_0_port, ADD_SUB => EX_ADD_SUB,
ALU_OUT(31) => EX_ALU_OUT_31_port, ALU_OUT(30) =>
EX_ALU_OUT_30_port, ALU_OUT(29) =>
EX_ALU_OUT_29_port, ALU_OUT(28) =>
EX_ALU_OUT_28_port, ALU_OUT(27) =>
EX_ALU_OUT_27_port, ALU_OUT(26) =>
EX_ALU_OUT_26_port, ALU_OUT(25) =>
EX_ALU_OUT_25_port, ALU_OUT(24) =>
EX_ALU_OUT_24_port, ALU_OUT(23) =>
EX_ALU_OUT_23_port, ALU_OUT(22) =>
EX_ALU_OUT_22_port, ALU_OUT(21) =>
EX_ALU_OUT_21_port, ALU_OUT(20) =>
EX_ALU_OUT_20_port, ALU_OUT(19) =>
EX_ALU_OUT_19_port, ALU_OUT(18) =>
EX_ALU_OUT_18_port, ALU_OUT(17) =>
EX_ALU_OUT_17_port, ALU_OUT(16) =>
EX_ALU_OUT_16_port, ALU_OUT(15) =>
EX_ALU_OUT_15_port, ALU_OUT(14) =>
EX_ALU_OUT_14_port, ALU_OUT(13) =>
EX_ALU_OUT_13_port, ALU_OUT(12) =>
EX_ALU_OUT_12_port, ALU_OUT(11) =>
EX_ALU_OUT_11_port, ALU_OUT(10) =>
EX_ALU_OUT_10_port, ALU_OUT(9) => EX_ALU_OUT_9_port,
ALU_OUT(8) => EX_ALU_OUT_8_port, ALU_OUT(7) =>
EX_ALU_OUT_7_port, ALU_OUT(6) => EX_ALU_OUT_6_port,
ALU_OUT(5) => EX_ALU_OUT_5_port, ALU_OUT(4) =>
EX_ALU_OUT_4_port, ALU_OUT(3) => EX_ALU_OUT_3_port,
ALU_OUT(2) => EX_ALU_OUT_2_port, ALU_OUT(1) =>
EX_ALU_OUT_1_port, ALU_OUT(0) => EX_ALU_OUT_0_port,
ZERO => net56116, OVERFLOW => net56117);
BOOTH_instance : BOOTH_N16 port map( A(15) => N4733, A(14) => N4732, A(13)
=> N4731, A(12) => N4730, A(11) => N4729, A(10) =>
N4728, A(9) => N4727, A(8) => N4726, A(7) => N4725,
A(6) => N4724, A(5) => N4723, A(4) => N4722, A(3) =>
N4721, A(2) => N4720, A(1) => N4719, A(0) => N4718,
B(15) => N4842, B(14) => N4841, B(13) => N4840,
B(12) => N4839, B(11) => N4838, B(10) => N4837, B(9)
=> N4836, B(8) => N4835, B(7) => N4834, B(6) =>
N4833, B(5) => N4832, B(4) => N4831, B(3) => N4830,
B(2) => n690, B(1) => n692, B(0) => n688, P(31) =>
EX_MULT_OUT_31_port, P(30) => EX_MULT_OUT_30_port,
P(29) => EX_MULT_OUT_29_port, P(28) =>
EX_MULT_OUT_28_port, P(27) => EX_MULT_OUT_27_port,
P(26) => EX_MULT_OUT_26_port, P(25) =>
EX_MULT_OUT_25_port, P(24) => EX_MULT_OUT_24_port,
P(23) => EX_MULT_OUT_23_port, P(22) =>
EX_MULT_OUT_22_port, P(21) => EX_MULT_OUT_21_port,
P(20) => EX_MULT_OUT_20_port, P(19) =>
EX_MULT_OUT_19_port, P(18) => EX_MULT_OUT_18_port,
P(17) => EX_MULT_OUT_17_port, P(16) =>
EX_MULT_OUT_16_port, P(15) => EX_MULT_OUT_15_port,
P(14) => EX_MULT_OUT_14_port, P(13) =>
EX_MULT_OUT_13_port, P(12) => EX_MULT_OUT_12_port,
P(11) => EX_MULT_OUT_11_port, P(10) =>
EX_MULT_OUT_10_port, P(9) => EX_MULT_OUT_9_port,
P(8) => EX_MULT_OUT_8_port, P(7) =>
EX_MULT_OUT_7_port, P(6) => EX_MULT_OUT_6_port, P(5)
=> EX_MULT_OUT_5_port, P(4) => EX_MULT_OUT_4_port,
P(3) => EX_MULT_OUT_3_port, P(2) =>
EX_MULT_OUT_2_port, P(1) => EX_MULT_OUT_1_port, P(0)
=> EX_MULT_OUT_0_port);
PC_instance : register_generic_N32_0 port map( CK => CLOCK, RESET => RESET,
ENABLE => n697, D(31) => N761, D(30) => N760, D(29)
=> N759, D(28) => N758, D(27) => N757, D(26) => N756
, D(25) => N755, D(24) => N754, D(23) => N753, D(22)
=> N752, D(21) => N751, D(20) => N750, D(19) => N749
, D(18) => N748, D(17) => N747, D(16) => N746, D(15)
=> N745, D(14) => N744, D(13) => N743, D(12) => N742
, D(11) => N741, D(10) => N740, D(9) => N739, D(8)
=> N738, D(7) => N737, D(6) => N736, D(5) => N735,
D(4) => N734, D(3) => N733, D(2) => N732, D(1) =>
N731, D(0) => N730, Q(31) => PORT_PC_31_port, Q(30)
=> PORT_PC_30_port, Q(29) => PORT_PC_29_port, Q(28)
=> PORT_PC_28_port, Q(27) => PORT_PC_27_port, Q(26)
=> PORT_PC_26_port, Q(25) => PORT_PC_25_port, Q(24)
=> PORT_PC_24_port, Q(23) => PORT_PC_23_port, Q(22)
=> PORT_PC_22_port, Q(21) => PORT_PC_21_port, Q(20)
=> PORT_PC_20_port, Q(19) => PORT_PC_19_port, Q(18)
=> PORT_PC_18_port, Q(17) => PORT_PC_17_port, Q(16)
=> PORT_PC_16_port, Q(15) => PORT_PC_15_port, Q(14)
=> PORT_PC_14_port, Q(13) => PORT_PC_13_port, Q(12)
=> PORT_PC_12_port, Q(11) => PORT_PC_11_port, Q(10)
=> PORT_PC_10_port, Q(9) => PORT_PC_9_port, Q(8) =>
PORT_PC_8_port, Q(7) => PORT_PC_7_port, Q(6) =>
PORT_PC_6_port, Q(5) => PORT_PC_5_port, Q(4) =>
PORT_PC_4_port, Q(3) => PORT_PC_3_port, Q(2) =>
PORT_PC_2_port, Q(1) => PORT_PC_1_port, Q(0) =>
PORT_PC_0_port);
ID_SIGN_EXT_instance : ID_SIGN_EXT port map( INPUT(15) => ID_INSTR_15_port,
INPUT(14) => ID_INSTR_14_port, INPUT(13) =>
ID_INSTR_13_port, INPUT(12) => ID_INSTR_12_port,
INPUT(11) => ID_INSTR_11_port, INPUT(10) =>
ID_INSTR_10_port, INPUT(9) => ID_INSTR_9_port,
INPUT(8) => ID_INSTR_8_port, INPUT(7) =>
ID_INSTR_7_port, INPUT(6) => ID_INSTR_6_port,
INPUT(5) => ID_INSTR_5_port, INPUT(4) =>
ID_INSTR_4_port, INPUT(3) => ID_INSTR_3_port,
INPUT(2) => ID_INSTR_2_port, INPUT(1) =>
ID_INSTR_1_port, INPUT(0) => ID_INSTR_0_port,
SIGN_EXT_CONTROL => ID_SIGN_EXT_CONTROL, OUTPUT(31)
=> ID_IMM16_EXT_31_port, OUTPUT(30) =>
ID_IMM16_EXT_30_port, OUTPUT(29) =>
ID_IMM16_EXT_29_port, OUTPUT(28) =>
ID_IMM16_EXT_28_port, OUTPUT(27) =>
ID_IMM16_EXT_27_port, OUTPUT(26) =>
ID_IMM16_EXT_26_port, OUTPUT(25) =>
ID_IMM16_EXT_25_port, OUTPUT(24) =>
ID_IMM16_EXT_24_port, OUTPUT(23) =>
ID_IMM16_EXT_23_port, OUTPUT(22) =>
ID_IMM16_EXT_22_port, OUTPUT(21) =>
ID_IMM16_EXT_21_port, OUTPUT(20) =>
ID_IMM16_EXT_20_port, OUTPUT(19) =>
ID_IMM16_EXT_19_port, OUTPUT(18) =>
ID_IMM16_EXT_18_port, OUTPUT(17) =>
ID_IMM16_EXT_17_port, OUTPUT(16) =>
ID_IMM16_EXT_16_port, OUTPUT(15) =>
ID_IMM16_EXT_15_port, OUTPUT(14) =>
ID_IMM16_EXT_14_port, OUTPUT(13) =>
ID_IMM16_EXT_13_port, OUTPUT(12) =>
ID_IMM16_EXT_12_port, OUTPUT(11) =>
ID_IMM16_EXT_11_port, OUTPUT(10) =>
ID_IMM16_EXT_10_port, OUTPUT(9) =>
ID_IMM16_EXT_9_port, OUTPUT(8) =>
ID_IMM16_EXT_8_port, OUTPUT(7) =>
ID_IMM16_EXT_7_port, OUTPUT(6) =>
ID_IMM16_EXT_6_port, OUTPUT(5) =>
ID_IMM16_EXT_5_port, OUTPUT(4) =>
ID_IMM16_EXT_4_port, OUTPUT(3) =>
ID_IMM16_EXT_3_port, OUTPUT(2) =>
ID_IMM16_EXT_2_port, OUTPUT(1) =>
ID_IMM16_EXT_1_port, OUTPUT(0) =>
ID_IMM16_EXT_0_port);
ID_IMM16_SIGN_EXT_instance : ID_IMM16_SIGN_EXT port map( INPUT(15) =>
ID_INSTR_15_port, INPUT(14) => ID_INSTR_14_port,
INPUT(13) => ID_INSTR_13_port, INPUT(12) =>
ID_INSTR_12_port, INPUT(11) => ID_INSTR_11_port,
INPUT(10) => ID_INSTR_10_port, INPUT(9) =>
ID_INSTR_9_port, INPUT(8) => ID_INSTR_8_port,
INPUT(7) => ID_INSTR_7_port, INPUT(6) =>
ID_INSTR_6_port, INPUT(5) => ID_INSTR_5_port,
INPUT(4) => ID_INSTR_4_port, INPUT(3) =>
ID_INSTR_3_port, INPUT(2) => ID_INSTR_2_port,
INPUT(1) => ID_INSTR_1_port, INPUT(0) =>
ID_INSTR_0_port, OUTPUT(31) => ID_IMM16_SHL2_31_port
, OUTPUT(30) => ID_IMM16_SHL2_30_port, OUTPUT(29) =>
ID_IMM16_SHL2_29_port, OUTPUT(28) =>
ID_IMM16_SHL2_28_port, OUTPUT(27) =>
ID_IMM16_SHL2_27_port, OUTPUT(26) =>
ID_IMM16_SHL2_26_port, OUTPUT(25) =>
ID_IMM16_SHL2_25_port, OUTPUT(24) =>
ID_IMM16_SHL2_24_port, OUTPUT(23) =>
ID_IMM16_SHL2_23_port, OUTPUT(22) =>
ID_IMM16_SHL2_22_port, OUTPUT(21) =>
ID_IMM16_SHL2_21_port, OUTPUT(20) =>
ID_IMM16_SHL2_20_port, OUTPUT(19) =>
ID_IMM16_SHL2_19_port, OUTPUT(18) =>
ID_IMM16_SHL2_18_port, OUTPUT(17) =>
ID_IMM16_SHL2_17_port, OUTPUT(16) =>
ID_IMM16_SHL2_16_port, OUTPUT(15) =>
ID_IMM16_SHL2_15_port, OUTPUT(14) =>
ID_IMM16_SHL2_14_port, OUTPUT(13) =>
ID_IMM16_SHL2_13_port, OUTPUT(12) =>
ID_IMM16_SHL2_12_port, OUTPUT(11) =>
ID_IMM16_SHL2_11_port, OUTPUT(10) =>
ID_IMM16_SHL2_10_port, OUTPUT(9) =>
ID_IMM16_SHL2_9_port, OUTPUT(8) =>
ID_IMM16_SHL2_8_port, OUTPUT(7) =>
ID_IMM16_SHL2_7_port, OUTPUT(6) =>
ID_IMM16_SHL2_6_port, OUTPUT(5) =>
ID_IMM16_SHL2_5_port, OUTPUT(4) =>
ID_IMM16_SHL2_4_port, OUTPUT(3) =>
ID_IMM16_SHL2_3_port, OUTPUT(2) =>
ID_IMM16_SHL2_2_port, OUTPUT(1) => net93325,
OUTPUT(0) => net93326);
WB_SIGN_EXT_16_instance : WB_SIGN_EXT_16 port map( INPUT(15) => N6149,
INPUT(14) => N6148, INPUT(13) => N6147, INPUT(12) =>
N6146, INPUT(11) => N6145, INPUT(10) => N6144,
INPUT(9) => N6143, INPUT(8) => N6142, INPUT(7) =>
N6141, INPUT(6) => N6140, INPUT(5) => N6139,
INPUT(4) => N6138, INPUT(3) => N6137, INPUT(2) =>
N6136, INPUT(1) => N6135, INPUT(0) => N6134,
SIGN_EXT_CONTROL => WB_SIGN_EXT_16_CONTROL,
OUTPUT(31) => WB_DATA_EXT_16_31_port, OUTPUT(30) =>
WB_DATA_EXT_16_30_port, OUTPUT(29) =>
WB_DATA_EXT_16_29_port, OUTPUT(28) =>
WB_DATA_EXT_16_28_port, OUTPUT(27) =>
WB_DATA_EXT_16_27_port, OUTPUT(26) =>
WB_DATA_EXT_16_26_port, OUTPUT(25) =>
WB_DATA_EXT_16_25_port, OUTPUT(24) =>
WB_DATA_EXT_16_24_port, OUTPUT(23) =>
WB_DATA_EXT_16_23_port, OUTPUT(22) =>
WB_DATA_EXT_16_22_port, OUTPUT(21) =>
WB_DATA_EXT_16_21_port, OUTPUT(20) =>
WB_DATA_EXT_16_20_port, OUTPUT(19) =>
WB_DATA_EXT_16_19_port, OUTPUT(18) =>
WB_DATA_EXT_16_18_port, OUTPUT(17) =>
WB_DATA_EXT_16_17_port, OUTPUT(16) =>
WB_DATA_EXT_16_16_port, OUTPUT(15) =>
WB_DATA_EXT_16_15_port, OUTPUT(14) =>
WB_DATA_EXT_16_14_port, OUTPUT(13) =>
WB_DATA_EXT_16_13_port, OUTPUT(12) =>
WB_DATA_EXT_16_12_port, OUTPUT(11) =>
WB_DATA_EXT_16_11_port, OUTPUT(10) =>
WB_DATA_EXT_16_10_port, OUTPUT(9) =>
WB_DATA_EXT_16_9_port, OUTPUT(8) =>
WB_DATA_EXT_16_8_port, OUTPUT(7) =>
WB_DATA_EXT_16_7_port, OUTPUT(6) =>
WB_DATA_EXT_16_6_port, OUTPUT(5) =>
WB_DATA_EXT_16_5_port, OUTPUT(4) =>
WB_DATA_EXT_16_4_port, OUTPUT(3) =>
WB_DATA_EXT_16_3_port, OUTPUT(2) =>
WB_DATA_EXT_16_2_port, OUTPUT(1) =>
WB_DATA_EXT_16_1_port, OUTPUT(0) =>
WB_DATA_EXT_16_0_port);
WB_SIGN_EXT_8_instance : WB_SIGN_EXT_8 port map( INPUT(7) => N6141, INPUT(6)
=> N6140, INPUT(5) => N6139, INPUT(4) => N6138,
INPUT(3) => N6137, INPUT(2) => N6136, INPUT(1) =>
N6135, INPUT(0) => N6134, OUTPUT(31) => net93301,
OUTPUT(30) => net93302, OUTPUT(29) => net93303,
OUTPUT(28) => net93304, OUTPUT(27) => net93305,
OUTPUT(26) => net93306, OUTPUT(25) => net93307,
OUTPUT(24) => net93308, OUTPUT(23) => net93309,
OUTPUT(22) => net93310, OUTPUT(21) => net93311,
OUTPUT(20) => net93312, OUTPUT(19) => net93313,
OUTPUT(18) => net93314, OUTPUT(17) => net93315,
OUTPUT(16) => net93316, OUTPUT(15) => net93317,
OUTPUT(14) => net93318, OUTPUT(13) => net93319,
OUTPUT(12) => net93320, OUTPUT(11) => net93321,
OUTPUT(10) => net93322, OUTPUT(9) =>
WB_DATA_EXT_8_9_port, OUTPUT(8) => net93323,
OUTPUT(7) => net93324, OUTPUT(6) =>
WB_DATA_EXT_8_6_port, OUTPUT(5) =>
WB_DATA_EXT_8_5_port, OUTPUT(4) =>
WB_DATA_EXT_8_4_port, OUTPUT(3) =>
WB_DATA_EXT_8_3_port, OUTPUT(2) =>
WB_DATA_EXT_8_2_port, OUTPUT(1) =>
WB_DATA_EXT_8_1_port, OUTPUT(0) =>
WB_DATA_EXT_8_0_port);
zero_instance : zero_N32 port map( INPUT(31) => RF_OUT1(31), INPUT(30) =>
RF_OUT1(30), INPUT(29) => RF_OUT1(29), INPUT(28) =>
RF_OUT1(28), INPUT(27) => RF_OUT1(27), INPUT(26) =>
RF_OUT1(26), INPUT(25) => RF_OUT1(25), INPUT(24) =>
RF_OUT1(24), INPUT(23) => RF_OUT1(23), INPUT(22) =>
RF_OUT1(22), INPUT(21) => RF_OUT1(21), INPUT(20) =>
RF_OUT1(20), INPUT(19) => RF_OUT1(19), INPUT(18) =>
RF_OUT1(18), INPUT(17) => RF_OUT1(17), INPUT(16) =>
RF_OUT1(16), INPUT(15) => RF_OUT1(15), INPUT(14) =>
RF_OUT1(14), INPUT(13) => RF_OUT1(13), INPUT(12) =>
RF_OUT1(12), INPUT(11) => RF_OUT1(11), INPUT(10) =>
RF_OUT1(10), INPUT(9) => RF_OUT1(9), INPUT(8) =>
RF_OUT1(8), INPUT(7) => RF_OUT1(7), INPUT(6) =>
RF_OUT1(6), INPUT(5) => RF_OUT1(5), INPUT(4) =>
RF_OUT1(4), INPUT(3) => RF_OUT1(3), INPUT(2) =>
RF_OUT1(2), INPUT(1) => RF_OUT1(1), INPUT(0) =>
RF_OUT1(0), ZERO => ID_REGA_ZERO);
IF_STALL_REG_instance : flip_flop port map( CK => CLOCK, RESET => RESET,
ENABLE => X_Logic1_port, D => IF_NOT_RESET, Q =>
IF_STALL_SEL);
IF_ID_PC_INC_REG_instance : register_generic_N32_14 port map( CK => CLOCK,
RESET => RESET, ENABLE => n697, D(31) =>
IF_PC_INC_31_port, D(30) => IF_PC_INC_30_port, D(29)
=> IF_PC_INC_29_port, D(28) => IF_PC_INC_28_port,
D(27) => IF_PC_INC_27_port, D(26) =>
IF_PC_INC_26_port, D(25) => IF_PC_INC_25_port, D(24)
=> IF_PC_INC_24_port, D(23) => IF_PC_INC_23_port,
D(22) => IF_PC_INC_22_port, D(21) =>
IF_PC_INC_21_port, D(20) => IF_PC_INC_20_port, D(19)
=> IF_PC_INC_19_port, D(18) => IF_PC_INC_18_port,
D(17) => IF_PC_INC_17_port, D(16) =>
IF_PC_INC_16_port, D(15) => IF_PC_INC_15_port, D(14)
=> IF_PC_INC_14_port, D(13) => IF_PC_INC_13_port,
D(12) => IF_PC_INC_12_port, D(11) =>
IF_PC_INC_11_port, D(10) => IF_PC_INC_10_port, D(9)
=> IF_PC_INC_9_port, D(8) => IF_PC_INC_8_port, D(7)
=> IF_PC_INC_7_port, D(6) => IF_PC_INC_6_port, D(5)
=> IF_PC_INC_5_port, D(4) => IF_PC_INC_4_port, D(3)
=> IF_PC_INC_3_port, D(2) => IF_PC_INC_2_port, D(1)
=> IF_PC_INC_1_port, D(0) => IF_PC_INC_0_port, Q(31)
=> net56084, Q(30) => net56085, Q(29) => net56086,
Q(28) => net56087, Q(27) => net56088, Q(26) =>
net56089, Q(25) => net56090, Q(24) => net56091,
Q(23) => net56092, Q(22) => net56093, Q(21) =>
net56094, Q(20) => net56095, Q(19) => net56096,
Q(18) => net56097, Q(17) => net56098, Q(16) =>
net56099, Q(15) => net56100, Q(14) => net56101,
Q(13) => net56102, Q(12) => net56103, Q(11) =>
net56104, Q(10) => net56105, Q(9) => net56106, Q(8)
=> net56107, Q(7) => net56108, Q(6) => net56109,
Q(5) => net56110, Q(4) => net56111, Q(3) => net56112
, Q(2) => net56113, Q(1) => net56114, Q(0) =>
net56115);
IF_ID_INSTR_REG_instance : register_generic_N32_13 port map( CK => CLOCK,
RESET => RESET, ENABLE => n697, D(31) => N795, D(30)
=> N794, D(29) => N793, D(28) => N792, D(27) => N791
, D(26) => N790, D(25) => N789, D(24) => N788, D(23)
=> N787, D(22) => N786, D(21) => N785, D(20) => N784
, D(19) => N783, D(18) => N782, D(17) => N781, D(16)
=> N780, D(15) => N779, D(14) => N778, D(13) => N777
, D(12) => N776, D(11) => N775, D(10) => N774, D(9)
=> N773, D(8) => N772, D(7) => N771, D(6) => N770,
D(5) => N769, D(4) => N768, D(3) => N767, D(2) =>
N766, D(1) => N765, D(0) => N764, Q(31) =>
ID_INSTR_31, Q(30) => ID_INSTR_30, Q(29) =>
ID_INSTR_29, Q(28) => ID_INSTR_28, Q(27) =>
ID_INSTR_27, Q(26) => ID_INSTR_26, Q(25) =>
RF_ADD_RD1_4_port, Q(24) => RF_ADD_RD1_3_port, Q(23)
=> RF_ADD_RD1_2_port, Q(22) => RF_ADD_RD1_1_port,
Q(21) => RF_ADD_RD1_0_port, Q(20) =>
RF_ADD_RD2_4_port, Q(19) => RF_ADD_RD2_3_port, Q(18)
=> RF_ADD_RD2_2_port, Q(17) => RF_ADD_RD2_1_port,
Q(16) => RF_ADD_RD2_0_port, Q(15) =>
ID_INSTR_15_port, Q(14) => ID_INSTR_14_port, Q(13)
=> ID_INSTR_13_port, Q(12) => ID_INSTR_12_port,
Q(11) => ID_INSTR_11_port, Q(10) => ID_INSTR_10_port
, Q(9) => ID_INSTR_9_port, Q(8) => ID_INSTR_8_port,
Q(7) => ID_INSTR_7_port, Q(6) => ID_INSTR_6_port,
Q(5) => ID_INSTR_5_port, Q(4) => ID_INSTR_4_port,
Q(3) => ID_INSTR_3_port, Q(2) => ID_INSTR_2_port,
Q(1) => ID_INSTR_1_port, Q(0) => ID_INSTR_0_port);
IF_ID_PC_REG_instance : register_generic_N32_12 port map( CK => CLOCK, RESET
=> RESET, ENABLE => n697, D(31) => PORT_PC_31_port,
D(30) => PORT_PC_30_port, D(29) => PORT_PC_29_port,
D(28) => PORT_PC_28_port, D(27) => PORT_PC_27_port,
D(26) => PORT_PC_26_port, D(25) => PORT_PC_25_port,
D(24) => PORT_PC_24_port, D(23) => PORT_PC_23_port,
D(22) => PORT_PC_22_port, D(21) => PORT_PC_21_port,
D(20) => PORT_PC_20_port, D(19) => PORT_PC_19_port,
D(18) => PORT_PC_18_port, D(17) => PORT_PC_17_port,
D(16) => PORT_PC_16_port, D(15) => PORT_PC_15_port,
D(14) => PORT_PC_14_port, D(13) => PORT_PC_13_port,
D(12) => PORT_PC_12_port, D(11) => PORT_PC_11_port,
D(10) => PORT_PC_10_port, D(9) => PORT_PC_9_port,
D(8) => PORT_PC_8_port, D(7) => PORT_PC_7_port, D(6)
=> PORT_PC_6_port, D(5) => PORT_PC_5_port, D(4) =>
PORT_PC_4_port, D(3) => PORT_PC_3_port, D(2) =>
PORT_PC_2_port, D(1) => PORT_PC_1_port, D(0) =>
PORT_PC_0_port, Q(31) => ID_PC_31_port, Q(30) =>
ID_PC_30_port, Q(29) => ID_PC_29_port, Q(28) =>
ID_PC_28_port, Q(27) => ID_PC_27_port, Q(26) =>
ID_PC_26_port, Q(25) => ID_PC_25_port, Q(24) =>
ID_PC_24_port, Q(23) => ID_PC_23_port, Q(22) =>
ID_PC_22_port, Q(21) => ID_PC_21_port, Q(20) =>
ID_PC_20_port, Q(19) => ID_PC_19_port, Q(18) =>
ID_PC_18_port, Q(17) => ID_PC_17_port, Q(16) =>
ID_PC_16_port, Q(15) => ID_PC_15_port, Q(14) =>
ID_PC_14_port, Q(13) => ID_PC_13_port, Q(12) =>
ID_PC_12_port, Q(11) => ID_PC_11_port, Q(10) =>
ID_PC_10_port, Q(9) => ID_PC_9_port, Q(8) =>
ID_PC_8_port, Q(7) => ID_PC_7_port, Q(6) =>
ID_PC_6_port, Q(5) => ID_PC_5_port, Q(4) =>
ID_PC_4_port, Q(3) => ID_PC_3_port, Q(2) =>
ID_PC_2_port, Q(1) => ID_PC_1_port, Q(0) =>
ID_PC_0_port);
ID_EX_REGA_REG_instance : register_generic_N32_11 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) => RF_OUT1(31)
, D(30) => RF_OUT1(30), D(29) => RF_OUT1(29), D(28)
=> RF_OUT1(28), D(27) => RF_OUT1(27), D(26) =>
RF_OUT1(26), D(25) => RF_OUT1(25), D(24) =>
RF_OUT1(24), D(23) => RF_OUT1(23), D(22) =>
RF_OUT1(22), D(21) => RF_OUT1(21), D(20) =>
RF_OUT1(20), D(19) => RF_OUT1(19), D(18) =>
RF_OUT1(18), D(17) => RF_OUT1(17), D(16) =>
RF_OUT1(16), D(15) => RF_OUT1(15), D(14) =>
RF_OUT1(14), D(13) => RF_OUT1(13), D(12) =>
RF_OUT1(12), D(11) => RF_OUT1(11), D(10) =>
RF_OUT1(10), D(9) => RF_OUT1(9), D(8) => RF_OUT1(8),
D(7) => RF_OUT1(7), D(6) => RF_OUT1(6), D(5) =>
RF_OUT1(5), D(4) => RF_OUT1(4), D(3) => RF_OUT1(3),
D(2) => RF_OUT1(2), D(1) => RF_OUT1(1), D(0) =>
RF_OUT1(0), Q(31) => EX_REGA_31_port, Q(30) =>
EX_REGA_30_port, Q(29) => EX_REGA_29_port, Q(28) =>
EX_REGA_28_port, Q(27) => EX_REGA_27_port, Q(26) =>
EX_REGA_26_port, Q(25) => EX_REGA_25_port, Q(24) =>
EX_REGA_24_port, Q(23) => EX_REGA_23_port, Q(22) =>
EX_REGA_22_port, Q(21) => EX_REGA_21_port, Q(20) =>
EX_REGA_20_port, Q(19) => EX_REGA_19_port, Q(18) =>
EX_REGA_18_port, Q(17) => EX_REGA_17_port, Q(16) =>
EX_REGA_16_port, Q(15) => EX_REGA_15_port, Q(14) =>
EX_REGA_14_port, Q(13) => EX_REGA_13_port, Q(12) =>
EX_REGA_12_port, Q(11) => EX_REGA_11_port, Q(10) =>
EX_REGA_10_port, Q(9) => EX_REGA_9_port, Q(8) =>
EX_REGA_8_port, Q(7) => EX_REGA_7_port, Q(6) =>
EX_REGA_6_port, Q(5) => EX_REGA_5_port, Q(4) =>
EX_REGA_4_port, Q(3) => EX_REGA_3_port, Q(2) =>
EX_REGA_2_port, Q(1) => EX_REGA_1_port, Q(0) =>
EX_REGA_0_port);
ID_EX_REGB_REG_instance : register_generic_N32_10 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) => RF_OUT2(31)
, D(30) => RF_OUT2(30), D(29) => RF_OUT2(29), D(28)
=> RF_OUT2(28), D(27) => RF_OUT2(27), D(26) =>
RF_OUT2(26), D(25) => RF_OUT2(25), D(24) =>
RF_OUT2(24), D(23) => RF_OUT2(23), D(22) =>
RF_OUT2(22), D(21) => RF_OUT2(21), D(20) =>
RF_OUT2(20), D(19) => RF_OUT2(19), D(18) =>
RF_OUT2(18), D(17) => RF_OUT2(17), D(16) =>
RF_OUT2(16), D(15) => RF_OUT2(15), D(14) =>
RF_OUT2(14), D(13) => RF_OUT2(13), D(12) =>
RF_OUT2(12), D(11) => RF_OUT2(11), D(10) =>
RF_OUT2(10), D(9) => RF_OUT2(9), D(8) => RF_OUT2(8),
D(7) => RF_OUT2(7), D(6) => RF_OUT2(6), D(5) =>
RF_OUT2(5), D(4) => RF_OUT2(4), D(3) => RF_OUT2(3),
D(2) => RF_OUT2(2), D(1) => RF_OUT2(1), D(0) =>
RF_OUT2(0), Q(31) => EX_REGB_31_port, Q(30) =>
EX_REGB_30_port, Q(29) => EX_REGB_29_port, Q(28) =>
EX_REGB_28_port, Q(27) => EX_REGB_27_port, Q(26) =>
EX_REGB_26_port, Q(25) => EX_REGB_25_port, Q(24) =>
EX_REGB_24_port, Q(23) => EX_REGB_23_port, Q(22) =>
EX_REGB_22_port, Q(21) => EX_REGB_21_port, Q(20) =>
EX_REGB_20_port, Q(19) => EX_REGB_19_port, Q(18) =>
EX_REGB_18_port, Q(17) => EX_REGB_17_port, Q(16) =>
EX_REGB_16_port, Q(15) => EX_REGB_15_port, Q(14) =>
EX_REGB_14_port, Q(13) => EX_REGB_13_port, Q(12) =>
EX_REGB_12_port, Q(11) => EX_REGB_11_port, Q(10) =>
EX_REGB_10_port, Q(9) => EX_REGB_9_port, Q(8) =>
EX_REGB_8_port, Q(7) => EX_REGB_7_port, Q(6) =>
EX_REGB_6_port, Q(5) => EX_REGB_5_port, Q(4) =>
EX_REGB_4_port, Q(3) => EX_REGB_3_port, Q(2) =>
EX_REGB_2_port, Q(1) => EX_REGB_1_port, Q(0) =>
EX_REGB_0_port);
ID_EX_IMM16_EXT_REG_instance : register_generic_N32_9 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) =>
ID_IMM16_EXT_31_port, D(30) => ID_IMM16_EXT_30_port,
D(29) => ID_IMM16_EXT_29_port, D(28) =>
ID_IMM16_EXT_28_port, D(27) => ID_IMM16_EXT_27_port,
D(26) => ID_IMM16_EXT_26_port, D(25) =>
ID_IMM16_EXT_25_port, D(24) => ID_IMM16_EXT_24_port,
D(23) => ID_IMM16_EXT_23_port, D(22) =>
ID_IMM16_EXT_22_port, D(21) => ID_IMM16_EXT_21_port,
D(20) => ID_IMM16_EXT_20_port, D(19) =>
ID_IMM16_EXT_19_port, D(18) => ID_IMM16_EXT_18_port,
D(17) => ID_IMM16_EXT_17_port, D(16) =>
ID_IMM16_EXT_16_port, D(15) => ID_IMM16_EXT_15_port,
D(14) => ID_IMM16_EXT_14_port, D(13) =>
ID_IMM16_EXT_13_port, D(12) => ID_IMM16_EXT_12_port,
D(11) => ID_IMM16_EXT_11_port, D(10) =>
ID_IMM16_EXT_10_port, D(9) => ID_IMM16_EXT_9_port,
D(8) => ID_IMM16_EXT_8_port, D(7) =>
ID_IMM16_EXT_7_port, D(6) => ID_IMM16_EXT_6_port,
D(5) => ID_IMM16_EXT_5_port, D(4) =>
ID_IMM16_EXT_4_port, D(3) => ID_IMM16_EXT_3_port,
D(2) => ID_IMM16_EXT_2_port, D(1) =>
ID_IMM16_EXT_1_port, D(0) => ID_IMM16_EXT_0_port,
Q(31) => EX_IMM16_EXT_31_port, Q(30) =>
EX_IMM16_EXT_30_port, Q(29) => EX_IMM16_EXT_29_port,
Q(28) => EX_IMM16_EXT_28_port, Q(27) =>
EX_IMM16_EXT_27_port, Q(26) => EX_IMM16_EXT_26_port,
Q(25) => EX_IMM16_EXT_25_port, Q(24) =>
EX_IMM16_EXT_24_port, Q(23) => EX_IMM16_EXT_23_port,
Q(22) => EX_IMM16_EXT_22_port, Q(21) =>
EX_IMM16_EXT_21_port, Q(20) => EX_IMM16_EXT_20_port,
Q(19) => EX_IMM16_EXT_19_port, Q(18) =>
EX_IMM16_EXT_18_port, Q(17) => EX_IMM16_EXT_17_port,
Q(16) => EX_IMM16_EXT_16_port, Q(15) =>
EX_IMM16_EXT_15_port, Q(14) => EX_IMM16_EXT_14_port,
Q(13) => EX_IMM16_EXT_13_port, Q(12) =>
EX_IMM16_EXT_12_port, Q(11) => EX_IMM16_EXT_11_port,
Q(10) => EX_IMM16_EXT_10_port, Q(9) =>
EX_IMM16_EXT_9_port, Q(8) => EX_IMM16_EXT_8_port,
Q(7) => EX_IMM16_EXT_7_port, Q(6) =>
EX_IMM16_EXT_6_port, Q(5) => EX_IMM16_EXT_5_port,
Q(4) => EX_IMM16_EXT_4_port, Q(3) =>
EX_IMM16_EXT_3_port, Q(2) => EX_IMM16_EXT_2_port,
Q(1) => EX_IMM16_EXT_1_port, Q(0) =>
EX_IMM16_EXT_0_port);
ID_EX_PC_REG_instance : register_generic_N32_8 port map( CK => CLOCK, RESET
=> RESET, ENABLE => n686, D(31) => ID_PC_31_port,
D(30) => ID_PC_30_port, D(29) => ID_PC_29_port,
D(28) => ID_PC_28_port, D(27) => ID_PC_27_port,
D(26) => ID_PC_26_port, D(25) => ID_PC_25_port,
D(24) => ID_PC_24_port, D(23) => ID_PC_23_port,
D(22) => ID_PC_22_port, D(21) => ID_PC_21_port,
D(20) => ID_PC_20_port, D(19) => ID_PC_19_port,
D(18) => ID_PC_18_port, D(17) => ID_PC_17_port,
D(16) => ID_PC_16_port, D(15) => ID_PC_15_port,
D(14) => ID_PC_14_port, D(13) => ID_PC_13_port,
D(12) => ID_PC_12_port, D(11) => ID_PC_11_port,
D(10) => ID_PC_10_port, D(9) => ID_PC_9_port, D(8)
=> ID_PC_8_port, D(7) => ID_PC_7_port, D(6) =>
ID_PC_6_port, D(5) => ID_PC_5_port, D(4) =>
ID_PC_4_port, D(3) => ID_PC_3_port, D(2) =>
ID_PC_2_port, D(1) => ID_PC_1_port, D(0) =>
ID_PC_0_port, Q(31) => EX_PC_31_port, Q(30) =>
EX_PC_30_port, Q(29) => EX_PC_29_port, Q(28) =>
EX_PC_28_port, Q(27) => EX_PC_27_port, Q(26) =>
EX_PC_26_port, Q(25) => EX_PC_25_port, Q(24) =>
EX_PC_24_port, Q(23) => EX_PC_23_port, Q(22) =>
EX_PC_22_port, Q(21) => EX_PC_21_port, Q(20) =>
EX_PC_20_port, Q(19) => EX_PC_19_port, Q(18) =>
EX_PC_18_port, Q(17) => EX_PC_17_port, Q(16) =>
EX_PC_16_port, Q(15) => EX_PC_15_port, Q(14) =>
EX_PC_14_port, Q(13) => EX_PC_13_port, Q(12) =>
EX_PC_12_port, Q(11) => EX_PC_11_port, Q(10) =>
EX_PC_10_port, Q(9) => EX_PC_9_port, Q(8) =>
EX_PC_8_port, Q(7) => EX_PC_7_port, Q(6) =>
EX_PC_6_port, Q(5) => EX_PC_5_port, Q(4) =>
EX_PC_4_port, Q(3) => EX_PC_3_port, Q(2) =>
EX_PC_2_port, Q(1) => EX_PC_1_port, Q(0) =>
EX_PC_0_port);
ID_EX_INSTR_REG_instance : register_generic_N32_7 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) =>
ID_INSTR_AFTER_CU_31_port, D(30) =>
ID_INSTR_AFTER_CU_30_port, D(29) =>
ID_INSTR_AFTER_CU_29_port, D(28) =>
ID_INSTR_AFTER_CU_28_port, D(27) =>
ID_INSTR_AFTER_CU_27_port, D(26) =>
ID_INSTR_AFTER_CU_26_port, D(25) =>
ID_INSTR_AFTER_CU_25_port, D(24) =>
ID_INSTR_AFTER_CU_24_port, D(23) =>
ID_INSTR_AFTER_CU_23_port, D(22) =>
ID_INSTR_AFTER_CU_22_port, D(21) =>
ID_INSTR_AFTER_CU_21_port, D(20) =>
ID_INSTR_AFTER_CU_20_port, D(19) =>
ID_INSTR_AFTER_CU_19_port, D(18) =>
ID_INSTR_AFTER_CU_18_port, D(17) =>
ID_INSTR_AFTER_CU_17_port, D(16) =>
ID_INSTR_AFTER_CU_16_port, D(15) =>
ID_INSTR_AFTER_CU_15_port, D(14) =>
ID_INSTR_AFTER_CU_14_port, D(13) =>
ID_INSTR_AFTER_CU_13_port, D(12) =>
ID_INSTR_AFTER_CU_12_port, D(11) =>
ID_INSTR_AFTER_CU_11_port, D(10) =>
ID_INSTR_AFTER_CU_10_port, D(9) =>
ID_INSTR_AFTER_CU_9_port, D(8) =>
ID_INSTR_AFTER_CU_8_port, D(7) =>
ID_INSTR_AFTER_CU_7_port, D(6) =>
ID_INSTR_AFTER_CU_6_port, D(5) =>
ID_INSTR_AFTER_CU_5_port, D(4) =>
ID_INSTR_AFTER_CU_4_port, D(3) =>
ID_INSTR_AFTER_CU_3_port, D(2) =>
ID_INSTR_AFTER_CU_2_port, D(1) =>
ID_INSTR_AFTER_CU_1_port, D(0) =>
ID_INSTR_AFTER_CU_0_port, Q(31) => EX_INSTR_31_port,
Q(30) => EX_INSTR_30_port, Q(29) => EX_INSTR_29_port
, Q(28) => EX_INSTR_28_port, Q(27) =>
EX_INSTR_27_port, Q(26) => EX_INSTR_26_port, Q(25)
=> EX_INSTR_25_port, Q(24) => EX_INSTR_24_port,
Q(23) => EX_INSTR_23_port, Q(22) => EX_INSTR_22_port
, Q(21) => EX_INSTR_21_port, Q(20) =>
EX_INSTR_20_port, Q(19) => EX_INSTR_19_port, Q(18)
=> EX_INSTR_18_port, Q(17) => EX_INSTR_17_port,
Q(16) => EX_INSTR_16_port, Q(15) => EX_INSTR_15_port
, Q(14) => EX_INSTR_14_port, Q(13) =>
EX_INSTR_13_port, Q(12) => EX_INSTR_12_port, Q(11)
=> EX_INSTR_11_port, Q(10) => EX_INSTR_10_port, Q(9)
=> EX_INSTR_9_port, Q(8) => EX_INSTR_8_port, Q(7) =>
EX_INSTR_7_port, Q(6) => EX_INSTR_6_port, Q(5) =>
EX_INSTR_5_port, Q(4) => EX_INSTR_4_port, Q(3) =>
EX_INSTR_3_port, Q(2) => EX_INSTR_2_port, Q(1) =>
EX_INSTR_1_port, Q(0) => EX_INSTR_0_port);
EX_MEM_REGB_REG_instance : register_generic_N32_6 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) =>
EX_REGB_31_port, D(30) => EX_REGB_30_port, D(29) =>
EX_REGB_29_port, D(28) => EX_REGB_28_port, D(27) =>
EX_REGB_27_port, D(26) => EX_REGB_26_port, D(25) =>
EX_REGB_25_port, D(24) => EX_REGB_24_port, D(23) =>
EX_REGB_23_port, D(22) => EX_REGB_22_port, D(21) =>
EX_REGB_21_port, D(20) => EX_REGB_20_port, D(19) =>
EX_REGB_19_port, D(18) => EX_REGB_18_port, D(17) =>
EX_REGB_17_port, D(16) => EX_REGB_16_port, D(15) =>
EX_REGB_15_port, D(14) => EX_REGB_14_port, D(13) =>
EX_REGB_13_port, D(12) => EX_REGB_12_port, D(11) =>
EX_REGB_11_port, D(10) => EX_REGB_10_port, D(9) =>
EX_REGB_9_port, D(8) => EX_REGB_8_port, D(7) =>
EX_REGB_7_port, D(6) => EX_REGB_6_port, D(5) =>
EX_REGB_5_port, D(4) => EX_REGB_4_port, D(3) =>
EX_REGB_3_port, D(2) => EX_REGB_2_port, D(1) =>
EX_REGB_1_port, D(0) => EX_REGB_0_port, Q(31) =>
PORT_REGB(31), Q(30) => PORT_REGB(30), Q(29) =>
PORT_REGB(29), Q(28) => PORT_REGB(28), Q(27) =>
PORT_REGB(27), Q(26) => PORT_REGB(26), Q(25) =>
PORT_REGB(25), Q(24) => PORT_REGB(24), Q(23) =>
PORT_REGB(23), Q(22) => PORT_REGB(22), Q(21) =>
PORT_REGB(21), Q(20) => PORT_REGB(20), Q(19) =>
PORT_REGB(19), Q(18) => PORT_REGB(18), Q(17) =>
PORT_REGB(17), Q(16) => PORT_REGB(16), Q(15) =>
PORT_REGB(15), Q(14) => PORT_REGB(14), Q(13) =>
PORT_REGB(13), Q(12) => PORT_REGB(12), Q(11) =>
PORT_REGB(11), Q(10) => PORT_REGB(10), Q(9) =>
PORT_REGB(9), Q(8) => PORT_REGB(8), Q(7) =>
PORT_REGB(7), Q(6) => PORT_REGB(6), Q(5) =>
PORT_REGB(5), Q(4) => PORT_REGB(4), Q(3) =>
PORT_REGB(3), Q(2) => PORT_REGB(2), Q(1) =>
PORT_REGB(1), Q(0) => PORT_REGB(0));
EX_MEM_OUT_REG_instance : register_generic_N32_5 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) => N4891,
D(30) => N4890, D(29) => N4889, D(28) => N4888,
D(27) => N4887, D(26) => N4886, D(25) => N4885,
D(24) => N4884, D(23) => N4883, D(22) => N4882,
D(21) => N4881, D(20) => N4880, D(19) => N4879,
D(18) => N4878, D(17) => N4877, D(16) => N4876,
D(15) => N4875, D(14) => N4874, D(13) => N4873,
D(12) => N4872, D(11) => N4871, D(10) => N4870, D(9)
=> N4869, D(8) => N4868, D(7) => N4867, D(6) =>
N4866, D(5) => N4865, D(4) => N4864, D(3) => N4863,
D(2) => N4862, D(1) => N4861, D(0) => N4860, Q(31)
=> PORT_ALU_31_port, Q(30) => PORT_ALU_30_port,
Q(29) => PORT_ALU_29_port, Q(28) => PORT_ALU_28_port
, Q(27) => PORT_ALU_27_port, Q(26) =>
PORT_ALU_26_port, Q(25) => PORT_ALU_25_port, Q(24)
=> PORT_ALU_24_port, Q(23) => PORT_ALU_23_port,
Q(22) => PORT_ALU_22_port, Q(21) => PORT_ALU_21_port
, Q(20) => PORT_ALU_20_port, Q(19) =>
PORT_ALU_19_port, Q(18) => PORT_ALU_18_port, Q(17)
=> PORT_ALU_17_port, Q(16) => PORT_ALU_16_port,
Q(15) => PORT_ALU_15_port, Q(14) => PORT_ALU_14_port
, Q(13) => PORT_ALU_13_port, Q(12) =>
PORT_ALU_12_port, Q(11) => PORT_ALU_11_port, Q(10)
=> PORT_ALU_10_port, Q(9) => PORT_ALU_9_port, Q(8)
=> PORT_ALU_8_port, Q(7) => PORT_ALU_7_port, Q(6) =>
PORT_ALU_6_port, Q(5) => PORT_ALU_5_port, Q(4) =>
PORT_ALU_4_port, Q(3) => PORT_ALU_3_port, Q(2) =>
PORT_ALU_2_port, Q(1) => PORT_ALU_1_port, Q(0) =>
PORT_ALU_0_port);
EX_MEM_INSTR_REG_instance : register_generic_N32_4 port map( CK => CLOCK,
RESET => RESET, ENABLE => n686, D(31) =>
EX_INSTR_31_port, D(30) => EX_INSTR_30_port, D(29)
=> EX_INSTR_29_port, D(28) => EX_INSTR_28_port,
D(27) => EX_INSTR_27_port, D(26) => EX_INSTR_26_port
, D(25) => EX_INSTR_25_port, D(24) =>
EX_INSTR_24_port, D(23) => EX_INSTR_23_port, D(22)
=> EX_INSTR_22_port, D(21) => EX_INSTR_21_port,
D(20) => EX_INSTR_20_port, D(19) => EX_INSTR_19_port
, D(18) => EX_INSTR_18_port, D(17) =>
EX_INSTR_17_port, D(16) => EX_INSTR_16_port, D(15)
=> EX_INSTR_15_port, D(14) => EX_INSTR_14_port,
D(13) => EX_INSTR_13_port, D(12) => EX_INSTR_12_port
, D(11) => EX_INSTR_11_port, D(10) =>
EX_INSTR_10_port, D(9) => EX_INSTR_9_port, D(8) =>
EX_INSTR_8_port, D(7) => EX_INSTR_7_port, D(6) =>
EX_INSTR_6_port, D(5) => EX_INSTR_5_port, D(4) =>
EX_INSTR_4_port, D(3) => EX_INSTR_3_port, D(2) =>
EX_INSTR_2_port, D(1) => EX_INSTR_1_port, D(0) =>
EX_INSTR_0_port, Q(31) => MEM_INSTR_31_port, Q(30)
=> MEM_INSTR_30_port, Q(29) => MEM_INSTR_29_port,
Q(28) => MEM_INSTR_28_port, Q(27) =>
MEM_INSTR_27_port, Q(26) => MEM_INSTR_26_port, Q(25)
=> MEM_INSTR_25_port, Q(24) => MEM_INSTR_24_port,
Q(23) => MEM_INSTR_23_port, Q(22) =>
MEM_INSTR_22_port, Q(21) => MEM_INSTR_21_port, Q(20)
=> MEM_INSTR_20_port, Q(19) => MEM_INSTR_19_port,
Q(18) => MEM_INSTR_18_port, Q(17) =>
MEM_INSTR_17_port, Q(16) => MEM_INSTR_16_port, Q(15)
=> MEM_INSTR_15_port, Q(14) => MEM_INSTR_14_port,
Q(13) => MEM_INSTR_13_port, Q(12) =>
MEM_INSTR_12_port, Q(11) => MEM_INSTR_11_port, Q(10)
=> MEM_INSTR_10_port, Q(9) => MEM_INSTR_9_port, Q(8)
=> MEM_INSTR_8_port, Q(7) => MEM_INSTR_7_port, Q(6)
=> MEM_INSTR_6_port, Q(5) => MEM_INSTR_5_port, Q(4)
=> MEM_INSTR_4_port, Q(3) => MEM_INSTR_3_port, Q(2)
=> MEM_INSTR_2_port, Q(1) => MEM_INSTR_1_port, Q(0)
=> MEM_INSTR_0_port);
MEM_WB_DATA_RAM_REG_instance : register_generic_N32_3 port map( CK => CLOCK,
RESET => RESET, ENABLE => X_Logic1_port, D(31) =>
PORT_DATA_RAM(31), D(30) => PORT_DATA_RAM(30), D(29)
=> PORT_DATA_RAM(29), D(28) => PORT_DATA_RAM(28),
D(27) => PORT_DATA_RAM(27), D(26) =>
PORT_DATA_RAM(26), D(25) => PORT_DATA_RAM(25), D(24)
=> PORT_DATA_RAM(24), D(23) => PORT_DATA_RAM(23),
D(22) => PORT_DATA_RAM(22), D(21) =>
PORT_DATA_RAM(21), D(20) => PORT_DATA_RAM(20), D(19)
=> PORT_DATA_RAM(19), D(18) => PORT_DATA_RAM(18),
D(17) => PORT_DATA_RAM(17), D(16) =>
PORT_DATA_RAM(16), D(15) => PORT_DATA_RAM(15), D(14)
=> PORT_DATA_RAM(14), D(13) => PORT_DATA_RAM(13),
D(12) => PORT_DATA_RAM(12), D(11) =>
PORT_DATA_RAM(11), D(10) => PORT_DATA_RAM(10), D(9)
=> PORT_DATA_RAM(9), D(8) => PORT_DATA_RAM(8), D(7)
=> PORT_DATA_RAM(7), D(6) => PORT_DATA_RAM(6), D(5)
=> PORT_DATA_RAM(5), D(4) => PORT_DATA_RAM(4), D(3)
=> PORT_DATA_RAM(3), D(2) => PORT_DATA_RAM(2), D(1)
=> PORT_DATA_RAM(1), D(0) => PORT_DATA_RAM(0), Q(31)
=> WB_DATA_RAM_31_port, Q(30) => WB_DATA_RAM_30_port
, Q(29) => WB_DATA_RAM_29_port, Q(28) =>
WB_DATA_RAM_28_port, Q(27) => WB_DATA_RAM_27_port,
Q(26) => WB_DATA_RAM_26_port, Q(25) =>
WB_DATA_RAM_25_port, Q(24) => WB_DATA_RAM_24_port,
Q(23) => WB_DATA_RAM_23_port, Q(22) =>
WB_DATA_RAM_22_port, Q(21) => WB_DATA_RAM_21_port,
Q(20) => WB_DATA_RAM_20_port, Q(19) =>
WB_DATA_RAM_19_port, Q(18) => WB_DATA_RAM_18_port,
Q(17) => WB_DATA_RAM_17_port, Q(16) =>
WB_DATA_RAM_16_port, Q(15) => WB_DATA_RAM_15_port,
Q(14) => WB_DATA_RAM_14_port, Q(13) =>
WB_DATA_RAM_13_port, Q(12) => WB_DATA_RAM_12_port,
Q(11) => WB_DATA_RAM_11_port, Q(10) =>
WB_DATA_RAM_10_port, Q(9) => WB_DATA_RAM_9_port,
Q(8) => WB_DATA_RAM_8_port, Q(7) =>
WB_DATA_RAM_7_port, Q(6) => WB_DATA_RAM_6_port, Q(5)
=> WB_DATA_RAM_5_port, Q(4) => WB_DATA_RAM_4_port,
Q(3) => WB_DATA_RAM_3_port, Q(2) =>
WB_DATA_RAM_2_port, Q(1) => WB_DATA_RAM_1_port, Q(0)
=> WB_DATA_RAM_0_port);
MEM_WB_ALU_REG_instance : register_generic_N32_2 port map( CK => CLOCK,
RESET => RESET, ENABLE => X_Logic1_port, D(31) =>
PORT_ALU_31_port, D(30) => PORT_ALU_30_port, D(29)
=> PORT_ALU_29_port, D(28) => PORT_ALU_28_port,
D(27) => PORT_ALU_27_port, D(26) => PORT_ALU_26_port
, D(25) => PORT_ALU_25_port, D(24) =>
PORT_ALU_24_port, D(23) => PORT_ALU_23_port, D(22)
=> PORT_ALU_22_port, D(21) => PORT_ALU_21_port,
D(20) => PORT_ALU_20_port, D(19) => PORT_ALU_19_port
, D(18) => PORT_ALU_18_port, D(17) =>
PORT_ALU_17_port, D(16) => PORT_ALU_16_port, D(15)
=> PORT_ALU_15_port, D(14) => PORT_ALU_14_port,
D(13) => PORT_ALU_13_port, D(12) => PORT_ALU_12_port
, D(11) => PORT_ALU_11_port, D(10) =>
PORT_ALU_10_port, D(9) => PORT_ALU_9_port, D(8) =>
PORT_ALU_8_port, D(7) => PORT_ALU_7_port, D(6) =>
PORT_ALU_6_port, D(5) => PORT_ALU_5_port, D(4) =>
PORT_ALU_4_port, D(3) => PORT_ALU_3_port, D(2) =>
PORT_ALU_2_port, D(1) => PORT_ALU_1_port, D(0) =>
PORT_ALU_0_port, Q(31) => WB_ALU_31_port, Q(30) =>
WB_ALU_30_port, Q(29) => WB_ALU_29_port, Q(28) =>
WB_ALU_28_port, Q(27) => WB_ALU_27_port, Q(26) =>
WB_ALU_26_port, Q(25) => WB_ALU_25_port, Q(24) =>
WB_ALU_24_port, Q(23) => WB_ALU_23_port, Q(22) =>
WB_ALU_22_port, Q(21) => WB_ALU_21_port, Q(20) =>
WB_ALU_20_port, Q(19) => WB_ALU_19_port, Q(18) =>
WB_ALU_18_port, Q(17) => WB_ALU_17_port, Q(16) =>
WB_ALU_16_port, Q(15) => WB_ALU_15_port, Q(14) =>
WB_ALU_14_port, Q(13) => WB_ALU_13_port, Q(12) =>
WB_ALU_12_port, Q(11) => WB_ALU_11_port, Q(10) =>
WB_ALU_10_port, Q(9) => WB_ALU_9_port, Q(8) =>
WB_ALU_8_port, Q(7) => WB_ALU_7_port, Q(6) =>
WB_ALU_6_port, Q(5) => WB_ALU_5_port, Q(4) =>
WB_ALU_4_port, Q(3) => WB_ALU_3_port, Q(2) =>
WB_ALU_2_port, Q(1) => WB_ALU_1_port, Q(0) =>
WB_ALU_0_port);
MEM_WB_INSTR_REG_instance : register_generic_N32_1 port map( CK => CLOCK,
RESET => RESET, ENABLE => X_Logic1_port, D(31) =>
MEM_INSTR_31_port, D(30) => MEM_INSTR_30_port, D(29)
=> MEM_INSTR_29_port, D(28) => MEM_INSTR_28_port,
D(27) => MEM_INSTR_27_port, D(26) =>
MEM_INSTR_26_port, D(25) => MEM_INSTR_25_port, D(24)
=> MEM_INSTR_24_port, D(23) => MEM_INSTR_23_port,
D(22) => MEM_INSTR_22_port, D(21) =>
MEM_INSTR_21_port, D(20) => MEM_INSTR_20_port, D(19)
=> MEM_INSTR_19_port, D(18) => MEM_INSTR_18_port,
D(17) => MEM_INSTR_17_port, D(16) =>
MEM_INSTR_16_port, D(15) => MEM_INSTR_15_port, D(14)
=> MEM_INSTR_14_port, D(13) => MEM_INSTR_13_port,
D(12) => MEM_INSTR_12_port, D(11) =>
MEM_INSTR_11_port, D(10) => MEM_INSTR_10_port, D(9)
=> MEM_INSTR_9_port, D(8) => MEM_INSTR_8_port, D(7)
=> MEM_INSTR_7_port, D(6) => MEM_INSTR_6_port, D(5)
=> MEM_INSTR_5_port, D(4) => MEM_INSTR_4_port, D(3)
=> MEM_INSTR_3_port, D(2) => MEM_INSTR_2_port, D(1)
=> MEM_INSTR_1_port, D(0) => MEM_INSTR_0_port, Q(31)
=> WB_INSTR_31, Q(30) => WB_INSTR_30, Q(29) =>
WB_INSTR_29, Q(28) => WB_INSTR_28, Q(27) =>
WB_INSTR_27, Q(26) => WB_INSTR_26, Q(25) => net56079
, Q(24) => net56080, Q(23) => net56081, Q(22) =>
net56082, Q(21) => net56083, Q(20) =>
WB_INSTR_20_port, Q(19) => WB_INSTR_19_port, Q(18)
=> WB_INSTR_18_port, Q(17) => WB_INSTR_17_port,
Q(16) => WB_INSTR_16_port, Q(15) => WB_INSTR_15_port
, Q(14) => WB_INSTR_14_port, Q(13) =>
WB_INSTR_13_port, Q(12) => WB_INSTR_12_port, Q(11)
=> WB_INSTR_11_port, Q(10) => WB_INSTR_10_port, Q(9)
=> WB_INSTR_9_port, Q(8) => WB_INSTR_8_port, Q(7) =>
WB_INSTR_7_port, Q(6) => WB_INSTR_6_port, Q(5) =>
WB_INSTR_5_port, Q(4) => WB_INSTR_4_port, Q(3) =>
WB_INSTR_3_port, Q(2) => WB_INSTR_2_port, Q(1) =>
WB_INSTR_1_port, Q(0) => WB_INSTR_0_port);
add_502 : DLX_DW01_add_0 port map( A(31) => PORT_PC_31_port, A(30) =>
PORT_PC_30_port, A(29) => PORT_PC_29_port, A(28) =>
PORT_PC_28_port, A(27) => PORT_PC_27_port, A(26) =>
PORT_PC_26_port, A(25) => PORT_PC_25_port, A(24) =>
PORT_PC_24_port, A(23) => PORT_PC_23_port, A(22) =>
PORT_PC_22_port, A(21) => PORT_PC_21_port, A(20) =>
PORT_PC_20_port, A(19) => PORT_PC_19_port, A(18) =>
PORT_PC_18_port, A(17) => PORT_PC_17_port, A(16) =>
PORT_PC_16_port, A(15) => PORT_PC_15_port, A(14) =>
PORT_PC_14_port, A(13) => PORT_PC_13_port, A(12) =>
PORT_PC_12_port, A(11) => PORT_PC_11_port, A(10) =>
PORT_PC_10_port, A(9) => PORT_PC_9_port, A(8) =>
PORT_PC_8_port, A(7) => PORT_PC_7_port, A(6) =>
PORT_PC_6_port, A(5) => PORT_PC_5_port, A(4) =>
PORT_PC_4_port, A(3) => PORT_PC_3_port, A(2) =>
PORT_PC_2_port, A(1) => PORT_PC_1_port, A(0) =>
PORT_PC_0_port, B(31) => n25, B(30) => n25, B(29) =>
n25, B(28) => n25, B(27) => n25, B(26) => n25, B(25)
=> n25, B(24) => n25, B(23) => n25, B(22) => n25,
B(21) => n25, B(20) => n25, B(19) => n25, B(18) =>
n25, B(17) => n25, B(16) => n25, B(15) => n25, B(14)
=> n25, B(13) => n25, B(12) => n25, B(11) => n25,
B(10) => n25, B(9) => n25, B(8) => n25, B(7) => n25,
B(6) => n25, B(5) => n25, B(4) => n25, B(3) => n25,
B(2) => X_Logic1_port, B(1) => X_Logic0_port, B(0)
=> X_Logic0_port, CI => n25, SUM(31) =>
IF_PC_INC_31_port, SUM(30) => IF_PC_INC_30_port,
SUM(29) => IF_PC_INC_29_port, SUM(28) =>
IF_PC_INC_28_port, SUM(27) => IF_PC_INC_27_port,
SUM(26) => IF_PC_INC_26_port, SUM(25) =>
IF_PC_INC_25_port, SUM(24) => IF_PC_INC_24_port,
SUM(23) => IF_PC_INC_23_port, SUM(22) =>
IF_PC_INC_22_port, SUM(21) => IF_PC_INC_21_port,
SUM(20) => IF_PC_INC_20_port, SUM(19) =>
IF_PC_INC_19_port, SUM(18) => IF_PC_INC_18_port,
SUM(17) => IF_PC_INC_17_port, SUM(16) =>
IF_PC_INC_16_port, SUM(15) => IF_PC_INC_15_port,
SUM(14) => IF_PC_INC_14_port, SUM(13) =>
IF_PC_INC_13_port, SUM(12) => IF_PC_INC_12_port,
SUM(11) => IF_PC_INC_11_port, SUM(10) =>
IF_PC_INC_10_port, SUM(9) => IF_PC_INC_9_port,
SUM(8) => IF_PC_INC_8_port, SUM(7) =>
IF_PC_INC_7_port, SUM(6) => IF_PC_INC_6_port, SUM(5)
=> IF_PC_INC_5_port, SUM(4) => IF_PC_INC_4_port,
SUM(3) => IF_PC_INC_3_port, SUM(2) =>
IF_PC_INC_2_port, SUM(1) => IF_PC_INC_1_port, SUM(0)
=> IF_PC_INC_0_port, CO => net93300);
add_545 : DLX_DW01_add_1 port map( A(31) => ID_PC_31_port, A(30) =>
ID_PC_30_port, A(29) => ID_PC_29_port, A(28) =>
ID_PC_28_port, A(27) => ID_PC_27_port, A(26) =>
ID_PC_26_port, A(25) => ID_PC_25_port, A(24) =>
ID_PC_24_port, A(23) => ID_PC_23_port, A(22) =>
ID_PC_22_port, A(21) => ID_PC_21_port, A(20) =>
ID_PC_20_port, A(19) => ID_PC_19_port, A(18) =>
ID_PC_18_port, A(17) => ID_PC_17_port, A(16) =>
ID_PC_16_port, A(15) => ID_PC_15_port, A(14) =>
ID_PC_14_port, A(13) => ID_PC_13_port, A(12) =>
ID_PC_12_port, A(11) => ID_PC_11_port, A(10) =>
ID_PC_10_port, A(9) => ID_PC_9_port, A(8) =>
ID_PC_8_port, A(7) => ID_PC_7_port, A(6) =>
ID_PC_6_port, A(5) => ID_PC_5_port, A(4) =>
ID_PC_4_port, A(3) => ID_PC_3_port, A(2) =>
ID_PC_2_port, A(1) => ID_PC_1_port, A(0) =>
ID_PC_0_port, B(31) => ID_IMM16_SHL2_31_port, B(30)
=> ID_IMM16_SHL2_30_port, B(29) =>
ID_IMM16_SHL2_29_port, B(28) =>
ID_IMM16_SHL2_28_port, B(27) =>
ID_IMM16_SHL2_27_port, B(26) =>
ID_IMM16_SHL2_26_port, B(25) =>
ID_IMM16_SHL2_25_port, B(24) =>
ID_IMM16_SHL2_24_port, B(23) =>
ID_IMM16_SHL2_23_port, B(22) =>
ID_IMM16_SHL2_22_port, B(21) =>
ID_IMM16_SHL2_21_port, B(20) =>
ID_IMM16_SHL2_20_port, B(19) =>
ID_IMM16_SHL2_19_port, B(18) =>
ID_IMM16_SHL2_18_port, B(17) =>
ID_IMM16_SHL2_17_port, B(16) =>
ID_IMM16_SHL2_16_port, B(15) =>
ID_IMM16_SHL2_15_port, B(14) =>
ID_IMM16_SHL2_14_port, B(13) =>
ID_IMM16_SHL2_13_port, B(12) =>
ID_IMM16_SHL2_12_port, B(11) =>
ID_IMM16_SHL2_11_port, B(10) =>
ID_IMM16_SHL2_10_port, B(9) => ID_IMM16_SHL2_9_port,
B(8) => ID_IMM16_SHL2_8_port, B(7) =>
ID_IMM16_SHL2_7_port, B(6) => ID_IMM16_SHL2_6_port,
B(5) => ID_IMM16_SHL2_5_port, B(4) =>
ID_IMM16_SHL2_4_port, B(3) => ID_IMM16_SHL2_3_port,
B(2) => ID_IMM16_SHL2_2_port, B(1) =>
ID_IMM16_SHL2_1_port, B(0) => ID_IMM16_SHL2_0_port,
CI => n26, SUM(31) => ID_PC_SUM_31_port, SUM(30) =>
ID_PC_SUM_30_port, SUM(29) => ID_PC_SUM_29_port,
SUM(28) => ID_PC_SUM_28_port, SUM(27) =>
ID_PC_SUM_27_port, SUM(26) => ID_PC_SUM_26_port,
SUM(25) => ID_PC_SUM_25_port, SUM(24) =>
ID_PC_SUM_24_port, SUM(23) => ID_PC_SUM_23_port,
SUM(22) => ID_PC_SUM_22_port, SUM(21) =>
ID_PC_SUM_21_port, SUM(20) => ID_PC_SUM_20_port,
SUM(19) => ID_PC_SUM_19_port, SUM(18) =>
ID_PC_SUM_18_port, SUM(17) => ID_PC_SUM_17_port,
SUM(16) => ID_PC_SUM_16_port, SUM(15) =>
ID_PC_SUM_15_port, SUM(14) => ID_PC_SUM_14_port,
SUM(13) => ID_PC_SUM_13_port, SUM(12) =>
ID_PC_SUM_12_port, SUM(11) => ID_PC_SUM_11_port,
SUM(10) => ID_PC_SUM_10_port, SUM(9) =>
ID_PC_SUM_9_port, SUM(8) => ID_PC_SUM_8_port, SUM(7)
=> ID_PC_SUM_7_port, SUM(6) => ID_PC_SUM_6_port,
SUM(5) => ID_PC_SUM_5_port, SUM(4) =>
ID_PC_SUM_4_port, SUM(3) => ID_PC_SUM_3_port, SUM(2)
=> ID_PC_SUM_2_port, SUM(1) => ID_PC_SUM_1_port,
SUM(0) => ID_PC_SUM_0_port, CO => net93299);
ID_HAZARD_MEM_reg : TLATX1 port map( G => N4716, D => N4710, Q => n696, QN
=> n319);
ID_HAZARD_WB_reg : TLATX1 port map( G => N4717, D => N4708, Q => n695, QN =>
n320);
ID_HAZARD_EX_reg : TLATX1 port map( G => N4717, D => N4712, Q => n694, QN =>
n321);
U654 : AOI22XL port map( A0 => EX_IMM16_EXT_0_port, A1 => n858, B0 =>
EX_REGB_0_port, B1 => n859, Y => n687);
U655 : AOI22XL port map( A0 => EX_IMM16_EXT_1_port, A1 => n858, B0 =>
EX_REGB_1_port, B1 => n859, Y => n691);
U656 : AOI22XL port map( A0 => EX_IMM16_EXT_2_port, A1 => n858, B0 =>
EX_REGB_2_port, B1 => n859, Y => n689);
U657 : NOR2BX4 port map( AN => n864, B => n865, Y => n863);
U658 : AOI2BB1XL port map( A0N => n917, A1N => n1073, B0 => n918, Y => n864)
;
U659 : MXI2X2 port map( A => n1088, B => n1089, S0 => n1031, Y => EX_ADD_SUB
);
U660 : NAND3X2 port map( A => n321, B => n320, C => n319, Y => n1020);
U661 : NAND3X2 port map( A => n852, B => n853, C => WB_INSTR_31, Y => n821);
U662 : NOR3X2 port map( A => n737_port, B => n738_port, C => n736_port, Y =>
n735_port);
U663 : NOR3X2 port map( A => n803, B => ID_INSTR_28, C => n804, Y =>
n737_port);
U664 : OAI31X4 port map( A0 => n1041, A1 => EX_INSTR_27_port, A2 => n1058,
B0 => n1042, Y => EX_LOGIC_CW_3_port);
U665 : NOR4X8 port map( A => n865, B => n1071, C => EX_INSTR_28_port, D =>
EX_INSTR_31_port, Y => n857);
U666 : INVX5 port map( A => n687, Y => n688);
U667 : INVX5 port map( A => n689, Y => n690);
U668 : NAND2X5 port map( A => n860, B => n861, Y => N4830);
U669 : INVX6 port map( A => n691, Y => n692);
U670 : NOR2XL port map( A => n820, B => n821, Y => n719);
U671 : INVXL port map( A => n1020, Y => n1028);
U672 : AOI211XL port map( A0 => n864, A1 => n865, B0 => n1031, C0 => n857, Y
=> n1072);
U673 : NOR2XL port map( A => n714, B => n1020, Y => ID_INSTR_AFTER_CU_7_port
);
U674 : NOR2XL port map( A => n712, B => n1020, Y => ID_INSTR_AFTER_CU_8_port
);
U675 : NOR2XL port map( A => n713, B => n1020, Y => ID_INSTR_AFTER_CU_9_port
);
U676 : NOR2XL port map( A => n901, B => n1020, Y =>
ID_INSTR_AFTER_CU_16_port);
U677 : NOR2XL port map( A => n902, B => n1020, Y =>
ID_INSTR_AFTER_CU_17_port);
U678 : NOR2XL port map( A => n960, B => n1020, Y =>
ID_INSTR_AFTER_CU_20_port);
U679 : NOR2XL port map( A => n985, B => n1020, Y =>
ID_INSTR_AFTER_CU_21_port);
U680 : NOR2XL port map( A => n897, B => n1020, Y =>
ID_INSTR_AFTER_CU_25_port);
U681 : NOR2XL port map( A => n704, B => n1020, Y =>
ID_INSTR_AFTER_CU_27_port);
U682 : NOR2XL port map( A => n699, B => n1020, Y =>
ID_INSTR_AFTER_CU_29_port);
U683 : NOR2XL port map( A => n987, B => n1020, Y =>
ID_INSTR_AFTER_CU_31_port);
U684 : MX2XL port map( A => EX_ALU_OUT_2_port, B => EX_MULT_OUT_2_port, S0
=> n857, Y => N4862);
U685 : MX2XL port map( A => EX_ALU_OUT_4_port, B => EX_MULT_OUT_4_port, S0
=> n857, Y => N4864);
U686 : MX2XL port map( A => EX_ALU_OUT_0_port, B => EX_MULT_OUT_0_port, S0
=> n857, Y => N4860);
U687 : MX2XL port map( A => EX_ALU_OUT_1_port, B => EX_MULT_OUT_1_port, S0
=> n857, Y => N4861);
U688 : MX2XL port map( A => EX_ALU_OUT_3_port, B => EX_MULT_OUT_3_port, S0
=> n857, Y => N4863);
U689 : MX2XL port map( A => EX_ALU_OUT_5_port, B => EX_MULT_OUT_5_port, S0
=> n857, Y => N4865);
U690 : MX2XL port map( A => EX_ALU_OUT_6_port, B => EX_MULT_OUT_6_port, S0
=> n857, Y => N4866);
U691 : MX2XL port map( A => EX_ALU_OUT_7_port, B => EX_MULT_OUT_7_port, S0
=> n857, Y => N4867);
U692 : MX2XL port map( A => EX_ALU_OUT_8_port, B => EX_MULT_OUT_8_port, S0
=> n857, Y => N4868);
U693 : MX2XL port map( A => EX_ALU_OUT_9_port, B => EX_MULT_OUT_9_port, S0
=> n857, Y => N4869);
U694 : MX2XL port map( A => EX_ALU_OUT_10_port, B => EX_MULT_OUT_10_port, S0
=> n857, Y => N4870);
U695 : MX2XL port map( A => EX_ALU_OUT_11_port, B => EX_MULT_OUT_11_port, S0
=> n857, Y => N4871);
U696 : MX2XL port map( A => EX_ALU_OUT_12_port, B => EX_MULT_OUT_12_port, S0
=> n857, Y => N4872);
U697 : MX2XL port map( A => EX_ALU_OUT_13_port, B => EX_MULT_OUT_13_port, S0
=> n857, Y => N4873);
U698 : MX2XL port map( A => EX_ALU_OUT_14_port, B => EX_MULT_OUT_14_port, S0
=> n857, Y => N4874);
U699 : MX2XL port map( A => EX_ALU_OUT_15_port, B => EX_MULT_OUT_15_port, S0
=> n857, Y => N4875);
U700 : MX2XL port map( A => EX_ALU_OUT_16_port, B => EX_MULT_OUT_16_port, S0
=> n857, Y => N4876);
U701 : MX2XL port map( A => EX_ALU_OUT_17_port, B => EX_MULT_OUT_17_port, S0
=> n857, Y => N4877);
U702 : MX2XL port map( A => EX_ALU_OUT_18_port, B => EX_MULT_OUT_18_port, S0
=> n857, Y => N4878);
U703 : MX2XL port map( A => EX_ALU_OUT_19_port, B => EX_MULT_OUT_19_port, S0
=> n857, Y => N4879);
U704 : MX2XL port map( A => EX_ALU_OUT_20_port, B => EX_MULT_OUT_20_port, S0
=> n857, Y => N4880);
U705 : MX2XL port map( A => EX_ALU_OUT_21_port, B => EX_MULT_OUT_21_port, S0
=> n857, Y => N4881);
U706 : MX2XL port map( A => EX_ALU_OUT_22_port, B => EX_MULT_OUT_22_port, S0
=> n857, Y => N4882);
U707 : MX2XL port map( A => EX_ALU_OUT_23_port, B => EX_MULT_OUT_23_port, S0
=> n857, Y => N4883);
U708 : MX2XL port map( A => EX_ALU_OUT_24_port, B => EX_MULT_OUT_24_port, S0
=> n857, Y => N4884);
U709 : MX2XL port map( A => EX_ALU_OUT_25_port, B => EX_MULT_OUT_25_port, S0
=> n857, Y => N4885);
U710 : MX2XL port map( A => EX_ALU_OUT_26_port, B => EX_MULT_OUT_26_port, S0
=> n857, Y => N4886);
U711 : MX2XL port map( A => EX_ALU_OUT_27_port, B => EX_MULT_OUT_27_port, S0
=> n857, Y => N4887);
U712 : MX2XL port map( A => EX_ALU_OUT_28_port, B => EX_MULT_OUT_28_port, S0
=> n857, Y => N4888);
U713 : MX2XL port map( A => EX_ALU_OUT_29_port, B => EX_MULT_OUT_29_port, S0
=> n857, Y => N4889);
U714 : MX2XL port map( A => EX_ALU_OUT_30_port, B => EX_MULT_OUT_30_port, S0
=> n857, Y => N4890);
U715 : NAND3BXL port map( AN => EX_LOGIC_CW_3_port, B => n1040, C => n1052,
Y => EX_ALU_SEL_1_port);
U716 : NAND2XL port map( A => WB_DATA_EXT_16_13_port, B => n720, Y => n828);
U717 : NAND2XL port map( A => WB_DATA_EXT_16_14_port, B => n720, Y => n826);
U718 : NAND2BX2 port map( AN => n1039, B => n1040, Y => EX_LOGIC_CW_2_port);
U719 : CLKAND2X2 port map( A => IF_STALL_SEL, B => n1020, Y => n693);
U720 : MX2XL port map( A => EX_REGA_31_port, B => EX_PC_31_port, S0 => n863,
Y => N4749);
U721 : MX2XL port map( A => EX_REGA_30_port, B => EX_PC_30_port, S0 => n863,
Y => N4748);
U722 : MX2XL port map( A => EX_REGA_18_port, B => EX_PC_18_port, S0 => n863,
Y => N4736);
U723 : MX2XL port map( A => EX_REGA_20_port, B => EX_PC_20_port, S0 => n863,
Y => N4738);
U724 : MXI2XL port map( A => WB_DATA_RAM_7_port, B => WB_ALU_7_port, S0 =>
n821, Y => n839);
U725 : MXI2XL port map( A => WB_DATA_RAM_8_port, B => WB_ALU_8_port, S0 =>
n821, Y => n837);
U726 : MXI2XL port map( A => WB_DATA_RAM_9_port, B => WB_ALU_9_port, S0 =>
n821, Y => n835);
U727 : MXI2XL port map( A => WB_DATA_RAM_10_port, B => WB_ALU_10_port, S0 =>
n821, Y => n833);
U728 : MXI2XL port map( A => WB_DATA_RAM_11_port, B => WB_ALU_11_port, S0 =>
n821, Y => n831);
U729 : MXI2XL port map( A => WB_DATA_RAM_12_port, B => WB_ALU_12_port, S0 =>
n821, Y => n829);
U730 : MXI2XL port map( A => WB_DATA_RAM_13_port, B => WB_ALU_13_port, S0 =>
n821, Y => n827);
U731 : MXI2XL port map( A => WB_DATA_RAM_14_port, B => WB_ALU_14_port, S0 =>
n821, Y => n825);
U732 : MXI2XL port map( A => WB_DATA_RAM_15_port, B => WB_ALU_15_port, S0 =>
n821, Y => n823);
U733 : MX2XL port map( A => EX_REGA_19_port, B => EX_PC_19_port, S0 => n863,
Y => N4737);
U734 : MX2XL port map( A => WB_DATA_RAM_0_port, B => WB_ALU_0_port, S0 =>
n821, Y => N6134);
U735 : MX2XL port map( A => WB_DATA_RAM_1_port, B => WB_ALU_1_port, S0 =>
n821, Y => N6135);
U736 : MX2XL port map( A => WB_DATA_RAM_2_port, B => WB_ALU_2_port, S0 =>
n821, Y => N6136);
U737 : MX2XL port map( A => WB_DATA_RAM_3_port, B => WB_ALU_3_port, S0 =>
n821, Y => N6137);
U738 : MX2XL port map( A => WB_DATA_RAM_4_port, B => WB_ALU_4_port, S0 =>
n821, Y => N6138);
U739 : MX2XL port map( A => WB_DATA_RAM_5_port, B => WB_ALU_5_port, S0 =>
n821, Y => N6139);
U740 : MX2XL port map( A => WB_DATA_RAM_6_port, B => WB_ALU_6_port, S0 =>
n821, Y => N6140);
U741 : INVX8 port map( A => n693, Y => n697);
U742 : OAI221X1 port map( A0 => n698, A1 => n699, B0 => n700, B1 => n701, C0
=> n702, Y => RF_RD2);
U743 : AOI31X1 port map( A0 => n703, A1 => n704, A2 => n705, B0 => n706, Y
=> n698);
U744 : CLKNAND2X2 port map( A => n707, B => n702, Y => RF_RD1);
U745 : AOI21X1 port map( A0 => n708, A1 => n709, B0 => n710, Y => n702);
U746 : NOR4X1 port map( A => n711, B => ID_INSTR_4_port, C =>
ID_INSTR_6_port, D => ID_INSTR_5_port, Y => n709);
U747 : NAND3XL port map( A => n712, B => n713, C => n714, Y => n711);
U748 : NOR4X1 port map( A => n715, B => N4717, C => ID_INSTR_10_port, D =>
ID_INSTR_0_port, Y => n708);
U749 : NAND3XL port map( A => ID_INSTR_2_port, B => ID_INSTR_1_port, C =>
ID_INSTR_3_port, Y => n715);
U750 : OAI2B11X1 port map( A1N => WB_ALU_31_port, A0 => n716, B0 => n717, C0
=> n718, Y => RF_DATAIN(31));
U751 : AOI22XL port map( A0 => WB_DATA_RAM_31_port, A1 => n719, B0 =>
WB_DATA_EXT_16_31_port, B1 => n720, Y => n718);
U752 : AOI211X1 port map( A0 => MEM_INSTR_29_port, A1 => MEM_INSTR_28_port,
B0 => n721, C0 => n722, Y => PORT_SIZE(1));
U753 : CLKNAND2X2 port map( A => n723, B => n724, Y => n721);
U754 : NOR3X1 port map( A => n725, B => n722, C => n723, Y => PORT_SIZE(0));
U755 : CLKINVX1 port map( A => n726, Y => n722);
U756 : NAND3XL port map( A => n724, B => n727, C => MEM_INSTR_28_port, Y =>
n725);
U757 : CLKINVX1 port map( A => MEM_INSTR_27_port, Y => n724);
U758 : CLKINVX1 port map( A => n728, Y => PORT_R_W);
U759 : CLKNAND2X2 port map( A => n728, B => n729, Y => PORT_EN);
U760 : NAND3XL port map( A => n726, B => n727, C => n730_port, Y => n728);
U761 : XOR2X1 port map( A => n731_port, B => MEM_INSTR_27_port, Y =>
n730_port);
U762 : CLKNAND2X2 port map( A => MEM_INSTR_26_port, B => n732_port, Y =>
n731_port);
U763 : CLKINVX1 port map( A => MEM_INSTR_29_port, Y => n727);
U764 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(31), B => n693, Y => N795);
U765 : NAND2BX1 port map( AN => PORT_INSTR_IRAM(30), B => n697, Y => N794);
U766 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(29), B => n693, Y => N793);
U767 : NAND2BX1 port map( AN => PORT_INSTR_IRAM(28), B => n697, Y => N792);
U768 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(27), B => n693, Y => N791);
U769 : NAND2BX1 port map( AN => PORT_INSTR_IRAM(26), B => n697, Y => N790);
U770 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(25), B => n693, Y => N789);
U771 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(24), B => n693, Y => N788);
U772 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(23), B => n693, Y => N787);
U773 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(22), B => n693, Y => N786);
U774 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(21), B => n693, Y => N785);
U775 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(20), B => n693, Y => N784);
U776 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(19), B => n693, Y => N783);
U777 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(18), B => n693, Y => N782);
U778 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(17), B => n693, Y => N781);
U779 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(16), B => n693, Y => N780);
U780 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(15), B => n693, Y => N779);
U781 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(14), B => n693, Y => N778);
U782 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(13), B => n693, Y => N777);
U783 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(12), B => n693, Y => N776);
U784 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(11), B => n693, Y => N775);
U785 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(10), B => n693, Y => N774);
U786 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(9), B => n693, Y => N773);
U787 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(8), B => n693, Y => N772);
U788 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(7), B => n693, Y => N771);
U789 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(6), B => n693, Y => N770);
U790 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(5), B => n693, Y => N769);
U791 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(4), B => n693, Y => N768);
U792 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(3), B => n693, Y => N767);
U793 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(2), B => n693, Y => N766);
U794 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(1), B => n693, Y => N765);
U795 : NOR2BX1 port map( AN => PORT_INSTR_IRAM(0), B => n693, Y => N764);
U796 : CLKNAND2X2 port map( A => n733_port, B => n734_port, Y => N761);
U797 : AOI22XL port map( A0 => RF_OUT1(31), A1 => n735_port, B0 =>
IF_PC_INC_31_port, B1 => n736_port, Y => n734_port);
U798 : AOI22XL port map( A0 => ID_PC_31_port, A1 => n737_port, B0 =>
ID_PC_SUM_31_port, B1 => n738_port, Y => n733_port);
U799 : CLKNAND2X2 port map( A => n739_port, B => n740_port, Y => N760);
U800 : AOI22XL port map( A0 => RF_OUT1(30), A1 => n735_port, B0 =>
IF_PC_INC_30_port, B1 => n736_port, Y => n740_port);
U801 : AOI22XL port map( A0 => ID_PC_30_port, A1 => n737_port, B0 =>
ID_PC_SUM_30_port, B1 => n738_port, Y => n739_port);
U802 : CLKNAND2X2 port map( A => n741_port, B => n742_port, Y => N759);
U803 : AOI22XL port map( A0 => RF_OUT1(29), A1 => n735_port, B0 =>
IF_PC_INC_29_port, B1 => n736_port, Y => n742_port);
U804 : AOI22XL port map( A0 => ID_PC_29_port, A1 => n737_port, B0 =>
ID_PC_SUM_29_port, B1 => n738_port, Y => n741_port);
U805 : CLKNAND2X2 port map( A => n743_port, B => n744_port, Y => N758);
U806 : AOI22XL port map( A0 => RF_OUT1(28), A1 => n735_port, B0 =>
IF_PC_INC_28_port, B1 => n736_port, Y => n744_port);
U807 : AOI22XL port map( A0 => ID_PC_28_port, A1 => n737_port, B0 =>
ID_PC_SUM_28_port, B1 => n738_port, Y => n743_port);
U808 : CLKNAND2X2 port map( A => n745_port, B => n746_port, Y => N757);
U809 : AOI22XL port map( A0 => RF_OUT1(27), A1 => n735_port, B0 =>
IF_PC_INC_27_port, B1 => n736_port, Y => n746_port);
U810 : AOI22XL port map( A0 => ID_PC_27_port, A1 => n737_port, B0 =>
ID_PC_SUM_27_port, B1 => n738_port, Y => n745_port);
U811 : CLKNAND2X2 port map( A => n747_port, B => n748_port, Y => N756);
U812 : AOI22XL port map( A0 => RF_OUT1(26), A1 => n735_port, B0 =>
IF_PC_INC_26_port, B1 => n736_port, Y => n748_port);
U813 : AOI22XL port map( A0 => ID_PC_26_port, A1 => n737_port, B0 =>
ID_PC_SUM_26_port, B1 => n738_port, Y => n747_port);
U814 : CLKNAND2X2 port map( A => n749_port, B => n750_port, Y => N755);
U815 : AOI22XL port map( A0 => RF_OUT1(25), A1 => n735_port, B0 =>
IF_PC_INC_25_port, B1 => n736_port, Y => n750_port);
U816 : AOI22XL port map( A0 => RF_ADD_RD1_4_port, A1 => n737_port, B0 =>
ID_PC_SUM_25_port, B1 => n738_port, Y => n749_port);
U817 : CLKNAND2X2 port map( A => n751_port, B => n752_port, Y => N754);
U818 : AOI22XL port map( A0 => RF_OUT1(24), A1 => n735_port, B0 =>
IF_PC_INC_24_port, B1 => n736_port, Y => n752_port);
U819 : AOI22XL port map( A0 => RF_ADD_RD1_3_port, A1 => n737_port, B0 =>
ID_PC_SUM_24_port, B1 => n738_port, Y => n751_port);
U820 : CLKNAND2X2 port map( A => n753_port, B => n754_port, Y => N753);
U821 : AOI22XL port map( A0 => RF_OUT1(23), A1 => n735_port, B0 =>
IF_PC_INC_23_port, B1 => n736_port, Y => n754_port);
U822 : AOI22XL port map( A0 => RF_ADD_RD1_2_port, A1 => n737_port, B0 =>
ID_PC_SUM_23_port, B1 => n738_port, Y => n753_port);
U823 : CLKNAND2X2 port map( A => n755_port, B => n756_port, Y => N752);
U824 : AOI22XL port map( A0 => RF_OUT1(22), A1 => n735_port, B0 =>
IF_PC_INC_22_port, B1 => n736_port, Y => n756_port);
U825 : AOI22XL port map( A0 => RF_ADD_RD1_1_port, A1 => n737_port, B0 =>
ID_PC_SUM_22_port, B1 => n738_port, Y => n755_port);
U826 : CLKNAND2X2 port map( A => n757_port, B => n758_port, Y => N751);
U827 : AOI22XL port map( A0 => RF_OUT1(21), A1 => n735_port, B0 =>
IF_PC_INC_21_port, B1 => n736_port, Y => n758_port);
U828 : AOI22XL port map( A0 => RF_ADD_RD1_0_port, A1 => n737_port, B0 =>
ID_PC_SUM_21_port, B1 => n738_port, Y => n757_port);
U829 : CLKNAND2X2 port map( A => n759_port, B => n760_port, Y => N750);
U830 : AOI22XL port map( A0 => RF_OUT1(20), A1 => n735_port, B0 =>
IF_PC_INC_20_port, B1 => n736_port, Y => n760_port);
U831 : AOI22XL port map( A0 => RF_ADD_RD2_4_port, A1 => n737_port, B0 =>
ID_PC_SUM_20_port, B1 => n738_port, Y => n759_port);
U832 : CLKNAND2X2 port map( A => n761_port, B => n762, Y => N749);
U833 : AOI22XL port map( A0 => RF_OUT1(19), A1 => n735_port, B0 =>
IF_PC_INC_19_port, B1 => n736_port, Y => n762);
U834 : AOI22XL port map( A0 => RF_ADD_RD2_3_port, A1 => n737_port, B0 =>
ID_PC_SUM_19_port, B1 => n738_port, Y => n761_port);
U835 : CLKNAND2X2 port map( A => n763, B => n764_port, Y => N748);
U836 : AOI22XL port map( A0 => RF_OUT1(18), A1 => n735_port, B0 =>
IF_PC_INC_18_port, B1 => n736_port, Y => n764_port);
U837 : AOI22XL port map( A0 => RF_ADD_RD2_2_port, A1 => n737_port, B0 =>
ID_PC_SUM_18_port, B1 => n738_port, Y => n763);
U838 : CLKNAND2X2 port map( A => n765_port, B => n766_port, Y => N747);
U839 : AOI22XL port map( A0 => RF_OUT1(17), A1 => n735_port, B0 =>
IF_PC_INC_17_port, B1 => n736_port, Y => n766_port);
U840 : AOI22XL port map( A0 => RF_ADD_RD2_1_port, A1 => n737_port, B0 =>
ID_PC_SUM_17_port, B1 => n738_port, Y => n765_port);
U841 : CLKNAND2X2 port map( A => n767_port, B => n768_port, Y => N746);
U842 : AOI22XL port map( A0 => RF_OUT1(16), A1 => n735_port, B0 =>
IF_PC_INC_16_port, B1 => n736_port, Y => n768_port);
U843 : AOI22XL port map( A0 => RF_ADD_RD2_0_port, A1 => n737_port, B0 =>
ID_PC_SUM_16_port, B1 => n738_port, Y => n767_port);
U844 : CLKNAND2X2 port map( A => n769_port, B => n770_port, Y => N745);
U845 : AOI22XL port map( A0 => RF_OUT1(15), A1 => n735_port, B0 =>
IF_PC_INC_15_port, B1 => n736_port, Y => n770_port);
U846 : AOI22XL port map( A0 => ID_INSTR_15_port, A1 => n737_port, B0 =>
ID_PC_SUM_15_port, B1 => n738_port, Y => n769_port);
U847 : CLKNAND2X2 port map( A => n771_port, B => n772_port, Y => N744);
U848 : AOI22XL port map( A0 => RF_OUT1(14), A1 => n735_port, B0 =>
IF_PC_INC_14_port, B1 => n736_port, Y => n772_port);
U849 : AOI22XL port map( A0 => ID_INSTR_14_port, A1 => n737_port, B0 =>
ID_PC_SUM_14_port, B1 => n738_port, Y => n771_port);
U850 : CLKNAND2X2 port map( A => n773_port, B => n774_port, Y => N743);
U851 : AOI22XL port map( A0 => RF_OUT1(13), A1 => n735_port, B0 =>
IF_PC_INC_13_port, B1 => n736_port, Y => n774_port);
U852 : AOI22XL port map( A0 => ID_INSTR_13_port, A1 => n737_port, B0 =>
ID_PC_SUM_13_port, B1 => n738_port, Y => n773_port);
U853 : CLKNAND2X2 port map( A => n775_port, B => n776_port, Y => N742);
U854 : AOI22XL port map( A0 => RF_OUT1(12), A1 => n735_port, B0 =>
IF_PC_INC_12_port, B1 => n736_port, Y => n776_port);
U855 : AOI22XL port map( A0 => ID_INSTR_12_port, A1 => n737_port, B0 =>
ID_PC_SUM_12_port, B1 => n738_port, Y => n775_port);
U856 : CLKNAND2X2 port map( A => n777_port, B => n778_port, Y => N741);
U857 : AOI22XL port map( A0 => RF_OUT1(11), A1 => n735_port, B0 =>
IF_PC_INC_11_port, B1 => n736_port, Y => n778_port);
U858 : AOI22XL port map( A0 => ID_INSTR_11_port, A1 => n737_port, B0 =>
ID_PC_SUM_11_port, B1 => n738_port, Y => n777_port);
U859 : CLKNAND2X2 port map( A => n779_port, B => n780_port, Y => N740);
U860 : AOI22XL port map( A0 => RF_OUT1(10), A1 => n735_port, B0 =>
IF_PC_INC_10_port, B1 => n736_port, Y => n780_port);
U861 : AOI22XL port map( A0 => ID_INSTR_10_port, A1 => n737_port, B0 =>
ID_PC_SUM_10_port, B1 => n738_port, Y => n779_port);
U862 : CLKNAND2X2 port map( A => n781_port, B => n782_port, Y => N739);
U863 : AOI22XL port map( A0 => RF_OUT1(9), A1 => n735_port, B0 =>
IF_PC_INC_9_port, B1 => n736_port, Y => n782_port);
U864 : AOI22XL port map( A0 => ID_INSTR_9_port, A1 => n737_port, B0 =>
ID_PC_SUM_9_port, B1 => n738_port, Y => n781_port);
U865 : CLKNAND2X2 port map( A => n783_port, B => n784_port, Y => N738);
U866 : AOI22XL port map( A0 => RF_OUT1(8), A1 => n735_port, B0 =>
IF_PC_INC_8_port, B1 => n736_port, Y => n784_port);
U867 : AOI22XL port map( A0 => ID_INSTR_8_port, A1 => n737_port, B0 =>
ID_PC_SUM_8_port, B1 => n738_port, Y => n783_port);
U868 : CLKNAND2X2 port map( A => n785_port, B => n786_port, Y => N737);
U869 : AOI22XL port map( A0 => RF_OUT1(7), A1 => n735_port, B0 =>
IF_PC_INC_7_port, B1 => n736_port, Y => n786_port);
U870 : AOI22XL port map( A0 => ID_INSTR_7_port, A1 => n737_port, B0 =>
ID_PC_SUM_7_port, B1 => n738_port, Y => n785_port);
U871 : CLKNAND2X2 port map( A => n787_port, B => n788_port, Y => N736);
U872 : AOI22XL port map( A0 => RF_OUT1(6), A1 => n735_port, B0 =>
IF_PC_INC_6_port, B1 => n736_port, Y => n788_port);
U873 : AOI22XL port map( A0 => ID_INSTR_6_port, A1 => n737_port, B0 =>
ID_PC_SUM_6_port, B1 => n738_port, Y => n787_port);
U874 : CLKNAND2X2 port map( A => n789_port, B => n790_port, Y => N735);
U875 : AOI22XL port map( A0 => RF_OUT1(5), A1 => n735_port, B0 =>
IF_PC_INC_5_port, B1 => n736_port, Y => n790_port);
U876 : AOI22XL port map( A0 => ID_INSTR_5_port, A1 => n737_port, B0 =>
ID_PC_SUM_5_port, B1 => n738_port, Y => n789_port);
U877 : CLKNAND2X2 port map( A => n791_port, B => n792_port, Y => N734);
U878 : AOI22XL port map( A0 => RF_OUT1(4), A1 => n735_port, B0 =>
IF_PC_INC_4_port, B1 => n736_port, Y => n792_port);
U879 : AOI22XL port map( A0 => ID_INSTR_4_port, A1 => n737_port, B0 =>
ID_PC_SUM_4_port, B1 => n738_port, Y => n791_port);
U880 : CLKNAND2X2 port map( A => n793_port, B => n794_port, Y => N733);
U881 : AOI22XL port map( A0 => RF_OUT1(3), A1 => n735_port, B0 =>
IF_PC_INC_3_port, B1 => n736_port, Y => n794_port);
U882 : AOI22XL port map( A0 => n737_port, A1 => ID_INSTR_3_port, B0 =>
ID_PC_SUM_3_port, B1 => n738_port, Y => n793_port);
U883 : CLKNAND2X2 port map( A => n795_port, B => n796, Y => N732);
U884 : AOI22XL port map( A0 => RF_OUT1(2), A1 => n735_port, B0 =>
IF_PC_INC_2_port, B1 => n736_port, Y => n796);
U885 : AOI22XL port map( A0 => n737_port, A1 => ID_INSTR_2_port, B0 =>
ID_PC_SUM_2_port, B1 => n738_port, Y => n795_port);
U886 : CLKNAND2X2 port map( A => n797, B => n798, Y => N731);
U887 : AOI22XL port map( A0 => RF_OUT1(1), A1 => n735_port, B0 =>
IF_PC_INC_1_port, B1 => n736_port, Y => n798);
U888 : AOI22XL port map( A0 => n737_port, A1 => ID_INSTR_1_port, B0 =>
ID_PC_SUM_1_port, B1 => n738_port, Y => n797);
U889 : CLKNAND2X2 port map( A => n799, B => n800, Y => N730);
U890 : AOI22XL port map( A0 => RF_OUT1(0), A1 => n735_port, B0 =>
IF_PC_INC_0_port, B1 => n736_port, Y => n800);
U891 : AOI21X1 port map( A0 => n801, A1 => n802, B0 => n738_port, Y =>
n736_port);
U892 : AOI22XL port map( A0 => ID_INSTR_0_port, A1 => n737_port, B0 =>
ID_PC_SUM_0_port, B1 => n738_port, Y => n799);
U893 : OAI2B11X1 port map( A1N => WB_ALU_30_port, A0 => n716, B0 => n717, C0
=> n805, Y => RF_DATAIN(30));
U894 : AOI22XL port map( A0 => WB_DATA_RAM_30_port, A1 => n719, B0 =>
WB_DATA_EXT_16_30_port, B1 => n720, Y => n805);
U895 : OAI2B11X1 port map( A1N => WB_ALU_29_port, A0 => n716, B0 => n717, C0
=> n806, Y => RF_DATAIN(29));
U896 : AOI22XL port map( A0 => WB_DATA_RAM_29_port, A1 => n719, B0 =>
WB_DATA_EXT_16_29_port, B1 => n720, Y => n806);
U897 : OAI2B11X1 port map( A1N => WB_ALU_28_port, A0 => n716, B0 => n717, C0
=> n807, Y => RF_DATAIN(28));
U898 : AOI22XL port map( A0 => WB_DATA_RAM_28_port, A1 => n719, B0 =>
WB_DATA_EXT_16_28_port, B1 => n720, Y => n807);
U899 : OAI2B11X1 port map( A1N => WB_ALU_27_port, A0 => n716, B0 => n717, C0
=> n808, Y => RF_DATAIN(27));
U900 : AOI22XL port map( A0 => WB_DATA_RAM_27_port, A1 => n719, B0 =>
WB_DATA_EXT_16_27_port, B1 => n720, Y => n808);
U901 : OAI2B11X1 port map( A1N => WB_ALU_26_port, A0 => n716, B0 => n717, C0
=> n809, Y => RF_DATAIN(26));
U902 : AOI22XL port map( A0 => WB_DATA_RAM_26_port, A1 => n719, B0 =>
WB_DATA_EXT_16_26_port, B1 => n720, Y => n809);
U903 : OAI2B11X1 port map( A1N => WB_ALU_25_port, A0 => n716, B0 => n717, C0
=> n810, Y => RF_DATAIN(25));
U904 : AOI22XL port map( A0 => WB_DATA_RAM_25_port, A1 => n719, B0 =>
WB_DATA_EXT_16_25_port, B1 => n720, Y => n810);
U905 : OAI2B11X1 port map( A1N => WB_ALU_24_port, A0 => n716, B0 => n717, C0
=> n811, Y => RF_DATAIN(24));
U906 : AOI22XL port map( A0 => WB_DATA_RAM_24_port, A1 => n719, B0 =>
WB_DATA_EXT_16_24_port, B1 => n720, Y => n811);
U907 : OAI2B11X1 port map( A1N => WB_ALU_23_port, A0 => n716, B0 => n717, C0
=> n812, Y => RF_DATAIN(23));
U908 : AOI22XL port map( A0 => WB_DATA_RAM_23_port, A1 => n719, B0 =>
WB_DATA_EXT_16_23_port, B1 => n720, Y => n812);
U909 : OAI2B11X1 port map( A1N => WB_ALU_22_port, A0 => n716, B0 => n717, C0
=> n813, Y => RF_DATAIN(22));
U910 : AOI22XL port map( A0 => WB_DATA_RAM_22_port, A1 => n719, B0 =>
WB_DATA_EXT_16_22_port, B1 => n720, Y => n813);
U911 : OAI2B11X1 port map( A1N => WB_ALU_21_port, A0 => n716, B0 => n717, C0
=> n814, Y => RF_DATAIN(21));
U912 : AOI22XL port map( A0 => WB_DATA_RAM_21_port, A1 => n719, B0 =>
WB_DATA_EXT_16_21_port, B1 => n720, Y => n814);
U913 : OAI2B11X1 port map( A1N => WB_ALU_20_port, A0 => n716, B0 => n717, C0
=> n815, Y => RF_DATAIN(20));
U914 : AOI22XL port map( A0 => WB_DATA_RAM_20_port, A1 => n719, B0 =>
WB_DATA_EXT_16_20_port, B1 => n720, Y => n815);
U915 : OAI2B11X1 port map( A1N => WB_ALU_19_port, A0 => n716, B0 => n717, C0
=> n816, Y => RF_DATAIN(19));
U916 : AOI22XL port map( A0 => WB_DATA_RAM_19_port, A1 => n719, B0 =>
WB_DATA_EXT_16_19_port, B1 => n720, Y => n816);
U917 : OAI2B11X1 port map( A1N => WB_ALU_18_port, A0 => n716, B0 => n717, C0
=> n817, Y => RF_DATAIN(18));
U918 : AOI22XL port map( A0 => WB_DATA_RAM_18_port, A1 => n719, B0 =>
WB_DATA_EXT_16_18_port, B1 => n720, Y => n817);
U919 : OAI2B11X1 port map( A1N => WB_ALU_17_port, A0 => n716, B0 => n717, C0
=> n818, Y => RF_DATAIN(17));
U920 : AOI22XL port map( A0 => WB_DATA_RAM_17_port, A1 => n719, B0 =>
WB_DATA_EXT_16_17_port, B1 => n720, Y => n818);
U921 : OAI2B11X1 port map( A1N => WB_ALU_16_port, A0 => n716, B0 => n717, C0
=> n819, Y => RF_DATAIN(16));
U922 : AOI22XL port map( A0 => WB_DATA_RAM_16_port, A1 => n719, B0 =>
WB_DATA_EXT_16_16_port, B1 => n720, Y => n819);
U923 : CLKNAND2X2 port map( A => n822, B => n821, Y => n716);
U924 : OAI211XL port map( A0 => n823, A1 => n820, B0 => n717, C0 => n824, Y
=> RF_DATAIN(15));
U925 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_15_port, B => n720, Y =>
n824);
U926 : OAI211XL port map( A0 => n825, A1 => n820, B0 => n717, C0 => n826, Y
=> RF_DATAIN(14));
U927 : OAI211XL port map( A0 => n827, A1 => n820, B0 => n717, C0 => n828, Y
=> RF_DATAIN(13));
U928 : OAI211XL port map( A0 => n829, A1 => n820, B0 => n717, C0 => n830, Y
=> RF_DATAIN(12));
U929 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_12_port, B => n720, Y =>
n830);
U930 : OAI211XL port map( A0 => n831, A1 => n820, B0 => n717, C0 => n832, Y
=> RF_DATAIN(11));
U931 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_11_port, B => n720, Y =>
n832);
U932 : OAI211XL port map( A0 => n833, A1 => n820, B0 => n717, C0 => n834, Y
=> RF_DATAIN(10));
U933 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_10_port, B => n720, Y =>
n834);
U934 : OAI211XL port map( A0 => n835, A1 => n820, B0 => n717, C0 => n836, Y
=> RF_DATAIN(9));
U935 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_9_port, B => n720, Y => n836
);
U936 : OAI211XL port map( A0 => n837, A1 => n820, B0 => n717, C0 => n838, Y
=> RF_DATAIN(8));
U937 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_8_port, B => n720, Y => n838
);
U938 : OAI211XL port map( A0 => n839, A1 => n820, B0 => n717, C0 => n840, Y
=> RF_DATAIN(7));
U939 : CLKNAND2X2 port map( A => WB_DATA_EXT_16_7_port, B => n720, Y => n840
);
U940 : CLKNAND2X2 port map( A => WB_DATA_EXT_8_9_port, B => n841, Y => n717)
;
U941 : CLKINVX1 port map( A => n822, Y => n820);
U942 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_6_port, A1N => n841, B0 =>
n842, Y => RF_DATAIN(6));
U943 : AOI22XL port map( A0 => n822, A1 => N6140, B0 =>
WB_DATA_EXT_16_6_port, B1 => n720, Y => n842);
U944 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_5_port, A1N => n841, B0 =>
n843, Y => RF_DATAIN(5));
U945 : AOI22XL port map( A0 => n822, A1 => N6139, B0 =>
WB_DATA_EXT_16_5_port, B1 => n720, Y => n843);
U946 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_4_port, A1N => n841, B0 =>
n844, Y => RF_DATAIN(4));
U947 : AOI22XL port map( A0 => n822, A1 => N6138, B0 =>
WB_DATA_EXT_16_4_port, B1 => n720, Y => n844);
U948 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_3_port, A1N => n841, B0 =>
n845, Y => RF_DATAIN(3));
U949 : AOI22XL port map( A0 => n822, A1 => N6137, B0 =>
WB_DATA_EXT_16_3_port, B1 => n720, Y => n845);
U950 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_2_port, A1N => n841, B0 =>
n846, Y => RF_DATAIN(2));
U951 : AOI22XL port map( A0 => n822, A1 => N6136, B0 =>
WB_DATA_EXT_16_2_port, B1 => n720, Y => n846);
U952 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_1_port, A1N => n841, B0 =>
n847, Y => RF_DATAIN(1));
U953 : AOI22XL port map( A0 => n822, A1 => N6135, B0 =>
WB_DATA_EXT_16_1_port, B1 => n720, Y => n847);
U954 : OAI2BB1X1 port map( A0N => WB_DATA_EXT_8_0_port, A1N => n841, B0 =>
n848, Y => RF_DATAIN(0));
U955 : AOI22XL port map( A0 => n822, A1 => N6134, B0 =>
WB_DATA_EXT_16_0_port, B1 => n720, Y => n848);
U956 : NOR2X1 port map( A => n720, B => n841, Y => n822);
U957 : OAI21X1 port map( A0 => WB_INSTR_30, A1 => n849, B0 =>
WB_SIGN_EXT_16_CONTROL, Y => n720);
U958 : NAND4X1 port map( A => WB_INSTR_28, B => WB_INSTR_27, C =>
WB_INSTR_29, D => n850, Y => WB_SIGN_EXT_16_CONTROL)
;
U959 : NOR3X1 port map( A => n851, B => WB_INSTR_31, C => WB_INSTR_30, Y =>
n850);
U960 : CLKINVX1 port map( A => n823, Y => N6149);
U961 : CLKINVX1 port map( A => n825, Y => N6148);
U962 : CLKINVX1 port map( A => n827, Y => N6147);
U963 : CLKINVX1 port map( A => n829, Y => N6146);
U964 : CLKINVX1 port map( A => n831, Y => N6145);
U965 : CLKINVX1 port map( A => n833, Y => N6144);
U966 : CLKINVX1 port map( A => n835, Y => N6143);
U967 : CLKINVX1 port map( A => n837, Y => N6142);
U968 : CLKINVX1 port map( A => n839, Y => N6141);
U969 : OAI22X1 port map( A0 => n851, A1 => n854, B0 => WB_INSTR_27, B1 =>
n855, Y => n852);
U970 : MXI2X1 port map( A => n851, B => n856, S0 => WB_INSTR_28, Y => n855);
U971 : MX2X1 port map( A => EX_ALU_OUT_31_port, B => EX_MULT_OUT_31_port, S0
=> n857, Y => N4891);
U972 : AO22X1 port map( A0 => EX_IMM16_EXT_30_port, A1 => n858, B0 =>
EX_REGB_30_port, B1 => n859, Y => N4857);
U973 : AO22X1 port map( A0 => EX_IMM16_EXT_29_port, A1 => n858, B0 =>
EX_REGB_29_port, B1 => n859, Y => N4856);
U974 : AO22X1 port map( A0 => EX_IMM16_EXT_28_port, A1 => n858, B0 =>
EX_REGB_28_port, B1 => n859, Y => N4855);
U975 : AO22X1 port map( A0 => EX_IMM16_EXT_27_port, A1 => n858, B0 =>
EX_REGB_27_port, B1 => n859, Y => N4854);
U976 : AO22X1 port map( A0 => EX_IMM16_EXT_26_port, A1 => n858, B0 =>
EX_REGB_26_port, B1 => n859, Y => N4853);
U977 : AO22X1 port map( A0 => EX_IMM16_EXT_25_port, A1 => n858, B0 =>
EX_REGB_25_port, B1 => n859, Y => N4852);
U978 : AO22X1 port map( A0 => EX_IMM16_EXT_24_port, A1 => n858, B0 =>
EX_REGB_24_port, B1 => n859, Y => N4851);
U979 : AO22X1 port map( A0 => EX_IMM16_EXT_23_port, A1 => n858, B0 =>
EX_REGB_23_port, B1 => n859, Y => N4850);
U980 : AO22X1 port map( A0 => EX_IMM16_EXT_22_port, A1 => n858, B0 =>
EX_REGB_22_port, B1 => n859, Y => N4849);
U981 : AO22X1 port map( A0 => EX_IMM16_EXT_21_port, A1 => n858, B0 =>
EX_REGB_21_port, B1 => n859, Y => N4848);
U982 : AO22X1 port map( A0 => EX_IMM16_EXT_20_port, A1 => n858, B0 =>
EX_REGB_20_port, B1 => n859, Y => N4847);
U983 : AO22X1 port map( A0 => EX_IMM16_EXT_19_port, A1 => n858, B0 =>
EX_REGB_19_port, B1 => n859, Y => N4846);
U984 : AO22X1 port map( A0 => EX_IMM16_EXT_18_port, A1 => n858, B0 =>
EX_REGB_18_port, B1 => n859, Y => N4845);
U985 : AO22X1 port map( A0 => EX_IMM16_EXT_17_port, A1 => n858, B0 =>
EX_REGB_17_port, B1 => n859, Y => N4844);
U986 : AO22X1 port map( A0 => EX_IMM16_EXT_16_port, A1 => n858, B0 =>
EX_REGB_16_port, B1 => n859, Y => N4843);
U987 : AO22X1 port map( A0 => EX_IMM16_EXT_15_port, A1 => n858, B0 =>
EX_REGB_15_port, B1 => n859, Y => N4842);
U988 : AO22X1 port map( A0 => EX_IMM16_EXT_14_port, A1 => n858, B0 =>
EX_REGB_14_port, B1 => n859, Y => N4841);
U989 : AO22X1 port map( A0 => EX_IMM16_EXT_13_port, A1 => n858, B0 =>
EX_REGB_13_port, B1 => n859, Y => N4840);
U990 : AO22X1 port map( A0 => EX_IMM16_EXT_12_port, A1 => n858, B0 =>
EX_REGB_12_port, B1 => n859, Y => N4839);
U991 : AO22X1 port map( A0 => EX_IMM16_EXT_11_port, A1 => n858, B0 =>
EX_REGB_11_port, B1 => n859, Y => N4838);
U992 : AO22X1 port map( A0 => EX_IMM16_EXT_10_port, A1 => n858, B0 =>
EX_REGB_10_port, B1 => n859, Y => N4837);
U993 : AO22X1 port map( A0 => EX_IMM16_EXT_9_port, A1 => n858, B0 =>
EX_REGB_9_port, B1 => n859, Y => N4836);
U994 : AO22X1 port map( A0 => EX_IMM16_EXT_8_port, A1 => n858, B0 =>
EX_REGB_8_port, B1 => n859, Y => N4835);
U995 : AO22X1 port map( A0 => EX_IMM16_EXT_7_port, A1 => n858, B0 =>
EX_REGB_7_port, B1 => n859, Y => N4834);
U996 : AO22X1 port map( A0 => EX_IMM16_EXT_6_port, A1 => n858, B0 =>
EX_REGB_6_port, B1 => n859, Y => N4833);
U997 : AO22X1 port map( A0 => EX_IMM16_EXT_5_port, A1 => n858, B0 =>
EX_REGB_5_port, B1 => n859, Y => N4832);
U998 : AO22X1 port map( A0 => EX_IMM16_EXT_4_port, A1 => n858, B0 =>
EX_REGB_4_port, B1 => n859, Y => N4831);
U999 : MXI2X1 port map( A => EX_IMM16_EXT_3_port, B => EX_REGB_3_port, S0 =>
n862, Y => n860);
U1000 : MX2X1 port map( A => EX_REGA_29_port, B => EX_PC_29_port, S0 => n863
, Y => N4747);
U1001 : MX2X1 port map( A => EX_REGA_28_port, B => EX_PC_28_port, S0 => n863
, Y => N4746);
U1002 : MX2X1 port map( A => EX_REGA_27_port, B => EX_PC_27_port, S0 => n863
, Y => N4745);
U1003 : MX2X1 port map( A => EX_REGA_26_port, B => EX_PC_26_port, S0 => n863
, Y => N4744);
U1004 : MX2X1 port map( A => EX_REGA_25_port, B => EX_PC_25_port, S0 => n863
, Y => N4743);
U1005 : MX2X1 port map( A => EX_REGA_24_port, B => EX_PC_24_port, S0 => n863
, Y => N4742);
U1006 : MX2X1 port map( A => EX_REGA_23_port, B => EX_PC_23_port, S0 => n863
, Y => N4741);
U1007 : MX2X1 port map( A => EX_REGA_22_port, B => EX_PC_22_port, S0 => n863
, Y => N4740);
U1008 : MX2X1 port map( A => EX_REGA_21_port, B => EX_PC_21_port, S0 => n863
, Y => N4739);
U1009 : MX2X1 port map( A => EX_REGA_17_port, B => EX_PC_17_port, S0 => n863
, Y => N4735);
U1010 : MX2X1 port map( A => EX_REGA_16_port, B => EX_PC_16_port, S0 => n863
, Y => N4734);
U1011 : MX2X1 port map( A => EX_REGA_15_port, B => EX_PC_15_port, S0 => n863
, Y => N4733);
U1012 : MX2X1 port map( A => EX_REGA_14_port, B => EX_PC_14_port, S0 => n863
, Y => N4732);
U1013 : MX2X1 port map( A => EX_REGA_13_port, B => EX_PC_13_port, S0 => n863
, Y => N4731);
U1014 : MX2X1 port map( A => EX_REGA_12_port, B => EX_PC_12_port, S0 => n863
, Y => N4730);
U1015 : MX2X1 port map( A => EX_REGA_11_port, B => EX_PC_11_port, S0 => n863
, Y => N4729);
U1016 : MX2X1 port map( A => EX_REGA_10_port, B => EX_PC_10_port, S0 => n863
, Y => N4728);
U1017 : MX2X1 port map( A => EX_REGA_9_port, B => EX_PC_9_port, S0 => n863,
Y => N4727);
U1018 : MX2X1 port map( A => EX_REGA_8_port, B => EX_PC_8_port, S0 => n863,
Y => N4726);
U1019 : MX2X1 port map( A => EX_REGA_7_port, B => EX_PC_7_port, S0 => n863,
Y => N4725);
U1020 : MX2X1 port map( A => EX_REGA_6_port, B => EX_PC_6_port, S0 => n863,
Y => N4724);
U1021 : MX2X1 port map( A => EX_REGA_5_port, B => EX_PC_5_port, S0 => n863,
Y => N4723);
U1022 : MX2X1 port map( A => EX_REGA_4_port, B => EX_PC_4_port, S0 => n863,
Y => N4722);
U1023 : MX2X1 port map( A => EX_REGA_3_port, B => EX_PC_3_port, S0 => n863,
Y => N4721);
U1024 : MX2X1 port map( A => EX_REGA_2_port, B => EX_PC_2_port, S0 => n863,
Y => N4720);
U1025 : MX2X1 port map( A => EX_REGA_1_port, B => EX_PC_1_port, S0 => n863,
Y => N4719);
U1026 : MX2X1 port map( A => EX_REGA_0_port, B => EX_PC_0_port, S0 => n863,
Y => N4718);
U1027 : AOI31X1 port map( A0 => n866, A1 => n803, A2 => n867, B0 => n868, Y
=> N4716);
U1028 : OAI32XL port map( A0 => n869, A1 => n870, A2 => n871, B0 => n867, B1
=> n872, Y => N4712);
U1029 : AOI21X1 port map( A0 => n710, A1 => n873, B0 => n874, Y => n872);
U1030 : AOI22XL port map( A0 => n875, A1 => n876, B0 => n877, B1 => n870, Y
=> n874);
U1031 : OAI21X1 port map( A0 => n878, A1 => n879, B0 => n880, Y => n876);
U1032 : OAI2BB2X1 port map( B0 => n881, B1 => n882, A0N => n871, A1N => n877
, Y => n875);
U1033 : CLKINVX1 port map( A => n879, Y => n877);
U1034 : OAI22X1 port map( A0 => n883, A1 => n884, B0 => n885, B1 => n886, Y
=> n879);
U1035 : OAI2B2X1 port map( A1N => n878, A0 => n870, B0 => n885, B1 => n884,
Y => n873);
U1036 : CLKINVX1 port map( A => n887, Y => n885);
U1037 : OAI31X1 port map( A0 => n888, A1 => n889, A2 => n890, B0 => n883, Y
=> n887);
U1038 : NAND3XL port map( A => n891, B => n892, C => n893, Y => n883);
U1039 : NOR3X1 port map( A => n894, B => n895, C => n896, Y => n893);
U1040 : XOR2X1 port map( A => RF_ADD_RD1_0_port, B => EX_INSTR_11_port, Y =>
n896);
U1041 : XOR2X1 port map( A => RF_ADD_RD1_2_port, B => EX_INSTR_13_port, Y =>
n895);
U1042 : XOR2X1 port map( A => RF_ADD_RD1_1_port, B => EX_INSTR_12_port, Y =>
n894);
U1043 : XNOR2X1 port map( A => EX_INSTR_14_port, B => RF_ADD_RD1_3_port, Y
=> n892);
U1044 : XOR2X1 port map( A => EX_INSTR_15_port, B => n897, Y => n891);
U1045 : XOR2X1 port map( A => RF_ADD_RD2_4_port, B => EX_INSTR_15_port, Y =>
n890);
U1046 : XOR2X1 port map( A => RF_ADD_RD2_2_port, B => EX_INSTR_13_port, Y =>
n889);
U1047 : NAND3XL port map( A => n898, B => n899, C => n900, Y => n888);
U1048 : XOR2X1 port map( A => EX_INSTR_11_port, B => n901, Y => n900);
U1049 : XOR2X1 port map( A => EX_INSTR_12_port, B => n902, Y => n899);
U1050 : XNOR2X1 port map( A => EX_INSTR_14_port, B => RF_ADD_RD2_3_port, Y
=> n898);
U1051 : OAI31X1 port map( A0 => n903, A1 => n904, A2 => n905, B0 => n871, Y
=> n878);
U1052 : XOR2X1 port map( A => RF_ADD_RD2_4_port, B => EX_INSTR_20_port, Y =>
n905);
U1053 : XOR2X1 port map( A => RF_ADD_RD2_2_port, B => EX_INSTR_18_port, Y =>
n904);
U1054 : NAND3XL port map( A => n906, B => n907, C => n908, Y => n903);
U1055 : XOR2X1 port map( A => EX_INSTR_16_port, B => n901, Y => n908);
U1056 : XOR2X1 port map( A => EX_INSTR_17_port, B => n902, Y => n907);
U1057 : XNOR2X1 port map( A => EX_INSTR_19_port, B => RF_ADD_RD2_3_port, Y
=> n906);
U1058 : NOR3X1 port map( A => n909, B => EX_INSTR_27_port, C => n910, Y =>
n867);
U1059 : NAND3XL port map( A => n911, B => n912, C => n913, Y => n871);
U1060 : NOR3X1 port map( A => n914, B => n915, C => n916, Y => n913);
U1061 : XOR2X1 port map( A => RF_ADD_RD1_0_port, B => EX_INSTR_16_port, Y =>
n916);
U1062 : XOR2X1 port map( A => RF_ADD_RD1_2_port, B => EX_INSTR_18_port, Y =>
n915);
U1063 : XOR2X1 port map( A => RF_ADD_RD1_1_port, B => EX_INSTR_17_port, Y =>
n914);
U1064 : XNOR2X1 port map( A => EX_INSTR_19_port, B => RF_ADD_RD1_3_port, Y
=> n912);
U1065 : XOR2X1 port map( A => EX_INSTR_20_port, B => n897, Y => n911);
U1066 : OAI2B11X1 port map( A1N => n917, A0 => n918, B0 => n886, C0 => n884,
Y => n870);
U1067 : CLKINVX1 port map( A => n919, Y => n886);
U1068 : CLKNAND2X2 port map( A => n866, B => n803, Y => n869);
U1069 : CLKINVX1 port map( A => n700, Y => n803);
U1070 : OAI33X1 port map( A0 => n920, A1 => n707, A2 => n921, B0 => n922, B1
=> n921, B2 => n923, Y => N4710);
U1071 : AOI21X1 port map( A0 => n924, A1 => n925, B0 => n926, Y => n923);
U1072 : AOI21BX1 port map( A0 => n927, A1 => n928, B0N => n929, Y => n926);
U1073 : AND4X1 port map( A => MEM_INSTR_30_port, B => n930, C =>
MEM_INSTR_26_port, D => MEM_INSTR_28_port, Y => n921
);
U1074 : AOI222XL port map( A0 => n929, A1 => n931, B0 => n932, B1 => n925,
C0 => n933, C1 => n924, Y => n920);
U1075 : CLKINVX1 port map( A => n934, Y => n933);
U1076 : OAI31X1 port map( A0 => n935, A1 => n936, A2 => n937, B0 => n934, Y
=> n925);
U1077 : NAND3XL port map( A => n938, B => n939, C => n940, Y => n934);
U1078 : NOR3X1 port map( A => n941, B => n942, C => n943, Y => n940);
U1079 : XOR2X1 port map( A => RF_ADD_RD1_0_port, B => MEM_INSTR_11_port, Y
=> n943);
U1080 : XOR2X1 port map( A => RF_ADD_RD1_2_port, B => MEM_INSTR_13_port, Y
=> n942);
U1081 : XOR2X1 port map( A => RF_ADD_RD1_1_port, B => MEM_INSTR_12_port, Y
=> n941);
U1082 : XNOR2X1 port map( A => MEM_INSTR_14_port, B => RF_ADD_RD1_3_port, Y
=> n939);
U1083 : XOR2X1 port map( A => MEM_INSTR_15_port, B => n897, Y => n938);
U1084 : XOR2X1 port map( A => RF_ADD_RD2_4_port, B => MEM_INSTR_15_port, Y
=> n937);
U1085 : XOR2X1 port map( A => RF_ADD_RD2_2_port, B => MEM_INSTR_13_port, Y
=> n936);
U1086 : NAND3XL port map( A => n944, B => n945, C => n946, Y => n935);
U1087 : XOR2X1 port map( A => MEM_INSTR_11_port, B => n901, Y => n946);
U1088 : XOR2X1 port map( A => MEM_INSTR_12_port, B => n902, Y => n945);
U1089 : XNOR2X1 port map( A => MEM_INSTR_14_port, B => RF_ADD_RD2_3_port, Y
=> n944);
U1090 : OAI21X1 port map( A0 => n947, A1 => n927, B0 => n928, Y => n931);
U1091 : NAND3XL port map( A => n948, B => n949, C => n950, Y => n928);
U1092 : NOR3X1 port map( A => n951, B => n952, C => n953, Y => n950);
U1093 : XOR2X1 port map( A => RF_ADD_RD1_0_port, B => MEM_INSTR_16_port, Y
=> n953);
U1094 : XOR2X1 port map( A => RF_ADD_RD1_2_port, B => MEM_INSTR_18_port, Y
=> n952);
U1095 : XOR2X1 port map( A => RF_ADD_RD1_1_port, B => MEM_INSTR_17_port, Y
=> n951);
U1096 : XNOR2X1 port map( A => MEM_INSTR_19_port, B => RF_ADD_RD1_3_port, Y
=> n949);
U1097 : XOR2X1 port map( A => MEM_INSTR_20_port, B => n897, Y => n948);
U1098 : NAND3XL port map( A => n954, B => n955, C => n956, Y => n927);
U1099 : NOR3X1 port map( A => n957, B => n958, C => n959, Y => n956);
U1100 : XOR2X1 port map( A => RF_ADD_RD2_0_port, B => MEM_INSTR_16_port, Y
=> n959);
U1101 : XOR2X1 port map( A => RF_ADD_RD2_2_port, B => MEM_INSTR_18_port, Y
=> n958);
U1102 : XOR2X1 port map( A => RF_ADD_RD2_1_port, B => MEM_INSTR_17_port, Y
=> n957);
U1103 : XNOR2X1 port map( A => MEM_INSTR_19_port, B => RF_ADD_RD2_3_port, Y
=> n955);
U1104 : XOR2X1 port map( A => MEM_INSTR_20_port, B => n960, Y => n954);
U1105 : NOR3BX1 port map( AN => n961, B => n924, C => n932, Y => n929);
U1106 : CLKINVX1 port map( A => n729, Y => n932);
U1107 : NAND4X1 port map( A => n962, B => n726, C => MEM_INSTR_29_port, D =>
n732_port, Y => n729);
U1108 : NOR2BX1 port map( AN => MEM_INSTR_31_port, B => MEM_INSTR_30_port, Y
=> n726);
U1109 : XOR2X1 port map( A => n723, B => MEM_INSTR_27_port, Y => n962);
U1110 : CLKINVX1 port map( A => MEM_INSTR_26_port, Y => n723);
U1111 : NOR4BX1 port map( AN => n930, B => MEM_INSTR_26_port, C =>
MEM_INSTR_28_port, D => MEM_INSTR_30_port, Y => n924
);
U1112 : NOR3X1 port map( A => MEM_INSTR_29_port, B => MEM_INSTR_31_port, C
=> MEM_INSTR_27_port, Y => n930);
U1113 : NAND3XL port map( A => MEM_INSTR_27_port, B => n732_port, C => n963,
Y => n961);
U1114 : NOR3X1 port map( A => MEM_INSTR_29_port, B => MEM_INSTR_31_port, C
=> MEM_INSTR_30_port, Y => n963);
U1115 : CLKINVX1 port map( A => MEM_INSTR_28_port, Y => n732_port);
U1116 : OA21X1 port map( A0 => n964, A1 => n965, B0 => RF_WR_port, Y =>
N4708);
U1117 : NAND3BX1 port map( AN => n966, B => n967, C => n968, Y => RF_WR_port
);
U1118 : AOI221XL port map( A0 => n969, A1 => n970, B0 => n971, B1 =>
WB_INSTR_28, C0 => n841, Y => n968);
U1119 : NOR3BX1 port map( AN => n971, B => WB_INSTR_26, C => WB_INSTR_28, Y
=> n841);
U1120 : NOR4X1 port map( A => n970, B => WB_INSTR_27, C => WB_INSTR_29, D =>
WB_INSTR_30, Y => n971);
U1121 : OAI211XL port map( A0 => n972, A1 => n853, B0 => n973, C0 => n854, Y
=> n969);
U1122 : OAI21X1 port map( A0 => n974, A1 => n853, B0 => WB_INSTR_29, Y =>
n973);
U1123 : CLKINVX1 port map( A => WB_INSTR_30, Y => n853);
U1124 : AOI32XL port map( A0 => n851, A1 => n856, A2 => WB_INSTR_28, B0 =>
n975, B1 => WB_INSTR_27, Y => n972);
U1125 : MXI2X1 port map( A => n976, B => n977, S0 => WB_INSTR_30, Y => n967)
;
U1126 : AOI21X1 port map( A0 => n854, A1 => n978, B0 => n856, Y => n977);
U1127 : NAND3XL port map( A => WB_INSTR_26, B => n974, C => WB_INSTR_28, Y
=> n978);
U1128 : NOR4X1 port map( A => n979, B => n980, C => n981, D => n982, Y =>
n965);
U1129 : XOR2X1 port map( A => RF_ADD_WR_2_port, B => RF_ADD_RD1_2_port, Y =>
n982);
U1130 : XOR2X1 port map( A => RF_ADD_WR_1_port, B => RF_ADD_RD1_1_port, Y =>
n981);
U1131 : XOR2X1 port map( A => RF_ADD_WR_4_port, B => RF_ADD_RD1_4_port, Y =>
n980);
U1132 : OAI2B11X1 port map( A1N => n707, A0 => n710, B0 => n983, C0 => n984,
Y => n979);
U1133 : XNOR2X1 port map( A => RF_ADD_RD1_3_port, B => RF_ADD_WR_3_port, Y
=> n984);
U1134 : XOR2X1 port map( A => n985, B => RF_ADD_WR_0_port, Y => n983);
U1135 : NOR3X1 port map( A => n882, B => n881, C => n880, Y => n707);
U1136 : AND3X1 port map( A => n986, B => n987, C => n866, Y => n881);
U1137 : CLKINVX1 port map( A => n701, Y => n866);
U1138 : OAI21X1 port map( A0 => ID_INSTR_30, A1 => n699, B0 => ID_INSTR_27,
Y => n986);
U1139 : CLKNAND2X2 port map( A => n988, B => n700, Y => n882);
U1140 : CLKNAND2X2 port map( A => ID_INSTR_30, B => n802, Y => n700);
U1141 : CLKINVX1 port map( A => n804, Y => n802);
U1142 : NAND3XL port map( A => n699, B => n987, C => ID_INSTR_27, Y => n804)
;
U1143 : MXI2X1 port map( A => n989, B => n990, S0 => ID_INSTR_28, Y => n988)
;
U1144 : AOI2B1X1 port map( A1N => n991, A0 => n992, B0 => n993, Y => n990);
U1145 : NAND3XL port map( A => n994, B => n704, C => ID_INSTR_29, Y => n992)
;
U1146 : OAI31X1 port map( A0 => n995, A1 => n704, A2 => n699, B0 => n996, Y
=> n989);
U1147 : NOR4X1 port map( A => n997, B => n998, C => n999, D => n1000, Y =>
n964);
U1148 : XOR2X1 port map( A => RF_ADD_WR_2_port, B => RF_ADD_RD2_2_port, Y =>
n1000);
U1149 : OAI2BB1X1 port map( A0N => WB_INSTR_13_port, A1N => n966, B0 =>
n1001, Y => RF_ADD_WR_2_port);
U1150 : AOI21X1 port map( A0 => WB_INSTR_18_port, A1 => n1002, B0 => n1003,
Y => n1001);
U1151 : XOR2X1 port map( A => RF_ADD_WR_1_port, B => RF_ADD_RD2_1_port, Y =>
n999);
U1152 : OAI2BB1X1 port map( A0N => WB_INSTR_12_port, A1N => n966, B0 =>
n1004, Y => RF_ADD_WR_1_port);
U1153 : AOI21X1 port map( A0 => WB_INSTR_17_port, A1 => n1002, B0 => n1003,
Y => n1004);
U1154 : XOR2X1 port map( A => RF_ADD_WR_4_port, B => RF_ADD_RD2_4_port, Y =>
n998);
U1155 : OAI2BB1X1 port map( A0N => WB_INSTR_15_port, A1N => n966, B0 =>
n1005, Y => RF_ADD_WR_4_port);
U1156 : AOI21X1 port map( A0 => WB_INSTR_20_port, A1 => n1002, B0 => n1003,
Y => n1005);
U1157 : OAI211XL port map( A0 => n710, A1 => n880, B0 => n1006, C0 => n1007,
Y => n997);
U1158 : XNOR2X1 port map( A => RF_ADD_RD2_3_port, B => RF_ADD_WR_3_port, Y
=> n1007);
U1159 : OAI2BB1X1 port map( A0N => WB_INSTR_14_port, A1N => n966, B0 =>
n1008, Y => RF_ADD_WR_3_port);
U1160 : AOI21X1 port map( A0 => WB_INSTR_19_port, A1 => n1002, B0 => n1003,
Y => n1008);
U1161 : XOR2X1 port map( A => n901, B => RF_ADD_WR_0_port, Y => n1006);
U1162 : OAI2BB1X1 port map( A0N => WB_INSTR_11_port, A1N => n966, B0 =>
n1009, Y => RF_ADD_WR_0_port);
U1163 : AOI21X1 port map( A0 => WB_INSTR_16_port, A1 => n1002, B0 => n1003,
Y => n1009);
U1164 : CLKINVX1 port map( A => n849, Y => n1003);
U1165 : CLKNAND2X2 port map( A => n976, B => n970, Y => n849);
U1166 : CLKINVX1 port map( A => WB_INSTR_31, Y => n970);
U1167 : NOR2BX1 port map( AN => n975, B => n854, Y => n976);
U1168 : NAND2BX1 port map( AN => WB_INSTR_28, B => WB_INSTR_27, Y => n854);
U1169 : OAI2BB2X1 port map( B0 => n1010, B1 => n1011, A0N => n1012, A1N =>
n975, Y => n966);
U1170 : NOR2X1 port map( A => n851, B => WB_INSTR_29, Y => n975);
U1171 : CLKINVX1 port map( A => WB_INSTR_26, Y => n851);
U1172 : OAI2B11X1 port map( A1N => n1013, A0 => WB_INSTR_5_port, B0 => n1014
, C0 => n1015, Y => n1011);
U1173 : AOI31X1 port map( A0 => WB_INSTR_1_port, A1 => n1016, A2 =>
WB_INSTR_2_port, B0 => n1002, Y => n1015);
U1174 : NAND3XL port map( A => n974, B => n856, C => n1012, Y => n1002);
U1175 : NOR3X1 port map( A => WB_INSTR_30, B => WB_INSTR_31, C =>
WB_INSTR_28, Y => n1012);
U1176 : CLKINVX1 port map( A => WB_INSTR_29, Y => n856);
U1177 : CLKINVX1 port map( A => WB_INSTR_27, Y => n974);
U1178 : OAI2BB1X1 port map( A0N => WB_INSTR_0_port, A1N => WB_INSTR_5_port,
B0 => n1017, Y => n1016);
U1179 : OAI21X1 port map( A0 => n1018, A1 => n1017, B0 => WB_INSTR_4_port, Y
=> n1014);
U1180 : AOI21X1 port map( A0 => WB_INSTR_2_port, A1 => WB_INSTR_0_port, B0
=> WB_INSTR_1_port, Y => n1018);
U1181 : OAI2B11X1 port map( A1N => WB_INSTR_0_port, A0 => WB_INSTR_1_port,
B0 => WB_INSTR_2_port, C0 => n1017, Y => n1013);
U1182 : CLKINVX1 port map( A => WB_INSTR_3_port, Y => n1017);
U1183 : OR3X1 port map( A => WB_INSTR_6_port, B => WB_INSTR_10_port, C =>
n1019, Y => n1010);
U1184 : OR3X1 port map( A => WB_INSTR_9_port, B => WB_INSTR_8_port, C =>
WB_INSTR_7_port, Y => n1019);
U1185 : CLKINVX1 port map( A => n947, Y => n880);
U1186 : CLKINVX1 port map( A => RESET, Y => IF_NOT_RESET);
U1187 : NAND3XL port map( A => n1021, B => n947, C => n1022, Y =>
ID_SIGN_EXT_CONTROL);
U1188 : NOR3X1 port map( A => n710, B => n738_port, C => n868, Y => n1022);
U1189 : CLKINVX1 port map( A => N4717, Y => n868);
U1190 : NAND3XL port map( A => n991, B => n801, C => ID_INSTR_26, Y => N4717
);
U1191 : AND2X1 port map( A => n1023, B => n991, Y => n738_port);
U1192 : MXI2X1 port map( A => n1024, B => n701, S0 => ID_REGA_ZERO, Y =>
n1023);
U1193 : CLKNAND2X2 port map( A => ID_INSTR_28, B => n993, Y => n701);
U1194 : CLKNAND2X2 port map( A => ID_INSTR_28, B => ID_INSTR_26, Y => n1024)
;
U1195 : CLKINVX1 port map( A => n922, Y => n710);
U1196 : CLKNAND2X2 port map( A => n703, B => n991, Y => n922);
U1197 : NOR4X1 port map( A => ID_INSTR_27, B => ID_INSTR_29, C =>
ID_INSTR_30, D => ID_INSTR_31, Y => n991);
U1198 : AOI31X1 port map( A0 => n705, A1 => n704, A2 => n1025, B0 => n706, Y
=> n947);
U1199 : NOR4X1 port map( A => n704, B => n994, C => n993, D => ID_INSTR_28,
Y => n706);
U1200 : OAI21BX1 port map( A0 => ID_INSTR_29, A1 => n801, B0N => n703, Y =>
n1025);
U1201 : CLKINVX1 port map( A => n994, Y => n705);
U1202 : CLKNAND2X2 port map( A => ID_INSTR_31, B => n995, Y => n994);
U1203 : AOI32XL port map( A0 => ID_INSTR_30, A1 => ID_INSTR_29, A2 => n1026,
B0 => n1027, B1 => n703, Y => n1021);
U1204 : NOR2X1 port map( A => ID_INSTR_26, B => ID_INSTR_28, Y => n703);
U1205 : CLKINVX1 port map( A => n996, Y => n1027);
U1206 : CLKNAND2X2 port map( A => ID_INSTR_29, B => n987, Y => n996);
U1207 : AOI21X1 port map( A0 => ID_INSTR_28, A1 => ID_INSTR_27, B0 =>
ID_INSTR_31, Y => n1026);
U1208 : CLKINVX1 port map( A => ID_INSTR_9_port, Y => n713);
U1209 : CLKINVX1 port map( A => ID_INSTR_8_port, Y => n712);
U1210 : CLKINVX1 port map( A => ID_INSTR_7_port, Y => n714);
U1211 : NOR2BX1 port map( AN => ID_INSTR_6_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_6_port);
U1212 : NOR2BX1 port map( AN => ID_INSTR_5_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_5_port);
U1213 : NOR2BX1 port map( AN => ID_INSTR_4_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_4_port);
U1214 : NOR2BX1 port map( AN => ID_INSTR_3_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_3_port);
U1215 : CLKINVX1 port map( A => ID_INSTR_31, Y => n987);
U1216 : CLKNAND2X2 port map( A => n1028, B => n995, Y =>
ID_INSTR_AFTER_CU_30_port);
U1217 : CLKINVX1 port map( A => ID_INSTR_30, Y => n995);
U1218 : NOR2BX1 port map( AN => ID_INSTR_2_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_2_port);
U1219 : CLKINVX1 port map( A => ID_INSTR_29, Y => n699);
U1220 : CLKNAND2X2 port map( A => n1028, B => n801, Y =>
ID_INSTR_AFTER_CU_28_port);
U1221 : CLKINVX1 port map( A => ID_INSTR_28, Y => n801);
U1222 : CLKINVX1 port map( A => ID_INSTR_27, Y => n704);
U1223 : CLKNAND2X2 port map( A => n1028, B => n993, Y =>
ID_INSTR_AFTER_CU_26_port);
U1224 : CLKINVX1 port map( A => ID_INSTR_26, Y => n993);
U1225 : CLKINVX1 port map( A => RF_ADD_RD1_4_port, Y => n897);
U1226 : NOR2BX1 port map( AN => RF_ADD_RD1_3_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_24_port);
U1227 : AND2X1 port map( A => RF_ADD_RD1_2_port, B => n1028, Y =>
ID_INSTR_AFTER_CU_23_port);
U1228 : AND2X1 port map( A => RF_ADD_RD1_1_port, B => n1028, Y =>
ID_INSTR_AFTER_CU_22_port);
U1229 : CLKINVX1 port map( A => RF_ADD_RD1_0_port, Y => n985);
U1230 : CLKINVX1 port map( A => RF_ADD_RD2_4_port, Y => n960);
U1231 : NOR2BX1 port map( AN => ID_INSTR_1_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_1_port);
U1232 : NOR2BX1 port map( AN => RF_ADD_RD2_3_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_19_port);
U1233 : AND2X1 port map( A => RF_ADD_RD2_2_port, B => n1028, Y =>
ID_INSTR_AFTER_CU_18_port);
U1234 : CLKINVX1 port map( A => RF_ADD_RD2_1_port, Y => n902);
U1235 : CLKINVX1 port map( A => RF_ADD_RD2_0_port, Y => n901);
U1236 : NOR2BX1 port map( AN => ID_INSTR_15_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_15_port);
U1237 : NOR2BX1 port map( AN => ID_INSTR_14_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_14_port);
U1238 : NOR2BX1 port map( AN => ID_INSTR_13_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_13_port);
U1239 : NOR2BX1 port map( AN => ID_INSTR_12_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_12_port);
U1240 : NOR2BX1 port map( AN => ID_INSTR_11_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_11_port);
U1241 : NOR2BX1 port map( AN => ID_INSTR_10_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_10_port);
U1242 : NOR2BX1 port map( AN => ID_INSTR_0_port, B => n1020, Y =>
ID_INSTR_AFTER_CU_0_port);
U1243 : MXI2X1 port map( A => n1029, B => n1030, S0 => n1031, Y =>
EX_SHIFTER_CW_1_port);
U1244 : NOR2X1 port map( A => n1032, B => n1033, Y => n1030);
U1245 : CLKINVX1 port map( A => n1034, Y => n1029);
U1246 : AOI31X1 port map( A0 => n1035, A1 => EX_INSTR_27_port, A2 => n1036,
B0 => n1037, Y => n1034);
U1247 : MXI2X1 port map( A => n1037, B => n1038, S0 => n1031, Y =>
EX_SHIFTER_CW_0_port);
U1248 : OAI32XL port map( A0 => n909, A1 => EX_INSTR_27_port, A2 => n1041,
B0 => n1042, B1 => n1043, Y => n1039);
U1249 : OAI21X1 port map( A0 => n1044, A1 => n1045, B0 => n1046, Y =>
EX_COMPARATOR_CW_4_port);
U1250 : OAI21X1 port map( A0 => n884, A1 => n1047, B0 => n1048, Y =>
EX_COMPARATOR_CW_3_port);
U1251 : OAI31X1 port map( A0 => n1045, A1 => n884, A2 => n1043, B0 => n1049,
Y => EX_COMPARATOR_CW_2_port);
U1252 : OAI31X1 port map( A0 => n1050, A1 => EX_INSTR_2_port, A2 => n1044,
B0 => n1051, Y => EX_COMPARATOR_CW_0_port);
U1253 : AOI33X1 port map( A0 => n1053, A1 => EX_INSTR_27_port, A2 => n1036,
B0 => n1054, B1 => n1055, B2 => n1056, Y => n1040);
U1254 : NOR3X1 port map( A => n1057, B => EX_INSTR_3_port, C => n1033, Y =>
n1054);
U1255 : NAND3XL port map( A => n1055, B => EX_INSTR_2_port, C => n1059, Y =>
n1042);
U1256 : NOR3X1 port map( A => n884, B => EX_INSTR_3_port, C =>
EX_INSTR_1_port, Y => n1059);
U1257 : NAND3XL port map( A => n1052, B => n1060, C => n1061, Y =>
EX_ALU_SEL_0_port);
U1258 : AOI211X1 port map( A0 => n1031, A1 => n1062, B0 =>
EX_COMPARATOR_CW_5_port, C0 =>
EX_COMPARATOR_CW_1_port, Y => n1061);
U1259 : OAI31X1 port map( A0 => n1063, A1 => n1043, A2 => n1050, B0 => n1064
, Y => EX_COMPARATOR_CW_1_port);
U1260 : CLKNAND2X2 port map( A => n1031, B => n1057, Y => n1063);
U1261 : OAI31X1 port map( A0 => n1050, A1 => n1057, A2 => n1044, B0 => n1065
, Y => EX_COMPARATOR_CW_5_port);
U1262 : CLKINVX1 port map( A => n1056, Y => n1044);
U1263 : AOI221XL port map( A0 => n1066, A1 => n1056, B0 => n1031, B1 =>
n1038, C0 => n1067, Y => n1052);
U1264 : CLKINVX1 port map( A => n1068, Y => n1067);
U1265 : NOR3X1 port map( A => n1033, B => n1032, C => n1043, Y => n1038);
U1266 : CLKINVX1 port map( A => EX_INSTR_0_port, Y => n1043);
U1267 : NOR2X1 port map( A => n884, B => EX_INSTR_0_port, Y => n1056);
U1268 : CLKINVX1 port map( A => n1031, Y => n884);
U1269 : CLKINVX1 port map( A => n1032, Y => n1066);
U1270 : NAND3XL port map( A => EX_INSTR_2_port, B => n1069, C => n1070, Y =>
n1032);
U1271 : NOR3X1 port map( A => EX_INSTR_3_port, B => EX_INSTR_5_port, C =>
EX_INSTR_4_port, Y => n1070);
U1272 : AO22X1 port map( A0 => EX_IMM16_EXT_31_port, A1 => n858, B0 =>
EX_REGB_31_port, B1 => n859, Y => EX_ALU_B_31_port);
U1273 : NOR2BX1 port map( AN => n861, B => n858, Y => n859);
U1274 : OAI211XL port map( A0 => n1058, A1 => n1071, B0 => n862, C0 => n1072
, Y => n861);
U1275 : CLKINVX1 port map( A => n858, Y => n862);
U1276 : NAND3BX1 port map( AN => n1074, B => n1075, C => n1076, Y => n858);
U1277 : AOI211X1 port map( A0 => n1077, A1 => EX_INSTR_31_port, B0 => n1053,
C0 => n919, Y => n1076);
U1278 : NOR2X1 port map( A => n1078, B => EX_INSTR_30_port, Y => n919);
U1279 : AOI33X1 port map( A0 => n1079, A1 => EX_INSTR_31_port, A2 => n1080,
B0 => n1081, B1 => EX_INSTR_29_port, B2 => n1082, Y
=> n1078);
U1280 : CLKINVX1 port map( A => n1083, Y => n1081);
U1281 : AOI21X1 port map( A0 => n1058, A1 => n1084, B0 => n1071, Y => n1077)
;
U1282 : NOR2X1 port map( A => n1036, B => n1085, Y => n1058);
U1283 : OAI31X1 port map( A0 => n1083, A1 => EX_INSTR_30_port, A2 => n918,
B0 => n1068, Y => n1074);
U1284 : AOI21X1 port map( A0 => n1036, A1 => n1035, B0 => n1037, Y => n1068)
;
U1285 : NOR3X1 port map( A => n909, B => n1086, C => n910, Y => n1037);
U1286 : CLKINVX1 port map( A => n910, Y => n1035);
U1287 : CLKNAND2X2 port map( A => n1073, B => n1087, Y => n910);
U1288 : CLKNAND2X2 port map( A => n1082, B => n1087, Y => n918);
U1289 : NOR3X1 port map( A => n1071, B => EX_INSTR_31_port, C => n1084, Y =>
n1031);
U1290 : NAND3XL port map( A => n1087, B => n1090, C => n1086, Y => n1071);
U1291 : CLKINVX1 port map( A => n1091, Y => n1089);
U1292 : AOI31X1 port map( A0 => n1055, A1 => n1057, A2 => EX_INSTR_1_port,
B0 => n1062, Y => n1091);
U1293 : NAND3XL port map( A => n1047, B => n1045, C => n1050, Y => n1062);
U1294 : NAND3XL port map( A => n1055, B => n1033, C => EX_INSTR_3_port, Y =>
n1050);
U1295 : NAND3XL port map( A => EX_INSTR_1_port, B => n1057, C => n1092, Y =>
n1045);
U1296 : NAND4X1 port map( A => n1092, B => EX_INSTR_0_port, C =>
EX_INSTR_2_port, D => n1033, Y => n1047);
U1297 : CLKINVX1 port map( A => EX_INSTR_1_port, Y => n1033);
U1298 : AND3X1 port map( A => EX_INSTR_5_port, B => n1069, C =>
EX_INSTR_3_port, Y => n1092);
U1299 : CLKINVX1 port map( A => EX_INSTR_2_port, Y => n1057);
U1300 : AND3X1 port map( A => n1069, B => n1093, C => EX_INSTR_5_port, Y =>
n1055);
U1301 : CLKINVX1 port map( A => EX_INSTR_4_port, Y => n1093);
U1302 : NOR3X1 port map( A => EX_INSTR_6_port, B => EX_INSTR_10_port, C =>
n1094, Y => n1069);
U1303 : OR3X1 port map( A => EX_INSTR_9_port, B => EX_INSTR_8_port, C =>
EX_INSTR_7_port, Y => n1094);
U1304 : OAI2BB1X1 port map( A0N => n1082, A1N => n1053, B0 => n1075, Y =>
n1088);
U1305 : AND3X1 port map( A => n1064, B => n1065, C => n1060, Y => n1075);
U1306 : AND4X1 port map( A => n1046, B => n1049, C => n1048, D => n1051, Y
=> n1060);
U1307 : NAND3XL port map( A => n1079, B => n1080, C => n1073, Y => n1051);
U1308 : NAND3XL port map( A => EX_INSTR_30_port, B => n1080, C => n1085, Y
=> n1048);
U1309 : CLKINVX1 port map( A => n909, Y => n1085);
U1310 : CLKNAND2X2 port map( A => EX_INSTR_28_port, B => EX_INSTR_26_port, Y
=> n909);
U1311 : OAI211XL port map( A0 => n1095, A1 => n1096, B0 => EX_INSTR_29_port,
C0 => n1082, Y => n1049);
U1312 : NOR2X1 port map( A => n1083, B => n1090, Y => n1096);
U1313 : CLKNAND2X2 port map( A => EX_INSTR_31_port, B => EX_INSTR_26_port, Y
=> n1083);
U1314 : NAND4X1 port map( A => EX_INSTR_30_port, B => n1079, C =>
EX_INSTR_27_port, D => EX_INSTR_29_port, Y => n1046)
;
U1315 : CLKINVX1 port map( A => n1084, Y => n1079);
U1316 : CLKNAND2X2 port map( A => n865, B => n1097, Y => n1084);
U1317 : NAND3XL port map( A => n1073, B => n1080, C => n1036, Y => n1065);
U1318 : NOR2X1 port map( A => n1097, B => EX_INSTR_26_port, Y => n1036);
U1319 : NAND3XL port map( A => n1080, B => n1097, C => n1095, Y => n1064);
U1320 : NOR2BX1 port map( AN => n1073, B => n865, Y => n1095);
U1321 : CLKINVX1 port map( A => EX_INSTR_26_port, Y => n865);
U1322 : NOR2X1 port map( A => n1090, B => EX_INSTR_31_port, Y => n1073);
U1323 : CLKINVX1 port map( A => EX_INSTR_30_port, Y => n1090);
U1324 : CLKINVX1 port map( A => EX_INSTR_28_port, Y => n1097);
U1325 : NOR2X1 port map( A => n1087, B => EX_INSTR_27_port, Y => n1080);
U1326 : CLKINVX1 port map( A => EX_INSTR_29_port, Y => n1087);
U1327 : CLKINVX1 port map( A => n1041, Y => n1053);
U1328 : CLKNAND2X2 port map( A => EX_INSTR_29_port, B => n917, Y => n1041);
U1329 : NOR2X1 port map( A => EX_INSTR_30_port, B => EX_INSTR_31_port, Y =>
n917);
U1330 : NOR2X1 port map( A => n1086, B => EX_INSTR_28_port, Y => n1082);
U1331 : CLKINVX1 port map( A => EX_INSTR_27_port, Y => n1086);
ID_IMM16_SHL2_0_port <= '0';
ID_IMM16_SHL2_1_port <= '0';
end SYN_RTL;
| lgpl-2.1 | 23324c6a9b3f3ad2adbe4b8b9b03b908 | 0.459188 | 2.730818 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd | 4 | 2,141 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity resistor is
port ( terminal node1, node2 : electrical );
end entity resistor;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
port ( terminal node1, node2 : electrical );
end entity capacitor;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity LF353_opamp is
port ( terminal plus, minus, output, pos_supply, neg_supply : electrical );
end entity LF353_opamp;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity active_filter is
end entity active_filter;
-- end not in book
library widget_parts, wasp_lib;
architecture component_based of active_filter is
-- declaration of signals, terminals, quantities, etc
-- ...
-- not in book
terminal input, node2, node3, node4, node7, node15, Vdd, Vss : electrical;
-- end not in book
begin
R1 : entity wasp_lib.resistor
port map ( node1 => input, node2 => node2 );
C1 : entity widget_parts.capacitor
port map ( node1 => node3, node2 => ground );
Amp1 : entity work.LF353_opamp
port map ( plus => node4, minus => node7, output => node15,
pos_supply => Vdd, neg_supply => Vss );
-- other component instantiations
-- ...
end architecture component_based;
| gpl-2.0 | 1135d3bddbf57d097246e951e3a5aae4 | 0.715553 | 3.843806 | false | false | false | false |
tgingold/ghdl | testsuite/synth/slice01/slice02.vhdl | 1 | 655 | library ieee;
use ieee.std_logic_1164.all;
entity slice02 is
generic (w: natural := 4);
port (clk : std_logic;
dat : std_logic_vector (7 downto 0);
mask : std_logic_vector (1 downto 0);
res : out std_logic_vector (7 downto 0));
end slice02;
architecture behav of slice02 is
begin
process(clk)
variable hi, lo : natural;
begin
if rising_edge (clk) then
res <= (others => '0');
for i in mask'range loop
if mask (i) = '1' then
lo := i * 4;
hi := lo + 3;
res (hi downto lo) <= dat (hi downto lo);
end if;
end loop;
end if;
end process;
end behav;
| gpl-2.0 | 03d5ded5fc3bd198714ea8bb2ddd1e9c | 0.557252 | 3.358974 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug077/repro7.vhdl | 1 | 552 | entity repro7 is
end repro7;
architecture behav of repro7 is
type my_rec is record
a : bit;
w : bit_vector;
end record;
procedure check (signal v : my_rec) is
begin
assert v.a = '0' and v.w = "01" severity failure;
end check;
procedure pack (signal a : bit; signal w : bit_vector) is
begin
check (v.a => a,
v.w => w);
end pack;
signal sa : bit;
signal sw : bit_vector (1 to 2);
begin
process
begin
sa <= '0';
sw <= "01";
wait for 0 ns;
pack (sa, sw);
wait;
end process;
end;
| gpl-2.0 | 1be8108f09c1c6ed418c0f61360ca73c | 0.574275 | 3.118644 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue30/definitions.vhdl | 2 | 63,457 | library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
package definitions is
-- flag bits
constant carry_bit: integer := 0;
constant add_sub_bit: integer := 1;
constant parity_overflow_bit: integer := 2;
constant half_carry_bit: integer := 4;
constant zero_bit: integer := 6;
constant sign_bit: integer := 7;
-- 8 bit register numbers
constant B: std_logic_vector(3 downto 0) := "0000";
constant B3: std_logic_vector(2 downto 0) := "000"; -- keep GHDL happy,
-- won't accept
-- bitslice of
-- constant in case
-- statements
constant C: std_logic_vector(3 downto 0) := "0001";
constant C3: std_logic_vector(2 downto 0) := "001";
constant D: std_logic_vector(3 downto 0) := "0010";
constant D3: std_logic_vector(2 downto 0) := "010";
constant E: std_logic_vector(3 downto 0) := "0011";
constant E3: std_logic_vector(2 downto 0) := "011";
constant H: std_logic_vector(3 downto 0) := "0100";
constant H3: std_logic_vector(2 downto 0) := "100";
constant L: std_logic_vector(3 downto 0) := "0101";
constant L3: std_logic_vector(2 downto 0) := "101";
constant memory_register: std_logic_vector(3 downto 0) := "0110";
constant memory_register3: std_logic_vector(2 downto 0) := "110";
constant A: std_logic_vector(3 downto 0) := "0111";
constant A3: std_logic_vector(2 downto 0) := "111";
constant one_register: std_logic_vector(3 downto 0) := "1000"; -- fixed constant of
-- one at register 8
-- in secondary ALU
-- register file
constant zero_register: std_logic_vector(3 downto 0) := "1001";
constant indexhigh: std_logic_vector(3 downto 0) := "1010";
constant indexlow: std_logic_vector(3 downto 0) := "1011";
constant bitreg: std_logic_vector(3 downto 0) := "1100";
constant not_bitreg: std_logic_vector(3 downto 0) := "1101";
constant SPhigh: std_logic_vector(3 downto 0) := "1110";
constant SPlow: std_logic_vector(3 downto 0) := "1111";
constant call_return_interrupt: std_logic_vector(3 downto 0) := "1000"; -- for sending call
-- return address
-- thru ALU, primary
-- register only
constant flags_register: std_logic_vector(3 downto 0) := "1000"; -- for sending flags
-- thru ALU -
-- multiplexed with
-- call return,
-- primary register
-- only
constant interrupt_register: std_logic_vector(3 downto 0) := "1000"; -- for sending
-- interrupt
-- register thru
-- ALU - multiplexed
-- with call return,
-- primary register
-- only
-- ALU operation codes
constant add_operation: std_logic_vector(4 downto 0) := "00000"; -- add without carry
constant adc_operation: std_logic_vector(4 downto 0) := "00001"; -- add with carry
constant sub_operation: std_logic_vector(4 downto 0) := "00010"; -- subtract without
-- carry
constant sbc_operation: std_logic_vector(4 downto 0) := "00011"; -- subtract with
-- carry
constant and_operation: std_logic_vector(4 downto 0) := "00100"; -- and
constant xor_operation: std_logic_vector(4 downto 0) := "00101"; -- xor
constant or_operation: std_logic_vector(4 downto 0) := "00110"; -- or
constant cmp_operation: std_logic_vector(4 downto 0) := "00111"; -- compare (subtract
-- and discard
-- results, set
-- flags
constant rlc_operation: std_logic_vector(4 downto 0) := "01000"; -- RLC
constant rrc_operation: std_logic_vector(4 downto 0) := "01001"; -- RRC
constant rl_operation: std_logic_vector(4 downto 0) := "01010"; -- RLA
constant rr_operation: std_logic_vector(4 downto 0) := "01011"; -- RRA
constant daa_operation: std_logic_vector(4 downto 0) := "01100"; -- DAA
constant cpl_operation: std_logic_vector(4 downto 0) := "01101"; -- CPL
constant scf_operation: std_logic_vector(4 downto 0) := "01110"; -- SCF
constant ccf_operation: std_logic_vector(4 downto 0) := "01111"; -- CCF
constant sla_operation: std_logic_vector(4 downto 0) := "10000"; -- SLA
constant sra_operation: std_logic_vector(4 downto 0) := "10001"; -- SRA
constant sll_operation: std_logic_vector(4 downto 0) := "10010"; -- SLL
constant srl_operation: std_logic_vector(4 downto 0) := "10011"; -- SRL
constant bit_operation: std_logic_vector(4 downto 0) := "10100"; -- BIT
constant res_operation: std_logic_vector(4 downto 0) := "10101"; -- RES
constant set_operation: std_logic_vector(4 downto 0) := "10110"; -- SET
constant in16_operation: std_logic_vector(4 downto 0) := "10111"; -- in r, (c)
constant rld_operation: std_logic_vector(4 downto 0) := "11000"; -- RLD
constant rrd_operation: std_logic_vector(4 downto 0) := "11001"; -- RRD
constant blockterm16_operation: std_logic_vector(4 downto 0) := "11010"; -- block instruction
-- termination:
-- P/V = 0 when
-- BC = 0
-- ALU operation flags masks - the ones that change are listed, others are masked out
constant alu_mask: std_logic_vector(7 downto 0) := ( carry_bit => '1',
add_sub_bit => '1',
parity_overflow_bit => '1',
half_carry_bit => '1',
zero_bit => '1',
sign_bit => '1',
others => '0'
);
-- Block operation load masks
constant block_load_mask: std_logic_vector(7 downto 0) := ( add_sub_bit => '1',
parity_overflow_bit => '1',
half_carry_bit => '1',
others => '0'
);
constant block_compare_mask1: std_logic_vector(7 downto 0) := ( add_sub_bit => '1',
half_carry_bit => '1',
zero_bit => '1',
sign_bit => '1',
others => '0'
);
constant block_compare_mask2: std_logic_vector(7 downto 0) := ( parity_overflow_bit => '1',
others => '0'
);
constant block_io_mask: std_logic_vector(7 downto 0) := ( add_sub_bit => '1',
zero_bit => '1',
others => '0'
);
-- bit masks for bit oriented instructions
constant bit7mask: std_logic_vector(7 downto 0) := (7 => '1', others => '0');
constant bit6mask: std_logic_vector(7 downto 0) := (6 => '1', others => '0');
constant bit5mask: std_logic_vector(7 downto 0) := (5 => '1', others => '0');
constant bit4mask: std_logic_vector(7 downto 0) := (4 => '1', others => '0');
constant bit3mask: std_logic_vector(7 downto 0) := (3 => '1', others => '0');
constant bit2mask: std_logic_vector(7 downto 0) := (2 => '1', others => '0');
constant bit1mask: std_logic_vector(7 downto 0) := (1 => '1', others => '0');
constant bit0mask: std_logic_vector(7 downto 0) := (0 => '1', others => '0');
-- address bus selector
constant address_bus_source_BC: std_logic_vector(3 downto 0) := x"0";
constant address_bus_source_DE: std_logic_vector(3 downto 0) := x"1";
constant address_bus_source_HL: std_logic_vector(3 downto 0) := x"2";
constant address_bus_source_SP: std_logic_vector(3 downto 0) := x"3";
constant address_bus_source_PC: std_logic_vector(3 downto 0) := x"4";
constant address_bus_source_operand: std_logic_vector(3 downto 0) := x"5";
constant address_bus_source_operand1: std_logic_vector(3 downto 0) := x"6";
constant address_bus_source_port8: std_logic_vector(3 downto 0) := x"7";
constant address_bus_source_index: std_logic_vector(3 downto 0) := x"8";
-- program counter selector
constant pc_source_next: std_logic_vector(3 downto 0) := x"0"; -- PC + 1
constant pc_source_operand: std_logic_vector(3 downto 0) := x"1"; -- operand
constant pc_source_HL: std_logic_vector(3 downto 0) := x"2"; -- PCHL
constant pc_source_return: std_logic_vector(3 downto 0) := x"3"; -- return
-- address
constant pc_source_next_next: std_logic_vector(3 downto 0) := x"4"; -- PC + 2
constant pc_source_rst: std_logic_vector(3 downto 0) := x"5"; -- RST nn
constant pc_source_index_register: std_logic_vector(3 downto 0) := x"6"; -- PCIX and PCIY
constant pc_source_jr: std_logic_vector(3 downto 0) := x"7"; -- JR offset
constant pc_source_block_repeat: std_logic_vector(3 downto 0) := x"8"; -- for
-- interrupted
-- block repeats
constant pc_source_reset: std_logic_vector(3 downto 0) := x"f"; -- sets PC
-- vector
-- after reset
-- initial program counter. Zilog spec says it is always zero, but often autojump hardware is
-- implemented to change this. I have the luxury of specifying the initial program counter as I see
-- fit.
constant PC_start_address: std_logic_vector(15 downto 0) := x"0000";
-- SP source mux input definitins
constant SPsource_databus: std_logic_vector(1 downto 0) := "00"; -- select
-- databus
constant SPsource_increment: std_logic_vector(1 downto 0) := "01"; -- select SP + 1
constant SPsource_decrement: std_logic_vector(1 downto 0) := "10"; -- select SP - 1
-- data output mux selectors
constant data_out_selector_databus: std_logic_vector(2 downto 0) := "000"; -- select
-- databus
constant data_out_selector_H: std_logic_vector(2 downto 0) := "001"; -- select
-- temporary
-- register
-- for
-- register
-- H
constant data_out_selector_L: std_logic_vector(2 downto 0) := "010"; -- select
-- temporary
-- register
-- for
-- register
-- L
constant data_out_selector_indexhigh: std_logic_vector(2 downto 0) := "011"; -- select
-- temporary
-- register
-- for
-- register
-- IXhigh
constant data_out_selector_indexlow: std_logic_vector(2 downto 0) := "100"; -- select
-- temporary
-- register
-- for
-- register
-- IXlow
constant data_out_selector_rrd_rld_output: std_logic_vector(2 downto 0) := "101"; -- select
-- secondary
-- ALU
-- output
-- (RLD and
-- RRD)
-- select among return address, flags, or interrupt vector register to go through the ALU.
constant selectRetAddr: std_logic_vector(1 downto 0) := "00"; -- select return
-- address
constant selectFlags: std_logic_vector(1 downto 0) := "01"; -- select flags
constant selectInterruptVector: std_logic_vector(1 downto 0) := "10"; -- select
-- interrupt
-- vector
-- register
-- operand register selection
constant operandSelectLow: std_logic := '0'; -- selects operand register low byte
constant operandSelectHigh: std_logic := '1'; -- selects operand register bigh byte
-- assertion and deassertion of control lines
constant assert_m1: std_logic := '1';
constant deassert_m1: std_logic := '0';
constant assert_write: std_logic := '1';
constant deassert_write: std_logic := '0';
constant assert_read: std_logic := '1';
constant deassert_read: std_logic := '0';
constant assert_iorq: std_logic := '1';
constant deassert_iorq: std_logic := '0';
constant assert_mreq: std_logic := '1';
constant deassert_mreq: std_logic := '0';
-- Index register selection
constant SelectIndexIX: std_logic := '0';
constant SelectIndexIY: std_logic := '1';
-- Return address byte selection
constant RetAddrLow: std_logic := '0';
constant RetAddrHigh: std_logic := '1';
-- Enable and disable writing to instruction register
constant disableOpcodeWrite: std_logic := '0';
constant enableOpcodeWrite: std_logic := '1';
-- Enable and disable XCHG hardware
constant disableXCHG: std_logic := '0';
constant enableXCHG: std_logic := '1';
-- For master and slave control of the address, data and control busses
constant masterControl: std_logic := '1';
constant slaveControl: std_logic := '0';
constant deassert_halted: std_logic := '0';
constant assert_halted: std_logic := '1';
-- For control of source of ALU operation
constant selectVHDL_ALU_operation: std_logic := '0';
constant selectOpcode_ALU_operation: std_logic := '1';
-- for source of primary and secondary ALU operand registers
constant selectOpcodeRegister: std_logic := '0';
constant selectVHDLRegister: std_logic := '1';
-- for register saving
constant save: std_logic := '1';
constant DontSave: std_logic := '0';
-- for choosing source of flags data
constant ALUflags: std_logic := '0';
constant POPflags: std_logic := '1';
-- for general clock enable and disable
constant clockEnable: std_logic := '1';
constant clockDisable: std_logic := '0';
-- for invalid instruction detector
constant safe: std_logic := '0';
constant fail: std_logic := '1';
-- for interrupt modes
constant IM_0: std_logic_vector(1 downto 0) := "00";
constant IM_1: std_logic_vector(1 downto 0) := "01";
constant IM_2: std_logic_vector(1 downto 0) := "10";
constant width_is_8: positive := 8;
-- State numbers. Done this way so state numbers can be stored and used as a return address
-- common to all opcodes
constant initialise: std_logic_vector(11 downto 0) := x"000"; -- initialise
-- processor,
-- enters on
-- rising edge of
-- clk_out
constant initialise1: std_logic_vector(11 downto 0) := x"001"; -- second
-- initialisation
-- state
constant initialise2: std_logic_vector(11 downto 0) := x"002"; -- third
-- initialisation
-- state
constant initialise3: std_logic_vector(11 downto 0) := x"003"; -- fourth
-- initialisation
-- state
constant opcode: std_logic_vector(11 downto 0) := x"004"; -- assert pc address
-- drivers and
-- m1n = '0'
-- for 1st opcode
-- byte, rising edge
-- of clock, done
-- in last state of
-- previous
-- instruction
constant opcode_mreq: std_logic_vector(11 downto 0) := x"005"; -- assert
-- mreqn = '0' and
-- rdn = '0' on
-- falling edge of
-- clock
constant opcode_latch: std_logic_vector(11 downto 0) := x"006"; -- latch opcode byte
-- on next rising
-- edge of clock
-- with waitn = '1',
-- rising edge of
-- clock
constant decode_opcode: std_logic_vector(11 downto 0) := x"007"; -- decode first
-- opcode
constant invalid: std_logic_vector(11 downto 0) := x"008"; -- state name for
-- invalid return
-- state and illegal
-- instruction
-- states for BUSRQ handling
constant busrq: std_logic_vector(11 downto 0) := x"009";
-- New PC state for use with jr, jp, ret, call, rst
constant NewPC: std_logic_vector(11 downto 0) := x"00f";
-- opcodes in order presented by z80.info/decoding. Number of states (initially) conforms
-- to number of clock cycles as advertised in the Z80 data sheet. States are added because
-- I process information on both positive and negative transitions of the clock. These
-- will be removed if they are not needed. Memory and port I/O operations are always
-- initiated at the positive going edge of the clock. Instructions that do not appear here
-- are processed entirely during the decoding phase of operation.
-- NOP states, 4 clock cycles, all required for timing loops, 1 m1 cycle
constant nop4: std_logic_vector(11 downto 0) := x"010"; -- instruction
-- origin + 3 rising
-- edges
constant nop5: std_logic_vector(11 downto 0) := x"011"; -- instruction
-- origin + 4 rising
-- edges
-- DJNZ, 8/13 cycles (met, not met), 1 m1 cycle
constant djnz4: std_logic_vector(11 downto 0) := x"030";
-- JR, 12 cycles, 1 m1 cycle
constant jr4: std_logic_vector(11 downto 0) := x"040";
constant jr5: std_logic_vector(11 downto 0) := x"041";
constant jr6: std_logic_vector(11 downto 0) := x"042";
constant jr7: std_logic_vector(11 downto 0) := x"043";
-- JR conditional, 12/7 cycles (met/not met), 1 m1 cycle
-- need one state to test condition, transfer control to jr code
-- Number of cycles = one or two more than jr
constant jrcc4: std_logic_vector(11 downto 0) := x"050";
constant jrcc5: std_logic_vector(11 downto 0) := x"051";
-- LD rp, immediate, 10 cycles, 1 m1 cycle
constant ldrpi4: std_logic_vector(11 downto 0) := x"060";
constant ldrpi5: std_logic_vector(11 downto 0) := x"061";
-- ADD HL, rp, 11 clock cycles, 1 m1 cycle
constant addhlrp4: std_logic_vector(11 downto 0) := x"070";
constant addhlrp5: std_logic_vector(11 downto 0) := x"071";
-- LDAX rp, 7 cycles, 1 m1 cycle
constant ldax4: std_logic_vector(11 downto 0) := x"080";
constant ldax5: std_logic_vector(11 downto 0) := x"081";
-- STAX rp, 7 cycles, 1 m1 cycle
constant stax4: std_logic_vector(11 downto 0) := x"090";
constant stax5: std_logic_vector(11 downto 0) := x"091";
-- LDA nn, 13 cycles, 1 m1 cycle
constant lda4: std_logic_vector(11 downto 0) := x"0a0";
constant lda5: std_logic_vector(11 downto 0) := x"0a1";
constant lda6: std_logic_vector(11 downto 0) := x"0a2";
constant lda7: std_logic_vector(11 downto 0) := x"0a3";
-- STA nn, 13 cycles, 1 m1 cycle
constant sta4: std_logic_vector(11 downto 0) := x"0b0";
constant sta5: std_logic_vector(11 downto 0) := x"0b1";
-- LHLD (nn), 16 cycles, 1 m1 cycle
constant ldhl4: std_logic_vector(11 downto 0) := x"0c0";
constant ldhl5: std_logic_vector(11 downto 0) := x"0c1";
constant ldhl6: std_logic_vector(11 downto 0) := x"0c2";
constant ldhl7: std_logic_vector(11 downto 0) := x"0c3";
constant ldhl8: std_logic_vector(11 downto 0) := x"0c4";
-- SHLD (nn), 16 cycles, 1 m1 cycle
constant sthl4: std_logic_vector(11 downto 0) := x"0d0";
constant sthl5: std_logic_vector(11 downto 0) := x"0d1";
constant sthl6: std_logic_vector(11 downto 0) := x"0d2";
constant sthl7: std_logic_vector(11 downto 0) := x"0d3";
-- 16 bit increment/decrement, 6 cycles, 1 m1 cycle
constant incdec16_4: std_logic_vector(11 downto 0) := x"0e0";
constant incdec16_5: std_logic_vector(11 downto 0) := x"0e1";
constant incdec16_6: std_logic_vector(11 downto 0) := x"0e2";
constant incdec16_7: std_logic_vector(11 downto 0) := x"0e3";
-- 8 bit register/memory increment/decrement, 11 cycles, 1 m1 cycle
constant incdec8_4: std_logic_vector(11 downto 0) := x"0f0";
-- 8 bit load immediate, 7 cycles, 1 m1 cycle
constant ldi4: std_logic_vector(11 downto 0) := x"100";
-- DAA, 4 cycles, 1 m1 cycle
constant daa4: std_logic_vector(11 downto 0) := x"110";
constant daa5: std_logic_vector(11 downto 0) := x"111";
constant daa6: std_logic_vector(11 downto 0) := x"112";
constant daa7: std_logic_vector(11 downto 0) := x"113";
-- SCF/CCF, 4 cycles, 1 m1 cycle
-- main processing done at instruction decoder stage
constant scf_ccf_save: std_logic_vector(11 downto 0) := x"120";
-- inter-register 8 bit loading, 4 cycles, 1 m1 cycle
constant irld4: std_logic_vector(11 downto 0) := x"130";
constant irld5: std_logic_vector(11 downto 0) := x"131";
-- HALT, 4 cycles, 1 m1 cycle, may trim this to three
-- cycles initially plus one cycle per instruction thereafter
constant halt4: std_logic_vector(11 downto 0) := x"140";
constant halt5: std_logic_vector(11 downto 0) := x"141";
constant halt6: std_logic_vector(11 downto 0) := x"142";
constant halt7: std_logic_vector(11 downto 0) := x"143";
-- alu operations on registers, 4 cycles, 1 m1 cycle
constant alu4: std_logic_vector(11 downto 0) := x"150";
-- POP, 10 cycles, 1 m1 cycle
constant pop4: std_logic_vector(11 downto 0) := x"160";
constant pop5: std_logic_vector(11 downto 0) := x"161";
constant pop6: std_logic_vector(11 downto 0) := x"162";
constant pop7: std_logic_vector(11 downto 0) := x"163";
constant pop8: std_logic_vector(11 downto 0) := x"164";
-- RET unconditional, 10 cycles, 1 m1 cycle
constant ret4: std_logic_vector(11 downto 0) := x"170";
constant ret5: std_logic_vector(11 downto 0) := x"171";
constant ret6: std_logic_vector(11 downto 0) := x"172";
constant ret7: std_logic_vector(11 downto 0) := x"173";
constant ret8: std_logic_vector(11 downto 0) := x"174";
constant ret9: std_logic_vector(11 downto 0) := x"175";
-- JP HL, 4 cycles,1 m1 cycle
constant jphl4: std_logic_vector(11 downto 0) := x"180";
-- LD SP, HL, 6 cycles, 1 m1 cycle
constant sphl4: std_logic_vector(11 downto 0) := x"190";
-- JP conditional, 10 cycles met or not, 1 m1 cycle
-- use one state to determine if ret is to be executed, then transfer to JP unconditional if so.
constant jpcc4: std_logic_vector(11 downto 0) := x"1a0";
constant jpcc5: std_logic_vector(11 downto 0) := x"1a1";
-- JP unconditional, 10 cycles, 1 m1 cycle
constant jp4: std_logic_vector(11 downto 0) := x"1b0";
constant jp5: std_logic_vector(11 downto 0) := x"1b1";
constant jp6: std_logic_vector(11 downto 0) := x"1b2";
-- CB prefix, must obtain next instruction byte
constant cb4: std_logic_vector(11 downto 0) := x"1c0";
constant cb5: std_logic_vector(11 downto 0) := x"1c1";
-- save results from CB prefixed opcodes other than BIT, SET, and RES
constant bitsave: std_logic_vector(11 downto 0) := x"1e0";
-- common state for save and load 16 bit registers with ED prefix
constant rp16io: std_logic_vector(11 downto 0) := x"1f0";
-- BIT
constant bit6: std_logic_vector(11 downto 0) := x"200";
constant bit7: std_logic_vector(11 downto 0) := x"201";
-- RES
constant res6: std_logic_vector(11 downto 0) := x"210";
-- SET
constant set6: std_logic_vector(11 downto 0) := x"220";
-- end of CB prefixed opcodes
-- 8 bit output of accumulator to 8 bit port address, 11 cycles, 1 m1 cycle
constant out4: std_logic_vector(11 downto 0) := x"230";
constant out5: std_logic_vector(11 downto 0) := x"231";
constant out6: std_logic_vector(11 downto 0) := x"232";
constant out7: std_logic_vector(11 downto 0) := x"233";
constant out8: std_logic_vector(11 downto 0) := x"234";
-- 8 bit input of accumulator from 8 bit port address, 11 cycles, 1 m1 cycle
constant in4: std_logic_vector(11 downto 0) := x"240";
constant in5: std_logic_vector(11 downto 0) := x"241";
constant in6: std_logic_vector(11 downto 0) := x"242";
constant in7: std_logic_vector(11 downto 0) := x"243";
-- EX (SP), HL, 19 cycles, 1 m1 cycle
constant xthl4: std_logic_vector(11 downto 0) := x"250";
constant xthl5: std_logic_vector(11 downto 0) := x"251";
constant xthl6: std_logic_vector(11 downto 0) := x"252";
constant xthl7: std_logic_vector(11 downto 0) := x"253";
constant xthl8: std_logic_vector(11 downto 0) := x"254";
constant xthl9: std_logic_vector(11 downto 0) := x"255";
constant xthl10: std_logic_vector(11 downto 0) := x"256";
-- DI, 4 cycles, 1 m1 cycle
constant di4: std_logic_vector(11 downto 0) := x"270";
constant di5: std_logic_vector(11 downto 0) := x"271";
constant di6: std_logic_vector(11 downto 0) := x"272";
constant di7: std_logic_vector(11 downto 0) := x"273";
-- EI, 4 cycles, 1 m1 cycle
constant ei4: std_logic_vector(11 downto 0) := x"280";
constant ei5: std_logic_vector(11 downto 0) := x"281";
constant ei6: std_logic_vector(11 downto 0) := x"282";
constant ei7: std_logic_vector(11 downto 0) := x"283";
-- PUSH, 10 cycles, 1 m1 cycle
constant push4: std_logic_vector(11 downto 0) := x"2a0";
constant push5: std_logic_vector(11 downto 0) := x"2a1";
constant push6: std_logic_vector(11 downto 0) := x"2a2";
constant push7: std_logic_vector(11 downto 0) := x"2a3";
-- CALL unconditional, 17 clock cycles, 1 m1 cycle
constant call4: std_logic_vector(11 downto 0) := x"2b0";
constant call5: std_logic_vector(11 downto 0) := x"2b1";
constant call6: std_logic_vector(11 downto 0) := x"2b2";
constant call7: std_logic_vector(11 downto 0) := x"2b3";
constant call8: std_logic_vector(11 downto 0) := x"2b4";
-- end of DD prefixed opcodes
-- ED prefix, must obtain next instruction byte
constant ed4: std_logic_vector(11 downto 0) := x"2c0";
constant ed5: std_logic_vector(11 downto 0) := x"2c1";
constant ed6: std_logic_vector(11 downto 0) := x"2c2";
constant ed7: std_logic_vector(11 downto 0) := x"2c3";
constant ed8: std_logic_vector(11 downto 0) := x"2c4";
constant ed9: std_logic_vector(11 downto 0) := x"2c5";
constant ed10: std_logic_vector(11 downto 0) := x"2c6";
-- 8 bit input to register from a 16 bit port address, 12 cycles, 1 m1 cycle
constant in16_5: std_logic_vector(11 downto 0) := x"2d0";
constant in16_6: std_logic_vector(11 downto 0) := x"2d1";
-- 8 bit output to register from a 16 bit port address, 12 cycles, 1 m1 cycle
constant out16_5: std_logic_vector(11 downto 0) := x"2e0";
constant out16_6: std_logic_vector(11 downto 0) := x"2e1";
-- 16 bit ADC
constant adc_sbc_16_5: std_logic_vector(11 downto 0) := x"2f0";
-- store register pair to immediate address
constant strp16_5: std_logic_vector(11 downto 0) := x"300";
constant strp16_6: std_logic_vector(11 downto 0) := x"301";
-- load register pair from immediate address
constant ldrp16_5: std_logic_vector(11 downto 0) := x"310";
constant ldrp16_6: std_logic_vector(11 downto 0) := x"311";
constant ldrp16_7: std_logic_vector(11 downto 0) := x"312";
-- NEG
constant neg6: std_logic_vector(11 downto 0) := x"320";
-- RETN
constant retn6: std_logic_vector(11 downto 0) := x"330";
constant retn7: std_logic_vector(11 downto 0) := x"331";
constant retn8: std_logic_vector(11 downto 0) := x"332";
constant retn9: std_logic_vector(11 downto 0) := x"333";
constant retn10: std_logic_vector(11 downto 0) := x"334";
constant retn11: std_logic_vector(11 downto 0) := x"335";
constant retn12: std_logic_vector(11 downto 0) := x"336";
constant retn13: std_logic_vector(11 downto 0) := x"337";
constant retn14: std_logic_vector(11 downto 0) := x"338";
constant retn15: std_logic_vector(11 downto 0) := x"339";
constant retn16: std_logic_vector(11 downto 0) := x"33a";
constant retn17: std_logic_vector(11 downto 0) := x"33b";
constant retn18: std_logic_vector(11 downto 0) := x"33c";
constant retn19: std_logic_vector(11 downto 0) := x"33d";
constant retn20: std_logic_vector(11 downto 0) := x"33e";
constant retn21: std_logic_vector(11 downto 0) := x"33f";
constant retn22: std_logic_vector(11 downto 0) := x"340";
constant retn23: std_logic_vector(11 downto 0) := x"342";
constant retn24: std_logic_vector(11 downto 0) := x"343";
constant retn25: std_logic_vector(11 downto 0) := x"344";
-- RETI
constant reti6: std_logic_vector(11 downto 0) := x"350";
constant reti7: std_logic_vector(11 downto 0) := x"351";
constant reti8: std_logic_vector(11 downto 0) := x"352";
constant reti9: std_logic_vector(11 downto 0) := x"353";
constant reti10: std_logic_vector(11 downto 0) := x"354";
constant reti11: std_logic_vector(11 downto 0) := x"355";
constant reti12: std_logic_vector(11 downto 0) := x"356";
constant reti13: std_logic_vector(11 downto 0) := x"357";
constant reti14: std_logic_vector(11 downto 0) := x"358";
constant reti15: std_logic_vector(11 downto 0) := x"359";
constant reti16: std_logic_vector(11 downto 0) := x"35a";
constant reti17: std_logic_vector(11 downto 0) := x"35b";
constant reti18: std_logic_vector(11 downto 0) := x"35c";
constant reti19: std_logic_vector(11 downto 0) := x"35d";
constant reti20: std_logic_vector(11 downto 0) := x"35e";
constant reti21: std_logic_vector(11 downto 0) := x"35f";
constant reti22: std_logic_vector(11 downto 0) := x"360";
constant reti23: std_logic_vector(11 downto 0) := x"361";
constant reti24: std_logic_vector(11 downto 0) := x"362";
constant reti25: std_logic_vector(11 downto 0) := x"363";
-- IM n
constant im0_6: std_logic_vector(11 downto 0) := x"370";
constant im0_7: std_logic_vector(11 downto 0) := x"371";
constant im0_8: std_logic_vector(11 downto 0) := x"372";
constant im0_9: std_logic_vector(11 downto 0) := x"373";
constant im0_10: std_logic_vector(11 downto 0) := x"374";
constant im0_11: std_logic_vector(11 downto 0) := x"375";
constant im0_12: std_logic_vector(11 downto 0) := x"376";
constant im0_13: std_logic_vector(11 downto 0) := x"377";
constant im1_6: std_logic_vector(11 downto 0) := x"380";
constant im1_7: std_logic_vector(11 downto 0) := x"381";
constant im1_8: std_logic_vector(11 downto 0) := x"382";
constant im1_9: std_logic_vector(11 downto 0) := x"383";
constant im1_10: std_logic_vector(11 downto 0) := x"384";
constant im1_11: std_logic_vector(11 downto 0) := x"385";
constant im1_12: std_logic_vector(11 downto 0) := x"386";
constant im1_13: std_logic_vector(11 downto 0) := x"387";
constant im2_6: std_logic_vector(11 downto 0) := x"390";
constant im2_7: std_logic_vector(11 downto 0) := x"391";
constant im2_8: std_logic_vector(11 downto 0) := x"392";
constant im2_9: std_logic_vector(11 downto 0) := x"393";
constant im2_10: std_logic_vector(11 downto 0) := x"394";
constant im2_11: std_logic_vector(11 downto 0) := x"395";
constant im2_12: std_logic_vector(11 downto 0) := x"396";
constant im2_13: std_logic_vector(11 downto 0) := x"397";
-- LD I, A
constant ldia5: std_logic_vector(11 downto 0) := x"3a0";
constant ldia6: std_logic_vector(11 downto 0) := x"3a1";
constant ldia7: std_logic_vector(11 downto 0) := x"3a2";
constant ldia8: std_logic_vector(11 downto 0) := x"3a3";
constant ldia9: std_logic_vector(11 downto 0) := x"3a4";
constant ldia10: std_logic_vector(11 downto 0) := x"3a5";
constant ldia11: std_logic_vector(11 downto 0) := x"3a6";
constant ldia12: std_logic_vector(11 downto 0) := x"3a7";
constant ldia13: std_logic_vector(11 downto 0) := x"3a8";
constant ldia14: std_logic_vector(11 downto 0) := x"3a9";
-- LD R, A, ignore this instruction
-- LD A, I
constant ldai5: std_logic_vector(11 downto 0) := x"3b0";
constant ldai6: std_logic_vector(11 downto 0) := x"3b1";
constant ldai7: std_logic_vector(11 downto 0) := x"3b2";
constant ldai8: std_logic_vector(11 downto 0) := x"3b3";
constant ldai9: std_logic_vector(11 downto 0) := x"3b4";
constant ldai10: std_logic_vector(11 downto 0) := x"3b5";
constant ldai11: std_logic_vector(11 downto 0) := x"3b6";
constant ldai12: std_logic_vector(11 downto 0) := x"3b7";
constant ldai13: std_logic_vector(11 downto 0) := x"3b8";
constant ldai14: std_logic_vector(11 downto 0) := x"3b9";
-- LD A, R, ignore this instruction
-- RRD and RLD
constant rrd_rld5: std_logic_vector(11 downto 0) := x"3c0";
-- Block instructions
-- LDI
constant bldi5: std_logic_vector(11 downto 0) := x"3d0";
constant bldi6: std_logic_vector(11 downto 0) := x"3d1";
constant bldi7: std_logic_vector(11 downto 0) := x"3d2";
constant bldi8: std_logic_vector(11 downto 0) := x"3d3";
constant bldi9: std_logic_vector(11 downto 0) := x"3d4";
constant bldi10: std_logic_vector(11 downto 0) := x"3d5";
constant bldi11: std_logic_vector(11 downto 0) := x"3d6";
constant bldi12: std_logic_vector(11 downto 0) := x"3d7";
constant bldi13: std_logic_vector(11 downto 0) := x"3d8";
constant bldi14: std_logic_vector(11 downto 0) := x"3d9";
-- CPI
constant bcpi5: std_logic_vector(11 downto 0) := x"3e0";
constant bcpi6: std_logic_vector(11 downto 0) := x"3e1";
constant bcpi7: std_logic_vector(11 downto 0) := x"3e2";
constant bcpi8: std_logic_vector(11 downto 0) := x"3e3";
constant bcpi9: std_logic_vector(11 downto 0) := x"3e4";
constant bcpi10: std_logic_vector(11 downto 0) := x"3e5";
constant bcpi11: std_logic_vector(11 downto 0) := x"3e6";
-- INI
constant bini5: std_logic_vector(11 downto 0) := x"3f0";
constant bini6: std_logic_vector(11 downto 0) := x"3f1";
constant bini7: std_logic_vector(11 downto 0) := x"3f2";
constant bini8: std_logic_vector(11 downto 0) := x"3f3";
constant bini9: std_logic_vector(11 downto 0) := x"3f4";
constant bini10: std_logic_vector(11 downto 0) := x"3f5";
constant bini11: std_logic_vector(11 downto 0) := x"3f6";
-- OUTI
constant bouti5: std_logic_vector(11 downto 0) := x"400";
constant bouti6: std_logic_vector(11 downto 0) := x"401";
constant bouti7: std_logic_vector(11 downto 0) := x"402";
constant bouti8: std_logic_vector(11 downto 0) := x"403";
constant bouti9: std_logic_vector(11 downto 0) := x"404";
constant bouti10: std_logic_vector(11 downto 0) := x"405";
constant bouti11: std_logic_vector(11 downto 0) := x"406";
constant bouti12: std_logic_vector(11 downto 0) := x"407";
-- LDD
constant bldd5: std_logic_vector(11 downto 0) := x"410";
constant bldd6: std_logic_vector(11 downto 0) := x"411";
constant bldd7: std_logic_vector(11 downto 0) := x"412";
constant bldd8: std_logic_vector(11 downto 0) := x"413";
constant bldd9: std_logic_vector(11 downto 0) := x"414";
constant bldd10: std_logic_vector(11 downto 0) := x"415";
constant bldd11: std_logic_vector(11 downto 0) := x"416";
constant bldd12: std_logic_vector(11 downto 0) := x"417";
constant bldd13: std_logic_vector(11 downto 0) := x"418";
-- CPD
constant bcpd5: std_logic_vector(11 downto 0) := x"420";
constant bcpd6: std_logic_vector(11 downto 0) := x"421";
constant bcpd7: std_logic_vector(11 downto 0) := x"422";
constant bcpd8: std_logic_vector(11 downto 0) := x"423";
constant bcpd9: std_logic_vector(11 downto 0) := x"424";
constant bcpd10: std_logic_vector(11 downto 0) := x"425";
constant bcpd11: std_logic_vector(11 downto 0) := x"426";
-- IND
constant bind5: std_logic_vector(11 downto 0) := x"430";
constant bind6: std_logic_vector(11 downto 0) := x"431";
constant bind7: std_logic_vector(11 downto 0) := x"432";
constant bind8: std_logic_vector(11 downto 0) := x"433";
constant bind9: std_logic_vector(11 downto 0) := x"434";
constant bind10: std_logic_vector(11 downto 0) := x"435";
constant bind11: std_logic_vector(11 downto 0) := x"436";
-- OUTD
constant boutd5: std_logic_vector(11 downto 0) := x"440";
constant boutd6: std_logic_vector(11 downto 0) := x"441";
constant boutd7: std_logic_vector(11 downto 0) := x"442";
constant boutd8: std_logic_vector(11 downto 0) := x"443";
constant boutd9: std_logic_vector(11 downto 0) := x"444";
constant boutd10: std_logic_vector(11 downto 0) := x"445";
constant boutd11: std_logic_vector(11 downto 0) := x"446";
-- LDIR
constant bldir5: std_logic_vector(11 downto 0) := x"450";
constant bldir6: std_logic_vector(11 downto 0) := x"451";
--constant bldir7: std_logic_vector(11 downto 0) := x"452";
--constant bldir8: std_logic_vector(11 downto 0) := x"453";
--constant bldir9: std_logic_vector(11 downto 0) := x"454";
--constant bldir10: std_logic_vector(11 downto 0) := x"455";
--constant bldir11: std_logic_vector(11 downto 0) := x"456";
--constant bldir12: std_logic_vector(11 downto 0) := x"457";
--constant bldir13: std_logic_vector(11 downto 0) := x"458";
--constant bldir14: std_logic_vector(11 downto 0) := x"459";
--constant bldir15: std_logic_vector(11 downto 0) := x"45a";
--constant bldir16: std_logic_vector(11 downto 0) := x"45b";
--constant bldir17: std_logic_vector(11 downto 0) := x"45c";
--constant bldir18: std_logic_vector(11 downto 0) := x"45d";
--constant bldir19: std_logic_vector(11 downto 0) := x"45e";
--constant bldir20: std_logic_vector(11 downto 0) := x"45f";
--constant bldir21: std_logic_vector(11 downto 0) := x"460";
--constant bldir22: std_logic_vector(11 downto 0) := x"461";
--constant bldir23: std_logic_vector(11 downto 0) := x"462";
--constant bldir24: std_logic_vector(11 downto 0) := x"463";
--constant bldir25: std_logic_vector(11 downto 0) := x"464";
--constant bldir26: std_logic_vector(11 downto 0) := x"465";
--constant bldir27: std_logic_vector(11 downto 0) := x"466";
--constant bldir28: std_logic_vector(11 downto 0) := x"467";
--constant bldir29: std_logic_vector(11 downto 0) := x"468";
--constant bldir30: std_logic_vector(11 downto 0) := x"469";
--constant bldir31: std_logic_vector(11 downto 0) := x"46a";
--constant bldir32: std_logic_vector(11 downto 0) := x"46b";
--constant bldir33: std_logic_vector(11 downto 0) := x"46c";
--constant bldir34: std_logic_vector(11 downto 0) := x"46d";
--constant bldir35: std_logic_vector(11 downto 0) := x"46e";
--constant bldir36: std_logic_vector(11 downto 0) := x"46f";
--constant bldir37: std_logic_vector(11 downto 0) := x"470";
--constant bldir38: std_logic_vector(11 downto 0) := x"471";
-- CPIR
constant bcpir5: std_logic_vector(11 downto 0) := x"480";
constant bcpir6: std_logic_vector(11 downto 0) := x"481";
--constant bcpir7: std_logic_vector(11 downto 0) := x"482";
--constant bcpir8: std_logic_vector(11 downto 0) := x"483";
--constant bcpir9: std_logic_vector(11 downto 0) := x"484";
--constant bcpir10: std_logic_vector(11 downto 0) := x"485";
--constant bcpir11: std_logic_vector(11 downto 0) := x"486";
--constant bcpir12: std_logic_vector(11 downto 0) := x"487";
--constant bcpir13: std_logic_vector(11 downto 0) := x"488";
--constant bcpir14: std_logic_vector(11 downto 0) := x"489";
--constant bcpir15: std_logic_vector(11 downto 0) := x"48a";
--constant bcpir16: std_logic_vector(11 downto 0) := x"48b";
--constant bcpir17: std_logic_vector(11 downto 0) := x"48c";
--constant bcpir18: std_logic_vector(11 downto 0) := x"48d";
--constant bcpir19: std_logic_vector(11 downto 0) := x"48e";
--constant bcpir20: std_logic_vector(11 downto 0) := x"48f";
--constant bcpir21: std_logic_vector(11 downto 0) := x"490";
--constant bcpir22: std_logic_vector(11 downto 0) := x"491";
--constant bcpir23: std_logic_vector(11 downto 0) := x"492";
--constant bcpir24: std_logic_vector(11 downto 0) := x"493";
--constant bcpir25: std_logic_vector(11 downto 0) := x"494";
--constant bcpir26: std_logic_vector(11 downto 0) := x"495";
--constant bcpir27: std_logic_vector(11 downto 0) := x"496";
--constant bcpir28: std_logic_vector(11 downto 0) := x"497";
--constant bcpir29: std_logic_vector(11 downto 0) := x"498";
--constant bcpir30: std_logic_vector(11 downto 0) := x"499";
--constant bcpir31: std_logic_vector(11 downto 0) := x"49a";
--constant bcpir32: std_logic_vector(11 downto 0) := x"49b";
--constant bcpir33: std_logic_vector(11 downto 0) := x"49c";
--constant bcpir34: std_logic_vector(11 downto 0) := x"49d";
--constant bcpir35: std_logic_vector(11 downto 0) := x"49e";
--constant bcpir36: std_logic_vector(11 downto 0) := x"49f";
--constant bcpir37: std_logic_vector(11 downto 0) := x"4a0";
--constant bcpir38: std_logic_vector(11 downto 0) := x"4a1";
-- INIR
constant binir5: std_logic_vector(11 downto 0) := x"4b0";
constant binir6: std_logic_vector(11 downto 0) := x"4b1";
--constant binir7: std_logic_vector(11 downto 0) := x"4b2";
--constant binir8: std_logic_vector(11 downto 0) := x"4b3";
--constant binir9: std_logic_vector(11 downto 0) := x"4b4";
--constant binir10: std_logic_vector(11 downto 0) := x"4b5";
--constant binir11: std_logic_vector(11 downto 0) := x"4b6";
--constant binir12: std_logic_vector(11 downto 0) := x"4b7";
--constant binir13: std_logic_vector(11 downto 0) := x"4b8";
--constant binir14: std_logic_vector(11 downto 0) := x"4b9";
--constant binir15: std_logic_vector(11 downto 0) := x"4ba";
--constant binir16: std_logic_vector(11 downto 0) := x"4bb";
--constant binir17: std_logic_vector(11 downto 0) := x"4bc";
--constant binir18: std_logic_vector(11 downto 0) := x"4bd";
--constant binir19: std_logic_vector(11 downto 0) := x"4be";
--constant binir20: std_logic_vector(11 downto 0) := x"4bf";
--constant binir21: std_logic_vector(11 downto 0) := x"4c0";
--constant binir22: std_logic_vector(11 downto 0) := x"4c1";
--constant binir23: std_logic_vector(11 downto 0) := x"4c2";
--constant binir24: std_logic_vector(11 downto 0) := x"4c3";
--constant binir25: std_logic_vector(11 downto 0) := x"4c4";
--constant binir26: std_logic_vector(11 downto 0) := x"4c5";
--constant binir27: std_logic_vector(11 downto 0) := x"4c6";
--constant binir28: std_logic_vector(11 downto 0) := x"4c7";
--constant binir29: std_logic_vector(11 downto 0) := x"4c8";
--constant binir30: std_logic_vector(11 downto 0) := x"4c9";
--constant binir31: std_logic_vector(11 downto 0) := x"4ca";
--constant binir32: std_logic_vector(11 downto 0) := x"4cb";
--constant binir33: std_logic_vector(11 downto 0) := x"4cc";
--constant binir34: std_logic_vector(11 downto 0) := x"4cd";
--constant binir35: std_logic_vector(11 downto 0) := x"4ce";
--constant binir36: std_logic_vector(11 downto 0) := x"4cf";
--constant binir37: std_logic_vector(11 downto 0) := x"4d0";
--constant binir38: std_logic_vector(11 downto 0) := x"4d1";
-- OTIR
constant botir5: std_logic_vector(11 downto 0) := x"4e0";
constant botir6: std_logic_vector(11 downto 0) := x"4e1";
--constant botir7: std_logic_vector(11 downto 0) := x"4e2";
--constant botir8: std_logic_vector(11 downto 0) := x"4e3";
--constant botir9: std_logic_vector(11 downto 0) := x"4e4";
--constant botir10: std_logic_vector(11 downto 0) := x"4e5";
--constant botir11: std_logic_vector(11 downto 0) := x"4e6";
--constant botir12: std_logic_vector(11 downto 0) := x"4e7";
--constant botir13: std_logic_vector(11 downto 0) := x"4e8";
--constant botir14: std_logic_vector(11 downto 0) := x"4e9";
--constant botir15: std_logic_vector(11 downto 0) := x"4ea";
--constant botir16: std_logic_vector(11 downto 0) := x"4eb";
--constant botir17: std_logic_vector(11 downto 0) := x"4ec";
--constant botir18: std_logic_vector(11 downto 0) := x"4ed";
--constant botir19: std_logic_vector(11 downto 0) := x"4ee";
--constant botir20: std_logic_vector(11 downto 0) := x"4ef";
--constant botir21: std_logic_vector(11 downto 0) := x"4f0";
--constant botir22: std_logic_vector(11 downto 0) := x"4f1";
--constant botir23: std_logic_vector(11 downto 0) := x"4f2";
--constant botir24: std_logic_vector(11 downto 0) := x"4f3";
--constant botir25: std_logic_vector(11 downto 0) := x"4f4";
--constant botir26: std_logic_vector(11 downto 0) := x"4f5";
--constant botir27: std_logic_vector(11 downto 0) := x"4f6";
--constant botir28: std_logic_vector(11 downto 0) := x"4f7";
--constant botir29: std_logic_vector(11 downto 0) := x"4f8";
--constant botir30: std_logic_vector(11 downto 0) := x"4f9";
--constant botir31: std_logic_vector(11 downto 0) := x"4fa";
--constant botir32: std_logic_vector(11 downto 0) := x"4fb";
--constant botir33: std_logic_vector(11 downto 0) := x"4fc";
--constant botir34: std_logic_vector(11 downto 0) := x"4fd";
--constant botir35: std_logic_vector(11 downto 0) := x"4fe";
--constant botir36: std_logic_vector(11 downto 0) := x"4ff";
--constant botir37: std_logic_vector(11 downto 0) := x"500";
--constant botir38: std_logic_vector(11 downto 0) := x"501";
-- LDDR
constant blddr5: std_logic_vector(11 downto 0) := x"510";
constant blddr6: std_logic_vector(11 downto 0) := x"511";
--constant blddr7: std_logic_vector(11 downto 0) := x"512";
--constant blddr8: std_logic_vector(11 downto 0) := x"513";
--constant blddr9: std_logic_vector(11 downto 0) := x"514";
--constant blddr10: std_logic_vector(11 downto 0) := x"515";
--constant blddr11: std_logic_vector(11 downto 0) := x"516";
--constant blddr12: std_logic_vector(11 downto 0) := x"517";
--constant blddr13: std_logic_vector(11 downto 0) := x"518";
--constant blddr14: std_logic_vector(11 downto 0) := x"519";
--constant blddr15: std_logic_vector(11 downto 0) := x"51a";
--constant blddr16: std_logic_vector(11 downto 0) := x"51b";
--constant blddr17: std_logic_vector(11 downto 0) := x"51c";
--constant blddr18: std_logic_vector(11 downto 0) := x"51d";
--constant blddr19: std_logic_vector(11 downto 0) := x"51e";
--constant blddr20: std_logic_vector(11 downto 0) := x"51f";
--constant blddr21: std_logic_vector(11 downto 0) := x"520";
--constant blddr22: std_logic_vector(11 downto 0) := x"521";
--constant blddr23: std_logic_vector(11 downto 0) := x"522";
--constant blddr24: std_logic_vector(11 downto 0) := x"523";
--constant blddr25: std_logic_vector(11 downto 0) := x"524";
--constant blddr26: std_logic_vector(11 downto 0) := x"525";
--constant blddr27: std_logic_vector(11 downto 0) := x"526";
--constant blddr28: std_logic_vector(11 downto 0) := x"527";
--constant blddr29: std_logic_vector(11 downto 0) := x"528";
--constant blddr30: std_logic_vector(11 downto 0) := x"529";
--constant blddr31: std_logic_vector(11 downto 0) := x"52a";
--constant blddr32: std_logic_vector(11 downto 0) := x"52b";
--constant blddr33: std_logic_vector(11 downto 0) := x"52c";
--constant blddr34: std_logic_vector(11 downto 0) := x"52d";
--constant blddr35: std_logic_vector(11 downto 0) := x"52e";
--constant blddr36: std_logic_vector(11 downto 0) := x"52f";
--constant blddr37: std_logic_vector(11 downto 0) := x"530";
--constant blddr38: std_logic_vector(11 downto 0) := x"531";
-- CPDR
constant bcpdr5: std_logic_vector(11 downto 0) := x"540";
constant bcpdr6: std_logic_vector(11 downto 0) := x"541";
--constant bcpdr7: std_logic_vector(11 downto 0) := x"542";
--constant bcpdr8: std_logic_vector(11 downto 0) := x"543";
--constant bcpdr9: std_logic_vector(11 downto 0) := x"544";
--constant bcpdr10: std_logic_vector(11 downto 0) := x"545";
--constant bcpdr11: std_logic_vector(11 downto 0) := x"546";
--constant bcpdr12: std_logic_vector(11 downto 0) := x"547";
--constant bcpdr13: std_logic_vector(11 downto 0) := x"548";
--constant bcpdr14: std_logic_vector(11 downto 0) := x"549";
--constant bcpdr15: std_logic_vector(11 downto 0) := x"54a";
--constant bcpdr16: std_logic_vector(11 downto 0) := x"54b";
--constant bcpdr17: std_logic_vector(11 downto 0) := x"54c";
--constant bcpdr18: std_logic_vector(11 downto 0) := x"54d";
--constant bcpdr19: std_logic_vector(11 downto 0) := x"54e";
--constant bcpdr20: std_logic_vector(11 downto 0) := x"54f";
--constant bcpdr21: std_logic_vector(11 downto 0) := x"550";
--constant bcpdr22: std_logic_vector(11 downto 0) := x"551";
--constant bcpdr23: std_logic_vector(11 downto 0) := x"552";
--constant bcpdr24: std_logic_vector(11 downto 0) := x"553";
--constant bcpdr25: std_logic_vector(11 downto 0) := x"554";
--constant bcpdr26: std_logic_vector(11 downto 0) := x"555";
--constant bcpdr27: std_logic_vector(11 downto 0) := x"556";
--constant bcpdr28: std_logic_vector(11 downto 0) := x"557";
--constant bcpdr29: std_logic_vector(11 downto 0) := x"558";
--constant bcpdr30: std_logic_vector(11 downto 0) := x"559";
--constant bcpdr32: std_logic_vector(11 downto 0) := x"55a";
--constant bcpdr33: std_logic_vector(11 downto 0) := x"55b";
--constant bcpdr34: std_logic_vector(11 downto 0) := x"55c";
--constant bcpdr35: std_logic_vector(11 downto 0) := x"55d";
--constant bcpdr36: std_logic_vector(11 downto 0) := x"55e";
--constant bcpdr37: std_logic_vector(11 downto 0) := x"55f";
--constant bcpdr38: std_logic_vector(11 downto 0) := x"560";
--constant bcpdr39: std_logic_vector(11 downto 0) := x"561";
-- INDR
constant bindr5: std_logic_vector(11 downto 0) := x"570";
constant bindr6: std_logic_vector(11 downto 0) := x"571";
--constant bindr7: std_logic_vector(11 downto 0) := x"572";
--constant bindr8: std_logic_vector(11 downto 0) := x"573";
--constant bindr9: std_logic_vector(11 downto 0) := x"574";
--constant bindr13: std_logic_vector(11 downto 0) := x"575";
--constant bindr10: std_logic_vector(11 downto 0) := x"576";
--constant bindr18: std_logic_vector(11 downto 0) := x"577";
--constant bindr12: std_logic_vector(11 downto 0) := x"578";
--constant bindr13: std_logic_vector(11 downto 0) := x"579";
--constant bindr14: std_logic_vector(11 downto 0) := x"57a";
--constant bindr15: std_logic_vector(11 downto 0) := x"57b";
--constant bindr16: std_logic_vector(11 downto 0) := x"57c";
--constant bindr17: std_logic_vector(11 downto 0) := x"57d";
--constant bindr18: std_logic_vector(11 downto 0) := x"57e";
--constant bindr19: std_logic_vector(11 downto 0) := x"57f";
--constant bindr20: std_logic_vector(11 downto 0) := x"580";
--constant bindr21: std_logic_vector(11 downto 0) := x"581";
--constant bindr22: std_logic_vector(11 downto 0) := x"582";
--constant bindr23: std_logic_vector(11 downto 0) := x"583";
--constant bindr24: std_logic_vector(11 downto 0) := x"584";
--constant bindr25: std_logic_vector(11 downto 0) := x"585";
--constant bindr26: std_logic_vector(11 downto 0) := x"586";
--constant bindr27: std_logic_vector(11 downto 0) := x"587";
--constant bindr28: std_logic_vector(11 downto 0) := x"588";
--constant bindr29: std_logic_vector(11 downto 0) := x"589";
--constant bindr30: std_logic_vector(11 downto 0) := x"58a";
--constant bindr31: std_logic_vector(11 downto 0) := x"58b";
--constant bindr32: std_logic_vector(11 downto 0) := x"58c";
--constant bindr33: std_logic_vector(11 downto 0) := x"58d";
--constant bindr34: std_logic_vector(11 downto 0) := x"58e";
--constant bindr35: std_logic_vector(11 downto 0) := x"58f";
--constant bindr36: std_logic_vector(11 downto 0) := x"590";
--constant bindr37: std_logic_vector(11 downto 0) := x"591";
-- OTDR
constant botdr5: std_logic_vector(11 downto 0) := x"5a0";
constant botdr6: std_logic_vector(11 downto 0) := x"5a1";
--constant botdr7: std_logic_vector(11 downto 0) := x"5a2";
--constant botdr8: std_logic_vector(11 downto 0) := x"5a3";
--constant botdr9: std_logic_vector(11 downto 0) := x"5a4";
--constant botdr10: std_logic_vector(11 downto 0) := x"5a5";
--constant botdr11: std_logic_vector(11 downto 0) := x"5a6";
--constant botdr12: std_logic_vector(11 downto 0) := x"5a7";
--constant botdr13: std_logic_vector(11 downto 0) := x"5a8";
--constant botdr14: std_logic_vector(11 downto 0) := x"5a9";
--constant botdr15: std_logic_vector(11 downto 0) := x"5aa";
--constant botdr16: std_logic_vector(11 downto 0) := x"5ab";
--constant botdr17: std_logic_vector(11 downto 0) := x"5ac";
--constant botdr18: std_logic_vector(11 downto 0) := x"5ad";
--constant botdr19: std_logic_vector(11 downto 0) := x"5ae";
--constant botdr20: std_logic_vector(11 downto 0) := x"5af";
--constant botdr21: std_logic_vector(11 downto 0) := x"5b0";
--constant botdr22: std_logic_vector(11 downto 0) := x"5b1";
--constant botdr23: std_logic_vector(11 downto 0) := x"5b2";
--constant botdr24: std_logic_vector(11 downto 0) := x"5b3";
--constant botdr25: std_logic_vector(11 downto 0) := x"5b4";
--constant botdr26: std_logic_vector(11 downto 0) := x"5b5";
--constant botdr27: std_logic_vector(11 downto 0) := x"5b6";
--constant botdr28: std_logic_vector(11 downto 0) := x"5b7";
--constant botdr29: std_logic_vector(11 downto 0) := x"5b8";
--constant botdr30: std_logic_vector(11 downto 0) := x"5b9";
--constant botdr31: std_logic_vector(11 downto 0) := x"5ba";
--constant botdr32: std_logic_vector(11 downto 0) := x"5bb";
--constant botdr33: std_logic_vector(11 downto 0) := x"5bc";
--constant botdr34: std_logic_vector(11 downto 0) := x"5bd";
--constant botdr35: std_logic_vector(11 downto 0) := x"5be";
--constant botdr36: std_logic_vector(11 downto 0) := x"5bf";
--constant botdr37: std_logic_vector(11 downto 0) := x"5c0";
--constant botdr38: std_logic_vector(11 downto 0) := x"5c1";
-- end of ED prefixed opcodes
-- index register instructions
constant index4: std_logic_vector(11 downto 0) := x"5d0";
constant index5: std_logic_vector(11 downto 0) := x"5d1";
constant index6: std_logic_vector(11 downto 0) := x"5d2";
constant index7: std_logic_vector(11 downto 0) := x"5d3";
constant index8: std_logic_vector(11 downto 0) := x"5d4";
-- alu ops on immediate operand, 7 cycles, 1 m1 cycle
constant alui4: std_logic_vector(11 downto 0) := x"5e0";
constant alui5: std_logic_vector(11 downto 0) := x"5e1";
-- RST, 11 clock cycles, 1 m1 cycle
constant rst4: std_logic_vector(11 downto 0) := x"5f0";
constant rst5: std_logic_vector(11 downto 0) := x"5f1";
constant rst6: std_logic_vector(11 downto 0) := x"5f2";
constant rst7: std_logic_vector(11 downto 0) := x"5f3";
constant rst8: std_logic_vector(11 downto 0) := x"5f4";
-- get next opcode byte
constant nxtop1: std_logic_vector(11 downto 0) := x"600";
constant nxtop2: std_logic_vector(11 downto 0) := x"601";
-- get next operand byte
constant nxtoprnd1: std_logic_vector(11 downto 0) := x"610";
constant nxtoprnd2: std_logic_vector(11 downto 0) := x"611";
-- general memory read
constant genmemrd1: std_logic_vector(11 downto 0) := x"620";
constant genmemrd2: std_logic_vector(11 downto 0) := x"621";
constant genmemrd3: std_logic_vector(11 downto 0) := x"622";
-- general memory write
constant genmemwrt1: std_logic_vector(11 downto 0) := x"630";
constant genmemwrt2: std_logic_vector(11 downto 0) := x"631";
constant genmemwrt3: std_logic_vector(11 downto 0) := x"632";
constant genmemwrt4: std_logic_vector(11 downto 0) := x"633";
-- for 2-byte operands
constant obtain_2byte_operand1: std_logic_vector(11 downto 0) := x"640";
constant obtain_2byte_operand2: std_logic_vector(11 downto 0) := x"641";
-- for SP increment
constant incSP1: std_logic_vector(11 downto 0) := x"650";
-- for SP decrement
constant decSP1: std_logic_vector(11 downto 0) := x"660";
-- for handling non-maskable interrupts
constant nmi1: std_logic_vector(11 downto 0) := x"670";
-- for handling maskable interrupts
constant int1: std_logic_vector(11 downto 0) := x"680";
-- index register bit operations
constant index_bit5: std_logic_vector(11 downto 0) := x"690";
constant index_bit6: std_logic_vector(11 downto 0) := x"691";
constant index_bit7: std_logic_vector(11 downto 0) := x"692";
-- BIT
constant index_bit_bit8: std_logic_vector(11 downto 0) := x"6a0";
-- common state for saving index bit operation results other than BIT
constant index_save8: std_logic_vector(11 downto 0) := x"6b0";
-- load index register with immediate operand
constant ld_index_immediate5: std_logic_vector(11 downto 0) := x"6c0";
constant ld_index_immediate6: std_logic_vector(11 downto 0) := x"6c1";
-- add index register to register pair
constant add_index_rp5: std_logic_vector(11 downto 0) := x"6d0";
constant add_index_rp6: std_logic_vector(11 downto 0) := x"6d1";
-- store index register direct
constant st_index_direct5: std_logic_vector(11 downto 0) := x"6e0";
constant st_index_direct6: std_logic_vector(11 downto 0) := x"6e1";
-- load index register direct
constant ld_index_direct5: std_logic_vector(11 downto 0) := x"6f0";
constant ld_index_direct6: std_logic_vector(11 downto 0) := x"6f1";
constant ld_index_direct7: std_logic_vector(11 downto 0) := x"6f2";
constant ld_index_direct8: std_logic_vector(11 downto 0) := x"6f3";
constant ld_index_direct9: std_logic_vector(11 downto 0) := x"6f4";
constant ld_index_direct10: std_logic_vector(11 downto 0) := x"6f5";
constant ld_index_direct11: std_logic_vector(11 downto 0) := x"6f6";
constant ld_index_direct12: std_logic_vector(11 downto 0) := x"6f7";
constant ld_index_direct13: std_logic_vector(11 downto 0) := x"6f8";
constant ld_index_direct14: std_logic_vector(11 downto 0) := x"6f9";
-- increment or decrement index register
constant incdec_index5: std_logic_vector(11 downto 0) := x"700";
constant incdec_index6: std_logic_vector(11 downto 0) := x"701";
-- increment or decrement memory at index register + offset
constant incdec_index_memory5: std_logic_vector(11 downto 0) := x"710";
constant incdec_index_memory6: std_logic_vector(11 downto 0) := x"711";
-- load immediate to index register + offset
constant ld_index_memory_immed5: std_logic_vector(11 downto 0) := x"720";
constant ld_index_memory_immed6: std_logic_vector(11 downto 0) := x"721";
-- store 8 bit register to index register + offset
constant st_index_memory5: std_logic_vector(11 downto 0) := x"730";
-- load 8 bit register from index register + offset
constant ld_index_memory5: std_logic_vector(11 downto 0) := x"740";
constant ld_index_memory6: std_logic_vector(11 downto 0) := x"741";
constant ld_index_memory7: std_logic_vector(11 downto 0) := x"742";
constant ld_index_memory8: std_logic_vector(11 downto 0) := x"743";
constant ld_index_memory9: std_logic_vector(11 downto 0) := x"744";
constant ld_index_memory10: std_logic_vector(11 downto 0) := x"745";
constant ld_index_memory11: std_logic_vector(11 downto 0) := x"746";
constant ld_index_memory12: std_logic_vector(11 downto 0) := x"747";
constant ld_index_memory13: std_logic_vector(11 downto 0) := x"748";
constant ld_index_memory14: std_logic_vector(11 downto 0) := x"749";
-- 8 bit ALU operations involving memory pointed to by index register + offset
constant index_alu_ops5: std_logic_vector(11 downto 0) := x"750";
constant index_alu_ops6: std_logic_vector(11 downto 0) := x"751";
constant index_alu_ops7: std_logic_vector(11 downto 0) := x"752";
constant index_alu_ops8: std_logic_vector(11 downto 0) := x"753";
constant index_alu_ops9: std_logic_vector(11 downto 0) := x"754";
constant index_alu_ops10: std_logic_vector(11 downto 0) := x"755";
constant index_alu_ops11: std_logic_vector(11 downto 0) := x"756";
constant index_alu_ops12: std_logic_vector(11 downto 0) := x"757";
constant index_alu_ops13: std_logic_vector(11 downto 0) := x"758";
constant index_alu_ops14: std_logic_vector(11 downto 0) := x"759";
-- pop index register off stack
constant pop_index5: std_logic_vector(11 downto 0) := x"770";
constant pop_index6: std_logic_vector(11 downto 0) := x"771";
constant pop_index7: std_logic_vector(11 downto 0) := x"772";
-- push index register on stack
constant push_index5: std_logic_vector(11 downto 0) := x"780";
constant push_index6: std_logic_vector(11 downto 0) := x"781";
constant push_index7: std_logic_vector(11 downto 0) := x"782";
constant push_index8: std_logic_vector(11 downto 0) := x"783";
constant push_index9: std_logic_vector(11 downto 0) := x"784";
constant push_index10: std_logic_vector(11 downto 0) := x"785";
constant push_index11: std_logic_vector(11 downto 0) := x"786";
constant push_index12: std_logic_vector(11 downto 0) := x"787";
constant push_index13: std_logic_vector(11 downto 0) := x"788";
constant push_index14: std_logic_vector(11 downto 0) := x"789";
-- SPI?
constant sp_index5: std_logic_vector(11 downto 0) := x"790";
-- XTI?
constant xtindex5: std_logic_vector(11 downto 0) := x"7a0";
constant xtindex6: std_logic_vector(11 downto 0) := x"7a1";
constant xtindex7: std_logic_vector(11 downto 0) := x"7a2";
constant xtindex8: std_logic_vector(11 downto 0) := x"7a3";
constant xtindex9: std_logic_vector(11 downto 0) := x"7a4";
constant xtindex10: std_logic_vector(11 downto 0) := x"7a5";
constant xtindex11: std_logic_vector(11 downto 0) := x"7a6";
constant xtindex12: std_logic_vector(11 downto 0) := x"7a7";
constant xtindex13: std_logic_vector(11 downto 0) := x"7a8";
constant xtindex14: std_logic_vector(11 downto 0) := x"7a9";
constant test: std_logic_vector(11 downto 0) := x"fff";
constant waitstate: std_logic_vector(11 downto 0) := x"ffe";
end; | gpl-2.0 | 4dbed96a7e4afede0ef13f731b510413 | 0.618104 | 2.673675 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd | 4 | 7,408 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc626.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:46 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:09 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:25 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00626ent IS
END c03s04b01x00p01n01i00626ent;
ARCHITECTURE c03s04b01x00p01n01i00626arch OF c03s04b01x00p01n01i00626ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
i: record_array_st;
end record;
type record_of_records_file is file of record_of_records;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C28 : boolean_vector_st :=(others => C1);
constant C29 : severity_level_vector_st:= (others => C4);
constant C30 : integer_vector_st:=(others => C5);
constant C31 : real_vector_st:=(others => C6);
constant C32 : time_vector_st:=(others => C7);
constant C33 : natural_vector_st:=(others => C8);
constant C34 : positive_vector_st:=(others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
constant C37 : record_of_records := (C26,C27,C35);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : record_of_records_file open read_mode is "iofile.35";
variable v : record_of_records;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C37) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00626"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00626 - File reading operation (record_of_records file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00626arch;
| gpl-2.0 | 582d62178a1350350a8c53fef4199a40 | 0.547921 | 3.844318 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd | 4 | 2,416 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_rf-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
architecture behavior of reg_file is
begin
reg: process ( a1, a2, a3, d3, write_en ) is
use work.dlx_instr.reg_index,
bv_utilities.bv_arithmetic.bv_to_natural;
constant all_zeros : dlx_word := X"0000_0000";
type register_array is array (reg_index range 1 to 31) of dlx_word;
variable register_file : register_array;
variable reg_index1, reg_index2, reg_index3 : reg_index;
begin
-- do write first if enabled
--
if To_bit(write_en) = '1' then
reg_index3 := bv_to_natural(To_bitvector(a3));
if reg_index3 /= 0 then
register_file(reg_index3) := To_X01(d3);
end if;
end if;
--
-- read port 1
--
reg_index1 := bv_to_natural(To_bitvector(a1));
if reg_index1 /= 0 then
q1 <= register_file(reg_index1) after Tac;
else
q1 <= all_zeros after Tac;
end if;
--
-- read port 2
--
reg_index2 := bv_to_natural(To_bitvector(a2));
if reg_index2 /= 0 then
q2 <= register_file(reg_index2) after Tac;
else
q2 <= all_zeros after Tac;
end if;
end process reg;
end architecture behavior;
| gpl-2.0 | 23b5ad176a20ceeb77b23a8ec312a2df | 0.551738 | 4.006633 | false | false | false | false |
nickg/nvc | test/regress/link2.vhd | 1 | 1,621 | package pack0 is
constant foo : integer := 42;
constant v : bit_vector := "1010101";
constant q : bit_vector(3 downto 0) := X"F";
constant z : integer := 2;
end package;
-------------------------------------------------------------------------------
use work.pack0.all;
package pack1 is
function bar return integer;
end package;
package body pack1 is
function bar return integer is
begin
return 5;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack1.all;
use work.pack0.all;
package pack2 is
function foo return integer;
function get_v return bit_vector;
function get_v0 return bit;
end package;
package body pack2 is
constant x : bit_vector(1 downto 0) := q(1 downto 0);
constant gv : bit_vector(6 downto 0) := get_v;
function foo return integer is
begin
return bar + 2;
end function;
function get_v return bit_vector is
begin
return v;
end function;
function get_v0 return bit is
begin
return v(0);
end function;
end package body;
-------------------------------------------------------------------------------
entity link2 is
end entity;
use work.pack2.all;
architecture test of link2 is
begin
process is
variable v : bit_vector(6 downto 0);
begin
assert foo = 7;
assert get_v = "1010101"; -- Will be constant folded
v := get_v;
wait for 1 ns;
assert v = get_v;
assert get_v0 = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 041e5d7bf6e35fa88453b00da1475538 | 0.528069 | 4.15641 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue559/dut.vhdl | 1 | 1,118 | --
-- dut
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dut is
Generic (
TARGETS_ADDR : std_logic_vector
);
end dut;
architecture a of dut is
signal slv : std_logic_vector(1 downto 0);
type slv_arr_t is array (0 to 1) of std_logic_vector(slv'range);
function addr_arr_init (
arg : std_logic_vector
) return slv_arr_t is
variable v : slv_arr_t;
begin
report "arg'length="&positive'image(arg'length);
report "v(0)'length="&positive'image(v(0)'length);
-- Bound check error
v(0) := arg(1 downto 0);
-- No bound check error
--v(0) := arg;
return v;
end function;
constant ADDR_ARR : slv_arr_t := addr_arr_init(TARGETS_ADDR);
begin
end a;
--
-- tb
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end entity;
architecture bench of tb is
constant C_SLV : std_logic_vector(1 downto 0) := "00";
begin
dut : entity work.dut
generic map (
-- Bound check error
TARGETS_ADDR => "00"
-- No bound check error
--TARGETS_ADDR => C_SLV
);
stimulus : process
begin
report "pass";
wait;
end process;
end bench;
| gpl-2.0 | c0f1a326d7895711e5391ce96b428a5c | 0.66458 | 2.707022 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1133/foo.vhdl | 1 | 554 | library ieee;
use ieee.std_logic_1164.all;
entity foo is
port (
input : in std_logic_vector(7 downto 0);
output_ok : out std_logic_vector(7 downto 0);
output_error : out std_logic_vector(7 downto 0)
);
end foo;
architecture foo of foo is
signal null_vector : std_logic_vector(-1 downto 0) := (others => '0');
begin
-- This works fine
null_vector <= input(null_vector'range);
output_ok <= null_vector & (7 downto 0 => '0');
-- This doesn't
output_error <= input(-1 downto 0) & (7 downto 0 => '0');
end foo;
| gpl-2.0 | cc40e66cb2fffef55750a88091d8b899 | 0.619134 | 3.11236 | false | false | false | false |
nickg/nvc | test/regress/vests22.vhd | 1 | 4,826 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc472.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY vests22 IS
END vests22;
ARCHITECTURE c03s02b01x01p19n01i00472arch OF vests22 IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C66 : array_rec_cons (0 to 7) := (others => C51);
function complex_scalar(s : array_rec_cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_cons(0 to 7);
signal S2 : array_rec_cons(0 to 7);
signal S3 : array_rec_cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00472"
severity NOTE;
assert s1 = c66;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00472 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00472arch;
| gpl-3.0 | e63d1b7292443b25135276f14c34d285 | 0.616038 | 3.672755 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd | 4 | 2,018 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc986.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p06n01i00986ent IS
END c06s03b00x00p06n01i00986ent;
ARCHITECTURE c06s03b00x00p06n01i00986arch OF c06s03b00x00p06n01i00986ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : BIT ;
S2 : Integer;
end record;
type T2 is access T1;
variable V1 : T2 := new T1'('0',0) ;
variable V2 : T1;
BEGIN
V2 := V1.all ; -- No_Failure_here
wait for 10 ns;
assert NOT(V2.S1='0' and V2.S2=0)
report "***PASSED TEST: c06s03b00x00p06n01i00986"
severity NOTE;
assert (V2.S1='0' and V2.S2=0)
report "***FAILED TEST: c06s03b00x00p06n01i00986 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00986arch;
| gpl-2.0 | 7580a4c906321c24599f3acfeeb07f39 | 0.648167 | 3.534151 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd | 4 | 2,194 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2460.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02460ent IS
END c07s03b02x02p03n02i02460ent;
ARCHITECTURE c07s03b02x02p03n02i02460arch OF c07s03b02x02p03n02i02460ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
type AGGREGATE_ARRAY is array (1 to 2) of CONSTRAINED_ARRAY;
signal V,W : CONSTRAINED_ARRAY;
BEGIN
TESTING: PROCESS
BEGIN
(V,W) <= AGGREGATE_ARRAY' (('d', 'x', others => 'a'),
('d', 'x', others => 'a'));
wait for 1 ns;
assert NOT( V(1)='d' and V(2)='x' and V(3)='a' )
report "***PASSED TEST: c07s03b02x02p03n02i02460"
severity NOTE;
assert ( V(1)='d' and V(2)='x' and V(3)='a' )
report "***FAILED TEST: c07s03b02x02p03n02i02460 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02460arch;
| gpl-2.0 | b9bf184c3d2abbabcb365484ebeba41d | 0.642662 | 3.687395 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd | 4 | 50,622 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00517pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00517pkg;
USE work.c03s03b00x00p03n04i00517pkg.ALL;
ENTITY c03s03b00x00p03n04i00517ent IS
END c03s03b00x00p03n04i00517ent;
ARCHITECTURE c03s03b00x00p03n04i00517arch OF c03s03b00x00p03n04i00517ent IS
--
-- Access type declarations
--
TYPE at_scre_1 IS ACCESS t_scre_1 ;
TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_scre_1 : at_scre_1 ;
VARIABLE AV2_scre_1 : at_scre_1 ;
VARIABLE AV0_cca1_1 : at_cca1_1 ;
VARIABLE AV2_cca1_1 : at_cca1_1 ;
VARIABLE AV0_cca1_2 : at_cca1_2 ;
VARIABLE AV2_cca1_2 : at_cca1_2 ;
VARIABLE AV0_cca1_3 : at_cca1_3 ;
VARIABLE AV2_cca1_3 : at_cca1_3 ;
VARIABLE AV0_cca1_4 : at_cca1_4 ;
VARIABLE AV2_cca1_4 : at_cca1_4 ;
VARIABLE AV0_cmre_1 : at_cmre_1 ;
VARIABLE AV2_cmre_1 : at_cmre_1 ;
VARIABLE AV0_cmre_2 : at_cmre_2 ;
VARIABLE AV2_cmre_2 : at_cmre_2 ;
VARIABLE AV0_cca1_7 : at_cca1_7 ;
VARIABLE AV2_cca1_7 : at_cca1_7 ;
VARIABLE AV0_cmre_3 : at_cmre_3 ;
VARIABLE AV2_cmre_3 : at_cmre_3 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_scre_1 := NEW t_scre_1 ;
AV0_cca1_1 := NEW t_cca1_1 ;
AV0_cca1_2 := NEW t_cca1_2 ;
AV0_cca1_3 := NEW t_cca1_3 ;
AV0_cca1_4 := NEW t_cca1_4 ;
AV0_cmre_1 := NEW t_cmre_1 ;
AV0_cmre_2 := NEW t_cmre_2 ;
AV0_cca1_7 := NEW t_cca1_7 ;
AV0_cmre_3 := NEW t_cmre_3 ;
---
AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
--
--
ASSERT AV0_scre_1.all = C0_scre_1
REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
ASSERT AV2_scre_1.all = C2_scre_1
REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
ASSERT AV0_cca1_1.all = C0_cca1_1
REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
ASSERT AV2_cca1_1.all = C2_cca1_1
REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
ASSERT AV0_cca1_2.all = C0_cca1_2
REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
ASSERT AV2_cca1_2.all = C2_cca1_2
REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
ASSERT AV0_cca1_3.all = C0_cca1_3
REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
ASSERT AV2_cca1_3.all = C2_cca1_3
REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
ASSERT AV0_cca1_4.all = C0_cca1_4
REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
ASSERT AV2_cca1_4.all = C2_cca1_4
REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
ASSERT AV0_cmre_1.all = C0_cmre_1
REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
ASSERT AV2_cmre_1.all = C2_cmre_1
REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
ASSERT AV0_cmre_2.all = C0_cmre_2
REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
ASSERT AV2_cmre_2.all = C2_cmre_2
REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
ASSERT AV0_cca1_7.all = C0_cca1_7
REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
ASSERT AV2_cca1_7.all = C2_cca1_7
REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
ASSERT AV0_cmre_3.all = C0_cmre_3
REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
ASSERT AV2_cmre_3.all = C2_cmre_3
REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***PASSED TEST: c03s03b00x00p03n04i00517"
severity NOTE;
assert ( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00517arch;
| gpl-2.0 | 3b5d09cca1340c16a48622658e1c65c7 | 0.574177 | 2.597732 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd | 4 | 2,669 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01073ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
SUBTYPE A8 IS A (1 TO 8);
SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
ELSE
IF (a=3) THEN
RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
ELSE
RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
END IF;
END IF;
END;
END c06s04b00x00p03n01i01073ent;
ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,0)(1,1,1);
q(2) := func1(0,3)(2,2,2);
q(3) := func1(0,0)(3,3,3);
q(4) := func1(4,4,4); -- Indexed name - function params defaulted
q(5) := func1(5,5,5);
q(6) := func1(6,6,6);
q(7) := func1(3,3,3);
q(8) := func1(1,1,1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***PASSED TEST: c06s04b00x00p03n01i01073"
severity NOTE;
assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01073arch;
| gpl-2.0 | 5e642f4a0713b4cbd74ccac5721a84e9 | 0.616336 | 3.064294 | false | true | false | false |
tgingold/ghdl | testsuite/synth/concat01/tb_concat01.vhdl | 1 | 583 | entity tb_concat01 is
end tb_concat01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_concat01 is
signal a : std_logic;
signal b : std_logic;
signal z : std_logic_vector(1 downto 0);
begin
dut: entity work.concat01
port map (a, b, z);
process
begin
a <= '0';
b <= '1';
wait for 1 ns;
assert z = "01" severity failure;
a <= '1';
b <= '1';
wait for 1 ns;
assert z = "11" severity failure;
a <= '1';
b <= '0';
wait for 1 ns;
assert z = "10" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 64c5f350eb4c43aea14c182bdd042e78 | 0.57976 | 3.068421 | false | false | false | false |
nickg/nvc | test/regress/wait23.vhd | 1 | 938 | entity wait23 is
end entity;
architecture test of wait23 is
type timerec is record
t : time;
end record;
type timerec_vec is array (natural range <>) of timerec;
signal s : integer := 0;
begin
p1: process is
variable a : timerec_vec(1 to 5) := ( (t => 1 ns),
(t => 2 ns),
(t => 3 ns),
(t => 4 ms),
(t => 5 ms) );
begin
for i in a'range loop
s <= transport i after a(i).t;
end loop;
assert s = 0;
wait for 1 ns;
assert s = 1;
wait for 1 ns;
assert s = 2;
wait for 1 ns;
assert s = 3;
wait for 4 ms;
assert s = 4;
wait for 1 ms;
assert s = 5;
wait;
end process;
end architecture;
| gpl-3.0 | 99bf477bc40a1e243ede132cce2cfa85 | 0.396588 | 4.302752 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/vhdl/axi_traffic_gen_v2_0_bmg_wrap.vhd | 1 | 15,694 | -------------------------------------------------------------------------------
-- (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
-- Filename: axi_traffic_gen_v2_0_bmg_wrap.v
-- Version : v1.0
-- Description: BMG Wrapper
-- Verilog-Standard:verilog-2001
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library lib_bmg_v1_0;
use lib_bmg_v1_0.all;
entity axi_traffic_gen_v2_0_bmg_wrap is
generic
(
-- Device Family
c_family : string := "virtex5";
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity axi_traffic_gen_v2_0_bmg_wrap;
architecture implementation of axi_traffic_gen_v2_0_bmg_wrap is
begin
-- component blk_mem_gen_wrapper is
-- generic
-- (
-- c_family : string := "virtex5";
-- c_xdevicefamily : string := "virtex5";
-- c_elaboration_dir : string := "";
-- c_mem_type : integer := 2;
-- c_algorithm : integer := 1;
-- c_prim_type : integer := 1;
-- c_byte_size : integer := 9; -- 8 or 9
-- c_sim_collision_check : string := "NONE";
-- c_common_clk : integer := 1; -- 0, 1
-- c_disable_warn_bhv_coll : integer := 0; -- 0, 1
-- c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- c_load_init_file : integer := 0;
-- c_init_file_name : string := "no_coe_file_loaded";
-- c_use_default_data : integer := 0; -- 0, 1
-- c_default_data : string := "0"; -- "..."
-- c_has_mem_output_regs_a : integer := 0; -- 0, 1
-- c_has_mux_output_regs_a : integer := 0; -- 0, 1
-- c_write_width_a : integer := 32; -- 1 to 1152
-- c_read_width_a : integer := 32; -- 1 to 1152
-- c_write_depth_a : integer := 64; -- 2 to 9011200
-- c_read_depth_a : integer := 64; -- 2 to 9011200
-- c_addra_width : integer := 6; -- 1 to 24
-- c_write_mode_a : string := "WRITE_FIRST";
-- c_has_ena : integer := 1; -- 0, 1
-- c_has_regcea : integer := 0; -- 0, 1
-- c_has_ssra : integer := 0; -- 0, 1
-- c_sinita_val : string := "0"; --"..."
-- c_use_byte_wea : integer := 0; -- 0, 1
-- c_wea_width : integer := 1; -- 1 to 128
-- c_has_mem_output_regs_b : integer := 0; -- 0, 1
-- c_has_mux_output_regs_b : integer := 0; -- 0, 1
-- c_write_width_b : integer := 32; -- 1 to 1152
-- c_read_width_b : integer := 32; -- 1 to 1152
-- c_write_depth_b : integer := 64; -- 2 to 9011200
-- c_read_depth_b : integer := 64; -- 2 to 9011200
-- c_addrb_width : integer := 6; -- 1 to 24
-- c_write_mode_b : string := "WRITE_FIRST";
-- c_has_enb : integer := 1; -- 0, 1
-- c_has_regceb : integer := 0; -- 0, 1
-- c_has_ssrb : integer := 0; -- 0, 1
-- c_sinitb_val : string := "0"; -- "..."
-- c_use_byte_web : integer := 0; -- 0, 1
-- c_web_width : integer := 1; -- 1 to 128
-- c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- c_use_ecc : integer := 0;
-- c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- );
-- port
-- (
-- clka : in std_logic;
-- ssra : in std_logic := '0';
-- dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
-- addra : in std_logic_vector(c_addra_width-1 downto 0);
-- ena : in std_logic := '1';
-- regcea : in std_logic := '1';
-- wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
-- douta : out std_logic_vector(c_read_width_a-1 downto 0);
-- clkb : in std_logic := '0';
-- ssrb : in std_logic := '0';
-- dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
-- addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
-- enb : in std_logic := '1';
-- regceb : in std_logic := '1';
-- web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
-- doutb : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr : out std_logic;
-- sbiterr : out std_logic
-- );
--end component;
proc_bmg :entity lib_bmg_v1_0.blk_mem_gen_wrapper
generic map
(
c_family => c_family ,
c_xdevicefamily => c_xdevicefamily ,
c_elaboration_dir => c_elaboration_dir ,
c_mem_type => c_mem_type ,
c_algorithm => c_algorithm ,
c_prim_type => c_prim_type ,
c_byte_size => c_byte_size ,
c_sim_collision_check => c_sim_collision_check ,
c_common_clk => c_common_clk ,
c_disable_warn_bhv_coll => c_disable_warn_bhv_coll ,
c_disable_warn_bhv_range => c_disable_warn_bhv_range ,
c_load_init_file => c_load_init_file ,
c_init_file_name => c_init_file_name ,
c_use_default_data => c_use_default_data ,
c_default_data => c_default_data ,
c_has_mem_output_regs_a => c_has_mem_output_regs_a ,
c_has_mux_output_regs_a => c_has_mux_output_regs_a ,
c_write_width_a => c_write_width_a ,
c_read_width_a => c_read_width_a ,
c_write_depth_a => c_write_depth_a ,
c_read_depth_a => c_read_depth_a ,
c_addra_width => c_addra_width ,
c_write_mode_a => c_write_mode_a ,
c_has_ena => c_has_ena ,
c_has_regcea => c_has_regcea ,
c_has_ssra => c_has_ssra ,
c_sinita_val => c_sinita_val ,
c_use_byte_wea => c_use_byte_wea ,
c_wea_width => c_wea_width ,
c_has_mem_output_regs_b => c_has_mem_output_regs_b ,
c_has_mux_output_regs_b => c_has_mux_output_regs_b ,
c_write_width_b => c_write_width_b ,
c_read_width_b => c_read_width_b ,
c_write_depth_b => c_write_depth_b ,
c_read_depth_b => c_read_depth_b ,
c_addrb_width => c_addrb_width ,
c_write_mode_b => c_write_mode_b ,
c_has_enb => c_has_enb ,
c_has_regceb => c_has_regceb ,
c_has_ssrb => c_has_ssrb ,
c_sinitb_val => c_sinitb_val ,
c_use_byte_web => c_use_byte_web ,
c_web_width => c_web_width ,
c_mux_pipeline_stages => c_mux_pipeline_stages ,
c_use_ecc => c_use_ecc ,
c_use_ramb16bwer_rst_bhv => c_use_ramb16bwer_rst_bhv
)
port map (
clka => clka ,
ssra => ssra ,
dina => dina ,
addra => addra ,
ena => ena ,
regcea => regcea ,
wea => wea ,
douta => douta ,
clkb => clkb ,
ssrb => ssrb ,
dinb => dinb ,
addrb => addrb ,
enb => enb ,
regceb => regceb ,
web => web ,
doutb => doutb ,
dbiterr => dbiterr ,
sbiterr => sbiterr
);
end implementation;
| mit | 79b85afd3a3200f55cd900260a6187c4 | 0.475532 | 3.456067 | false | false | false | false |
nickg/nvc | test/lower/synopsys1.vhd | 1 | 767 | package synopsys1 is
type std_ulogic_vector is array (natural range <>) of bit;
type line is access string;
type side is (left, right);
subtype width is natural;
end package;
package body synopsys1 is
type char_indexed_by_MVL9 is array (bit) of character;
constant MVL9_to_char: char_indexed_by_MVL9 := "01";
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
--write(l, s, justified, field);
end WRITE;
end package body;
| gpl-3.0 | b821f2d8c4775e89d935b908e572bd02 | 0.625815 | 3.600939 | false | false | false | false |
nickg/nvc | test/regress/agg7.vhd | 1 | 654 | entity agg7 is
end entity;
architecture test of agg7 is
begin
main: process is
variable x : integer_vector(1 to 4);
variable y, z : integer_vector(1 to 2);
begin
x := ( integer_vector'(1, 2), integer_vector'(3, 4) );
assert x = (1, 2, 3, 4);
y := (5, 6);
z := (7, 8);
x := ( y, z );
assert x = (5, 6, 7, 8);
x := ( 1 to 2 => z, 3 to 4 => integer_vector'(1, 2) );
assert x = (7, 8, 1, 2);
x := ( 4 downto 1 => x );
assert x = (7, 8, 1, 2);
x := ( y, 9, 8 );
assert x = (5, 6, 9, 8);
wait;
end process;
end architecture;
| gpl-3.0 | 15cf38dadecd9a08745d2a3e07c5fa60 | 0.434251 | 3.013825 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue301/packages/pkg_param.vhd | 7 | 2,076 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Parameters
--! @author Markus Fehrenz
--! @date 2011/07/01
--!
--! @details This is the configuration file of the Viterbi decoder.
--! Any changes for parameters should be done here.
--! Changing parameters somewhere else may result in a malicious
--! behavior.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_param is
-----------------------------------
-- Convolutional Code Parameters --
-----------------------------------
--
-- Set the number of parity values
-- This has to correspond to PARITY_POLYNOMIALS
--
constant NUMBER_PARITY_BITS : natural := 2;
type t_parity is array (NUMBER_PARITY_BITS - 1 downto 0) of natural;
--
-- Set parity polynoms in decimal notation
-- NUMBER_PARITY_BITS has to correspond to the number of elements
-- Examples: WiFi : [121,91] or [121,91,101]
-- CDMA : [491,369] or [367,435,369] or [501,441,331,315]
-- GSM : [27,19] or [27,21,31]
-- DAB : [91,121,101,91]
-- WiMAX: [91,121,117]
--
constant PARITY_POLYNOMIALS : t_parity := (121,91);
--
-- Set a recursive polynomial
-- Set to 0 if no recursion is used
-- Setting this arbitrary may result in a worse error correction ability
--
constant FEEDBACK_POLYNOMIAL : natural := 0;
-----------------------------
-- Architecture Parameters --
-----------------------------
--
-- Set bit width of LLR input
-- Recommended values: 3 or 4
--
constant BW_LLR_INPUT : natural := 4;
--
-- Set the maximum window length which shall be allowed at runtime.
-- Recommended: at least 6 * constraint length
--
constant MAX_WINDOW_LENGTH : natural := 96;
--
-- Set to 'true' if distributed RAM shall be used
-- Set to 'false' if block RAM shall be used
--
constant DISTRIBUTED_RAM : boolean := true;
end package pkg_param;
| gpl-2.0 | 1bde518b37d0968aedf8ddc34d03f495 | 0.614644 | 3.59792 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_pipe_v3_0_2/xbip_pipe_v3_0.vhd | 9 | 8,323 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
iX1WH6lCwGPTfoT4q/xNrK1Aj2reaQarfseiUAS/ifZXhEwoB6oE2D6RZAFaF0LKNSam6Ru10gWw
5pLuKoROIQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
bARjz+rQAsd4I8CGYLjXNRkBYuWKzzuB9PMbJDCJ04njXAjtXL/+6vyr+nxazh3VyCYSnkr5TJI7
Ve5ZLr6quqhg31JXTykN7hQnYHCd9kyM7r0OxtPDQ1LBVhMXDkYfsb9It5sObCsIyuqLphQn9OPb
TnXAYHH1Blz3OHUzqJg=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
uhPlqy3xo1NihYW65X7CDC709m7cEaomoqflzTMuS/8WBbp6sRi4syCpke34NLfAuO5W2qaz0R6K
WEYPH+EiH235nzNLMA8J24xu5dT9joybYah3TPZ0DYhTF75c6itxyHJIMV1xl+556A7yxyTqF8zi
s7XwcSTxQDJDiuMSoCU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Eb4QcmBeu+Cl8swJPx7VDsvjSfEWrnkHhWG4rWRwsc73fhQAQLplR4cWpWgTSreaLZ4C48JupiM9
B2hgDC4DJky8pusJSDf2FgZJphdDMwHLGDGbvr4ojVfULIp5wq91+a0GQnWhNlTKEmY5lBkY/P4n
7kf1Z9mEwremI8vQ2FD1+UlD5xKMI9lLLJVag6NZ1YkXBsVJcDVAo6BFDwhoEk09WbjqU65vcpB7
TL8fY7vF4lLCxbhnxZdd/P8p5EcddQnV5zhwTDPiVunMZ3hX4XFz2AQeYuapAnELVOwngFw/ukl/
7rL9ZrqYTxZjst53Sx3KBWP8KZxhzQUaTCr+vQ==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
CVMWmA316JheGpWyNHL/MR7hELV6yopB7vREjYADDQToPcmx+apIakfQlTn+lUhbK8TYawVFWrMW
8PVl9nMkWkYU6XADi6k34a09IpJNL/zeeeR9RCXkOOAFO6i0pT+HWPb/mM+mAEusd4sZJFgErDAW
5nJsfDAJaDxrOASWGYFYEhQkMoNA7UNtmA6oAGI4jfWX94mAA3Zr5lTvq25xDQ9oyKTdcZCIpiiC
Olb288Irph+QJBryAyW6n8zFiZg9eG8BRH7elDSTqTNXP1pu2v2r6L/uBeSc84gGz+5wZijOYm5p
fh3s11Kcsikk8/7ECM//T89z/v2tqdQKtlsxmA==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mTHmFURTiwMZxNH+DQsg+aX9Oa+gLa+goHbf9Wxe/MlyJHwoCuP3Q5v/Q77VpR/j1dlxGRKVGWYa
yxG6QgffcjhepHu/PcrwyyCoKhWjCNM5zi+Ot4+wTUhVBVdEJiP6WaXp4cnaIemA+otZGCMu2sX3
qnsAP9E78Xd/i7bWf42AAREfamnrdHKEIM0h7CWavLUaIZNnqa4lk91Uu7RPd225C5Psd9JD95vP
eu4FnUKLoOlr5PEsChnJwV4j2zhf9hh3PLsVUF/pW0oC6mECK5kHdByNct7cUUWMPn5vvIYimb3+
5AT2S53HD36AKdsgk5tHDf9csmg0fD3RLMSzNw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
/szp2oV7ktTa9Pb86zLCM3Q9zWV5CmdfEmzwXwgG1w7Yt2gBE/CAlXNOrMC/NiBkJm2Orivp8b3P
cTUkeiWE2t+dK/VR+bg+S5Ch+5soFd9mjwKv0L9QZyw0v4CPGbOzU4lt8RYdyTEPJGq1/VIB9Qld
tuj75igt9YcVgKhsH8ggRfqnghf2fWMilzLKcSACsMOu5JUyGZpceEQQ8icwtSZ//fHIYReZb8LD
ph6/WiUPRjgg85rCPxFJ2N11Wk08dxsDByqnru+yP2D9D8Q+kVyvxmHgRQIAkflppVrHd39dwxmf
bS8BvK2iZ9EDQsuthss90PZi4JvwgxFDLNJDz7H9QMna2L6qQo1IAOKfDITsRWG8KKHEc52rXHmS
j5/FWb9ybK4aTIduvIUCkTG+2uXSfGCSmp5ugLxpvWSYOdjLa87WMlpcxR0WFmCENNmOAvr8/x+U
LzpZO5hXBMoP+g4u9Ih3y7cYY2Fz8ftJAyyN7i/xEC3gPwxPWUDqewSq0iCMdNn2gYDoSZJhiF19
Z8YG6lZcIIzKGxovspYG+nWO1DbceQchk0YBnM+3uY2sUST8R05tBMm7Kvmb5m0ioG1FJ3fH9oBU
WKSqYoQHczCr0Rd69TkwxciU+VyLdhyhC/d0mSfVtO6pkWKUc+2O/E+VjTqma043PzpYOXTbjATJ
TkkiD2q4GmRPtKnKJHGqO20PmLwFJycMIvILa2hjeUsvd9Rnp9dpQVtDW6Rj4FXox7tM/70k010M
3yz8aWjicBWnuC68FXp071/J+BXaPFBhHoc6b0RzXe9ILJOeI6YtGozNeSfBIw+KOz9tt80t0IlI
E0OtSp0dPMYyr7QlzaHTLZ8Ut7AG8ubKrI6ocnpJUbha4mMNOGpbU3wo5jKRySKBeKmF227D8LZf
moGO8T9xLQbM/1siKovu9d5IBjUJOL9uUU/ooHHXPNIQrOntRp4Ci6Mynq8m/cwQVWUddooBofGV
AwbyYSpGrBlT2brY2F8z/x5WVEZ6gmp7Ri6dI8xBX9JzrKLuY+izWJ+Tx9jYjPlbrvG32JVZyajT
i5u61UpaT8PRLu/ph8mpGRJJEIBoetg7V7kXmIDUXSjc39iZiRKkvLbKL/1bQRMx4U0f72YTZgeS
24Ll04sxa7zprL0QTexfDaywXbjWxfp8TmT1P3DOCUKvPkqKjWsOi4jJw5u/5QYRL7Q/xXNhw5wa
pBmXzricvF5C5LKhRTG6EeCng+LiVCpdDXaeugV117XxoKvIF6n06uM7j0ZPB5+MF3ewu1KDPsTg
hBJebYsLe94ygDfEmWhP+eO3580eRFqjbZy+C8MOLOaUIy3Kl5FQsEM1jtVzU/XfTs1QD9DZqTxG
+pSGoWKjgVZ7VEt9VNX/F8gO5mthcRTK8bm4r+f2ebZJp4rqaXq4sBPCqTMI1eJn2JB188f0cfK1
MzSEGPBn81EWC306H3xq9a8BSS0X6i2mCSkou/eRclXmM3/TNr7p1KuDpmAMTRDsyjJGr8afkdI3
bNDBBnnRPfNGzNYwPHzn6mnbcLeeSKa2drCE9fqBo2i0O7owzs4t9EiY+KkdoJ2F7RgztMyFjcdr
KDAcKNbXLaHDMHZUmoXNEXswOYPzXl5rEc428midkOAb6KAslYvkQcRl6wD7udPzclVMvOOfpGKN
pjrMgFQb2wgJqQ0uXBhVeHFy4r/e+r+xzN7lgQRiv+gz0qoVgyUIT6mymI1S2vYkE2jdT3kGdz28
Kl9sFXtxFjs3YRbez85ofJKvVHvgGjmO/Ogb3PKBNKNXqIiVDRRBFpkYA+DtRGTvLZsw82l8tnTZ
zgHWG0DvXVYVoH73+BjL2bv4bv3326N9lLJKYRWSj2LyY3DaUzgifGRr6kWeRtxLHyXGs/Ie49Rd
dWaIF4kfVwbwLWxzJAsI0sBxB9PWHq5EI9E74KZ8B1pVLsx65/8jGetaAp/Xfykfvw5VnCeox4qx
Nyino2Yh+VuRE+RR/8+JcNC2p+hUwRiwD4V+XR/GMrkqxvAuqo0LB74+XPgI4jRzGEAzrk2pxOR3
GBdG80xJ5ZwQ/aCKBIyyvoKtNcjTv19WbBJcpJxK3n9bbcDtxMGWlNhq+Gb/pHLCs0Z7GJne+HOr
z/wyhWQI3Q1J0qw6bVQRbLS60l+bWwtJ7s1PIFO3bnOt4ohRJxWgX06sbAoYb1VSWcaWoVrTRzDK
Kgmw1A0F8YdW/3npQ3Eu/CoFLR4xVU4YYZ5mREJJS+sVE9I/CIfvvUzarB8EZ2qAKCZzEYaD/kjL
JtMnhKdGckrdQwhlC1niHMyyViMG9ke62Kh5AdCnMuiJAAVrsp8ktAmN6lTIi5pwXI6pGCRrKrwQ
v5RnbA9bT675EmePIC/fudAxY5W1QVvLG5r1PVzLO4bwc6b8qm4zkHHF9tJA/pOY4jRYgdpK2PsS
J+VlwscJpfjtr0PMhfIKPG23ITP1PA9jaZwl/Biv4skwEAKBWVzxCHVoOBklicB9uYY96T6qN41/
bJ9LL5O64V36J607DfhAnrCNH7jLuhln1jq5reHPxV/gtUdf3Wy8k/+qKMNdhKgWbC81Ygz5JnPY
fFFTs/HrXjyi9ILtNuoief8MlDHB1lo/NiDyKCCJlW+yYkAzxM3xx0zl65B9sQQfL5nVp/YTlzF6
fMFK4uKSDjezxvh5hJJqHuGqilSUQeX9Trx9SqZELVZqvxpANpG+laqtFMj0Csn8o2cs9dVk2Quk
U3ne/hZNklxZTJ0r4qQYNXvEzcyHlRv4uf5owb3OjIfXnjAFAc2I7ADOGgFkzDLc0by1Kj7+n9Li
HWJ2kluYSZvKSUIPiF3qfMG62cvTx2c20Czpo63jF0CLEfqi2sKYPLb2syl27uNdhLx2US7ppqew
hpb2CkW1TUxLZnHUWi+MemjzoCTPCYtUUDXo+3YlFtuIogDEsE0HzRz+KVF46t5PK3ROKkWZv1IE
sloN8idZmFiagWsz7FKX2MDhX5eQDgW+rITuAGtPEqJJD2l7ohftOR5p1rQVf6OxclFtPpkxsApO
M4fwoTde0GAgW0VDux58ZhiDZ8QP96Y9t7q6RJG5EiiaODgJReo9tnbVtT2sspaP8RMzvIEv7Xen
mhHM52ZW3srt8SLNeM4fDISMlM/w0bLGuQRkp4BtgsbfVsupjyYuxmlAhBkgvIpTE+ajVF0ECqgU
gQi4zDIlWPidGKYMuriD0NAduFRHYWlKAt9fBUVm7+vEEYbcUWg+d+gQow15KMjLL6AVyJXx93fR
MFtsUoBCuaHZ+6/SNB/8tiPnvwNvdj5Eho7zsWlOEdm6tIWhUfDSxjepKOLNKIEeReV/Ha34QM6R
pCy4uLSLyv1vZPLui/y1M3ecJ1ufYmdPrwKdBzLryUVgqDezFyvc2OKR2CwKMq9xi6mQnz5PNrBE
BwrohnNRVkwlCx82NZLEdu80OY18BomVXYofYrzn7FR7JE9zoX6koMnbIeO6TbsBRlirHS+7APmN
pggE6K6RbOgFvmw9SYzCkID8iFpHKgYhyjBpWdB332yBW1eA9Vl2coKWCb8Gd1ceDRBcXQteMGoh
DdZHitmfuc6hA+TQ80ZY12fG1cuOGqEKhLIPPJNdaLFpTAlqgwDHP3HD6S9i0vGbhk/GGPC8J+e8
RGD2Y8ssq5GguuTDNfqTYUij56hNIbyIThB4efQZI4CoYzwM+bNDqHQ1fADEutkzMsI6JnUIxE5j
1OjhR8LGX0hjM+QRmF3msTKj5F6r+EmostCrzPea+HZtyrfS+0o40wKZgodfj5yxIBhctEWDsec5
vuOCUUJZ3e2CsZmZ1+iG7WUiDJDIiVNaZ/phHTKe1Uf9xYc6FnUTwXAqVO1desALCPmcp7aMsaX7
Xk62m6a+WdKIl/Gb2ya+f0vEHxhxupVoUjxuGAfSL+W4MG0oa5Jo8zMfAt+JSKItJhJHjGIvO/ca
ffT24irnvq8SXstc9LiJTIRpyjnwVKpWHspi5G6WoEArVVVtHSeC2Zo/PeI+rROiMv9HeYloVClJ
wnKqEkojI1H9ttdnvrXmH5znoquf0Qc00cacfcQaKKWVDxG8kRTEJ4yKPfUJsSUOCsANrb/8Bo7Y
x9jvwQ+O9AxY9QXNnRKvN2qQo+pMpUvRwc/UHdEcDOKjS5vWHv31ne4dO46dw9dyNS/CDAuwR6AY
NaMbmj+k5S151reMsu4LVm/BYe3UPLGiz82moIwxLXWV9Il9P+pisjCJVRv3eBCmRFpf4JQi77Lf
8gdjaE2GE677DrkuYn/PIYH/Y4DVJI0VVX9xFvRdysIxTRUcdUxvjTRsGsv+A6awBjiIokhzqfqr
W88rCGLbsHFBN15L1BybYgLmfIQ4m+xpRHynavEEu5KirtZzxDlf5Us/TBw5m4z3f6NnEZT+ixfp
1OeLK1bZXrca+5uCiWQo6DOgbQ2qdHqODrrfukspDcTT8ZU6SWHtbtKAVJowrVvnMlJ0pX9NYivn
S+P1jwfFeIOTA2y7IkKyO+gEzEbzP6WhqD+F89qgBbl6lpySc+45fAnYXjZl88AvUPwE3ol20AIp
wgi5mARVMdpPewlixL160A4KeRr7kN4ZcmF8rd4HLDihfJoWpdIt/feAqSiXPxN5MF/lswHbqy7I
BGhf6RagRSJ/I8HXTzERjwks8gDrVIFLdY7Im+TDs4s5b2YJOf4A7PiGmDpjxKxDkHPppG0ugo7q
B2B3z5ZzThh1XkuGYFV+okoKpJ+0eUb4o2tl+iZnLMSm23KCdzCY4O7AlZ8HxNweQHu5+lrhr0QS
tK1oqFvbOeHuuiIFHKw1Lpge19XexXp2KUZ5cW+EAtw7axBEYw4bOeZOoVEdT3cKe9XxrmlW0M6n
VAcz52VHkQh3rP1DdxGZ3yxHXNYnjFRcYxtLMEfLRBCTPShTEZKTNQ43eOrCGlXR7KqbqR6ma2K0
ZvCGvDkN1icHQzCL9LZWI5MHuAqibpfQcxGltkYQG5ZrnJyrBtCo0FdZLFm+7oF2yxM55upD3O4O
pcjkS6l/ZUUFfKzbG/FiyPjQ95/WpoXfE0U6s8ADkqKzVv/mzYvots5dJKRDYCCfhTgI/n4WycJh
s6VecTTqeykQ5dhB0tXvZhS2QYNM6zsF6vK67OYDrjk4wJ5MFS5r7V+U0HAxlKssarY6GJ+ukVfv
cg6vg5OqpqqlF5fLJ9OIdr1P09+97TJoWJZ1H8yIZ4UGZL26B4JC2xZKgsbfLqEo8cDYON2AlTCp
yuMzIDX8PyObFHkcNnud2vNPudIh8uhVSWwLejW1XdGagr+5FLhzZ6eHaxNnSetYOpwTOed2z9lJ
PHEKZGSDwU1T5nUPNw/xFx5ho/Csrt9so9amr/ef8xYHPpYKXjqaBygy
`protect end_protected
| gpl-3.0 | ad8540b9bacc43d2c3cce274d3a68ee1 | 0.912051 | 1.962046 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd | 4 | 8,163 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc762.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00762pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00762pkg;
use work.c01s01b01x01p05n02i00762pkg.ALL;
ENTITY c01s01b01x01p05n02i00762ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00762ent;
ARCHITECTURE c01s01b01x01p05n02i00762arch OF c01s01b01x01p05n02i00762ent IS
constant Vgen1 : boolean := true;
constant Vgen2 : bit := '1';
constant Vgen3 : character := 's';
constant Vgen4 : severity_level := note;
constant Vgen5 : integer := 3;
constant Vgen6 : real := 3.0;
constant Vgen7 : time := 3 ns;
constant Vgen8 : natural := 1;
constant Vgen9 : positive := 1;
constant Vgen70 : boolean_vector_st :=(others => Cgen1);
constant Vgen71 : severity_level_vector_st :=(others => Cgen4);
constant Vgen72 : integer_vector_st :=(others => Cgen5);
constant Vgen73 : real_vector_st :=(others => Cgen6);
constant Vgen74 : time_vector_st :=(others => Cgen7);
constant Vgen75 : natural_vector_st :=(others => Cgen8);
constant Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00762"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00762 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00762arch;
| gpl-2.0 | 67f2de24e5157d3df989cad377557132 | 0.601985 | 3.888995 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_205.vhd | 2 | 1,846 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_205 is
port (
gt : out std_logic;
ge : out std_logic;
lt : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_205;
architecture augh of sub_205 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
ge <= tmp_ge;
lt <= not(tmp_ge);
le <= tmp_le;
end architecture;
| gpl-2.0 | 4561c2a58359df28e11b12a255495076 | 0.619177 | 2.549724 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue810/repro.vhdl | 1 | 278 | entity repro is
end;
architecture behav of repro is
type my_time is range -integer'low to integer'high units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
begin
end behav;
| gpl-2.0 | 962cae7881542752de8173f6ba2abef8 | 0.597122 | 3.232558 | false | false | false | false |
nickg/nvc | test/regress/issue542.vhd | 1 | 443 | entity issue542 is
end entity;
architecture beh of issue542 is
signal s : bit_vector(1 to 3);
begin
p_proc : process
procedure proc(
signal target : inout bit_vector) is
begin
target(target'range) <= (others => '0'); -- Issue is here
end;
begin
s <= "111";
wait for 1 ns;
proc(s);
assert s = "111";
wait for 0 ns;
assert s = "000";
wait;
end process;
end architecture;
| gpl-3.0 | 47cd889d5ae009de73d1c187013e11c7 | 0.577878 | 3.488189 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec02.vhdl | 1 | 481 | entity tb_rec02 is
end tb_rec02;
library ieee;
use ieee.std_logic_1164.all;
use work.rec02_pkg.all;
architecture behav of tb_rec02 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec02
port map (inp => inp, o => r);
process
begin
inp <= '0';
wait for 1 ns;
assert r = (b => '1', a => 5) severity failure;
inp <= '1';
wait for 1 ns;
assert r = (b => '0', a => 3) severity failure;
wait;
end process;
end behav;
| gpl-2.0 | b856519d35e16b067204d77250b8dcdb | 0.592516 | 2.95092 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd | 4 | 1,796 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofp-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of to_fp is
begin
behavior : process (vec) is
variable temp : bit_vector(vec'range);
variable negative : boolean;
variable int_result : integer;
begin
temp := to_bitvector(vec);
negative := temp(temp'left) = '1';
if negative then
temp := not temp;
end if;
int_result := 0;
for index in vec'range loop -- sign bit of temp = '0'
int_result := int_result * 2 + bit'pos(temp(index));
end loop;
if negative then
int_result := (-int_result) - 1;
end if;
-- convert to floating point and scale to [-1, +1)
r <= real(int_result) / real(2**15);
end process behavior;
end architecture behavioral;
| gpl-2.0 | 7abf69352c9e565459300828bd10be97 | 0.593541 | 4.147806 | false | false | false | false |
tgingold/ghdl | testsuite/synth/oper01/snum06.vhdl | 1 | 729 | entity snum06 is
end snum06;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum06 is
begin
assert signed'("0100") * signed'("001") = signed'("0000100");
assert signed'("0101") * signed'("001") = signed'("0000101");
assert signed'("0101") * signed'("011") = signed'("0001111");
assert signed'("11") * signed'("11") = signed'("0001");
assert signed'("10") * signed'("11") = signed'("0010");
assert signed'("10") * signed'("01") = signed'("1110");
assert signed'("01") * signed'("10") = signed'("1110");
assert unsigned'("1011") * unsigned'("000011") = unsigned'("0000100001");
-- assert false report to_bstring(unsigned'("1011") * unsigned'("000011"));
end behav;
| gpl-2.0 | b0d982d5b758b4d00ff2e6dd2b3f8714 | 0.631001 | 3.681818 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug23165/mwe_working/mwe.vhd | 3 | 909 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);
signal ctl_cnt_tmp : ctl_sig(0 to cnt_stages-1);
signal clk : std_logic := '0';
begin
clk <= not clk after 50 ns;
controller : entity work.counter
generic map(
width => cnt_len
)
port map(
clk => clk,
q => ctl_cnt(0)
);
-- workaround: use concurrent assignment of temporary signal
bla : for k in 1 to cnt_stages-1 generate
ctl_cnt(k) <= ctl_cnt_tmp(k);
end generate bla;
ctl_cnt_delay : process
begin
wait until rising_edge(clk);
for i in 0 to cnt_stages-2 loop
-- then this works...
ctl_cnt_tmp(i+1) <= ctl_cnt(i);
end loop;
end process;
end lulz;
| gpl-2.0 | bed653ae6bcf4e1a311e7bf0434ae43f | 0.668867 | 2.713433 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_afifo_autord.vhd | 7 | 15,525 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 | 4be9b0351566276c4a626a1b488c34fd | 0.475556 | 4.203899 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd | 4 | 2,234 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2287.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02287ent IS
END c07s02b06x00p32n01i02287ent;
ARCHITECTURE c07s02b06x00p32n01i02287arch OF c07s02b06x00p32n01i02287ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 fs;
assert NOT( ((1 fs * 1000) = 1 ps) and
((1 ps * 1000) = 1 ns) and
((1 ns * 1000) = 1 us) and
((1000 * 1 fs) = 1 ps) and
((1000 * 1 ps) = 1 ns) and
((1000 * 1 ns) = 1 us) )
report "***PASSED TEST: c07s02b06x00p32n01i02287"
severity NOTE;
assert ( ((1 fs * 1000) = 1 ps) and
((1 ps * 1000) = 1 ns) and
((1 ns * 1000) = 1 us) and
((1000 * 1 fs) = 1 ps) and
((1000 * 1 ps) = 1 ns) and
((1000 * 1 ns) = 1 us) )
report "***FAILED TEST: c07s02b06x00p32n01i02287 - Multiplication of a predefined physical type by an integer test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02287arch;
| gpl-2.0 | 19a0fe76f7ac26376cce13460bf62c6e | 0.582811 | 3.644372 | false | true | false | false |
nickg/nvc | test/regress/record23.vhd | 1 | 497 | entity record23 is
end entity;
architecture test of record23 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
r : rec1;
end record;
signal s1 : rec1;
signal s2 : rec2;
begin
main: process is
begin
s1 <= (3, 4);
wait for 1 ns;
s2 <= (r => s1); -- Error here
wait for 1 ns;
assert s2.r.x = 3;
assert s2.r.y = 4;
wait;
end process;
end architecture;
| gpl-3.0 | 095bf83099272a6e05970e54b0adefcb | 0.509054 | 3.451389 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_smple_sm.vhd | 3 | 16,881 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
| gpl-3.0 | b70a0ce39ac1d0e2682f939ee3f2eca8 | 0.382264 | 5.447241 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd | 4 | 3,386 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity fg_07_03 is
end entity fg_07_03;
library bv_utilities;
architecture interpreter of fg_07_03 is
subtype word is bit_vector(31 downto 0);
signal address_bus, data_bus_in : word := X"0000_0000";
signal mem_read, mem_request, mem_ready : bit := '0';
begin
-- code from book
instruction_interpreter : process is
variable mem_address_reg, mem_data_reg,
prog_counter, instr_reg, accumulator, index_reg : word;
-- . . .
-- not in book
type opcode_type is (load_mem);
constant opcode : opcode_type := load_mem;
constant displacement : word := X"0000_0010";
use bv_utilities.bv_arithmetic.all;
-- end not in book
procedure read_memory is
begin
address_bus <= mem_address_reg;
mem_read <= '1';
mem_request <= '1';
wait until mem_ready = '1';
mem_data_reg := data_bus_in;
mem_request <= '0';
wait until mem_ready = '0';
end procedure read_memory;
begin
-- . . . -- initialization
loop
-- fetch next instruction
mem_address_reg := prog_counter;
read_memory; -- call procedure
instr_reg := mem_data_reg;
-- . . .
case opcode is
-- . . .
when load_mem =>
mem_address_reg := index_reg + displacement;
read_memory; -- call procedure
accumulator := mem_data_reg;
-- . . .
end case;
end loop;
end process instruction_interpreter;
-- end code from book
memory : process is
begin
wait until mem_request = '1';
data_bus_in <= X"1111_1111";
mem_ready <= '1';
wait until mem_request = '0';
mem_ready <= '0';
end process memory;
end architecture interpreter;
| gpl-2.0 | a6bb7d14de99f94f420d86d9278b8de9 | 0.485529 | 4.769014 | false | false | false | false |
pleonex/Efponga | Pong/pong.vhdl | 1 | 4,859 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY pong IS
PORT(
clock : IN STD_LOGIC;
-- Puertos VGA
vga_red : OUT STD_LOGIC;
vga_green : OUT STD_LOGIC;
vga_blue : OUT STD_LOGIC;
vga_blank : OUT STD_LOGIC;
vga_hs : OUT STD_LOGIC;
vga_vs : OUT STD_LOGIC;
vga_clk : OUT STD_LOGIC;
-- Controles de juego
btn_up1 : IN STD_LOGIC;
btn_down1 : IN STD_LOGIC;
btn_up2 : IN STD_LOGIC;
btn_down2 : IN STD_LOGIC;
-- Marcados de 7 segmentos
hex00 : OUT STD_LOGIC;
hex01 : OUT STD_LOGIC;
hex02 : OUT STD_LOGIC;
hex03 : OUT STD_LOGIC;
hex04 : OUT STD_LOGIC;
hex05 : OUT STD_LOGIC;
hex06 : OUT STD_LOGIC;
hex20 : OUT STD_LOGIC;
hex21 : OUT STD_LOGIC;
hex22 : OUT STD_LOGIC;
hex23 : OUT STD_LOGIC;
hex24 : OUT STD_LOGIC;
hex25 : OUT STD_LOGIC;
hex26 : OUT STD_LOGIC
);
END pong;
ARCHITECTURE funcional OF pong IS
-- Escenario
COMPONENT escenario
PORT (
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Controles del juego
btn_up1 : IN STD_LOGIC;
btn_down1 : IN STD_LOGIC;
btn_up2 : IN STD_LOGIC;
btn_down2 : IN STD_LOGIC;
-- Marcados de 7 segmentos
hex00 : OUT STD_LOGIC;
hex01 : OUT STD_LOGIC;
hex02 : OUT STD_LOGIC;
hex03 : OUT STD_LOGIC;
hex04 : OUT STD_LOGIC;
hex05 : OUT STD_LOGIC;
hex06 : OUT STD_LOGIC;
hex20 : OUT STD_LOGIC;
hex21 : OUT STD_LOGIC;
hex22 : OUT STD_LOGIC;
hex23 : OUT STD_LOGIC;
hex24 : OUT STD_LOGIC;
hex25 : OUT STD_LOGIC;
hex26 : OUT STD_LOGIC
);
END COMPONENT;
-- PLL para adaptar reloj (50 MHz -> 25 MHz)
COMPONENT vga_PLL
PORT(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END COMPONENT;
-- Controlador de VGA
COMPONENT vga_sync
PORT(
clock_25Mhz : IN STD_LOGIC;
red : IN STD_LOGIC;
green : IN STD_LOGIC;
blue : IN STD_LOGIC;
vga_red : OUT STD_LOGIC;
vga_green : OUT STD_LOGIC;
vga_blue : OUT STD_LOGIC;
vga_blank : OUT STD_LOGIC;
vga_hs : OUT STD_LOGIC;
vga_vs : OUT STD_LOGIC;
vga_clk : OUT STD_LOGIC;
pixel_row : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Variables
SIGNAL clock_25MHz : STD_LOGIC;
SIGNAL Red_Data : STD_LOGIC;
SIGNAL Green_Data : STD_LOGIC;
SIGNAL Blue_Data : STD_LOGIC;
SIGNAL vert_sync : STD_LOGIC;
SIGNAL pixel_col : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL pixel_row : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
vga_vs <= vert_sync;
-- Conexión de componentes
PLL: vga_pll PORT MAP (
inclk0 => clock,
c0 => clock_25Mhz
);
SYNC: VGA_SYNC PORT MAP (
clock_25Mhz => clock_25MHz,
red => red_data,
green => green_data,
blue => blue_data,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_blank => vga_blank,
vga_hs => vga_hs,
vga_vs => vert_sync,
vga_clk => vga_clk,
pixel_row => pixel_row,
pixel_column => pixel_col
);
ESCE: escenario PORT MAP (
Red => red_data,
Green => green_data,
Blue => blue_data,
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_col,
btn_up1 => btn_up1,
btn_down1 => btn_down1,
btn_up2 => btn_up2,
btn_down2 => btn_down2,
hex00 => hex00,
hex01 => hex01,
hex02 => hex02,
hex03 => hex03,
hex04 => hex04,
hex05 => hex05,
hex06 => hex06,
hex20 => hex20,
hex21 => hex21,
hex22 => hex22,
hex23 => hex23,
hex24 => hex24,
hex25 => hex25,
hex26 => hex26
);
END funcional; | gpl-3.0 | 4afe7424ac2e409cab71cb14cbe59aaf | 0.477876 | 3.468237 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_208.vhd | 2 | 1,725 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_208 is
port (
ge : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_208;
architecture augh of sub_208 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
ge <= tmp_ge;
end architecture;
| gpl-2.0 | 79751bca822f6c4c86274c5080a16ef7 | 0.624348 | 2.578475 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.