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|---|---|---|---|---|---|---|---|---|---|---|---|---|
tgingold/ghdl | testsuite/synth/mem01/tb_rom1.vhdl | 1 | 736 | entity tb_rom1 is
end tb_rom1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_rom1 is
signal addr : std_logic_vector(3 downto 0);
signal dat : std_logic_vector(7 downto 0);
begin
dut: entity work.rom1
port map (addr, dat);
process
begin
addr <= "0000";
wait for 1 ns;
assert dat = x"00" severity failure;
addr <= "0101";
wait for 1 ns;
assert dat = x"41" severity failure;
addr <= "1100";
wait for 1 ns;
assert dat = x"fc" severity failure;
addr <= "1011";
wait for 1 ns;
assert dat = x"fb" severity failure;
addr <= "0010";
wait for 1 ns;
assert dat = x"02" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 7fc04cc39bd039f92da6fde24c1c4b52 | 0.599185 | 3.391705 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug037/utils.vhdl | 2 | 32,199 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.my_config.all;
package utils is
-- PoC settings
-- ==========================================================================
constant POC_VERBOSE : BOOLEAN := MY_VERBOSE;
-- Environment
-- ==========================================================================
-- Distinguishes simulation from synthesis
constant SIMULATION : BOOLEAN; -- deferred constant declaration
-- Type declarations
-- ==========================================================================
--+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++
type T_BOOLVEC is array(NATURAL range <>) of BOOLEAN;
type T_INTVEC is array(NATURAL range <>) of INTEGER;
type T_NATVEC is array(NATURAL range <>) of NATURAL;
type T_POSVEC is array(NATURAL range <>) of POSITIVE;
type T_REALVEC is array(NATURAL range <>) of REAL;
--+ Integer subranges sometimes useful for speeding up simulation ++++++++++
subtype T_INT_8 is INTEGER range -128 to 127;
subtype T_INT_16 is INTEGER range -32768 to 32767;
subtype T_UINT_8 is INTEGER range 0 to 255;
subtype T_UINT_16 is INTEGER range 0 to 65535;
--+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Intellectual Property (IP) type
type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT);
-- Bit Order
type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST);
-- Byte Order (Endian)
type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN);
-- rounding style
type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
type T_BCD is array(3 downto 0) of std_logic;
type T_BCD_VECTOR is array(NATURAL range <>) of T_BCD;
constant C_BCD_MINUS : T_BCD := "1010";
constant C_BCD_OFF : T_BCD := "1011";
-- Function declarations
-- ==========================================================================
--+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(a / b)
function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL;
--+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- is input a power of 2?
function is_pow2(int : NATURAL) return BOOLEAN;
-- round to next power of 2
function ceil_pow2(int : NATURAL) return POSITIVE;
-- round to previous power of 2
function floor_pow2(int : NATURAL) return NATURAL;
--+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(ld(arg))
function log2ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(ld(arg)))
function log2ceilnz(arg : positive) return positive;
-- Calculates: ceil(lg(arg))
function log10ceil(arg : POSITIVE) return NATURAL;
-- Calculates: max(1, ceil(lg(arg)))
function log10ceilnz(arg : POSITIVE) return POSITIVE;
--+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++
function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN;
function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER;
function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL;
function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC;
function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR;
function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED;
function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER;
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING;
--+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers
alias rmin is IEEE.math_real.realmin[real, real return real];
-- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals
function imin(vec : T_INTVEC) return INTEGER; -- Calculates: min(vec) for a integer vector
function imin(vec : T_NATVEC) return NATURAL; -- Calculates: min(vec) for a natural vector
function imin(vec : T_POSVEC) return POSITIVE; -- Calculates: min(vec) for a positive vector
function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector
function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers
alias rmax is IEEE.math_real.realmax[real, real return real];
-- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals
function imax(vec : T_INTVEC) return INTEGER; -- Calculates: max(vec) for a integer vector
function imax(vec : T_NATVEC) return NATURAL; -- Calculates: max(vec) for a natural vector
function imax(vec : T_POSVEC) return POSITIVE; -- Calculates: max(vec) for a positive vector
function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector
function isum(vec : T_NATVEC) return NATURAL; -- Calculates: sum(vec) for a natural vector
function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector
function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector
function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector
--+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- to integer: to_int
function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER;
-- to std_logic: to_sl
function to_sl(Value : BOOLEAN) return STD_LOGIC;
function to_sl(Value : CHARACTER) return STD_LOGIC;
-- to std_logic_vector: to_slv
function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR; -- short for std_logic_vector(to_unsigned(Value, Size))
-- TODO: comment
function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER;
function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER;
-- is_*
function is_sl(c : CHARACTER) return BOOLEAN;
--+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++
-- Aggregate functions
function slv_or (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_nor (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_and (vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC;
function slv_xor (vec : std_logic_vector) return std_logic;
-- NO slv_xnor! This operation would not be well-defined as
-- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd.
-- Reverses the elements of the passed Vector.
--
-- @synthesis supported
--
function reverse(vec : std_logic_vector) return std_logic_vector;
function reverse(vec : bit_vector) return bit_vector;
function reverse(vec : unsigned) return unsigned;
-- scale a value into a range [Minimum, Maximum]
function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL;
-- Resizes the vector to the specified length. The adjustment is make on
-- on the 'high end of the vector. The 'low index remains as in the argument.
-- If the result vector is larger, the extension uses the provided fill value
-- (default: '0').
-- Use the resize functions of the numeric_std package for value-preserving
-- resizes of the signed and unsigned data types.
--
-- @synthesis supported
--
function resize(vec : bit_vector; length : natural; fill : bit := '0')
return bit_vector;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0')
return std_logic_vector;
-- Shift the index range of a vector by the specified offset.
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector;
-- Shift the index range of a vector making vec'low = 0.
function movez(vec : std_logic_vector) return std_logic_vector;
function ascend(vec : std_logic_vector) return std_logic_vector;
function descend(vec : std_logic_vector) return std_logic_vector;
-- Least-Significant Set Bit (lssb):
-- Computes a vector of the same length as the argument with
-- at most one bit set at the rightmost '1' found in arg.
--
-- @synthesis supported
--
function lssb(arg : std_logic_vector) return std_logic_vector;
function lssb(arg : bit_vector) return bit_vector;
-- Returns the index of the least-significant set bit.
--
-- @synthesis supported
--
function lssb_idx(arg : std_logic_vector) return integer;
function lssb_idx(arg : bit_vector) return integer;
-- Most-Significant Set Bit (mssb): computes a vector of the same length
-- with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector;
function mssb(arg : bit_vector) return bit_vector;
function mssb_idx(arg : std_logic_vector) return integer;
function mssb_idx(arg : bit_vector) return integer;
-- Swap sub vectors in vector (endian reversal)
function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR;
-- generate bit masks
function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR;
--+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- One-Hot-Code to Binary-Code.
function onehot2bin(onehot : std_logic_vector) return unsigned;
-- Converts Gray-Code into Binary-Code.
--
-- @synthesis supported
--
function gray2bin (gray_val : std_logic_vector) return std_logic_vector;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector;
end package;
package body utils is
-- Environment
-- ==========================================================================
function is_simulation return boolean is
variable ret : boolean;
begin
ret := false;
--synthesis translate_off
if Is_X('X') then ret := true; end if;
--synthesis translate_on
return ret;
end function;
-- deferred constant assignment
constant SIMULATION : BOOLEAN := is_simulation;
-- Divisions: div_*
function div_ceil(a : NATURAL; b : POSITIVE) return NATURAL is -- calculates: ceil(a / b)
begin
return (a + (b - 1)) / b;
end function;
-- Power functions: *_pow2
-- ==========================================================================
-- is input a power of 2?
function is_pow2(int : NATURAL) return BOOLEAN is
begin
return ceil_pow2(int) = int;
end function;
-- round to next power of 2
function ceil_pow2(int : NATURAL) return POSITIVE is
begin
return 2 ** log2ceil(int);
end function;
-- round to previous power of 2
function floor_pow2(int : NATURAL) return NATURAL is
variable temp : UNSIGNED(30 downto 0);
begin
temp := to_unsigned(int, 31);
for i in temp'range loop
if (temp(i) = '1') then
return 2 ** i;
end if;
end loop;
return 0;
end function;
-- Logarithms: log*ceil*
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
function log2ceilnz(arg : positive) return positive is
begin
return imax(1, log2ceil(arg));
end function;
function log10ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 10;
log := log + 1;
end loop;
return log;
end function;
function log10ceilnz(arg : positive) return positive is
begin
return imax(1, log10ceil(arg));
end function;
-- if-then-else (ite)
-- ==========================================================================
function ite(cond : BOOLEAN; value1 : BOOLEAN; value2 : BOOLEAN) return BOOLEAN is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : INTEGER; value2 : INTEGER) return INTEGER is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : REAL; value2 : REAL) return REAL is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STD_LOGIC; value2 : STD_LOGIC) return STD_LOGIC is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BIT_VECTOR; value2 : BIT_VECTOR) return BIT_VECTOR is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : CHARACTER; value2 : CHARACTER) return CHARACTER is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- *min / *max / *sum
-- ==========================================================================
function imin(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
-- function rmin(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 < arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imin(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := INTEGER'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imin(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := NATURAL'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imin(vec : T_POSVEC) return POSITIVE is
variable Result : POSITIVE;
begin
Result := POSITIVE'high;
for i in vec'range loop
if (vec(I) < Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function rmin(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
-- function rmax(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 > arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imax(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := INTEGER'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imax(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := NATURAL'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function imax(vec : T_POSVEC) return POSITIVE is
variable Result : POSITIVE;
begin
Result := POSITIVE'low;
for i in vec'range loop
if (vec(I) > Result) then
Result := vec(I);
end if;
end loop;
return Result;
end function;
function rmax(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function isum(vec : T_INTVEC) return INTEGER is
variable Result : INTEGER;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_NATVEC) return NATURAL is
variable Result : NATURAL;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(I);
end loop;
return Result;
end function;
function isum(vec : T_POSVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(I);
end loop;
return Result;
end function;
function rsum(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := 0.0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
-- Vector aggregate functions: slv_*
-- ==========================================================================
function slv_or(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
variable Result : STD_LOGIC;
begin
Result := '0';
for i in vec'range loop
Result := Result or vec(i);
end loop;
return Result;
end function;
function slv_nor(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return not slv_or(vec);
end function;
function slv_and(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
variable Result : STD_LOGIC;
begin
Result := '1';
for i in vec'range loop
Result := Result and vec(i);
end loop;
return Result;
end function;
function slv_nand(vec : STD_LOGIC_VECTOR) return STD_LOGIC is
begin
return not slv_and(vec);
end function;
function slv_xor(vec : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in vec'range loop
res := res xor vec(i);
end loop;
return res;
end slv_xor;
-- Convert to integer: to_int
function to_int(bool : BOOLEAN; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
begin
return ite(bool, one, zero);
end function;
function to_int(sl : STD_LOGIC; zero : INTEGER := 0; one : INTEGER := 1) return INTEGER is
begin
if (sl = '1') then
return one;
end if;
return zero;
end function;
-- Convert to bit: to_sl
-- ==========================================================================
function to_sl(Value : BOOLEAN) return STD_LOGIC is
begin
return ite(Value, '1', '0');
end function;
function to_sl(Value : CHARACTER) return STD_LOGIC is
begin
case Value is
when 'U' => return 'U';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when OTHERS => return 'X';
end case;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- short for std_logic_vector(to_unsigned(Value, Size))
-- the return value is guaranteed to have the range (Size-1 downto 0)
function to_slv(Value : NATURAL; Size : POSITIVE) return STD_LOGIC_VECTOR is
constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size));
begin
return res;
end function;
function to_index(slv : UNSIGNED; max : NATURAL := 0) return INTEGER is
variable res : integer;
begin
if (slv'length = 0) then return 0; end if;
res := to_integer(slv);
if SIMULATION and max > 0 then
res := imin(res, max);
end if;
return res;
end function;
function to_index(slv : STD_LOGIC_VECTOR; max : NATURAL := 0) return INTEGER is
begin
return to_index(unsigned(slv), max);
end function;
-- is_*
-- ==========================================================================
function is_sl(c : CHARACTER) return BOOLEAN is
begin
case c is
when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true;
when OTHERS => return false;
end case;
end function;
-- Reverse vector elements
function reverse(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high-i)) := vec(i);
end loop;
return res;
end function;
function reverse(vec : bit_vector) return bit_vector is
variable res : bit_vector(vec'range);
begin
res := to_bitvector(reverse(to_stdlogicvector(vec)));
return res;
end reverse;
function reverse(vec : unsigned) return unsigned is
begin
return unsigned(reverse(std_logic_vector(vec)));
end function;
-- Swap sub vectors in vector
-- ==========================================================================
function swap(slv : STD_LOGIC_VECTOR; Size : POSITIVE) return STD_LOGIC_VECTOR IS
CONSTANT SegmentCount : NATURAL := slv'length / Size;
variable FromH : NATURAL;
variable FromL : NATURAL;
variable ToH : NATURAL;
variable ToL : NATURAL;
variable Result : STD_LOGIC_VECTOR(slv'length - 1 DOWNTO 0);
begin
for i in 0 TO SegmentCount - 1 loop
FromH := ((I + 1) * Size) - 1;
FromL := I * Size;
ToH := ((SegmentCount - I) * Size) - 1;
ToL := (SegmentCount - I - 1) * Size;
Result(ToH DOWNTO ToL) := slv(FromH DOWNTO FromL);
end loop;
return Result;
end function;
-- generate bit masks
-- ==========================================================================
function genmask_high(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR IS
begin
if (Bits = 0) then
return (MaskLength - 1 DOWNTO 0 => '0');
else
return (MaskLength - 1 DOWNTO MaskLength - Bits + 1 => '1') & (MaskLength - Bits DOWNTO 0 => '0');
end if;
end function;
function genmask_low(Bits : NATURAL; MaskLength : POSITIVE) return STD_LOGIC_VECTOR is
begin
if (Bits = 0) then
return (MaskLength - 1 DOWNTO 0 => '0');
else
return (MaskLength - 1 DOWNTO Bits => '0') & (Bits - 1 DOWNTO 0 => '1');
end if;
end function;
-- binary encoding conversion functions
-- ==========================================================================
-- One-Hot-Code to Binary-Code
function onehot2bin(onehot : std_logic_vector) return unsigned is
variable res : unsigned(log2ceilnz(onehot'high+1)-1 downto 0);
variable chk : natural;
begin
res := (others => '0');
chk := 0;
for i in onehot'range loop
if onehot(i) = '1' then
res := res or to_unsigned(i, res'length);
chk := chk + 1;
end if;
end loop;
if SIMULATION and chk /= 1 then
report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set."
severity error;
end if;
return res;
end onehot2bin;
-- Gray-Code to Binary-Code
function gray2bin(gray_val : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(gray_val'range);
begin -- gray2bin
res(res'left) := gray_val(gray_val'left);
for i in res'left-1 downto res'right loop
res(i) := res(i+1) xor gray_val(i);
end loop;
return res;
end gray2bin;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(2**value'length - 1 downto 0);
begin
result := (others => '0');
result(to_index(value, 0)) := '1';
return result;
end function;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(value'range);
begin
result(result'left) := value(value'left);
for i in (result'left - 1) downto result'right loop
result(i) := value(i) xor value(i + 1);
end loop;
return result;
end function;
-- bit searching / bit indices
-- ==========================================================================
-- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg.
function lssb(arg : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(arg'range);
begin
res := arg and std_logic_vector(unsigned(not arg)+1);
return res;
end function;
function lssb(arg : bit_vector) return bit_vector is
variable res : bit_vector(arg'range);
begin
res := to_bitvector(lssb(to_stdlogicvector(arg)));
return res;
end lssb;
-- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
function mssb(arg : bit_vector) return bit_vector is
begin
return reverse(lssb(reverse(arg)));
end mssb;
-- Index of lssb
function lssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(lssb(arg)));
end function;
function lssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return lssb_idx(slv);
end lssb_idx;
-- Index of mssb
function mssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(mssb(arg)));
end function;
function mssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return mssb_idx(slv);
end mssb_idx;
-- scale a value into a given range
function scale(Value : INTEGER; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
return scale(real(Value), Minimum, Maximum, RoundingStyle);
end function;
function scale(Value : REAL; Minimum : INTEGER; Maximum : INTEGER; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
variable Result : REAL;
begin
if (Maximum < Minimum) then
return INTEGER'low;
else
Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5);
case RoundingStyle is
when ROUND_TO_NEAREST => return integer(round(Result));
when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_UP => return integer(ceil(Result));
when ROUND_DOWN => return integer(floor(Result));
when others => report "scale: unsupported RoundingStyle." severity FAILURE;
end case;
end if;
end function;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is
begin
if (Maximum < Minimum) then
return REAL'low;
else
return Value * (Maximum - Minimum) + Minimum;
end if;
end function;
function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : bit_vector(vec'low to high2b);
variable res_dn : bit_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end resize;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : std_logic_vector(vec'low to high2b);
variable res_dn : std_logic_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end resize;
-- Move vector boundaries
-- ==========================================================================
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is
variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs);
variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs);
begin
if vec'ascending then
res_up := vec;
return res_up;
else
res_dn := vec;
return res_dn;
end if;
end move;
function movez(vec : std_logic_vector) return std_logic_vector is
begin
return move(vec, -vec'low);
end movez;
function ascend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'low to vec'high);
begin
res := vec;
return res;
end ascend;
function descend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'high downto vec'low);
begin
res := vec;
return res;
end descend;
end package body;
| gpl-2.0 | 8419d914935e4a399f4a788f22b846bb | 0.606106 | 3.535244 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/var06.vhdl | 1 | 555 | library ieee;
use ieee.std_logic_1164.all;
entity var06 is
port (mask : std_logic_vector (1 downto 0);
val : std_logic_vector (15 downto 0);
res : out std_logic_vector (15 downto 0));
end var06;
architecture behav of var06 is
begin
process (all)
variable t : std_logic_vector (15 downto 0);
begin
t := (others => '0');
if mask (0) = '1' then
t (7 downto 0) := val (7 downto 0);
end if;
if mask (1) = '1' then
t (15 downto 8) := val (15 downto 8);
end if;
res <= t;
end process;
end behav;
| gpl-2.0 | 21eaa97ce9ca586b7fc59be356f23248 | 0.581982 | 3.083333 | false | false | false | false |
nickg/nvc | test/lower/choice1.vhd | 1 | 456 | entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
p1: process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when integer'low to 0 =>
x := -1;
when others =>
x := 5;
end case;
wait;
end process;
end architecture;
| gpl-3.0 | f93173d31a992ab6ded6b807e8a8edaa | 0.423246 | 4.301887 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd | 4 | 2,669 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc564.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:32 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:29 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:04 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00564ent IS
END c03s04b01x00p01n01i00564ent;
ARCHITECTURE c03s04b01x00p01n01i00564arch OF c03s04b01x00p01n01i00564ent IS
type severity_level_file is file of severity_level;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : severity_level_file open read_mode is "iofile.17";
variable v : severity_level;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= note) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00564"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00564 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00564arch;
| gpl-2.0 | 81d84acae64a27758287cf5b6bbcf220 | 0.557887 | 3.959941 | false | true | false | false |
nickg/nvc | test/regress/default2.vhd | 1 | 1,192 | entity default2 is
end entity;
architecture test of default2 is
procedure proc1 (x : integer) is
type real_vec is array (integer range <>) of real;
variable v : real_vec(1 to x);
begin
assert v(1) = real'left;
assert v(x) = real'left;
end procedure;
procedure proc2 (x : integer) is
type rec is record
x : real;
y : bit_vector(1 to x);
end record;
type rec_vec is array (natural range <>) of rec;
variable v : rec_vec(1 to x);
begin
assert v(1).x = real'left;
assert v(1).y = (1 to x => '0');
assert v(x).x = real'left;
assert v(x).y = (1 to x => '0');
end procedure;
procedure proc3 (x : integer) is
type int_ptr is access integer;
type rec is record
x : int_ptr;
end record;
type rec_vec is array (natural range <>) of rec;
variable v : rec_vec(1 to x);
begin
assert v(1).x = null;
assert v(x).x = null;
end procedure;
begin
main: process is
begin
proc1(5);
proc2(6);
proc3(2);
wait;
end process;
end architecture;
| gpl-3.0 | 2234330413d1b7e1174844f8bb0c15ba | 0.526007 | 3.601208 | false | false | false | false |
nickg/nvc | lib/std.08/env-body.vhd | 1 | 1,589 | -------------------------------------------------------------------------------
-- Copyright (C) 2014-2021 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer);
attribute foreign of stop_impl : procedure is "_std_env_stop";
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
| gpl-3.0 | d9363b30f0aedb1a77a2ab8a408b3470 | 0.609188 | 4.553009 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd | 4 | 1,842 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2264.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02264ent IS
END c07s02b06x00p11n01i02264ent;
ARCHITECTURE c07s02b06x00p11n01i02264arch OF c07s02b06x00p11n01i02264ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := (-A)/B ;
V2 := A/(-B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02264"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02264 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02264arch;
| gpl-2.0 | cc3041c8b3f4fe1513d7dac6b66eb7fb | 0.653637 | 3.535509 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1062/ent.vhdl | 1 | 365 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (gen1 : natural;
genb : boolean := false;
genv : std_logic_vector(7 downto 0) := "00001111";
gens : string);
port (d : out std_logic);
end ent;
architecture behav of ent is
begin
d <= '1' when gen1 = 5 and genb and (gens = "TRUE")
else '0';
end behav;
| gpl-2.0 | 20b77330571fcbe56a374aa692313437 | 0.589041 | 3.201754 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue522/shifter.vhdl | 1 | 3,855 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
entity Shifter is
port(shift_lsl :in std_logic;
shift_lsr :in std_logic;
shift_asr :in std_logic;
shift_ror :in std_logic;
shift_rrx :in std_logic;
cin :in std_logic;
shift_val :in std_logic_vector (4 downto 0);
din :in std_logic_vector(31 downto 0);
dout :out std_logic_vector(31 downto 0);
cout :out std_logic;
vdd :in bit;
vss :in bit);
end Shifter;
architecture ArchiShifter of Shifter is
signal res1, res2, res3, res4, res5, res6, res7 : std_logic_vector(31 downto 0):=x"00000000";
signal carryOut: std_logic;
begin
--LSL & LSR & ASR
res1 <= din(30 downto 0) & '0' when shift_val(0)='1' and shift_lsl='1' else
'0' & din(31 downto 1) when shift_val(0)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else
'1' & din(31 downto 1) when shift_val(0)='1' and (shift_asr='1' and din(31)='1' ) else din;
res2 <= res1(29 downto 0) & "00" when shift_val(1)='1' and shift_lsl='1' else
"00" & res1(31 downto 2) when shift_val(1)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else
"11" & res1(31 downto 2) when shift_val(1)='1' and (shift_asr='1'and din(31)='1' ) else res1;
res3 <= res2(27 downto 0) & x"0" when shift_val(2)='1' and shift_lsl='1' else
x"0" & res2(31 downto 4) when shift_val(2)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else
x"F" & res2(31 downto 4) when shift_val(2)='1' and (shift_asr='1'and din(31)='1' ) else res2;
res4 <= res3(23 downto 0) & x"00" when shift_val(3)='1' and shift_lsl='1' else
x"00" & res3(31 downto 8) when shift_val(3)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else
x"FF" & res3(31 downto 8) when shift_val(3)='1' and (shift_asr='1' and din(31)='1' ) else res3;
res5 <= res4(15 downto 0) & x"0000" when shift_val(4)='1' and shift_lsl='1' else
x"0000" & res4(31 downto 16) when shift_val(4)='1' and (shift_lsr='1' or (shift_asr='1' and din(31)='0')) else
x"FFFF" & res4(31 downto 16) when shift_val(4)='1' and (shift_asr='1' and din(31)='1' ) else res4;
carryOut <= din(32-to_integer(unsigned(shift_val))) when shift_val /="00000" and shift_lsl='1' else
din(to_integer(unsigned(shift_val))-1) when shift_val /="00000" and (shift_lsr='1' or shift_asr='1' or shift_ror='1') else
din(0) when shift_rrx='1' else cin;
--RRX
res6 <= cin & din(31 downto 1) when shift_rrx='1' else din;
--ROR
res7(31 downto (32-to_integer(unsigned(shift_val)))) <= din((to_integer(unsigned(shift_val))-1) downto 0) when shift_ror='1' and shift_val /="00000"
else din;
res7((31-to_integer(unsigned(shift_val))) downto 0) <= din(31 downto to_integer(unsigned(shift_val))) when shift_ror='1' and shift_val /="00000"
else din;
dout <= res5 when shift_lsl='1' or shift_asr='1' or shift_lsr='1' else
res6 when shift_rrx='1' else
res7 when shift_ror='1' else
din;
cout <= carryOut;
end ArchiShifter;
| gpl-2.0 | a56116a3e07611ea118bf03f6218bd8f | 0.486122 | 3.311856 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue317/OSVVM/AlertLogPkg.vhd | 1 | 129,426 | --
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Alert handling and log filtering (verbosity control)
-- Alert handling provides a method to count failures, errors, and warnings
-- To accumlate counts, a data structure is created in a shared variable
-- It is of type AlertLogStructPType which is defined in AlertLogBasePkg
-- Log filtering provides verbosity control for logs (display or do not display)
-- AlertLogPkg provides a simplified interface to the shared variable
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015: 2015.01 Initial revision
-- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail,
-- ReportNonZeroAlerts, ReadLogEnables
-- 05/2015 2015.06 Added IncAlertCount, AffirmIf
-- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs
-- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel)
-- Created LocalInitialize
--
-- Copyright (c) 2015 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package AlertLogPkg is
subtype AlertLogIDType is integer ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0.
constant ALERTLOG_DEFAULT_ID : AlertLogIDType := 1 ;
constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant OSVVM_ALERTLOG_ID : AlertLogIDType := 2 ;
constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- NUM_PREDEFINED_AL_IDS intended to be local, but depends on others
-- constant NUM_PREDEFINED_AL_IDS : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID - ALERTLOG_BASE_ID ; -- Not including base
constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right
constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ;
constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated
alias AlertLogOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ;
------------------------------------------------------------
-- Alert always goes to the transcript file
procedure Alert(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) ;
procedure Alert( Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
procedure IncAlertCount( -- A silent form of alert
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) ;
procedure IncAlertCount( Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Similar to assert, except condition is positive
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- Direct replacement for assert
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- overloading for common functionality
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Simple Diff for file comparisons
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType := PASSED ;
AlertLevel : AlertType := ERROR
) ;
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR) ;
------------------------------------------------------------
procedure SetAlertLogJustify ;
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ;
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ;
procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ;
procedure ClearAlerts ;
function "ABS" (L : AlertCountType) return AlertCountType ;
function "+" (L, R : AlertCountType) return AlertCountType ;
function "-" (L, R : AlertCountType) return AlertCountType ;
function "-" (R : AlertCountType) return AlertCountType ;
impure function SumAlertCount(AlertCount: AlertCountType) return integer ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount return integer ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ;
------------------------------------------------------------
-- log filtering for verbosity control, optionally has a separate file parameter
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ;
------------------------------------------------------------
-- Accessor Methods
procedure SetAlertLogName(Name : string ) ;
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ;
procedure DeallocateAlertLogStruct ;
procedure InitializeAlertLogStruct ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
------------------------------------------------------------
-- Accessor Methods
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCheckCount ;
impure function GetAffirmCheckCount return natural ;
--?? procedure IncAffirmPassCount ;
--?? impure function GetAffirmPassCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertStopCount(Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertStopCount(Level : AlertType) return integer ;
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
impure function GetAlertEnable(Level : AlertType) return boolean ;
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
impure function GetLogEnable(Level : LogType) return boolean ;
impure function IsLoggingEnabled(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; -- same as GetLogEnable
impure function IsLoggingEnabled(Level : LogType) return boolean ;
procedure ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ReportAlertLogOptions ;
impure function GetAlertLogFailOnWarning return AlertLogOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ;
impure function GetAlertLogReportHierarchy return AlertLogOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertName return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ;
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteLogName return AlertLogOptionsType ;
impure function GetAlertLogWriteLogTime return AlertLogOptionsType ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
-- File Reading Utilities
function IsLogEnableType (Name : String) return boolean ;
procedure ReadLogEnables (file AlertLogInitFile : text) ;
procedure ReadLogEnables (FileName : string) ;
-- String Helper Functions -- This should be in a more general string package
function PathTail (A : string) return string ;
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
use work.NamePkg.all ;
package body AlertLogPkg is
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
type LogNameType is array(LogType) of string(1 to 7) ;
constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER "
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
------------------------------------------------------------
procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ;
procedure SetJustify ;
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ;
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE ) ;
procedure ClearAlerts ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
------------------------------------------------------------
-- FILE IO Controls
-- procedure SetTranscriptEnable (A : boolean := TRUE) ;
-- impure function IsTranscriptEnabled return boolean ;
-- procedure MirrorTranscript (A : boolean := TRUE) ;
-- impure function IsTranscriptMirrored return boolean ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) ;
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : integer) ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure Initialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) ;
procedure Deallocate ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCheckCount ;
impure function GetAffirmCheckCount return natural ;
--?? procedure IncAffirmPassCount ;
--?? impure function GetAffirmPassCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
procedure ReportLogEnables ;
------------------------------------------------------------
-- Reporting Accessor
procedure SetAlertLogOptions (
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ReportAlertLogOptions ;
impure function GetAlertLogFailOnWarning return AlertLogOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ;
impure function GetAlertLogReportHierarchy return AlertLogOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertName return AlertLogOptionsType ;
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ;
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ;
impure function GetAlertLogWriteLogName return AlertLogOptionsType ;
impure function GetAlertLogWriteLogTime return AlertLogOptionsType ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
end protected AlertLogStructPType ;
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on
variable AffirmCheckCountVar : natural := 0 ;
--?? variable AffirmPassedCountVar : natural := 0 ;
------------------------------------------------------------
type AlertLogRecType is record
------------------------------------------------------------
Name : Line ;
ParentID : AlertLogIDType ;
AlertCount : AlertCountType ;
AlertStopCount : AlertCountType ;
AlertEnabled : AlertEnableType ;
LogEnabled : LogEnableType ;
end record AlertLogRecType ;
------------------------------------------------------------
-- Basis for AlertLog Data Structure
variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize
variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ;
--xx variable NumPredefinedAlIDsVar : AlertLogIDType := 0 ; -- defined by initialize
type AlertLogRecPtrType is access AlertLogRecType ;
type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ;
type AlertLogArrayPtrType is access AlertLogArrayType ;
variable AlertLogPtr : AlertLogArrayPtrType ;
------------------------------------------------------------
-- Report formatting settings, with defaults
variable FailOnWarningVar : boolean := TRUE ;
variable FailOnDisabledErrorsVar : boolean := TRUE ;
variable ReportHierarchyVar : boolean := TRUE ;
variable FoundReportHierVar : boolean := FALSE ;
variable FoundAlertHierVar : boolean := FALSE ;
variable WriteAlertLevelVar : boolean := TRUE ;
variable WriteAlertNameVar : boolean := TRUE ;
variable WriteAlertTimeVar : boolean := TRUE ;
variable WriteLogLevelVar : boolean := TRUE ;
variable WriteLogNameVar : boolean := TRUE ;
variable WriteLogTimeVar : boolean := TRUE ;
variable AlertPrefixVar : NamePType ;
variable LogPrefixVar : NamePType ;
variable ReportPrefixVar : NamePType ;
variable DoneNameVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
variable AlertLogJustifyAmountVar : integer := 0 ;
variable ReportJustifyAmountVar : integer := 0 ;
------------------------------------------------------------
-- PT Local
impure function LeftJustify(A : String; Amount : integer) return string is
------------------------------------------------------------
constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ;
begin
if A'length >= Amount then
return A ;
else
return A & Spaces(1 to Amount - A'length) ;
end if ;
end function LeftJustify ;
------------------------------------------------------------
-- PT Local
procedure IncrementAlertCount(
------------------------------------------------------------
constant AlertLogID : in AlertLogIDType ;
constant Level : in AlertType ;
variable StopDueToCount : inout boolean
) is
begin
-- Always Count at this level
AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + 1 ;
-- Only do remaining actions if enabled
if AlertLogPtr(AlertLogID).AlertEnabled(Level) then
-- Exceeded Stop Count at this level?
if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then
StopDueToCount := TRUE ;
end if ;
-- Propagate counts to parent(s) -- Ascend Hierarchy
if AlertLogID /= ALERTLOG_BASE_ID then
IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount) ;
end if ;
end if ;
end procedure IncrementAlertCount ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
variable buf : Line ;
constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
begin
if GlobalAlertEnabledVar then
-- Do not write or count when GlobalAlertEnabledVar is disabled
if AlertLogPtr(AlertLogID).AlertEnabled(Level) then
-- do not write when disabled
write(buf, AlertPrefix) ;
if WriteAlertLevelVar then
-- write(buf, " " & to_string(Level) ) ;
write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup
end if ;
--xx if (NumAlertLogIDsVar > NumPredefinedAlIDsVar) and WriteAlertNameVar then -- print hierarchy names even when silent
if FoundAlertHierVar and WriteAlertNameVar then
-- write(buf, " in " & justify(AlertLogPtr(AlertLogID).Name.all & ",", LEFT, AlertLogJustifyAmountVar) ) ;
write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ;
end if ;
write(buf, " " & Message) ;
if WriteAlertTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end if ;
-- Always Count
IncrementAlertCount(AlertLogID, Level, StopDueToCount) ;
if StopDueToCount then
write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
--xx if NumAlertLogIDsVar > NumPredefinedAlIDsVar then -- print hierarchy names even when silent
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportAll => TRUE) ;
std.env.stop(1) ;
end if ;
end if ;
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
level : AlertType := ERROR
) is
variable buf : Line ;
constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
begin
if GlobalAlertEnabledVar then
IncrementAlertCount(AlertLogID, Level, StopDueToCount) ;
if StopDueToCount then
write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
--xx if NumAlertLogIDsVar > NumPredefinedAlIDsVar then -- print hierarchy names even when silent
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportAll => TRUE) ;
std.env.stop ;
end if ;
end if ;
end procedure IncAlertCount ;
------------------------------------------------------------
-- PT Local
impure function CalcJustify (AlertLogID : AlertLogIDType ; CurrentLength : integer ; IndentAmount : integer) return integer_vector is
------------------------------------------------------------
variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented
begin
ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar
ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar
for i in AlertLogID+1 to NumAlertLogIDsVar loop
if AlertLogID = AlertLogPtr(i).ParentID then
LowerLevelValues := CalcJustify(i, AlertLogPtr(i).Name'length, IndentAmount + 2) ;
ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ;
ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ;
end if ;
end loop ;
return ResultValues ;
end function CalcJustify ;
------------------------------------------------------------
procedure SetJustify is
------------------------------------------------------------
variable ResultValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented
begin
ResultValues := CalcJustify(ALERTLOG_BASE_ID, 0, 0) ;
AlertLogJustifyAmountVar := ResultValues(1) ;
ReportJustifyAmountVar := ResultValues(2) ;
end procedure SetJustify ;
------------------------------------------------------------
-- PT Local
impure function GetEnabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
if AlertEnabled(FAILURE) then
Count(FAILURE) := AlertCount(FAILURE) ;
end if ;
if AlertEnabled(ERROR) then
Count(ERROR) := AlertCount(ERROR) ;
end if ;
if FailOnWarningVar and AlertEnabled(WARNING) then
Count(WARNING) := AlertCount(WARNING) ;
end if ;
return Count ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable AlertCount : AlertCountType ;
begin
return AlertLogPtr(AlertLogID).AlertCount ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable AlertCount : AlertCountType ;
begin
return GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
-- PT Local
impure function GetDisabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
if not AlertEnabled(FAILURE) then
Count(FAILURE) := AlertCount(FAILURE) ;
end if ;
if not AlertEnabled(ERROR) then
Count(ERROR) := AlertCount(ERROR) ;
end if ;
if FailOnWarningVar and not AlertEnabled(WARNING) then
Count(WARNING) := AlertCount(WARNING) ;
end if ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Count := Count + GetDisabledAlertCount(AlertLogPtr(i).AlertCount, AlertLogPtr(i).AlertEnabled) ;
end loop ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
Count := GetDisabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ;
for i in AlertLogID+1 to NumAlertLogIDsVar loop
if AlertLogID = AlertLogPtr(i).ParentID then
Count := Count + GetDisabledAlertCount(i) ;
end if ;
end loop ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
-- PT Local
procedure PrintTopAlerts (
------------------------------------------------------------
NumErrors : integer ;
AlertCount : AlertCountType ;
Name : string ;
NumDisabledErrors : integer
) is
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
begin
if NumErrors = 0 then
if NumDisabledErrors = 0 then
-- Passed
write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ;
if AffirmCheckCountVar > 0 then
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
else
-- Failed Due to Disabled Errors
write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ;
write(buf, " Failed Due to Disabled Error(s) = " & to_string(NumDisabledErrors)) ;
if AffirmCheckCountVar > 0 then
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
end if ;
else
-- Failed
write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ;
write(buf, " Total Error(s) = " & to_string(NumErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
if AffirmCheckCountVar > 0 then
--?? write(buf, " Affirmations Passed: " & to_string(AffirmPassedCountVar)) ;
--?? write(buf, " Checked: " & to_string(AffirmCheckCountVar)) ;
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ;
end if ;
Write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
end if ;
end procedure PrintTopAlerts ;
------------------------------------------------------------
-- PT Local
procedure PrintChild(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportAll : boolean
) is
variable buf : line ;
begin
for i in AlertLogID+1 to NumAlertLogIDsVar loop
if AlertLogID = AlertLogPtr(i).ParentID then
if ReportAll or SumAlertCount(AlertLogPtr(i).AlertCount) > 0 then
Write(buf, Prefix & " " & LeftJustify(AlertLogPtr(i).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
write(buf, " Failures: " & to_string(AlertLogPtr(i).AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(i).AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(i).AlertCount(WARNING) ) ) ;
WriteLine(buf) ;
end if ;
PrintChild(
AlertLogID => i,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2,
ReportAll => ReportAll
) ;
end if ;
end loop ;
end procedure PrintChild ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE) is
------------------------------------------------------------
variable NumErrors : integer ;
variable NumDisabledErrors : integer ;
constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
begin
if ReportJustifyAmountVar <= 0 then
SetJustify ;
end if ;
NumErrors := SumAlertCount( ExternalErrors + GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ) ;
if FailOnDisabledErrorsVar then
NumDisabledErrors := SumAlertCount( GetDisabledAlertCount(AlertLogID) ) ;
else
NumDisabledErrors := 0 ;
end if ;
if IsOsvvmStringSet(Name) then
PrintTopAlerts (
NumErrors => NumErrors,
AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors,
Name => Name,
NumDisabledErrors => NumDisabledErrors
) ;
else
PrintTopAlerts (
NumErrors => NumErrors,
AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors,
Name => AlertLogPtr(AlertLogID).Name.all,
NumDisabledErrors => NumDisabledErrors
) ;
end if ;
--Print Hierarchy when enabled and error or disabled error
if (FoundReportHierVar and ReportHierarchyVar) and (NumErrors /= 0 or NumDisabledErrors /=0) then
PrintChild(
AlertLogID => AlertLogID,
Prefix => ReportPrefix & " ",
IndentAmount => 2,
ReportAll => ReportAll
) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is
------------------------------------------------------------
begin
PrintTopAlerts (
NumErrors => SumAlertCount(AlertCount),
AlertCount => AlertCount,
Name => Name,
NumDisabledErrors => 0
) ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
AffirmCheckCountVar := 0 ;
--?? AffirmPassedCountVar := 0 ;
AlertLogPtr(ALERTLOG_BASE_ID).AlertCount := (0, 0, 0) ;
AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertCount := (0, 0, 0) ;
AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end loop ;
end procedure ClearAlerts ;
------------------------------------------------------------
-- PT Local
procedure LocalLog (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType
) is
variable buf : line ;
constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
begin
write(buf, LogPrefix) ;
if WriteLogLevelVar then
write(buf, " " & LOG_NAME(Level) ) ;
end if ;
--xx if (NumAlertLogIDsVar > NumPredefinedAlIDsVar) and WriteLogNameVar then -- print hierarchy names even when silent
if FoundAlertHierVar and WriteLogNameVar then
-- write(buf, " in " & justify(AlertLogPtr(AlertLogID).Name.all & ",", LEFT, AlertLogJustifyAmountVar) ) ;
write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ;
end if ;
write(buf, " " & Message) ;
if WriteLogTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end procedure LocalLog ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
begin
if Level = ALWAYS or Enable then
LocalLog(AlertLogID, Message, Level) ;
elsif AlertLogPtr(AlertLogID).LogEnabled(Level) then
LocalLog(AlertLogID, Message, Level) ;
end if ;
end procedure log ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ;
end procedure SetAlertLogName ;
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogPtr(AlertLogID).Name.all ;
end function GetAlertLogName ;
------------------------------------------------------------
-- PT Local
procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; Name : string ; ParentID : AlertLogIDType) is
------------------------------------------------------------
variable AlertEnabled : AlertEnableType ;
variable AlertStopCount : AlertCountType ;
variable LogEnabled : LogEnableType ;
begin
if AlertLogID = ALERTLOG_BASE_ID then
AlertEnabled := (TRUE, TRUE, TRUE) ;
LogEnabled := (others => FALSE) ;
AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
else
if ParentID < ALERTLOG_BASE_ID then
AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ;
LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ;
else
AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ;
LogEnabled := AlertLogPtr(ParentID).LogEnabled ;
end if ;
AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end if ;
AlertLogPtr(AlertLogID) := new AlertLogRecType ;
AlertLogPtr(AlertLogID).Name := new string'(NAME) ;
AlertLogPtr(AlertLogID).ParentID := ParentID ;
AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ;
AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ;
AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ;
-- AlertLogPtr(AlertLogID) := new AlertLogRecType'(
-- Name => new string'(NAME),
-- ParentID => ParentID,
-- AlertCount => (0, 0, 0),
-- AlertEnabled => AlertEnabled,
-- AlertStopCount => AlertStopCount,
-- LogEnabled => LogEnabled
-- ) ;
end procedure NewAlertLogRec ;
------------------------------------------------------------
-- PT Local
-- Construct initial data structure
procedure LocalInitialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
if NumAllocatedAlertLogIDsVar /= 0 then
Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ;
return ;
end if ;
-- Initialize Pointer
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
-- Create BASE AlertLogID (if it differs from DEFAULT
if ALERTLOG_BASE_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ;
end if ;
-- Create DEFAULT AlertLogID
NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := ALERT_DEFAULT_ID ;
-- Create OSVVM AlertLogID (if it differs from DEFAULT
if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then
NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
end procedure LocalInitialize ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize(NewNumAlertLogIDs : integer := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
LocalInitialize(NewNumAlertLogIDs) ;
end procedure Initialize ;
------------------------------------------------------------
-- PT Local
-- Constructs initial data structure using constant below
impure function LocalInitialize return boolean is
------------------------------------------------------------
begin
LocalInitialize(MIN_NUM_AL_IDS) ;
return TRUE ;
end function LocalInitialize ;
constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Deallocate(AlertLogPtr(i).Name) ;
Deallocate(AlertLogPtr(i)) ;
end loop ;
deallocate(AlertLogPtr) ;
-- Free up space used by protected types within AlertLogPkg
AlertPrefixVar.Deallocate ;
LogPrefixVar.Deallocate ;
ReportPrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
-- Restore variables to their initial state
NumAlertLogIDsVar := 0 ;
NumAllocatedAlertLogIDsVar := 0 ;
GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on
AffirmCheckCountVar := 0 ;
--?? AffirmPassedCountVar := 0 ;
FailOnWarningVar := TRUE ;
FailOnDisabledErrorsVar := TRUE ;
ReportHierarchyVar := TRUE ;
FoundReportHierVar := FALSE ;
FoundAlertHierVar := FALSE ;
WriteAlertLevelVar := TRUE ;
WriteAlertNameVar := TRUE ;
WriteAlertTimeVar := TRUE ;
WriteLogLevelVar := TRUE ;
WriteLogNameVar := TRUE ;
WriteLogTimeVar := TRUE ;
end procedure Deallocate ;
------------------------------------------------------------
-- PT Local.
procedure GrowAlertStructure (NewNumAlertLogIDs : integer) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NumAllocatedAlertLogIDsVar = 0 then
Initialize (NewNumAlertLogIDs) ; -- Construct initial structure
else
oldAlertLogPtr := AlertLogPtr ;
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ;
AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ;
deallocate(oldAlertLogPtr) ;
end if ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
end procedure GrowAlertStructure ;
------------------------------------------------------------
-- Sets a AlertLogPtr to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : integer) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NewNumAlertLogIDs) ;
end if;
end procedure SetNumAlertLogIDs ;
------------------------------------------------------------
-- PT Local
impure function GetNextAlertLogID return AlertLogIDType is
------------------------------------------------------------
variable NewNumAlertLogIDs : AlertLogIDType ;
begin
NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ;
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ;
end if ;
NumAlertLogIDsVar := NewNumAlertLogIDs ;
return NumAlertLogIDsVar ;
end function GetNextAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
if Name = AlertLogPtr(i).Name.all then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end function FindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable CurParentID : AlertLogIDType ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
CurParentID := AlertLogPtr(i).ParentID ;
if Name = AlertLogPtr(i).Name.all and
(CurParentID = ParentID or CurParentID = ALERTLOG_ID_NOT_ASSIGNED or ParentID = ALERTLOG_ID_NOT_ASSIGNED)
then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end function FindAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
begin
ResultID := FindAlertLogID(Name, ParentID) ;
if ResultID /= ALERTLOG_ID_NOT_FOUND then
-- found it, set ParentID
if AlertLogPtr(ResultID).ParentID = ALERTLOG_ID_NOT_ASSIGNED then
AlertLogPtr(ResultID).ParentID := ParentID ;
-- else -- do not update as ParentIDs are either same or input ParentID = ALERTLOG_ID_NOT_ASSIGNED
end if ;
else
ResultID := GetNextAlertLogID ;
NewAlertLogRec(ResultID, Name, ParentID) ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
end if ;
return ResultID ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogPtr(AlertLogID).ParentID ;
end function GetAlertLogParentID ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
GlobalAlertEnabledVar := A ;
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
begin
return GlobalAlertEnabledVar ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
procedure IncAffirmCheckCount is
------------------------------------------------------------
begin
if GlobalAlertEnabledVar then
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmCheckCount ;
------------------------------------------------------------
impure function GetAffirmCheckCount return natural is
------------------------------------------------------------
begin
return AffirmCheckCountVar ;
end function GetAffirmCheckCount ;
--?? ------------------------------------------------------------
--?? procedure IncAffirmPassCount is
--?? ------------------------------------------------------------
--?? begin
--?? if GlobalAlertEnabledVar then
--?? AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
--?? AffirmPassedCountVar := AffirmPassedCountVar + 1 ;
--?? end if ;
--?? end procedure IncAffirmPassCount ;
--??
--?? ------------------------------------------------------------
--?? impure function GetAffirmPassCount return natural is
--?? ------------------------------------------------------------
--?? begin
--?? return AffirmPassedCountVar ;
--?? end function GetAffirmPassCount ;
------------------------------------------------------------
-- PT LOCAL
procedure SetOneStopCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType ;
Count : integer
) is
begin
if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then
AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ;
else
AlertLogPtr(AlertLogID).AlertStopCount(Level) :=
AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ;
end if ;
end procedure SetOneStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
SetOneStopCount(AlertLogID, Level, Count) ;
if AlertLogID /= ALERTLOG_BASE_ID then
SetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ;
end if ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
begin
return AlertLogPtr(AlertLogID).AlertStopCount(Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertEnabled(Level) := Enable ;
end loop ;
end procedure SetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ;
if DescendHierarchy then
for i in AlertLogID+1 to NumAlertLogIDsVar loop
if AlertLogID = AlertLogPtr(i).ParentID then
SetAlertEnable(i, Level, Enable, DescendHierarchy) ;
end if ;
end loop ;
end if ;
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
begin
return AlertLogPtr(AlertLogID).AlertEnabled(Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).LogEnabled(Level) := Enable ;
end loop ;
end procedure SetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ;
if DescendHierarchy then
for i in AlertLogID+1 to NumAlertLogIDsVar loop
if AlertLogID = AlertLogPtr(i).ParentID then
SetLogEnable(i, Level, Enable, DescendHierarchy) ;
end if ;
end loop ;
end if ;
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
begin
if Level = ALWAYS then
return TRUE ;
else
return AlertLogPtr(AlertLogID).LogEnabled(Level) ;
end if ;
end function GetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure PrintLogLevels(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer
) is
variable buf : line ;
begin
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
for i in LogIndexType loop
if AlertLogPtr(AlertLogID).LogEnabled(i) then
-- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ;
write(buf, " " & to_string(i)) ;
end if ;
end loop ;
WriteLine(buf) ;
for i in AlertLogID+1 to NumAlertLogIDsVar loop
if AlertLogID = AlertLogPtr(i).ParentID then
PrintLogLevels(
AlertLogID => i,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2
) ;
end if ;
end loop ;
end procedure PrintLogLevels ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
begin
if ReportJustifyAmountVar <= 0 then
SetJustify ;
end if ;
PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ;
end procedure ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if FailOnWarning /= OPT_INIT_PARM_DETECT then
FailOnWarningVar := IsEnabled(FailOnWarning) ;
end if ;
if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then
FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ;
end if ;
if ReportHierarchy /= OPT_INIT_PARM_DETECT then
ReportHierarchyVar := IsEnabled(ReportHierarchy) ;
end if ;
if WriteAlertLevel /= OPT_INIT_PARM_DETECT then
WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ;
end if ;
if WriteAlertName /= OPT_INIT_PARM_DETECT then
WriteAlertNameVar := IsEnabled(WriteAlertName) ;
end if ;
if WriteAlertTime /= OPT_INIT_PARM_DETECT then
WriteAlertTimeVar := IsEnabled(WriteAlertTime) ;
end if ;
if WriteLogLevel /= OPT_INIT_PARM_DETECT then
WriteLogLevelVar := IsEnabled(WriteLogLevel) ;
end if ;
if WriteLogName /= OPT_INIT_PARM_DETECT then
WriteLogNameVar := IsEnabled(WriteLogName) ;
end if ;
if WriteLogTime /= OPT_INIT_PARM_DETECT then
WriteLogTimeVar := IsEnabled(WriteLogTime) ;
end if ;
if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
AlertPrefixVar.Set(AlertPrefix) ;
end if ;
if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
LogPrefixVar.Set(LogPrefix) ;
end if ;
if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
ReportPrefixVar.Set(ReportPrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
variable buf : line ;
begin
-- Boolean Values
swrite(buf, "ReportAlertLogOptions" & LF ) ;
swrite(buf, "---------------------" & LF ) ;
swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ;
swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ;
swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ;
swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user
swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user
swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ;
swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ;
swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ;
swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ;
swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ;
swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ;
-- String
swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ;
swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ;
swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ;
swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ;
swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ;
swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ;
writeline(buf) ;
end procedure ReportAlertLogOptions ;
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnWarningVar) ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(ReportHierarchyVar) ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return FoundReportHierVar ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return FoundAlertHierVar ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertLevelVar) ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertNameVar) ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertTimeVar) ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogLevelVar) ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogNameVar) ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogTimeVar) ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return ResolveOsvvmPassName(PassNameVar.GetOpt) ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return ResolveOsvvmFailName(FailNameVar.GetOpt) ;
end function GetAlertLogFailName ;
end protected body AlertLogStructPType ;
shared variable AlertLogStruct : AlertLogStructPType ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
procedure Alert(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) is
begin
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end procedure alert ;
------------------------------------------------------------
procedure Alert( Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) is
begin
AlertLogStruct.IncAlertCount(AlertLogID, Level) ;
end procedure IncAlertCount ;
------------------------------------------------------------
procedure IncAlertCount( Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ;
end procedure IncAlertCount ;
------------------------------------------------------------
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
end procedure AlertIf ;
------------------------------------------------------------
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
AlertIf( AlertLogID, condition, Message, Level) ;
end procedure AlertIf ;
------------------------------------------------------------
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ;
end if ;
end procedure AlertIf ;
------------------------------------------------------------
-- useful with exit conditions in a loop: exit when alert( not ReadValid, failure, "Read Failed") ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
return condition ;
end function AlertIf ;
------------------------------------------------------------
-- deprecated
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
return AlertIf( AlertLogID, condition, Message, Level) ;
end function AlertIf ;
------------------------------------------------------------
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
return condition ;
end function AlertIf ;
------------------------------------------------------------
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
end procedure AlertIfNot ;
------------------------------------------------------------
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
AlertIfNot( AlertLogID, condition, Message, Level) ;
end procedure AlertIfNot ;
------------------------------------------------------------
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
end procedure AlertIfNot ;
------------------------------------------------------------
-- useful with exit conditions in a loop: exit when alert( not ReadValid, failure, "Read Failed") ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
-- deprecated
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
return AlertIfNot( AlertLogID, condition, Message, Level) ;
end function AlertIfNot ;
------------------------------------------------------------
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
return not condition ;
end function AlertIfNot ;
-- With AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfEqual ;
-- Without AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfEqual ;
-- With AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfNotEqual ;
-- Without AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L ?/= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
file FileID1, FileID2 : text ;
variable status1, status2 : file_open_status ;
begin
file_open(status1, FileID1, Name1, READ_MODE) ;
file_open(status2, FileID2, Name2, READ_MODE) ;
if status1 = OPEN_OK and status2 = OPEN_OK then
AlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level) ;
else
if status1 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ;
end if ;
if status2 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ;
end if ;
end if;
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
AlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level) ;
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
-- Simple diff.
------------------------------------------------------------
variable Buf1, Buf2 : line ;
variable File1Done, File2Done : boolean ;
variable LineCount : integer := 0 ;
begin
ReadLoop : loop
File1Done := EndFile(File1) ;
File2Done := EndFile(File2) ;
exit ReadLoop when File1Done or File2Done ;
ReadLine(File1, Buf1) ;
ReadLine(File2, Buf2) ;
LineCount := LineCount + 1 ;
if Buf1.all /= Buf2.all then
AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ;
exit ReadLoop ;
end if ;
end loop ReadLoop ;
if File1Done /= File2Done then
if not File1Done then
AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ;
end if ;
if not File2Done then
AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ;
end if ;
end if;
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
AlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level) ;
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType := PASSED ;
AlertLevel : AlertType := ERROR
) is
begin
AlertLogStruct.IncAffirmCheckCount ; -- increment check count
if condition then
-- passed
AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log
-- AlertLogStruct.IncAffirmPassCount ; -- increment pass & check count
else
AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure
end if ;
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType := PASSED ; AlertLevel : AlertType := ERROR) is
------------------------------------------------------------
begin
AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ;
end procedure AffirmIf;
------------------------------------------------------------
procedure SetAlertLogJustify is
------------------------------------------------------------
begin
AlertLogStruct.SetJustify ;
end procedure SetAlertLogJustify ;
------------------------------------------------------------
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is
------------------------------------------------------------
begin
AlertLogStruct.ReportAlerts(Name, AlertCount) ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is
------------------------------------------------------------
begin
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, TRUE) ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is
------------------------------------------------------------
begin
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE) ;
end procedure ReportNonZeroAlerts ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
AlertLogStruct.ClearAlerts ;
end procedure ClearAlerts ;
------------------------------------------------------------
function "ABS" (L : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
Result(FAILURE) := ABS( L(FAILURE) ) ;
Result(ERROR) := ABS( L(ERROR) ) ;
Result(WARNING) := ABS( L(WARNING) );
return Result ;
end function "ABS" ;
------------------------------------------------------------
function "+" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
Result(FAILURE) := L(FAILURE) + R(FAILURE) ;
Result(ERROR) := L(ERROR) + R(ERROR) ;
Result(WARNING) := L(WARNING) + R(WARNING) ;
return Result ;
end function "+" ;
------------------------------------------------------------
function "-" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
Result(FAILURE) := L(FAILURE) - R(FAILURE) ;
Result(ERROR) := L(ERROR) - R(ERROR) ;
Result(WARNING) := L(WARNING) - R(WARNING) ;
return Result ;
end function "-" ;
------------------------------------------------------------
function "-" (R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
Result(FAILURE) := - R(FAILURE) ;
Result(ERROR) := - R(ERROR) ;
Result(WARNING) := - R(WARNING) ;
return Result ;
end function "-" ;
------------------------------------------------------------
impure function SumAlertCount(AlertCount: AlertCountType) return integer is
------------------------------------------------------------
begin
-- Using ABS ensures correct expected error handling.
return abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ;
end function SumAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertCount(AlertLogID) ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
begin
return SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
begin
return AlertLogStruct.GetEnabledAlertCount(AlertLogID) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
begin
return SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
begin
return AlertLogStruct.GetDisabledAlertCount ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return integer is
------------------------------------------------------------
begin
return SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
begin
return AlertLogStruct.GetDisabledAlertCount(AlertLogID) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is
------------------------------------------------------------
begin
return SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
begin
AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ;
end procedure log ;
------------------------------------------------------------
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ;
end procedure log ;
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
AlertLogStruct.SetAlertLogName(Name) ;
end procedure SetAlertLogName ;
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogName(AlertLogID) ;
end GetAlertLogName ;
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
AlertLogStruct.Deallocate ;
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
procedure InitializeAlertLogStruct is
------------------------------------------------------------
begin
AlertLogStruct.Initialize ;
end procedure InitializeAlertLogStruct ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogStruct.FindAlertLogID(Name) ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogStruct.FindAlertLogID(Name, ParentID) ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy ) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogParentID(AlertLogID) ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogStruct.SetGlobalAlertEnable(A) ;
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
-- Set using constant. Set before code runs.
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is
------------------------------------------------------------
begin
AlertLogStruct.SetGlobalAlertEnable(A) ;
return A ;
end function SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetGlobalAlertEnable ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
procedure IncAffirmCheckCount is
------------------------------------------------------------
begin
AlertLogStruct.IncAffirmCheckCount ;
end procedure IncAffirmCheckCount ;
------------------------------------------------------------
impure function GetAffirmCheckCount return natural is
------------------------------------------------------------
begin
return AlertLogStruct.GetAffirmCheckCount ;
end function GetAffirmCheckCount ;
--?? ------------------------------------------------------------
--?? procedure IncAffirmPassCount is
--?? ------------------------------------------------------------
--?? begin
--?? AlertLogStruct.IncAffirmPassCount ;
--?? end procedure IncAffirmPassCount ;
--??
--?? ------------------------------------------------------------
--?? impure function GetAffirmPassCount return natural is
--?? ------------------------------------------------------------
--?? begin
--?? return AlertLogStruct.GetAffirmPassCount ;
--?? end function GetAffirmPassCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(Level : AlertType) return integer is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
AlertLogStruct.SetAlertEnable(Level, Enable) ;
end procedure SetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertEnable(AlertLogID, Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(Level : AlertType) return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
AlertLogStruct.SetLogEnable(Level, Enable) ;
end procedure SetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetLogEnable(AlertLogID, Level) ;
end function GetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(Level : LogType) return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ;
end function GetLogEnable ;
------------------------------------------------------------
impure function IsLoggingEnabled(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetLogEnable(AlertLogID, Level) ;
end function IsLoggingEnabled ;
------------------------------------------------------------
impure function IsLoggingEnabled(Level : LogType) return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ;
end function IsLoggingEnabled ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
begin
AlertLogStruct.ReportLogEnables ;
end ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
AlertLogStruct.SetAlertLogOptions (
FailOnWarning => FailOnWarning ,
FailOnDisabledErrors => FailOnDisabledErrors,
ReportHierarchy => ReportHierarchy ,
WriteAlertLevel => WriteAlertLevel ,
WriteAlertName => WriteAlertName ,
WriteAlertTime => WriteAlertTime ,
WriteLogLevel => WriteLogLevel ,
WriteLogName => WriteLogName ,
WriteLogTime => WriteLogTime ,
AlertPrefix => AlertPrefix ,
LogPrefix => LogPrefix ,
ReportPrefix => ReportPrefix ,
DoneName => DoneName ,
PassName => PassName ,
FailName => FailName
);
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
begin
AlertLogStruct.ReportAlertLogOptions ;
end procedure ReportAlertLogOptions ;
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnWarning ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnDisabledErrors ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportHierarchy ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundReportHier ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundAlertHier ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertLevel ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertName ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertTime ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogLevel ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogName ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return AlertLogOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogTime ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogAlertPrefix ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogLogPrefix ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportPrefix ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDoneName ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPassName ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailName ;
end function GetAlertLogFailName ;
------------------------------------------------------------
function IsLogEnableType (Name : String) return boolean is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then return TRUE ;
elsif Name = "DEBUG" then return TRUE ;
elsif Name = "FINAL" then return TRUE ;
elsif Name = "INFO" then return TRUE ;
end if ;
return FALSE ;
end function IsLogEnableType ;
------------------------------------------------------------
procedure ReadLogEnables (file AlertLogInitFile : text) is
-- Preferred Read format
-- Line 1: instance1_name log_enable log_enable log_enable
-- Line 2: instance2_name log_enable log_enable log_enable
-- when reading multiple log_enables on a line, they must be separated by a space
--
--- Also supports alternate format from Lyle/....
-- Line 1: instance1_name
-- Line 2: log enable
-- Line 3: instance2_name
-- Line 4: log enable
--
------------------------------------------------------------
type ReadStateType is (GET_ID, GET_ENABLE) ;
variable ReadState : ReadStateType := GET_ID ;
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable Name : string(1 to 80) ;
variable NameLen : integer ;
variable AlertLogID : AlertLogIDType ;
variable ReadAnEnable : boolean ;
variable LogLevel : LogType ;
begin
ReadState := GET_ID ;
ReadLineLoop : while not EndFile(AlertLogInitFile) loop
ReadLine(AlertLogInitFile, buf) ;
if ReadAnEnable then
-- Read one or more enable values, next line read AlertLog name
-- Note that any newline with ReadAnEnable TRUE will result in
-- searching for another AlertLogID name - this includes multi-line comments.
ReadState := GET_ID ;
end if ;
ReadNameLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLineLoop when Empty ;
case ReadState is
when GET_ID =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ;
ReadState := GET_ENABLE ;
ReadAnEnable := FALSE ;
when GET_ENABLE =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
ReadAnEnable := TRUE ;
if not IsLogEnableType(Name(1 to NameLen)) then
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ;
exit ReadNameLoop ;
end if ;
LogLevel := LogType'value(Name(1 to NameLen)) ;
SetLogEnable(AlertLogID, LogLevel, TRUE) ;
end case ;
end loop ReadNameLoop ;
end loop ReadLineLoop ;
end procedure ReadLogEnables ;
------------------------------------------------------------
procedure ReadLogEnables (FileName : string) is
------------------------------------------------------------
file AlertLogInitFile : text open READ_MODE is FileName ;
begin
ReadLogEnables(AlertLogInitFile) ;
end procedure ReadLogEnables ;
------------------------------------------------------------
function PathTail (A : string) return string is
------------------------------------------------------------
alias aA : string(1 to A'length) is A ;
begin
for i in aA'length - 1 downto 1 loop
if aA(i) = ':' then
return aA(i+1 to aA'length-1) ;
end if ;
end loop ;
return aA ;
end function PathTail ;
end package body AlertLogPkg ; | gpl-2.0 | 8b875d2702df406b38ea24e182637b79 | 0.518574 | 5.97783 | false | false | false | false |
nickg/nvc | test/simp/shift2.vhd | 2 | 4,150 | entity shift2 is
end entity;
architecture test of shift2 is
begin
assert bit_vector'("11100") ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'("11100") ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'("11100") ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'("11100") ror -5 = "11100"
report "ror -5 is broken" severity error;
assert bit_vector'("11100") ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'("11100") ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'("11100") ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'("11100") ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'("11100") ror 0 = "11100"
report "ror 0 is broken" severity error;
assert bit_vector'("11100") ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'("11100") ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'("11100") ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'("11100") ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'("11100" ror 5) = "11100"
report "ror 5 is broken" severity error;
assert bit_vector'("11100") ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'("11100") ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'("11100") ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'("11100") rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'("11100") rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'("11100") rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'("11100" rol -5) = "11100"
report "rol -5 is broken" severity error;
assert bit_vector'("11100") rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'("11100") rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'("11100") rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'("11100") rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'("11100") rol 0 = "11100"
report "rol 0 is broken" severity error;
assert bit_vector'("11100") rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'("11100") rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'("11100") rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'("11100") rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'("11100") rol 5 = "11100"
report "rol 5 is broken" severity error;
assert bit_vector'("11100") rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'("11100") rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'("11100") rol 8 = "00111"
report "rol 8 is broken" severity error;
-- Misc
assert ("1011" sll 1) = "0110";
assert ("1011" srl 1) = "0101";
assert ("1011" sla 1) = "0111";
assert ("1011" sra 1) = "1101";
assert ("1011" srl -1) = "0110";
assert ("1011" sll -1) = "0101";
assert ("1011" sra -1) = "0111";
assert ("1011" sla -1) = "1101";
end architecture;
| gpl-3.0 | deb39504316b751843494c4366a122b0 | 0.544578 | 3.821363 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue531/sample_slice_ports.vhd | 1 | 1,003 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sliced_ex is
port (
clk : in std_logic;
reset : in std_logic;
arg_a : in std_logic_vector(3 downto 0);
arg_b : in std_logic_vector(3 downto 0)
);
end sliced_ex;
architecture rtl of sliced_ex is
signal aa, ab : std_logic_vector(3 downto 0);
begin
aa <= arg_a(aa'range);
ab <= arg_b(ab'range);
monitor : process(clk)
begin
if rising_edge(clk) then
report "arg_a: " & integer'image(to_integer(unsigned(arg_a)))
& ", arg_b: " & integer'image(to_integer(unsigned(arg_b)));
end if;
end process;
sub_module : entity work.submodule
port map (
clk => clk,
-- This version works
--arg( 7 downto 0) => aa,
--arg(15 downto 8) => ab,
-- This one works
--arg => arg_a,
-- This one fails
arg(3 downto 0) => arg_a(3 downto 0),
arg(7 downto 4) => arg_b(3 downto 0),
res => OPEN
);
end rtl;
| gpl-2.0 | 2c8f993cef4a0b1b196dbf752be3a35c | 0.566301 | 3.086154 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0104/alt.vhdl | 1 | 1,679 | library ieee;
use ieee.std_logic_1164.all;
entity delay is
port (
clk : in std_logic;
reset: in std_logic;
start: in std_logic;
done: out std_logic
);
end entity delay;
architecture fast of delay is -- The reader is unenlightened as to fast/slow
begin
end architecture fast;
architecture slow of delay is
begin
end architecture slow;
library ieee;
use ieee.std_logic_1164.all;
entity dut is
generic (
SPEED : string := "fast"
);
port(
clk : in std_logic;
reset: in std_logic;
start: in std_logic;
done: out std_logic);
end entity dut;
architecture dutarch of dut is
-- component delay is -- component declaration not needed or used here.
-- port (
-- clk : in std_logic;
-- reset: in std_logic;
-- start: in std_logic;
-- done: out std_logic
-- );
-- end component delay;
begin
d1g:
if SPEED = "fast" generate
d1: -- The alternative labels, if any, within an if generate statement or a
-- case generate statement shall all be distinct. 11.8 Generate statements
entity work.delay(fast)
port map (
clk => clk,
reset => reset,
start => start,
done => done
);
else generate
d1: -- This isn't a distinct label in the else alternative
entity work.delay(slow)
port map (
clk => clk,
reset => reset,
start => start,
done => done
);
end generate;
end architecture dutarch;
| gpl-2.0 | de3c9a7bc438515426166482e324da3d | 0.541394 | 4.135468 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_router_async_s1d2_x4_b/src/fifo_async_fwft_64x513_v8_2/fifo_async_fwft_64x513_v8_2.vhd | 1 | 10,975 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_async_fwft_64x513_v8_2.vhd when simulating
-- the core, fifo_async_fwft_64x513_v8_2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_async_fwft_64x513_v8_2 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END fifo_async_fwft_64x513_v8_2;
ARCHITECTURE fifo_async_fwft_64x513_v8_2_a OF fifo_async_fwft_64x513_v8_2 IS
-- synthesis translate_off
COMPONENT wrapped_fifo_async_fwft_64x513_v8_2
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo_async_fwft_64x513_v8_2 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 64,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "virtex6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 1,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 1,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_async_fwft_64x513_v8_2
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count
);
-- synthesis translate_on
END fifo_async_fwft_64x513_v8_2_a;
| mit | a9708b5e9c85995389e0c5283a89387e | 0.528656 | 3.304727 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd | 3 | 21,799 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_4;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_9.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| gpl-3.0 | d20a7a2e6dfe2974baff9e21c6f6ef65 | 0.438919 | 4.351098 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd | 4 | 1,929 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
type phase_type is (wash, other_phase);
signal phase : phase_type := other_phase;
type cycle_type is (delicate_cycle, other_cycle);
signal cycle_select : cycle_type := delicate_cycle;
type speed_type is (slow, fast);
signal agitator_speed : speed_type := slow;
signal agitator_on : boolean := false;
begin
process_1_e : process (phase, cycle_select) is
begin
-- code from book:
if phase = wash then
if cycle_select = delicate_cycle then
agitator_speed <= slow;
else
agitator_speed <= fast;
end if;
agitator_on <= true;
end if;
-- end of code from book
end process process_1_e;
stimulus : process is
begin
cycle_select <= other_cycle; wait for 100 ns;
phase <= wash; wait for 100 ns;
cycle_select <= delicate_cycle; wait for 100 ns;
cycle_select <= other_cycle; wait for 100 ns;
phase <= other_phase; wait for 100 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | dadaea3f3f641c17eb2fdecf0f26e638 | 0.665111 | 3.97732 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff02/dff08a.vhdl | 1 | 521 | library ieee;
use ieee.std_logic_1164.all;
entity dff08a is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
en : std_logic;
rst : std_logic);
end dff08a;
architecture behav of dff08a is
signal p : std_logic_vector(7 downto 0);
begin
process (clk, rst) is
begin
if en = '0' then
null;
elsif rst = '1' then
p <= x"00";
elsif rising_edge (clk) then
p <= d;
end if;
end process;
q <= p;
end behav;
| gpl-2.0 | 514673e603ace1408c6ad7b9427e1c72 | 0.577735 | 3.046784 | false | false | false | false |
tgingold/ghdl | testsuite/synth/oper01/cmp02.vhdl | 1 | 643 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cmp02 is
port (l : std_logic_vector(3 downto 0);
r : natural;
eq : out std_logic;
ne : out std_logic;
lt : out std_logic;
le : out std_logic;
ge : out std_logic;
gt : out std_logic);
end cmp02;
architecture behav of cmp02 is
begin
eq <= '1' when unsigned(l) = r else '0';
ne <= '1' when unsigned(l) /= r else '0';
lt <= '1' when unsigned(l) < r else '0';
le <= '1' when unsigned(l) <= r else '0';
gt <= '1' when unsigned(l) > r else '0';
ge <= '1' when unsigned(l) >= r else '0';
end behav;
| gpl-2.0 | bb819b9a2d47d5554e399b24e2766684 | 0.556765 | 2.857778 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd | 4 | 7,173 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2258.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02258ent IS
END c07s02b06x00p05n01i02258ent;
ARCHITECTURE c07s02b06x00p05n01i02258arch OF c07s02b06x00p05n01i02258ent IS
BEGIN
TESTING: PROCESS
constant mul11 : integer := (1 - 4) * (1 - 4);
constant mul12 : integer := (1 - 4) * (2 - 4);
constant mul13 : integer := (1 - 4) * (3 - 4);
constant mul14 : integer := (1 - 4) * (4 - 4);
constant mul15 : integer := (1 - 4) * (5 - 4);
constant mul16 : integer := (1 - 4) * (6 - 4);
constant mul17 : integer := (1 - 4) * (7 - 4);
constant mul18 : integer := (1 - 4) * (8 - 4);
constant mul19 : integer := (1 - 4) * (9 - 4);
constant mul41 : integer := (4 - 4) * (1 - 4);
constant mul42 : integer := (4 - 4) * (2 - 4);
constant mul43 : integer := (4 - 4) * (3 - 4);
constant mul44 : integer := (4 - 4) * (4 - 4);
constant mul45 : integer := (4 - 4) * (5 - 4);
constant mul46 : integer := (4 - 4) * (6 - 4);
constant mul47 : integer := (4 - 4) * (7 - 4);
constant mul48 : integer := (4 - 4) * (8 - 4);
constant mul49 : integer := (4 - 4) * (9 - 4);
constant mul61 : integer := (6 - 4) * (1 - 4);
constant mul62 : integer := (6 - 4) * (2 - 4);
constant mul63 : integer := (6 - 4) * (3 - 4);
constant mul64 : integer := (6 - 4) * (4 - 4);
constant mul65 : integer := (6 - 4) * (5 - 4);
constant mul66 : integer := (6 - 4) * (6 - 4);
constant mul67 : integer := (6 - 4) * (7 - 4);
constant mul68 : integer := (6 - 4) * (8 - 4);
constant mul69 : integer := (6 - 4) * (9 - 4);
variable four : integer := 4;
BEGIN
assert mul11 = (1 - four) * (1 - four);
assert mul12 = (1 - four) * (2 - four);
assert mul13 = (1 - four) * (3 - four);
assert mul14 = (1 - four) * (4 - four);
assert mul15 = (1 - four) * (5 - four);
assert mul16 = (1 - four) * (6 - four);
assert mul17 = (1 - four) * (7 - four);
assert mul18 = (1 - four) * (8 - four);
assert mul19 = (1 - four) * (9 - four);
assert mul41 = (4 - four) * (1 - four);
assert mul42 = (4 - four) * (2 - four);
assert mul43 = (4 - four) * (3 - four);
assert mul44 = (4 - four) * (4 - four);
assert mul45 = (4 - four) * (5 - four);
assert mul46 = (4 - four) * (6 - four);
assert mul47 = (4 - four) * (7 - four);
assert mul48 = (4 - four) * (8 - four);
assert mul49 = (4 - four) * (9 - four);
assert mul61 = (6 - four) * (1 - four);
assert mul62 = (6 - four) * (2 - four);
assert mul63 = (6 - four) * (3 - four);
assert mul64 = (6 - four) * (4 - four);
assert mul65 = (6 - four) * (5 - four);
assert mul66 = (6 - four) * (6 - four);
assert mul67 = (6 - four) * (7 - four);
assert mul68 = (6 - four) * (8 - four);
assert mul69 = (6 - four) * (9 - four);
assert NOT(( mul11 = (1 - four) * (1 - four)) and
( mul12 = (1 - four) * (2 - four)) and
( mul13 = (1 - four) * (3 - four)) and
( mul14 = (1 - four) * (4 - four)) and
( mul15 = (1 - four) * (5 - four)) and
( mul16 = (1 - four) * (6 - four)) and
( mul17 = (1 - four) * (7 - four)) and
( mul18 = (1 - four) * (8 - four)) and
( mul19 = (1 - four) * (9 - four)) and
( mul41 = (4 - four) * (1 - four)) and
( mul42 = (4 - four) * (2 - four)) and
( mul43 = (4 - four) * (3 - four)) and
( mul44 = (4 - four) * (4 - four)) and
( mul45 = (4 - four) * (5 - four)) and
( mul46 = (4 - four) * (6 - four)) and
( mul47 = (4 - four) * (7 - four)) and
( mul48 = (4 - four) * (8 - four)) and
( mul49 = (4 - four) * (9 - four)) and
( mul61 = (6 - four) * (1 - four)) and
( mul62 = (6 - four) * (2 - four)) and
( mul63 = (6 - four) * (3 - four)) and
( mul64 = (6 - four) * (4 - four)) and
( mul65 = (6 - four) * (5 - four)) and
( mul66 = (6 - four) * (6 - four)) and
( mul67 = (6 - four) * (7 - four)) and
( mul68 = (6 - four) * (8 - four)) and
( mul69 = (6 - four) * (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02258"
severity NOTE;
assert (( mul11 = (1 - four) * (1 - four)) and
( mul12 = (1 - four) * (2 - four)) and
( mul13 = (1 - four) * (3 - four)) and
( mul14 = (1 - four) * (4 - four)) and
( mul15 = (1 - four) * (5 - four)) and
( mul16 = (1 - four) * (6 - four)) and
( mul17 = (1 - four) * (7 - four)) and
( mul18 = (1 - four) * (8 - four)) and
( mul19 = (1 - four) * (9 - four)) and
( mul41 = (4 - four) * (1 - four)) and
( mul42 = (4 - four) * (2 - four)) and
( mul43 = (4 - four) * (3 - four)) and
( mul44 = (4 - four) * (4 - four)) and
( mul45 = (4 - four) * (5 - four)) and
( mul46 = (4 - four) * (6 - four)) and
( mul47 = (4 - four) * (7 - four)) and
( mul48 = (4 - four) * (8 - four)) and
( mul49 = (4 - four) * (9 - four)) and
( mul61 = (6 - four) * (1 - four)) and
( mul62 = (6 - four) * (2 - four)) and
( mul63 = (6 - four) * (3 - four)) and
( mul64 = (6 - four) * (4 - four)) and
( mul65 = (6 - four) * (5 - four)) and
( mul66 = (6 - four) * (6 - four)) and
( mul67 = (6 - four) * (7 - four)) and
( mul68 = (6 - four) * (8 - four)) and
( mul69 = (6 - four) * (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02258 - Constant integer type multiplication test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02258arch;
| gpl-2.0 | f708eca090f743bb34c1513dc62ca84a | 0.463683 | 3.065385 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1307/hdmi_design.vhd | 1 | 8,309 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hdmi_design is
Port (
clk100 : in STD_LOGIC;
-- Control signals
led : out std_logic_vector(7 downto 0) :=(others => '0');
sw : in std_logic_vector(7 downto 0) :=(others => '0');
debug_pmod : out std_logic_vector(7 downto 0) :=(others => '0');
--HDMI input signals
hdmi_rx_cec : inout std_logic;
hdmi_rx_hpa : out std_logic;
hdmi_rx_scl : in std_logic;
hdmi_rx_sda : inout std_logic;
hdmi_rx_txen : out std_logic;
hdmi_rx_clk_n : in std_logic;
hdmi_rx_clk_p : in std_logic;
hdmi_rx_n : in std_logic_vector(2 downto 0);
hdmi_rx_p : in std_logic_vector(2 downto 0);
--- HDMI out
hdmi_tx_cec : inout std_logic;
hdmi_tx_clk_n : out std_logic;
hdmi_tx_clk_p : out std_logic;
hdmi_tx_hpd : in std_logic;
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0);
-- For dumping symbols
rs232_tx : out std_logic
);
end hdmi_design;
architecture Behavioral of hdmi_design is
component hdmi_io is
Port (
clk100 : in STD_LOGIC;
-------------------------------
-- Control signals
-------------------------------
clock_locked : out std_logic;
data_synced : out std_logic;
debug : out std_logic_vector(7 downto 0);
-------------------------------
--HDMI input signals
-------------------------------
hdmi_rx_cec : inout std_logic;
hdmi_rx_hpa : out std_logic;
hdmi_rx_scl : in std_logic;
hdmi_rx_sda : inout std_logic;
hdmi_rx_txen : out std_logic;
hdmi_rx_clk_n : in std_logic;
hdmi_rx_clk_p : in std_logic;
hdmi_rx_n : in std_logic_vector(2 downto 0);
hdmi_rx_p : in std_logic_vector(2 downto 0);
-------------
-- HDMI out
-------------
hdmi_tx_cec : inout std_logic;
hdmi_tx_clk_n : out std_logic;
hdmi_tx_clk_p : out std_logic;
hdmi_tx_hpd : in std_logic;
hdmi_tx_rscl : inout std_logic;
hdmi_tx_rsda : inout std_logic;
hdmi_tx_p : out std_logic_vector(2 downto 0);
hdmi_tx_n : out std_logic_vector(2 downto 0);
pixel_clk : out std_logic;
-------------------------------
-- VGA data recovered from HDMI
-------------------------------
in_hdmi_detected : out std_logic;
in_blank : out std_logic;
in_hsync : out std_logic;
in_vsync : out std_logic;
in_red : out std_logic_vector(7 downto 0);
in_green : out std_logic_vector(7 downto 0);
in_blue : out std_logic_vector(7 downto 0);
is_interlaced : out std_logic;
is_second_field : out std_logic;
-------------------------------------
-- Audio Levels
-------------------------------------
audio_channel : out std_logic_vector(2 downto 0);
audio_de : out std_logic;
audio_sample : out std_logic_vector(23 downto 0);
-----------------------------------
-- VGA data to be converted to HDMI
-----------------------------------
out_blank : in std_logic;
out_hsync : in std_logic;
out_vsync : in std_logic;
out_red : in std_logic_vector(7 downto 0);
out_green : in std_logic_vector(7 downto 0);
out_blue : in std_logic_vector(7 downto 0);
-----------------------------------
-- For symbol dump or retransmit
-----------------------------------
symbol_sync : out std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : out std_logic_vector(9 downto 0);
symbol_ch1 : out std_logic_vector(9 downto 0);
symbol_ch2 : out std_logic_vector(9 downto 0)
);
end component;
signal symbol_sync : std_logic;
signal symbol_ch0 : std_logic_vector(9 downto 0);
signal symbol_ch1 : std_logic_vector(9 downto 0);
signal symbol_ch2 : std_logic_vector(9 downto 0);
component pixel_processing is
Port ( clk : in STD_LOGIC;
switches : in std_logic_vector(7 downto 0);
------------------
-- Incoming pixels
------------------
in_blank : in std_logic;
in_hsync : in std_logic;
in_vsync : in std_logic;
in_red : in std_logic_vector(7 downto 0);
in_green : in std_logic_vector(7 downto 0);
in_blue : in std_logic_vector(7 downto 0);
is_interlaced : in std_logic;
is_second_field : in std_logic;
-------------------
-- Processed pixels
-------------------
out_blank : out std_logic;
out_hsync : out std_logic;
out_vsync : out std_logic;
out_red : out std_logic_vector(7 downto 0);
out_green : out std_logic_vector(7 downto 0);
out_blue : out std_logic_vector(7 downto 0);
-------------------------------------
-- Audio samples for metering
-------------------------------------
audio_channel : in std_logic_vector(2 downto 0);
audio_de : in std_logic;
audio_sample : in std_logic_vector(23 downto 0)
);
end component;
component symbol_dump is
port (
clk : in std_logic;
clk100 : in std_logic;
symbol_sync : in std_logic; -- indicates a fixed reference point in the frame.
symbol_ch0 : in std_logic_vector(9 downto 0);
symbol_ch1 : in std_logic_vector(9 downto 0);
symbol_ch2 : in std_logic_vector(9 downto 0);
rs232_tx : out std_logic);
end component;
signal pixel_clk : std_logic;
signal in_blank : std_logic;
signal in_hsync : std_logic;
signal in_vsync : std_logic;
signal in_red : std_logic_vector(7 downto 0);
signal in_green : std_logic_vector(7 downto 0);
signal in_blue : std_logic_vector(7 downto 0);
signal is_interlaced : std_logic;
signal is_second_field : std_logic;
signal out_blank : std_logic;
signal out_hsync : std_logic;
signal out_vsync : std_logic;
signal out_red : std_logic_vector(7 downto 0);
signal out_green : std_logic_vector(7 downto 0);
signal out_blue : std_logic_vector(7 downto 0);
signal audio_channel : std_logic_vector(2 downto 0);
signal audio_de : std_logic;
signal audio_sample : std_logic_vector(23 downto 0);
signal debug : std_logic_vector(7 downto 0);
begin
i_processing: pixel_processing Port map (
clk => pixel_clk,
switches => sw,
------------------
-- Incoming pixels
------------------
in_blank => in_blank,
in_hsync => in_hsync,
in_vsync => in_vsync,
in_red => in_red,
in_green => in_green,
in_blue => in_blue,
is_interlaced => is_interlaced,
is_second_field => is_second_field,
audio_channel => audio_channel,
audio_de => audio_de,
audio_sample => audio_sample,
-------------------
-- Processed pixels
-------------------
out_blank => out_blank,
out_hsync => out_hsync,
out_vsync => out_vsync,
out_red => out_red,
out_green => out_green,
out_blue => out_blue
);
end Behavioral;
| gpl-2.0 | 94a7ad816e8212fc7ea3bc18df0264ef | 0.463473 | 3.949144 | false | false | false | false |
nickg/nvc | test/regress/assign6.vhd | 1 | 577 | entity assign6 is
end entity;
architecture test of assign6 is
signal x : bit := '1';
begin
main: process is
type int_ptr is access integer;
type int_ptr_vec is array (natural range <>) of int_ptr;
variable a, b : bit;
variable p, q : int_ptr;
begin
wait for 1 ns;
(a, b) := bit_vector'(x, not x);
assert a = '1';
assert b = '0';
p := new integer'(5);
(p, q) := int_ptr_vec'(q, p);
assert q.all = 5;
assert p = null;
wait;
end process;
end architecture;
| gpl-3.0 | d9b43a6fd5d0631175c178a50bfa6c96 | 0.514731 | 3.45509 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug048/leftof1.vhdl | 2 | 540 | entity leftofrightof is
end entity;
architecture subclass_constant of leftofrightof is
begin
process
constant i: integer := 1;
begin
report "constant i = " & integer'image(i);
report "integer'leftof(i) = " & integer'image(integer'leftof(i));
wait;
end process;
process
constant j: integer := 1;
begin
report "constant j = " & integer'image(j);
report "integer'rightof(j) = " & integer'image(integer'rightof(j));
wait;
end process;
end architecture;
| gpl-2.0 | 2ce4855886c221f101f40d76f8cebdb1 | 0.612963 | 3.829787 | false | false | false | false |
tgingold/ghdl | testsuite/synth/fsm01/tb_fsm_4s.vhdl | 1 | 891 | entity tb_fsm_4s is
end tb_fsm_4s;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_fsm_4s is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic;
signal done : std_logic;
begin
dut: entity work.fsm_4s
port map (
done => done,
d => din,
clk => clk,
rst => rst);
process
constant dat : std_logic_vector := b"1001_1001_1100";
constant res : std_logic_vector := b"0001_0001_0000";
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
din <= '0';
pulse;
assert done = '0' severity failure;
-- Test the whole sequence.
rst <= '0';
for i in dat'range loop
din <= dat (i);
pulse;
assert done = res(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 97b06f0700997a83f970a14609d07e31 | 0.566779 | 3.275735 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr03/tb_mdim01.vhdl | 1 | 644 | entity tb_mdim01 is
end tb_mdim01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_mdim01 is
signal a : std_logic_vector (3 downto 0);
signal b : std_logic_vector (3 downto 0);
signal c : std_logic_vector (3 downto 0);
begin
dut: entity work.mdim01
port map (a, b, c);
process
constant av : std_logic_vector := b"1101";
constant bv : std_logic_vector := b"0111";
constant cv : std_logic_vector := b"0011";
constant zv : std_logic_vector := b"0111";
begin
a <= "1111";
b <= "0000";
wait for 1 ns;
assert c = "1100" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1d88a5ced44ec2a6691de421e88264bf | 0.630435 | 3.126214 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/src/io/uart/uart.pkg.vhdl | 3 | 4,739 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: Component declarations for PoC.io.uart
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
package uart is
type T_IO_UART_FLOWCONTROL_KIND is (
UART_FLOWCONTROL_NONE,
UART_FLOWCONTROL_XON_XOFF,
UART_FLOWCONTROL_RTS_CTS,
UART_FLOWCONTROL_RTR_CTS
);
constant C_IO_UART_TYPICAL_BAUDRATES : T_BAUDVEC := (
0 => 300 Bd, 1 => 600 Bd, 2 => 1200 Bd, 3 => 1800 Bd, 4 => 2400 Bd,
5 => 4000 Bd, 6 => 4800 Bd, 7 => 7200 Bd, 8 => 9600 Bd, 9 => 14400 Bd,
10 => 16000 Bd, 11 => 19200 Bd, 12 => 28800 Bd, 13 => 38400 BD, 14 => 51200 Bd,
15 => 56000 Bd, 16 => 57600 Bd, 17 => 64000 Bd, 18 => 76800 Bd, 19 => 115200 Bd,
20 => 128000 Bd, 21 => 153600 Bd, 22 => 230400 Bd, 23 => 250000 Bd, 24 => 256000 BD,
25 => 460800 Bd, 26 => 500000 Bd, 27 => 576000 Bd, 28 => 921600 Bd
);
function io_UART_IsTypicalBaudRate(br : BAUD) return BOOLEAN;
-- Bit clock generator
component uart_bclk is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
BAUDRATE : BAUD := 115200 Bd
);
port (
clk : in std_logic;
rst : in std_logic;
bclk_r : out std_logic;
bclk_x8_r : out std_logic
);
end component;
-- Transmitter
component uart_tx is
port (
clk : in std_logic;
rst : in std_logic;
bclk_r : in std_logic;
stb : in std_logic;
din : in std_logic_vector(7 downto 0);
rdy : out std_logic;
txd : out std_logic
);
end component;
-- Receiver
component uart_rx is
generic (
OUT_REGS : boolean
);
port (
clk : in std_logic;
rst : in std_logic;
bclk_x8_r : in std_logic;
rxd : in std_logic;
dos : out std_logic;
dout : out std_logic_vector(7 downto 0)
);
end component;
-- Wrappers
-- ===========================================================================
-- UART with FIFOs and optional flow control
component uart_fifo is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
BAUDRATE : BAUD := 115200 Bd;
FLOWCONTROL : T_IO_UART_FLOWCONTROL_KIND := UART_FLOWCONTROL_NONE;
TX_MIN_DEPTH : POSITIVE := 16;
TX_ESTATE_BITS : NATURAL := 1;
RX_MIN_DEPTH : POSITIVE := 16;
RX_FSTATE_BITS : NATURAL := 1;
RX_OUT_REGS : BOOLEAN := FALSE;
SWFC_XON_CHAR : std_logic_vector(7 downto 0) := x"11"; -- ^Q
SWFC_XON_TRIGGER : real := 0.0625;
SWFC_XOFF_CHAR : std_logic_vector(7 downto 0) := x"13"; -- ^S
SWFC_XOFF_TRIGGER : real := 0.75
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- FIFO interface
TX_put : in STD_LOGIC;
TX_Data : in STD_LOGIC_VECTOR(7 downto 0);
TX_Full : out STD_LOGIC;
TX_EmptyState : out STD_LOGIC_VECTOR(TX_ESTATE_BITS - 1 downto 0);
RX_Valid : out STD_LOGIC;
RX_Data : out STD_LOGIC_VECTOR(7 downto 0);
RX_got : in STD_LOGIC;
RX_FullState : out STD_LOGIC_VECTOR(RX_FSTATE_BITS - 1 downto 0);
RX_Overflow : out std_logic;
-- External Pins
UART_RX : in std_logic;
UART_TX : out std_logic
);
end component;
end package;
package body uart is
function io_UART_IsTypicalBaudRate(br : BAUD) return BOOLEAN is
begin
for i in C_IO_UART_TYPICAL_BAUDRATES'range loop
next when (br /= C_IO_UART_TYPICAL_BAUDRATES(i));
return TRUE;
end loop;
return FALSE;
end function;
end package body;
| gpl-2.0 | 676534f78547bcaa05ebee60fa92e659 | 0.566153 | 3.00698 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func08b.vhdl | 1 | 573 | entity tb_func08b is
end tb_func08b;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func08b is
signal v : std_ulogic_vector(3 downto 0);
signal r : integer;
begin
dut: entity work.func08b
port map (v, r);
process
begin
v <= x"0";
wait for 1 ns;
assert r = 4 severity failure;
v <= x"1";
wait for 1 ns;
assert r = 3 severity failure;
v <= x"8";
wait for 1 ns;
assert r = 0 severity failure;
v <= x"3";
wait for 1 ns;
assert r = 2 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 086e64d7aa74227a0614efbcdb39eb02 | 0.60733 | 3.148352 | false | false | false | false |
nickg/nvc | test/regress/access7.vhd | 1 | 1,008 | entity access7 is
end entity;
architecture test of access7 is
type int_ptr is access integer;
type int_ptr_ptr is access int_ptr;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr(x : out int_ptr_ptr) is
begin
x := new int_ptr;
end procedure;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array(1 to 3);
end procedure;
begin
process is
variable pp : int_ptr_ptr;
variable pa : int_ptr_array_ptr;
begin
alloc_ptr(pp);
assert pp.all = null;
pp.all := new integer'(4);
assert pp.all.all = 4;
deallocate(pp.all);
deallocate(pp);
alloc_ptr_array(pa);
assert pa.all = (null, null, null);
pa(1) := new integer'(6);
assert pa(1).all = 6;
deallocate(pa(1));
deallocate(pa);
wait;
end process;
end architecture;
| gpl-3.0 | 05f289c2b40495700e1c328f6e85aaef | 0.578373 | 3.5 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue963/ent2.vhdl | 1 | 767 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent2 is
port (
clk : in std_logic;
set_7 : in std_logic;
set_f : in std_logic;
set_a : in std_logic;
set_0 : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end;
architecture a of ent2 is
signal s : unsigned(3 downto 0);
begin
process(clk, set_0, set_a, set_f, set_7)
begin
if set_0 = '1' then
s <= x"0";
elsif set_a = '1' then
s <= x"a";
elsif set_f = '1' then
s <= x"f";
elsif set_7 = '1' then
s <= x"7";
elsif rising_edge(clk) then
s <= s + 1;
end if;
end process;
q <= std_logic_vector(s);
end;
| gpl-2.0 | a5ca29c9c02f0c99b4ef738cbb71978f | 0.483703 | 3.055777 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd | 3 | 1,864 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_01.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_01 is
end entity test_bench_04_01;
library ch4_pkgs;
use ch4_pkgs.pk_04_01.all;
architecture test_coeff_ram_abstract of test_bench_04_01 is
signal rd, wr : bit := '0';
signal addr : coeff_ram_address := 0;
signal d_in, d_out : real := 0.0;
begin
dut : entity work.coeff_ram(abstract)
port map ( rd => rd, wr => wr,
addr => addr,
d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 100 ns;
addr <= 10; d_in <= 10.0; wait for 10 ns;
wr <= '1'; wait for 10 ns;
d_in <= 20.0; wait for 10 ns;
wr <= '0'; wait for 70 ns;
addr <= 20; wait for 10 ns;
rd <= '1'; wait for 10 ns;
addr <= 10; wait for 10 ns;
rd <= '0'; wait for 10 ns;
wait;
end process stumulus;
end architecture test_coeff_ram_abstract;
| gpl-2.0 | 30cca6026f0e4bcbb248141d8577adfa | 0.598176 | 3.464684 | false | true | false | false |
nickg/nvc | test/regress/ieee7.vhd | 1 | 733 | entity ieee7 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
architecture test of ieee7 is
begin
main: process is
variable x, y, z : ufixed(7 downto -3) := (others => '0');
begin
z := to_ufixed(0, 7, -3);
assert x + y = z;
x := to_ufixed(5, 7, -3);
y := to_ufixed(6, 7, -3);
z := to_ufixed(11, 7, -3);
assert x + y = z;
assert to_string(z) = "00001011.000" report to_string(z);
x := to_ufixed(7, 7, -3);
y := to_ufixed(2, 7, -3);
z := to_ufixed(3.5, 7, -3);
assert x / y = z;
assert to_string(z) = "00000011.100" report to_string(z);
wait;
end process;
end architecture;
| gpl-3.0 | d4e2340d20ba32c69b0d273b3db35bcf | 0.514325 | 2.897233 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/restrict2.vhdl | 1 | 520 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity restrict2 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end restrict2;
architecture behav of restrict2 is
signal val : unsigned (3 downto 0);
default clock is rising_edge(clk);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
restrict {rst; (not rst)[*]};
end behav;
| gpl-2.0 | b71faa134b98de0674b7833a7e24272e | 0.625 | 3.209877 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispout01/tb_rec10.vhdl | 1 | 461 | entity tb_rec10 is
end tb_rec10;
library ieee;
use ieee.std_logic_1164.all;
use work.rec10_pkg.all;
architecture behav of tb_rec10 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec10
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r.b (1) = '0' severity failure;
inp <= '0';
wait for 1 ns;
assert r.b (1) = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | f2e42c4e29681faec87498cfe6ca49f1 | 0.613883 | 2.936306 | false | false | false | false |
nickg/nvc | test/regress/alias11.vhd | 1 | 999 | entity sub is
port ( p : in bit_vector(7 downto 0) );
end entity;
architecture test of sub is
alias a1 : bit_vector(3 downto 0) is p(7 downto 4);
alias a2 : bit_vector(3 downto 0) is p(3 downto 0);
begin
process is
begin
wait for 2 ns;
assert a1 = "1111";
assert a2 = "0000";
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity alias11 is
end entity;
architecture test of alias11 is
signal s : bit_vector(7 downto 0);
alias a1 : bit_vector(3 downto 0) is s(7 downto 4);
alias a2 : bit_vector(3 downto 0) is s(3 downto 0);
begin
sub_i: entity work.sub port map (s);
process is
begin
s <= "10100011";
wait for 1 ns;
assert a1 = "1010";
assert a2 = "0011";
a1 <= "1111";
a2 <= "0000";
wait for 1 ns;
assert s = "11110000";
wait;
end process;
end architecture;
| gpl-3.0 | e21cf50594ffc6e00df25b09b16578eb | 0.517518 | 3.659341 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/AESL_axi_slave_CTRL_BUS.vhd | 1 | 49,951 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_slave_CTRL_BUS is
generic (
constant TV_IN_xMin : STRING (1 to 49) := "../tv/cdatafile/c.doHistStretch.autotvin_xMin.dat";
constant TV_IN_xMax : STRING (1 to 49) := "../tv/cdatafile/c.doHistStretch.autotvin_xMax.dat";
constant ADDR_WIDTH : INTEGER := 5;
constant DATA_WIDTH : INTEGER := 32;
constant xMin_DEPTH : INTEGER := 1;
constant xMin_c_bitwidth : INTEGER := 8;
constant xMax_DEPTH : INTEGER := 1;
constant xMax_c_bitwidth : INTEGER := 8;
constant START_ADDR : INTEGER := 0;
constant doHistStretch_continue_addr : INTEGER := 0;
constant doHistStretch_auto_start_addr : INTEGER := 0;
constant xMin_data_in_addr : INTEGER := 16;
constant xMax_data_in_addr : INTEGER := 24;
constant STATUS_ADDR : INTEGER := 0;
constant INTERFACE_TYPE : STRING (1 to 8) := "CTRL_BUS"
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WDATA : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_WSTRB : OUT STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0);
TRAN_s_axi_CTRL_BUS_ARADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RDATA : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_CTRL_BUS_RRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_s_axi_CTRL_BUS_BVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_CTRL_BUS_interrupt : IN STD_LOGIC;
TRAN_CTRL_BUS_write_data_finish : OUT STD_LOGIC;
TRAN_CTRL_BUS_start_in : IN STD_LOGIC;
TRAN_CTRL_BUS_done_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_ready_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_ready_in : IN STD_LOGIC;
TRAN_CTRL_BUS_idle_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_write_start_in : IN STD_LOGIC;
TRAN_CTRL_BUS_write_start_finish : OUT STD_LOGIC;
TRAN_CTRL_BUS_transaction_done_in : IN STD_LOGIC
);
end AESL_axi_slave_CTRL_BUS;
architecture behav of AESL_axi_slave_CTRL_BUS is
------------------------Local signal-------------------
shared variable xMin_OPERATE_DEPTH : INTEGER;
shared variable xMax_OPERATE_DEPTH : INTEGER;
signal AWADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_2_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_3_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal AWVALID_reg : STD_LOGIC := '0';
signal process_0_AWVALID_var : STD_LOGIC := '0';
signal process_1_AWVALID_var : STD_LOGIC := '0';
signal process_2_AWVALID_var : STD_LOGIC := '0';
signal process_3_AWVALID_var : STD_LOGIC := '0';
signal WVALID_reg : STD_LOGIC := '0';
signal process_0_WVALID_var : STD_LOGIC := '0';
signal process_1_WVALID_var : STD_LOGIC := '0';
signal process_2_WVALID_var : STD_LOGIC := '0';
signal process_3_WVALID_var : STD_LOGIC := '0';
signal WDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_2_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_3_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal WSTRB_reg : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_0_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_1_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_2_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_3_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal ARADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_2_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_3_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal ARVALID_reg : STD_LOGIC := '0';
signal process_0_ARVALID_var : STD_LOGIC := '0';
signal process_1_ARVALID_var : STD_LOGIC := '0';
signal process_2_ARVALID_var : STD_LOGIC := '0';
signal process_3_ARVALID_var : STD_LOGIC := '0';
signal RREADY_reg : STD_LOGIC := '0';
signal process_0_RREADY_var : STD_LOGIC := '0';
signal process_1_RREADY_var : STD_LOGIC := '0';
signal process_2_RREADY_var : STD_LOGIC := '0';
signal process_3_RREADY_var : STD_LOGIC := '0';
signal RDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_2_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_3_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal BREADY_reg : STD_LOGIC := '0';
signal process_0_BREADY_var : STD_LOGIC := '0';
signal process_1_BREADY_var : STD_LOGIC := '0';
signal process_2_BREADY_var : STD_LOGIC := '0';
signal process_3_BREADY_var : STD_LOGIC := '0';
type mem_xMin_arr2D is array(0 to xMin_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_xMin : mem_xMin_arr2D;
signal xMin_write_data_finish : STD_LOGIC := '0';
type mem_xMax_arr2D is array(0 to xMax_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_xMax : mem_xMax_arr2D;
signal xMax_write_data_finish : STD_LOGIC := '0';
signal AESL_ready_out_index_reg : STD_LOGIC := '0';
signal AESL_write_start_finish : STD_LOGIC := '0';
signal AESL_ready_reg : STD_LOGIC;
signal ready_initial : STD_LOGIC;
signal AESL_done_index_reg : STD_LOGIC := '0';
signal AESL_idle_index_reg : STD_LOGIC := '0';
signal AESL_auto_restart_index_reg : STD_LOGIC;
signal process_0_finish : STD_LOGIC := '0';
signal process_1_finish : STD_LOGIC := '0';
signal process_2_finish : STD_LOGIC := '0';
signal process_3_finish : STD_LOGIC := '0';
--write xMin reg
shared variable write_xMin_count : INTEGER;
signal write_xMin_run_flag : STD_LOGIC := '0';
signal write_one_xMin_data_done : STD_LOGIC := '0';
--write xMax reg
shared variable write_xMax_count : INTEGER;
signal write_xMax_run_flag : STD_LOGIC := '0';
signal write_one_xMax_data_done : STD_LOGIC := '0';
shared variable write_start_count : INTEGER;
signal write_start_run_flag : STD_LOGIC := '0';
--===================process control=================
signal ongoing_process_number : INTEGER;
-- Process number depends on how much processes needed.
shared variable process_busy : STD_LOGIC := '0';
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
procedure count_c_data_four_byte_num_by_bitwidth (constant bitwidth : IN INTEGER; variable num : OUT INTEGER) is
variable factor : INTEGER;
variable i : INTEGER;
begin
factor := 32;
for i in 1 to 32 loop
if (bitwidth <= factor and bitwidth > factor - 32) then
num := i;
end if;
factor := factor + 32;
end loop;
end procedure;
procedure count_seperate_factor_by_bitwidth(bitwidth : in INTEGER; factor : out INTEGER) is
begin
if (bitwidth <= 8) then
factor := 4;
elsif (bitwidth <= 16 and bitwidth > 8 ) then
factor := 2;
elsif (bitwidth <= 32 and bitwidth > 16 ) then
factor := 1;
elsif (bitwidth <= 1024 and bitwidth > 32 ) then
factor := 1;
end if;
end procedure;
procedure count_operate_depth_by_bitwidth_and_depth(bitwidth : in INTEGER; depth : in INTEGER; operate_depth : out INTEGER) is
variable factor : INTEGER;
variable remain : INTEGER;
variable operate_depth_tmp : INTEGER;
begin
count_seperate_factor_by_bitwidth (bitwidth , factor);
operate_depth_tmp := depth / factor;
remain := depth mod factor;
if (remain > 0) then
operate_depth_tmp := operate_depth_tmp + 1;
end if;
operate_depth := operate_depth_tmp;
end procedure;
begin
--=================== signal connection ==============
TRAN_s_axi_CTRL_BUS_AWADDR <= AWADDR_reg;
TRAN_s_axi_CTRL_BUS_AWVALID <= AWVALID_reg;
TRAN_s_axi_CTRL_BUS_WVALID <= WVALID_reg;
TRAN_s_axi_CTRL_BUS_WDATA <= WDATA_reg;
TRAN_s_axi_CTRL_BUS_WSTRB <= WSTRB_reg;
TRAN_s_axi_CTRL_BUS_ARADDR <= ARADDR_reg;
TRAN_s_axi_CTRL_BUS_ARVALID <= ARVALID_reg;
TRAN_s_axi_CTRL_BUS_RREADY <= RREADY_reg;
TRAN_s_axi_CTRL_BUS_BREADY <= BREADY_reg;
TRAN_CTRL_BUS_done_out <= AESL_done_index_reg;
TRAN_CTRL_BUS_ready_out <= AESL_ready_out_index_reg;
TRAN_CTRL_BUS_write_start_finish <= AESL_write_start_finish;
TRAN_CTRL_BUS_idle_out <= AESL_idle_index_reg;
TRAN_CTRL_BUS_write_data_finish <= '1' and xMin_write_data_finish and xMax_write_data_finish;
AESL_ready_reg_proc : process(TRAN_CTRL_BUS_ready_in, ready_initial)
begin
AESL_ready_reg <= TRAN_CTRL_BUS_ready_in or ready_initial;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until reset = '1';
wait until clk'event and clk = '1';
ready_initial <= '1';
wait until clk'event and clk = '1';
ready_initial <= '0';
wait;
end process;
ongoing_process_number_gen : process(reset , process_0_finish , process_1_finish , process_2_finish , process_3_finish )
begin
if (reset = '0') then
ongoing_process_number <= 0;
elsif (ongoing_process_number = 0 and process_0_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 1 and process_1_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 2 and process_2_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 3 and process_3_finish = '1') then
ongoing_process_number <= 0;
end if;
end process;
output_reg_write_value_function : process
begin
wait until reset = '1';
wait until clk'event and clk = '1';
while (true) loop
if (ongoing_process_number = 0 ) then
AWADDR_reg <= process_0_AWADDR_var;
AWVALID_reg <= process_0_AWVALID_var;
WVALID_reg <= process_0_WVALID_var;
WDATA_reg <= process_0_WDATA_var;
WSTRB_reg <= process_0_WSTRB_var;
ARADDR_reg <= process_0_ARADDR_var;
ARVALID_reg <= process_0_ARVALID_var;
RREADY_reg <= process_0_RREADY_var;
BREADY_reg <= process_0_BREADY_var;
elsif (ongoing_process_number = 1 ) then
AWADDR_reg <= process_1_AWADDR_var;
AWVALID_reg <= process_1_AWVALID_var;
WVALID_reg <= process_1_WVALID_var;
WDATA_reg <= process_1_WDATA_var;
WSTRB_reg <= process_1_WSTRB_var;
ARADDR_reg <= process_1_ARADDR_var;
ARVALID_reg <= process_1_ARVALID_var;
RREADY_reg <= process_1_RREADY_var;
BREADY_reg <= process_1_BREADY_var;
elsif (ongoing_process_number = 2 ) then
AWADDR_reg <= process_2_AWADDR_var;
AWVALID_reg <= process_2_AWVALID_var;
WVALID_reg <= process_2_WVALID_var;
WDATA_reg <= process_2_WDATA_var;
WSTRB_reg <= process_2_WSTRB_var;
ARADDR_reg <= process_2_ARADDR_var;
ARVALID_reg <= process_2_ARVALID_var;
RREADY_reg <= process_2_RREADY_var;
BREADY_reg <= process_2_BREADY_var;
elsif (ongoing_process_number = 3 ) then
AWADDR_reg <= process_3_AWADDR_var;
AWVALID_reg <= process_3_AWVALID_var;
WVALID_reg <= process_3_WVALID_var;
WDATA_reg <= process_3_WDATA_var;
WSTRB_reg <= process_3_WSTRB_var;
ARADDR_reg <= process_3_ARADDR_var;
ARVALID_reg <= process_3_ARVALID_var;
RREADY_reg <= process_3_RREADY_var;
BREADY_reg <= process_3_BREADY_var;
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
update_status_proc : process
variable process_num : INTEGER;
variable read_status_resp : INTEGER;
variable process_0_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 0;
while (true) loop
process_0_finish <= '0';
AESL_done_index_reg <= '0';
AESL_ready_out_index_reg <= '0';
if (ongoing_process_number = process_num and process_busy = '0') then
process_busy := '1';
--=======================one single read operate======================
read_status_resp := 0;
process_0_ARADDR_var <= STD_LOGIC_VECTOR(to_unsigned(STATUS_ADDR, ADDR_WIDTH));
process_0_ARVALID_var <= '1';
while (TRAN_s_axi_CTRL_BUS_ARREADY /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_ARVALID_var <= '0';
process_0_RREADY_var <= '1';
while (TRAN_s_axi_CTRL_BUS_RVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_RDATA_tmp := TRAN_s_axi_CTRL_BUS_RDATA;
process_0_RREADY_var <= '0';
if (TRAN_s_axi_CTRL_BUS_RRESP = (2 => '0') ) then
read_status_resp := 1;
--output success. in fact RRESP is always 2'b00
end if;
wait until clk'event and clk = '1';
--=======================one single read operate end======================
AESL_done_index_reg <= process_0_RDATA_tmp(1);
AESL_ready_out_index_reg <= process_0_RDATA_tmp(1);
AESL_idle_index_reg <= process_0_RDATA_tmp(2);
process_busy := '0';
process_0_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_xMin_run_flag : process (reset , clk)
begin
if (reset = '0') then
xMin_write_data_finish <= '0';
write_xMin_run_flag <= '0';
write_xMin_count := 0;
count_operate_depth_by_bitwidth_and_depth (xMin_c_bitwidth, xMin_DEPTH, xMin_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_CTRL_BUS_start_in = '1') then
xMin_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_xMin_run_flag <= '1';
write_xMin_count := 0;
end if;
if (write_one_xMin_data_done = '1') then
write_xMin_count := write_xMin_count + 1;
if (write_xMin_count = xMin_OPERATE_DEPTH) then
write_xMin_run_flag <= '0';
xMin_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_xMin_proc : process
variable write_xMin_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_1_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable xMin_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := xMin_c_bitwidth;
process_num := 1;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_1_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_xMin_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write xMin data
for i in 0 to four_byte_num - 1 loop
if (xMin_c_bitwidth < 32) then
xMin_data_tmp_reg := mem_xMin(write_xMin_count);
else
for j in 0 to 31 loop
if (i*32 + j < xMin_c_bitwidth) then
xMin_data_tmp_reg(j) := mem_xMin(write_xMin_count)(i*32 + j);
else
xMin_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_xMin_resp := 0;
aw_flag := '0';
w_flag := '0';
process_1_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(xMin_data_in_addr + write_xMin_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_1_AWVALID_var <= '1';
process_1_WDATA_var <= xMin_data_tmp_reg;
process_1_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_1_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_CTRL_BUS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_CTRL_BUS_WREADY and WVALID_reg;
end if;
process_1_AWVALID_var <= not aw_flag;
process_1_WVALID_var <= not w_flag;
end loop;
process_1_BREADY_var <= '1';
while (TRAN_s_axi_CTRL_BUS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_1_BREADY_var <= '0';
if (TRAN_s_axi_CTRL_BUS_BRESP = (2 => '0')) then
write_xMin_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_xMin_data_done <= '1';
wait until clk'event and clk = '1';
write_one_xMin_data_done <= '0';
end if;
process_1_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_xMax_run_flag : process (reset , clk)
begin
if (reset = '0') then
xMax_write_data_finish <= '0';
write_xMax_run_flag <= '0';
write_xMax_count := 0;
count_operate_depth_by_bitwidth_and_depth (xMax_c_bitwidth, xMax_DEPTH, xMax_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_CTRL_BUS_start_in = '1') then
xMax_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_xMax_run_flag <= '1';
write_xMax_count := 0;
end if;
if (write_one_xMax_data_done = '1') then
write_xMax_count := write_xMax_count + 1;
if (write_xMax_count = xMax_OPERATE_DEPTH) then
write_xMax_run_flag <= '0';
xMax_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_xMax_proc : process
variable write_xMax_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_2_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable xMax_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := xMax_c_bitwidth;
process_num := 2;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_2_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_xMax_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write xMax data
for i in 0 to four_byte_num - 1 loop
if (xMax_c_bitwidth < 32) then
xMax_data_tmp_reg := mem_xMax(write_xMax_count);
else
for j in 0 to 31 loop
if (i*32 + j < xMax_c_bitwidth) then
xMax_data_tmp_reg(j) := mem_xMax(write_xMax_count)(i*32 + j);
else
xMax_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_xMax_resp := 0;
aw_flag := '0';
w_flag := '0';
process_2_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(xMax_data_in_addr + write_xMax_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_2_AWVALID_var <= '1';
process_2_WDATA_var <= xMax_data_tmp_reg;
process_2_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_2_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_CTRL_BUS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_CTRL_BUS_WREADY and WVALID_reg;
end if;
process_2_AWVALID_var <= not aw_flag;
process_2_WVALID_var <= not w_flag;
end loop;
process_2_BREADY_var <= '1';
while (TRAN_s_axi_CTRL_BUS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_2_BREADY_var <= '0';
if (TRAN_s_axi_CTRL_BUS_BRESP = (2 => '0')) then
write_xMax_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_xMax_data_done <= '1';
wait until clk'event and clk = '1';
write_one_xMax_data_done <= '0';
end if;
process_2_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_start_run_flag : process (reset , clk)
begin
if (reset = '0') then
write_start_run_flag <= '0';
write_start_count := 0;
elsif (clk'event and clk = '1') then
if (write_start_count >= 1) then
write_start_run_flag <= '0';
elsif (TRAN_CTRL_BUS_write_start_in = '1') then
write_start_run_flag <= '1';
end if;
if (AESL_write_start_finish = '1') then
write_start_count := write_start_count + 1;
write_start_run_flag <= '0';
end if;
end if;
end process;
write_start_proc : process
variable process_num : INTEGER;
variable write_start_resp : INTEGER;
variable write_start_tmp : STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0) ;
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
variable i : INTEGER;
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 3;
while (true) loop
process_3_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
if (write_start_run_flag = '1') then
process_busy := '1';
write_start_tmp := (others => '0');
write_start_tmp(0) := '1';
--=======================one single write operate======================
write_start_resp := 0;
aw_flag := '0';
w_flag := '0';
process_3_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(START_ADDR, ADDR_WIDTH));
process_3_AWVALID_var <= '1';
process_3_WDATA_var <= write_start_tmp;
process_3_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_3_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_CTRL_BUS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_CTRL_BUS_WREADY and WVALID_reg;
end if;
process_3_AWVALID_var <= not aw_flag;
process_3_WVALID_var <= not w_flag;
end loop;
process_3_BREADY_var <= '1';
while (TRAN_s_axi_CTRL_BUS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_3_BREADY_var <= '0';
if (TRAN_s_axi_CTRL_BUS_BRESP = (2 => '0')) then
write_start_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
process_busy := '0';
AESL_write_start_finish <= '1';
wait until clk'event and clk = '1';
AESL_write_start_finish <= '0';
end if;
process_3_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
--------------------------Read file------------------------
-- Read data from file
read_xMin_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(xMin_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (xMin_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_xMin , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_xMin & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to xMin_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, xMin_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to xMin_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_xMin(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to xMin_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_xMin(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (xMin_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to xMin_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_xMin(i)(31 downto 0) := mem_tmp_32;
else
mem_xMin(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_xMin(xMin_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_xMin(xMin_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_xMax_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(xMax_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (xMax_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_xMax , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_xMax & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to xMax_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, xMax_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to xMax_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_xMax(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to xMax_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_xMax(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (xMax_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to xMax_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_xMax(i)(31 downto 0) := mem_tmp_32;
else
mem_xMax(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_xMax(xMax_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_xMax(xMax_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
end behav;
| gpl-3.0 | 6c38211a9683c515927bda53d9167aa9 | 0.495786 | 3.657538 | false | false | false | false |
makestuff/comm-fpga | epp/vhdl/comm_fpga_epp.vhdl | 1 | 6,508 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity comm_fpga_epp is
port(
clk_in : in std_logic; -- clock input (asynchronous with EPP signals)
reset_in : in std_logic; -- synchronous active-high reset input
reset_out : out std_logic; -- synchronous active-high reset output
-- EPP interface -----------------------------------------------------------------------------
eppData_io : inout std_logic_vector(7 downto 0); -- bidirectional 8-bit data bus
eppAddrStb_in : in std_logic; -- active-low asynchronous address strobe
eppDataStb_in : in std_logic; -- active-low asynchronous data strobe
eppWrite_in : in std_logic; -- read='1'; write='0'
eppWait_out : out std_logic; -- active-low asynchronous wait signal
-- Channel read/write interface --------------------------------------------------------------
chanAddr_out : out std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_out : out std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_out : out std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData_out"
h2fReady_in : in std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_in : in std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_in : in std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_out : out std_logic -- '1' means "on the next clock rising edge, put your next byte of data on f2hData_in"
);
end entity;
architecture rtl of comm_fpga_epp is
type StateType is (
S_RESET,
S_IDLE,
S_ADDR_WRITE_WAIT,
S_DATA_WRITE_EXEC,
S_DATA_WRITE_WAIT,
S_DATA_READ_EXEC,
S_DATA_READ_WAIT
);
-- State and next-state
signal state : StateType := S_RESET;
signal state_next : StateType;
-- Synchronised versions of asynchronous inputs
signal eppAddrStb_sync : std_logic := '1';
signal eppDataStb_sync : std_logic := '1';
signal eppWrite_sync : std_logic := '1';
-- Registers
signal eppWait : std_logic := '1';
signal eppWait_next : std_logic;
signal chanAddr : std_logic_vector(6 downto 0) := (others => '0');
signal chanAddr_next : std_logic_vector(6 downto 0);
signal eppData : std_logic_vector(7 downto 0) := (others => '0');
signal eppData_next : std_logic_vector(7 downto 0);
-- Other signals
signal driveBus : std_logic := '0'; -- whether or not to drive eppData_io
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_RESET;
chanAddr <= (others => '0');
eppData <= (others => '0');
eppWait <= '1';
eppAddrStb_sync <= '1';
eppDataStb_sync <= '1';
eppWrite_sync <= '1';
else
state <= state_next;
chanAddr <= chanAddr_next;
eppData <= eppData_next;
eppWait <= eppWait_next;
eppAddrStb_sync <= eppAddrStb_in;
eppDataStb_sync <= eppDataStb_in;
eppWrite_sync <= eppWrite_in;
end if;
end if;
end process;
-- Next state logic
process(
state, eppData_io, eppAddrStb_sync, eppDataStb_sync, eppWrite_sync, chanAddr, eppWait, eppData,
f2hData_in, f2hValid_in, h2fReady_in)
begin
state_next <= state;
chanAddr_next <= chanAddr;
eppWait_next <= eppWait;
eppData_next <= eppData;
h2fData_out <= (others => '0');
f2hReady_out <= '0';
h2fValid_out <= '0';
reset_out <= '0';
driveBus <= eppWrite_sync;
case state is
-- Finish the address update cycle
when S_ADDR_WRITE_WAIT =>
if ( eppAddrStb_sync = '1' ) then
eppWait_next <= '0';
state_next <= S_IDLE;
end if;
-- Host writes a byte to the FPGA
when S_DATA_WRITE_EXEC =>
h2fData_out <= eppData_io;
h2fValid_out <= '1';
if ( h2fReady_in = '1') then
eppWait_next <= '1';
state_next <= S_DATA_WRITE_WAIT;
end if;
when S_DATA_WRITE_WAIT =>
if ( eppDataStb_sync = '1' ) then
eppWait_next <= '0';
state_next <= S_IDLE;
end if;
-- Host reads a byte from the FPGA
when S_DATA_READ_EXEC =>
eppData_next <= f2hData_in;
f2hReady_out <= '1';
if ( f2hValid_in = '1' ) then
eppWait_next <= '1';
state_next <= S_DATA_READ_WAIT;
end if;
when S_DATA_READ_WAIT =>
if ( eppDataStb_sync = '1' ) then
eppWait_next <= '0';
state_next <= S_IDLE;
end if;
-- S_RESET - tri-state everything
when S_RESET =>
reset_out <= '1';
driveBus <= '0';
if ( eppWrite_sync = '0' ) then
state_next <= S_IDLE;
end if;
-- S_IDLE and others
when others =>
eppWait_next <= '0';
if ( eppAddrStb_sync = '0' ) then
-- Address can only be written, not read
if ( eppWrite_sync = '0' ) then
eppWait_next <= '1';
chanAddr_next <= eppData_io(6 downto 0);
state_next <= S_ADDR_WRITE_WAIT;
end if;
elsif ( eppDataStb_sync = '0' ) then
-- Register read or write
if ( eppWrite_sync = '0' ) then
state_next <= S_DATA_WRITE_EXEC;
else
state_next <= S_DATA_READ_EXEC;
end if;
end if;
end case;
end process;
-- Drive stateless signals
chanAddr_out <= chanAddr;
eppWait_out <= eppWait;
eppData_io <=
eppData when ( driveBus = '1' ) else
"ZZZZZZZZ";
end architecture;
| gpl-3.0 | 5012eb16a257e018cc79cc21b2f87445 | 0.589121 | 3.351184 | false | false | false | false |
makestuff/comm-fpga | ss/vhdl/sync-recv/tb_unit/sync_recv_tb.vhdl | 1 | 3,670 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity sync_recv_tb is
end entity;
architecture behavioural of sync_recv_tb is
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
-- Serial in
signal serClk : std_logic;
signal serData : std_logic;
-- Parallel out
signal recvData : std_logic_vector(7 downto 0);
signal recvValid : std_logic;
-- Detect rising serClk edges
signal serClk_prev : std_logic;
signal serClkFE : std_logic;
begin
-- Instantiate sync_recv module for testing
uut: entity work.sync_recv
port map(
clk_in => sysClk,
-- Serial in
serClkFE_in => serClkFE,
serData_in => serData,
-- Parallel out
recvData_out => recvData,
recvValid_out => recvValid
);
-- Infer registers
process(sysClk)
begin
if ( rising_edge(sysClk) ) then
serClk_prev <= serClk;
end if;
end process;
-- Detect rising edges on serClk
serClkFE <=
'1' when serClk = '0' and serClk_prev = '1'
else '0';
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive serClk
process
begin
serClk <= '0';
loop
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
serClk <= not(serClk);
end loop;
end process;
-- Drive the sync serial signals
process
procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is
begin
serData <= '0'; -- start bit
wait until rising_edge(serClk); serData <= b(0); -- bit 0
wait until rising_edge(serClk); serData <= b(1); -- bit 1
wait until rising_edge(serClk); serData <= b(2); -- bit 2
wait until rising_edge(serClk); serData <= b(3); -- bit 3
wait until rising_edge(serClk); serData <= b(4); -- bit 4
wait until rising_edge(serClk); serData <= b(5); -- bit 5
wait until rising_edge(serClk); serData <= b(6); -- bit 6
wait until rising_edge(serClk); serData <= b(7); -- bit 7
wait until rising_edge(serClk); serData <= '1'; -- stop bit
wait until rising_edge(serClk);
end procedure;
procedure pause(constant n : in integer) is
variable i : integer;
begin
for i in 1 to n loop
wait until rising_edge(serClk);
end loop;
end procedure;
begin
serData <= '1';
pause(4);
sendByte(x"55");
sendByte(x"5B");
sendByte(x"5A");
serData <= 'Z'; -- tri-state data line after final send (AVR disables sender)
wait;
end process;
end architecture;
| gpl-3.0 | 16504e59cdd6fb23019be72b7c02a655 | 0.664305 | 3.282648 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd | 4 | 3,000 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
| gpl-2.0 | 816340cf14d9842ff3ae99b3f5ec41f2 | 0.445667 | 5.181347 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_pipe_v3_0_2/xbip_pipe_v3_0_vh_rfs.vhd | 9 | 24,644 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
| gpl-3.0 | d2522c384dae9a5427c5418adb9b86c9 | 0.941649 | 1.87037 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1258/ent.vhdl | 1 | 515 | -- count number of '1'.
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
sel : in std_ulogic;
din : in std_ulogic_vector(15 downto 0);
dout : out std_ulogic
);
end;
architecture rtl of ent is
begin
comb : process (sel, din)
variable v : std_ulogic;
begin
v := '0';
if sel = '1' then
for i in din'range loop
if din(i) = '0' then
next;
end if;
v := not v;
end loop;
end if;
dout <= v;
end process;
end;
| gpl-2.0 | c19f7624f16e41cb4e09a3ce14ec585d | 0.535922 | 3.121212 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd | 4 | 2,951 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc407.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00407ent IS
END c03s02b01x01p19n01i00407ent;
ARCHITECTURE c03s02b01x01p19n01i00407arch OF c03s02b01x01p19n01i00407ent IS
constant C1 : bit := '1';
function complex_scalar(s : bit) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return bit is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : bit;
signal S2 : bit;
signal S3 : bit := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00407"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00407 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00407arch;
| gpl-2.0 | b1ea4cc84c2989f5b875c24ed1a63c7d | 0.651982 | 3.656753 | false | true | false | false |
nickg/nvc | lib/std.08/standard.vhd | 1 | 4,240 | -- -------------------------------------------------*- coding: latin-1; -*-----
-- Copyright (C) 2011-2022 Nick Gasson
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- STANDARD package as defined by IEEE 1076-2008.
-------------------------------------------------------------------------------
package STANDARD is
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134, C135,
C136, C137, C138, C139, C140, C141, C142, C143,
C144, C145, C146, C147, C148, C149, C150, C151,
C152, C153, C154, C155, C156, C157, C158, C159,
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '¶', '¹',
C184, C185, C186, C187, C188, C189, C190, C191,
C192, C193, C194, C195, C196, C197, C198, C199,
C200, C201, C202, C203, C204, C205, C206, C207,
C208, C209, C210, C211, C212, C213, C214, C215,
C216, C217, C218, C219, C220, C221, C222, C223,
C224, C225, C226, C227, C228, C229, C230, C231,
C232, C233, C234, C235, C236, C237, C238, C239,
C240, C241, C242, C243, C244, C245, C246, C247,
C248, C249, C250, C251, C252, C253, C254, C255
);
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
-- type universal_integer is range implementation_defined;
type INTEGER is range -2147483648 to 2147483647;
-- type universal_real is range implementation_defined;
type REAL is range -1.7976931348623157e308 to 1.7976931348623157e308;
type TIME is range -9223372036854775807 - 1 to 9223372036854775807
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
impure function NOW return DELAY_LENGTH;
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
type STRING is array (POSITIVE range <>) of CHARACTER;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR,
MODE_ERROR);
attribute FOREIGN : STRING;
attribute FOREIGN of NOW : function is "_std_standard_now";
end package;
| gpl-3.0 | 85ebbc1ee8132baf7066657a9038f5dd | 0.489858 | 3.309914 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug021/tb_cosim.vhd | 2 | 1,333 | --------------------------------------------------------------------------------
-- Company: Dossmatik GmbH
-- Create Date: 21:08:31 05/17/2011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench
-- test for VHPI
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sim_pkg.all;
entity tb_cosim is
end tb_cosim;
architecture behavior of tb_cosim is
function crc (crc_value : std_logic_vector(31 downto 0)
) return std_logic_vector is
variable crc_out : std_logic_vector(31 downto 0);
begin
crc_out := (crc(3 downto 0)& crc_out(31 downto 4)) xor crc;
return crc_out;
end crc;
signal random : std_logic_vector ( 31 downto 0):=X"00000000";
-- Clock period definitions
constant board_clk_period : time := 20 ns;
signal board_clk: std_logic;
begin
process (board_clk)
begin
if rising_edge(board_clk) then
street(to_integer(unsigned(random)));
random<=crc(random);
end if;
end process;
-- Clock process definitions
board_clk_process : process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
end;
| gpl-2.0 | 86070a25006d61713f0bef8e39f63894 | 0.555889 | 3.702778 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn01.vhdl | 1 | 612 | entity tb_asgn01 is
end tb_asgn01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn01 is
signal a : std_logic_vector (2 downto 0);
signal s0 : std_logic;
signal r : std_logic_vector (2 downto 0);
begin
dut: entity work.asgn01
port map (a => a, s0 => s0, r => r);
process
begin
s0 <= '1';
wait for 1 ns;
assert r = "000" severity failure;
a <= "101";
s0 <= '0';
wait for 1 ns;
assert r = "101" severity failure;
a <= "110";
s0 <= '0';
wait for 1 ns;
assert r = "110" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | aebfd0adf5f95f26810329de1d8d79e2 | 0.584967 | 3 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue332/irqc_pif_pkg.vhd | 1 | 4,647 | --========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 6; -- 1 <= C_NUM_SOURCES <= Data width
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rd : std_logic; -- to dut
wr : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
------------------------------------------
-- init_sbi_if_signals
------------------------------------------
-- - This function returns an SBI interface with initialized signals.
-- - All SBI input signals are initialized to 0
-- - All SBI output signals are initialized to Z
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if;
end package irqc_pif_pkg;
package body irqc_pif_pkg is
---------------------------------------------------------------------------------
-- initialize sbi to dut signals
---------------------------------------------------------------------------------
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if( addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rd := '0';
result.wr := '0';
result.addr := (others => '0');
result.wdata := (others => '0');
result.ready := 'Z';
result.rdata := (others => 'Z');
return result;
end function;
end package body irqc_pif_pkg;
| gpl-2.0 | be6f10bbf17a8a30562f425cae42b97a | 0.531741 | 4.197832 | false | false | false | false |
tgingold/ghdl | testsuite/synth/exit01/tb_exit02.vhdl | 1 | 806 | entity tb_exit02 is
end tb_exit02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_exit02 is
signal v : std_logic_vector(3 downto 0);
signal r : integer;
begin
dut: entity work.exit02
port map (val => v, res => r);
process
begin
v <= "0001";
wait for 1 ns;
assert r = 0 severity failure;
v <= "0010";
wait for 1 ns;
assert r = 1 severity failure;
v <= "0100";
wait for 1 ns;
assert r = 2 severity failure;
v <= "1000";
wait for 1 ns;
assert r = 3 severity failure;
v <= "0000";
wait for 1 ns;
assert r = 4 severity failure;
v <= "0110";
wait for 1 ns;
assert r = 1 severity failure;
v <= "1001";
wait for 1 ns;
assert r = 0 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | da3acf7d3d3889ba9c4b21ab7cb275e7 | 0.584367 | 3.386555 | false | false | false | false |
nickg/nvc | test/regress/bounds24.vhd | 1 | 535 | entity bounds24 is
end entity;
architecture test of bounds24 is
function func (n : natural) return bit is
variable r : bit_vector(1 to 3) := (1 to n => '1');
begin
return r(1) xor r(2) xor r(3);
end function;
signal n : integer := 3;
begin
main: process is
begin
assert func(3) = '1'; -- OK
assert func(n) = '1'; -- OK
n <= 1000;
wait for 1 ns;
assert func(n) = '1'; -- Error
wait;
end process;
end architecture;
| gpl-3.0 | 8bb184ed2f606fb519a6fe8dff9eabf5 | 0.508411 | 3.566667 | false | false | false | false |
nickg/nvc | test/sem/mcase.vhd | 1 | 1,121 | entity mcase is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of mcase is
begin
p1: process is
variable x : std_logic;
variable y : std_logic_vector(1 to 3);
variable z : integer;
begin
case? x is -- OK
when '1' => null;
when '-' => null;
end case?;
case? z is
when 1 => null; -- Error
end case?;
case? y is -- OK
when "---" => null;
end case?;
wait;
end process;
p2 : process is
type my_vec is array (natural range <>) of std_logic;
type my_vec2 is array (natural range <>, natural range <>) of std_logic;
variable x : my_vec(1 to 1);
variable y : my_vec2(1 to 1, 1 to 1);
begin
case? x is -- OK
when "1" => null;
when "-" => null;
end case?;
case? y is -- Error
when others => null;
end case?;
wait;
end process;
end architecture;
| gpl-3.0 | 7f2980d9f0b2801c874425f22a423ed1 | 0.446922 | 4.151852 | false | false | false | false |
nickg/nvc | test/regress/vests20.vhd | 1 | 12,280 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc870.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00870pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00870pkg;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
entity test1 is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test1 of test1 is
begin
sigout1 <= false;
sigout2 <= '0';
sigout4 <= error;
sigout5 <= 6;
sigout6 <= 6.0;
sigout7 <= 6 ns;
sigout8 <= 6;
sigout9 <= 6;
sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
end;
configuration test1bench of test1 is
for test1
end for;
end;
use work.c01s03b01x00p12n01i00870pkg.all;
ENTITY c01s03b01x00p12n01i00870ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15);
port(
dumy : inout bit_vector(zero to three));
END c01s03b01x00p12n01i00870ent;
ARCHITECTURE c01s03b01x00p12n01i00870arch OF c01s03b01x00p12n01i00870ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test1
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test1
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
variable dumb : bit_vector(zero to three);
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***PASSED TEST: c01s03b01x00p12n01i00870"
severity NOTE;
assert ( Sin1(0) = sin1(4) and
Sin2(0) = Sin2(4) and
Sin4(0) = Sin4(4) and
Sin5(0) = Sin5(4) and
Sin6(0) = Sin6(4) and
Sin7(0) = Sin7(4) and
Sin8(0) = Sin8(4) and
Sin9(0) = Sin9(4) and
Sin10(0)= Sin10(4) and
Sin1(5) = '0' and
Sin2(5) = FALSE and
Sin4(5) = error and
Sin5(5) = 6 and
Sin6(5) = 6.0 and
Sin7(5) = 6 ns and
Sin8(5) = 6 and
Sin9(5) = 6 and
Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
report "***FAILED TEST: c01s03b01x00p12n01i00870 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00870arch;
configuration vests20 of c01s03b01x00p12n01i00870ent is
for c01s03b01x00p12n01i00870arch
for K
for others:test1 use configuration work.test1bench;
end for;
for G(0 to 3)
for all :test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-3.0 | 0024549ba052ef1e936ec125b6a459af | 0.573371 | 3.346961 | false | true | false | false |
nickg/nvc | test/jit/access1.vhd | 1 | 1,224 | package access1 is
type int_ptr is access integer;
procedure deref (variable p : int_ptr; result : out integer);
procedure test1 (variable p : inout int_ptr);
procedure oom;
procedure gc_a_lot;
end package;
package body access1 is
procedure deref (variable p : int_ptr; result : out integer) is
begin
result := p.all;
end procedure;
procedure test1 (variable p : inout int_ptr) is
variable i : integer;
begin
p := new integer;
p.all := 5;
deref(p, i);
assert i = 5;
deallocate(p);
end procedure;
type biglist;
type biglist_ptr is access biglist;
type biglist is record
str : string(1 to 2 ** 10);
chain : biglist_ptr;
end record;
procedure oom is
variable head, tail : biglist_ptr;
begin
head := new biglist;
tail := head;
while true loop
tail.chain := new biglist;
tail := tail.chain;
end loop;
end procedure;
procedure gc_a_lot is
variable tail : biglist_ptr;
begin
for i in 1 to 5000 loop
tail := new biglist;
end loop;
end procedure;
end package body;
| gpl-3.0 | eb8f15697de36b00ae2c8c9bdba1e772 | 0.571078 | 4.135135 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1090/simple_ram.vhdl | 1 | 2,035 | -- Machine generated from ram.img.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package bootrom is
type rom_t is array (0 to 127) of std_logic_vector(31 downto 0);
constant rom : rom_t := (
x"00000110",
x"00001ffc",
x"00000110",
-- more stuff, doesn't matter as long as it fits...
x"23811fac",
x"00afffac",
others => x"00000000" );
end package;
package body bootrom is
end package body;
-- A simple pre-initalized RAM, which reads from a binary file at synthesis time
-- single 32 bit read/write port.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity simple_ram is
generic (
-- 32-bit read/write port. ADDR_WIDTH is in bytes, not words.
ADDR_WIDTH : integer := 8 -- default 32k
);
port (
clk : in std_logic;
en : in std_logic;
raddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
do : out std_logic_vector(31 downto 0);
we : in std_logic_vector(3 downto 0);
waddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
di : in std_logic_vector(31 downto 0)
);
end simple_ram;
use work.bootrom.all;
architecture behavioral of simple_ram is
constant NUM_WORDS : integer := 2**(ADDR_WIDTH - 2);
signal ram : rom_t := work.bootrom.rom; -- FIXME init internal error
begin
process (clk, en)
variable read : std_logic_vector(31 downto 0);
begin
if clk'event and clk = '1' and en = '1' then -- Unsupported: clock enable
if we(3) = '1' then
ram(to_integer(unsigned(waddr)))(31 downto 24) <= di(31 downto 24);
end if;
if we(2) = '1' then
ram(to_integer(unsigned(waddr)))(23 downto 16) <= di(23 downto 16);
end if;
if we(1) = '1' then
ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= di(15 downto 8 );
end if;
if we(0) = '1' then
ram(to_integer(unsigned(waddr)))(7 downto 0 ) <= di(7 downto 0 );
end if;
read := ram(to_integer(unsigned(raddr)));
do <= read;
end if;
end process;
end behavioral;
| gpl-2.0 | cd2c56ced34c198d08502e8a3a88d34e | 0.626044 | 3.22504 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/CTIMER.vhd | 1 | 1,520 | -- TIMER.VHD (a peripheral module for SCOMP)
-- 2003.04.24
--
-- Timer returns a 16 bit counter value with a resolution of the CLOCK period.
-- Writing any value to timer resets to 0x0000, but the timer continues to run.
-- The counter value rolls over to 0x0000 after a clock tick at 0xFFFF.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTIMER IS
PORT(CLOCK,
RESETN,
CS : IN STD_LOGIC;
IO_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
INT : OUT STD_LOGIC );
END CTIMER;
ARCHITECTURE a OF CTIMER IS
SIGNAL COUNT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL TRIGVAL : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
-- Use value from SCOMP as trigger value
PROCESS (CS, RESETN)
BEGIN
IF RESETN = '0' THEN
TRIGVAL <= x"0000";
ELSIF RISING_EDGE(CS) THEN
TRIGVAL <= IO_DATA;
END IF;
END PROCESS;
-- Count up until reaching trigger value, then reset.
PROCESS (CLOCK, RESETN, CS)
BEGIN
IF (RESETN = '0') OR (CS = '1') THEN
COUNT <= x"0000";
ELSIF (FALLING_EDGE(CLOCK)) THEN
IF TRIGVAL = x"0000" THEN
INT <= '0';
ELSIF COUNT = TRIGVAL THEN
COUNT <= x"0001";
INT <= '1';
ELSE
COUNT <= COUNT + 1;
INT <= '0';
END IF;
END IF;
END PROCESS;
END a;
| mit | 9df89f43a3da17c89106d15987a18b81 | 0.550658 | 3.743842 | false | false | false | false |
nickg/nvc | test/regress/alias10.vhd | 1 | 1,002 | entity alias10 is
end entity;
package p is
signal s : bit_vector(1 to 3);
alias t : bit_vector(3 downto 1) is s;
end package;
use work.p.all;
architecture test of alias10 is
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL)
return BIT_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
begin
process is
variable v : bit_vector(3 downto 0);
begin
v := "0101";
assert XSLL(v, 1) = "1010";
wait for 1 ns;
v := "0011";
assert XSLL(v, 2) = "1100";
s <= "001";
wait for 1 ns;
assert t = "001";
t <= "101";
wait for 1 ns;
assert s = "101";
wait;
end process;
end architecture;
| gpl-3.0 | d1c92ed54e58d6019a73b0ba96f21906 | 0.550898 | 3.408163 | false | false | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn05.vhdl | 1 | 524 | entity tb_asgn05 is
end tb_asgn05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn05 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (5 downto 0);
begin
dut: entity work.asgn05
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
s1 <= '0';
wait for 1 ns;
assert r = "000000" severity failure;
s0 <= '1';
s1 <= '0';
wait for 1 ns;
assert r = "010110" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 5e35e6e344c3b9e595b14c9468d9dbd2 | 0.597328 | 2.927374 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/assert_uut.vhd | 2 | 9,795 | --test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity assert_uut is
port(
clock : in std_logic;
reset : in std_logic;
context_uut : in context_t;
en_feed : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : out std_logic;
stdin_data : out stdin_vector;
en_check : in std_logic;
stdout_rdy : in std_logic;
stdout_ack : out std_logic;
stdout_data : in stdout_vector;
vecs_found : out std_logic;
vec_read : out std_logic;
n_error : out std_logic
);
end assert_uut;
architecture rtl of assert_uut is
type vin_table is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
constant input_vectors_1 : vin_table := (
--##INPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"00_00_00_a3",
1 => x"00_00_00_ea",
2 => x"00_00_00_cc",
3 => x"00_00_00_28",
4 => x"00_00_00_30",
5 => x"00_00_00_a0",
6 => x"00_00_00_c0",
7 => x"00_00_00_80",
8 => x"00_00_00_00",
9 => x"00_00_00_00",
10 => x"00_00_00_00",
11 => x"00_00_00_00",
12 => x"00_00_00_00",
13 => x"00_00_00_00",
14 => x"00_00_00_00",
15 => x"00_00_00_00",
16 => x"00_00_00_00",
17 => x"00_00_00_00",
18 => x"00_00_00_00",
19 => x"00_00_00_00",
20 => x"00_00_00_00",
21 => x"00_00_00_00",
22 => x"00_00_00_00",
23 => x"00_00_00_00",
24 => x"00_00_00_00",
25 => x"00_00_00_00",
26 => x"00_00_00_00",
27 => x"00_00_00_00",
28 => x"00_00_00_00",
29 => x"00_00_00_00",
30 => x"00_00_00_00",
31 => x"00_00_00_00",
32 => x"00_00_00_00",
33 => x"00_00_00_00",
34 => x"00_00_00_00",
35 => x"00_00_00_00",
36 => x"00_00_00_00",
37 => x"00_00_00_00",
38 => x"00_00_00_00",
39 => x"00_00_00_00",
40 => x"00_00_00_00",
41 => x"00_00_00_00",
42 => x"00_00_00_00",
43 => x"00_00_00_00",
44 => x"00_00_00_00",
45 => x"00_00_00_00",
46 => x"00_00_00_00",
47 => x"00_00_00_00",
48 => x"00_00_00_00",
49 => x"00_00_00_00",
50 => x"00_00_00_00",
51 => x"00_00_00_00",
52 => x"00_00_00_00",
53 => x"00_00_00_00",
54 => x"00_00_00_00",
55 => x"00_00_00_00",
56 => x"00_00_00_00",
57 => x"00_00_00_00",
58 => x"00_00_00_00",
59 => x"00_00_00_00",
60 => x"00_00_00_00",
61 => x"00_00_00_00",
62 => x"00_00_00_00",
63 => x"00_00_00_00",
--##INPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_1 : vout_table := (
--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"ff",
1 => x"00",
2 => x"ff",
3 => x"ff",
4 => x"00",
5 => x"00",
6 => x"ff",
7 => x"00",
8 => x"ff",
9 => x"00",
10 => x"ff",
11 => x"ff",
12 => x"00",
13 => x"00",
14 => x"ff",
15 => x"00",
16 => x"ff",
17 => x"00",
18 => x"ff",
19 => x"ff",
20 => x"00",
21 => x"00",
22 => x"ff",
23 => x"00",
24 => x"ff",
25 => x"00",
26 => x"ff",
27 => x"ff",
28 => x"00",
29 => x"00",
30 => x"ff",
31 => x"00",
32 => x"ff",
33 => x"00",
34 => x"ff",
35 => x"ff",
36 => x"00",
37 => x"00",
38 => x"ff",
39 => x"00",
40 => x"ff",
41 => x"00",
42 => x"ff",
43 => x"ff",
44 => x"00",
45 => x"00",
46 => x"ff",
47 => x"00",
48 => x"ff",
49 => x"00",
50 => x"ff",
51 => x"ff",
52 => x"00",
53 => x"00",
54 => x"ff",
55 => x"00",
56 => x"ff",
57 => x"00",
58 => x"ff",
59 => x"ff",
60 => x"00",
61 => x"00",
62 => x"ff",
63 => x"00",
--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant input_vectors_2 : vin_table := (
--##INPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"00_00_00_a3",
1 => x"00_00_00_ea",
2 => x"00_00_00_cc",
3 => x"00_00_00_28",
4 => x"00_00_00_30",
5 => x"00_00_00_a0",
6 => x"00_00_00_c0",
7 => x"00_00_00_80",
8 => x"00_00_00_00",
9 => x"00_00_00_00",
10 => x"00_00_00_00",
11 => x"00_00_00_00",
12 => x"00_00_00_00",
13 => x"00_00_00_00",
14 => x"00_00_00_00",
15 => x"00_00_00_00",
16 => x"00_00_00_00",
17 => x"00_00_00_00",
18 => x"00_00_00_00",
19 => x"00_00_00_00",
20 => x"00_00_00_00",
21 => x"00_00_00_00",
22 => x"00_00_00_00",
23 => x"00_00_00_00",
24 => x"00_00_00_00",
25 => x"00_00_00_00",
26 => x"00_00_00_00",
27 => x"00_00_00_00",
28 => x"00_00_00_00",
29 => x"00_00_00_00",
30 => x"00_00_00_00",
31 => x"00_00_00_00",
32 => x"00_00_00_00",
33 => x"00_00_00_00",
34 => x"00_00_00_00",
35 => x"00_00_00_00",
36 => x"00_00_00_00",
37 => x"00_00_00_00",
38 => x"00_00_00_00",
39 => x"00_00_00_00",
40 => x"00_00_00_00",
41 => x"00_00_00_00",
42 => x"00_00_00_00",
43 => x"00_00_00_00",
44 => x"00_00_00_00",
45 => x"00_00_00_00",
46 => x"00_00_00_00",
47 => x"00_00_00_00",
48 => x"00_00_00_00",
49 => x"00_00_00_00",
50 => x"00_00_00_00",
51 => x"00_00_00_00",
52 => x"00_00_00_00",
53 => x"00_00_00_00",
54 => x"00_00_00_00",
55 => x"00_00_00_00",
56 => x"00_00_00_00",
57 => x"00_00_00_00",
58 => x"00_00_00_00",
59 => x"00_00_00_00",
60 => x"00_00_00_00",
61 => x"00_00_00_00",
62 => x"00_00_00_00",
63 => x"00_00_00_00",
--##INPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_2 : vout_table := (
--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"ff",
1 => x"00",
2 => x"ff",
3 => x"ff",
4 => x"00",
5 => x"00",
6 => x"ff",
7 => x"00",
8 => x"ff",
9 => x"00",
10 => x"ff",
11 => x"ff",
12 => x"00",
13 => x"00",
14 => x"ff",
15 => x"00",
16 => x"ff",
17 => x"00",
18 => x"ff",
19 => x"ff",
20 => x"00",
21 => x"00",
22 => x"ff",
23 => x"00",
24 => x"ff",
25 => x"00",
26 => x"ff",
27 => x"ff",
28 => x"00",
29 => x"00",
30 => x"ff",
31 => x"00",
32 => x"ff",
33 => x"00",
34 => x"ff",
35 => x"ff",
36 => x"00",
37 => x"00",
38 => x"ff",
39 => x"00",
40 => x"ff",
41 => x"00",
42 => x"ff",
43 => x"ff",
44 => x"00",
45 => x"00",
46 => x"ff",
47 => x"00",
48 => x"ff",
49 => x"00",
50 => x"ff",
51 => x"ff",
52 => x"00",
53 => x"00",
54 => x"ff",
55 => x"00",
56 => x"ff",
57 => x"00",
58 => x"ff",
59 => x"ff",
60 => x"00",
61 => x"00",
62 => x"ff",
63 => x"00",
--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
signal in_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal in_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal stdin_ack_sig : std_logic;
signal vector_read : std_logic;
begin
feed : process(reset, clock) is
begin
if (reset = '1') then
in_vec_counter_1 <= (others => '0');
in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
elsif rising_edge(clock) then
case context_uut is
when "01" =>
if (en_feed = '1') then
stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_1 <= in_vec_counter_1 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_1 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when "10" =>
if (en_feed = '1') then
stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_2 <= in_vec_counter_2 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when others =>
end case;
end if;
end process feed;
check : process(reset, clock) is
begin
if (reset = '1') then
n_error <= '1';
vec_read <= '0';
elsif rising_edge(clock) then
vec_read <= '0';
if (en_check = '1') then
if (stdout_rdy = '1') then
vec_read <= '1';
case context_uut is
when "01" =>
assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
n_error <= '0';
end if;
when "10" =>
assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
n_error <= '0';
end if;
when others =>
end case;
end if;
end if;
end if;
end process check;
read_counter : process(reset, clock) is
begin
if (reset = '1') then
out_vec_counter_1 <= (others => '0');
out_vec_counter_2 <= (others => '0');
elsif rising_edge(clock) then
if (en_check = '1') then
if (stdout_rdy = '1') then
case context_uut is
when "01" =>
out_vec_counter_1 <= out_vec_counter_1 + 1;
when "10" =>
out_vec_counter_2 <= out_vec_counter_2 + 1;
when others =>
end case;
end if;
--else
-- case context_uut is
-- when "01" =>
-- out_vec_counter_1 <= (others => '0');
-- when "10" =>
-- out_vec_counter_2 <= (others => '0');
-- when others =>
-- end case;
end if;
end if;
end process read_counter;
--asynchronous declarations
stdout_ack <= en_check;
stdin_ack <= stdin_ack_sig;
vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
end rtl;
| gpl-2.0 | 43a456e02b5134ac8c658abbd5dd8d3f | 0.486269 | 2.145204 | false | false | false | false |
nickg/nvc | test/regress/signal25.vhd | 1 | 422 | entity signal25 is
end entity;
architecture test of signal25 is
type rec is record
f : bit_vector;
end record;
signal v : bit_vector(1 to 3);
signal r : rec(f(1 to 2));
begin
v(1 to r.f'right) <= (others => '1');
v(r.f'right + 1 to 3) <= (others => '0');
check: process is
begin
wait for 1 ns;
assert v = "110";
wait;
end process;
end architecture;
| gpl-3.0 | 97bd9968ba955aa2f7bab79f61985337 | 0.549763 | 3.271318 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/LFSR/tb_lfsr.vhd | 1 | 4,435 | -------------------------------------------------------------------------------------
-- FILE NAME : testbench_template.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - testbench_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- This entity is template for writing test benches
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--Library UNISIM;
-- use UNISIM.vcomponents.all;
--Library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_lfsr is
end tb_lfsr;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_lfsr is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_10_MHZ : time := 100 ns;
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_368_MHZ : time := 2.7126 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
type bus064 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
type bus016 is array(natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal clk200 : std_logic := '1';
signal clk100 : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal rst_rstin : std_logic_vector(31 downto 0) := (others=>'1');
signal clk_clkin : std_logic_vector(31 downto 0) := (others=>'1');
signal reg0_out : std_logic_vector(2 downto 0);
signal reg1_out : std_logic_vector(2 downto 0);
signal reg2_out : std_logic_vector(2 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
clk200 <= not clk200 after CLK_200_MHZ / 2;
clk100 <= not clk100 after CLK_100_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 10;
rst_rstin <= (0=>rst, 1 => rst, 2=> rst, others =>'0');
clk_clkin <= (13 => clk200, 14 => clk100, others=>clk);
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
uut: entity work.LFSR_0
generic map (
WIDTH => 3
)
port map (
clk_in => clk,
rst_in => rst,
reg_out => reg0_out
);
uut0: entity work.lfsr_internal
generic map (
WIDTH => 3
)
port map (
clk_in => clk,
rst_in => rst,
reg_out => reg1_out
);
uut1: entity work.lfsr_external
generic map (
WIDTH => 3
)
port map (
clk_in => clk,
rst_in => rst,
reg_out => reg2_out
);
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 1bd6062b02430ea4a0112d844b1e97c1 | 0.371815 | 4.763695 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_maxcode.vhd | 2 | 1,460 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_dhuff_tbl_maxcode;
architecture augh of p_jinfo_dc_dhuff_tbl_maxcode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | d6f8e5d01ba04f90b9bf0b8ab579d4a8 | 0.676712 | 2.874016 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_doHistStretch_0_0/synth/design_1_doHistStretch_0_0.vhd | 1 | 13,233 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHistStretch:1.0
-- IP Revision: 1606210026
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHistStretch_0_0 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doHistStretch_0_0;
ARCHITECTURE design_1_doHistStretch_0_0_arch OF design_1_doHistStretch_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT doHistStretch IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doHistStretch;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "doHistStretch,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doHistStretch_0_0_arch : ARCHITECTURE IS "design_1_doHistStretch_0_0,doHistStretch,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doHistStretch
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doHistStretch_0_0_arch;
| gpl-3.0 | 51808e7e86053352c88c35bdf352f7b7 | 0.714124 | 3.381804 | false | false | false | false |
nickg/nvc | test/parse/error7.vhd | 1 | 426 | package error7 is
type foo is (a, b, c);
function "=" (l, r : foo) return boolean;
constant foo : integer := 1; -- Error
end package;
package body error7 is -- Error
constant k : boolean := a = b; -- Error (suppressed)
end package body;
use work.error7.all; -- Error
package other is
constant x : integer := bad; -- Error (suppressed)
end package;
| gpl-3.0 | 49934c695821fcd5604733e83388bc0d | 0.556338 | 3.769912 | false | false | false | false |
nickg/nvc | test/bounds/issue54.vhd | 1 | 448 | entity issue54 is
begin
end entity issue54;
architecture a of issue54 is
begin
p : process
variable v : bit_vector(7 downto 0) := (others => '0');
begin
v(3 downto 0) := (7 downto 4 => '1'); -- Error
v(7 downto 4) := (3 downto 0 => '1'); -- Error
v(7 downto 4) := (3 downto 0 => '1', others => '0'); -- Error
assert (v = (7 downto 0 => '1'));
wait;
end process p;
end architecture a;
| gpl-3.0 | d262e82995a81ce746d148aa66e111ea | 0.522321 | 3.294118 | false | false | false | false |
nickg/nvc | test/regress/vests13.vhd | 1 | 6,610 | -- -*- vhdl-basic-offset: 2 -*-
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1363.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests13 IS
END vests13;
ARCHITECTURE c08s05b00x00p03n01i01363arch OF vests13 IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
--
BEGIN
assert c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) = c_st_arr1_2;
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2));
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01363"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01363 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01363arch;
| gpl-3.0 | 605c42df447ee3d2b76f80c9c0596843 | 0.581392 | 2.931264 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue301/src/ram_ctrl.vhd | 7 | 16,387 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Viterbi decoder RAM control
--! @author Markus Fehrenz
--! @date 2011/12/13
--!
--! @details Manage RAM behavior. Write and read data.
--! The decisions are sent to the traceback units
--! It is signaled if the data belongs to acquisition or window phase.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
use dec_viterbi.pkg_components.all;
entity ram_ctrl is
port(
clk : in std_logic;
rst : in std_logic;
--
-- Slave data signals, delivers the LLR parity values.
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Master data signals for traceback units, delivers the decision vectors.
--
m_axis_output_tvalid : out std_logic_vector(1 downto 0);
m_axis_output_tdata : out t_ram_rd_data;
m_axis_output_tlast : out std_logic_vector(1 downto 0);
m_axis_output_tready : in std_logic_vector(1 downto 0);
-- Signals the traceback unit when the decision bits do not belong to an acquisition.
m_axis_output_window_tuser : out std_logic_vector(1 downto 0);
-- Signals whether this is the last decision vector of the window.
m_axis_output_last_tuser : out std_logic_vector(1 downto 0);
--
-- Slave configuration signals, delivering the configuration data.
--
s_axis_ctrl_tvalid : in std_logic;
s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
s_axis_ctrl_tready : out std_logic
);
end entity ram_ctrl;
architecture rtl of ram_ctrl is
------------------------
-- Type definition
------------------------
--
-- Record contains runtime configuration.
-- The input configuration is stored in a register.
-- It is received from a AXI4-Stream interface from the top entity.
--
type trec_runtime_param is record
window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
end record trec_runtime_param;
-- Types for finite state machines
type t_write_ram_fsm is (CONFIGURE, START, RUN, WAIT_FOR_TRACEBACK, WAIT_FOR_LAST_TRACEBACK);
type t_read_ram_fsm is (WAIT_FOR_WINDOW, TRACEBACK, WAIT_FOR_RAM, FINISH);
type t_read_ram_fsm_array is array (0 to 1) of t_read_ram_fsm;
-- RAM controling types
type t_ram_data is array (3 downto 0) of std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
type t_ram_addr is array (3 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
type t_ram_rd_addr is array (1 downto 0) of unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
type t_ram_ptr is array (1 downto 0) of unsigned(1 downto 0);
type t_ram_ptr_int is array (1 downto 0) of integer range 3 downto 0;
type t_ram_data_cnt is array (1 downto 0) of integer range 2 * MAX_WINDOW_LENGTH downto 0;
------------------------
-- Signal declaration
------------------------
signal ram_buffer : t_ram_rd_data;
signal ram_buffer_full : std_logic_vector(1 downto 0);
signal config : trec_runtime_param;
signal write_ram_fsm : t_write_ram_fsm;
signal read_ram_fsm : t_read_ram_fsm_array;
signal wen_ram : std_logic_vector(3 downto 0);
signal addr : t_ram_addr;
signal q_reg : t_ram_data;
-- ram addess, number and data pointer
signal write_ram_ptr : unsigned(1 downto 0);
signal read_ram_ptr : t_ram_ptr;
signal read_ram_ptr_d : t_ram_ptr;
signal write_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
signal read_addr_ptr : t_ram_rd_addr;
-- internal signals of outputs
signal m_axis_output_tvalid_int : std_logic_vector(1 downto 0);
signal m_axis_output_tlast_int : std_logic_vector(1 downto 0);
signal m_axis_output_window_tuser_int : std_logic_vector(1 downto 0);
signal m_axis_output_last_tuser_int : std_logic_vector(1 downto 0);
signal s_axis_input_tready_int : std_logic;
signal s_axis_ctrl_tready_int : std_logic;
signal next_traceback : std_logic_vector(1 downto 0);
signal write_window_complete : std_logic;
signal write_last_window_complete : std_logic;
signal last_of_block : std_logic;
signal read_last_addr_ptr : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
begin
m_axis_output_tvalid <= m_axis_output_tvalid_int;
m_axis_output_tlast <= m_axis_output_tlast_int;
m_axis_output_window_tuser <= m_axis_output_window_tuser_int;
m_axis_output_last_tuser <= m_axis_output_last_tuser_int;
m_axis_output_tdata(0) <= q_reg(to_integer(read_ram_ptr_d(0))) when ram_buffer_full(0) = '0' else ram_buffer(0);
m_axis_output_tdata(1) <= q_reg(to_integer(read_ram_ptr_d(1))) when ram_buffer_full(1) = '0' else ram_buffer(1);
--
-- When the output port is not ready to read the output of the RAM immediately
-- we have to remember the output value of the RAM in an extra register.
-- When the output is ready to read, we first use the ouput of the register
-- and only then the output of the RAM again.
--
pr_buf_ram_output: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
ram_buffer <= (others => (others => '0'));
ram_buffer_full <= (others => '0');
else
for i in 0 to 1 loop
if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '0' and ram_buffer_full(i) = '0' then
ram_buffer(i) <= q_reg(to_integer(read_ram_ptr_d(i)));
ram_buffer_full(i) <= '1';
end if;
if m_axis_output_tvalid_int(i) = '1' and m_axis_output_tready(i) = '1' and ram_buffer_full(i) = '1' then
ram_buffer_full(i) <= '0';
end if;
end loop;
end if;
end if;
end process pr_buf_ram_output;
-----------------------------
-- Manage writing from ACS --
-----------------------------
s_axis_input_tready_int <= '0' when (write_ram_fsm = CONFIGURE) or
(write_ram_ptr = read_ram_ptr(0) and read_ram_fsm(0) /= WAIT_FOR_WINDOW) or
(write_ram_ptr = read_ram_ptr(1) and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or
write_ram_fsm = WAIT_FOR_TRACEBACK or write_ram_fsm = WAIT_FOR_LAST_TRACEBACK else
'1';
s_axis_input_tready <= s_axis_input_tready_int;
s_axis_ctrl_tready_int <= '1' when (read_ram_fsm(0) = WAIT_FOR_WINDOW and read_ram_fsm(1) = WAIT_FOR_WINDOW and write_ram_fsm = CONFIGURE) else
'0';
s_axis_ctrl_tready <= s_axis_ctrl_tready_int;
-- Process for writing to the RAM
pr_write_ram: process(clk) is
variable v_window_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
variable v_acquisition_length : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
write_ram_fsm <= CONFIGURE;
write_addr_ptr <= (others => '0');
write_ram_ptr <= (others => '0');
wen_ram <= (others => '0');
write_window_complete <= '0';
write_last_window_complete <= '0';
read_last_addr_ptr <= (others => '0');
else
case write_ram_fsm is
--
-- It is necessary to configure the decoder before each block
--
when CONFIGURE =>
write_window_complete <= '0';
write_last_window_complete <= '0';
if s_axis_ctrl_tvalid = '1' and s_axis_ctrl_tready_int = '1' then
v_window_length := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 + 16 downto 16));
v_acquisition_length := unsigned(s_axis_ctrl_tdata(BW_MAX_WINDOW_LENGTH - 1 downto 0));
write_addr_ptr <= v_window_length - v_acquisition_length;
config.window_length <= v_window_length;
config.acquisition_length <= v_acquisition_length;
write_ram_fsm <= START;
wen_ram(to_integer(write_ram_ptr)) <= '1';
end if;
--
-- After the decoder is configured, the decoder is waiting for a new block.
-- When the AXIS handshake is there the packet transmission begins.
-- The first write is a special case, since writing data starts at the acquisition length.
-- There is no complete window available afterwards.
--
when START =>
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
if write_addr_ptr = config.window_length - 1 then
-- When we switch to the next RAM, we reset the write addr.
write_addr_ptr <= (others => '0');
-- Switch to the next RAM.
write_ram_ptr <= write_ram_ptr + 1;
wen_ram(to_integer(write_ram_ptr)) <= '0';
wen_ram(to_integer(write_ram_ptr + 1)) <= '1';
write_ram_fsm <= RUN;
else
write_addr_ptr <= write_addr_ptr + 1;
end if;
end if;
--
-- The decoder is receiving data from the ACS.
--
when RUN =>
write_window_complete <= '0';
write_last_window_complete <= '0';
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
write_addr_ptr <= write_addr_ptr + 1;
if write_addr_ptr = config.window_length - 1 then
-- When we switch to the next RAM, we reset the write addr.
write_addr_ptr <= (others => '0');
-- Switch to the next RAM.
write_ram_ptr <= write_ram_ptr + 1;
wen_ram(to_integer(write_ram_ptr)) <= '0';
wen_ram(to_integer(write_ram_ptr + 1)) <= '1';
-- Indicate, that a complete window is within the RAM and traceback may start.
write_window_complete <= '1';
if read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW then
write_ram_fsm <= WAIT_FOR_TRACEBACK;
end if;
else
write_addr_ptr <= write_addr_ptr + 1;
end if;
if s_axis_input_tlast = '1' then
write_ram_fsm <= CONFIGURE;
wen_ram <= (others => '0');
write_last_window_complete <= '1';
if (read_ram_fsm(0) /= WAIT_FOR_WINDOW and read_ram_fsm(1) /= WAIT_FOR_WINDOW) or write_window_complete = '1' then
write_ram_fsm <= WAIT_FOR_LAST_TRACEBACK;
end if;
read_last_addr_ptr <= write_addr_ptr;
write_addr_ptr <= (others => '0');
write_ram_ptr <= write_ram_ptr + 1;
end if;
end if;
when WAIT_FOR_TRACEBACK =>
if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then
write_ram_fsm <= RUN;
write_window_complete <= '0';
end if;
when WAIT_FOR_LAST_TRACEBACK =>
if read_ram_fsm(0) = WAIT_FOR_WINDOW or read_ram_fsm(1) = WAIT_FOR_WINDOW then
write_ram_fsm <= CONFIGURE;
write_last_window_complete <= '0';
end if;
end case;
end if;
end if;
end process pr_write_ram;
-------------------------------------------
-- Manage reading from RAM for traceback --
-------------------------------------------
gen_read_ram: for i in 0 to 1 generate
pr_read_ram: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
read_addr_ptr(i) <= (others => '0');
read_ram_fsm(i) <= WAIT_FOR_WINDOW;
m_axis_output_tvalid_int(i) <= '0';
m_axis_output_tlast_int(i) <= '0';
m_axis_output_window_tuser_int(i) <= '0';
m_axis_output_last_tuser_int(i) <= '0';
read_ram_ptr(i) <= (others => '0');
read_ram_ptr_d(i) <= (others => '0');
else
read_ram_ptr_d(i) <= read_ram_ptr(i);
case read_ram_fsm(i) is
-- Wait for the next window to be ready within the RAM.
when WAIT_FOR_WINDOW =>
read_addr_ptr(i) <= config.window_length - 1;
m_axis_output_tlast_int(i) <= '0';
m_axis_output_tvalid_int(i) <= '0';
m_axis_output_last_tuser_int(i) <= '0';
m_axis_output_window_tuser_int(i) <= '0';
read_ram_ptr(i) <= write_ram_ptr;
-- We always start from the RAM, which was written last.
if write_window_complete = '1' and next_traceback(i) = '1' then
read_ram_ptr(i) <= write_ram_ptr - 1;
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
read_ram_fsm(i) <= TRACEBACK;
m_axis_output_tvalid_int(i) <= '1';
end if;
if write_last_window_complete = '1' and next_traceback(i) = '1' then
read_ram_ptr(i) <= write_ram_ptr - 1;
read_addr_ptr(i) <= read_last_addr_ptr;
read_ram_fsm(i) <= TRACEBACK;
m_axis_output_window_tuser_int(i) <= '1';
end if;
-- Perform the Traceback on the RAM data of the first RAM we need for acquisition and traceback.
when TRACEBACK =>
m_axis_output_tlast_int(i) <= '0';
m_axis_output_last_tuser_int(i) <= '0';
m_axis_output_tvalid_int(i) <= '1';
if m_axis_output_tready(i) = '1' then
if read_addr_ptr(i) = 0 then
if read_ram_fsm(1 - i) = TRACEBACK and read_ram_ptr(1 - i) = read_ram_ptr(i) - 1 then
read_ram_fsm(i) <= WAIT_FOR_RAM;
else
read_addr_ptr(i) <= config.window_length - 1;
read_ram_ptr(i) <= read_ram_ptr(i) - 1;
read_ram_fsm(i) <= FINISH;
end if;
else
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
end if;
-- Signal the traceback unit, acquisition is over.
if read_addr_ptr(i) = config.window_length - config.acquisition_length - 1 then
m_axis_output_window_tuser_int(i) <= '1';
end if;
end if;
when WAIT_FOR_RAM =>
m_axis_output_tvalid_int(i) <= '0';
if read_ram_fsm(1 - i) /= TRACEBACK or read_ram_ptr(1 - i) /= read_ram_ptr(i) - 1 then
read_addr_ptr(i) <= config.window_length - 1;
read_ram_ptr(i) <= read_ram_ptr(i) - 1;
read_ram_fsm(i) <= FINISH;
end if;
-- Get the remaining values from the second RAM we need for traceback (no acquisition values in this RAM)
when FINISH =>
if m_axis_output_tvalid_int(i) <= '0' then
m_axis_output_tvalid_int(i) <= '1';
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
end if;
if m_axis_output_tready(i) = '1' then
if read_addr_ptr(i) = config.window_length - config.acquisition_length then
m_axis_output_last_tuser_int(i) <= '1';
read_addr_ptr(i) <= config.window_length - 1;
read_ram_fsm(i) <= WAIT_FOR_WINDOW;
-- Check if the other read process finished processing.
if read_ram_fsm((i+1) mod 2) = WAIT_FOR_WINDOW and last_of_block = '1' then
m_axis_output_tlast_int(i) <= '1';
end if;
else
read_addr_ptr(i) <= read_addr_ptr(i) - 1;
end if;
end if;
end case;
end if;
end if;
end process pr_read_ram;
end generate gen_read_ram;
-- This process decides which traceback unit is the next one to use.
pr_next_traceback: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
next_traceback <= "01";
last_of_block <= '0';
else
if write_window_complete = '1' then
if next_traceback(0) = '1' then
next_traceback(0) <= '0';
next_traceback(1) <= '1';
else
next_traceback(0) <= '1';
next_traceback(1) <= '0';
end if;
end if;
if s_axis_input_tlast = '1' then
last_of_block <= '1';
end if;
end if;
end if;
end process pr_next_traceback;
------------------------------
--- Portmapping components ---
------------------------------
gen_generic_sp_ram : for i in 0 to 3 generate
begin
addr(i) <= write_addr_ptr when (write_ram_fsm = RUN or write_ram_fsm = START) and to_integer(write_ram_ptr) = i else
read_addr_ptr(0) when (to_integer(read_ram_ptr(0)) = i and (read_ram_fsm(0) = TRACEBACK or read_ram_fsm(0) = WAIT_FOR_RAM or read_ram_fsm(0) = FINISH)) or
(next_traceback(0) = '1' and write_window_complete = '1' and to_integer(read_ram_ptr(0)) = i) else
read_addr_ptr(1);
inst_generic_sp_ram : generic_sp_ram
generic map(
DISTR_RAM => DISTRIBUTED_RAM,
WORDS => MAX_WINDOW_LENGTH,
BITWIDTH => NUMBER_TRELLIS_STATES
)
port map(
clk => clk,
rst => rst,
wen => wen_ram(i),
en => '1',
a => std_logic_vector(addr(i)),
d => s_axis_input_tdata,
q => q_reg(i)
);
end generate gen_generic_sp_ram;
end architecture rtl;
| gpl-2.0 | bc7982958fa2da25240598294d98bcbd | 0.600659 | 2.944654 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1090/tb_simple_ram.vhdl | 1 | 1,062 | entity tb_simple_ram is
end tb_simple_ram;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_simple_ram is
signal raddr : std_logic_vector(5 downto 0);
signal rdat : std_logic_vector(31 downto 0);
signal en : std_logic;
signal waddr : std_logic_vector(5 downto 0);
signal wdat : std_logic_vector(31 downto 0);
signal we : std_logic_vector (3 downto 0);
signal clk : std_logic;
begin
dut: entity work.simple_ram
port map (clk => clk,
en => en, raddr => raddr, do => rdat,
we => we, waddr => waddr, di => wdat);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en <= '1';
raddr <= "000000";
we <= "0000";
waddr <= "000001";
wdat <= x"00_00_00_01";
pulse;
assert rdat = x"0000_0110" severity failure;
raddr <= "000001";
waddr <= "000010";
wdat <= x"00_00_00_02";
pulse;
assert rdat = x"0000_1ffc" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | b841a697e4b5cc0edbffc2d1219e1c8b | 0.584746 | 3.329154 | false | false | false | false |
nickg/nvc | test/regress/array8.vhd | 1 | 2,178 | -- Test case from Brian Padalino
--
package p1 is
type t_byte_endianness is (LOWER_BYTE_LEFT, FIRST_BYTE_LEFT, LOWER_BYTE_RIGHT, FIRST_BYTE_RIGHT) ;
type t_slv_array is array(natural range <>) of bit_vector ;
subtype t_byte_array is t_slv_array(open)(7 downto 0) ;
function convert_byte_array_to_slv(
constant byte_array : t_byte_array ;
constant byte_endianness : t_byte_endianness
) return bit_vector ;
end package ;
package body p1 is
-- example taken directly from uvvm:
-- https://github.com/UVVM/UVVM/blob/92cb1495afa007f74ed79fb9935282196420add0/uvvm_util/src/methods_pkg.vhd#L6801
function convert_byte_array_to_slv(
constant byte_array : t_byte_array;
constant byte_endianness : t_byte_endianness
) return bit_vector is
constant c_num_bytes : integer := byte_array'length;
alias normalized_byte_array : t_byte_array(0 to c_num_bytes-1) is byte_array;
variable v_slv : bit_vector(8*c_num_bytes-1 downto 0);
begin
assert byte_array'ascending report "byte_array must be ascending" severity error;
for byte_idx in 0 to c_num_bytes-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
v_slv(8*(c_num_bytes-byte_idx)-1 downto 8*(c_num_bytes-1-byte_idx)) := normalized_byte_array(byte_idx);
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
v_slv(8*(byte_idx+1)-1 downto 8*byte_idx) := normalized_byte_array(byte_idx);
end if;
end loop;
return v_slv;
end function;
end package body ;
entity array8 is end entity ;
use work.p1.all;
architecture arch of array8 is
signal s : t_byte_array(0 to 2) := ( X"44", X"55", X"66" );
begin
process
begin
assert convert_byte_array_to_slv((X"01", X"02", X"03"), LOWER_BYTE_LEFT) = X"010203";
assert convert_byte_array_to_slv((X"01", X"02", X"03"), LOWER_BYTE_RIGHT) = X"030201";
assert convert_byte_array_to_slv(s, LOWER_BYTE_LEFT) = X"445566";
assert convert_byte_array_to_slv(s, LOWER_BYTE_RIGHT) = X"665544";
std.env.stop ;
end process;
end architecture ;
| gpl-3.0 | 0b850a54f76fa752728ad05047b7eb1e | 0.651515 | 3.161103 | false | false | false | false |
snow4life/PipelinedDLX | IRAM.vhd | 1 | 1,518 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity IRAM is
generic( RAM_DEPTH: integer := 2048; -- 64 instructions
I_SIZE: integer := 32);
port( Rst: in std_logic;
Addr: in std_logic_vector(11 downto 0);
Dout: out std_logic_vector(I_SIZE - 1 downto 0));
end IRAM;
architecture IRam_Bhe of IRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0);
signal IRAM_mem : RAMtype;
begin -- IRam_Bhe
Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))),I_SIZE);
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: IRAM_mem
-- FILL_MEM_P: process (Rst)
-- file mem_fp: text;
-- variable file_line : line;
-- variable index : integer := 0;
-- variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0);
-- begin -- process FILL_MEM_P
-- if (Rst = '0') then
-- file_open(mem_fp,"test.asm.mem",READ_MODE);
-- while (not endfile(mem_fp)) loop
-- readline(mem_fp,file_line);
-- hread(file_line,tmp_data_u);
-- IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u));
-- index := index + 1;
-- end loop;
-- end if;
-- end process FILL_MEM_P;
end IRam_Bhe;
| lgpl-2.1 | 43b5bbbf4f92257261cd941a428237a7 | 0.629117 | 3.02994 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/v_split4.vhd | 2 | 1,357 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split4 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v_split4;
architecture augh of v_split4 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 8b7e2096fdb1f6073914bb075380ce11 | 0.668386 | 2.856842 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth14/repro.vhdl | 1 | 431 | library ieee;
use ieee.std_logic_1164.all;
entity repro is
port (clk : std_logic;
rst : std_logic;
o : out std_logic);
end repro;
architecture behav of repro is
signal v : natural range 0 to 3;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
v <= 0;
else
v <= v + 1;
end if;
end if;
end process;
o <= '1' when v = 0 else '0';
end behav;
| gpl-2.0 | 6b05e73415a83a15522bd3005c2aace1 | 0.556845 | 3.169118 | false | false | false | false |
nickg/nvc | test/regress/vecorder2.vhd | 1 | 1,506 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity vecorder2 is
end vecorder2;
architecture rtl of vecorder2 is
signal c_a : std_logic_vector(11 downto 0) := x"FAE";
signal c_b : std_logic_vector(11 downto 0) := x"182";
signal s_expected_vector : std_logic_vector(31 downto 0);
signal s_resulting_vector : std_logic_vector(31 downto 0);
begin
-- Compute expected value using intermediate variables for padding
expected_value : process
variable v_a_padded : std_logic_vector(15 downto 0);
variable v_b_padded : std_logic_vector(15 downto 0);
begin
v_a_padded := (15 downto 12 => c_a(11), 11 downto 0 => c_a);
v_b_padded := (15 downto 12 => c_b(11), 11 downto 0 => c_b);
s_expected_vector <= v_a_padded & v_b_padded;
wait for 1 ns;
report "Expected result " & to_hstring(s_expected_vector) severity note;
wait;
end process;
-- Perform the concatenation and the padding in 1 line
resulting_value : process
begin
s_resulting_vector <=
(15 downto 12 => c_a(11), 11 downto 0 => c_a) &
(15 downto 12 => c_b(11), 11 downto 0 => c_b);
wait for 2 ns;
report "Actual result " & to_hstring(s_resulting_vector) severity note;
wait;
end process;
checker : process
begin
wait for 3 ns;
assert s_resulting_vector = s_expected_vector severity failure;
wait;
end process;
end rtl;
| gpl-3.0 | 7b0d6467234d231193bebbd4e05a95ec | 0.61421 | 3.502326 | false | false | false | false |
makestuff/comm-fpga | ss/vhdl/tb_unit/comm_fpga_ss_tb.vhdl | 1 | 6,830 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity comm_fpga_ss_tb is
end entity;
architecture behavioural of comm_fpga_ss_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
-- Serial signals
signal serClk : std_logic;
signal serDataIn : std_logic;
signal serDataOut : std_logic;
-- Pipe signals
signal chanAddr : std_logic_vector(6 downto 0);
signal h2fData : std_logic_vector(7 downto 0);
signal h2fValid : std_logic;
signal h2fReady : std_logic;
signal f2hData : std_logic_vector(7 downto 0);
signal f2hValid : std_logic;
signal f2hReady : std_logic;
-- Pause for N serClks
procedure pause(constant n : in integer) is
variable i : integer;
begin
for i in 1 to n loop
wait until rising_edge(serClk);
end loop;
end procedure;
begin
-- Instantiate comm_fpga_ss for testing
uut: entity work.comm_fpga_ss
generic map(
FIFO_DEPTH => 1
)
port map(
clk_in => sysClk,
reset_in => '0',
-- Serial interface
serClk_in => serClk,
serData_in => serDataIn,
serData_out => serDataOut,
-- Channel read/write
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
-- Data to send
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive serClk
process
begin
serClk <= '0';
loop
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
serClk <= not(serClk);
end loop;
end process;
-- Drive the sync serial side
process
procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is
begin
if ( serDataOut = '1' ) then
wait until falling_edge(serDataOut);
wait until rising_edge(serClk);
end if;
serDataIn <= '0'; -- start bit
wait until rising_edge(serClk); serDataIn <= b(0); -- bit 0
wait until rising_edge(serClk); serDataIn <= b(1); -- bit 1
wait until rising_edge(serClk); serDataIn <= b(2); -- bit 2
wait until rising_edge(serClk); serDataIn <= b(3); -- bit 3
wait until rising_edge(serClk); serDataIn <= b(4); -- bit 4
wait until rising_edge(serClk); serDataIn <= b(5); -- bit 5
wait until rising_edge(serClk); serDataIn <= b(6); -- bit 6
wait until rising_edge(serClk); serDataIn <= b(7); -- bit 7
wait until rising_edge(serClk); serDataIn <= '1'; -- stop bit
wait until rising_edge(serClk);
end procedure;
begin
serDataIn <= '1';
pause(4);
-- Send first packet (write 63 bytes)
if ( serDataOut = '1' ) then
wait until falling_edge(serDataOut);
wait until rising_edge(serClk);
end if;
sendByte(x"00"); -- dir bit & channel
sendByte(x"00"); -- length high byte
sendByte(x"3F"); -- length low byte
sendByte(x"00"); sendByte(x"01"); sendByte(x"02"); sendByte(x"03"); sendByte(x"04"); sendByte(x"05"); sendByte(x"06"); sendByte(x"07"); sendByte(x"08"); sendByte(x"09"); sendByte(x"0A"); sendByte(x"0B"); sendByte(x"0C"); sendByte(x"0D"); sendByte(x"0E"); sendByte(x"0F");
sendByte(x"10"); sendByte(x"11"); sendByte(x"12"); sendByte(x"13"); sendByte(x"14"); sendByte(x"15"); sendByte(x"16"); sendByte(x"17"); sendByte(x"18"); sendByte(x"19"); sendByte(x"1A"); sendByte(x"1B"); sendByte(x"1C"); sendByte(x"1D"); sendByte(x"1E"); sendByte(x"1F");
sendByte(x"20"); sendByte(x"21"); sendByte(x"22"); sendByte(x"23"); sendByte(x"24"); sendByte(x"25"); sendByte(x"26"); sendByte(x"27"); sendByte(x"28"); sendByte(x"29"); sendByte(x"2A"); sendByte(x"2B"); sendByte(x"2C"); sendByte(x"2D"); sendByte(x"2E"); sendByte(x"2F");
sendByte(x"30"); sendByte(x"31"); sendByte(x"32"); sendByte(x"33"); sendByte(x"34"); sendByte(x"35"); sendByte(x"36"); sendByte(x"37"); sendByte(x"38"); sendByte(x"39"); sendByte(x"3A"); sendByte(x"3B"); sendByte(x"3C"); sendByte(x"3D"); sendByte(x"3E");
-- Send second packet (write four bytes)
if ( serDataOut = '1' ) then
wait until falling_edge(serDataOut);
wait until rising_edge(serClk);
end if;
sendByte(x"00");
sendByte(x"00"); -- length high byte
sendByte(x"04"); -- length low byte
sendByte(x"55");sendByte(x"50");sendByte(x"AA");sendByte(x"A0");
-- Send third packet (read four bytes)
if ( serDataOut = '1' ) then
wait until falling_edge(serDataOut);
wait until rising_edge(serClk);
end if;
sendByte(x"80");
sendByte(x"00"); -- length high byte
sendByte(x"10"); -- length low byte
serDataIn <= '0'; -- "I'm ready to receive"
pause(16*10);
serDataIn <= '1'; -- "I've finished receiving"
wait;
end process;
-- Drive the FPGA->Host pipe
process
procedure sendByte(constant b : in std_logic_vector(7 downto 0)) is
begin
wait until rising_edge(f2hReady);
f2hData <= b;
f2hValid <= '1';
wait until falling_edge(f2hReady);
f2hData <= (others => 'X');
f2hValid <= '0';
end procedure;
begin
f2hData <= (others => 'X');
f2hValid <= '0';
sendByte(x"01");
sendByte(x"02");
sendByte(x"03");
sendByte(x"04");
sendByte(x"05");
sendByte(x"06");
sendByte(x"07");
sendByte(x"08");
sendByte(x"09");
sendByte(x"0a");
sendByte(x"0b");
sendByte(x"0c");
sendByte(x"0d");
sendByte(x"0e");
sendByte(x"0f");
sendByte(x"10");
sendByte(x"11");
sendByte(x"12");
sendByte(x"13");
sendByte(x"14");
wait;
end process;
-- Drive the sync serial side
process
begin
h2fReady <= '0';
wait for 20 us;
h2fReady <= '1';
wait;
end process;
end architecture;
| gpl-3.0 | f5c8dc62ccfbfda27e0472ba4d6f3bb9 | 0.64612 | 2.992989 | false | false | false | false |
nickg/nvc | test/regress/conv4.vhd | 1 | 1,831 | package pack is
type int_vector is array (natural range <>) of natural;
function spread_ints (x : integer) return int_vector;
end package;
package body pack is
function spread_ints (x : integer) return int_vector is
variable r : int_vector(1 to 5);
begin
for i in 1 to 5 loop
r(i) := x;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( o1 : out int_vector(1 to 5);
i1 : in integer;
i2 : in int_vector(1 to 5) );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = 0;
assert i2 = (1 to 5 => 0);
o1 <= (1, 2, 3, 4, 5);
wait for 1 ns;
assert i1 = 150;
assert i2 = (1 to 5 => 42);
o1(1) <= 10;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv4 is
end entity;
use work.pack.all;
architecture test of conv4 is
signal x : integer;
signal y : int_vector(1 to 5);
signal q : natural;
function sum_ints(v : in int_vector) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
begin
uut: entity work.sub
port map ( sum_ints(o1) => x,
i1 => sum_ints(y),
i2 => spread_ints(q) );
p2: process is
begin
assert x = 0;
y <= (10, 20, 30, 40, 50);
q <= 42;
wait for 1 ns;
assert x = 15;
wait for 1 ns;
assert x = 24;
wait;
end process;
end architecture;
| gpl-3.0 | 2d22f3802361ec0d449e164feb9127b6 | 0.479519 | 3.79089 | false | false | false | false |
nickg/nvc | test/jit/issue496.vhd | 1 | 283 | package genpack is
generic ( type t; n : t );
constant k : t := n;
end package;
package issue496 is
constant one : string := "one";
package gen_one is new work.genpack generic map ( t => string, n => one );
constant c : string(1 to 3) := gen_one.k;
end package;
| gpl-3.0 | bc28855be862c16eed1afb3f97a59a34 | 0.614841 | 3.369048 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth39/tb_rec2.vhdl | 1 | 1,486 | entity tb_rec2 is
end tb_rec2;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_rec2 is
signal clk : std_logic;
signal sl_in : std_logic;
signal slv_in : std_logic_vector(7 downto 0);
signal int_in : integer range 0 to 15;
signal usig_in : unsigned(7 downto 0);
signal sl_out : std_logic;
signal slv_out : std_logic_vector(7 downto 0);
signal int_out : integer range 0 to 15;
signal usig_out : unsigned(7 downto 0);
begin
dut: entity work.rec2
port map (
clk => clk,
sl_in => sl_in,
slv_in => slv_in,
int_in => int_in,
usig_in => usig_in,
sl_out => sl_out,
slv_out => slv_out,
int_out => int_out,
usig_out => usig_out);
process
begin
clk <= '0';
sl_in <= '1';
slv_in <= x"12";
int_in <= 13;
usig_in <= x"d5";
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert sl_out = '1' severity failure;
assert slv_out = x"12" severity failure;
assert int_out = 13 severity failure;
assert usig_out = x"d5" severity failure;
sl_in <= '0';
slv_in <= x"9b";
int_in <= 3;
usig_in <= x"72";
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert sl_out = '0' severity failure;
assert slv_out = x"9b" severity failure;
assert int_out = 3 severity failure;
assert usig_out = x"72" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | f58b34e71551e820f6c94e0e7e1f4379 | 0.565949 | 3.00202 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_check_data/fifo_64_in_out/sim/fifo_64in_out.vhd | 1 | 33,565 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY fifo_64in_out IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END fifo_64in_out;
ARCHITECTURE fifo_64in_out_arch OF fifo_64in_out IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_64in_out_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "virtex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 12,
C_RD_DEPTH => 4096,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 12,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
rd_data_count => rd_data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_64in_out_arch;
| mit | 065a3bfd1a039b44211c7efc394e866b | 0.60715 | 3.071468 | false | false | false | false |
nickg/nvc | test/regress/record20.vhd | 1 | 479 | entity record20 is
end entity;
architecture test of record20 is
type rec is record
x : bit_vector(7 downto 0);
end record;
signal s : rec;
signal t : bit_vector(3 downto 0);
begin
p1: t <= s.x(5 downto 2);
main: process is
begin
s <= ( x => X"ff" );
wait for 1 ns;
assert t = X"f";
s.x(7 downto 4) <= X"0";
wait for 1 ns;
assert t = "0011";
wait;
end process;
end architecture;
| gpl-3.0 | b9d0f727ec1c9206ab70b4d6fffcac72 | 0.524008 | 3.373239 | false | false | false | false |
nickg/nvc | test/regress/vests1.vhd | 1 | 50,338 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc520.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00520pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00520pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP -- i: st_ind3 (character)
FOR j IN res'RANGE(2) loop -- j: st_ind2 (integer)
FOR k IN res'RANGE(3) loop -- k: st_ind1 (integer)
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00520pkg;
USE work.c03s03b00x00p03n04i00520pkg.ALL;
ENTITY vests1 IS
END vests1;
ARCHITECTURE c03s03b00x00p03n04i00520arch OF vests1 IS
--
-- Access type declarations
--
TYPE at_usa1_1 IS ACCESS t_usa1_1 ;
TYPE at_usa1_2 IS ACCESS t_usa1_2 ;
TYPE at_usa1_3 IS ACCESS t_usa1_3 ;
TYPE at_usa1_4 IS ACCESS t_usa1_4 ;
TYPE at_csa1_1 IS ACCESS t_csa1_1 ;
TYPE at_csa1_2 IS ACCESS t_csa1_2 ;
TYPE at_csa1_3 IS ACCESS t_csa1_3 ;
TYPE at_csa1_4 IS ACCESS t_csa1_4 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_usa1_1 : at_usa1_1 ;
VARIABLE AV2_usa1_1 : at_usa1_1 ;
VARIABLE AV0_usa1_2 : at_usa1_2 ;
VARIABLE AV2_usa1_2 : at_usa1_2 ;
VARIABLE AV0_usa1_3 : at_usa1_3 ;
VARIABLE AV2_usa1_3 : at_usa1_3 ;
VARIABLE AV0_usa1_4 : at_usa1_4 ;
VARIABLE AV2_usa1_4 : at_usa1_4 ;
VARIABLE AV0_csa1_1 : at_csa1_1 ;
VARIABLE AV2_csa1_1 : at_csa1_1 ;
VARIABLE AV0_csa1_2 : at_csa1_2 ;
VARIABLE AV2_csa1_2 : at_csa1_2 ;
VARIABLE AV0_csa1_3 : at_csa1_3 ;
VARIABLE AV2_csa1_3 : at_csa1_3 ;
VARIABLE AV0_csa1_4 : at_csa1_4 ;
VARIABLE AV2_csa1_4 : at_csa1_4 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_usa1_1 := NEW t_usa1_1 (st_ind1 ) ;
AV0_usa1_2 := NEW t_usa1_2 (st_ind2 ) ;
AV0_usa1_3 := NEW t_usa1_3 (st_ind3 ) ;
AV0_usa1_4 := NEW t_usa1_4 (st_ind4 ) ;
AV0_csa1_1 := NEW t_csa1_1 ;
AV0_csa1_2 := NEW t_csa1_2 ;
AV0_csa1_3 := NEW t_csa1_3 ;
AV0_csa1_4 := NEW t_csa1_4 ;
---
AV2_usa1_1 := NEW t_usa1_1 ' ( C2_csa1_1 ) ;
AV2_usa1_2 := NEW t_usa1_2 ' ( C2_csa1_2 ) ;
AV2_usa1_3 := NEW t_usa1_3 ' ( C2_csa1_3 ) ;
AV2_usa1_4 := NEW t_usa1_4 ' ( C2_csa1_4 ) ;
AV2_csa1_1 := NEW t_csa1_1 ' ( C2_csa1_1 ) ;
AV2_csa1_2 := NEW t_csa1_2 ' ( C2_csa1_2 ) ;
AV2_csa1_3 := NEW t_csa1_3 ' ( C2_csa1_3 ) ;
AV2_csa1_4 := NEW t_csa1_4 ' ( C2_csa1_4 ) ;
--
--
ASSERT AV0_usa1_1.all = C0_csa1_1
REPORT "Improper initialization of AV0_usa1_1" SEVERITY FAILURE;
ASSERT AV2_usa1_1.all = C2_csa1_1
REPORT "Improper initialization of AV2_usa1_1" SEVERITY FAILURE;
ASSERT AV0_usa1_2.all = C0_csa1_2
REPORT "Improper initialization of AV0_usa1_2" SEVERITY FAILURE;
ASSERT AV2_usa1_2.all = C2_csa1_2
REPORT "Improper initialization of AV2_usa1_2" SEVERITY FAILURE;
ASSERT AV0_usa1_3.all = C0_csa1_3
REPORT "Improper initialization of AV0_usa1_3" SEVERITY FAILURE;
ASSERT AV2_usa1_3.all = C2_csa1_3
REPORT "Improper initialization of AV2_usa1_3" SEVERITY FAILURE;
ASSERT AV0_usa1_4.all = C0_csa1_4
REPORT "Improper initialization of AV0_usa1_4" SEVERITY FAILURE;
ASSERT AV2_usa1_4.all = C2_csa1_4
REPORT "Improper initialization of AV2_usa1_4" SEVERITY FAILURE;
ASSERT AV0_csa1_1.all = C0_csa1_1
REPORT "Improper initialization of AV0_csa1_1" SEVERITY FAILURE;
ASSERT AV2_csa1_1.all = C2_csa1_1
REPORT "Improper initialization of AV2_csa1_1" SEVERITY FAILURE;
ASSERT AV0_csa1_2.all = C0_csa1_2
REPORT "Improper initialization of AV0_csa1_2" SEVERITY FAILURE;
ASSERT AV2_csa1_2.all = C2_csa1_2
REPORT "Improper initialization of AV2_csa1_2" SEVERITY FAILURE;
ASSERT AV0_csa1_3.all = C0_csa1_3
REPORT "Improper initialization of AV0_csa1_3" SEVERITY FAILURE;
ASSERT AV2_csa1_3.all = C2_csa1_3
REPORT "Improper initialization of AV2_csa1_3" SEVERITY FAILURE;
ASSERT AV0_csa1_4.all = C0_csa1_4
REPORT "Improper initialization of AV0_csa1_4" SEVERITY FAILURE;
ASSERT AV2_csa1_4.all = C2_csa1_4
REPORT "Improper initialization of AV2_csa1_4" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_usa1_1.all = C0_csa1_1 )
and ( AV2_usa1_1.all = C2_csa1_1 )
and ( AV0_usa1_2.all = C0_csa1_2 )
and ( AV2_usa1_2.all = C2_csa1_2 )
and ( AV0_usa1_3.all = C0_csa1_3 )
and ( AV2_usa1_3.all = C2_csa1_3 )
and ( AV0_usa1_4.all = C0_csa1_4 )
and ( AV2_usa1_4.all = C2_csa1_4 )
and ( AV0_csa1_1.all = C0_csa1_1 )
and ( AV2_csa1_1.all = C2_csa1_1 )
and ( AV0_csa1_2.all = C0_csa1_2 )
and ( AV2_csa1_2.all = C2_csa1_2 )
and ( AV0_csa1_3.all = C0_csa1_3 )
and ( AV2_csa1_3.all = C2_csa1_3 )
and ( AV0_csa1_4.all = C0_csa1_4 )
and ( AV2_csa1_4.all = C2_csa1_4 ))
report "***PASSED TEST: c03s03b00x00p03n04i00520"
severity NOTE;
assert ( ( AV0_usa1_1.all = C0_csa1_1 )
and ( AV2_usa1_1.all = C2_csa1_1 )
and ( AV0_usa1_2.all = C0_csa1_2 )
and ( AV2_usa1_2.all = C2_csa1_2 )
and ( AV0_usa1_3.all = C0_csa1_3 )
and ( AV2_usa1_3.all = C2_csa1_3 )
and ( AV0_usa1_4.all = C0_csa1_4 )
and ( AV2_usa1_4.all = C2_csa1_4 )
and ( AV0_csa1_1.all = C0_csa1_1 )
and ( AV2_csa1_1.all = C2_csa1_1 )
and ( AV0_csa1_2.all = C0_csa1_2 )
and ( AV2_csa1_2.all = C2_csa1_2 )
and ( AV0_csa1_3.all = C0_csa1_3 )
and ( AV2_csa1_3.all = C2_csa1_3 )
and ( AV0_csa1_4.all = C0_csa1_4 )
and ( AV2_csa1_4.all = C2_csa1_4 ))
report "***FAILED TEST: c03s03b00x00p03n04i00520 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00520arch;
| gpl-3.0 | f31f9e528b2e73f6c2c78246e15c4ed5 | 0.570563 | 2.601044 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1244/ram_protected_sharedvar.vhd | 1 | 2,716 | --
-- Dual-Port Block RAM with Two Write Ports
-- Modelization with a protected shared variable
-- Simulates without warning in VHDL-2002 simulators
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/ram_protected_sharedvar.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package ram_pkg is
subtype data_type is std_logic_vector(15 downto 0);
type ram_type is protected
procedure write (
addr : std_logic_vector(6 downto 0);
data : data_type);
impure function read (
addr : std_logic_vector(6 downto 0))
return data_type;
end protected ram_type;
end ram_pkg;
package body ram_pkg is
type ram_array is array(0 to 127) of data_type;
type ram_type is protected body
variable ram : ram_array;
procedure write (
addr : std_logic_vector(6 downto 0);
data : data_type) is
begin
ram(conv_integer(addr)) := data;
end procedure write;
impure function read (
addr : std_logic_vector(6 downto 0))
return data_type is
begin
return ram(conv_integer(addr));
end function read;
end protected body ram_type;
end ram_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_pkg.all;
entity ram_protected_sharedvar is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 7
);
port(
clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
addra : in std_logic_vector(ADDR_WIDTH-1 downto 0);
addrb : in std_logic_vector(ADDR_WIDTH-1 downto 0);
dia : in std_logic_vector(DATA_WIDTH-1 downto 0);
dib : in std_logic_vector(DATA_WIDTH-1 downto 0);
doa : out std_logic_vector(DATA_WIDTH-1 downto 0);
dob : out std_logic_vector(DATA_WIDTH-1 downto 0));
end ram_protected_sharedvar;
architecture behavioral of ram_protected_sharedvar is
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if rising_edge(clka) then
if ENA = '1' then
doa <= RAM.read(addra);
if WEA = '1' then
RAM.write(addra, dia);
end if;
end if;
end if;
end process;
process (CLKB)
begin
if rising_edge(clkb) then
if ENB = '1' then
dob <= RAM.read(addrb);
if WEB = '1' then
RAM.write(addrb, dib);
end if;
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | 9178e3aca1020537a2f1fde61263ffcb | 0.601252 | 3.518135 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1155/ent.vhdl | 1 | 745 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
port (
clk : in std_logic;
write : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_write : in std_logic_vector(3 downto 0);
x0 : out std_logic_vector(3 downto 0);
x1 : out std_logic_vector(3 downto 0);
x2 : out std_logic_vector(3 downto 0);
x3 : out std_logic_vector(3 downto 0)
);
end;
architecture a of ent is
type store_t is array(0 to 3) of std_logic_vector(3 downto 0);
signal store : store_t;
begin
process(clk)
begin
if rising_edge(clk) and write = '1' then
store(to_integer(unsigned(addr))) <= data_write;
end if;
end process;
x0 <= store(0);
x1 <= store(1);
x2 <= store(2);
x3 <= store(3);
end;
| gpl-2.0 | f8f69a26aa2bc0527b7201ff9cb8a9f4 | 0.648322 | 2.568966 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug037/config.vhdl | 2 | 45,834 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Global configuration settings.
--
-- Description:
-- ------------------------------------
-- This file evaluates the settings declared in the project specific package my_config.
-- See also template file my_config.vhdl.template.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package config_private is
-- TODO:
-- ===========================================================================
subtype T_BOARD_STRING is STRING(1 to 16);
subtype T_BOARD_CONFIG_STRING is STRING(1 to 64);
subtype T_DEVICE_STRING is STRING(1 to 32);
-- Data structures to describe UART / RS232
type T_BOARD_UART_DESC is record
IsDTE : BOOLEAN; -- Data terminal Equipment (e.g. PC, Printer)
FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS)
BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd"
BaudRate_Max : T_BOARD_CONFIG_STRING;
end record;
-- Data structures to describe Ethernet
type T_BOARD_ETHERNET_DESC is record
IPStyle : T_BOARD_CONFIG_STRING;
RS_DataInterface : T_BOARD_CONFIG_STRING;
PHY_Device : T_BOARD_CONFIG_STRING;
PHY_DeviceAddress : STD_LOGIC_VECTOR(7 downto 0);
PHY_DataInterface : T_BOARD_CONFIG_STRING;
PHY_ManagementInterface : T_BOARD_CONFIG_STRING;
end record;
subtype T_BOARD_ETHERNET_DESC_INDEX is NATURAL range 0 to 7;
type T_BOARD_ETHERNET_DESC_VECTOR is array(NATURAL range <>) of T_BOARD_ETHERNET_DESC;
-- Data structures to describe a board layout
type T_BOARD_INFO is record
BoardName : T_BOARD_CONFIG_STRING;
FPGADevice : T_BOARD_CONFIG_STRING;
UART : T_BOARD_UART_DESC;
Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX);
EthernetCount : T_BOARD_ETHERNET_DESC_INDEX;
end record;
type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO;
constant C_POC_NUL : CHARACTER;
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING;
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING;
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING;
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR;
function conf(str : string) return T_BOARD_CONFIG_STRING;
end package;
package body config_private is
constant C_POC_NUL : CHARACTER := '~';
constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL);
constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL);
constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL);
function conf(str : string) return T_BOARD_CONFIG_STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to T_BOARD_CONFIG_STRING'length);
begin
Result := (others => C_POC_NUL);
if (str'length > 0) then
Result(1 to imin(T_BOARD_CONFIG_STRING'length, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL);
end if;
return Result;
end function;
constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := (
IPStyle => C_BOARD_CONFIG_STRING_EMPTY,
RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_Device => C_BOARD_CONFIG_STRING_EMPTY,
PHY_DeviceAddress => x"00",
PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY,
PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY
);
-- predefined UART descriptions
function brd_CreateUART(IsDTE : BOOLEAN; FlowControl : STRING; BaudRate : STRING; BaudRate_Max : STRING := "") return T_BOARD_UART_DESC is
variable Result : T_BOARD_UART_DESC;
begin
Result.IsDTE := IsDTE;
Result.FlowControl := conf(FlowControl);
Result.BaudRate := conf(BaudRate);
Result.BaudRate_Max := ite((BaudRate_Max = ""), conf(BaudRate), conf(BaudRate_Max));
return Result;
end function;
-- IsDTE FlowControl BaudRate
constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd");
constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd");
constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd");
constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd");
constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd");
function brd_CreateEthernet(IPStyle : STRING; RS_DataInt : STRING; PHY_Device : STRING; PHY_DevAddress : STD_LOGIC_VECTOR(7 downto 0); PHY_DataInt : STRING; PHY_MgntInt : STRING) return T_BOARD_ETHERNET_DESC is
variable Result : T_BOARD_ETHERNET_DESC;
begin
Result.IPStyle := conf(IPStyle);
Result.RS_DataInterface := conf(RS_DataInt);
Result.PHY_Device := conf(PHY_Device);
Result.PHY_DeviceAddress := PHY_DevAddress;
Result.PHY_DataInterface := conf(PHY_DataInt);
Result.PHY_ManagementInterface := conf(PHY_MgntInt);
return Result;
end function;
constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", "");
constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO");
constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC");
constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY);
-- Board Descriptions
-- ===========================================================================
CONSTANT C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := (
-- Altera boards
-- =========================================================================
(
BoardName => conf("DE0"),
FPGADevice => conf("EP3C16F484"), -- EP3C16F484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S2GXAV"),
FPGADevice => conf("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("DE4"),
FPGADevice => conf("EP4SGX230KF40C2"), -- EP4SGX230KF40C2
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"),
1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"),
2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"),
3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"),
others => C_BOARD_ETH_EMPTY
),
EthernetCount => 4
),(
BoardName => conf("DE5"),
FPGADevice => conf("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Lattice boards
-- =========================================================================
(
BoardName => conf("ECP5 Versa"),
FPGADevice => conf("LFE5UM-45F-6BG381C"), -- LFE5UM-45F-6BG381C
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Xilinx boards
-- =========================================================================
(
BoardName => conf("S3SK200"),
FPGADevice => conf("XC3S200FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3SK1000"),
FPGADevice => conf("XC3S1000FT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3ESK500"),
FPGADevice => conf("XC3S500EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("S3ESK1600"),
FPGADevice => conf("XC3S1600EFT256"), -- XC2S200FT256
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("ATLYS"),
FPGADevice => conf("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324
UART => C_BOARD_UART_DCE_460800_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ZC706"),
FPGADevice => conf("XC7Z045-2FFG900"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("KC705"),
FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML505"),
FPGADevice => conf("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML506"),
FPGADevice => conf("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML507"),
FPGADevice => conf("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("XUPV5"),
FPGADevice => conf("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136
UART => C_BOARD_UART_DCE_115200_NONE,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("ML605"),
FPGADevice => conf("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156
UART => C_BOARD_UART_EMPTY,
Ethernet => (
0 => C_BOARD_ETH_HARD_GMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("VC707"),
FPGADevice => conf("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => (
0 => C_BOARD_ETH_SOFT_SGMII_88E1111,
others => C_BOARD_ETH_EMPTY),
EthernetCount => 1
),(
BoardName => conf("VC709"),
FPGADevice => conf("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C
UART => C_BOARD_UART_DTE_921600_NONE,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),(
BoardName => conf("ZEDBOARD"),
FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
),
-- Custom Board (MUST BE LAST ONE)
-- =========================================================================
(
BoardName => conf("Custom"),
FPGADevice => conf("Device is unknown for a custom board"),
UART => C_BOARD_UART_EMPTY,
Ethernet => C_BOARD_ETH_NONE,
EthernetCount => 0
)
);
end package body;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.my_config.all;
use PoC.my_project.all;
use PoC.config_private.all;
use PoC.utils.all;
package config is
constant PROJECT_DIR : string := MY_PROJECT_DIR;
constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM;
-- List of known FPGA / Chip vendors
-- ---------------------------------------------------------------------------
type T_VENDOR is (
VENDOR_UNKNOWN,
VENDOR_ALTERA,
VENDOR_LATTICE,
VENDOR_XILINX
);
-- List of known synthesis tool chains
-- ---------------------------------------------------------------------------
type T_SYNTHESIS_TOOL is (
SYNTHESIS_TOOL_UNKNOWN,
SYNTHESIS_TOOL_ALTERA_QUARTUS2,
SYNTHESIS_TOOL_LATTICE_LSE,
SYNTHESIS_TOOL_SYNOPSIS,
SYNTHESIS_TOOL_XILINX_XST,
SYNTHESIS_TOOL_XILINX_VIVADO
);
-- List of known device families
-- ---------------------------------------------------------------------------
type T_DEVICE_FAMILY is (
DEVICE_FAMILY_UNKNOWN,
-- Altera
DEVICE_FAMILY_ARRIA,
DEVICE_FAMILY_CYCLONE,
DEVICE_FAMILY_STRATIX,
-- Lattice
DEVICE_FAMILY_ICE,
DEVICE_FAMILY_MACHXO,
DEVICE_FAMILY_ECP,
-- Xilinx
DEVICE_FAMILY_SPARTAN,
DEVICE_FAMILY_ZYNQ,
DEVICE_FAMILY_ARTIX,
DEVICE_FAMILY_KINTEX,
DEVICE_FAMILY_VIRTEX
);
type T_DEVICE_SERIES is (
DEVICE_SERIES_UNKNOWN,
-- Xilinx FPGA series
DEVICE_SERIES_7_SERIES,
DEVICE_SERIES_ULTRASCALE,
DEVICE_SERIES_ULTRASCALE_PLUS
);
-- List of known devices
-- ---------------------------------------------------------------------------
type T_DEVICE is (
DEVICE_UNKNOWN,
-- Altera
DEVICE_MAX2, DEVICE_MAX10, -- Altera.Max
DEVICE_ARRIA1, DEVICE_ARRIA2, DEVICE_ARRIA5, DEVICE_ARRIA10, -- Altera.Arria
DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, DEVICE_CYCLONE4, -- Altera.Cyclone
DEVICE_CYCLONE5, --
DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX3, DEVICE_STRATIX4, -- Altera.Stratix
DEVICE_STRATIX5, DEVICE_STRATIX10, --
-- Lattice
DEVICE_ICE40, DEVICE_ICE65, DEVICE_ICE5, -- Lattice.iCE
DEVICE_MACHXO, DEVICE_MACHXO2, -- Lattice.MachXO
DEVICE_ECP3, DEVICE_ECP4, DEVICE_ECP5, -- Lattice.ECP
-- Xilinx
DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan
DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq
DEVICE_ARTIX7, -- Xilinx.Artix
DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex
DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex
DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS --
);
-- List of known device subtypes
-- ---------------------------------------------------------------------------
type T_DEVICE_SUBTYPE is (
DEVICE_SUBTYPE_NONE,
-- Altera
DEVICE_SUBTYPE_E,
DEVICE_SUBTYPE_GS,
DEVICE_SUBTYPE_GX,
DEVICE_SUBTYPE_GT,
-- Lattice
DEVICE_SUBTYPE_U,
DEVICE_SUBTYPE_UM,
-- Xilinx
DEVICE_SUBTYPE_X,
DEVICE_SUBTYPE_T,
DEVICE_SUBTYPE_XT,
DEVICE_SUBTYPE_HT,
DEVICE_SUBTYPE_LX,
DEVICE_SUBTYPE_SXT,
DEVICE_SUBTYPE_LXT,
DEVICE_SUBTYPE_TXT,
DEVICE_SUBTYPE_FXT,
DEVICE_SUBTYPE_CXT,
DEVICE_SUBTYPE_HXT
);
-- List of known transceiver (sub-)types
-- ---------------------------------------------------------------------------
type T_TRANSCEIVER is (
TRANSCEIVER_NONE,
-- TODO: add more? Altera transceivers
-- Altera transceivers
TRANSCEIVER_GXB, -- Altera GXB transceiver
--Lattice transceivers
TRANSCEIVER_MGT, -- Lattice transceiver
-- Xilinx transceivers
TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers
TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers
TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers
TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers
TRANSCEIVER_GTY -- Xilinx GTY transceivers
);
-- Properties of an FPGA architecture
-- ===========================================================================
type T_DEVICE_INFO is record
Vendor : T_VENDOR;
Device : T_DEVICE;
DevFamily : T_DEVICE_FAMILY;
DevNumber : natural;
DevSubType : T_DEVICE_SUBTYPE;
DevSeries : T_DEVICE_SERIES;
TransceiverType : T_TRANSCEIVER;
LUT_FanIn : positive;
end record;
-- Functions extracting board and PCB properties from "MY_BOARD"
-- which is declared in package "my_config".
-- ===========================================================================
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return NATURAL;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO;
function BOARD_NAME(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING;
-- Functions extracting device and architecture properties from "MY_DEVICE"
-- which is declared in package "my_config".
-- ===========================================================================
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL;
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE;
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE;
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive;
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING;
end package;
package body config is
-- inlined function from PoC.utils, to break dependency
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is begin
if cond then return value1; else return value2; end if;
end function;
-- chr_is* function
function chr_isDigit(chr : CHARACTER) return boolean is
begin
return ((CHARACTER'pos('0') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('9')));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return (((CHARACTER'pos('a') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('z'))) or
((CHARACTER'pos('A') <= CHARACTER'pos(chr)) and (CHARACTER'pos(chr) <= CHARACTER'pos('Z'))));
end function;
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_trim(str : STRING) return STRING is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return str(str'low to i-1);
end if;
end loop;
return str;
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
variable chr1 : CHARACTER;
variable chr2 : CHARACTER;
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in 0 to len-1 loop
chr1 := str1(str1'low + i);
chr2 := str2(str2'low + i);
if (CHARACTER'pos('A') <= CHARACTER'pos(chr1)) and (CHARACTER'pos(chr1) <= CHARACTER'pos('Z')) then
chr1 := CHARACTER'val(CHARACTER'pos(chr1) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (CHARACTER'pos('A') <= CHARACTER'pos(chr2)) and (CHARACTER'pos(chr2) <= CHARACTER'pos('Z')) then
chr2 := CHARACTER'val(CHARACTER'pos(chr2) - CHARACTER'pos('A') + CHARACTER'pos('a'));
end if;
if (chr1 /= chr2) then
return FALSE;
elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then
return FALSE;
elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
if ((str1'length = len) and (str2'length = len)) then -- both strings are fully consumed and equal
return TRUE;
elsif (str1'length > len) then
return (str1(str1'low + len) = C_POC_NUL); -- str1 is longer, but str_length equals len
else
return (str2(str2'low + len) = C_POC_NUL); -- str2 is longer, but str_length equals len
end if;
end function;
function str_find(str : STRING; pattern : STRING; start : NATURAL := 0) return BOOLEAN is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
-- private functions required by board description
-- ModelSim requires that this functions is defined before it is used below.
-- ===========================================================================
function getLocalDeviceString(DeviceString : STRING) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
constant MY_DEVICE_STR : STRING := BOARD_DEVICE;
variable Result : STRING(1 to T_DEVICE_STRING'length);
begin
Result := (others => C_POC_NUL);
-- report DeviceString for debugging
if (POC_VERBOSE = TRUE) then
report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE;
end if;
-- if DeviceString is populated
if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL);
-- if MY_DEVICE is set, prefer it
elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL);
-- otherwise use MY_BOARD
else
Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL);
end if;
return Result;
end function;
function extractFirstNumber(str : STRING) return NATURAL is
variable low : integer;
variable high : integer;
variable Result : NATURAL;
variable Digit : INTEGER;
begin
low := -1;
high := -1;
for i in str'low to str'high loop
if chr_isDigit(str(i)) then
low := i;
exit;
end if;
end loop;
-- abort if no digit can be found
if (low = -1) then return 0; end if;
for i in (low + 1) to str'high loop
if chr_isAlpha(str(i)) then
high := i - 1;
exit;
end if;
end loop;
if (high = -1) then return 0; end if;
-- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1
-- convert substring to a number
for i in low to high loop
if (chr_isDigit(str(i)) = FALSE) then
return 0;
end if;
Result := (Result * 10) + (character'pos(str(i)) - character'pos('0'));
end loop;
return Result;
end function;
-- Public functions
-- ===========================================================================
-- TODO: comment
function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return NATURAL is
constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD));
constant BOARD_NAME : STRING := str_trim(MY_BRD);
begin
if (POC_VERBOSE = TRUE) then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if;
for i in C_BOARD_INFO_LIST'range loop
if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then
return i;
end if;
end loop;
report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure;
return C_BOARD_INFO_LIST'high;
end function;
function BOARD_INFO(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is
constant BRD : NATURAL := BOARD(BoardConfig);
begin
return C_BOARD_INFO_LIST(BRD);
end function;
-- TODO: comment
function BOARD_NAME(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : NATURAL := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).BoardName);
end function;
-- TODO: comment
function BOARD_DEVICE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : NATURAL := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice);
end function;
function BOARD_UART_BAUDRATE(BoardConfig : STRING := C_BOARD_STRING_EMPTY) return STRING is
constant BRD : NATURAL := BOARD(BoardConfig);
begin
return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate);
end function;
-- purpose: extract vendor from MY_DEVICE
function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN_STR2 : string(1 to 2) := MY_DEV(1 to 2);
constant VEN_STR3 : string(1 to 3) := MY_DEV(1 to 3);
begin
case VEN_STR2 is
when "EP" => return VENDOR_ALTERA;
when "XC" => return VENDOR_XILINX;
when others => null;
end case;
case VEN_STR3 is
when "iCE" => return VENDOR_LATTICE; -- iCE devices
when "LCM" => return VENDOR_LATTICE; -- MachXO device
when "LFE" => return VENDOR_LATTICE; -- ECP devices
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA =>
return SYNTHESIS_TOOL_ALTERA_QUARTUS2;
when VENDOR_LATTICE =>
return SYNTHESIS_TOOL_LATTICE_LSE;
--return SYNTHESIS_TOOL_SYNOPSIS;
when VENDOR_XILINX =>
if (1 fs /= 1 us) then
return SYNTHESIS_TOOL_XILINX_XST;
else
return SYNTHESIS_TOOL_XILINX_VIVADO;
end if;
when others =>
return SYNTHESIS_TOOL_UNKNOWN;
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4);
begin
case VEN is
when VENDOR_ALTERA =>
case DEV_STR is
when "1C" => return DEVICE_CYCLONE1;
when "2C" => return DEVICE_CYCLONE2;
when "3C" => return DEVICE_CYCLONE3;
when "1S" => return DEVICE_STRATIX1;
when "2S" => return DEVICE_STRATIX2;
when "4S" => return DEVICE_STRATIX4;
when "5S" => return DEVICE_STRATIX5;
when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_LATTICE =>
if (MY_DEV(1 to 6) = "LCMX02") then return DEVICE_MACHXO2;
elsif (MY_DEV(1 to 5) = "LCMX0") then return DEVICE_MACHXO;
elsif (MY_DEV(1 to 5) = "iCE40") then return DEVICE_ICE40;
elsif (MY_DEV(1 to 5) = "iCE65") then return DEVICE_ICE65;
elsif (MY_DEV(1 to 4) = "iCE5") then return DEVICE_ICE5;
elsif (MY_DEV(1 to 4) = "LFE3") then return DEVICE_ECP3;
elsif (MY_DEV(1 to 4) = "LFE4") then return DEVICE_ECP4;
elsif (MY_DEV(1 to 4) = "LFE5") then return DEVICE_ECP5;
else report "Unknown Lattice device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when VENDOR_XILINX =>
case DEV_STR is
when "7A" => return DEVICE_ARTIX7;
when "7K" => return DEVICE_KINTEX7;
when "KU" => return DEVICE_KINTEX_ULTRA;
when "3S" => return DEVICE_SPARTAN3;
when "6S" => return DEVICE_SPARTAN6;
when "5V" => return DEVICE_VIRTEX5;
when "6V" => return DEVICE_VIRTEX6;
when "7V" => return DEVICE_VIRTEX7;
when "VU" => return DEVICE_VIRTEX_ULTRA;
when "7Z" => return DEVICE_ZYNQ7;
when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract device from MY_DEVICE
function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
constant FAM_CHAR : character := MY_DEV(4);
begin
case VEN is
when VENDOR_ALTERA =>
case FAM_CHAR is
when 'C' => return DEVICE_FAMILY_CYCLONE;
when 'S' => return DEVICE_FAMILY_STRATIX;
when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_LATTICE =>
case FAM_CHAR is
--when 'M' => return DEVICE_FAMILY_MACHXO;
when 'E' => return DEVICE_FAMILY_ECP;
when others => report "Unknown Lattice device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when VENDOR_XILINX =>
case FAM_CHAR is
when 'A' => return DEVICE_FAMILY_ARTIX;
when 'K' => return DEVICE_FAMILY_KINTEX;
when 'S' => return DEVICE_FAMILY_SPARTAN;
when 'V' => return DEVICE_FAMILY_VIRTEX;
when 'Z' => return DEVICE_FAMILY_ZYNQ;
when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure;
end case;
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- some devices share some common features: e.g. XADC, BlockRAM, ...
function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
begin
case DEV is
-- all Xilinx ****7 devices
when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 =>
return DEVICE_SERIES_7_SERIES;
-- all Xilinx ****UltraScale devices
when DEVICE_KINTEX_ULTRA | DEVICE_VIRTEX_ULTRA =>
return DEVICE_SERIES_ULTRASCALE;
-- all Xilinx ****UltraScale+ devices
when DEVICE_KINTEX_ULTRA_PLUS | DEVICE_VIRTEX_ULTRA_PLUS | DEVICE_ZYNQ_ULTRA_PLUS =>
return DEVICE_SERIES_ULTRASCALE_PLUS;
when others =>
return DEVICE_SERIES_UNKNOWN;
end case;
end function;
function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant VEN : T_VENDOR := VENDOR(DeviceString);
begin
case VEN is
when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high));
when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high));
when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return t_device_subtype is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(MY_DEV);
constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- work around for GHDL
begin
case DEV is
-- TODO: extract Arria GX subtype
when DEVICE_ARRIA1 =>
report "TODO: parse Arria device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract ArriaII GX,GZ subtype
when DEVICE_ARRIA2 =>
report "TODO: parse ArriaII device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract ArriaV GX, GT, SX, GZ subtype
when DEVICE_ARRIA5 =>
report "TODO: parse ArriaV device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- TODO: extract Arria10 GX, GT, SX subtype
when DEVICE_ARRIA10 =>
report "TODO: parse Arria10 device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
-- Altera Cyclon I, II, III, IV, V devices have no subtype
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 | DEVICE_CYCLONE4 |
DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE;
when DEVICE_STRATIX2 =>
if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_STRATIX4 =>
if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E;
elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX;
-- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT;
else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
-- TODO: extract StratixV subtype
when DEVICE_STRATIX5 =>
report "TODO: parse Stratix V device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
when DEVICE_ECP5 =>
if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U;
elsif (DEV_SUB_STR = "UM") then return DEVICE_SUBTYPE_UM;
else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_SPARTAN3 =>
report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure;
return DEVICE_SUBTYPE_NONE;
when DEVICE_SPARTAN6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX5 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT;
elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT;
else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX6 =>
if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX;
elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT;
elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT;
elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT;
elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT;
else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_ARTIX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_KINTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when DEVICE_VIRTEX7 =>
if ( ( str_find(MY_DEV(5 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T;
elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT;
elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 TO MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT;
else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure;
end if;
when DEVICE_VIRTEX_ULTRA => return DEVICE_SUBTYPE_NONE;
when DEVICE_VIRTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when DEVICE_ZYNQ7 => return DEVICE_SUBTYPE_NONE;
when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE;
when others => report "Device sub-type is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString);
begin
case SERIES is
when DEVICE_SERIES_7_SERIES | DEVICE_SERIES_ULTRASCALE |
DEVICE_SERIES_ULTRASCALE_PLUS => return 6;
when others => null;
end case;
case DEV is
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4;
when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4;
when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6;
when DEVICE_ECP5 => return 4;
when DEVICE_SPARTAN3 => return 4;
when DEVICE_SPARTAN6 => return 6;
when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6;
when others => report "LUT fan-in is unknown for the given device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is
constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString);
constant DEV : T_DEVICE := DEVICE(DeviceString);
constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString);
constant DEV_SUB : t_device_subtype := DEVICE_SUBTYPE(DeviceString);
begin
case DEV is
when DEVICE_MAX2 | DEVICE_MAX10 => return TRANSCEIVER_NONE; -- Altera MAX II, 10 devices have no transceivers
when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers
when DEVICE_STRATIX2 => return TRANSCEIVER_GXB;
when DEVICE_STRATIX4 => return TRANSCEIVER_GXB;
--when DEVICE_STRATIX5 => return TRANSCEIVER_GXB;
when DEVICE_ECP5 => return TRANSCEIVER_MGT;
when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers
when DEVICE_SPARTAN6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1;
when others => report "Unknown Spartan-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX5 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL;
when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX;
when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX;
when others => report "Unknown Virtex-5 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_VIRTEX6 =>
case DEV_SUB is
when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE;
when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1;
when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1;
when others => report "Unknown Virtex-6 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2;
when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2;
when DEVICE_VIRTEX7 =>
case DEV_SUB is
when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2;
when DEVICE_SUBTYPE_XT =>
if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2;
else return TRANSCEIVER_GTHE2;
end if;
when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2;
when others => report "Unknown Virtex-7 subtype: " & t_device_subtype'image(DEV_SUB) severity failure;
end case;
when DEVICE_ZYNQ7 =>
case DEV_NUM is
when 10 | 20 => return TRANSCEIVER_NONE;
when 15 => return TRANSCEIVER_GTPE2;
when others => return TRANSCEIVER_GTXE2;
end case;
when others => report "Unknown device." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
-- purpose: extract architecture properties from DEVICE
function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is
variable Result : T_DEVICE_INFO;
begin
Result.Vendor := VENDOR(DeviceString);
Result.Device := DEVICE(DeviceString);
Result.DevFamily := DEVICE_FAMILY(DeviceString);
Result.DevNumber := DEVICE_NUMBER(DeviceString);
Result.DevSubType := DEVICE_SUBTYPE(DeviceString);
Result.DevSeries := DEVICE_SERIES(DeviceString);
Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString);
Result.LUT_FanIn := LUT_FANIN(DeviceString);
return Result;
end function;
-- force FSM to predefined encoding in debug mode
function getFSMEncoding_gray(debug : BOOLEAN) return STRING is
begin
if (debug = true) then
return "gray";
else
case VENDOR is
when VENDOR_ALTERA => return "default";
--when VENDOR_LATTICE => return "default";
when VENDOR_XILINX => return "auto";
when others => report "Unknown vendor." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end if;
end function;
end package body;
| gpl-2.0 | d1fbe6e52f0afc60803e487359eae423 | 0.611969 | 3.337751 | false | false | false | false |
rogerluan/Arquitetura-PUC-Campinas-2016 | Project 2/cpu.vhd | 1 | 2,209 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;
ENTITY cpu IS
PORT ( Data : IN STD_LOGIC_VECTOR(24 DOWNTO 0) ;
Clock : IN STD_LOGIC;
BusWires : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
r0_stream, r1_stream, r2_stream, r3_stream, rsys_stream, rtemp0_stream, rtemp1_stream : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
debug_state: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; -- Used for debugging
END cpu ;
ARCHITECTURE Behavior OF cpu IS
SIGNAL r0_data, r1_data, r2_data, r3_data, rsys_data, rtemp0_data, rtemp1_in_data, rtemp1_out_data : STD_LOGIC_VECTOR(15 DOWNTO 0) ;
SIGNAL Imedout, Rsysin, Rsysout, ALU : STD_LOGIC;
SIGNAL Rtempin, Rtempout : STD_LOGIC_VECTOR(0 TO 1);
SIGNAL Rin, Rout : STD_LOGIC_VECTOR(0 TO 3);
BEGIN
-- Unit Control
unit_control: uc PORT MAP ( Data, Clock, Imedout, Rin, Rout, Rtempin, Rtempout, Rsysin, Rsysout, ALU, debug_state);
-- ALU
logical_unit: alu_component PORT MAP (rtemp0_data, BusWires, ALU, rtemp1_in_data);
-- Registers
reg0: regn PORT MAP ( BusWires, Rin(0), Clock, r0_data ) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, r1_data ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, r2_data ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, r3_data ) ;
regsys: regn PORT MAP ( BusWires, Rsysin, Clock, rsys_data ) ;
regtemp0: regn PORT MAP ( BusWires, Rtempin(0), Clock, rtemp0_data ) ;
regtemp1: regn PORT MAP ( rtemp1_in_data, Rtempin(1), Clock, rtemp1_out_data ) ;
-- Tri-States
tri_imed: trin PORT MAP ( Data(15 DOWNTO 0), Imedout, BusWires ) ;
tri_r0: trin PORT MAP ( r0_data, Rout(0), BusWires ) ;
tri_r1: trin PORT MAP ( r1_data, Rout(1), BusWires ) ;
tri_r2: trin PORT MAP ( r2_data, Rout(2), BusWires ) ;
tri_r3: trin PORT MAP ( r3_data, Rout(3), BusWires ) ;
tri_rsys: trin PORT MAP ( rsys_data, Rsysout, BusWires ) ;
tri_rtemp0: trin PORT MAP ( rtemp0_data, Rtempout(0), BusWires ) ;
tri_rtemp1: trin PORT MAP ( rtemp1_out_data, Rtempout(1), BusWires ) ;
-- Debugging Variables
r0_stream <= r0_data;
r1_stream <= r1_data;
r2_stream <= r2_data;
r3_stream <= r3_data;
rsys_stream <= rsys_data;
rtemp0_stream <= rtemp0_data;
rtemp1_stream <= rtemp1_in_data;
END Behavior ; | mit | 404ad2e8548030f5cc700aa225357a35 | 0.673155 | 2.59577 | false | false | false | false |
nickg/nvc | test/lower/slice1.vhd | 1 | 675 | entity slice1 is
end entity;
architecture test of slice1 is
type int_vector is array (integer range <>) of integer;
signal x : int_vector(0 to 3);
begin
p1: process is
variable u : int_vector(5 downto 2);
variable v : int_vector(0 to 3);
begin
v := ( 1, 2, 3, 4 );
v(1 to 2) := ( 6, 7 );
assert v(2 to 3) = ( 7, 4 );
wait for 1 ns;
x <= ( 1, 2, 3, 4 );
x(1 to 2) <= ( 6, 7 );
assert x(2 to 3) = ( 7, 4 );
wait for 1 ns;
u := ( 1, 2, 3, 4);
u(4 downto 3) := ( 6, 7 );
assert u(3 downto 2) = ( 7, 4 );
wait;
end process;
end architecture;
| gpl-3.0 | d19c1030d966f8ffb1c8f85960e3614f | 0.460741 | 3.09633 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1139/tb_ent.vhdl | 1 | 568 | entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal a : std_logic;
signal b : std_logic;
signal z : std_logic;
begin
dut: entity work.ent
port map (a, b, z);
process
constant av : std_logic_vector := b"1101";
constant bv : std_logic_vector := b"0111";
constant zv : std_logic_vector := b"0101";
begin
for i in av'range loop
a <= av (i);
b <= bv (i);
wait for 1 ns;
assert z = zv(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 57ca1209b8ea97d2e50b9896e9a7b082 | 0.605634 | 3.138122 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug18810/OISC_SUBLEQ.vhd | 3 | 9,815 | library ieee;
use ieee.std_logic_1164.all;
use work.DMEM_PKG.all;
package OISC_SUBLEQ_PKG is
component OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := false;
LVT_DMEM : boolean := true;
ASYNC : boolean := false
);
port (
iPCLK : in std_logic;
iPWE : in std_logic;
iPADDR : in integer range 0 to 2**log2PADDR-1;
iPINST : in std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
oPINST : out std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLR : in std_logic;
iCLK : in std_logic;
iACT : in std_logic;
oACT : out std_logic;
oPC : out integer range 0 to 2**log2PADDR-1;
oLEQ : out std_logic
);
end component OISC_SUBLEQ;
constant cOISC_SUBLEQ_PW_LATENCY : integer := 1;
constant cOISC_SUBLEQ_PR_LATENCY : integer := 0;
constant cOISC_SUBLEQ_LATENCY : integer := 1;
pure function fOISC_SUBLEQ_DW_LATENCY (
iLVT_DMEM : boolean
) return integer;
pure function fOISC_SUBLEQ_DR_LATENCY (
iLVT_DMEM : boolean
) return integer;
end package OISC_SUBLEQ_PKG;
package body OISC_SUBLEQ_PKG is
pure function fOISC_SUBLEQ_DW_LATENCY (
iLVT_DMEM : boolean
) return integer is
begin
if (iLVT_DMEM = true) then
return cDMEM_DW_LATENCY;
else
return 1;
end if;
end function fOISC_SUBLEQ_DW_LATENCY;
pure function fOISC_SUBLEQ_DR_LATENCY (
iLVT_DMEM : boolean
) return integer is
begin
if (iLVT_DMEM = true) then
return cDMEM_DR_LATENCY;
else
return 0;
end if;
end function fOISC_SUBLEQ_DR_LATENCY;
end package body OISC_SUBLEQ_PKG;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.DMEM_PKG.all;
entity OISC_SUBLEQ is
generic (
log2PADDR : integer range 0 to integer'high := 8;
log2DADDR : integer range 0 to integer'high := 4;
DW : integer range 1 to integer'high := 8;
ZERO : boolean := true;
LVT_DMEM : boolean := true;
ASYNC : boolean := false
);
port (
iPCLK : in std_logic;
iPWE : in std_logic;
iPADDR : in integer range 0 to 2**log2PADDR-1;
iPINST : in std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
oPINST : out std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
iDCLK : in std_logic;
iDWE : in std_logic;
iDADDR : in integer range 0 to 2**log2DADDR-1;
iDDATA : in std_logic_vector(DW-1 downto 0);
oDDATA : out std_logic_vector(DW-1 downto 0);
iCLR : in std_logic;
iCLK : in std_logic;
iACT : in std_logic;
oACT : out std_logic;
oPC : out integer range 0 to 2**log2PADDR-1;
oLEQ : out std_logic
);
begin
-- RTL_SYNTHESIS OFF
A_DMEM_AR_LATENCY : assert (not (LVT_DMEM = true and cDMEM_AR_LATENCY /= 0))
report OISC_SUBLEQ'instance_name &
"cDMEM_AR_LATENCY =" & integer'image(cDMEM_AR_LATENCY)
severity warning;
A_DMEM_BW_LATENCY : assert (not (LVT_DMEM = true and cDMEM_BW_LATENCY /= 1))
report OISC_SUBLEQ'instance_name &
"cDMEM_BW_LATENCY =" & integer'image(cDMEM_BW_LATENCY)
severity warning;
A_DMEM_BR_LATENCY : assert (not (LVT_DMEM = true and cDMEM_BR_LATENCY /= 0))
report OISC_SUBLEQ'instance_name &
"cDMEM_BR_LATENCY =" & integer'image(cDMEM_BR_LATENCY)
severity warning;
-- RTL_SYNTHESIS ON
end entity OISC_SUBLEQ;
architecture TP of OISC_SUBLEQ is
type tIF is record
PMEM_oA : integer range 0 to 2**log2DADDR-1;
PMEM_oB : integer range 0 to 2**log2DADDR-1;
PMEM_oC : integer range 0 to 2**log2PADDR-1;
DMEM_oA : std_logic_vector(DW-1 downto 0);
DMEM_oB : std_logic_vector(DW-1 downto 0);
end record tIF;
signal s : tIF;
type t is record
ACT : std_logic;
SUB : std_logic_vector(DW-1 downto 0);
PC : integer range 0 to 2**log2PADDR-1;
LEQ : std_logic;
end record t;
constant c : t := (
ACT => '0',
SUB => (DW-1 downto 0 => '0'),
PC => 0,
LEQ => '0'
);
signal g : t;
signal r : t := c;
begin
B_BLOB : block is
type tPMEM is array (0 to 2**log2PADDR-1) of std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
signal aPMEM : tPMEM := (0 to 2**log2PADDR-1 => (log2DADDR+log2DADDR+log2PADDR-1 downto 0 => '0'));
signal gPMEM_oINST : std_logic_vector(log2DADDR+log2DADDR+log2PADDR-1 downto 0);
signal gPMEM_oA : std_logic_vector(log2DADDR-1 downto 0);
signal gPMEM_oB : std_logic_vector(log2DADDR-1 downto 0);
signal gPMEM_oC : std_logic_vector(log2PADDR-1 downto 0);
begin
P_PMEM_P : process (iPCLK)
begin
if (rising_edge(iPCLK)) then
if (iPWE = '1') then
aPMEM(iPADDR) <= iPINST;
end if;
end if;
end process P_PMEM_P;
oPINST <= aPMEM(iPADDR);
gPMEM_oINST <= aPMEM(r.PC);
gPMEM_oA <= gPMEM_oINST(log2DADDR+log2DADDR+log2PADDR-1 downto log2DADDR+log2PADDR);
gPMEM_oB <= gPMEM_oINST( log2DADDR+log2PADDR-1 downto log2PADDR);
gPMEM_oC <= gPMEM_oINST( log2PADDR-1 downto 0);
s.PMEM_oA <= to_integer(unsigned(gPMEM_oA));
s.PMEM_oB <= to_integer(unsigned(gPMEM_oB));
s.PMEM_oC <= to_integer(unsigned(gPMEM_oC));
G_LVT_DMEM : if (LVT_DMEM = true) generate
begin
U_DMEM : DMEM
generic map (
log2DADDR => log2DADDR,
DW => DW,
ZERO => ZERO
)
port map (
iDCLK => iDCLK,
iDWE => iDWE,
iDADDR => iDADDR,
iDDATA => iDDATA,
oDDATA => oDDATA,
iCLK => iCLK,
iAADDR => s.PMEM_oA,
oADATA => s.DMEM_oA,
iBWE => iACT,
iBADDR => s.PMEM_oB,
iBDATA => g.SUB,
oBDATA => s.DMEM_oB
);
end generate G_LVT_DMEM;
G_2W3R_DMEM : if (LVT_DMEM = false) generate
-- FIXME: ISE 13.2 does not support "protected"... :(
--type tDMEM is protected
-- procedure pWRITE(
-- iADDR : in integer range 0 to 2**log2DADDR-1;
-- iDATA : in std_logic_vector(DW-1 downto 0)
-- );
-- impure function fREAD(
-- iADDR : integer range 0 to 2**log2DADDR-1
-- ) return std_logic_vector;
--end protected tDMEM;
--type tDMEM is protected body
-- type tDMEM_PRIM is array (0 to 2**log2DADDR-1) of std_logic_vector(DW-1 downto 0);
-- variable aDMEM_PRIM : tDMEM_PRIM := (0 to 2**log2DADDR-1 => (DW-1 downto 0 => '0'));
-- procedure pWRITE(
-- iADDR : in integer range 0 to 2**log2DADDR-1;
-- iDATA : in std_logic_vector(DW-1 downto 0)
-- ) is
-- begin
-- aDMEM_PRIM(iADDR) := iDATA;
-- end procedure pWRITE;
-- impure function fREAD(
-- iADDR : integer range 0 to 2**log2DADDR-1
-- ) return std_logic_vector is
-- begin
-- return aDMEM_PRIM(iADDR);
-- end function fREAD;
--end protected body tDMEM;
--shared variable aDMEM : tDMEM;
-- FIXME: VHDL-93 shared variable does not provide mutex... :(
type tDMEM is array (0 to 2**log2DADDR-1) of std_logic_vector(DW-1 downto 0);
shared variable aDMEM : tDMEM := (0 to 2**log2DADDR-1 => (DW-1 downto 0 => '0'));
begin
P_DMEM_D : process (iDCLK)
begin
if (rising_edge(iDCLK)) then
if (iDWE = '1') then
--aDMEM.pWRITE(iDADDR, iDDATA);
aDMEM(iDADDR) := iDDATA;
end if;
end if;
end process P_DMEM_D;
--oDDATA <= (DW-1 downto 0 => '0') when (ZERO = true and iDADDR = 0) else aDMEM.fREAD(iDADDR);
--s.DMEM_oA <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oA = 0) else aDMEM.fREAD(s.PMEM_oA);
--s.DMEM_oB <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oB = 0) else aDMEM.fREAD(s.PMEM_oB);
oDDATA <= (DW-1 downto 0 => '0') when (ZERO = true and iDADDR = 0) else aDMEM(iDADDR);
s.DMEM_oA <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oA = 0) else aDMEM(s.PMEM_oA);
s.DMEM_oB <= (DW-1 downto 0 => '0') when (ZERO = true and s.PMEM_oB = 0) else aDMEM(s.PMEM_oB);
-- FIXME: This DMEM write back is kludge... :(
P_DMEM_WRITE_BACK : process (iCLK)
begin
if (rising_edge(iCLK)) then
if (iACT = '1') then
--aDMEM.pWRITE(s.PMEM_oB, g.SUB);
aDMEM(s.PMEM_oB) := g.SUB;
end if;
end if;
end process P_DMEM_WRITE_BACK;
end generate G_2W3R_DMEM;
end block B_BLOB;
P_COMB : process (iACT, r, s)
variable v : t := c;
pure function fSUB (
iA : std_logic_vector(DW-1 downto 0);
iB : std_logic_vector(DW-1 downto 0)
) return std_logic_vector is
variable vSUB : signed(DW-1 downto 0);
begin
-- FIXME: Consider th3 borrow?
vSUB := signed(iB) - signed(iA);
return std_logic_vector(vSUB);
end function fSUB;
begin
if (iACT = '1') then
v.ACT := '1';
v.SUB := fSUB(s.DMEM_oA, s.DMEM_oB);
if (signed(v.SUB) <= 0) then
v.PC := s.PMEM_oC;
v.LEQ := '1';
else
if (r.PC >= 2**log2PADDR-1) then
v.PC := 0;
else
v.PC := r.PC + 1;
end if;
v.LEQ := '0';
end if;
else
v.ACT := '0';
v.SUB := r.SUB;
v.PC := r.PC;
v.LEQ := r.LEQ;
end if;
g <= v;
oACT <= r.ACT;
oPC <= r.PC;
oLEQ <= r.LEQ;
end process P_COMB;
G_ASYNC : if (ASYNC = true) generate
begin
P_SEQ : process (iCLR, iCLK)
begin
if (iCLR = '1') then
r <= c;
elsif (rising_edge(iCLK)) then
r <= g;
end if;
end process P_SEQ;
end generate G_ASYNC;
G_SYNC : if (ASYNC = false) generate
begin
P_SEQ : process (iCLK)
begin
if (rising_edge(iCLK)) then
if (iCLR = '1') then
r <= c;
else
r <= g;
end if;
end if;
end process P_SEQ;
end generate G_SYNC;
end architecture TP;
| gpl-2.0 | de3be95d82a5c1feae7d4118a837aec4 | 0.608456 | 2.721852 | false | false | false | false |
nickg/nvc | test/regress/issue447.vhd | 1 | 768 | entity issue447 is
end entity;
architecture test of issue447 is
procedure assign(v : out bit_vector; b : in bit) is
variable canary : integer := 42;
begin
v := (v'range => b);
report integer'image(canary);
end procedure;
procedure proc (x : natural) is
type rec is record
f : bit_vector(1 to x);
end record;
variable v : rec;
begin
wait for 1 ns;
assert v.f = (1 to x => '0');
wait for 1 ns;
assign(v.f, '1');
wait for 1 ns;
assert v.f = (1 to x => '1');
end procedure;
begin
main: process is
begin
proc(12); -- This call would clobber stack
wait;
end process;
end architecture;
| gpl-3.0 | 11536b0585ae0b97ed292226b489dd8a | 0.519531 | 3.820896 | false | false | false | false |
tgingold/ghdl | testsuite/synth/oper01/tb_cmp02.vhdl | 1 | 1,386 | entity tb_cmp02 is
end tb_cmp02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cmp02 is
signal l : std_logic_vector(3 downto 0);
signal r : natural;
signal eq : std_logic;
signal ne : std_logic;
signal lt : std_logic;
signal le : std_logic;
signal ge : std_logic;
signal gt : std_logic;
begin
cmp02_1: entity work.cmp02
port map (
l => l,
r => r,
eq => eq,
ne => ne,
lt => lt,
le => le,
ge => ge,
gt => gt);
process
begin
l <= x"5";
r <= 7;
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '1' severity failure;
assert le = '1' severity failure;
assert ge = '0' severity failure;
assert gt = '0' severity failure;
l <= x"a";
r <= 7;
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '0' severity failure;
assert le = '0' severity failure;
assert ge = '1' severity failure;
assert gt = '1' severity failure;
l <= x"9";
r <= 9;
wait for 1 ns;
assert eq = '1' severity failure;
assert ne = '0' severity failure;
assert lt = '0' severity failure;
assert le = '1' severity failure;
assert ge = '1' severity failure;
assert gt = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | dd32ac9b4ccfcc1ee2c9033e4b9acd37 | 0.575036 | 3.307876 | false | false | false | false |
tgingold/ghdl | testsuite/synth/insert01/insert02.vhdl | 1 | 434 | library ieee;
use ieee.std_logic_1164.all;
entity insert02 is
port (a : std_logic_vector (3 downto 0);
b : std_logic_vector (1 downto 0);
o0, o1, o2 : out std_logic_vector (3 downto 0));
end insert02;
architecture behav of insert02 is
begin
process(a, b)
begin
o0 <= a;
o0 (1 downto 0) <= b;
o1 <= a;
o1 (2 downto 1) <= b;
o2 <= a;
o2 (3 downto 2) <= b;
end process;
end behav;
| gpl-2.0 | 47488083e166179b6ca228019ea81507 | 0.573733 | 2.818182 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd | 4 | 3,280 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_fg_18_03.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
package CPU_types is
subtype word is bit_vector(0 to 31);
subtype byte is bit_vector(0 to 7);
alias convert_to_natural is
bv_utilities.bv_arithmetic.bv_to_natural [ bit_vector return natural ];
constant halt_opcode : byte := "00000000";
type code_array is array (natural range <>) of word;
constant code : code_array := ( X"01000000", X"01000000", X"02000000",
X"01000000", X"01000000", X"02000000",
X"00000000" );
end package CPU_types;
use work.CPU_types.all;
entity CPU is
end entity CPU;
-- code from book
architecture instrumented of CPU is
type count_file is file of natural;
file instruction_counts : count_file open write_mode is "instructions";
begin
interpreter : process is
variable IR : word;
alias opcode : byte is IR(0 to 7);
variable opcode_number : natural;
type counter_array is array (0 to 2**opcode'length - 1) of natural;
variable counters : counter_array := (others => 0);
-- . . .
-- not in book
variable code_index : natural := 0;
-- end not in book
begin
-- . . . -- initialize the instruction set interpreter
instruction_loop : loop
-- . . . -- fetch the next instruction into IR
-- not in book
IR := code(code_index);
code_index := code_index + 1;
-- end not in book
-- decode the instruction
opcode_number := convert_to_natural(opcode);
counters(opcode_number) := counters(opcode_number) + 1;
-- . . .
-- execute the decoded instruction
case opcode is
-- . . .
when halt_opcode => exit instruction_loop;
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop instruction_loop;
for index in counters'range loop
write(instruction_counts, counters(index));
end loop;
wait; -- program finished, wait forever
end process interpreter;
end architecture instrumented;
-- code from book
| gpl-2.0 | 901afd29186ae87e698080a0772ac95b | 0.579573 | 4.390897 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd | 4 | 1,499 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic ( r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1 );
port ( terminal c, p1, p2 : electrical );
end entity sw_LoopCtrl_wa;
----------------------------------------------------------------
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1 * i1;
v2 == r2 * i2;
end architecture ideal;
| gpl-2.0 | 7981afaa8f2c323979240448a6b8f716 | 0.655103 | 3.728856 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue301/src/traceback.vhd | 4 | 3,115 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Traceback unit for a viterbi decoder
--! @author Markus Fehrenz
--! @date 2011/07/11
--!
--! @details The traceback unit only processes a data stream.
--! There is no knowledge about the decoder configuration.
--! The information about acquisition and window lengths is received from ram control.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
entity trellis_traceback is
port(
-- general signals
clk : in std_logic;
rst : in std_logic;
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
s_axis_input_window_tuser : in std_logic;
s_axis_input_last_tuser : in std_logic;
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_last_tuser : out std_logic;
m_axis_output_tready : in std_logic
);
end entity trellis_traceback;
architecture rtl of trellis_traceback is
signal current_node : unsigned(BW_TRELLIS_STATES - 1 downto 0);
signal m_axis_output_tvalid_int : std_logic;
signal s_axis_input_tready_int : std_logic;
begin
s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
'0';
s_axis_input_tready <= s_axis_input_tready_int;
m_axis_output_tvalid <= m_axis_output_tvalid_int;
-- Traceback the ACS local path decisions and output the resulting global path.
pr_traceback : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
m_axis_output_tvalid_int <= '0';
m_axis_output_tdata <= '0';
m_axis_output_tlast <= '0';
m_axis_output_last_tuser <= '0';
current_node <= (others => '0');
else
if m_axis_output_tready = '1' then
m_axis_output_tvalid_int <= '0';
end if;
-- calculate the decoded bit with an shift register
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
m_axis_output_tlast <= s_axis_input_tlast;
m_axis_output_last_tuser <= s_axis_input_last_tuser;
-- handle tvalid output signal
if s_axis_input_window_tuser = '1' then
m_axis_output_tvalid_int <= '1';
m_axis_output_tdata <= current_node(BW_TRELLIS_STATES - 1);
end if;
-- last value of current window?
if s_axis_input_last_tuser = '1' then
current_node <= to_unsigned(0, BW_TRELLIS_STATES);
else
current_node <= current_node(BW_TRELLIS_STATES - 2 downto 0)
& s_axis_input_tdata(to_integer(current_node(BW_TRELLIS_STATES - 1 downto 0)));
end if;
end if;
end if;
end if;
end process pr_traceback;
end architecture rtl;
| gpl-2.0 | 876d61f4c335568ac466a7526511405d | 0.648796 | 3.065945 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd | 4 | 1,801 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp_2pole_res is
generic ( A : real := 1.0e6; -- open loop gain
rin : real := 1.0e6; -- input resistance
rout : real := 100.0; -- output resistance
fp1 : real := 5.0; -- first pole
fp2 : real := 9.0e5 ); -- second pole
port ( terminal in_pos, in_neg, output : electrical );
end entity opamp_2pole_res;
----------------------------------------------------------------
architecture ltf of opamp_2pole_res is
constant wp1 : real := fp1 * math_2_pi;
constant wp2 : real := fp2 * math_2_pi;
constant num : real_vector := (0 => wp1 * wp2 * A);
constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
quantity v_in across i_in through in_pos to in_neg;
quantity v_out across i_out through output;
begin
i_in == v_in / rin; -- input current
v_out == v_in'ltf(num, den) + i_out * rout;
end architecture ltf;
| gpl-2.0 | 1ffa78ce51d2444fee1b7a4fd3b51f9f | 0.646308 | 3.616466 | false | false | false | false |
nickg/nvc | test/lower/array2.vhd | 1 | 1,539 | entity array2 is
end entity;
architecture test of array2 is
type int_vec is array (natural range <>) of integer;
type int_vec_ptr is access int_vec;
type int_vec2x2 is array (natural range <>, natural range <>) of integer;
signal s : int_vec(1 to 2);
begin
p1: process is
variable v : int_vec(1 to 2);
variable x : integer;
begin
v := (x, x);
wait;
end process;
p2: process is
variable v : int_vec(1 to 2);
variable x : integer;
begin
v := (1 => x, others => 0);
wait;
end process;
p3: process is
variable v : int_vec2x2(1 to 2, 1 to 2);
variable x, y : integer;
begin
v := ((x, x), (y, y));
wait;
end process;
p4: process is
variable v : int_vec2x2(1 to 2, 1 to 2);
variable x, y : integer;
begin
v := ((x, x), others => (y, y));
wait;
end process;
p5: process is
variable v : int_vec(1 to 3);
variable x : integer;
begin
v := (1 => 1, 2 => x, 3 => 3);
wait;
end process;
p6: process is
variable x : integer;
begin
s <= (x, x);
wait;
end process;
p7: process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 3);
wait;
end process;
p8: process is
variable p : int_vec_ptr;
variable x : integer;
begin
p := new int_vec'(x, x);
wait;
end process;
end architecture;
| gpl-3.0 | b5b33d965d703fed527e872e9e269822 | 0.499025 | 3.489796 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd | 4 | 1,994 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity tb_05_04 is
end entity tb_05_04;
architecture test of tb_05_04 is
signal a, b, sel, z : bit;
begin
dut : entity work.mux2(behavioral)
port map ( a => a, b => b, sel => sel, z => z );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0100",
"1001",
"1101",
"0010",
"0111",
"1010",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 09247aca4d81ca83540019ecb689ab98 | 0.531595 | 4.251599 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue963/tb_ent2.vhdl | 1 | 1,768 | entity tb_ent2 is
end tb_ent2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent2 is
signal clk : std_logic;
signal dout : std_logic_vector(3 downto 0);
signal set_0 : std_logic;
signal set_a : std_logic;
signal set_f : std_logic;
signal set_7 : std_logic;
begin
dut: entity work.ent2
port map (
set_0 => set_0,
set_a => set_a,
set_f => set_f,
set_7 => set_7,
q => dout,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
set_0 <= '1';
set_a <= '0';
set_f <= '0';
set_7 <= '0';
pulse;
assert dout = x"0" severity failure;
set_0 <= '0';
set_a <= '0';
set_f <= '0';
set_7 <= '0';
pulse;
assert dout = x"1" severity failure;
set_0 <= '0';
set_a <= '0';
set_f <= '0';
set_7 <= '0';
pulse;
assert dout = x"2" severity failure;
set_0 <= '0';
set_a <= '1';
set_f <= '0';
set_7 <= '0';
pulse;
assert dout = x"a" severity failure;
set_0 <= '0';
set_a <= '0';
set_f <= '0';
set_7 <= '0';
pulse;
assert dout = x"b" severity failure;
set_0 <= '0';
set_a <= '0';
set_f <= '1';
set_7 <= '0';
pulse;
assert dout = x"f" severity failure;
set_0 <= '0';
set_a <= '0';
set_f <= '0';
set_7 <= '1';
pulse;
assert dout = x"7" severity failure;
set_0 <= '1';
set_a <= '0';
set_f <= '0';
set_7 <= '1';
pulse;
assert dout = x"0" severity failure;
set_0 <= '0';
set_a <= '1';
set_f <= '0';
set_7 <= '1';
pulse;
assert dout = x"a" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | efa38493cc60ff8823be3aa3c8dcbf65 | 0.472285 | 2.824281 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1166/tb_ent.vhdl | 1 | 766 | library ieee;
use ieee.std_logic_1164.all;
entity tb_ent is
end;
architecture a of tb_ent is
signal a, enable, d_in, d_out : std_logic;
begin
uut: entity work.ent
port map (
a => a,
enable => enable,
d_in => d_in,
d_out => d_out
);
process
begin
a <= '0';
enable <= '0';
wait for 10 ns;
assert d_out = '0';
a <= '1';
wait for 10 ns;
assert d_out = '1' severity failure;
enable <= '1';
a <= 'Z';
d_in <= '0';
wait for 10 ns;
assert a = '0' severity failure;
d_in <= '1';
wait for 10 ns;
assert a = '1' severity failure;
wait;
end process;
end;
| gpl-2.0 | 5e9883c456c75084cb18aee4c44e387f | 0.442559 | 3.481818 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd | 4 | 4,917 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1782.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n05i01782pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n05i01782pkg;
use work.c09s06b00x00p04n05i01782pkg.all;
entity c09s06b00x00p04n05i01782ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff := ((234,567.7),(429,35.7))
);
end c09s06b00x00p04n05i01782ent_a;
use work.c09s06b00x00p04n05i01782pkg.all;
architecture c09s06b00x00p04n05i01782arch_a of c09s06b00x00p04n05i01782ent_a is
-- Check that the data was passed...
begin
TESTING : PROCESS
BEGIN
assert NOT( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n05i01782"
severity NOTE;
assert ( g0 = True and
g1 = '0' and
g2 = '@' and
g3 = NOTE and
g4 = 123456789 and
g5 = 987654321.5 and
g6 = 110 ns and
g7 = 12312 and
g8 = 3423 and
g9 = "16 characters OK" and
gA = B"01010010100101010010101001010100"and
gB = ((123, 456.7 ), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n05i01782 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
end c09s06b00x00p04n05i01782arch_a;
-------------------------------------------------------------------------
ENTITY c09s06b00x00p04n05i01782ent IS
END c09s06b00x00p04n05i01782ent;
use work.c09s06b00x00p04n05i01782pkg.all;
ARCHITECTURE c09s06b00x00p04n05i01782arch OF c09s06b00x00p04n05i01782ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector ;
gB : stuff :=((123,456.7),(890,135.7)));
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01782ent_a(c09s06b00x00p04n05i01782arch_a);
BEGIN
u1 : MultiType generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100"
);
END c09s06b00x00p04n05i01782arch;
| gpl-2.0 | 3bd20dc149367cc25e37bcd76075fe80 | 0.512101 | 3.736322 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd | 4 | 2,069 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1720.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p01n02i01720ent IS
END c12s06b01x00p01n02i01720ent;
ARCHITECTURE c12s06b01x00p01n02i01720arch OF c12s06b01x00p01n02i01720ent IS
-- Global type declaration.
type NIBBLE is array( 0 to 3 ) of BIT;
-- Global signals.
SIGNAL B : BIT := '1';
SIGNAL N : NIBBLE := B"1111";
BEGIN
TESTING: PROCESS
BEGIN
-- If one driver created, it will take on the indicated value.
B <= '0' after 10 ns;
N <= B"0000" after 10 ns;
wait on N,B;
assert NOT( B='0' and N=B"0000" )
report "***PASSED TEST: c12s06b01x00p01n02i01720"
severity NOTE;
assert ( B='0' and N=B"0000" )
report "***FAILED TEST: c12s06b01x00p01n02i01720 - At least one driver gets created for eah signal which is assigned to either directly or indirectly inside of a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p01n02i01720arch;
| gpl-2.0 | 6000fbd3aa708866d4b46749fa66d797 | 0.663122 | 3.60453 | false | true | false | false |
nickg/nvc | test/eopt/slice1.vhd | 1 | 542 | entity slice1 is
end entity;
architecture test of slice1 is
function resolved (x : bit_vector) return bit;
subtype r_bit is resolved bit;
type r_bit_vector is array (natural range <>) of r_bit;
signal x : r_bit_vector(0 to 7);
signal y : r_bit_vector(7 downto 0);
begin
x(0 to 3) <= "1111";
x(4 to 2) <= (others => '0');
x(4 to 5) <= "00";
x(5 to 7) <= "111";
y(3 downto 0) <= "1111";
y(2 downto 4) <= (others => '0');
y(5 downto 4) <= "00";
y(7 downto 5) <= "111";
end architecture;
| gpl-3.0 | 75bd5e0c55d57a07e75f24b33cd45b6d | 0.555351 | 2.913978 | false | false | false | false |
lfmunoz/vhdl | templates/host_interface/clkrst_xx720_emu.vhd | 1 | 8,440 |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_clkrst_xx720.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_clkrst_xx720
-- architecture - arch_sip_clkrst_xx720
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- sip_clkrst_xx720
-- Notes: sip_clkrst_xx720
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_clkrst_xx720 is
port (
--Wormhole 'cmdclk_in' of type 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'clkout' of type 'clkout':
clkout_clkout : out std_logic_vector(31 downto 0);
--Wormhole 'ext_clkrst_sfmc720' of type 'ext_clkrst_sfmc720':
clk200_n : in std_logic;
clk200_p : in std_logic;
fpga_emcclk : in std_logic;
--Wormhole 'rst_out' of type 'rst_out':
rst_out_rstout : out std_logic_vector(31 downto 0);
--Wormhole 'ifpga_rst_in' of type 'ifpga_rst_in':
ifpga_rst_in_ifpga_rst : in std_logic
);
end entity sip_clkrst_xx720;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture arch_sip_clkrst_xx720 of sip_clkrst_xx720 is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk200M_o :std_logic;
-------------------------------------------------------------------------------------
--components declarations
-------------------------------------------------------------------------------------
component clkrst_xx720 is
generic ( reset_base :integer:=1024);
port
(
clk200_n : in std_logic;
clk200_p : in std_logic;
fpga_emcclk : in std_logic;
reset_i :in std_logic; --reset complete FPGA
--command if
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
cmdclk_in :in std_logic;
--clk outputs
clk200M_o :out std_logic;
dly_ready_o :out std_logic;
clk_ddr_0_div2o :out std_logic;
clk_ddr_0o :out std_logic;
clk_ddr_90o :out std_logic;
clk_ddr_180o :out std_logic;
clk_ddr_270o :out std_logic;
fpga_emcclko :out std_logic;
--reset outputs
reset1_o :out std_logic;
reset2_o :out std_logic;
reset3_o :out std_logic
);
end component;
begin
-------------------------------------------------------------------------------------
--components instantiations
-------------------------------------------------------------------------------------
i_clkrst_xx720:clkrst_xx720
generic map( reset_base =>2)
port map
(
clk200_n =>clk200_n,
clk200_p =>clk200_p,
fpga_emcclk =>fpga_emcclk,
reset_i =>ifpga_rst_in_ifpga_rst,
--command if
out_cmd =>cmd_out_cmdout,
out_cmd_val =>cmd_out_cmdout_val,
in_cmd =>cmd_in_cmdin,
in_cmd_val =>cmd_in_cmdin_val,
cmdclk_in =>cmdclk_in_cmdclk,
--clk outputs
clk200M_o =>clk200M_o,
dly_ready_o =>open,
clk_ddr_0_div2o =>clkout_clkout(9),
clk_ddr_0o =>clkout_clkout(5),
clk_ddr_90o =>clkout_clkout(6),
clk_ddr_180o =>clkout_clkout(7),
clk_ddr_270o =>clkout_clkout(8),
fpga_emcclko =>clkout_clkout(12),
--reset outputs
reset1_o =>rst_out_rstout(0),
reset2_o =>rst_out_rstout(1),
reset3_o =>rst_out_rstout(2)
);
clkout_clkout(10) <=clk200M_o;
clkout_clkout(11) <=clk200M_o; --clock is used for the command clock
-------------------------------------------------------------------------------------
--synchronous processes
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--asynchronous processes
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--asynchronous mapping
-------------------------------------------------------------------------------------
rst_out_rstout(31 downto 18) <= (others=>'0');
rst_out_rstout(15 downto 3) <= (others=>'0');
end architecture arch_sip_clkrst_xx720 ; -- of sip_clkrst_xx720
| mit | 75247801360e7c61bc2111cfa11d3812 | 0.386967 | 4.858952 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd | 4 | 1,824 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02464ent IS
END c07s03b02x02p03n02i02464ent;
ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
subtype BV1 is BIT_VECTOR (2 downto 1);
constant c : BV1 := (1 => '0', others => '1');
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( c="10" )
report "***PASSED TEST: c07s03b02x02p03n02i02464"
severity NOTE;
assert ( c="10" )
report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02464arch;
| gpl-2.0 | 72691c599f4b68064aa3ff682f3fbb27 | 0.671053 | 3.662651 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd | 4 | 1,629 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_02a is
end entity inline_02a;
architecture test of inline_02a is
begin
block_1 : block is
-- code from book
quantity input1, input2, output : real;
quantity amplified_input1, amplified_input2 : real;
constant gain1 : real := 2.0;
constant gain2 : real := 4.0;
-- end code from book
begin
-- code from book
amplified_input1 == input1 * gain1;
amplified_input2 == input2 * gain2;
output == amplified_input1 * amplified_input2;
-- end code from book
end block block_1;
block_2 : block is
quantity input1, input2, output : real;
constant gain1 : real := 2.0;
constant gain2 : real := 4.0;
begin
-- code from book
output == input1 * gain1 * input2 * gain2;
-- end code from book
end block block_2;
end architecture test;
| gpl-2.0 | 37905f18323aab5218e800aaffffaedc | 0.686311 | 3.887828 | false | false | false | false |
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