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tgingold/ghdl | testsuite/synth/match01/tb_match02.vhdl | 1 | 590 | entity tb_match02 is
end tb_match02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_match02 is
signal a : std_logic_vector(3 downto 0);
signal z : std_logic;
begin
dut: entity work.match02
port map (a, z);
process
begin
a <= "1000";
wait for 1 ns;
assert z = '0' severity failure;
a <= "1010";
wait for 1 ns;
assert z = '0' severity failure;
a <= "0000";
wait for 1 ns;
assert z = '1' severity failure;
a <= "0001";
wait for 1 ns;
assert z = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 35ddd2a3c167bd4952bcca9a54a0103f | 0.60339 | 3.206522 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split5.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split5 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split5;
architecture augh of output_split5 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 4a119ecf3e2ec4f51d93c363a87c4862 | 0.673759 | 2.895277 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd | 4 | 2,715 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_09 is
end entity ch_05_09;
----------------------------------------------------------------
architecture test of ch_05_09 is
signal clk, reset, trigger, test0, test1 : bit := '0';
begin
process_05_3_h : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk rising edge detected";
end process process_05_3_h;
----------------
process_05_3_i : process is
begin
-- code from book:
wait on clk until reset = '0';
-- end of code from book
report "synchronous reset detected";
end process process_05_3_i;
----------------
process_05_3_j : process is
begin
-- code from book:
wait until trigger = '1' for 1 ms;
-- end of code from book
if trigger'event and trigger = '1' then
report "trigger rising edge detected";
else
report "trigger timeout";
end if;
end process process_05_3_j;
----------------
-- code from book:
test_gen : process is
begin
test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
test1 <= '0' after 10 ns, '1' after 30 ns;
wait;
end process test_gen;
-- end of code from book
----------------
stimulus_05_3_h_i_j : process is
begin
clk <= '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns,
'1' after 50 ns, '0' after 60 ns,
'1' after 70 ns, '0' after 80 ns;
reset <= '1' after 45 ns, '0' after 75 ns;
trigger <= '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
wait;
end process stimulus_05_3_h_i_j;
end architecture test;
| gpl-2.0 | c8c760bd13b5e7a93d6440cd2af86a63 | 0.564273 | 3.75 | false | true | false | false |
tgingold/ghdl | testsuite/synth/fsm01/fsm_2s.vhdl | 1 | 749 | library ieee;
use ieee.std_logic_1164.all;
entity fsm_2s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_2s;
architecture behav of fsm_2s is
type state_t is (S0_1, S1_0);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 9ae6cfe936c143c82afc6e9b57e3ac68 | 0.449933 | 3.187234 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/packer_12bit/tb_packer_128.vhd | 1 | 5,033 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_packer_128.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - tb_packer_128
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_packer_128 is
end tb_packer_128;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_packer_128 is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_200_MHZ : time := 5 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_300_MHZ : time := 3.3333 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal din : std_logic_vector(127 downto 0);
signal val_in : std_logic;
signal sample : std_logic_vector(15 downto 0);
signal dout : std_logic_vector(127 downto 0);
signal val_out : std_logic;
signal din_64bit : std_logic_vector(63 downto 0);
signal validin_64bit : std_logic;
signal dout_64bit : std_logic_vector(63 downto 0);
signal validout_64bit : std_logic;
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_100_MHZ / 2;
rst <= '0' after CLK_100_MHZ * 10;
rstn <= '1' after CLK_100_MHZ * 10;
-----------------------------------------------------------------------------------
-- Unit under test
-----------------------------------------------------------------------------------
packer_128_inst0 :
entity work.packer_128
port map (
clk_in => clk,
rst_in => rst,
val_in => val_in(127 downto 0),
data_in => din,
val_out => val_out(127 downto 0),
data_out => dout,
test_mode => '1'
);
--pack_16to12_inst0:
--entity work.pack_16to12
--port map(
-- clk => clk,
-- rst => rst,
-- enable => '1',
-- data_in_dval => validin_64bit,
-- data_in => din_64bit,
-- data_in_stop => open,
-- data_out_dval => dout_64bit,
-- data_out => validout_64bit,
-- data_out_stop => '0'
--);
-----------------------------------------------------------------------------------
-- Stimulus
-----------------------------------------------------------------------------------
process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
val_in <= '0';
sample <= (others=>'0');
else
val_in <= '1';
sample <= sample + 8;
end if;
end if;
end process;
--din(15 downto 0) <= sample + 0;
--din(31 downto 16) <= sample + 1;
--din(47 downto 32) <= sample + 2;
--din(63 downto 48) <= sample + 3;
--din(79 downto 64) <= sample + 4;
--din(95 downto 80) <= sample + 5;
--din(111 downto 96) <= sample + 6;
--din(127 downto 112) <= sample + 7;
din(15 downto 0) <= x"0" & x"AAA";
din(31 downto 16) <= x"0" & x"BBB";
din(47 downto 32) <= x"0" & x"CCC";
din(63 downto 48) <= x"0" & x"DDD";
din(79 downto 64) <= x"0" & x"EEE";
din(95 downto 80) <= x"0" & x"FFF";
din(111 downto 96) <= x"0" & x"999";
din(127 downto 112) <= x"0" & x"888";
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | e202094893a0a0a4c7a80a7fa619cf97 | 0.346116 | 4.391798 | false | false | false | false |
snow4life/PipelinedDLX | alu/carry_select_adder/carry_select_adder.vhd | 1 | 1,052 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use WORK.all;
entity CARRY_SELECT_ADDER is
port( A: in std_logic_vector(31 downto 0);
B: in std_logic_vector(31 downto 0);
S: out std_logic_vector(31 downto 0);
Ci: in std_logic;
Co: out std_logic
);
end entity CARRY_SELECT_ADDER;
architecture STRUCTURAL of CARRY_SELECT_ADDER is
signal CARRY: std_logic_vector(8 downto 0);
component CARRY_SELECT_BLOCK
generic (N: integer);
port ( A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
Ci:in std_logic;
S: out std_logic_vector(N-1 downto 0);
Co:out std_logic);
end component;
begin
RCA_GENERATE: for i in 0 to 7 generate
CSB : CARRY_SELECT_BLOCK
generic map (N=>4)
port map ( A => A(((i*4)+3) downto (i*4)),
B => B(((i*4)+3) downto (i*4)),
S => S(((i*4)+3) downto (i*4)),
Ci => CARRY(i),
Co => CARRY(i+1));
end generate;
CARRY(0) <= Ci;
Co <= CARRY(8);
end architecture STRUCTURAL;
| lgpl-2.1 | df4275401654ca517656dc9f0b438d59 | 0.631179 | 2.670051 | false | false | false | false |
nickg/nvc | test/jit/record4.vhd | 1 | 2,220 | package pack5 is
type int_vector is array (natural range <>) of integer;
type pair is record
first : integer;
second : integer;
end record;
type pair_ptr is access pair;
type pair_vector is array (natural range <>) of pair;
type pair_vector_ptr is access pair_vector;
function func1 (x : integer) return integer;
function func2 (x : integer) return integer;
function func3 (x : integer) return integer;
function func4 (x : integer) return integer;
end package;
package body pack5 is
function func1 (x : integer) return integer is
variable p : pair_vector_ptr;
variable result : integer := 0;
begin
p := new pair_vector(1 to x);
for i in 1 to x loop
p.all(i).first := i;
p.all(i).second := x;
end loop;
for i in p.all'range loop
result := result + p(i).first + p(i).second;
end loop;
return result;
end function;
function func2 (x : integer) return integer is
variable p : pair_vector(1 to x);
variable result : integer := 0;
begin
for i in 1 to x loop
p(i).first := i;
p(i).second := x;
end loop;
for i in p'range loop
result := result + p(i).first + p(i).second;
end loop;
return result;
end function;
function func3 (x : integer) return integer is
variable p : pair_ptr;
begin
p := new pair;
p.first := x;
p.second := x * 2;
return p.first + p.second;
end function;
function func4 (x : integer) return integer is
type rec is record
p : pair_vector(1 to x);
end record;
type rec_ptr is access rec;
variable rp : rec_ptr;
variable r : rec;
variable result : integer := 0;
begin
rp := new rec;
for i in 1 to x loop
rp.all.p(i).first := x;
rp.all.p(i).second := x * 2;
end loop;
r := rp.all;
for i in 1 to x loop
result := result + r.p(i).first + r.p(i).second;
end loop;
return result;
end function;
end package body;
| gpl-3.0 | dcc0cfa8a3ff8fc774a3c66baecccac4 | 0.53964 | 3.854167 | false | false | false | false |
nickg/nvc | test/sem/signal.vhd | 1 | 2,391 | entity e is
port (
p : in bit );
end entity;
architecture a of e is
signal v : bit_vector(1 to 3);
signal x, y, z : bit;
begin
process is
begin
(x, y, z) <= v; -- OK
(x, y, z) <= x; -- Error
(x, y, z) <= "101"; -- Error
(bit'('1'), y, z) <= v; -- Error
(others => x) <= v; -- Error
(p, y, z) <= v; -- Error
end process;
(x, y, z) <= v; -- OK
(x, y, z) <= x; -- Error
(bit'('1'), y, z) <= v; -- Error
(others => x) <= v; -- Error
(p, y, z) <= v; -- Error
process is
variable i : integer;
begin
(v(i), v(1), v(2)) <= v; -- Error
end process;
b1: block is
procedure proc1 (signal s : out bit) is
procedure nested is
begin
s <= '0'; -- OK
end procedure;
begin
x <= '1'; -- Error
s <= '1'; -- OK
end procedure;
begin
end block;
b2: block (true) is
begin
guard <= false; -- Error
end block;
b3: block is
signal guard : integer;
begin
x <= guarded not x; -- Error
end block;
b4: block (v) is -- Error
begin
end block;
b5: block is
constant guard : boolean := false;
begin
x <= guarded not x; -- Error
x <= null; -- Error
end block;
b6: block is
signal q : integer bus; -- Error
begin
end block;
b7: block is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
signal s : rbit bus; -- OK
disconnect s : rbit after 1 ns; -- OK
disconnect 'x' : character after 1 ns; -- Error
disconnect v : bit_vector after 1 ns; -- Error
disconnect s : bit_vector after 2 ns; -- Error
disconnect s : rbit after s; -- Error
signal i : integer;
disconnect s : rbit after i * ns; -- Error
begin
end block;
b8: block is
signal bad : bit := e; -- Error
begin
end block;
end architecture;
| gpl-3.0 | 056a0a4e1421dcba578f6554ed110cec | 0.406943 | 3.985 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd | 4 | 2,522 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_11_fg_11_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity misc_logic is
end entity misc_logic;
-- end not in book
use work.MVL4.all;
architecture gate_level of misc_logic is
signal src1, src1_enable : MVL4_ulogic;
signal src2, src2_enable : MVL4_ulogic;
signal selected_val : MVL4_logic;
-- . . .
begin
src1_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src1, enable => src1_enable, y => selected_val );
src2_buffer : entity work.tri_state_buffer(behavioral)
port map ( a => src2, enable => src2_enable, y => selected_val );
-- . . .
-- not in book
stimulus : process is
begin
wait for 10 ns;
src1_enable <= '0'; src2_enable <= '0'; wait for 10 ns;
src1 <= '0'; src2 <= '1'; wait for 10 ns;
src1_enable <= '1'; wait for 10 ns;
src1 <= 'Z'; wait for 10 ns;
src1 <= '1'; wait for 10 ns;
src1_enable <= '0'; wait for 10 ns;
src2_enable <= '1'; wait for 10 ns;
src2 <= 'Z'; wait for 10 ns;
src2 <= '0'; wait for 10 ns;
src2_enable <= '0'; wait for 10 ns;
src1_enable <= '1'; src2_enable <= '1'; wait for 10 ns;
src1 <= '0'; wait for 10 ns;
src1 <= 'X'; wait for 10 ns;
src1 <= '1'; src2 <= '1'; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture gate_level;
| gpl-2.0 | 32ba4f22d34296b53457fbd8ca3d93af | 0.552736 | 3.681752 | false | false | false | false |
nickg/nvc | test/regress/wait17.vhd | 1 | 415 | entity wait17 is
end entity;
architecture test of wait17 is
function func (x : bit) return bit_vector is
begin
return (0 to 7 => x);
end function;
signal result, x : bit;
begin
p1: result <= func(x)(0);
p2: process is
begin
assert result = '0';
x <= '1';
wait for 1 ns;
assert result = '1';
wait;
end process;
end architecture;
| gpl-3.0 | c0af254b42bca2823a4baaf21ca080f5 | 0.546988 | 3.640351 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/tb_memmux02.vhdl | 1 | 1,209 | entity tb_memmux02 is
end tb_memmux02;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux02 is
signal wen : std_logic;
signal addr : std_logic_vector (3 downto 0);
signal rdat : std_logic;
signal wdat : std_logic_vector (15 downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
dut : entity work.memmux02
port map (
wen => wen,
addr => addr,
rdat => rdat,
wdat => wdat,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
constant c : std_logic_vector (15 downto 0) := x"56bc";
begin
rst <= '1';
wen <= '0';
wdat <= c;
addr <= x"0";
pulse;
rst <= '0';
pulse;
assert rdat = '0' severity failure;
addr <= x"4";
wen <= '1';
pulse;
assert rdat = '0' severity failure;
wen <= '0';
pulse;
assert rdat = '1' severity failure;
for i in c'range loop
addr <= std_logic_vector (to_unsigned (i, 4));
pulse;
assert rdat = c(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | ef8a3b2e98f6588dfab74a7d84836f85 | 0.555831 | 3.321429 | false | false | false | false |
nickg/nvc | test/regress/case12.vhd | 1 | 800 | entity case12 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of case12 is
signal x : std_logic_vector(1 to 3);
signal y : natural;
begin
p1 : process (x) is
begin
y <= 0;
case? x is
when "111" => y <= 1;
when "000" => y <= 2;
when "1--" => y <= 3;
when "0--" => y <= 4;
when "--0" => y <= 5;
when others => y <= 6;
end case?;
end process;
p2 : process is
begin
x <= "000";
wait for 1 ns;
assert y = 2;
x <= "XXX";
wait for 1 ns;
assert y = 6;
x <= "11-"; -- Error
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
| gpl-3.0 | b8cccd9d61d6a702d34fe3ab788fbb52 | 0.41875 | 3.555556 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd | 4 | 2,628 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc570.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:34 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:32 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:06 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00570ent IS
END c03s04b01x00p01n01i00570ent;
ARCHITECTURE c03s04b01x00p01n01i00570arch OF c03s04b01x00p01n01i00570ent IS
type real_file is file of real;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_file open read_mode is "iofile.19";
variable v : real;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= 3.0) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00570"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00570 - File reading operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00570arch;
| gpl-2.0 | 2b23e7189e7155c4def2ad80c70f8b3f | 0.552131 | 3.975794 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/tb/common/my_config_ML605.vhdl | 2 | 1,809 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML605"; -- ML605 - Xilinx Virtex 6 reference design board: XC6VLX240T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
package body my_config is
end package body;
| gpl-2.0 | 1b8f68d1fda9d85eb96377dc957393aa | 0.585406 | 4.40146 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd | 4 | 2,008 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2459.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02459ent IS
END c07s03b02x02p03n02i02459ent;
ARCHITECTURE c07s03b02x02p03n02i02459arch OF c07s03b02x02p03n02i02459ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
signal V : CONSTRAINED_ARRAY;
BEGIN
TESTING: PROCESS
BEGIN
V <= ( others => '$' );
wait for 1 ns;
assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02459"
severity NOTE;
assert ( V(1)='$' and V(2)='$' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02459 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02459arch;
| gpl-2.0 | 00f6db4a4811168112a1ffd6667adfae | 0.661853 | 3.711645 | false | true | false | false |
nickg/nvc | test/simp/func9.vhd | 5 | 494 | entity func9 is
end entity;
architecture test of func9 is
constant msg0 : string := "zero";
constant msg1 : string := "one";
function get_message(x : in bit) return string is
begin
case x is
when '0' => return msg0;
when '1' => return msg1;
end case;
end function;
begin
process is
begin
assert get_message('1') = "one";
assert get_message('0') = "zero";
wait;
end process;
end architecture;
| gpl-3.0 | a3a452b26035cebd42c6b19a2d27d5fa | 0.560729 | 3.829457 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0105/econcat1_87.vhdl | 1 | 449 | entity econcat1_87 is
end econcat1_87;
architecture behav of econcat1_87 is
constant c1 : string (21 downto 17) := "hello";
constant c2 : string (6 downto 1) := " world";
constant r : string := c1 & c2;
begin
process
begin
case True is
when c1 & c2 = "hello world" => null;
when false => null;
end case;
assert r'left = 21 severity failure;
assert r'right = 11 severity failure;
wait;
end process;
end;
| gpl-2.0 | 281810cd32dd8a1521a155f9ca123c09 | 0.632517 | 3.427481 | false | false | false | false |
tgingold/ghdl | testsuite/synth/iassoc01/tb_iassoc12.vhdl | 1 | 510 | entity tb_iassoc12 is
end tb_iassoc12;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc12 is
signal a : natural;
signal b : natural;
signal v : natural;
begin
dut: entity work.iassoc12
port map (v, a, b);
process
begin
v <= 5;
wait for 1 ns;
assert a = 6 severity failure;
assert b = 7 severity failure;
v <= 203;
wait for 1 ns;
assert a = 204 severity failure;
assert b = 205 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 81efead9f2878647ef9bcfec9f67ed42 | 0.645098 | 3.445946 | false | false | false | false |
nickg/nvc | test/sem/protected.vhd | 1 | 3,743 | entity e is
end entity;
architecture a of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type bad1 is protected
procedure foo (x : not_here); -- Error
end protected;
type bad1 is protected body -- OK
end protected body;
type bad2 is protected body -- Error
end protected body;
type boolean is protected body -- Error
end protected body;
type now is protected body -- Error
end protected body;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
type SharedCounter is protected body -- Error
end protected body;
subtype s is SharedCounter; -- Error
shared variable x : integer; -- Error
shared variable y : SharedCounter; -- OK
shared variable z : SharedCounter := 1; -- Error
function make return SharedCounter is -- Error
variable result : SharedCounter;
begin
return result;
end function;
procedure proc(variable sh : in SharedCounter := make) is -- error
begin
end procedure;
begin
end architecture;
architecture a2 of e is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
procedure foo (x : in integer);
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
procedure bar (x : in integer ) is
begin
null;
end procedure;
procedure foo (x : in integer ) is
begin
bar(x + 1);
end procedure;
end protected body;
shared variable x : SharedCounter; -- OK
begin
process is
begin
x.increment(2); -- OK
x.increment; -- OK
x.counter := 5; -- Error
x.decrement(1, 2); -- Error
assert x.value = 5; -- OK
end process;
process is
function get_value (x : in sharedcounter ) return integer is -- Error
begin
return x.value; -- Error
end function;
begin
end process;
bad_assignment: process
variable y : SharedCounter;
variable z : SharedCounter;
begin
y := z; -- Error
wait;
end process;
end architecture;
package issue85 is
type protected_t is protected
procedure add(argument : inout protected_t); -- OK
end protected protected_t;
end package;
package pkg is
type protected_t is protected
end protected protected_t;
end package;
package body pkg is
-- Missing body for protected_t
end package body;
| gpl-3.0 | b180783081faafec340574a61d8d825b | 0.577879 | 4.99733 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1080/repro4.vhdl | 1 | 504 | library ieee;
use ieee.std_logic_1164.all;
entity repro4 is
generic (
num : natural := 1);
port (
clk : std_logic;
o : out std_logic);
end;
architecture behav of repro4 is
signal s : natural range 0 to num - 1 := 0;
begin
process (clk) is
begin
if rising_edge(clk) then
if s = 0 then
o <= '1';
else
o <= '0';
end if;
if s = num - 1 then
s <= 0;
else
s <= s + 1;
end if;
end if;
end process;
end behav;
| gpl-2.0 | 2228a81f05d318b539422249de690e3f | 0.513889 | 3.230769 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug017/call6b.vhdl | 2 | 374 | entity call6b is
end;
architecture behav of call6b is
type my_rec is record
a, b, c : character;
end record;
procedure check (s : my_rec) is
begin
wait for 1 ns;
assert s.b = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ((a => 'e', b => 'a', c => 'c'));
report "SUCCESS";
wait;
end process;
end behav;
| gpl-2.0 | 78126b648fa32ebcda1ca7af4db9d7cf | 0.569519 | 3.142857 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd | 4 | 1,761 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
-- code from book:
type alu_func is (pass1, pass2, add, subtract);
-- end of code from book
signal func : alu_func := pass1;
signal operand1 : integer := 10;
signal operand2 : integer := 3;
begin
process_2_a : process (func, operand1, operand2) is
variable result : integer := 0;
begin
-- code from book:
case func is
when pass1 =>
result := operand1;
when pass2 =>
result := operand2;
when add =>
result := operand1 + operand2;
when subtract =>
result := operand1 - operand2;
end case;
-- end of code from book
end process process_2_a;
stimulus : process is
begin
func <= pass2 after 10 ns,
add after 20 ns,
subtract after 30 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | b18614947c21755a67906a7de793710c | 0.645088 | 4.172986 | false | false | false | false |
nickg/nvc | test/regress/textio5.vhd | 1 | 811 | entity textio5 is
end entity;
use std.textio.all;
architecture test of textio5 is
begin
process is
file fptr : text;
variable l : line;
begin
file_open(fptr, "tmp.txt", WRITE_MODE);
write(l, string'("0123"));
tee(fptr, l);
write(l, string'("4567"));
tee(fptr, l);
assert l'length = 0;
file_close(fptr);
file_open(fptr, "tmp.txt", READ_MODE);
readline(fptr, l);
assert l.all = "0123";
readline(fptr, l);
assert l.all = "4567";
file_close(fptr);
assert justify("hello", right, 7) = " hello";
assert justify("hello", left, 0) = "hello";
assert justify("hello", left, 6) = "hello ";
deallocate(l);
wait;
end process;
end architecture;
| gpl-3.0 | 9375841da918d10aaa9b502eb65fed73 | 0.53021 | 3.620536 | false | false | false | false |
nickg/nvc | test/regress/const2.vhd | 1 | 1,322 | package pack is
function foo(x : in integer) return real;
end package;
package body pack is
type real_vector is array (integer range <>) of real;
function get_results return real_vector is
begin
return ( 52.6, 16.7, 1.832, 0.623, 762.236 );
end function;
constant results : real_vector := get_results;
function foo(x : in integer) return real is
begin
return results(x);
end function;
type int_vector is array (integer range <>) of integer;
subtype int_vector4 is int_vector(1 to 4);
constant blah : int_vector4 := ( 0, 1, 6, 6 );
constant blah2 : int_vector4 := blah;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity const2 is
end entity;
architecture test of const2 is
function get_it return integer is
begin
return integer(foo(integer'left + 1));
end function;
function get_bits return bit_vector is
begin
return "110101";
end function;
constant some_bits : bit_vector := get_bits;
constant a_bit : bit := some_bits(2);
begin
process is
begin
assert get_it = 17;
assert some_bits(some_bits'right) = '1';
assert a_bit = '0';
wait;
end process;
end architecture;
| gpl-3.0 | aae1722a981d8dfcd34d97270ac7c6a7 | 0.587746 | 3.888235 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd | 4 | 3,189 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc703.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:42 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00703ent IS
END c03s04b01x00p23n01i00703ent;
ARCHITECTURE c03s04b01x00p23n01i00703arch OF c03s04b01x00p23n01i00703ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
subtype STRING12 is STRING( 1 to 12 );
type FT is file of STRING12;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.56";
-- Declare a variable into which we will read.
constant CON : STRING12 := "hello, world";
variable VAR : STRING12;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00703"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00703 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00703arch;
| gpl-2.0 | 22f967fb31f041c19d740f19fde401b5 | 0.547507 | 4.021438 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd | 4 | 1,896 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of product_adder_subtracter is
begin
behavior : process (a, b) is
constant Tpd_in_out : time := 3 ns;
variable op2 : std_ulogic_vector(b'range);
variable carry_in : std_ulogic;
variable carry_out : std_ulogic;
begin
carry_out := To_X01(mode);
if To_X01(mode) = '1' then
op2 := not b;
else
op2 := b;
end if;
for index in 0 to 31 loop
carry_in := carry_out; -- of previous bit
s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
carry_out := (a(index) and op2(index))
or (carry_in and (a(index) xor op2(index)));
end loop;
s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
end process behavior;
end architecture behavioral;
| gpl-2.0 | 7731a6acb0235bcb2fa5b71bd6a4462b | 0.583333 | 3.941788 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func03/tb_func01.vhdl | 1 | 494 | entity tb_func01 is
end tb_func01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func01 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.func01
port map (a, b);
process
begin
a <= x"5d";
wait for 1 ns;
assert b = x"ba" severity failure;
a <= x"ff";
wait for 1 ns;
assert b = x"fe" severity failure;
a <= x"23";
wait for 1 ns;
assert b = x"46" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e75e1435945a78496fb1ab9d7631a4f1 | 0.61336 | 3.030675 | false | false | false | false |
nickg/nvc | test/regress/attr15.vhd | 1 | 1,182 | entity attr15 is
end entity;
architecture test of attr15 is
function double (x : in integer_vector) return integer_vector is
variable result : x'subtype;
begin
for i in result'range loop
result(i) := x(i) * 2;
end loop;
return result;
end function;
type int_vec_2d is array (natural range <>, natural range <>) of integer;
function double (x : in int_vec_2d) return int_vec_2d is
variable result : x'subtype;
begin
for i in result'range(1) loop
for j in result'range(2) loop
result(i, j) := x(i, j) * 2;
end loop;
end loop;
return result;
end function;
signal s1, s2 : integer_vector(1 to 5) := (others => 0);
signal s3, s4 : int_vec_2d(1 to 2, 5 to 5) := (others => (others => 0));
begin
p1: s2 <= double(s1);
p2: s4 <= double(s3);
check: process is
begin
s1 <= (1, 2, 3, 4, 5);
wait for 1 ns;
assert s2 = (2, 4, 6, 8, 10);
s3 <= ( (5 => 1), (5 => 2) );
wait for 1 ns;
assert s4 = ( (5 => 2), (5 => 4) );
wait;
end process;
end architecture;
| gpl-3.0 | a42c76c616e8e8a4605ec1d801080d4a | 0.516074 | 3.301676 | false | false | false | false |
nickg/nvc | test/regress/elab33.vhd | 1 | 1,324 | package pack is
type rec is record
x : integer;
y : bit_vector;
end record;
type rec_array is array (natural range <>) of rec;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i : in rec_array;
o1 : out integer_vector;
o2 : out bit_vector );
end entity;
architecture test of sub is
begin
g: for n in i'range generate
constant stride : natural := i(n).y'length;
begin
o1(n) <= i(n).x;
o2(1 + (n-1)*stride to n*stride) <= i(n).y;
end generate;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity elab33 is
end entity;
architecture test of elab33 is
signal a : rec_array(1 to 2)(y(1 to 3));
signal b : integer_vector(1 to 2);
signal c : bit_vector(1 to 6);
begin
u : entity work.sub
port map ( a, b, c );
check: process is
begin
a(1) <= (y => "101", x => 2);
wait for 1 ns;
assert b = (2, integer'left);
assert c = "101000";
a(2).x <= 5;
a(2).y <= "110";
wait for 1 ns;
assert b = (2, 5);
assert c = "101110";
wait;
end process;
end architecture;
| gpl-3.0 | 8bdf717f626c18ce01110447edfb1424 | 0.469033 | 3.617486 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_pntr.vhd | 7 | 22,062 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
ch2_eof_detected : in std_logic ; --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
tail_updt : in std_logic;
tail_updt_latch : out std_logic;
ch2_updt_done : in std_logic;
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic ; --
bd_eq : out std_logic
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal first : std_logic;
signal eof_latch : std_logic;
signal ch2_sg_idle_int : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch1_fetch_address <= ch1_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif((ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0'))then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch2_fetch_address <= ch2_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1' or ch2_eof_detected = '1')then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
ch2_sg_idle_int <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
-- Needed for multi channel
EOF_LATCH_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_taildesc_wren = '1' or eof_latch = '1')then -- nned to have some reset condition here
eof_latch <= '0';
elsif (ch2_sg_idle_int = '1' and ch2_updt_done = '1') then
eof_latch <= '1';
end if;
end if;
end process EOF_LATCH_PROC;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or eof_latch = '1')then -- nned to have some reset condition here
tail_updt_latch <= '0';
first <= '0';
elsif (tail_updt = '1') then
tail_updt_latch <= '0';
elsif(ch2_taildesc_wren = '1' and first = '0')then
first <= '1';
elsif(ch2_taildesc_wren = '1' and first = '1')then
tail_updt_latch <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
EQUAL_BD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
bd_eq <= '0';
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
bd_eq <= '0';
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
bd_eq <= '1';
end if;
end if;
end process EQUAL_BD;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
tail_updt_latch <= '0';
bd_eq <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
| gpl-3.0 | 4a4ab9a850e851bae92d71d70b5c5423 | 0.41814 | 4.808631 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug084/mod5.vhdl | 1 | 3,699 | library ieee;
use ieee.std_logic_1164.all;
entity mod5 is
generic (
NBITS: natural := 13
);
port (
clk: in std_logic;
dividend: in std_logic_vector (NBITS - 1 downto 0);
load: in std_logic;
remzero: out std_logic
);
end entity;
architecture foo of mod5 is
type remains is (r0, r1, r2, r3, r4); -- remainder values
type remain_array is array (NBITS downto 0) of remains;
signal remaindr: remain_array := (others => r0);
type branch is array (remains, bit) of remains;
-- Dave Tweeds state transition table:
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
begin
do_ig:
process (dividend)
variable tbit: bit_vector(NBITS - 1 downto 0);
variable remaind: remain_array := (others => r0);
begin
do_mod:
for i in NBITS - 1 downto 0 loop
tbit := to_bitvector(dividend);
remaind(i) := br_table(remaind(i + 1),tbit(i));
end loop;
remaindr <= remaind; -- all values for waveform display
end process;
remainders:
process (clk)
begin
if rising_edge(clk) then
if remaindr(0) = r0 then
remzero <= '1';
else
remzero <= '0';
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mod5_tb is
end entity;
architecture foo of mod5_tb is
constant NBITS: integer range 0 to 13 := 8;
signal clk: std_logic := '0';
signal dividend: std_logic_vector (NBITS - 1 downto 0);
signal load: std_logic := '0';
signal remzero: std_logic;
signal psample: std_ulogic;
signal sample: std_ulogic;
signal done: boolean;
begin
DUT:
entity work.mod5
generic map (NBITS)
port map (
clk => clk,
dividend => dividend,
load => load,
remzero => remzero
);
CLOCK:
process
begin
wait for 5 ns;
clk <= not clk;
if done'delayed(30 ns) then
wait;
end if;
end process;
STIMULI:
process
begin
for i in 0 to 2 ** NBITS - 1 loop
wait for 10 ns;
dividend <= std_logic_vector(to_unsigned(i,NBITS));
wait for 10 ns;
load <= '1';
wait for 10 ns;
load <= '0';
end loop;
wait for 15 ns;
done <= true;
wait;
end process;
SAMPLER:
process (clk)
begin
if rising_edge(clk) then
psample <= load;
sample <= psample;
end if;
end process;
MONITOR:
process (sample)
variable i: integer;
variable rem5: integer;
begin
if rising_edge (sample) then
i := to_integer(unsigned(dividend));
rem5 := i mod 5;
if rem5 = 0 and remzero /= '1' then
assert rem5 = 0 and remzero = '1'
report LF & HT &
"i = " & integer'image(i) &
" rem 5 expected " & integer'image(rem5) &
" remzero = " & std_ulogic'image(remzero)
SEVERITY ERROR;
end if;
end if;
end process;
end architecture; | gpl-2.0 | 55864ce378952e6571a1793b69822bee | 0.476075 | 3.897787 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/numeric_std_unsigned-body.vhdl | 2 | 18,190 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
end package body NUMERIC_STD_UNSIGNED;
| gpl-2.0 | b9e39737d1e47c4649063bef99a9085b | 0.549203 | 4.062081 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd | 4 | 3,365 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc467.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00467ent IS
END c03s02b01x01p19n01i00467ent;
ARCHITECTURE c03s02b01x01p19n01i00467arch OF c03s02b01x01p19n01i00467ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type real_vector is array (natural range <>) of real;
subtype real_vector_range is real_vector(hi_to_low_range);
constant C66: real_vector_range := (others => 3.0);
function complex_scalar(s : real_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real_vector_range;
signal S2 : real_vector_range;
signal S3 : real_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00467"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00467 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00467arch;
| gpl-2.0 | effe9358d0fa0680f35e802d5dc5b124 | 0.6526 | 3.61828 | false | true | false | false |
nickg/nvc | test/regress/signal23.vhd | 1 | 1,920 | -- Test case from Brian Padalino
--
library ieee ;
use ieee.std_logic_1164.all ;
package pack is
type iface_t is record
cs : std_logic ;
addr : std_logic_vector ;
rdata : std_logic_vector ;
wdata : std_logic_vector ;
end record ;
function init_iface_signals(addr_width : natural ; data_width : natural) return iface_t;
end package ;
package body pack is
function init_iface_signals(addr_width : natural ; data_width : natural) return iface_t is
variable rv : iface_t(addr(addr_width-1 downto 0), wdata(data_width-1 downto 0), rdata(data_width-1 downto 0)) ;
begin
rv.cs := '0' ;
rv.addr := (rv.addr'range => '0') ;
rv.wdata := (rv.wdata'range => '0') ;
rv.rdata := (rv.rdata'range => '0') ;
return rv ;
end function ;
end package body ;
library ieee ;
use ieee.std_logic_1164.all ;
use work.pack.all ;
entity master is
port (
clock : in std_logic ;
iface : inout iface_t := init_iface_signals(16, 32)
) ;
end entity ;
architecture arch of master is
begin
end architecture ;
library ieee ;
use ieee.std_logic_1164.all ;
use work.pack.all ;
entity signal23 is end entity ;
architecture arch of signal23 is
signal clock : std_logic := '0' ;
signal iface : iface_t(addr(15 downto 0), rdata(31 downto 0), wdata(31 downto 0)) ;
begin
clock <= not clock after 1 ns ;
U_master : entity work.master
port map (
clock => clock,
iface => iface
) ;
tb : process
begin
report LF &
"if:" & LF &
" cs: " & std_logic'image(iface.cs) & LF &
" addr: " & to_hstring(iface.addr) & LF &
" rdata: " & to_hstring(iface.rdata) & LF &
" wdata: " & to_hstring(iface.wdata) ;
std.env.stop ;
end process ;
end architecture ;
| gpl-3.0 | 4cb0d416e38940049043116a609662dd | 0.570313 | 3.362522 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0110/tb3.vhdl | 1 | 604 | package pkg3 is
type my_rec is record
adr : bit_vector (7 downto 0);
end record;
end pkg3;
use work.pkg3.all;
entity ent3 is
port (v : out my_rec;
b : in bit);
end ent3;
architecture behav of ent3 is
begin
v.adr <= (others => b);
end behav;
entity top3 is
end top3;
use work.pkg3.all;
architecture behav of top3 is
signal s : bit_vector (7 downto 0);
signal b : bit;
begin
dut : entity work.ent3
port map (
-- ERROR: missing 1 downto 0!
v.adr (3 downto 2) => s (3 downto 2),
v.adr (7 downto 6) => s (7 downto 6),
b => b);
b <= '0';
end behav;
| gpl-2.0 | f4c4207766b40efc971abe8af0406363 | 0.599338 | 2.889952 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1225/top.vhdl | 1 | 443 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top is
port (
clk, en : in std_logic;
a, b : in std_logic;
p, q : out std_logic
);
end entity;
architecture arch of top is
begin
process (clk, en, a)
variable tmp : std_logic;
begin
if en = '1' then
tmp := a;
p <= tmp;
else
p <= '0';
end if;
if rising_edge(clk) then
tmp := b;
q <= tmp;
end if;
end process;
end architecture;
| gpl-2.0 | 9bf95faa3224eedfc3c25e262cca8ad7 | 0.602709 | 2.502825 | false | false | false | false |
tgingold/ghdl | testsuite/synth/var01/var03.vhdl | 1 | 599 | library ieee;
use ieee.std_logic_1164.all;
entity var03 is
port (mask : std_logic_vector (1 downto 0);
a, b : std_logic_vector (15 downto 0);
res : out std_logic_vector (15 downto 0));
end var03;
architecture behav of var03 is
begin
process (all)
variable t : std_logic_vector (15 downto 0) := (others => '0');
variable hi, lo : integer;
begin
t := a;
for i in 0 to 1 loop
if mask (i) = '1' then
lo := i * 8;
hi := lo + 7;
t (hi downto lo) := b (hi downto lo);
end if;
end loop;
res <= t;
end process;
end behav;
| gpl-2.0 | b03caa0a3dc6e337d5d2e4d7b9421774 | 0.559265 | 3.152632 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd | 4 | 3,762 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_19 is
end entity fg_05_19;
architecture test of fg_05_19 is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
| gpl-2.0 | 0004449737b812ace3d940175730d442 | 0.614567 | 4.582217 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd | 4 | 2,428 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2952.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p24n01i02952pkg is
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
end c02s02b00x00p24n01i02952pkg;
use work.c02s02b00x00p24n01i02952pkg.all;
ENTITY c02s02b00x00p24n01i02952ent IS
END c02s02b00x00p24n01i02952ent;
ARCHITECTURE c02s02b00x00p24n01i02952arch OF c02s02b00x00p24n01i02952ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2) ; --- No_failure_here
wait for 5 ns;
assert NOT(S3='1' and S2=12)
report "***PASSED TEST: c02s02b00x00p24n01i02952"
severity NOTE;
assert (S3='1' and S2=12)
report "***FAILED TEST: c02s02b00x00p24n01i02952 - Subprogram declaration should appear before call of subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p24n01i02952arch;
package body c02s02b00x00p24n01i02952pkg is
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
assert (I1 /= '1')
report "No failure on test"
severity note;
assert (I3 /= 5)
report "No failure on test"
severity note;
I2 <= '1';
I3 <= 12;
end PX;
end c02s02b00x00p24n01i02952pkg;
| gpl-2.0 | 72a49696fb89a82def9c54540ac5fd09 | 0.666804 | 3.339752 | false | true | false | false |
tgingold/ghdl | testsuite/synth/var01/tb_var02.vhdl | 1 | 1,013 | entity tb_var02 is
end tb_var02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var02 is
signal clk : std_logic;
signal mask : std_logic_vector (3 downto 0);
signal val : std_logic_vector (31 downto 0);
signal res : std_logic_vector (31 downto 0);
begin
dut: entity work.var02
port map (
clk => clk,
mask => mask,
val => val,
res => res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
mask <= x"f";
val <= x"12_34_56_78";
pulse;
assert res = x"12_34_56_78" severity failure;
mask <= x"8";
val <= x"9a_00_00_00";
pulse;
assert res = x"9a_34_56_78" severity failure;
mask <= x"0";
val <= x"00_00_00_00";
pulse;
assert res = x"9a_34_56_78" severity failure;
mask <= x"5";
val <= x"00_bc_00_de";
pulse;
assert res = x"9a_bc_56_de" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 79d787872fb1fed2bc319d33d7097faa | 0.562685 | 2.997041 | false | false | false | false |
tgingold/ghdl | testsuite/synth/iassoc01/iassoc12.vhdl | 1 | 508 | use work.pkg.all;
entity riassoc12 is
port (v : natural;
res : out nat_rec);
end riassoc12;
architecture behav of riassoc12 is
begin
res.a <= v + 1;
res.b <= v + 2;
end behav;
entity iassoc12 is
port (v : natural;
a, b : out natural);
end iassoc12;
use work.pkg.all;
architecture behav of iassoc12 is
component riassoc12 is
port (v : natural;
res : out nat_rec);
end component;
begin
inst : riassoc12
port map (v => v, res.a => a, res.b => b);
end behav;
| gpl-2.0 | 819c5247a23de2f26a528a37787aacdc | 0.620079 | 3.097561 | false | false | false | false |
nickg/nvc | test/regress/agg3.vhd | 5 | 524 | entity agg3 is
end entity;
architecture test of agg3 is
type int_array is array (integer range <>) of integer;
function get_array return int_array is
begin
return (4 => 4, 3 => 3, 5 => 5);
end function;
begin
process is
variable x : int_array(1 to 3) := (others => 5);
variable y : integer;
begin
x := (6 => 7) & (6 => 2, 7 => 9);
assert x = (7, 2, 9);
x := get_array;
assert x = (3, 4, 5);
wait;
end process;
end architecture;
| gpl-3.0 | ca71ac089497e0ae9e5d65d89ca739d4 | 0.520992 | 3.447368 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CSA/32bits/CSA32bits/CSA32bits.vhd | 1 | 5,708 | -- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY CSA32bits IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (31 downto 0);
SomaResult: out std_logic_vector (31 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END CSA32bits ;
ARCHITECTURE strc_CSA32bits OF CSA32bits IS
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL Outs10, Outs11, Outs20, Outs21, Outs30, Outs31, Outs40, Outs41, Outs50, Outs51, Outs60, Outs61, Outs70, Outs71, Outs80, Outs81: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL Couts10, Couts11, Couts20, Couts21, Couts30, Couts31, Couts40, Couts41, Couts50, Couts51, Couts60, Couts61, Couts70, Couts71, Couts80, Couts81: STD_LOGIC;
SIGNAL sel1,sel2,sel3,sel4,sel5,sel6,sel7: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4,SomaT5,SomaT6,SomaT7,SomaT8:STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg32Bit
port(
valIn: in std_logic_vector(31 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(31 downto 0)
);
END COMPONENT ;
COMPONENT RCA
port (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (3 downto 0);
SomaResult: out std_logic_vector (3 downto 0);
CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT mux84
port (
In0, In1: in std_logic_vector(3 downto 0);
sel: in std_logic;
Outs : out std_logic_vector(3 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg32Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg32Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg32Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som10: RCA PORT MAP (
val1 => A_sig(3 DOWNTO 0),
val2 => B_sig(3 DOWNTO 0),
CarryIn=>'0',
CarryOut=>Couts10,
SomaResult=>Outs10
);
Som11: RCA PORT MAP (
val1 => A_sig(3 DOWNTO 0),
val2 => B_sig(3 DOWNTO 0),
CarryIn=>'1',
CarryOut=>Couts11,
SomaResult=>Outs11
);
Mux1: mux84 PORT MAP (
In1=>Outs11,
In0=>Outs10,
sel=>Cin_sig,
Outs=>SomaT1
);
sel1 <= Couts10 OR (Couts11 AND Cin_sig);
Som20: RCA PORT MAP (
val1 => A_sig(7 DOWNTO 4),
val2 => B_sig(7 DOWNTO 4),
CarryIn=>'0',
CarryOut=>Couts20,
SomaResult=>Outs20
);
Som21: RCA PORT MAP (
val1 => A_sig(7 DOWNTO 4),
val2 => B_sig(7 DOWNTO 4),
CarryIn=>'1',
CarryOut=>Couts21,
SomaResult=>Outs21
);
Mux2: mux84 PORT MAP (
In1=>Outs21,
In0=>Outs20,
sel=>sel1,
Outs=>SomaT2
);
sel2 <= Couts20 OR (Couts21 AND sel1);
--asdfasdf
Som30: RCA PORT MAP (
val1 => A_sig(11 DOWNTO 8),
val2 => B_sig(11 DOWNTO 8),
CarryIn=>'0',
CarryOut=>Couts30,
SomaResult=>Outs30
);
Som31: RCA PORT MAP (
val1 => A_sig(11 DOWNTO 8),
val2 => B_sig(11 DOWNTO 8),
CarryIn=>'1',
CarryOut=>Couts31,
SomaResult=>Outs31
);
Mux3: mux84 PORT MAP (
In1=>Outs31,
In0=>Outs30,
sel=>sel2,
Outs=>SomaT3
);
sel3 <= Couts30 OR (Couts31 AND sel2);
Som40: RCA PORT MAP (
val1 => A_sig(15 DOWNTO 12),
val2 => B_sig(15 DOWNTO 12),
CarryIn=>'0',
CarryOut=>Couts40,
SomaResult=>Outs40
);
Som41: RCA PORT MAP (
val1 => A_sig(15 DOWNTO 12),
val2 => B_sig(15 DOWNTO 12),
CarryIn=>'1',
CarryOut=>Couts41,
SomaResult=>Outs41
);
Mux4: mux84 PORT MAP (
In1=>Outs41,
In0=>Outs40,
sel=>sel3,
Outs=>SomaT4
);
sel4 <= Couts40 OR (Couts41 AND sel3);
--aaasdfasdfasdfasdf
Som50: RCA PORT MAP (
val1 => A_sig(19 DOWNTO 16),
val2 => B_sig(19 DOWNTO 16),
CarryIn=>'0',
CarryOut=>Couts50,
SomaResult=>Outs50
);
Som51: RCA PORT MAP (
val1 => A_sig(19 DOWNTO 16),
val2 => B_sig(19 DOWNTO 16),
CarryIn=>'1',
CarryOut=>Couts51,
SomaResult=>Outs51
);
Mux5: mux84 PORT MAP (
In1=>Outs51,
In0=>Outs50,
sel=>sel4,
Outs=>SomaT5
);
sel5 <= Couts50 OR (Couts51 AND sel4);
Som60: RCA PORT MAP (
val1 => A_sig(23 DOWNTO 20),
val2 => B_sig(23 DOWNTO 20),
CarryIn=>'0',
CarryOut=>Couts60,
SomaResult=>Outs60
);
Som61: RCA PORT MAP (
val1 => A_sig(23 DOWNTO 20),
val2 => B_sig(23 DOWNTO 20),
CarryIn=>'1',
CarryOut=>Couts61,
SomaResult=>Outs61
);
Mux6: mux84 PORT MAP (
In1=>Outs61,
In0=>Outs60,
sel=>sel5,
Outs=>SomaT6
);
sel6 <= Couts60 OR (Couts61 AND sel5);
--asdfasdf
Som70: RCA PORT MAP (
val1 => A_sig(27 DOWNTO 24),
val2 => B_sig(27 DOWNTO 24),
CarryIn=>'0',
CarryOut=>Couts70,
SomaResult=>Outs70
);
Som71: RCA PORT MAP (
val1 => A_sig(27 DOWNTO 24),
val2 => B_sig(27 DOWNTO 24),
CarryIn=>'1',
CarryOut=>Couts71,
SomaResult=>Outs71
);
Mux7: mux84 PORT MAP (
In1=>Outs71,
In0=>Outs70,
sel=>sel6,
Outs=>SomaT7
);
sel7 <= Couts70 OR (Couts71 AND sel6);
Som80: RCA PORT MAP (
val1 => A_sig(31 DOWNTO 28),
val2 => B_sig(31 DOWNTO 28),
CarryIn=>'0',
CarryOut=>Couts80,
SomaResult=>Outs80
);
Som81: RCA PORT MAP (
val1 => A_sig(31 DOWNTO 28),
val2 => B_sig(31 DOWNTO 28),
CarryIn=>'1',
CarryOut=>Couts81,
SomaResult=>Outs81
);
Mux8: mux84 PORT MAP (
In1=>Outs81,
In0=>Outs80,
sel=>sel7,
Outs=>SomaT8
);
Cout_sig <= Couts80 OR (Couts81 AND sel7);
Out_sig <= SomaT8 & SomaT7 & SomaT6 & SomaT5 & SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CSA32bits ; | mit | 56696519c6014e77b950489feae1454e | 0.628416 | 2.552773 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd | 4 | 6,569 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3124.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p01n01i03124ent_a IS
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
END c05s02b01x02p01n01i03124ent_a;
ARCHITECTURE c05s02b01x02p01n01i03124arch_a OF c05s02b01x02p01n01i03124ent_a IS
BEGIN
socket_p1 <= socket_g1 after 22 ns;
socket_p2 <= socket_g2 after 22 ns;
socket_p3 <= socket_g3 after 22 ns;
socket_p4 <= socket_g4 after 22 ns;
socket_p5 <= socket_g5 after 22 ns;
socket_p6 <= socket_g6 after 22 ns;
socket_p7 <= socket_g7 after 22 ns;
socket_p8 <= socket_g8 after 22 ns;
socket_p9 <= socket_g9 after 22 ns;
END c05s02b01x02p01n01i03124arch_a;
ENTITY c05s02b01x02p01n01i03124ent IS
END c05s02b01x02p01n01i03124ent;
ARCHITECTURE c05s02b01x02p01n01i03124arch OF c05s02b01x02p01n01i03124ent IS
component ic_socket
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
end component;
signal socket_p1 : Boolean;
signal socket_p2 : Bit;
signal socket_p3 : character;
signal socket_p4 : severity_level;
signal socket_p5 : integer;
signal socket_p6 : real;
signal socket_p7 : time;
signal socket_p8 : natural;
signal socket_p9 : positive;
BEGIN
instance : ic_socket
generic map ( true,
'1',
'$',
warning,
-100002,
-9.999,
20 ns,
23423,
4564576
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***PASSED TEST: c05s02b01x02p01n01i03124"
severity NOTE;
assert ( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***FAILED TEST: c05s02b01x02p01n01i03124 - Positional association generic and port list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p01n01i03124arch;
configuration c05s02b01x02p01n01i03124cfg of c05s02b01x02p01n01i03124ent is
for c05s02b01x02p01n01i03124arch
for instance : ic_socket use entity work.c05s02b01x02p01n01i03124ent_a (c05s02b01x02p01n01i03124arch_a)
generic map ( true,
'1',
'$',
warning,
-100002,
-9.999,
20 ns,
23423,
4564576
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
end for;
end for;
end c05s02b01x02p01n01i03124cfg;
| gpl-2.0 | 5317260f6bb9481ef0255edf951f4e40 | 0.484092 | 4.092835 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/w_split5.vhd | 2 | 1,359 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity w_split5 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end w_split5;
architecture augh of w_split5 is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
signal ram : ram_type := (
"00000111", "00000111"
);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | bb4ea7f5e5d4e7b57e4c7e7f22beb4c7 | 0.66961 | 2.843096 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1090/simple_ram-orig.vhdl | 1 | 1,599 | -- A simple pre-initalized RAM, which reads from a binary file at synthesis time
-- single 32 bit read/write port.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bootrom.all;
entity simple_ram is
generic (
-- 32-bit read/write port. ADDR_WIDTH is in bytes, not words.
ADDR_WIDTH : integer := 8 -- default 32k
);
port (
clk : in std_logic;
en : in std_logic;
raddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
do : out std_logic_vector(31 downto 0);
we : in std_logic_vector(3 downto 0);
waddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
di : in std_logic_vector(31 downto 0)
);
end simple_ram;
architecture behavioral of simple_ram is
constant NUM_WORDS : integer := 2**(ADDR_WIDTH - 2);
signal ram : rom_t := work.bootrom.rom; -- FIXME init internal error
begin
process (clk, en)
variable read : std_logic_vector(31 downto 0);
begin
if clk'event and clk = '1' then -- and en = '1' then -- Unsupported: clock enable
if we(3) = '1' then
ram(to_integer(unsigned(waddr)))(31 downto 24) <= di(31 downto 24);
end if;
if we(2) = '1' then
ram(to_integer(unsigned(waddr)))(23 downto 16) <= di(23 downto 16);
end if;
if we(1) = '1' then
ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= di(15 downto 8 );
end if;
if we(0) = '1' then
ram(to_integer(unsigned(waddr)))(7 downto 0 ) <= di(7 downto 0 );
end if;
read := ram(to_integer(unsigned(raddr)));
do <= read;
end if;
end process;
end behavioral;
| gpl-2.0 | 8057d3b59b92166bd1ed23f9f40231aa | 0.614759 | 3.276639 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1273/tb_assert3.vhdl | 1 | 651 | entity tb_assert3 is
generic (with_err : boolean := False);
end tb_assert3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_assert3 is
signal v : std_logic_Vector (7 downto 0);
signal en : std_logic := '0';
signal res : natural;
begin
dut: entity work.assert3
port map (v, en, res);
process
begin
wait for 1 ns;
en <= '1';
v <= b"0010_0000";
wait for 1 ns;
assert res = 5 severity failure;
-- Trigger an error.
if with_err then
en <= '1';
v <= b"0000_0010";
wait for 1 ns;
assert res = 1 severity failure;
end if;
wait;
end process;
end behav;
| gpl-2.0 | 1eca96a0913216c58ab7db48449df218 | 0.599078 | 3.271357 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/sub_125.vhd | 2 | 1,735 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_125 is
port (
le : out std_logic;
sign : in std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_125;
architecture augh of sub_125 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
le <= tmp_le;
end architecture;
| gpl-2.0 | a72e72f338167a06db1cd58e07aecd17 | 0.626513 | 2.593423 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1471.vhd | 4 | 1,734 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1471.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p03n01i01471ent IS
END c08s08b00x00p03n01i01471ent;
ARCHITECTURE c08s08b00x00p03n01i01471arch OF c08s08b00x00p03n01i01471ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 0;
BEGIN
case x is
when 1 => NULL;
when 2 => NULL:
when 3 => NULL;
when others => ;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p03n01i01471 - missing sequence of statement in a case alternative"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p03n01i01471arch;
| gpl-2.0 | 750ec912139cb9a110c044ec4f232b97 | 0.656286 | 3.794311 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd | 4 | 2,902 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3099.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p09n01i03099ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p09n01i03099ent;
ARCHITECTURE c05s01b00x00p09n01i03099arch OF c05s01b00x00p09n01i03099ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
ATTRIBUTE attr1 OF s1,s2,s3,s4,s5,s6,s7 : SIGNAL IS 101;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 101 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 101 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 101 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 101 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 101 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 101 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 101 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 101 and
s2'attr1 = 101 and
s3'attr1 = 101 and
s4'attr1 = 101 and
s5'attr1 = 101 and
s6'attr1 = 101 and
s7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p09n01i03099"
severity NOTE;
assert ( s1'attr1 = 101 and
s2'attr1 = 101 and
s3'attr1 = 101 and
s4'attr1 = 101 and
s5'attr1 = 101 and
s6'attr1 = 101 and
s7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p09n01i03099 - Attribute specification applies to the entity designators list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p09n01i03099arch;
| gpl-2.0 | b9e6fa23036bca2691b5415218df5d8e | 0.627843 | 3.509069 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_207.vhd | 2 | 1,762 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_207 is
port (
ge : out std_logic;
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_207;
architecture augh of sub_207 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
ge <= tmp_ge;
le <= tmp_le;
end architecture;
| gpl-2.0 | 6869b3a5d6772b13b081ed9c00349f5f | 0.622588 | 2.568513 | false | false | false | false |
nickg/nvc | test/regress/vhpi4.vhd | 1 | 1,151 | entity vhpi4 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of vhpi4 is
function sum (x, y : integer) return integer;
attribute foreign of sum : function is "VHPIDIRECT __vhpi_sum";
type int_vec is array (natural range <>) of integer;
function sum_array (a : int_vec; len : integer) return integer;
attribute foreign of sum_array : function is "VHPIDIRECT __vhpi_sum_array";
function my_not (x : std_logic) return std_logic;
attribute foreign of my_not : function is "VHPIDIRECT __vhpi_my_not";
procedure test_proc (x : out integer; arr : out int_vec);
attribute foreign of test_proc : procedure is "VHPIDIRECT __vhpi_test_proc";
begin
main: process is
variable i : integer;
variable v : int_vec(1 to 3);
begin
assert sum(2, 3) = 5;
assert sum_array(int_vec'(1, 2, 3, 4, 5), 5) = 15;
assert my_not('1') = '0';
assert my_not('0') = '1';
assert my_not('U') = 'U';
test_proc(i, v);
assert i = 42;
assert v = (integer'left, 5, integer'left);
wait;
end process;
end architecture;
| gpl-3.0 | ea1da7148d503e60e2930b82df935036 | 0.612511 | 3.49848 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug24065/cic_up.vhd | 2 | 8,011 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cic_up is
generic(
num_bits : natural := 16; -- How many bits in our incoming data?
num_stages : natural := 3; -- How many stages in the CIC? (N)
resamp : natural := 32; -- By what factor are we changing our data rate? (R)
diff_dly : natural := 1; -- The differential delay (M)
out_rate : natural := 8); -- Number of clocks per output sample
-- Must be a power of two
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- Input ports
data_i : in std_logic_vector(num_bits-1 downto 0);
valid_i : in std_logic;
-- Output samples
data_o : out std_logic_vector;
valid_o : out std_logic);
end entity cic_up;
architecture behavior of cic_up is
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
function log(b,n: positive) return natural is
variable temp : natural := 1;
variable answer : natural := 0;
begin
while temp < n loop
answer := answer + 1;
temp := temp * b;
end loop;
return answer;
end function log;
-----------------------------------------------------------------------------
function signed_add(l,r: std_logic_vector) return std_logic_vector is
variable resized_r : signed(r'high+1 downto r'low);
begin
resized_r := resize(signed(r), r'length+1);
return std_logic_vector(signed(l) + resized_r);
end function signed_add;
-----------------------------------------------------------------------------
function signed_sub(l,r: std_logic_vector) return std_logic_vector is
variable resized_r : signed(r'high+1 downto r'low);
begin
resized_r := resize(signed(r), r'length+1);
return std_logic_vector(signed(l) - resized_r);
end function signed_sub;
-----------------------------------------------------------------------------
impure function input_bits return natural is
variable a, b, c : integer;
begin
a := (num_bits + 1);
b := (num_stages - 2)*(log(2,resamp));
c := (num_stages - 1)*(log(2,diff_dly));
return a + b + c;
end function input_bits;
-----------------------------------------------------------------------------
impure function output_bits return natural is
variable a, b, c : integer;
begin
a := (num_bits + 0);
b := (num_stages - 1)*(log(2,resamp));
c := (num_stages - 0)*(log(2,diff_dly));
return a + b + c;
end function output_bits;
-----------------------------------------------------------------------------
-- Types, subtypes, and constants
-----------------------------------------------------------------------------
-- Bit growth constants
constant direction : string := "up";
subtype int_i_range is natural range input_bits-1 downto 0;
subtype int_o_range is natural range output_bits-1 downto 0;
subtype comb_sum_range is natural range num_bits downto 0;
subtype count_range is natural range log(2,out_rate)-1 downto 0;
-- Array type for differential delay
subtype word is std_logic_vector(num_bits-1 downto 0);
type comb_reg_type is array (integer range <>) of word;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal comb_reg : comb_reg_type(0 to diff_dly-1) := (others => (others => '0'));
signal comb_sum : std_logic_vector(comb_sum_range):= (others => '0');
signal int_in : std_logic_vector(int_i_range);
signal int_sum : signed (int_o_range) := (others => '0');
signal int_en : std_logic;
signal count : unsigned(count_range) := (others => '0');
signal c_dly : std_logic;
begin
-----------------------------------------------------------------------------
-- Map outputs
-----------------------------------------------------------------------------
data_o <= std_logic_vector(int_sum);
-----------------------------------------------------------------------------
-- Comb (derivative) section
-----------------------------------------------------------------------------
comb_proc : process(clk_i)
begin
if rising_edge(clk_i) then
-- Comb registers
if rst_i = '1' then
comb_reg <= (others => (others => '0'));
comb_sum <= (others => '0');
elsif valid_i = '1' then
comb_reg <= data_i & comb_reg(0 to comb_reg'high-1);
comb_sum <= signed_sub(data_i, comb_reg(comb_reg'high));
end if;
end if;
end process comb_proc;
-----------------------------------------------------------------------------
-- Integrator section
-----------------------------------------------------------------------------
int_proc : process(clk_i)
begin
if rising_edge(clk_i) then
-- Integrator registers
if rst_i = '1' then
int_sum <= (others => '0');
else
if num_stages = 1 then
-- The connection between the ints and the combs is determined
-- by the generic out_rate. This is indirectly controlled by
-- the top bit in count, which counts to out_rate.
if out_rate = 1 then
valid_o <= '1';
else
valid_o <= count(count'left) and not c_dly;
end if;
-- The size of the first integrator register could be a different
-- size from the last stage of the combs. This should make up
-- that difference.
if valid_i = '1' then
int_sum <= resize(int_sum + signed(comb_sum), int_sum'length);
end if;
-- Every other stage of the integrators is controlled by the enable
-- signal of the previous stage
elsif int_en = '1' then
int_sum <= int_sum + signed(int_in);
valid_o <= '1';
else
valid_o <= '0';
end if;
end if;
end if;
end process int_proc;
-----------------------------------------------------------------------------
-- Recursive instantiation and termination
-----------------------------------------------------------------------------
cic_gen : if num_stages > 1 generate
begin
cic_inst : entity work.cic_up
generic map(
num_bits => num_bits+1,
num_stages => num_stages-1,
diff_dly => diff_dly,
resamp => resamp,
out_rate => out_rate)
port map(
clk_i => clk_i,
rst_i => rst_i,
-- Input ports
data_i => comb_sum,
valid_i => valid_i,
-- Output samples
data_o => int_in,
valid_o => int_en);
end generate cic_gen;
valid_gen : if num_stages = 1 generate
begin
vary_valid_o : if out_rate /= 1 generate
begin
valid_o_proc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
count <= (others => '0');
c_dly <= '0';
else
count <= count + 1;
c_dly <= count(count'left);
end if;
end if;
end process valid_o_proc;
end generate vary_valid_o;
end generate valid_gen;
end architecture behavior;
| gpl-2.0 | 811652e7e5caaf6d9652092fe2ac0410 | 0.424416 | 4.546538 | false | false | false | false |
tgingold/ghdl | testsuite/synth/match01/tb_match01.vhdl | 1 | 590 | entity tb_match01 is
end tb_match01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_match01 is
signal a : std_logic_vector(3 downto 0);
signal z : std_logic;
begin
dut: entity work.match01
port map (a, z);
process
begin
a <= "1000";
wait for 1 ns;
assert z = '1' severity failure;
a <= "1010";
wait for 1 ns;
assert z = '1' severity failure;
a <= "0000";
wait for 1 ns;
assert z = '0' severity failure;
a <= "0001";
wait for 1 ns;
assert z = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 053fc23f39ca28af3a965cf36331287c | 0.60339 | 3.206522 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth14/top.vhdl | 1 | 1,133 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.top_pack.all;
entity top is port (
clk : in std_logic;
D : out std_logic_vector(1 to 5));
end top;
architecture beh of top is
signal this_c : top_reg_t;
signal this_r : top_reg_t;
-- signal rst : std_logic := '0';
begin
led : process(this_r, clk)
variable this : top_reg_t;
variable en : std_logic;
begin
this := this_r;
en := '0';
if this.prescale < 5000000 then en := '1'; end if;
this.y := to_slv(this.count, this.blip, en);
if this.prescale > 5999999 then
this.prescale := 0;
this.blip := '1';
if this.count = 3 then
this.count := 0;
else
this.count := this.count + 1;
end if;
else
if this.prescale = 1000000 then this.blip := '0'; end if;
this.prescale := this.prescale + 1;
end if;
this_c <= this;
end process;
led_r0 : process(clk)
begin
if clk = '1' and clk'event then
this_r <= this_c;
end if;
end process;
D <= this_r.y;
end beh;
| gpl-2.0 | 2889b6dec8fad5812765ab82411266c5 | 0.55075 | 3.087193 | false | false | false | false |
lfmunoz/vhdl | templates/host_interface/std_logic_textio.vhd | 4 | 18,485 | ----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
| mit | 59391995957d3d61a8350e6b685d3e31 | 0.606708 | 2.878387 | false | false | false | false |
tgingold/ghdl | testsuite/synth/mem01/tb_dpram2.vhdl | 1 | 823 | entity tb_dpram2 is
end tb_dpram2;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram2 is
signal raddr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal waddr : std_logic_vector(3 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
dut: entity work.dpram2
port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
raddr <= "0000";
waddr <= x"a";
wdat <= x"5a";
pulse;
raddr <= x"a";
waddr <= x"7";
wdat <= x"87";
pulse;
assert rdat = x"5a" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 6b2d191c19ad3ac5711cf70ce3ffaab5 | 0.585662 | 3.305221 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd | 4 | 1,839 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1463.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01463ent IS
END c08s08b00x00p02n01i01463ent;
ARCHITECTURE c08s08b00x00p02n01i01463arch OF c08s08b00x00p02n01i01463ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
variable k : integer := 0;
BEGIN
case x is
when 1 => k := 5;
when 2 => NULL;
when 3 => NULL;
when others => NULL;
end case;
assert NOT( k=5 )
report "***PASSED TEST: c08s08b00x00p02n01i01463"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c08s08b00x00p02n01i01463 - missing reserved word 'when'"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01463arch;
| gpl-2.0 | dd0d6cc370d8cd0938249ab4799033fe | 0.650353 | 3.656064 | false | true | false | false |
tgingold/ghdl | testsuite/synth/asgn01/tb_asgn09.vhdl | 1 | 764 | entity tb_asgn09 is
end tb_asgn09;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn09 is
signal a, b, c, d : std_logic_vector (1 downto 0);
signal sel : std_logic_vector(1 downto 0);
signal o : std_logic_vector (3 downto 0);
begin
dut: entity work.asgn09
port map (a, b, c, d, sel, o);
process
begin
a <= "10";
b <= "01";
c <= "00";
d <= "11";
sel <= "00";
wait for 1 ns;
assert o = "1110" severity failure;
sel <= "01";
wait for 1 ns;
assert o = "1101" severity failure;
sel <= "10";
wait for 1 ns;
assert o = "1100" severity failure;
sel <= "11";
wait for 1 ns;
assert o = "1111" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | dc3349094d845813215319ec6a7896b1 | 0.562827 | 3.131148 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split3.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split3 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split3;
architecture augh of output_split3 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 9455470593992ef7e091d38e937f2a54 | 0.673759 | 2.895277 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug24326/tb_thingy9.vhdl | 2 | 353 | entity tb_thingy is
end tb_thingy;
architecture tb of tb_thingy is
component thingy is
generic (
a_a : integer
);
port (
x%x : in bit; -- <==
y_y : out bit
);
end component;
signal stimuli : bit;
signal response : bit;
begin
dut : thingy
generic map (
a_a => 42
)
port map (
x_x => stimuli,
y_y => response
);
end tb;
| gpl-2.0 | ca39631e4578feb2435f098061986e4d | 0.592068 | 2.557971 | false | false | false | false |
nickg/nvc | test/sem/varinit.vhd | 1 | 1,663 | entity computation is
end entity;
package my_logic is
type std_logic is ('0', '1');
type std_logic_vector is array (natural range <>) of std_logic;
type unsigned is array (natural range <>) of std_logic;
type signed is array (natural range <>) of std_logic;
function to_integer(x : unsigned) return integer;
end package;
use work.my_logic.all;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
signal y : bit_vector(1 to bad'length); -- OK
begin
end architecture;
| gpl-3.0 | d658f98ce5528a94f353d169bdbc7684 | 0.628382 | 3.876457 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth121/fpadd_normalize_struct.vhdl | 1 | 6,171 | -- VHDL Entity work.FPadd_normalize.symbol
--
-- Created by
-- Guillermo Marcus, [email protected]
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY FPadd_normalize IS
PORT(
EXP_in : IN std_logic_vector (7 DOWNTO 0);
SIG_in : IN std_logic_vector (27 DOWNTO 0);
EXP_out : OUT std_logic_vector (7 DOWNTO 0);
SIG_out : OUT std_logic_vector (27 DOWNTO 0);
zero : OUT std_logic
);
-- Declarations
END FPadd_normalize ;
--
-- VHDL Architecture work.FPadd_normalize.struct
--
-- Created by
-- Guillermo Marcus, [email protected]
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ARCHITECTURE struct OF FPadd_normalize IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL EXP_lshift : std_logic_vector(7 DOWNTO 0);
SIGNAL EXP_rshift : std_logic_vector(7 DOWNTO 0);
SIGNAL SIG_lshift : std_logic_vector(27 DOWNTO 0);
SIGNAL SIG_rshift : std_logic_vector(27 DOWNTO 0);
SIGNAL add_in : std_logic_vector(7 DOWNTO 0);
SIGNAL cin : std_logic;
SIGNAL count : std_logic_vector(4 DOWNTO 0);
SIGNAL isDN : std_logic;
SIGNAL shift_RL : std_logic;
SIGNAL word : std_logic_vector(26 DOWNTO 0);
SIGNAL zero_int : std_logic;
SIGNAL denormal : std_logic;
SIGNAL lshift_cnt : std_logic_vector(4 DOWNTO 0);
-- Component Declarations
COMPONENT FPlzc
PORT (
word : IN std_logic_vector (26 DOWNTO 0);
zero : OUT std_logic ;
count : OUT std_logic_vector (4 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPlzc USE ENTITY work.FPlzc;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
-- eb1 1
SIG_rshift <= '0' & SIG_in(27 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));
-- HDL Embedded Text Block 2 eb2
-- eb2 2
add_in <= "000" & count;
-- limit the count to the exponent value
PROCESS(count,EXP_in)
BEGIN
IF (signed(count) > signed(EXP_in)) THEN
lshift_cnt <= EXP_in(4 downto 0)-1;
denormal <= '1';
ELSE
lshift_cnt <= count;
denormal <= '0';
END IF;
END PROCESS;
-- HDL Embedded Text Block 3 eb3
-- eb3 3
PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in, denormal)
BEGIN
IF (isDN='1') THEN
EXP_out <= X"00";
SIG_out <= SIG_in;
ELSE
IF (shift_RL='1') THEN
-- Shift Right
IF (SIG_in(27)='1') THEN
EXP_out <= EXP_rshift;
SIG_out <= SIG_rshift;
ELSE
EXP_out <= EXP_in;
SIG_out <= SIG_in;
END IF;
ELSE
-- Shift Left
IF (denormal='1') THEN
EXP_out <= (OTHERS => '0');
SIG_out <= SIG_lshift;
ELSE
EXP_out <= EXP_lshift;
SIG_out <= SIG_lshift;
END IF;
END IF;
END IF;
END PROCESS;
-- HDL Embedded Text Block 4 eb4
-- eb4 4
zero <= zero_int AND NOT SIG_in(27);
-- HDL Embedded Text Block 5 eb5
-- eb5 5
word <= SIG_in(26 DOWNTO 0);
-- HDL Embedded Text Block 6 eb6
-- eb6 6
PROCESS(SIG_in,EXP_in)
BEGIN
IF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in=X"01")) THEN
isDN <= '1';
shift_RL <= '0';
ELSIF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in/=X"00")) THEN
isDN <= '0';
shift_RL <= '0';
ELSE
isDN <= '0';
shift_RL <= '1';
END IF;
END PROCESS;
-- ModuleWare code(v1.1) for instance 'I3' of 'gnd'
cin <= '0';
-- ModuleWare code(v1.1) for instance 'I4' of 'inc'
I4combo: PROCESS (EXP_in)
VARIABLE t0 : std_logic_vector(8 DOWNTO 0);
VARIABLE sum : signed(8 DOWNTO 0);
VARIABLE din_l : std_logic_vector(7 DOWNTO 0);
BEGIN
din_l := EXP_in;
t0 := din_l(7) & din_l;
sum := (signed(t0) + '1');
EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
END PROCESS I4combo;
-- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
I1combo : PROCESS (SIG_in, lshift_cnt)
VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
VARIABLE temp : std_logic_vector (27 DOWNTO 0);
BEGIN
temp := (OTHERS=> 'X');
stemp := lshift_cnt;
temp := SIG_in;
FOR i IN 4 DOWNTO 0 LOOP
IF (i < 5) THEN
IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
dtemp := (OTHERS => '0');
dtemp(27 DOWNTO 2**i) := temp(27 - 2**i DOWNTO 0);
ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
dtemp := temp;
ELSE
dtemp := (OTHERS => 'X');
END IF;
ELSE
IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
dtemp := (OTHERS => '0');
ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
dtemp := temp;
ELSE
dtemp := (OTHERS => 'X');
END IF;
END IF;
temp := dtemp;
END LOOP;
SIG_lshift <= dtemp;
END PROCESS I1combo;
-- ModuleWare code(v1.1) for instance 'I2' of 'sub'
I2combo: PROCESS (EXP_in, add_in, cin)
VARIABLE mw_I2t0 : std_logic_vector(8 DOWNTO 0);
VARIABLE mw_I2t1 : std_logic_vector(8 DOWNTO 0);
VARIABLE diff : signed(8 DOWNTO 0);
VARIABLE borrow : std_logic;
BEGIN
mw_I2t0 := EXP_in(7) & EXP_in;
mw_I2t1 := add_in(7) & add_in;
borrow := cin;
diff := signed(mw_I2t0) - signed(mw_I2t1) - borrow;
EXP_lshift <= conv_std_logic_vector(diff(7 DOWNTO 0),8);
END PROCESS I2combo;
-- Instance port mappings.
I0 : FPlzc
PORT MAP (
word => word,
zero => zero_int,
count => count
);
END struct;
| gpl-2.0 | ae97658087b9940ef04dd20e1b1eaa1c | 0.558905 | 3.190796 | false | false | false | false |
nickg/nvc | test/sem/ports.vhd | 1 | 8,989 | package foo_pkg is
type my_int is range 0 to 100;
subtype my_int_sub is my_int range 10 to 20;
end package;
-------------------------------------------------------------------------------
use work.foo_pkg.all;
entity foo is
port (
o : out my_int;
i : in my_int );
end entity;
-------------------------------------------------------------------------------
architecture bar of foo is
begin
process is
variable x : my_int;
begin
x := i; -- OK
end process;
process is
variable x : my_int;
begin
-- Cannot read output
x := o;
end process;
process is
begin
o <= 24; -- OK
end process;
process is
begin
-- Cannot assign input
i <= 23;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is generic (str : string := "boo");
end entity;
use work.foo_pkg.all;
architecture test of top is
component foo is
port (
o : out my_int;
i : in my_int );
end component;
type int_vec is array (integer range <>) of integer;
component bar is
port (
i : in int_vec(1 to 10);
o : out int_vec(1 to 2) );
end component;
signal x, y : my_int;
begin
foo1: entity work.foo -- OK
port map (
o => x,
i => y );
foo2: entity work.foo -- OK
port map ( x, y );
foo3: entity work.foo
; -- Missing i association
foo4: entity work.foo -- Two associations for i
port map ( i => x, i => y,
o => x );
foo5: entity work.foo -- Too many ports
port map ( x, y, x, y );
foo6: entity work.foo -- No port cake
port map ( cake => 4 );
bad1: entity work.bad; -- No such entity
open1: entity work.foo -- OK
port map (
i => x,
o => open );
open2: entity work.foo -- Cannot use OPEN with input
port map (
i => open,
o => open );
foo7: foo -- OK
port map (
o => x,
i => y );
foo8: component foo -- OK
port map (
o => x,
i => y );
bad2: component x -- Not component
port map (
a => 1,
b => 2 );
b1: block is
signal x : int_vec(1 to 10);
signal y : int_vec(1 to 2);
signal k : integer;
begin
bar1: bar -- OK
port map (
o(1 to 10) => x(1 to 10),
i(1 to 2) => y(1 to 2) );
bar2: bar -- OK
port map (
o(1 to 4) => x(1 to 4),
o(5 to 10) => x(5 to 10),
i(1 to 2) => y(1 to 2) );
bar3: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to 10) => x(3 to 10),
i => y );
bar4: bar
port map (
o(1) => x(1),
o(2) => x(k), -- Error
o(3 to 10) => x(3 to 10),
i => y );
bar5: bar
port map (
o(1) => x(1),
o(q) => x(2), -- Error
o(3 to 10) => x(3 to 10),
i => y );
bar6: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to u) => x(3 to 10), -- Error
i => y );
bar7: bar
port map (
o(k) => x(1), -- Error
o(2) => x(2),
o(3 to 10) => x(3 to 10),
i => y );
bar8: bar
port map (
o(1) => x(1),
o(2) => x(2),
o(3 to k) => x(3 to 10), -- Error
i => y );
end block;
foo9: foo -- Error
port map (
o => x,
i => hello(5) );
foo10: foo
port map (
i => y ); -- OK
end architecture;
-------------------------------------------------------------------------------
architecture other of top is
type int_vec is array (integer range <>) of integer;
component comp1 is
port (
a : in integer := 5;
o : out int_vec );
end component;
signal s : int_vec(1 to 3);
begin
c1: component comp1 -- OK
port map (
a => open,
o => s );
c2: component comp1
port map (
a => 5,
o => open ); -- Error
c3: component comp1
port map (
a => 1.0, -- Error
o => s );
end architecture;
-------------------------------------------------------------------------------
architecture conv of top is
type int_vec1 is array (integer range <>) of integer;
type int_vec2 is array (integer range <>) of integer;
type my_int1 is range 0 to 1;
component comp1 is
port (
i : in int_vec1(1 to 3);
n : in my_int1 := 5;
o : out int_vec2(1 to 3) );
end component;
component comp2 is
port (
i : in int_vec1 );
end component;
component comp3 is
port (
b : out bit );
end component;
component comp4 is
port (
b : inout bit );
end component;
function func1(x : in bit) return my_int1;
function func2(x : in bit; y : in integer := 5) return my_int1;
function func3(x : in bit) return integer;
function func4(x : in integer) return bit;
signal x : int_vec1(1 to 3);
signal y : int_vec2(1 to 3);
signal z : bit;
signal i : integer;
shared variable b : bit;
begin
c1: component comp1
port map ( i => int_vec1(y) ); -- OK
c2: component comp2
port map ( i => int_vec1(y) ); -- Error
c3: component comp1
port map ( i => x,
n => func1(z) ); -- OK
c4: component comp1
port map ( i => x,
n => func2(z) ); -- Error
c6: component comp1
port map ( i => int_vec1(y),
o => int_vec2(x) ); -- Error
c7: component comp3
port map ( func3(b) => i ); -- OK
c8: component comp1
port map ( i => (1, 1, 1),
int_vec1(o) => x ); -- OK
c9: component comp1
port map ( int_vec2(i) => y, -- Error
int_vec1(o) => x );
c10: component comp3
port map ( func3(b) => open ); -- Error
c11: component comp4
port map ( func3(b) => func4(i) ); -- OK
c12: component comp4
port map ( '0' ); -- Error
c13: component comp4
port map ( b ); -- Error
end architecture;
entity ent_with_vec is
port ( x : in bit_vector(3 downto 0);
y : out bit_vector(3 downto 0) );
end entity;
architecture test of ent_with_vec is
begin
x(1) <= '0'; -- Error
y(1) <= y(0); -- Error
end architecture;
-------------------------------------------------------------------------------
architecture other2 of top is
procedure assign(x : out integer) is
begin
x := 5;
end procedure;
procedure assign_and_check(x : inout integer) is
begin
assign(x); -- OK
assert x = 5;
end procedure;
procedure bad(variable x : in integer) is
begin
assign(x);
end procedure;
begin
end architecture;
-------------------------------------------------------------------------------
architecture actual_func of top is
component comp is
port (
i : in integer );
end component;
signal s : integer;
function "not"(x : integer) return integer;
function foo(x : integer; y : integer := 2) return integer;
begin
c1: component comp
port map (
i => "not"(s) ); -- OK
c2: component comp
port map (
i => not s ); -- Error, not treated as conversion func
c3: component comp
port map (
i => foo(s) ); -- Error, not treated as conversion func
c4: component comp
port map (
i => "not"(1) ); -- OK (not a conversion function)
c5: component comp
port map (
"not"(5) => s ); -- Error
end architecture;
| gpl-3.0 | 4c347b631f13876c474850f9e1eee4fa | 0.387362 | 4.087767 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/synth/design_1_axi_timer_0_0.vhd | 1 | 9,208 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_timer_0_0_arch : ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "design_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
| gpl-3.0 | b514f6a585092f8a88e57fefaf3921a4 | 0.690921 | 3.289746 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd | 4 | 4,342 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity nor_gate is
generic ( width : positive;
Tpd01, Tpd10 : delay_length );
port ( input : in std_logic_vector(0 to width - 1);
output : out std_logic );
end entity nor_gate;
architecture primitive of nor_gate is
function max ( a, b : delay_length ) return delay_length is
begin
if a > b then
return a;
else
return b;
end if;
end function max;
begin
reducer : process (input) is
variable result : std_logic;
begin
result := '0';
for index in input'range loop
result := result or input(index);
end loop;
if not result = '1' then
output <= not result after Tpd01;
elsif not result = '0' then
output <= not result after Tpd10;
else
output <= not result after max(Tpd01, Tpd10);
end if;
end process reducer;
end architecture primitive;
library ieee; use ieee.std_logic_1164.all;
library cell_lib;
entity interlock_control is
end entity interlock_control;
-- code from book
architecture detailed_timing of interlock_control is
component nor_gate is
generic ( input_width : positive );
port ( input : in std_logic_vector(0 to input_width - 1);
output : out std_logic );
end component nor_gate;
for ex_interlock_gate : nor_gate
use entity cell_lib.nor_gate(primitive)
generic map ( width => input_width,
Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates
-- . . .
-- not in book
signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
-- end not in book
begin
ex_interlock_gate : component nor_gate
generic map ( input_width => 2 )
port map ( input(0) => reg_access_hazard,
input(1) => load_hazard,
output => stall_ex_n);
-- . . .
-- not in book
reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
'0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
'0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
'0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
-- end not in book
end architecture detailed_timing;
-- end code from book
| gpl-2.0 | 8858477972be9d1554f7d30aa14f85af | 0.461999 | 4.962286 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth109/ram4.vhdl | 1 | 1,561 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram4 is
generic (
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkB : in std_logic;
enB : in std_logic;
weB : in std_logic;
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end ram4;
architecture behavioral of ram4 is
constant WIDTH : natural := WIDTHB / 4;
constant SIZE : natural := SIZEB * 4;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
begin
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(to_integer(unsigned(addrB)&"00")) := diB(WIDTH-1 downto 0);
ram(to_integer(unsigned(addrB)&"01")) := diB(2*WIDTH-1 downto WIDTH);
ram(to_integer(unsigned(addrB)&"10")) := diB(3*WIDTH-1 downto 2*WIDTH);
ram(to_integer(unsigned(addrB)&"11")) := diB(4*WIDTH-1 downto 3*WIDTH);
end if;
doB(WIDTH-1 downto 0) <= ram(to_integer(unsigned(addrB)&"00"));
doB(2*WIDTH-1 downto WIDTH) <= ram(to_integer(unsigned(addrB)&"01"));
doB(3*WIDTH-1 downto 2*WIDTH) <= ram(to_integer(unsigned(addrB)&"10"));
doB(4*WIDTH-1 downto 3*WIDTH) <= ram(to_integer(unsigned(addrB)&"11"));
end if;
end if;
end process;
end behavioral;
| gpl-2.0 | 478daa8805e83e87f61c76707fab2139 | 0.59385 | 3.258873 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1080/repro2.vhdl | 1 | 3,078 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro2 is
end repro2;
architecture behav of repro2 is
constant ERR_COUNT : natural := 3;
subtype byte_t is std_logic_vector(7 downto 0);
function I2S(a: integer; l: integer) return std_logic_vector is
begin
return std_logic_vector(TO_UNSIGNED(a,l));
end;
-- Generics and arrays don't mix; use this function to index.
constant TOTAL_MSGS : integer := ERR_COUNT + 2;
subtype msgidx_t is integer range 0 to TOTAL_MSGS-1;
impure function get_err_msg(n : integer) return string is
begin
case n is
when 0 => return "OK";
when 1 => return "START";
when 2 => return "ERR_MSG00"; -- Note +2 offset
when 3 => return "ERR_MSG01-1";
when 4 => return "ERR_MSG02--2";
when 5 => return "ERR_MSG03";
when 6 => return "ERR_MSG04";
when 7 => return "ERR_MSG05";
when 8 => return "ERR_MSG06";
when 9 => return "ERR_MSG07";
when 10 => return "ERR_MSG08";
when 11 => return "ERR_MSG09";
when 12 => return "ERR_MSG10";
when 13 => return "ERR_MSG11";
when 14 => return "ERR_MSG12";
when 15 => return "ERR_MSG13";
when 16 => return "ERR_MSG14";
when 17 => return "ERR_MSG15";
when others => return "UNK";
end case;
end function;
impure function get_err_len(n : msgidx_t) return integer is
constant msg : string := get_err_msg(n);
begin
return msg'length;
end function;
-- Calculate total length of all active messages (including startup).
impure function get_total_bytes return integer is
constant EXTRA_CHARS : integer := 2; -- Msg + CR + LF
variable total : integer := 0;
begin
for n in 0 to TOTAL_MSGS-1 loop
total := total + get_err_len(n) + EXTRA_CHARS;
end loop;
return total;
end function;
constant TOTAL_BYTES : integer := get_total_bytes;
-- Define terminal newline characters (CR+LF)
constant NEWLINE_CR : byte_t := i2s(13, 8);
constant NEWLINE_LF : byte_t := i2s(10, 8);
-- Create ROM array with all concatenated messages.
type array_t is array(0 to TOTAL_BYTES-1) of byte_t;
subtype romaddr_t is integer range 0 to TOTAL_BYTES-1;
impure function get_msg_array return array_t is
variable result : array_t := (others => (others => '0'));
variable ridx : integer := 0;
procedure append(constant msg : string) is
begin
-- Append the message to the output array.
for c in 0 to msg'length-1 loop
result(ridx) := i2s(character'pos(msg(msg'left+c)), 8);
ridx := ridx + 1;
end loop;
-- Then append the CR+LF characters.
result(ridx+0) := NEWLINE_CR;
result(ridx+1) := NEWLINE_LF;
ridx := ridx + 2;
end procedure;
begin
-- For each fixed message...
for n in 0 to TOTAL_MSGS-1 loop
append(get_err_msg(n));
end loop;
return result;
end function;
constant MESSAGE_ROM : array_t := get_msg_array;
begin
end behav;
| gpl-2.0 | a4da9d71e462d24aacfd1eaa4c719105 | 0.611111 | 3.521739 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue476/repro2/test_op.vhd | 2 | 1,818 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_op is
generic (
NBITS : natural := 1;
NBR_OF_CHROMA : natural := 1;
NBR_OF_ROW : natural := 1;
NBR_OF_COL : natural := 1;
NBR_OF_MATRIX : natural := 1);
port (
signal clock, rst : in std_logic;
signal in_data : in std_logic_vector(NBR_OF_MATRIX*NBR_OF_COL*NBR_OF_ROW*NBR_OF_CHROMA*NBITS-1 downto 0));
end entity test_op;
architecture rtl of test_op is
package local_pixel_pkg is new work.pixel_pkg
generic map (
NBITS => NBITS,
NBR_OF_CHROMA => NBR_OF_CHROMA
);
package local_pixel_column_pkg is new work.pixel_column_pkg
generic map (
NBITS => NBITS,
NBR_OF_CHROMA => NBR_OF_CHROMA,
NBR_OF_ROW => NBR_OF_ROW,
local_pixel_pkg => local_pixel_pkg
);
package local_pixel_matrix_pkg is new work.pixel_matrix_pkg
generic map (
NBITS => NBITS,
NBR_OF_CHROMA => NBR_OF_CHROMA,
NBR_OF_ROW => NBR_OF_ROW,
NBR_OF_COL => NBR_OF_COL,
local_pixel_column_pkg => local_pixel_column_pkg
);
use local_pixel_matrix_pkg.all;
signal input_pixel_matrix : TYPE_PIXEL_MATRIX;
begin
-- As soon as a function from the local_pixel_matrix_pkg is used it breaks
input_pixel_matrix <= std_logic_vector_to_pixel_matrix(in_data(NBR_OF_COL*NBR_OF_ROW*NBR_OF_CHROMA*NBITS-1 downto 0));
end architecture rtl;
| gpl-2.0 | a753daa2d782382d54d18d8ca4322cc3 | 0.49945 | 3.884615 | false | true | false | false |
nickg/nvc | test/regress/proc12.vhd | 1 | 1,052 | package pack is
procedure check (i, o : integer);
procedure debug (i, o : integer);
end package;
package body pack is
procedure check (i, o : integer) is
begin
assert i < o;
end procedure;
procedure debug (i, o : integer) is
begin
report "i=" & integer'image(i) & " o=" & integer'image(o);
end procedure;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( i : in integer;
o : out integer := integer'right );
begin
debug(i, o);
postponed check(i, o);
end entity;
architecture test of sub is
begin
o <= i + 1;
end architecture;
-------------------------------------------------------------------------------
entity proc12 is
end entity;
architecture test of proc12 is
signal i, o : integer;
begin
u: entity work.sub port map (i, o);
p1: process is
begin
i <= 5;
wait for 1 ns;
assert o = 6;
wait;
end process;
end architecture;
| gpl-3.0 | e654e0d67a7d4d0d98972aefc3011c4a | 0.501901 | 4.046154 | false | false | false | false |
nickg/nvc | test/regress/vests7.vhd | 1 | 50,336 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00517pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00517pkg;
USE work.c03s03b00x00p03n04i00517pkg.ALL;
ENTITY vests7 IS
END vests7;
ARCHITECTURE c03s03b00x00p03n04i00517arch OF vests7 IS
--
-- Access type declarations
--
TYPE at_scre_1 IS ACCESS t_scre_1 ;
TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_scre_1 : at_scre_1 ;
VARIABLE AV2_scre_1 : at_scre_1 ;
VARIABLE AV0_cca1_1 : at_cca1_1 ;
VARIABLE AV2_cca1_1 : at_cca1_1 ;
VARIABLE AV0_cca1_2 : at_cca1_2 ;
VARIABLE AV2_cca1_2 : at_cca1_2 ;
VARIABLE AV0_cca1_3 : at_cca1_3 ;
VARIABLE AV2_cca1_3 : at_cca1_3 ;
VARIABLE AV0_cca1_4 : at_cca1_4 ;
VARIABLE AV2_cca1_4 : at_cca1_4 ;
VARIABLE AV0_cmre_1 : at_cmre_1 ;
VARIABLE AV2_cmre_1 : at_cmre_1 ;
VARIABLE AV0_cmre_2 : at_cmre_2 ;
VARIABLE AV2_cmre_2 : at_cmre_2 ;
VARIABLE AV0_cca1_7 : at_cca1_7 ;
VARIABLE AV2_cca1_7 : at_cca1_7 ;
VARIABLE AV0_cmre_3 : at_cmre_3 ;
VARIABLE AV2_cmre_3 : at_cmre_3 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_scre_1 := NEW t_scre_1 ;
AV0_cca1_1 := NEW t_cca1_1 ;
AV0_cca1_2 := NEW t_cca1_2 ;
AV0_cca1_3 := NEW t_cca1_3 ;
AV0_cca1_4 := NEW t_cca1_4 ;
AV0_cmre_1 := NEW t_cmre_1 ;
AV0_cmre_2 := NEW t_cmre_2 ;
AV0_cca1_7 := NEW t_cca1_7 ;
AV0_cmre_3 := NEW t_cmre_3 ;
---
AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
--
--
ASSERT AV0_scre_1.all = C0_scre_1
REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
ASSERT AV2_scre_1.all = C2_scre_1
REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
ASSERT AV0_cca1_1.all = C0_cca1_1
REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
ASSERT AV2_cca1_1.all = C2_cca1_1
REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
ASSERT AV0_cca1_2.all = C0_cca1_2
REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
ASSERT AV2_cca1_2.all = C2_cca1_2
REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
ASSERT AV0_cca1_3.all = C0_cca1_3
REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
ASSERT AV2_cca1_3.all = C2_cca1_3
REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
ASSERT AV0_cca1_4.all = C0_cca1_4
REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
ASSERT AV2_cca1_4.all = C2_cca1_4
REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
ASSERT AV0_cmre_1.all = C0_cmre_1
REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
ASSERT AV2_cmre_1.all = C2_cmre_1
REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
ASSERT AV0_cmre_2.all = C0_cmre_2
REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
ASSERT AV2_cmre_2.all = C2_cmre_2
REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
ASSERT AV0_cca1_7.all = C0_cca1_7
REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
ASSERT AV2_cca1_7.all = C2_cca1_7
REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
ASSERT AV0_cmre_3.all = C0_cmre_3
REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
ASSERT AV2_cmre_3.all = C2_cmre_3
REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***PASSED TEST: c03s03b00x00p03n04i00517"
severity NOTE;
assert ( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00517arch;
| gpl-3.0 | ff7a9e814dba9adc004852774051cfe9 | 0.576188 | 2.588501 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd | 4 | 1,248 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity S_R_flipflop is
port ( s, r : in bit; q, q_n : out bit );
end entity S_R_flipflop;
--------------------------------------------------
architecture functional of S_R_flipflop is
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
check : assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
end architecture functional;
| gpl-2.0 | 0dc9f7a4cee3f1be03ad0340d4b42afa | 0.652244 | 3.759036 | false | false | false | false |
nickg/nvc | test/regress/elab8.vhd | 5 | 1,228 | entity sub is
port (
foo : out bit_vector(1 to 3) );
end entity;
architecture test of sub is
begin
process is
begin
foo <= "101";
wait for 10 ns;
foo <= "010";
wait for 10 ns;
foo <= "100";
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab8 is
end entity;
architecture test of elab8 is
signal bar : bit_vector(1 to 3);
signal a, b, c : bit;
begin
sub1_i: entity work.sub
port map (
foo(1) => bar(3),
foo(2) => bar(2),
foo(3) => bar(1) );
sub2_i: entity work.sub
port map (
foo(1) => a,
foo(2) => b,
foo(3) => c );
process is
begin
wait for 1 ns;
assert a = '1';
assert b = '0';
assert c = '1';
assert bar = "101";
wait for 10 ns;
assert a = '0';
assert b = '1';
assert c = '0';
assert bar = "010";
wait for 10 ns;
assert a = '1';
assert b = '0';
assert c = '0';
assert bar = "001";
wait;
end process;
end architecture;
| gpl-3.0 | f4e2e5f149c6e4d2cfa7a2bae56c42a1 | 0.416938 | 3.743902 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_utils_v3_0_6/xbip_utils_v3_0_vh_rfs.vhd | 9 | 157,786 | `protect begin_protected
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`protect end_protected
| gpl-3.0 | ce6e1b40c118da3a9d8564a8e4af8941 | 0.953976 | 1.832547 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue937/tb_enot.vhdl | 1 | 492 | entity tb_enot is
end tb_enot;
architecture behav of tb_enot is
signal i : bit;
signal x : boolean;
signal o : bit;
begin
dut: entity work.enot
port map (i, x, o);
process
begin
i <= '0';
x <= false;
wait for 1 ns;
assert o = '0' severity failure;
i <= '1';
x <= false;
wait for 1 ns;
assert o = '1' severity failure;
i <= '1';
x <= True;
wait for 1 ns;
assert o = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 714953f398aba8776ffd47cb9293731a | 0.552846 | 3.113924 | false | false | false | false |
nickg/nvc | test/parse/access.vhd | 1 | 473 | entity ee is end entity;
architecture aa of ee is
type int_ptr is access integer;
type bv_ptr is access bit_vector;
begin
process is
variable x, p : int_ptr;
variable v : integer;
variable a : bv_ptr;
variable q : bit_vector(1 to 3);
variable r : bit;
begin
x.all := 1;
v := x.all + 5;
p := new integer;
q := a.all(1 to 3);
r := a.all(3);
end process;
end architecture;
| gpl-3.0 | cfc85b9b8e06766cbf40302a22f62344 | 0.530655 | 3.529851 | false | false | false | false |
tgingold/ghdl | testsuite/synth/insert01/tb_insert01.vhdl | 1 | 586 | entity tb_insert01 is
end tb_insert01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_insert01 is
signal a : std_logic_vector (3 downto 0);
signal b : std_logic;
signal o0, o1, o2, o3 : std_logic_vector (3 downto 0);
begin
dut: entity work.insert01
port map (a, b, o0, o1, o2, o3);
process
begin
a <= "0111";
b <= '0';
wait for 1 ns;
assert o0 = "0110" severity failure;
assert o1 = "0101" severity failure;
assert o2 = "0011" severity failure;
assert o3 = "0111" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | e0e536da9615b017d0015679225803b7 | 0.643345 | 3.020619 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd | 4 | 2,837 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_11.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity RAM16x1 is
port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
\d\, \we\ : in std_ulogic;
\o\ : out std_ulogic );
end entity RAM16x1;
architecture a of RAM16x1 is
begin
end architecture a;
entity fg_a_11 is
end entity fg_a_11;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_11 is
-- code from book
component RAM16x1 is
port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
\d\, \we\ : in std_ulogic;
\o\ : out std_ulogic );
end component RAM16x1;
-- . . .
-- end code from book
signal address : std_ulogic_vector(3 downto 0);
signal raminp, ramout : std_ulogic_vector(15 downto 0);
signal write_enable : std_ulogic;
begin
-- code from book
g1 : for i in 0 to 15 generate
rama : component RAM16x1
port map ( \a<0>\ => address(0),
\a<1>\ => address(1),
\a<2>\ => address(2),
\a<3>\ => address(3),
\d\ => raminp ( i ),
\we\ => write_enable,
\o\ => ramout ( i ) );
end generate g1;
-- end code from book
end architecture test;
| gpl-2.0 | 329443e74ac08d96b2c6a8984dc0f293 | 0.451181 | 4.481833 | false | false | false | false |
tgingold/ghdl | testsuite/synth/memmux01/tb_memmux07.vhdl | 1 | 929 | entity tb_memmux07 is
end tb_memmux07;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux07 is
signal ad : std_logic;
signal val : std_logic_vector (1 downto 0);
signal dat, res : std_logic_vector (7 downto 0);
begin
dut : entity work.memmux07
port map (
ad => ad,
val => val,
dat => dat,
res => res);
process
begin
dat <= x"de";
ad <= '0';
val <= "00";
wait for 1 ns;
assert res = x"dc" severity failure;
ad <= '1';
val <= "00";
wait for 1 ns;
assert res = x"ce" severity failure;
ad <= '0';
val <= "01";
wait for 1 ns;
assert res = x"dd" severity failure;
ad <= '0';
val <= "10";
wait for 1 ns;
assert res = x"de" severity failure;
ad <= '1';
val <= "10";
wait for 1 ns;
assert res = x"ee" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 23c38d3edb21d769a862e853e99b373f | 0.555436 | 3.203448 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd | 4 | 2,296 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2159.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02159ent IS
END c07s02b04x00p21n01i02159ent;
ARCHITECTURE c07s02b04x00p21n01i02159arch OF c07s02b04x00p21n01i02159ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_5 is severity_level_v (1 to 5);
SUBTYPE severity_level_4 is severity_level_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : severity_level_5;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***PASSED TEST: c07s02b04x00p21n01i02159"
severity NOTE;
assert ((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
report "***FAILED TEST: c07s02b04x00p21n01i02159 - Concatenation of element and SEVERITY_LEVEL array failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02159arch;
| gpl-2.0 | f4f9f61cd690c52409bdb303da2ac16e | 0.675523 | 3.644444 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd | 4 | 2,221 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity buf is
port ( a : in std_logic; y : out std_logic );
end entity buf;
architecture basic of buf is
begin
y <= a;
end architecture basic;
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity fanout_tree is
generic ( height : natural );
port ( input : in std_logic;
output : out std_logic_vector (0 to 2**height - 1) );
end entity fanout_tree;
--------------------------------------------------
architecture recursive of fanout_tree is
begin
degenerate_tree : if height = 0 generate
begin
output(0) <= input;
end generate degenerate_tree;
compound_tree : if height > 0 generate
signal buffered_input_0, buffered_input_1 : std_logic;
begin
buf_0 : entity work.buf(basic)
port map ( a => input, y => buffered_input_0 );
subtree_0 : entity work.fanout_tree(recursive)
generic map ( height => height - 1 )
port map ( input => buffered_input_0,
output => output(0 to 2**(height - 1) - 1) );
buf_1 : entity work.buf(basic)
port map ( a => input, y => buffered_input_1 );
subtree_1 : entity work.fanout_tree(recursive)
generic map ( height => height - 1 )
port map ( input => buffered_input_1,
output => output(2**(height - 1) to 2**height - 1) );
end generate compound_tree;
end architecture recursive;
-- end code from book
| gpl-2.0 | 0b7e52742422c19cbb38f7cb9b399e41 | 0.656011 | 3.816151 | false | false | false | false |
nickg/nvc | test/regress/gensub6.vhd | 1 | 1,113 | entity gensub6 is
end entity;
architecture test of gensub6 is
procedure proc
generic (procedure preal(value : out real);
procedure pint(value : out integer))
(x : out integer; y : out real) is
begin
preal(y);
pint(x);
end procedure;
procedure get generic (type t; n : t) (x : out t) is
begin
x := n;
end procedure;
procedure get_one is new get generic map (t => integer, n => 1);
procedure get_one is new get generic map (t => real, n => 1.0);
procedure get_two is new get generic map (t => integer, n => 2);
procedure get_two is new get generic map (t => real, n => 2.0);
procedure proc_one is new proc generic map (preal => get_one, get_one);
procedure proc_two is new proc generic map (preal => get_two, get_two);
begin
p1: process is
variable i : integer;
variable r : real;
begin
proc_one(i, r);
assert i = 1;
assert r = 1.0;
proc_two(i, r);
assert i = 2;
assert r = 2.0;
wait;
end process;
end architecture;
| gpl-3.0 | c255995cab37791b6d0e958e7f4f3551 | 0.565139 | 3.64918 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1220/tb_top.vhdl | 1 | 795 | entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal x, y : std_logic_vector (1 downto 0);
signal data : std_logic_vector (3 downto 0);
begin
dut: entity work.top
port map (clk, x, y, data);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
x <= "00";
y <= "00";
pulse;
assert data = "0001" severity failure;
x <= "10";
pulse;
assert data = "1110" severity failure;
y <= "01";
pulse;
assert data = "1101" severity failure;
x <= "10";
y <= "11";
pulse;
assert data = "0111" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | a81f4847f7010055ba136c8d44e79779 | 0.559748 | 3.3125 | false | false | false | false |
nickg/nvc | test/regress/func12.vhd | 5 | 994 | entity func12 is
end entity;
architecture test of func12 is
function popcnt_high(value : in bit_vector(7 downto 0)) return natural is
variable cnt : natural := 0;
begin
report integer'image(value'left);
for i in 7 downto 4 loop
report bit'image(value(i));
if value(i) = '1' then
cnt := cnt + 1;
end if;
end loop;
return cnt;
end function;
function get_bits(v : in bit_vector(7 downto 0)) return bit_vector is
begin
for i in v'range loop
report integer'image(i) & " = " & bit'image(v(i));
end loop;
return v;
end function;
begin
process is
variable v : bit_vector(0 to 7) := X"05";
begin
assert popcnt_high(v) = 0;
v := X"f0";
assert popcnt_high(v) = 4;
assert popcnt_high(get_bits(X"20")) = 1;
--assert popcnt_high(v(0 to 3)) = 2;
wait;
end process;
end architecture;
| gpl-3.0 | c0bff84e65f4d77cf4a9865cb88a3809 | 0.539235 | 3.627737 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue467/AbstractMmPkg.vhd | 1 | 18,112 | -------------------------------------------------------------------------------
-- Title : Abstract Memory-Mapped Interface
-- Project :
-------------------------------------------------------------------------------
-- File : AbstractMmPkg.vhd
-- Author : Rob Gaddi <[email protected]>
-- Company : Highland Technology, Inc.
-- Created : 20-Nov-2017
-- Last update: 2017-11-25
-- Platform : Simulation
-- Standard : VHDL-2008
-------------------------------------------------------------------------------
-- Description: Support package for abstract memory-mapped interface BFMs.
-------------------------------------------------------------------------------
-- Revision History:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.AlertLogPkg.all;
use osvvm.TbUtilPkg.all;
use osvvm.ResolutionPkg.all;
package AbstractMmPkg is
-----------------------------------------------------------------------
-- Constants and Types
-----------------------------------------------------------------------
type AlertLogIDArrayType is array(integer range <>) of AlertLogIDType;
function alert_resolver(ta: AlertLogIDArrayType) return AlertLogIDType;
subtype ResolvedAlert is alert_resolver AlertLogIDType;
-- Transaction types
type TransactionType_unresolved is (
NONE,
SINGLE,
LINEAR_BURST,
CONSTANT_BURST,
CYCLE_BURST,
BURST_DATA,
PARAM
);
type TransactionArrayType is array(integer range <>) of TransactionType_unresolved;
function resolved(ta: TransactionArrayType) return TransactionType_unresolved;
subtype TransactionType is resolved TransactionType_unresolved;
type AbstractMmRecType is record
writedata : std_logic_vector;
readdata : std_logic_vector;
address : unsigned;
byteen : std_logic_vector;
write : std_logic;
burstlen : integer_max;
trans : TransactionType;
addressiswords : std_logic;
alert : ResolvedAlert;
rdy : std_logic;
ack : std_logic;
end record AbstractMmRecType;
constant AMR_READ: std_logic := '0';
constant AMR_WRITE: std_logic := '1';
constant AMR_ADDRESS_BYTES : std_logic := '0';
constant AMR_ADDRESS_WORDS : std_logic := '1';
constant ALRT : AlertLogIDType := GetAlertLogID("AbstractMmPkg");
-----------------------------------------------------------------------
-- Driver Functions
-----------------------------------------------------------------------
-- AmrRead (single read)
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
);
-- AmrWrite (single write)
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
);
-- AmrAssert (single assert)
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
);
-----------------------------------------------------------------------
-- Model Support Functions
-----------------------------------------------------------------------
procedure InterpretByteEnable(
rec : in AbstractMmRecType;
width : out natural;
align : out natural
);
function GetByteAddress(rec: in AbstractMmRecType; unalign: boolean := false) return unsigned;
function GetWordAddress(rec: in AbstractMmRecType) return unsigned;
-----------------------------------------------------------------------
-- Utility Functions
-----------------------------------------------------------------------
-- Initialization
procedure InitializeAmr(signal rec: out AbstractMmRecType);
-- function INIT_AMR(datalen, addrlen : positive) return AbstractMmRecType;
-- function INIT_AMR(datalen, addrlen, belen : positive) return AbstractMmRecType;
-- Selecting word/byte addressing
procedure SetAddressWords(signal rec: inout AbstractMmRecType);
procedure SetAddressBytes(signal rec: inout AbstractMmRecType);
-- Overriding the default alert
procedure OverrideAlert(signal rec: inout AbstractMmRecType; alert: AlertLogIDType);
end package AbstractMmPkg;
package body AbstractMmPkg is
procedure InitializeAmr(signal rec: out AbstractMmRecType) is
variable local : AbstractMmRecType(
writedata(rec.writedata'range),
readdata(rec.readdata'range),
address(rec.address'range),
byteen(rec.byteen'range)
);
constant WD : std_logic_vector(rec.writedata'range) := (others => 'Z');
constant RD : std_logic_vector(rec.readdata'range) := (others => 'Z');
constant AD : unsigned(rec.address'range) := (others => 'Z');
constant BE : std_logic_vector(rec.byteen'range) := (others => 'Z');
begin
local := (
writedata => WD,
readdata => RD,
address => AD,
byteen => BE,
write => 'Z',
burstlen => integer'left,
trans => NONE,
addressiswords => 'Z',
alert => ALRT,
rdy => 'Z',
ack => 'Z'
);
rec <= local;
end procedure InitializeAmr;
--function INIT_AMR(
-- datalen, addrlen : positive
--) return AbstractMmRecType is
-- constant belen : positive := datalen / 8;
--begin
-- return INIT_AMR(datalen, addrlen, belen);
--end function INIT_AMR;
--function INIT_AMR(
-- datalen, addrlen, belen: positive
--) return AbstractMmRecType is
--begin
-- return (
-- writedata => (datalen downto 1 => 'Z'),
-- readdata => (datalen downto 1 => 'Z'),
-- address => (addrlen downto 1 => 'Z'),
-- byteen => (belen downto 1 => 'Z'),
-- write => 'Z',
-- burstlen => integer'left,
-- trans => NONE,
-- addressiswords => 'Z',
-- alert => ALRT,
-- rdy => 'Z',
-- ack => 'Z'
-- );
--end function INIT_AMR;
procedure SetAddressWords(signal rec: inout AbstractMmRecType) is
begin
rec.addressiswords <= AMR_ADDRESS_WORDS;
end procedure SetAddressWords;
procedure SetAddressBytes(signal rec: inout AbstractMmRecType) is
begin
rec.addressiswords <= AMR_ADDRESS_BYTES;
end procedure SetAddressBytes;
-----------------------------------------------------------------------
-- AmrRead
-----------------------------------------------------------------------
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
constant WD : std_logic_vector(rec.writedata'range) := (others => 'X');
begin
rec.writedata <= WD;
rec.address <= RESIZE(addr, rec.address'length);
rec.byteen <= byteen;
rec.write <= AMR_READ;
rec.burstlen <= 1;
rec.trans <= SINGLE;
RequestTransaction(rec.rdy, rec.ack);
data := rec.readdata;
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
begin
AmrRead(data, UNSIGNED(addr), byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
begin
AmrRead(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
) is
variable byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrRead(data, addr, byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
variable byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrRead(data, UNSIGNED(addr), byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
) is
variable byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrRead(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrRead;
-----------------------------------------------------------------------
-- AmrWrite (single write)
-----------------------------------------------------------------------
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
begin
rec.writedata <= data;
rec.address <= RESIZE(addr, rec.address'length);
rec.byteen <= byteen;
rec.write <= AMR_WRITE;
rec.burstlen <= 1;
rec.trans <= SINGLE;
RequestTransaction(rec.rdy, rec.ack);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrWrite(data, UNSIGNED(addr), byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrWrite(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrWrite(data, addr, byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrWrite(data, UNSIGNED(addr), byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrWrite(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrWrite;
-----------------------------------------------------------------------
-- AmrAssert (single assert)
-----------------------------------------------------------------------
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
variable readdata : std_logic_vector(data'range);
begin
AmrRead(readdata, addr, byteen, rec);
--AffirmIfEqual(rec.alert, readdata, data, "Assert @ 0x" & TO_HSTRING(addr));
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrAssert(data, UNSIGNED(addr), byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrAssert(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrAssert(data, addr, byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrAssert(data, UNSIGNED(addr), byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrAssert(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrAssert;
-----------------------------------------------------------------------
-- Utility Functions
-----------------------------------------------------------------------
-- Turn a number into the number of bits needed to represent it.
function clog2(x : positive) return natural is
variable y : natural := 1;
begin
for log in 0 to 255 loop
if y >= x then
return log;
end if;
y := y * 2;
end loop;
return natural'right;
end function clog2;
-- Allow only 1 entry to be other than NONE.
function resolved(ta: TransactionArrayType) return TransactionType_unresolved is
variable r : TransactionType_unresolved := NONE;
variable t : TransactionType_unresolved;
begin
for idx in ta'range loop
t := ta(idx);
if t /= NONE then
assert r = NONE
report "Multiple non-NONE transaction types."
severity failure;
r := t;
end if;
end loop;
return r;
end function resolved;
-- Allow up to 1 entry to be other than our local ALRT, in which
-- case it wins.
function alert_resolver(ta: AlertLogIDArrayType) return AlertLogIDType is
variable r : AlertLogIDType := ALRT;
variable t : AlertLogIDType;
begin
for idx in ta'range loop
t := ta(idx);
if (t /= ALRT) and (t >= ALERTLOG_BASE_ID) then
assert r = ALRT
report "Multiple alerts provided."
severity failure;
r := t;
end if;
end loop;
return r;
end function alert_resolver;
procedure InterpretByteEnable(
rec : in AbstractMmRecType;
width : out natural;
align : out natural
) is
alias byteen : std_logic_vector(rec.byteen'range) is rec.byteen;
alias LA : AlertLogIDType is rec.alert;
variable first, last: integer;
variable found : boolean := false;
begin
if (and byteen) = '1' then
-- Try to provide fast resolution for the most common case.
width := byteen'length;
align := 0;
else
-- Alright, do it the hard way. Scan for contiguous enables.
for i in byteen'low to byteen'high loop
if byteen(i) = '1' then
found := true;
first := i;
exit;
end if;
end loop;
if not found then
-- No byte enables are set
Alert(LA, "No byte enables set.", WARNING);
width := 0;
align := 0;
else
last := first;
for i in first+1 to byteen'high loop
if byteen(i) = '1' then
last := i;
else
exit;
end if;
end loop;
if last /= byteen'high then
for i in last+1 to byteen'high loop
if byteen(i) = '1' then
Alert(LA, "Non-contiguous byte enables " & TO_STRING(byteen), WARNING);
exit;
end if;
end loop;
end if;
width := last-first+1;
align := first;
end if;
end if;
end procedure InterpretByteEnable;
function GetByteAddress(rec: in AbstractMmRecType; unalign: boolean := false) return unsigned is
variable padding : unsigned(clog2(rec.byteen'length)-1 downto 0);
variable alignment : integer := integer'left;
begin
case rec.addressiswords is
when AMR_ADDRESS_BYTES =>
return rec.address;
when AMR_ADDRESS_WORDS =>
if unalign then
for i in rec.byteen'low to rec.byteen'high loop
if rec.byteen(i) = '1' then
alignment := i;
exit;
end if;
end loop;
if alignment /= integer'left then
report "All bytes disabled." severity warning;
alignment := 0;
end if;
padding := TO_UNSIGNED(alignment, padding'length);
else
padding := (others => '0');
end if;
return rec.address & PADDING;
when others =>
report "Byte/word addressing not defined." severity failure;
return (rec.address'range => 'X');
end case;
end function GetByteAddress;
function GetWordAddress(rec: in AbstractMmRecType) return unsigned is
variable padding : unsigned(clog2(rec.byteen'length)-1 downto 0);
variable alignment, width : integer;
begin
case rec.addressiswords is
when AMR_ADDRESS_BYTES =>
return rec.address(rec.address'high downto padding'length);
when AMR_ADDRESS_WORDS =>
return rec.address;
when others =>
report "Byte/word addressing not defined." severity failure;
return (rec.address'range => 'X');
end case;
end function GetWordAddress;
procedure OverrideAlert(signal rec: inout AbstractMmRecType; alert: AlertLogIDType) is
begin
rec.alert <= alert;
end procedure OverrideAlert;
end package body AbstractMmPkg;
| gpl-2.0 | 3d2f6ad89ebf001b370a4a25beacacb9 | 0.633723 | 3.642067 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_doImgProc_0_2/synth/design_1_doImgProc_0_2.vhd | 1 | 18,279 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls_video:doImgProc:1.0
-- IP Revision: 1606211642
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doImgProc_0_2 IS
PORT (
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doImgProc_0_2;
ARCHITECTURE design_1_doImgProc_0_2_arch OF design_1_doImgProc_0_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doImgProc_0_2_arch: ARCHITECTURE IS "yes";
COMPONENT doImgProc IS
GENERIC (
C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER;
C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doImgProc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doImgProc_0_2_arch: ARCHITECTURE IS "doImgProc,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doImgProc_0_2_arch : ARCHITECTURE IS "design_1_doImgProc_0_2,doImgProc,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CRTL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CRTL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_KERNEL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_KERNEL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doImgProc
GENERIC MAP (
C_S_AXI_CRTL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CRTL_BUS_DATA_WIDTH => 32,
C_S_AXI_KERNEL_BUS_ADDR_WIDTH => 5,
C_S_AXI_KERNEL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CRTL_BUS_AWADDR => s_axi_CRTL_BUS_AWADDR,
s_axi_CRTL_BUS_AWVALID => s_axi_CRTL_BUS_AWVALID,
s_axi_CRTL_BUS_AWREADY => s_axi_CRTL_BUS_AWREADY,
s_axi_CRTL_BUS_WDATA => s_axi_CRTL_BUS_WDATA,
s_axi_CRTL_BUS_WSTRB => s_axi_CRTL_BUS_WSTRB,
s_axi_CRTL_BUS_WVALID => s_axi_CRTL_BUS_WVALID,
s_axi_CRTL_BUS_WREADY => s_axi_CRTL_BUS_WREADY,
s_axi_CRTL_BUS_BRESP => s_axi_CRTL_BUS_BRESP,
s_axi_CRTL_BUS_BVALID => s_axi_CRTL_BUS_BVALID,
s_axi_CRTL_BUS_BREADY => s_axi_CRTL_BUS_BREADY,
s_axi_CRTL_BUS_ARADDR => s_axi_CRTL_BUS_ARADDR,
s_axi_CRTL_BUS_ARVALID => s_axi_CRTL_BUS_ARVALID,
s_axi_CRTL_BUS_ARREADY => s_axi_CRTL_BUS_ARREADY,
s_axi_CRTL_BUS_RDATA => s_axi_CRTL_BUS_RDATA,
s_axi_CRTL_BUS_RRESP => s_axi_CRTL_BUS_RRESP,
s_axi_CRTL_BUS_RVALID => s_axi_CRTL_BUS_RVALID,
s_axi_CRTL_BUS_RREADY => s_axi_CRTL_BUS_RREADY,
s_axi_KERNEL_BUS_AWADDR => s_axi_KERNEL_BUS_AWADDR,
s_axi_KERNEL_BUS_AWVALID => s_axi_KERNEL_BUS_AWVALID,
s_axi_KERNEL_BUS_AWREADY => s_axi_KERNEL_BUS_AWREADY,
s_axi_KERNEL_BUS_WDATA => s_axi_KERNEL_BUS_WDATA,
s_axi_KERNEL_BUS_WSTRB => s_axi_KERNEL_BUS_WSTRB,
s_axi_KERNEL_BUS_WVALID => s_axi_KERNEL_BUS_WVALID,
s_axi_KERNEL_BUS_WREADY => s_axi_KERNEL_BUS_WREADY,
s_axi_KERNEL_BUS_BRESP => s_axi_KERNEL_BUS_BRESP,
s_axi_KERNEL_BUS_BVALID => s_axi_KERNEL_BUS_BVALID,
s_axi_KERNEL_BUS_BREADY => s_axi_KERNEL_BUS_BREADY,
s_axi_KERNEL_BUS_ARADDR => s_axi_KERNEL_BUS_ARADDR,
s_axi_KERNEL_BUS_ARVALID => s_axi_KERNEL_BUS_ARVALID,
s_axi_KERNEL_BUS_ARREADY => s_axi_KERNEL_BUS_ARREADY,
s_axi_KERNEL_BUS_RDATA => s_axi_KERNEL_BUS_RDATA,
s_axi_KERNEL_BUS_RRESP => s_axi_KERNEL_BUS_RRESP,
s_axi_KERNEL_BUS_RVALID => s_axi_KERNEL_BUS_RVALID,
s_axi_KERNEL_BUS_RREADY => s_axi_KERNEL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doImgProc_0_2_arch;
| gpl-3.0 | 116b9aaf622263db8da7e65ac168098e | 0.709995 | 3.226085 | false | false | false | false |
nickg/nvc | test/regress/wait16.vhd | 1 | 774 | entity wait16 is
end entity;
architecture test of wait16 is
type int_vec is array (natural range <>) of integer;
function get_4_ints(a, b, c, d : integer) return int_vec is
begin
return (a, b, c, d);
end function;
begin
p1: process is
constant x : int_vec := (1, 2, 3, 4, 5);
variable y : int_vec(1 to x'length) := x;
begin
wait for 5 ns;
assert y = (1, 2, 3, 4, 5);
wait;
end process;
p2: process is
constant x : int_vec := (6, 7, 8, 9);
variable y : int_vec(1 to x'length) := x;
begin
wait for 5 ns;
assert get_4_ints(1, 2, 3, 4) = (1, 2, 3, 4); -- Would overwrite y
assert y = (6, 7, 8, 9);
wait;
end process;
end architecture;
| gpl-3.0 | a3d49421f0be4b4442f6b6b796985040 | 0.523256 | 3.083665 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_common_bit_cc.vhd | 1 | 2,374 | ------------------------------------------------------------------------------
-- Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Description
------------------------------------------------------------------------------
-- This is a very basic clock crossing that allows passing multple independent
-- single-bit signals from one clock domain to another one.
-- Double stage synchronizers are implemeted for each bit, including then
-- required attributes.
--
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
entity psi_common_bit_cc is
generic (
NumBits_g : positive := 1
);
port (
-- Clock Domain A
BitsA : in std_logic_vector(NumBits_g-1 downto 0);
-- Clock Domain B
ClkB : in std_logic;
BitsB : out std_logic_vector(NumBits_g-1 downto 0)
);
end entity;
------------------------------------------------------------------------------
-- Architecture Declaration
------------------------------------------------------------------------------
architecture rtl of psi_common_bit_cc is
signal Reg0 : std_logic_vector(NumBits_g-1 downto 0) := (others => '0');
signal Reg1 : std_logic_vector(NumBits_g-1 downto 0) := (others => '0');
attribute syn_srlstyle : string;
attribute syn_srlstyle of Reg0 : signal is "registers";
attribute syn_srlstyle of Reg1 : signal is "registers";
attribute shreg_extract : string;
attribute shreg_extract of Reg0 : signal is "no";
attribute shreg_extract of Reg1 : signal is "no";
attribute ASYNC_REG : string;
attribute ASYNC_REG of Reg0 : signal is "TRUE";
attribute ASYNC_REG of Reg1 : signal is "TRUE";
begin
-- Process
p : process(ClkB)
begin
if rising_edge(ClkB) then
Reg0 <= BitsA;
Reg1 <= Reg0;
end if;
end process;
BitsB <= Reg1;
end;
| gpl-2.0 | 2b993adf292c4fc42da54c9dbd8d1701 | 0.457456 | 4.600775 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd | 4 | 2,036 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity motor_system is
port ( terminal vp, vm : electrical;
terminal px : electrical_vector(1 to 3) );
end entity motor_system;
----------------------------------------------------------------
architecture state_space of motor_system is
quantity v_in across vp to vm;
quantity x across i_x through px to electrical_ref;
constant Tfb : real := 0.001;
constant Kfb : real := 1.0;
constant Te : real := 0.001;
constant Ke : real := 1.0;
constant Tm : real := 0.1;
constant Km : real := 1.0;
type real_matrix is array (1 to 3, 1 to 3) of real;
constant c : real_matrix := ( ( -1.0/Tfb, 0.0, Kfb/Tfb ),
( -Ke/Te, -1.0/Te, 0.0 ),
( 0.0, Km/Tm, -1.0/Tm ) );
begin
state_eqn : procedural is
variable sum : real_vector(1 to 3) := (0.0, 0.0, 0.0);
begin
for i in 1 to 3 loop
for j in 1 to 3 loop
sum(i) := sum(i) + c(i, j) * x(j);
end loop;
end loop;
x(1)'dot := sum(1);
x(2)'dot := sum(2) + (Ke/Te)*v_in;
x(3)'dot := sum(3);
end procedural state_eqn;
end architecture state_space;
| gpl-2.0 | d274a945b5d7bc6e977a0fd5daa4cffb | 0.602161 | 3.590829 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_huffval.vhd | 2 | 1,461 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_xhuff_tbl_huffval;
architecture augh of p_jinfo_dc_xhuff_tbl_huffval is
-- Embedded RAM
type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | a23af1523d4c4ccc859c7651bd8c02af | 0.676934 | 2.875984 | false | false | false | false |
nickg/nvc | test/regress/bounds38.vhd | 1 | 656 | entity bounds38 is
end entity;
architecture test of bounds38 is
type int_vec_2d is array (natural range <>, natural range <>) of integer;
function double (x : in int_vec_2d) return int_vec_2d is
variable result : int_vec_2d(x'range(2), x'range(1));
variable sum : integer;
begin
for i in result'range(1) loop
for j in result'range(2) loop
result(i, j) := x(i, j) * 2; -- Error
end loop;
end loop;
return result;
end function;
signal s3, s4 : int_vec_2d(1 to 2, 5 to 7) := (others => (others => 0));
begin
p2: s4 <= double(s3);
end architecture;
| gpl-3.0 | b9890985aa61723e728b28f95c603ee9 | 0.570122 | 3.296482 | false | false | false | false |
nickg/nvc | test/elab/issue93.vhd | 5 | 676 | entity t is
generic(
ORDER : integer := 8
);
port(
clk : in bit;
reset : in bit
);
end entity t;
architecture RTL of t is
function calc_order(i:integer) return integer is
begin
if i mod 2 = 1 then
return i/2+1;
else
return i/2;
end if;
end function;
constant C_ORDER :integer:=calc_order(ORDER);
type t_48 is array (C_ORDER-1 downto 0) of bit_vector(47 downto 0);
signal a:t_48;
constant zero48 : bit_vector(47 downto 0):=(others=>'0');
begin
loop_gen: for i in 0 to C_ORDER-1 generate
a(i)<=zero48;
end generate;
end architecture RTL;
| gpl-3.0 | e7cd5e448280899467af074015384fc1 | 0.56213 | 3.595745 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/uart_dcfifo_in.vhd | 1 | 7,772 | -- megafunction wizard: %LPM_FIFO+%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: uart_dcfifo_in.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY uart_dcfifo_in IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END uart_dcfifo_in;
ARCHITECTURE SYN OF uart_dcfifo_in IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_hint : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdempty : OUT STD_LOGIC ;
rdreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
rdempty <= sub_wire0;
wrfull <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_hint => "MAXIMIZE_SPEED=7,",
lpm_numwords => 32,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => 8,
lpm_widthu => 5,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "32"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=7,"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL uart_dcfifo_in_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | f92edfc5b481caa7560bfb69e2a48dc4 | 0.651312 | 3.466548 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd | 4 | 1,655 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity mixer_wa is
port ( terminal inputs : electrical_vector(1 to 8);
terminal output : electrical );
end entity mixer_wa;
----------------------------------------------------------------
architecture weighted of mixer_wa is
quantity v_in across inputs;
quantity v_out across i_out through output;
quantity v1, v2, v3, v4, v5, v6, v7, v8 : real;
constant gains : real_vector(1 to 8)
:= ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
begin
v1 == v_in(1) * gains(1);
v2 == v_in(2) * gains(2);
v3 == v_in(3) * gains(3);
v4 == v_in(4) * gains(4);
v5 == v_in(5) * gains(5);
v6 == v_in(6) * gains(6);
v7 == v_in(7) * gains(7);
v8 == v_in(8) * gains(8);
v_out == v1 + v2 + v3 + v4 + v5 + v6 + v7 + v8;
end architecture weighted;
| gpl-2.0 | e685331590f995cd82fa71e47dc815d5 | 0.634441 | 3.232422 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug037/sim_global.v08.vhdl | 2 | 1,578 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Global simulation constants and shared varibales.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
use PoC.sim_protected.all;
package sim_global is
-- The default global status objects.
-- ===========================================================================
shared variable globalSimulationStatus : T_SIM_STATUS;
end package;
| gpl-2.0 | 0efa8dfe34295cc4c546f77f52b7d9a5 | 0.538023 | 4.508571 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue30/tb-alu.vhdl | 2 | 220,692 | library ieee;
use ieee.std_logic_1164.all;
package testbench is
constant zero: std_logic_vector(3 downto 0) := x"0";
constant one: std_logic_vector(3 downto 0) := x"1";
constant two: std_logic_vector(3 downto 0) := x"2";
constant three: std_logic_vector(3 downto 0) := x"3";
constant four: std_logic_vector(3 downto 0) := x"4";
constant five: std_logic_vector(3 downto 0) := x"5";
constant six: std_logic_vector(3 downto 0) := x"6";
constant seven: std_logic_vector(3 downto 0) := x"7";
constant eight: std_logic_vector(3 downto 0) := x"8";
constant nine: std_logic_vector(3 downto 0) := x"9";
constant ten: std_logic_vector(3 downto 0) := x"a";
constant eleven: std_logic_vector(3 downto 0) := x"b";
constant twelve: std_logic_vector(3 downto 0) := x"c";
constant thirteen: std_logic_vector(3 downto 0) := x"d";
constant fourteen: std_logic_vector(3 downto 0) := x"e";
constant fifteen: std_logic_vector(3 downto 0) := x"f";
constant counter_width: positive := 24;
constant Disable: std_logic := '0';
constant enable: std_logic := '1';
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.testbench.all;
use work.definitions.all;
entity tb_alu is
end;
architecture struct_tb_alu of tb_alu is
component clkgen is
port(
clk_out: out std_logic;
resetn: out std_logic
);
end component;
component synchronous_latchN is
generic(
N: positive
);
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic_vector((N-1) downto 0);
q: out std_logic_vector((N-1) downto 0)
);
end component;
component synchronous_latch_autoclear is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
component counterN is
generic(
N: positive
);
port(
clock: in std_logic;
carry_in: in std_logic;
clock_enable: in std_logic;
resetn: in std_logic;
output: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end component;
component alu is
port(
-- control
operation: in std_logic_vector(4 downto 0);
-- operands
primary_operand: in std_logic_vector(7 downto 0);
secondary_operand: in std_logic_vector(7 downto 0);
flags_in: in std_logic_vector(7 downto 0);
-- results
output, flags_out: out std_logic_vector(7 downto 0);
secondary_out: out std_logic_vector(7 downto 0)
);
end component;
component magnitudeN is
generic(
N: positive
);
port(
a, b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end component;
signal clock: std_logic;
signal resetn: std_logic;
signal notclock: std_logic;
signal next_state: std_logic_vector(3 downto 0);
signal nxt_state: std_logic_vector(3 downto 0);
signal current_state: std_logic_vector(3 downto 0);
signal counter_state: std_logic;
signal counter_clock: std_logic;
signal counter_clock_enable: std_logic;
signal counter_out: std_logic_vector((counter_width - 1) downto 0);
signal counter_zero: std_logic;
signal zero_secondary_alu_result: std_logic;
signal test_bits: std_logic;
signal res_bits: std_logic;
signal res_result: std_logic_vector(7 downto 0);
signal alu_result: std_logic_vector(7 downto 0);
signal secondary_alu_result: std_logic_vector(7 downto 0);
signal flags_in: std_logic_vector(7 downto 0);
signal flags: std_logic_vector(7 downto 0);
signal sum_check: std_logic_vector(8 downto 0);
signal sum_overflow_check: std_logic;
signal sum_zero_check: std_logic;
signal half_sum_check: std_logic_vector(4 downto 0);
signal sum_checker: std_logic;
signal subtract_check: std_logic_vector(8 downto 0);
signal subtract_overflow_check: std_logic;
signal subtract_zero_check: std_logic;
signal half_difference_check: std_logic_vector(4 downto 0);
signal subtract_checker: std_logic;
signal and_check: std_logic_vector(7 downto 0);
signal and_zero_check: std_logic;
signal and_parity_check: std_logic;
signal and_checker: std_logic;
signal xor_check: std_logic_vector(7 downto 0);
signal xor_zero_check: std_logic;
signal xor_parity_check: std_logic;
signal xor_checker: std_logic;
signal or_check: std_logic_vector(7 downto 0);
signal or_zero_check: std_logic;
signal or_parity_check: std_logic;
signal or_checker: std_logic;
signal rlc_check: std_logic_vector(7 downto 0);
signal rlc_zero_check: std_logic;
signal rlc_parity_check: std_logic;
signal rlc_checker: std_logic;
signal rrc_check: std_logic_vector(7 downto 0);
signal rrc_zero_check: std_logic;
signal rrc_parity_check: std_logic;
signal rrc_checker: std_logic;
signal rl_check: std_logic_vector(7 downto 0);
signal rl_zero_check: std_logic;
signal rl_parity_check: std_logic;
signal rl_checker: std_logic;
signal rr_check: std_logic_vector(7 downto 0);
signal rr_zero_check: std_logic;
signal rr_parity_check: std_logic;
signal rr_checker: std_logic;
signal daa_unimp: std_logic;
signal cpl_check: std_logic_vector(7 downto 0);
signal cpl_checker: std_logic;
signal scf_checker: std_logic;
signal ccf_flags: std_logic_vector(7 downto 0);
signal sla_check: std_logic_vector(7 downto 0);
signal sla_zero_check: std_logic;
signal sla_parity_check: std_logic;
signal sla_checker: std_logic;
signal sra_check: std_logic_vector(7 downto 0);
signal sra_zero_check: std_logic;
signal sra_parity_check: std_logic;
signal sra_checker: std_logic;
signal sll_check: std_logic_vector(7 downto 0);
signal sll_zero_check: std_logic;
signal sll_parity_check: std_logic;
signal sll_checker: std_logic;
signal srl_check: std_logic_vector(7 downto 0);
signal srl_zero_check: std_logic;
signal srl_parity_check: std_logic;
signal srl_checker: std_logic;
signal bit_checker: std_logic;
signal bit_check: std_logic_vector(7 downto 0);
signal bit_zero_checker: std_logic;
signal res_checker: std_logic;
signal set_checker: std_logic;
signal inrc_zero: std_logic;
signal inrc_parity: std_logic;
signal primary_rld_check: std_logic_vector(7 downto 0);
signal secondary_rld_check: std_logic_vector(7 downto 0);
signal rld_zero_check: std_logic;
signal rld_parity_check: std_logic;
signal primary_rld_checker: std_logic;
signal secondary_rld_checker: std_logic;
signal primary_rrd_check: std_logic_vector(7 downto 0);
signal secondary_rrd_check: std_logic_vector(7 downto 0);
signal rrd_zero_check: std_logic;
signal rrd_parity_check: std_logic;
signal primary_rrd_checker: std_logic;
signal secondary_rrd_checker: std_logic;
signal bmtc_check: std_logic_vector(7 downto 0);
signal bmtc_parity_check: std_logic;
signal bmtc_checker: std_logic;
signal done: std_logic;
begin
u1: clkgen port map(
clk_out => clock,
resetn => resetn
);
notclock <= not clock;
u2: synchronous_latchN
generic map(
N => 4
)
port map(
rstn => resetn,
clock => notclock,
clock_enable => '1',
d => next_state,
q => nxt_state
);
u3: synchronous_latchN
generic map(
N => 4
)
port map(
rstn => resetn,
clock => clock,
clock_enable => '1',
d => nxt_state,
q => current_state
);
u4: synchronous_latch_autoclear port map(
rstn => resetn,
clock => notclock,
clock_enable => counter_clock,
d => counter_state,
q => counter_clock_enable
);
u5: counterN
generic map(
N => counter_width
)
port map(
clock => clock,
carry_in => '1',
clock_enable => counter_clock_enable,
resetn => resetn,
output => counter_out((counter_width - 1) downto 0),
carry_out => open
);
u6: alu port map(
operation => counter_out(21 downto 17),
primary_operand => counter_out(7 downto 0),
secondary_operand => counter_out(15 downto 8),
flags_in => flags_in,
output => alu_result,
flags_out => flags,
secondary_out => secondary_alu_result
);
flags_in <= ( carry_bit => counter_out(16),
others => '0');
u7: magnitudeN
generic map(
N => counter_width
)
port map(
a => counter_out,
b => x"000000",
equal => counter_zero,
lt => open,
gt => open
);
u8: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sum_check(7 downto 0),
equal => sum_checker,
lt => open,
gt => open
);
u9: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => x"00",
equal => zero_secondary_alu_result,
lt => open,
gt => open
);
u10: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => subtract_check(7 downto 0),
equal => subtract_checker,
lt => open,
gt => open
);
u11: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => and_check(7 downto 0),
equal => and_checker,
lt => open,
gt => open
);
u12: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => xor_check(7 downto 0),
equal => xor_checker,
lt => open,
gt => open
);
u13: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => or_check(7 downto 0),
equal => or_checker,
lt => open,
gt => open
);
u14: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rlc_check(7 downto 0),
equal => rlc_checker,
lt => open,
gt => open
);
u15: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rrc_check(7 downto 0),
equal => rrc_checker,
lt => open,
gt => open
);
u16: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rl_check(7 downto 0),
equal => rl_checker,
lt => open,
gt => open
);
u17: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => rr_check(7 downto 0),
equal => rr_checker,
lt => open,
gt => open
);
u18: magnitudeN
generic map(
N => 17
)
port map(
a => counter_out(16 downto 0),
b => "00000000000000000",
equal => daa_unimp,
lt => open,
gt => open
);
u19: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => cpl_check(7 downto 0),
equal => cpl_checker,
lt => open,
gt => open
);
u20: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => counter_out(7 downto 0),
equal => scf_checker,
lt => open,
gt => open
);
u21: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sla_check(7 downto 0),
equal => sla_checker,
lt => open,
gt => open
);
u22: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sra_check(7 downto 0),
equal => sra_checker,
lt => open,
gt => open
);
u23: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => sll_check(7 downto 0),
equal => sll_checker,
lt => open,
gt => open
);
u24: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => srl_check(7 downto 0),
equal => srl_checker,
lt => open,
gt => open
);
u25: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => counter_out(15 downto 8),
equal => bit_checker,
lt => open,
gt => open
);
bit_check <= (counter_out(7 downto 0) and counter_out(15 downto 8));
u26: magnitudeN
generic map(
N => 8
)
port map(
a => x"00",
b => bit_check,
equal => bit_zero_checker,
lt => open,
gt => open
);
u27: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => res_result,
equal => res_checker,
lt => open,
gt => open
);
u28: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => primary_rld_check,
equal => primary_rld_checker,
lt => open,
gt => open
);
u29: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => secondary_rld_check,
equal => secondary_rld_checker,
lt => open,
gt => open
);
u30: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => primary_rrd_check,
equal => primary_rrd_checker,
lt => open,
gt => open
);
u31: magnitudeN
generic map(
N => 8
)
port map(
a => secondary_alu_result,
b => secondary_rrd_check,
equal => secondary_rrd_checker,
lt => open,
gt => open
);
u32: magnitudeN
generic map(
N => 8
)
port map(
a => alu_result,
b => bmtc_check,
equal => bmtc_checker,
lt => open,
gt => open
);
u33: magnitudeN
generic map(
N => 22
)
port map(
a => counter_out(21 downto 0),
b => (others => '1'), -- x"3fffff",
equal => done,
lt => open,
gt => open
);
process(current_state, resetn) begin
if resetn = '0' then
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= zero;
else
case current_state is
when zero =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= one;
when one =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
assert counter_zero = '1'
report "counter initialisation failure"
severity failure;
next_state <= two;
when two =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= three;
when three =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
case counter_out(21 downto 17) is
when add_operation | adc_operation =>
assert sum_checker = '1'
report "incorrect sum"
severity failure;
assert sum_check(8) = flags(carry_bit)
report "incorrect addition carry flag"
severity failure;
assert sum_overflow_check = flags(parity_overflow_bit)
report "incorrect addition overflow flag"
severity failure;
assert sum_zero_check = flags(zero_bit)
report "incorrect addition zero flag"
severity failure;
assert half_sum_check(4) = flags(half_carry_bit)
report "incorrect interdigit carry flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect addition sign flag"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect addition add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for add/adc"
severity failure;
when sub_operation | sbc_operation =>
assert subtract_checker = '1'
report "incorrect difference"
severity failure;
assert subtract_check(8) = flags(carry_bit)
report "incorrect subtraction borrow flag"
severity failure;
assert subtract_overflow_check = flags(parity_overflow_bit)
report "incorrect subtraction overflow flag"
severity failure;
assert subtract_zero_check = flags(zero_bit)
report "incorrect subtraction zero flag"
severity failure;
assert half_difference_check(4) = flags(half_carry_bit)
report "incorrect interdigit borrow flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect subtraction sign flag"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect subtraction add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sub/sbc"
severity failure;
when and_operation =>
assert and_checker = '1'
report "incorrect logical AND result"
severity failure;
assert and_zero_check = flags(zero_bit)
report "incorrect logical AND zero flag"
severity failure;
assert and_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical AND"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical AND"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical AND"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract bit for logical AND"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry bit for logical AND"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for and"
severity failure;
when xor_operation =>
assert xor_checker = '1'
report "incorrect logical XOR result"
severity failure;
assert xor_zero_check = flags(zero_bit)
report "incorrect logical XOR zero flag"
severity failure;
assert xor_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical XOR"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical XOR"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical XOR"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for logical XOR"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry bit for logical XOR"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for xor"
severity failure;
when or_operation =>
assert or_checker = '1'
report "incorrect logical OR result"
severity failure;
assert or_zero_check = flags(zero_bit)
report "incorrect logical OR zero flag"
severity failure;
assert or_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for logical OR"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for logical OR"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect half-carry flag for logical OR"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for logical OR"
severity failure;
assert flags(carry_bit) = '0'
report "incorrect carry flag for logical OR"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for OR operation"
severity failure;
when cmp_operation =>
assert subtract_checker = '1'
report "incorrect compare result"
severity failure;
assert subtract_check(8) = flags(carry_bit)
report "incorrect compare borrow flag"
severity failure;
assert subtract_overflow_check = flags(parity_overflow_bit)
report "incorrect compare overflow flag"
severity failure;
assert subtract_zero_check = flags(zero_bit)
report "incorrect compare zero flag"
severity failure;
assert half_difference_check(4) = flags(half_carry_bit)
report "incorrect compare interdigit borrow flag"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect compare sign flag"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect compare add/subtract flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for compare"
severity failure;
when rlc_operation =>
assert rlc_checker = '1'
report "incorrect rlc result"
severity failure;
assert rlc_zero_check = flags(zero_bit)
report "incorrect rlc zero flag"
severity failure;
assert rlc_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rlc"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rlc"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rlc"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rlc"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for rlc"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rls"
severity failure;
when rrc_operation =>
assert rrc_checker = '1'
report "incorrect rrc result"
severity failure;
assert rrc_zero_check = flags(zero_bit)
report "incorrect rrc zero bit"
severity failure;
assert rrc_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rrc"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rrc"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rrc"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rrc"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for rrc"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rrc"
severity failure;
when rl_operation =>
assert rl_checker = '1'
report "incorrect rl result"
severity failure;
assert rl_zero_check = flags(zero_bit)
report "incorrect rl zero bit"
severity failure;
assert rl_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rl"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rl"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rl"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rl"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for rl"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rl"
severity failure;
when rr_operation =>
assert rr_checker = '1'
report "incorrect rr result"
severity failure;
assert rr_zero_check = flags(zero_bit)
report "incorrect rr zero bit"
severity failure;
assert rr_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rr"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for rr"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rr"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rr"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for rr"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for rr"
severity failure;
when daa_operation =>
assert daa_unimp = '0'
report "DAA is not implemented"
severity note;
when cpl_operation =>
assert cpl_checker = '1'
report "incorrect cpl result"
severity failure;
assert flags(add_sub_bit) = '1'
report "incorrect cpl add/sub flag"
severity failure;
assert flags(half_carry_bit) = '1'
report "incorrect cpl half-carry flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for cpl"
severity failure;
when scf_operation =>
assert scf_checker = '1'
report "incorrect scf result"
severity failure;
assert flags(carry_bit) = '1'
report "incorrect carry flag for scf"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for scf"
severity failure;
when ccf_operation =>
assert scf_checker = '1'
report "incorrect ccf result"
severity failure;
assert flags(carry_bit) = not (counter_out(16))
report "incorrect ccf carry flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for ccf"
severity failure;
when sla_operation =>
assert sla_checker = '1'
report "incorrect sla result"
severity failure;
assert sla_zero_check = flags(zero_bit)
report "incorrect sla zero flag"
severity failure;
assert sla_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sla"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sla"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sla"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sla"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry bit for flag"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sla"
severity failure;
when sra_operation =>
assert sra_checker = '1'
report "incorrect sra result"
severity failure;
assert sra_zero_check = flags(zero_bit)
report "incorrect sra zero flag"
severity failure;
assert sra_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sra"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sra"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sra"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sra"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for sra"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sra"
severity failure;
when sll_operation =>
assert sll_checker = '1'
report "incorrect sll result"
severity failure;
assert sll_zero_check = flags(zero_bit)
report "incorrect sll zero flag"
severity failure;
assert sll_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for sll"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for sll"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for sll"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for sll"
severity failure;
assert flags(carry_bit) = counter_out(7)
report "incorrect carry flag for sll"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for sll"
severity failure;
when srl_operation =>
assert srl_checker = '1'
report "incorrect srl result"
severity failure;
assert srl_zero_check = flags(zero_bit)
report "incorrect srl zero flag"
severity failure;
assert srl_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for srl"
severity failure;
assert alu_result(7) = flags(sign_bit)
report "incorrect sign flag for srl"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for srl"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for srl"
severity failure;
assert flags(carry_bit) = counter_out(0)
report "incorrect carry flag for srl"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for srl"
severity failure;
when bit_operation =>
assert bit_checker = '1'
report "incorrect result for bit operation"
severity failure;
if test_bits = '1' then
if bit_zero_checker = '1' then
assert flags(zero_bit) = '1'
report "BIT: zero flag != '1'"
severity failure;
elsif bit_zero_checker = '0' then
assert flags(zero_bit) = '0'
report "BIT: zero flag != '0'"
severity failure;
end if;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for bit"
severity failure;
when res_operation =>
if test_bits = '1' then
assert res_checker = '1'
report "incorrect result for RES"
severity failure;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for res"
severity failure;
when set_operation =>
if test_bits = '1' then
assert or_checker = '1'
report "incorrect result for SET"
severity failure;
end if;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for set"
severity failure;
when in16_operation =>
assert scf_checker = '1'
report "incorrect result for in r,(C)"
severity failure;
assert flags(zero_bit) = inrc_zero
report "incorrect zero flag for in r,(c)"
severity failure;
assert flags(parity_overflow_bit) = inrc_parity
report "incorrect parity flag for in r,(c)"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for in r,(c)"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for in r,(c)"
severity failure;
assert flags(sign_bit) = alu_result(sign_bit)
report "incorrect sign flag for in r,(c)"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for in r, (c)"
severity failure;
when rld_operation =>
assert primary_rld_checker = '1'
report "incorrect primary result for rld"
severity failure;
assert secondary_rld_checker = '1'
report "incorrect secondary rld result"
severity failure;
assert alu_result(sign_bit) = flags(sign_bit)
report "incorrect sign flag for rld"
severity failure;
assert rld_zero_check = flags(zero_bit)
report "incorrect zero flag for rld"
severity failure;
assert rld_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rld"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rld"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rld"
severity failure;
when rrd_operation =>
assert primary_rrd_checker = '1'
report "incorrect primary result for rrd"
severity failure;
assert secondary_rrd_checker = '1'
report "incorrect secondary rrd result"
severity failure;
assert alu_result(sign_bit) = flags(sign_bit)
report "incorrect sign flag for rrd"
severity failure;
assert rrd_zero_check = flags(zero_bit)
report "incorrect zero flag for rrd"
severity failure;
assert rrd_parity_check = flags(parity_overflow_bit)
report "incorrect parity flag for rrd"
severity failure;
assert flags(half_carry_bit) = '0'
report "incorrect half-carry flag for rrd"
severity failure;
assert flags(add_sub_bit) = '0'
report "incorrect add/subtract flag for rrd"
severity failure;
when blockterm16_operation =>
assert bmtc_checker = '1'
report "incorrect bmtc result"
severity failure;
assert bmtc_parity_check = flags(parity_overflow_bit)
report "incorrect bmtc parity bit"
severity failure;
assert zero_secondary_alu_result = '1'
report "secondary_alu_result != 0 for block termination"
severity failure;
when others =>
-- assert counter_out(16 downto 0) /= ('0' & x"0000")
-- report "unimplemented alu operation"
-- severity warning;
end case;
if done = '1' then
counter_state <= Disable;
counter_clock <= Disable;
next_state <= fifteen;
else
counter_clock <= enable;
counter_state <= enable;
next_state <= two;
end if;
when four =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= five;
when five =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= six;
when six =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= seven;
when seven =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= eight;
when eight =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= nine;
when nine =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= ten;
when ten =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= eleven;
when eleven =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= twelve;
when twelve =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= thirteen;
when thirteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= fourteen;
when fourteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= fifteen;
when fifteen =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
assert false
report "test success"
severity note;
when others =>
-- default states begin here
counter_state <= Disable;
counter_clock <= Disable;
test_bits <= (
(( counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and (not counter_out(0))) or
((not counter_out(7)) and (not counter_out(6)) and (not counter_out(5)) and (not counter_out(4)) and (not counter_out(3)) and (not counter_out(2)) and (not counter_out(1)) and ( counter_out(0)))
);
res_bits <= (
((not counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and (not counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and (not counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and (not counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and (not counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and (not counter_out(2)) and ( counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and (not counter_out(1)) and ( counter_out(0))) or
(( counter_out(7)) and ( counter_out(6)) and ( counter_out(5)) and ( counter_out(4)) and ( counter_out(3)) and ( counter_out(2)) and ( counter_out(1)) and (not counter_out(0)))
);
sum_check <= ('0' & counter_out(15 downto 8)) + ('0' & counter_out(7 downto 0)) + (x"00" & (counter_out(16) and counter_out(17)));
sum_overflow_check <= (not (counter_out(15) xor counter_out(7))) and (counter_out(15) xor sum_check(7));
sum_zero_check <= not (sum_check(7) or sum_check(6) or sum_check(5) or sum_check(4) or sum_check(3) or sum_check(2) or sum_check(1) or sum_check(0));
half_sum_check <= ('0' & counter_out(11 downto 8)) + ('0' & counter_out(3 downto 0)) + (x"0" & (counter_out(16) and counter_out(17)));
subtract_check <= ('0' & counter_out(7 downto 0)) - ('0' & counter_out(15 downto 8)) - (x"00" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
subtract_overflow_check <= (counter_out(7) xor counter_out(15)) and (counter_out(7) xor subtract_check(7));
subtract_zero_check <= not (subtract_check(7) or subtract_check(6) or subtract_check(5) or subtract_check(4) or subtract_check(3) or subtract_check(2) or subtract_check(1) or subtract_check(0));
half_difference_check <= ('0' & counter_out(3 downto 0)) - ('0' & counter_out(11 downto 8)) - (x"0" & (counter_out(16) and counter_out(17) and counter_out(18) and (not counter_out(19))));
and_check <= counter_out(15 downto 8) and counter_out(7 downto 0);
and_zero_check <= not (and_check(7) or and_check(6) or and_check(5) or and_check(4) or and_check(3) or and_check(2) or and_check(1) or and_check(0));
and_parity_check <= not (and_check(7) xor and_check(6) xor and_check(5) xor and_check(4) xor and_check(3) xor and_check(2) xor and_check(1) xor and_check(0));
xor_check <= counter_out(15 downto 8) xor counter_out(7 downto 0);
xor_zero_check <= not (xor_check(7) or xor_check(6) or xor_check(5) or xor_check(4) or xor_check(3) or xor_check(2) or xor_check(1) or xor_check(0));
xor_parity_check <= not (xor_check(7) xor xor_check(6) xor xor_check(5) xor xor_check(4) xor xor_check(3) xor xor_check(2) xor xor_check(1) xor xor_check(0));
or_check <= counter_out(15 downto 8) or counter_out(7 downto 0);
or_zero_check <= not (or_check(7) or or_check(6) or or_check(5) or or_check(4) or or_check(3) or or_check(2) or or_check(1) or or_check(0));
or_parity_check <= not (or_check(7) xor or_check(6) xor or_check(5) xor or_check(4) xor or_check(3) xor or_check(2) xor or_check(1) xor or_check(0));
rlc_check <= counter_out(6 downto 0) & counter_out(7);
rlc_zero_check <= not (rlc_check(7) or rlc_check(6) or rlc_check(5) or rlc_check(4) or rlc_check(3) or rlc_check(2) or rlc_check(1) or rlc_check(0));
rlc_parity_check <= not (rlc_check(7) xor rlc_check(6) xor rlc_check(5) xor rlc_check(4) xor rlc_check(3) xor rlc_check(2) xor rlc_check(1) xor rlc_check(0));
rrc_check <= counter_out(0) & counter_out(7 downto 1);
rrc_zero_check <= not (rrc_check(7) or rrc_check(6) or rrc_check(5) or rrc_check(4) or rrc_check(3) or rrc_check(2) or rrc_check(1) or rrc_check(0));
rrc_parity_check <= not (rrc_check(7) xor rrc_check(6) xor rrc_check(5) xor rrc_check(4) xor rrc_check(3) xor rrc_check(2) xor rrc_check(1) xor rrc_check(0));
rl_check <= counter_out(6 downto 0) & counter_out(16);
rl_zero_check <= not (rl_check(7) or rl_check(6) or rl_check(5) or rl_check(4) or rl_check(3) or rl_check(2) or rl_check(1) or rl_check(0));
rl_parity_check <= not (rl_check(7) xor rl_check(6) xor rl_check(5) xor rl_check(4) xor rl_check(3) xor rl_check(2) xor rl_check(1) xor rl_check(0));
rr_check <= counter_out(16) & counter_out(7 downto 1);
rr_zero_check <= not (rr_check(7) or rr_check(6) or rr_check(5) or rr_check(4) or rr_check(3) or rr_check(2) or rr_check(1) or rr_check(0));
rr_parity_check <= not (rr_check(7) xor rr_check(6) xor rr_check(5) xor rr_check(4) xor rr_check(3) xor rr_check(2) xor rr_check(1) xor rr_check(0));
cpl_check <= not counter_out(7 downto 0);
sla_check <= counter_out(6 downto 0) & '0';
sla_zero_check <= not (sla_check(7) or sla_check(6) or sla_check(5) or sla_check(4) or sla_check(3) or sla_check(2) or sla_check(1) or sla_check(0));
sla_parity_check <= not (sla_check(7) xor sla_check(6) xor sla_check(5) xor sla_check(4) xor sla_check(3) xor sla_check(2) xor sla_check(1) xor sla_check(0));
sra_check <= counter_out(7) & counter_out(7 downto 1);
sra_zero_check <= not (sra_check(7) or sra_check(6) or sra_check(5) or sra_check(4) or sra_check(3) or sra_check(2) or sra_check(1) or sra_check(0));
sra_parity_check <= not (sra_check(7) xor sra_check(6) xor sra_check(5) xor sra_check(4) xor sra_check(3) xor sra_check(2) xor sra_check(1) xor sra_check(0));
sll_check <= counter_out(6 downto 0) & '0';
sll_zero_check <= not (sll_check(7) or sll_check(6) or sll_check(5) or sll_check(4) or sll_check(3) or sll_check(2) or sll_check(1) or sll_check(0));
sll_parity_check <= not (sll_check(7) xor sll_check(6) xor sll_check(5) xor sll_check(4) xor sll_check(3) xor sll_check(2) xor sll_check(1) xor sll_check(0));
srl_check <= '0' & counter_out(7 downto 1);
srl_zero_check <= not (srl_check(7) or srl_check(6) or srl_check(5) or srl_check(4) or srl_check(3) or srl_check(2) or srl_check(1) or srl_check(0));
srl_parity_check <= not (srl_check(7) xor srl_check(6) xor srl_check(5) xor srl_check(4) xor srl_check(3) xor srl_check(2) xor srl_check(1) xor srl_check(0));
inrc_zero <= not (counter_out(7) or counter_out(6) or counter_out(5) or counter_out(4) or counter_out(3) or counter_out(2) or counter_out(1) or counter_out(0));
inrc_parity <= not (counter_out(7) xor counter_out(6) xor counter_out(5) xor counter_out(4) xor counter_out(3) xor counter_out(2) xor counter_out(1) xor counter_out(0));
primary_rld_check <= counter_out(7 downto 4) & counter_out(15 downto 12);
secondary_rld_check <= counter_out(11 downto 8) & counter_out(3 downto 0);
rld_zero_check <= not (primary_rld_check(7) or primary_rld_check(6) or primary_rld_check(5) or primary_rld_check(4) or primary_rld_check(3) or primary_rld_check(2) or primary_rld_check(1) or primary_rld_check(0));
rld_parity_check <= not (primary_rld_check(7) xor primary_rld_check(6) xor primary_rld_check(5) xor primary_rld_check(4) xor primary_rld_check(3) xor primary_rld_check(2) xor primary_rld_check(1) xor primary_rld_check(0));
primary_rrd_check <= counter_out(7 downto 4) & counter_out(11 downto 8);
secondary_rrd_check <= counter_out(3 downto 0) & counter_out(15 downto 12);
rrd_zero_check <= not (primary_rrd_check(7) or primary_rrd_check(6) or primary_rrd_check(5) or primary_rrd_check(4) or primary_rrd_check(3) or primary_rrd_check(2) or primary_rrd_check(1) or primary_rrd_check(0));
rrd_parity_check <= not (primary_rrd_check(7) xor primary_rrd_check(6) xor primary_rrd_check(5) xor primary_rrd_check(4) xor primary_rrd_check(3) xor primary_rrd_check(2) xor primary_rrd_check(1) xor primary_rrd_check(0));
bmtc_check <= counter_out(7 downto 0) or counter_out(15 downto 8);
bmtc_parity_check <= not (bmtc_check(7) or bmtc_check(6) or bmtc_check(5) or bmtc_check(4) or bmtc_check(3) or bmtc_check(2) or bmtc_check(1) or bmtc_check(0));
-- default states end here
next_state <= zero;
assert false
report "state machine failure"
severity failure;
end case;
end if;
end process;
end;
| gpl-2.0 | 0e5f72870377ae3cc261da997c4b2df0 | 0.64957 | 2.518395 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd | 4 | 6,489 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1364.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01364ent IS
END c08s05b00x00p03n01i01364ent;
ARCHITECTURE c08s05b00x00p03n01i01364arch OF c08s05b00x00p03n01i01364ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01364"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01364 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01364arch;
| gpl-2.0 | 8b6dd347957c3090f093664a436f4f2d | 0.582832 | 2.957612 | false | false | false | false |
nickg/nvc | test/regress/issue153.vhd | 1 | 2,167 | entity test_inst is
generic(
G_ROUND : natural := 0;
G_ROUND_ENABLE : boolean := false
);
port(
i_value : in bit_vector(7 downto 0);
o_ena : out bit;
o_value : out bit_vector(7 downto 0)
);
end test_inst;
architecture rtl of test_inst is
begin
o_ena <='1' when G_ROUND_ENABLE else '0';
o_value <=(others=>'1') when G_ROUND=1 and G_ROUND_ENABLE else not i_value;
end architecture rtl;
entity issue153 is
end entity issue153;
architecture beh of issue153 is
constant G_ROUND_ENABLE:boolean:=true;
constant C_ADDROUND : bit_vector(7 downto 0):="00001111";
constant C_ZERO8 : bit_vector(7 downto 0):=(others=>'0');
signal s_ena:bit_vector(7 downto 0);
type T_IN_DATA is array(integer range<>) of bit_vector(7 downto 0);
--signal s_value: T_IN_DATA(7 downto -1);-- this should work anyway, uncomment this to compare with ghdl for bug 2
signal s_value: T_IN_DATA(7 downto 0);--this is for bug 1, nvc should report error
begin
GEN_MACS_V : for v in 0 to 7 generate
signal C :bit_vector(7 downto 0);
signal D :bit_vector(7 downto 0);
begin
--should fail here, but doesn't
--GHDL failed here with "bound check failure"
-- ghdl drives correct values on each instances, nvc doesn't
--C <= C_ADDROUND when v=0 and G_ROUND_ENABLE else s_value(v-1);--bug 1
-- below is workaround, but I am lazy enough to not use it :))))
c_gen: if v=0 and G_ROUND_ENABLE generate
C <= C_ADDROUND;
end generate c_gen;
nc_gen: if v>0 generate
C <= s_value(v-1);
end generate nc_gen;
test_i : entity work.test_inst
generic map(
G_ROUND => 1
)
port map(
i_value => C,
o_ena => s_ena(v),
o_value => s_value(v)
);
end generate GEN_MACS_V;
process
begin
wait for 1 ns;
assert s_value(0) = not C_ADDROUND;
assert s_value(1) = C_ADDROUND;
wait;
end process;
end architecture;
| gpl-3.0 | 017898eea689044dce12027bd104f4d1 | 0.565759 | 3.558292 | false | true | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_alternate/pr_region_alternate_sysid_qsys_0/pr_region_alternate_sysid_qsys_0_inst.vhd | 1 | 693 | component pr_region_alternate_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X'; -- address
reset_n : in std_logic := 'X' -- reset_n
);
end component pr_region_alternate_sysid_qsys_0;
u0 : component pr_region_alternate_sysid_qsys_0
port map (
clock => CONNECTED_TO_clock, -- clk.clk
readdata => CONNECTED_TO_readdata, -- control_slave.readdata
address => CONNECTED_TO_address, -- .address
reset_n => CONNECTED_TO_reset_n -- reset.reset_n
);
| mit | 6abcf659a603ead0daf49bccb4d9bb21 | 0.541126 | 3.331731 | false | false | false | false |
tgingold/ghdl | testsuite/synth/cnt01/tb_cnt02.vhdl | 1 | 791 | entity tb_cnt02 is
end tb_cnt02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cnt02 is
signal clk : std_logic;
signal rst : std_logic;
signal low : std_logic;
begin
dut: entity work.cnt02
port map (clk => clk, rst => rst, low => low);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert low = '0' severity failure;
rst <= '0';
pulse;
assert low = '0' severity failure;
pulse;
assert low = '0' severity failure;
pulse;
assert low = '0' severity failure;
pulse;
assert low = '1' severity failure;
pulse;
assert low = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 5045ab9c2a69b77024c7e3df3cbf72fc | 0.586599 | 3.43913 | false | false | false | false |
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