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stringlengths 137
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classes | has_no_keywords
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tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd
| 4 | 2,221 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_22a is
end entity inline_22a;
architecture test of inline_22a is
signal clock : bit;
quantity q : real;
signal sample : integer;
signal average : real;
quantity v_in : real;
constant v_il : real := 0.8;
constant v_ih : real := 2.0;
signal data : std_ulogic;
begin
-- code from book
sampler : process ( clock ) is
constant num_levels : real := 64.0;
constant max_val : real := 5.0;
begin
if clock = '1' then
sample <= integer(q * num_levels / max_val) after 5 ns;
end if;
end process sampler;
--
compute_running_average : process (clock) is
variable num_samples : integer := 0;
variable total : real := 0.0;
variable running_average : real := 0.0;
begin
if clock = '1' then
total := total + q;
num_samples := num_samples + 1;
running_average := total / real(num_samples);
average <= running_average after 5 ns;
end if;
end process compute_running_average;
--
analog_to_std_logic : process (v_in'above(v_il), v_in'above(v_ih)) is
begin
if not v_in'above(v_il) then
data <= '0';
elsif v_in'above(v_ih) then
data <= '1';
else
data <= 'X';
end if;
end process analog_to_std_logic;
-- end code from book
end architecture test;
|
gpl-2.0
|
7d19b95a6bafd66b0f6a1f2bc6341fe5
| 0.658262 | 3.646962 | false | false | false | false |
nickg/nvc
|
test/simp/issue438.vhd
| 1 | 1,799 |
-- test_ng.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ISSUE438 is
generic(
INFO_SIZE : integer := 1;
INFO_BITS : integer := 8
);
end entity;
architecture MODEL of ISSUE438 is
type INFO_RANGE_TYPE is record
VAL_POS : integer;
DATA_LO : integer;
DATA_HI : integer;
end record;
type INFO_RANGE_VECTOR is array (integer range <>) of INFO_RANGE_TYPE;
type VEC_RANGE_TYPE is record
VAL_LO : integer;
VAL_HI : integer;
DATA_LO : integer;
DATA_HI : integer;
INFO_LIST : INFO_RANGE_VECTOR(INFO_SIZE-1 downto 0);
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable v_pos : integer;
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.VAL_POS := v_pos;
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
v_pos := v_pos + 1;
d_pos := d_pos + BITS;
end procedure;
begin
v_pos := 0;
d_pos := 0;
v.VAL_LO := v_pos;
v.DATA_LO := d_pos;
for i in 0 to INFO_SIZE-1 loop
SET_INFO_RANGE(v.INFO_LIST(i), INFO_BITS);
end loop;
v.VAL_HI := v_pos - 1;
v.DATA_HI := d_pos - 1;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal data : std_logic_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
begin
end MODEL;
|
gpl-3.0
|
4321e46b7351e830c28b31253ed22796
| 0.494719 | 3.576541 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue381/test.vhdl
| 1 | 306 |
library ieee;
use ieee.std_logic_1164.all;
entity can_rx is
port (
demo : in std_logic;
status : out std_logic_vector (31 downto 0)
);
end can_rx;
architecture rtl of can_rx is
begin
status(0) <= (0=>'0', others => '0') when demo = '1' else (0=>'1', others => '0');
end rtl;
|
gpl-2.0
|
9b936c22c2cb3bd65ae94dbeccc12095
| 0.578431 | 2.914286 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd
| 4 | 1,587 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_transmission_line is
end tb_transmission_line;
architecture TB_transmission_line of tb_transmission_line is
quantity in_src, line_out : voltage;
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
q1 : entity work.src_pulse(ideal)
generic map(
initial => 0.0,
pulse => 1.0e1,
ti2p => 1.0e-12,
tp2i => 1.0e-12,
delay => 1 ps,
width => 20 ns,
period => 50 ns
)
port map(
output => in_src
);
T1 : entity work.transmission_line_wa(abstract)
port map(
vin => in_src,
vout => line_out
);
end TB_transmission_line;
|
gpl-2.0
|
e26c2e0367995eab0c70504284a492cf
| 0.662256 | 3.937965 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_rst_in/ghrd_10as066n2_rst_in_inst.vhd
| 1 | 483 |
component ghrd_10as066n2_rst_in is
port (
clk : in std_logic := 'X'; -- clk
in_reset_n : in std_logic := 'X'; -- reset_n
out_reset_n : out std_logic -- reset_n
);
end component ghrd_10as066n2_rst_in;
u0 : component ghrd_10as066n2_rst_in
port map (
clk => CONNECTED_TO_clk, -- clk.clk
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
);
|
mit
|
aa5d6af792920cc96e40eda3b40e67e9
| 0.565217 | 2.542105 | false | false | false | false |
nickg/nvc
|
test/regress/guard2.vhd
| 1 | 871 |
entity guard2 is
end entity;
architecture test of guard2 is
type int_vec is array (natural range <>) of integer;
function resolved (x : int_vec) return integer is
begin
return x'length;
end function;
subtype rint is resolved integer;
signal vbus : rint bus;
signal vreg : rint register;
begin
check: process is
begin
assert vbus = 1;
assert vbus'driving;
vbus <= 100;
wait for 1 ns;
assert vbus = 1;
vbus <= null;
wait for 1 ns;
assert vbus = 0;
assert not vbus'driving;
assert vreg = 1;
assert vreg'driving;
vreg <= 123;
wait for 1 ns;
assert vreg = 1;
vreg <= null;
wait for 1 ns;
assert vreg = 1;
assert not vreg'driving;
wait;
end process;
end architecture;
|
gpl-3.0
|
7a0a45c8df423e28bbb4eea2d062cb1e
| 0.555683 | 4.269608 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/mem02/tb_ram4.vhdl
| 1 | 996 |
entity tb_ram4 is
end tb_ram4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram4 is
signal rdat : std_logic_vector(1 downto 0);
signal raddr : std_logic_vector(1 downto 0);
signal init : std_logic_vector(7 downto 0);
signal rst : std_logic;
signal clk : std_logic;
begin
dut: entity work.ram4
port map (raddr => raddr, rdat => rdat, rst => rst, init => init,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
init <= b"01_11_00_10";
pulse;
rst <= '0';
init <= b"00_00_00_00";
raddr <= "00";
pulse;
assert rdat = "10" severity failure;
raddr <= "11";
pulse;
assert rdat = "01" severity failure;
raddr <= "01";
pulse;
assert rdat = "00" severity failure;
raddr <= "10";
pulse;
assert rdat = "11" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
815b24ab227579f582beef20f6767f93
| 0.569277 | 3.32 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug019/PoC/src/common/fileio.vhdl
| 4 | 3,036 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: File I/O-related Functions.
--
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Description:
-- Exploring the options for providing a more convenient API than std.textio.
-- Not yet recommended for adoption as it depends on the VHDL generation and
-- still is under discussion.
--
-- Open problems:
-- - verify that std.textio.write(text, string) is, indeed, specified and
-- that it does *not* print a trailing \newline
-- -> would help to eliminate line buffering in shared variables
-- - move C_LINEBREAK to my_config to keep platform dependency out?
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library PoC;
use PoC.my_project.all;
package FileIO is
-- Constant declarations
constant C_LINEBREAK : STRING;
-- =============================================================================
procedure stdout_write (str : STRING);
procedure stdout_writeline(str : STRING := "");
end package;
package body FileIO is
function ite(cond : BOOLEAN; value1 : STRING; value2 : STRING) return STRING is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
-- =============================================================================
constant C_LINEBREAK : STRING := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF));
-- =============================================================================
shared variable stdout_line : line;
shared variable stderr_line : line;
procedure stdout_write(str : STRING) is
begin
write(stdout_line, str);
end procedure;
procedure stdout_writeline(str : STRING := "") is
begin
write(stdout_line, str);
writeline(output, stdout_line);
end procedure;
end package body;
|
gpl-2.0
|
a4477c9039ac6234719eb886dcad21cb
| 0.588603 | 4.13624 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/synth109/asymmetric_ram_2b.vhd
| 1 | 3,403 |
--
-- Asymmetric port RAM
-- Port A is 256x8-bit read-and-write (write-first synchronization)
-- Port B is 64x32-bit read-and-write (write-first synchronization)
-- Compact description with a for-loop statement
--
-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
-- File: HDL_Coding_Techniques/rams/asymmetric_ram_2b.vhd
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity asymmetric_ram_2b is
generic (
WIDTHA : integer := 8;
SIZEA : integer := 256;
ADDRWIDTHA : integer := 8;
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diA : in std_logic_vector(WIDTHA-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doA : out std_logic_vector(WIDTHA-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end asymmetric_ram_2b;
architecture behavioral of asymmetric_ram_2b is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE : integer := max(SIZEA,SIZEB);
constant RATIO : integer := maxWIDTH / minWIDTH;
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
regA <= readA;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in 0 to RATIO-1 loop
ram(conv_integer(addrB & conv_std_logic_vector(i,log2(RATIO))))
:= diB((i+1)*minWIDTH-1 downto i*minWIDTH);
end loop;
end if;
for i in 0 to RATIO-1 loop
readB((i+1)*minWIDTH-1 downto i*minWIDTH)
<= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(RATIO))));
end loop;
end if;
regB <= readB;
end if;
end process;
doA <= regA;
doB <= regB;
end behavioral;
|
gpl-2.0
|
37fdb21cb1b72a62967648b63dc182d5
| 0.585954 | 3.423541 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dispin01/tb_rec02.vhdl
| 1 | 667 |
entity tb_rec02 is
end tb_rec02;
library ieee;
use ieee.std_logic_1164.all;
use work.rec02_pkg.all;
architecture behav of tb_rec02 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec02
port map (inp => inp, o => r);
process
begin
inp.a <= 5;
inp.b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
inp.a <= 2;
inp.b <= '1';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= 1;
inp.b <= '0';
wait for 1 ns;
assert r = '0' severity failure;
inp.a <= 4;
inp.b <= '0';
wait for 1 ns;
assert r = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
775a92cea292eb1b8921300d0c4a5e0b
| 0.565217 | 2.938326 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug037/physical.vhdl
| 2 | 32,800 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Martin Zabel
--
-- Package: This VHDL package declares new physical types and their
-- conversion functions.
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- NAMING CONVENTION:
-- t - time
-- p - period
-- d - delay
-- f - frequency
-- br - baud rate
-- vec - vector
--
-- ATTENTION:
-- This package is not supported by Xilinx Synthese Tools prior to 14.7!
--
-- It was successfully tested with:
-- - Xilinx Synthesis Tool (XST) 14.7 and Xilinx ISE Simulator (iSim) 14.7
-- - Quartus II 13.1
-- - QuestaSim 10.0d
-- - GHDL 0.31
--
-- Tool chains with known issues:
-- - Xilinx Vivado Synthesis 2014.4
--
-- Untested tool chains
-- - Xilinx Vivado Simulator (xSim) 2014.4
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
package physical is
type FREQ is range 0 to INTEGER'high units
Hz;
kHz = 1000 Hz;
MHz = 1000 kHz;
GHz = 1000 MHz;
end units;
type BAUD is range 0 to INTEGER'high units
Bd;
kBd = 1000 Bd;
MBd = 1000 kBd;
GBd = 1000 MBd;
end units;
type MEMORY is range 0 to INTEGER'high units
Byte;
KiB = 1024 Byte;
MiB = 1024 KiB;
GiB = 1024 MiB;
end units;
-- vector data types
type T_TIMEVEC is array(NATURAL range <>) of TIME;
type T_FREQVEC is array(NATURAL range <>) of FREQ;
type T_BAUDVEC is array(NATURAL range <>) of BAUD;
type T_MEMVEC is array(NATURAL range <>) of MEMORY;
-- if true: TimingToCycles reports difference between expected and actual result
constant C_PHYSICAL_REPORT_TIMING_DEVIATION : BOOLEAN := TRUE;
-- conversion functions
function to_time(f : FREQ) return TIME;
function to_freq(p : TIME) return FREQ;
function to_freq(br : BAUD) return FREQ;
function to_baud(str : STRING) return BAUD;
-- if-then-else
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY;
-- min/ max for 2 arguments
function tmin(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: min(arg1, arg2) for times
function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: min(arg1, arg2) for frequencies
function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: min(arg1, arg2) for symbols per second
function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: min(arg1, arg2) for memory
function tmax(arg1 : TIME; arg2 : TIME) return TIME; -- Calculates: max(arg1, arg2) for times
function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ; -- Calculates: max(arg1, arg2) for frequencies
function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD; -- Calculates: max(arg1, arg2) for symbols per second
function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY; -- Calculates: max(arg1, arg2) for memory
-- min/max/sum as vector aggregation
function tmin(vec : T_TIMEVEC) return TIME; -- Calculates: min(vec) for a time vector
function fmin(vec : T_FREQVEC) return FREQ; -- Calculates: min(vec) for a frequency vector
function bmin(vec : T_BAUDVEC) return BAUD; -- Calculates: min(vec) for a baud vector
function mmin(vec : T_MEMVEC) return MEMORY; -- Calculates: min(vec) for a memory vector
function tmax(vec : T_TIMEVEC) return TIME; -- Calculates: max(vec) for a time vector
function fmax(vec : T_FREQVEC) return FREQ; -- Calculates: max(vec) for a frequency vector
function bmax(vec : T_BAUDVEC) return BAUD; -- Calculates: max(vec) for a baud vector
function mmax(vec : T_MEMVEC) return MEMORY; -- Calculates: max(vec) for a memory vector
function tsum(vec : T_TIMEVEC) return TIME; -- Calculates: sum(vec) for a time vector
function fsum(vec : T_FREQVEC) return FREQ; -- Calculates: sum(vec) for a frequency vector
function bsum(vec : T_BAUDVEC) return BAUD; -- Calculates: sum(vec) for a baud vector
function msum(vec : T_MEMVEC) return MEMORY; -- Calculates: sum(vec) for a memory vector
-- convert standard types (NATURAL, REAL) to time (TIME)
function fs2Time(t_fs : INTEGER) return TIME;
function ps2Time(t_ps : INTEGER) return TIME;
function ns2Time(t_ns : INTEGER) return TIME;
function us2Time(t_us : INTEGER) return TIME;
function ms2Time(t_ms : INTEGER) return TIME;
function sec2Time(t_sec : INTEGER) return TIME;
function fs2Time(t_fs : REAL) return TIME;
function ps2Time(t_ps : REAL) return TIME;
function ns2Time(t_ns : REAL) return TIME;
function us2Time(t_us : REAL) return TIME;
function ms2Time(t_ms : REAL) return TIME;
function sec2Time(t_sec : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to period (TIME)
function Hz2Time(f_Hz : NATURAL) return TIME;
function kHz2Time(f_kHz : NATURAL) return TIME;
function MHz2Time(f_MHz : NATURAL) return TIME;
function GHz2Time(f_GHz : NATURAL) return TIME;
function Hz2Time(f_Hz : REAL) return TIME;
function kHz2Time(f_kHz : REAL) return TIME;
function MHz2Time(f_MHz : REAL) return TIME;
function GHz2Time(f_GHz : REAL) return TIME;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
function Hz2Freq(f_Hz : NATURAL) return FREQ;
function kHz2Freq(f_kHz : NATURAL) return FREQ;
function MHz2Freq(f_MHz : NATURAL) return FREQ;
function GHz2Freq(f_GHz : NATURAL) return FREQ;
function Hz2Freq(f_Hz : REAL) return FREQ;
function kHz2Freq(f_kHz : REAL) return FREQ;
function MHz2Freq(f_MHz : REAL) return FREQ;
function GHz2Freq(f_GHz : REAL) return FREQ;
-- convert physical types to standard type (REAL)
function to_real(t : TIME; scale : TIME) return REAL;
function to_real(f : FREQ; scale : FREQ) return REAL;
function to_real(br : BAUD; scale : BAUD) return REAL;
function to_real(mem : MEMORY; scale : MEMORY) return REAL;
-- convert physical types to standard type (INTEGER)
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING;
function to_string(f : FREQ; precision : NATURAL) return STRING;
function to_string(br : BAUD; precision : NATURAL) return STRING;
function to_string(mem : MEMORY; precision : NATURAL) return STRING;
end physical;
package body physical is
-- iSim 14.7 does not support fs in simulation (fs values are converted to 0 ps)
function MinimalTimeResolutionInSimulation return TIME is
begin
if (1 fs > 0 sec) then return 1 fs;
elsif (1 ps > 0 sec) then return 1 ps;
elsif (1 ns > 0 sec) then return 1 ns;
elsif (1 us > 0 sec) then return 1 us;
elsif (1 ms > 0 sec) then return 1 ms;
else return 1 sec;
end if;
end function;
-- real division for physical types
-- ===========================================================================
function div(a : TIME; b : TIME) return REAL is
constant MTRIS : TIME := MinimalTimeResolutionInSimulation;
variable a_real : real;
variable b_real : real;
begin
-- Quartus-II work-around
if a < 1 us then
a_real := real(a / MTRIS);
elsif a < 1 ms then
a_real := real(a / (1000 * MTRIS)) * 1000.0;
elsif a < 1 sec then
a_real := real(a / (1000000 * MTRIS)) * 1000000.0;
else
a_real := real(a / (1000000000 * MTRIS)) * 1000000000.0;
end if;
if b < 1 us then
b_real := real(b / MTRIS);
elsif b < 1 ms then
b_real := real(b / (1000 * MTRIS)) * 1000.0;
elsif b < 1 sec then
b_real := real(b / (1000000 * MTRIS)) * 1000000.0;
else
b_real := real(b / (1000000000 * MTRIS)) * 1000000000.0;
end if;
return a_real / b_real;
end function;
function div(a : FREQ; b : FREQ) return REAL is
begin
return real(a / 1 Hz) / real(b / 1 Hz);
end function;
function div(a : BAUD; b : BAUD) return REAL is
begin
return real(a / 1 Bd) / real(b / 1 Bd);
end function;
function div(a : MEMORY; b : MEMORY) return REAL is
begin
return real(a / 1 Byte) / real(b / 1 Byte);
end function;
-- conversion functions
-- ===========================================================================
function to_time(f : FREQ) return TIME is
variable res : TIME;
begin
res := div(1000 MHz, f) * 1 ns;
if (POC_VERBOSE = TRUE) then
report "to_time: f= " & to_string(f, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(p : TIME) return FREQ is
variable res : FREQ;
begin
if (p <= 1 sec) then res := div(1 sec, p) * 1 Hz;
else report "to_freq: input period exceeds output frequency scale." severity failure;
end if;
if (POC_VERBOSE = TRUE) then
report "to_freq: p= " & to_string(p, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_freq(br : BAUD) return FREQ is
variable res : FREQ;
begin
res := (br / 1 Bd) * 1 Hz;
if (POC_VERBOSE = TRUE) then
report "to_freq: br= " & to_string(br, 3) & " return " & to_string(res, 3) severity note;
end if;
return res;
end function;
function to_baud(str : STRING) return BAUD is
variable pos : INTEGER;
variable int : NATURAL;
variable base : POSITIVE;
variable frac : NATURAL;
variable digits : NATURAL;
begin
pos := str'low;
int := 0;
frac := 0;
digits := 0;
-- read integer part
for i in pos to str'high loop
if (chr_isDigit(str(i)) = TRUE) then int := int * 10 + to_digit_dec(str(i));
elsif (str(i) = '.') then pos := -i; exit;
elsif (str(i) = ' ') then pos := i; exit;
else pos := 0; exit;
end if;
end loop;
-- read fractional part
if ((pos < 0) and (-pos < str'high)) then
for i in -pos+1 to str'high loop
if ((frac = 0) and (str(i) = '0')) then next;
elsif (chr_isDigit(str(i)) = TRUE) then frac := frac * 10 + to_digit_dec(str(i));
elsif (str(i) = ' ') then digits := i + pos - 1; pos := i; exit;
else pos := 0; exit;
end if;
end loop;
end if;
-- abort if format is unknown
if (pos = 0) then report "to_baud: Unknown format" severity FAILURE; end if;
-- parse unit
pos := pos + 1;
if ((pos + 1 = str'high) and (str(pos to pos + 1) = "Bd")) then
return int * 1 Bd;
elsif (pos + 2 = str'high) then
if (str(pos to pos + 2) = "kBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 kBd) + (frac * 10**(3 - digits) * 1 Bd);
else return (int * 1 kBd) + (frac / 10**(digits - 3) * 100 Bd);
end if;
elsif (str(pos to pos + 2) = "MBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 MBd) + (frac * 10**(3 - digits) * 1 kBd);
elsif (digits <= 6) then return (int * 1 MBd) + (frac * 10**(6 - digits) * 1 Bd);
else return (int * 1 MBd) + (frac / 10**(digits - 6) * 100000 Bd);
end if;
elsif (str(pos to pos + 2) = "GBd") then
if (frac = 0) then return (int * 1 kBd);
elsif (digits <= 3) then return (int * 1 GBd) + (frac * 10**(3 - digits) * 1 MBd);
elsif (digits <= 6) then return (int * 1 GBd) + (frac * 10**(6 - digits) * 1 kBd);
elsif (digits <= 9) then return (int * 1 GBd) + (frac * 10**(9 - digits) * 1 Bd);
else return (int * 1 GBd) + (frac / 10**(digits - 9) * 100000000 Bd);
end if;
else
report "to_baud: Unknown unit." severity FAILURE;
end if;
else
report "to_baud: Unknown format" severity FAILURE;
end if;
end function;
-- if-then-else
-- ===========================================================================
function ite(cond : BOOLEAN; value1 : TIME; value2 : TIME) return TIME is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : FREQ; value2 : FREQ) return FREQ is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : BAUD; value2 : BAUD) return BAUD is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : BOOLEAN; value1 : MEMORY; value2 : MEMORY) return MEMORY is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- min/ max for 2 arguments
-- ===========================================================================
-- Calculates: min(arg1, arg2) for times
function tmin(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for frequencies
function fmin(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for symbols per second
function bmin(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: min(arg1, arg2) for memory
function mmin(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 < arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for times
function tmax(arg1 : TIME; arg2 : TIME) return TIME is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for frequencies
function fmax(arg1 : FREQ; arg2 : FREQ) return FREQ is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for symbols per second
function bmax(arg1 : BAUD; arg2 : BAUD) return BAUD is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- Calculates: max(arg1, arg2) for memory
function mmax(arg1 : MEMORY; arg2 : MEMORY) return MEMORY is
begin
if (arg1 > arg2) then return arg1; end if;
return arg2;
end function;
-- min/max/sum as vector aggregation
-- ===========================================================================
-- Calculates: min(vec) for a time vector
function tmin(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'high;
begin
for i in vec'range loop
if (vec(i) < res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a frequency vector
function fmin(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'high;
begin
for i in vec'range loop
if (integer(FREQ'pos(vec(i))) < integer(FREQ'pos(res))) then -- Quartus workaround
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a baud vector
function bmin(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'high;
begin
for i in vec'range loop
if (integer(BAUD'pos(vec(i))) < integer(BAUD'pos(res))) then -- Quartus workaround
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: min(vec) for a memory vector
function mmin(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'high;
begin
for i in vec'range loop
if (integer(MEMORY'pos(vec(i))) < integer(MEMORY'pos(res))) then -- Quartus workaround
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a time vector
function tmax(vec : T_TIMEVEC) return TIME is
variable res : TIME := TIME'low;
begin
for i in vec'range loop
if (vec(i) > res) then
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a frequency vector
function fmax(vec : T_FREQVEC) return FREQ is
variable res : FREQ := FREQ'low;
begin
for i in vec'range loop
if (integer(FREQ'pos(vec(i))) > integer(FREQ'pos(res))) then -- Quartus workaround
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a baud vector
function bmax(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := BAUD'low;
begin
for i in vec'range loop
if (integer(BAUD'pos(vec(i))) > integer(BAUD'pos(res))) then -- Quartus workaround
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: max(vec) for a memory vector
function mmax(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := MEMORY'low;
begin
for i in vec'range loop
if (integer(MEMORY'pos(vec(i))) > integer(MEMORY'pos(res))) then -- Quartus workaround
res := vec(i);
end if;
end loop;
return res;
end;
-- Calculates: sum(vec) for a time vector
function tsum(vec : T_TIMEVEC) return TIME is
variable res : TIME := 0 fs;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a frequency vector
function fsum(vec : T_FREQVEC) return FREQ is
variable res : FREQ := 0 Hz;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a baud vector
function bsum(vec : T_BAUDVEC) return BAUD is
variable res : BAUD := 0 Bd;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- Calculates: sum(vec) for a memory vector
function msum(vec : T_MEMVEC) return MEMORY is
variable res : MEMORY := 0 Byte;
begin
for i in vec'range loop
res := res + vec(i);
end loop;
return res;
end;
-- convert standard types (NATURAL, REAL) to time (TIME)
-- ===========================================================================
function fs2Time(t_fs : INTEGER) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : INTEGER) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : INTEGER) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : INTEGER) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : INTEGER) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : INTEGER) return TIME is
begin
return t_sec * 1 sec;
end function;
function fs2Time(t_fs : REAL) return TIME is
begin
return t_fs * 1 fs;
end function;
function ps2Time(t_ps : REAL) return TIME is
begin
return t_ps * 1 ps;
end function;
function ns2Time(t_ns : REAL) return TIME is
begin
return t_ns * 1 ns;
end function;
function us2Time(t_us : REAL) return TIME is
begin
return t_us * 1 us;
end function;
function ms2Time(t_ms : REAL) return TIME is
begin
return t_ms * 1 ms;
end function;
function sec2Time(t_sec : REAL) return TIME is
begin
return t_sec * 1 sec;
end function;
-- convert standard types (NATURAL, REAL) to period (TIME)
-- ===========================================================================
function Hz2Time(f_Hz : NATURAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : NATURAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : NATURAL) return TIME
is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : NATURAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
function Hz2Time(f_Hz : REAL) return TIME is
begin
return 1 sec / f_Hz;
end function;
function kHz2Time(f_kHz : REAL) return TIME is
begin
return 1 ms / f_kHz;
end function;
function MHz2Time(f_MHz : REAL) return TIME is
begin
return 1 us / f_MHz;
end function;
function GHz2Time(f_GHz : REAL) return TIME is
begin
return 1 ns / f_GHz;
end function;
-- convert standard types (NATURAL, REAL) to frequency (FREQ)
-- ===========================================================================
function Hz2Freq(f_Hz : NATURAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : NATURAL) return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : NATURAL) return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : NATURAL) return FREQ is
begin
return f_GHz * 1 GHz;
end function;
function Hz2Freq(f_Hz : REAL) return FREQ is
begin
return f_Hz * 1 Hz;
end function;
function kHz2Freq(f_kHz : REAL )return FREQ is
begin
return f_kHz * 1 kHz;
end function;
function MHz2Freq(f_MHz : REAL )return FREQ is
begin
return f_MHz * 1 MHz;
end function;
function GHz2Freq(f_GHz : REAL )return FREQ is
begin
return f_GHz * 1 GHz;
end function;
-- convert physical types to standard type (REAL)
-- ===========================================================================
function to_real(t : TIME; scale : TIME) return REAL is
begin
if (scale = 1 fs) then return div(t, 1 fs);
elsif (scale = 1 ps) then return div(t, 1 ps);
elsif (scale = 1 ns) then return div(t, 1 ns);
elsif (scale = 1 us) then return div(t, 1 us);
elsif (scale = 1 ms) then return div(t, 1 ms);
elsif (scale = 1 sec) then return div(t, 1 sec);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(f : FREQ; scale : FREQ) return REAL is
begin
if (scale = 1 Hz) then return div(f, 1 Hz);
elsif (scale = 1 kHz) then return div(f, 1 kHz);
elsif (scale = 1 MHz) then return div(f, 1 MHz);
elsif (scale = 1 GHz) then return div(f, 1 GHz);
-- elsif (scale = 1 THz) then return div(f, 1 THz);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(br : BAUD; scale : BAUD) return REAL is
begin
if (scale = 1 Bd) then return div(br, 1 Bd);
elsif (scale = 1 kBd) then return div(br, 1 kBd);
elsif (scale = 1 MBd) then return div(br, 1 MBd);
elsif (scale = 1 GBd) then return div(br, 1 GBd);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
function to_real(mem : MEMORY; scale : MEMORY) return REAL is
begin
if (scale = 1 Byte) then return div(mem, 1 Byte);
elsif (scale = 1 KiB) then return div(mem, 1 KiB);
elsif (scale = 1 MiB) then return div(mem, 1 MiB);
elsif (scale = 1 GiB) then return div(mem, 1 GiB);
else report "to_real: scale must have a value of '1 <unit>'" severity failure;
end if;
end;
-- convert physical types to standard type (INTEGER)
-- ===========================================================================
function to_int(t : TIME; scale : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(t, scale)));
when ROUND_DOWN => return integer(floor(to_real(t, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(t, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(f : FREQ; scale : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(f, scale)));
when ROUND_DOWN => return integer(floor(to_real(f, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(f, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(br : BAUD; scale : BAUD; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(br, scale)));
when ROUND_DOWN => return integer(floor(to_real(br, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(br, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
function to_int(mem : MEMORY; scale : MEMORY; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return INTEGER is
begin
case RoundingStyle is
when ROUND_UP => return integer(ceil(to_real(mem, scale)));
when ROUND_DOWN => return integer(floor(to_real(mem, scale)));
when ROUND_TO_NEAREST => return integer(round(to_real(mem, scale)));
when others => null;
end case;
report "to_int: unsupported RoundingStyle: " & T_ROUNDING_STYLE'image(RoundingStyle) severity failure;
end;
-- calculate needed counter cycles to achieve a given 1. timing/delay and 2. frequency/period
-- ===========================================================================
-- @param Timing A given timing or delay, which should be achived
-- @param Clock_Period The period of the circuits clock
-- @RoundingStyle Default = round to nearest; other choises: ROUND_UP, ROUND_DOWN
function TimingToCycles(Timing : TIME; Clock_Period : TIME; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
variable res_real : REAL;
variable res_nat : NATURAL;
variable res_time : TIME;
variable res_dev : REAL;
begin
res_real := div(Timing, Clock_Period);
case RoundingStyle is
when ROUND_TO_NEAREST => res_nat := natural(round(res_real));
when ROUND_UP => res_nat := natural(ceil(res_real));
when ROUND_DOWN => res_nat := natural(floor(res_real));
when others => report "RoundingStyle '" & T_ROUNDING_STYLE'image(RoundingStyle) & "' not supported." severity failure;
end case;
res_time := CyclesToDelay(res_nat, Clock_Period);
res_dev := (div(res_time, Timing) - 1.0) * 100.0;
if (POC_VERBOSE = TRUE) then
report "TimingToCycles: " & CR &
" Timing: " & to_string(Timing, 3) & CR &
" Clock_Period: " & to_string(Clock_Period, 3) & CR &
" RoundingStyle: " & str_substr(T_ROUNDING_STYLE'image(RoundingStyle), 7) & CR &
" res_real = " & str_format(res_real, 3) & CR &
" => " & INTEGER'image(res_nat)
severity note;
end if;
if (C_PHYSICAL_REPORT_TIMING_DEVIATION = TRUE) then
report "TimingToCycles (timing deviation report): " & CR &
" timing to achieve: " & to_string(Timing, 3) & CR &
" calculated cycles: " & INTEGER'image(res_nat) & " cy" & CR &
" resulting timing: " & to_string(res_time, 3) & CR &
" deviation: " & to_string(res_time - Timing, 3) & " (" & str_format(res_dev, 2) & "%)"
severity note;
end if;
return res_nat;
end;
function TimingToCycles(Timing : TIME; Clock_Frequency : FREQ; RoundingStyle : T_ROUNDING_STYLE := ROUND_UP) return NATURAL is
begin
return TimingToCycles(Timing, to_time(Clock_Frequency), RoundingStyle);
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Period : TIME) return TIME is
begin
return Clock_Period * Cycles;
end function;
function CyclesToDelay(Cycles : NATURAL; Clock_Frequency : FREQ) return TIME is
begin
return CyclesToDelay(Cycles, to_time(Clock_Frequency));
end function;
-- convert and format physical types to STRING
function to_string(t : TIME; precision : NATURAL) return STRING is
variable tt : TIME;
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
tt := abs t;
if (tt < 1 ps) then
unit(1 to 2) := "fs";
value := to_real(tt, 1 fs);
elsif (tt < 1 ns) then
unit(1 to 2) := "ps";
value := to_real(tt, 1 ps);
elsif (tt < 1 us) then
unit(1 to 2) := "ns";
value := to_real(tt, 1 ns);
elsif (tt < 1 ms) then
unit(1 to 2) := "us";
value := to_real(tt, 1 us);
elsif (tt < 1 sec) then
unit(1 to 2) := "ms";
value := to_real(tt, 1 ms);
else
unit := "sec";
value := to_real(tt, 1 sec);
end if;
return ite(t >= 0 fs, str_format(value, precision) & " " & str_trim(unit),
'-' & str_format(value, precision) & " " & str_trim(unit));
end function;
function to_string(f : FREQ; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (f < 1 kHz) then
unit(1 to 2) := "Hz";
value := to_real(f, 1 Hz);
elsif (f < 1 MHz) then
unit := "kHz";
value := to_real(f, 1 kHz);
elsif (f < 1 GHz) then
unit := "MHz";
value := to_real(f, 1 MHz);
else
unit := "GHz";
value := to_real(f, 1 GHz);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(br : BAUD; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (br < 1 kBd) then
unit(1 to 2) := "Bd";
value := to_real(br, 1 Bd);
elsif (br < 1 MBd) then
unit := "kBd";
value := to_real(br, 1 kBd);
elsif (br < 1 GBd) then
unit := "MBd";
value := to_real(br, 1 MBd);
else
unit := "GBd";
value := to_real(br, 1 GBd);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
function to_string(mem : MEMORY; precision : NATURAL) return STRING is
variable unit : STRING(1 to 3) := (others => C_POC_NUL);
variable value : REAL;
begin
if (mem < 1 KiB) then
unit(1) := 'B';
value := to_real(mem, 1 Byte);
elsif (mem < 1 MiB) then
unit := "KiB";
value := to_real(mem, 1 KiB);
elsif (mem < 1 GiB) then
unit := "MiB";
value := to_real(mem, 1 MiB);
else
unit := "GiB";
value := to_real(mem, 1 GiB);
end if;
return str_format(value, precision) & " " & str_trim(unit);
end function;
end package body;
|
gpl-2.0
|
597cc68adaab4209a339c22d06c1ae77
| 0.60561 | 3.142063 | false | false | false | false |
pleonex/Efponga
|
Pong/escenario.vhd
| 1 | 6,726 |
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.NUMERIC_STD.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY escenario IS
PORT (
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Controles del juego
btn_up1 : IN STD_LOGIC;
btn_down1 : IN STD_LOGIC;
btn_up2 : IN STD_LOGIC;
btn_down2 : IN STD_LOGIC;
-- Marcados de 7 segmentos
hex00 : OUT STD_LOGIC;
hex01 : OUT STD_LOGIC;
hex02 : OUT STD_LOGIC;
hex03 : OUT STD_LOGIC;
hex04 : OUT STD_LOGIC;
hex05 : OUT STD_LOGIC;
hex06 : OUT STD_LOGIC;
hex20 : OUT STD_LOGIC;
hex21 : OUT STD_LOGIC;
hex22 : OUT STD_LOGIC;
hex23 : OUT STD_LOGIC;
hex24 : OUT STD_LOGIC;
hex25 : OUT STD_LOGIC;
hex26 : OUT STD_LOGIC
);
END escenario;
ARCHITECTURE funcional OF escenario IS
-- Pelota de juego
COMPONENT bola
PORT(
-- Variables de dibujado
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Control de bola
bola_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rebote_xIzq : IN STD_LOGIC;
rebote_xDer : IN STD_LOGIC;
rebote_y : IN STD_LOGIC;
gol1 : OUT STD_LOGIC;
gol2 : OUT STD_LOGIC
);
END COMPONENT;
-- Pala de juego
COMPONENT pala
GENERIC (
DEFAULT_POS_X : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 10)
);
PORT (
-- Puertos para dibujado
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Botones de control
btn_up : IN STD_LOGIC;
btn_down : IN STD_LOGIC;
-- Control de rebotes de bola
bola_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rebote : OUT STD_LOGIC
);
END COMPONENT;
-- Marcador
COMPONENT marcador
PORT (
numero : IN UNSIGNED(3 DOWNTO 0);
hex0 : OUT STD_LOGIC;
hex1 : OUT STD_LOGIC;
hex2 : OUT STD_LOGIC;
hex3 : OUT STD_LOGIC;
hex4 : OUT STD_LOGIC;
hex5 : OUT STD_LOGIC;
hex6 : OUT STD_LOGIC
);
END COMPONENT;
-- Constantes de la pantalla
CONSTANT PANTALLA_ANCHO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(640, 10);
CONSTANT PANTALLA_ALTO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(480, 10);
-- Variables
SIGNAL red_bola, red_palaIzq, red_palaDer : STD_LOGIC;
SIGNAL green_bola, green_palaIzq, green_palaDer : STD_LOGIC;
SIGNAL blue_bola, blue_palaIzq, blue_palaDer : STD_LOGIC;
SIGNAL bola_x, bola_y, bola_size_x, bola_size_y : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rebote_palaIzq, rebote_palaDer : STD_LOGIC;
SIGNAL contador1 : UNSIGNED(3 DOWNTO 0);
SIGNAL contador2 : UNSIGNED(3 DOWNTO 0);
SIGNAL gol1 : STD_LOGIC;
SIGNAL gol2 : STD_LOGIC;
BEGIN
Red <= red_bola or red_palaIzq or red_palaDer;
Green <= green_bola or green_palaIzq or green_palaDer;
Blue <= blue_bola or blue_palaIzq or blue_palaDer;
PROCESS (vert_sync)
BEGIN
IF (vert_sync'event AND vert_sync = '1') THEN
-- FIX: Arreglar fallo de doble detección de borde
contador1 <= contador1 + gol1;
contador2 <= contador2 + gol2;
END IF;
END PROCESS;
PELOTA: bola
PORT MAP (
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_column,
Red => red_bola,
Green => green_bola,
Blue => blue_bola,
bola_x => bola_x,
bola_y => bola_y,
bola_size_x => bola_size_x,
bola_size_y => bola_size_y,
rebote_xIzq => rebote_palaDer,
rebote_xDer => rebote_palaIzq,
rebote_y => '0',
gol1 => gol1,
gol2 => gol2
);
PALA_IZQ: pala
GENERIC MAP (
DEFAULT_POS_X => CONV_STD_LOGIC_VECTOR(10, 10)
)
PORT MAP (
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_column,
Red => red_palaIzq,
Green => green_palaIzq,
Blue => blue_palaIzq,
btn_up => btn_up1,
btn_down => btn_down1,
bola_x => bola_x,
bola_y => bola_y,
bola_size_x => bola_size_x,
bola_size_y => bola_size_y,
rebote => rebote_palaIzq
);
PALA_DER: pala
GENERIC MAP (
DEFAULT_POS_X => PANTALLA_ANCHO - CONV_STD_LOGIC_VECTOR(10, 10)
)
PORT MAP (
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_column,
Red => red_palaDer,
Green => green_palaDer,
Blue => blue_palaDer,
btn_up => btn_up2,
btn_down => btn_down2,
bola_x => bola_x,
bola_y => bola_y,
bola_size_x => bola_size_x,
bola_size_y => bola_size_y,
rebote => rebote_palaDer
);
MARCADOR1: marcador
PORT MAP (
numero => contador1,
hex0 => hex00,
hex1 => hex01,
hex2 => hex02,
hex3 => hex03,
hex4 => hex04,
hex5 => hex05,
hex6 => hex06
);
MARCADOR2: marcador
PORT MAP (
numero => contador2,
hex0 => hex20,
hex1 => hex21,
hex2 => hex22,
hex3 => hex23,
hex4 => hex24,
hex5 => hex25,
hex6 => hex26
);
END funcional;
|
gpl-3.0
|
b1dfc6b1438ef39919ec0e631803b09f
| 0.509813 | 3.431633 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd
| 4 | 1,776 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity notch_filter is
port ( terminal input, output, vdd, vss, gnd : electrical );
end entity notch_filter;
----------------------------------------------------------------
architecture opamp_based of notch_filter is
component simple_opamp is
port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
end component simple_opamp;
-- ...
terminal opamp1_in, opamp1_out, opamp2_in, -- ...
-- not in book
other_terminal
-- end not in book
: electrical;
begin
opamp1 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out,
vdd => vdd, vss => vss, gnd => gnd );
opamp2 : component simple_opamp
port map ( plus_in => gnd, minus_in => opamp2_in, output => output,
vdd => vdd, vss => vss, gnd => gnd );
-- other component instances
-- ...
end architecture opamp_based;
|
gpl-2.0
|
98552fd4c170825d784e8bf3f7c7548a
| 0.655968 | 4.092166 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd
| 4 | 4,804 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p07n01i01348ent IS
END c08s04b01x00p07n01i01348ent;
ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS
-- Local signals.
signal S : BIT := '0';
BEGIN
TESTING: PROCESS
-- local variables.
variable S_INITIAL : BIT;
variable ShouldBeTime : TIME;
variable k : integer := 0;
BEGIN
-- 0. Keep around the initial value of S.
S_INITIAL := S;
-- 1. When no preemption necessary, verify the results.
S <= transport (not S) after 10 ns, (S) after 20 ns;
-- a. Wait for first transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Wait for second transaction.
ShouldBeTime := NOW + 10 ns;
wait on S;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- 2. Preempt a transaction which is to occur at the same time as second one.
S_INITIAL := S;
S <= transport (S) after 10 ns;
S <= transport (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 3. Preempt a transaction which is to occur at a later time than second one.
S_INITIAL := S;
S <= transport (S) after 15 ns;
S <= transport (not S) after 10 ns; -- Should preempt first transaction.
-- a. Verify that the second transaction comes as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
-- b. Verify that the first transaction has been preempted.
ShouldBeTime := NOW + 10 ns;
wait on S for 10 ns;
if (ShouldBeTime /= now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
-- 4. Preempt multiple transactions.
S_INITIAL := S;
S <= transport (S) after 15 ns, (not S) after 30 ns;
S <= transport (not S) after 10 ns, (S) after 20 ns;
-- a. Verify that the second transactions come as expected.
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= not S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = (not S_INITIAL));
ShouldBeTime := NOW + 10 ns;
wait on S;
if (ShouldBeTime /= now or S /= S_INITIAL) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (S = S_INITIAL);
-- b. Verify that the first transactions have been preempted.
ShouldBeTime := NOW + 40 ns;
wait on S for 40 ns;
if (ShouldBeTime /= now) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p07n01i01348"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p07n01i01348arch;
|
gpl-2.0
|
2ae0f75e9866e7df9750222322a76c8f
| 0.623855 | 3.861736 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd
| 4 | 1,385 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( S, R : in bit; Q : out bit );
end entity SR_flipflop;
architecture checking of SR_flipflop is
begin
set_reset : process (S, R) is
begin
assert S = '1' nand R = '1';
if S = '1' then
Q <= '1';
end if;
if R = '1' then
Q <= '0';
end if;
end process set_reset;
end architecture checking;
|
gpl-2.0
|
fe8ca922896a56475df607cb1df27344
| 0.607942 | 3.890449 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd
| 3 | 50,277 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(31 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1_9.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1_9.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1_9.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1_9.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1_9.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1_9.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
|
gpl-3.0
|
2e80be8da04d3a0439007cb261a23942
| 0.398592 | 4.339461 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue301/src/branch_distance.vhd
| 7 | 3,100 |
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Branch distance calculation unit.
--! @author Markus Fehrenz
--! @date 2011/08/04
--!
--! @details Each branch has to be calculated only once.
--! The branch calculations are configured with a generic.
--! There is no limitation in branch calculations.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
entity branch_distance is
generic(
EDGE_WEIGHT : in std_logic_vector(0 to NUMBER_PARITY_BITS - 1)
);
port(
clk : in std_logic;
rst : in std_logic;
--
-- Input LLR values
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in t_input_block;
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Output branch metrics, going to ACS unit.
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0);
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic
);
end entity branch_distance;
architecture rtl of branch_distance is
signal m_axis_output_tvalid_int : std_logic;
signal s_axis_input_tready_int : std_logic;
begin
-- We are ready, when we are allowed to write to the output, or the output is idle.
s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' else
'0';
-- Connect internal versions of signal to output port.
s_axis_input_tready <= s_axis_input_tready_int;
m_axis_output_tvalid <= m_axis_output_tvalid_int;
-- Calculation of specific branch distance with a geometric distance function.
pr_branch : process(clk) is
variable v_branch_result : integer;
begin
if rising_edge(clk) then
if rst = '1' then
m_axis_output_tvalid_int <= '0';
m_axis_output_tdata <= (others => '0');
m_axis_output_tlast <= '0';
else
if m_axis_output_tvalid_int = '1' and m_axis_output_tready = '1' then
m_axis_output_tvalid_int <= '0';
m_axis_output_tlast <= '0';
end if;
if s_axis_input_tready_int = '1' and s_axis_input_tvalid = '1' then
v_branch_result := 0;
for i in NUMBER_PARITY_BITS - 1 downto 0 loop
--
-- Either the value is added or subtracted, depending on
-- the current branch metric we are computing.
--
if EDGE_WEIGHT(i) = '0' then
v_branch_result := v_branch_result + to_integer(s_axis_input_tdata(i));
else
v_branch_result := v_branch_result - to_integer(s_axis_input_tdata(i));
end if;
end loop;
m_axis_output_tdata <= std_logic_vector(to_signed(v_branch_result, BW_BRANCH_RESULT));
m_axis_output_tvalid_int <= '1';
m_axis_output_tlast <= s_axis_input_tlast;
end if;
end if;
end if;
end process pr_branch;
end architecture rtl;
|
gpl-2.0
|
8cc276ca7b09fccc9d88774495dde43a
| 0.647742 | 3.042198 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/RegisterFile.vhd
| 1 | 2,075 |
--
-- RegisterFile
--
--
-- A register file implementation in VHDL.
--
-- Since we have a 10-bit operand to work with, we can implement 32 registers.
--
-- Harrison Statham
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RegisterFile is
port (
clock : in std_logic;
resetn : in std_logic;
-- Read/Write Signals.
writeEnable : in std_logic;
-- Read/Write addresses.
readAddrA : in std_logic_vector(3 downto 0);
readAddrB : in std_logic_vector(3 downto 0);
writeAddr : in std_logic_vector(3 downto 0);
-- In register is the data that we want to write to some given register.
inReg : in std_logic_vector(15 downto 0);
-- Get two registers' contents.
outRegA : out std_logic_vector(15 downto 0)
outRegB : out std_logic_vector(15 downto 0)
);
end RegisterFile;
architecture arch of RegisterFile is
begin
--
-- Register File
--
-- An array that holds the contents of the registers.
--
type register_file is array(0 to 31) of std_logic_vector(15 downto 0);
signal registers : register_file;
process (clock, resetn)
begin
-- If we are in a reset state, then we want to clear all of the register contents.
if (resetn = '0') then
-- Set all of the registers in the register file to 0.
-- registers <= x"0000";
-- On the rising edge of the clock, we want to write the data into, and read the data
-- from the register file, and "return" it to the "caller" for use.
elsif (RISING_EDGE(clock)) then
--
-- Note: I didn't know how to implement the "to_integer(unsigned(...))" portion.
-- I found this link on SO.
--
-- See: http://stackoverflow.com/questions/19942067/writing-a-register-file-in-vhdl
--
outRegA <= registers(to_integer(unsigned(readAddrA)));
outRegB <= registers(to_integer(unsigned(readAddrB)));
if (writeSignal = '1') then
registers(to_integer(unsigned(writeAddr))) <= inReg;
end if;
end if;
end process;
end architecture arch;
|
mit
|
9a47f02de93b24c712a9f0cc3e5ba131
| 0.671807 | 3.129713 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/insert01/tb_insert02.vhdl
| 1 | 558 |
entity tb_insert02 is
end tb_insert02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_insert02 is
signal a : std_logic_vector (3 downto 0);
signal b : std_logic_vector (1 downto 0);
signal o0, o1, o2 : std_logic_vector (3 downto 0);
begin
dut: entity work.insert02
port map (a, b, o0, o1, o2);
process
begin
a <= "0111";
b <= "10";
wait for 1 ns;
assert o0 = "0110" severity failure;
assert o1 = "0101" severity failure;
assert o2 = "1011" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
b55c8634b44ce749f83d94245ec767ff
| 0.646953 | 3.04918 | false | false | false | false |
pleonex/Efponga
|
Pong/marcador.vhd
| 1 | 2,993 |
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY marcador IS
PORT (
numero : IN UNSIGNED(3 DOWNTO 0);
hex0 : OUT STD_LOGIC;
hex1 : OUT STD_LOGIC;
hex2 : OUT STD_LOGIC;
hex3 : OUT STD_LOGIC;
hex4 : OUT STD_LOGIC;
hex5 : OUT STD_LOGIC;
hex6 : OUT STD_LOGIC
);
END marcador;
ARCHITECTURE funcional OF marcador IS
BEGIN
PROCESS (numero)
BEGIN
CASE numero IS
WHEN x"0" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '1';
WHEN x"1" =>
hex0 <= '1';
hex1 <= '0';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '1';
hex6 <= '1';
WHEN x"2" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '1';
hex3 <= '0';
hex4 <= '0';
hex5 <= '1';
hex6 <= '0';
WHEN x"3" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '1';
hex5 <= '1';
hex6 <= '0';
WHEN x"4" =>
hex0 <= '0';
hex1 <= '1';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '0';
hex6 <= '0';
WHEN x"5" =>
hex0 <= '0';
hex1 <= '1';
hex2 <= '0';
hex3 <= '0';
hex4 <= '1';
hex5 <= '0';
hex6 <= '0';
WHEN x"6" =>
hex0 <= '0';
hex1 <= '1';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '0';
WHEN x"7" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '0';
hex6 <= '1';
WHEN x"8" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '0';
WHEN x"9" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '0';
hex6 <= '0';
WHEN OTHERS =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '0';
END CASE;
END process;
END funcional;
|
gpl-3.0
|
2298137f3827b058a87380e266728df2
| 0.268961 | 3.783818 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/sip_check_data/performance.vhd
| 1 | 5,789 |
-------------------------------------------------------------------------------------
-- FILE NAME : performance.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - toplevel_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Counts clock cycles and valids
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity performance is
port (
clk_in : in std_logic;
rst_in : in std_logic;
start_in : in std_logic;
in_val : in std_logic;
out_val : in std_logic;
cycle_cnt : out std_logic_vector(63 downto 0);
in_cnt : out std_logic_vector(63 downto 0);
out_cnt : out std_logic_vector(63 downto 0)
);
end performance;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of performance is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type state_m is (T_IDLE, T_COUNT, T_DONE);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal state_reg : state_m;
signal timer_count : std_logic_vector(63 downto 0);
signal input_count : std_logic_vector(63 downto 0);
signal output_count : std_logic_vector(63 downto 0);
signal count_rst : std_logic;
signal valid : std_logic;
signal input_valid : std_logic;
signal output_valid : std_logic;
--***********************************************************************************
begin
--***********************************************************************************
-- output mapping
cycle_cnt <= timer_count;
out_cnt <= output_count;
in_cnt <= input_count;
-- control state machine
process (clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
state_reg <= T_IDLE;
timer_count <= (others=>'0');
count_rst <= '1';
valid <= '0';
input_valid <= '0';
output_valid <= '0';
else
input_valid <= valid and in_val;
output_valid <= valid and out_val;
case state_reg is
when T_IDLE =>
timer_count <= (others=>'0');
count_rst <= '1'; -- don't allow counting
valid <= '0'; -- don't accept data
if start_in = '1' then
state_reg <= T_COUNT;
end if;
when T_COUNT =>
timer_count <= timer_count + 1;
state_reg <= T_COUNT;
count_rst <= '0'; -- allow counting
valid <= '1'; -- accept data
if start_in = '0' then
state_reg <= T_DONE;
end if;
when T_DONE =>
valid <= '0'; -- allow counting (hold)
count_rst <= '0'; -- don't accept data
if start_in = '1' then
state_reg <= T_IDLE;
end if;
when others =>
timer_count <= (others=>'0');
count_rst <= '1';
valid <= '0';
state_reg <= T_IDLE;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------------
-- Input counter process
-------------------------------------------------------------------------------------
process(clk_in, count_rst)
begin
if rising_edge(clk_in) then
if count_rst = '1' then
input_count <= (others=>'0');
else
if input_valid = '1' then
input_count <= input_count + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------
-- Output counter process
-------------------------------------------------------------------------------------
process(clk_in, count_rst)
begin
if rising_edge(clk_in) then
if count_rst = '1' then
output_count <= (others=>'0');
else
if output_valid = '1' then
output_count <= output_count + 1;
end if;
end if;
end if;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
8feed9dedc6f56a1c146094a8f00d651
| 0.326827 | 5.405229 | false | false | false | false |
nickg/nvc
|
test/regress/logical3.vhd
| 1 | 608 |
entity logical3 is
end entity;
architecture test of logical3 is
signal v : bit_vector(1 to 3);
begin
process is
begin
v <= "110";
wait for 1 ns;
assert and v = '0';
assert nand v = '1';
assert or v = '1';
assert nor v = '0';
assert xor v = '0';
assert xnor v = '1';
v <= "111";
wait for 1 ns;
assert and v = '1';
assert nand v = '0';
assert or v = '1';
assert nor v = '0';
assert xor v = '1';
assert xnor v = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
266c6eb3ff66414dd2929fd4f5c4ea0b
| 0.465461 | 3.619048 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
| 4 | 27,275 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal limit_in : electrical;
terminal ll_in : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
f2 => 2000.0,
f1 => 5.0,
k => 400.0
)
port map(
input => ll_in,
output => limit_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => limit_in,
output => servo_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- library IEEE;
-- use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang > ang_max use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang > ang_min use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_sine.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Electrical sinusoidal voltage source
-- Includes frequency domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/03 1.1 Mentor Graphics Changed generics from real to
-- voltage.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_Mech_Domain is
end TB_CS2_Mech_Domain;
architecture TB_CS2_Mech_Domain of TB_CS2_Mech_Domain is
-- Component declarations
-- Signal declarations
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal rudder : rotational;
terminal src_in : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => mot_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
XCMP35 : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP36 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
v6 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 4.8
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
end TB_CS2_Mech_Domain;
--
|
gpl-2.0
|
b02e54796c6a65b85558a0f80d147ca8
| 0.567773 | 4.397775 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd
| 4 | 1,611 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_variable_comparator is
end tb_variable_comparator;
architecture TB_variable_comparator of tb_variable_comparator is
-- Component declarations
-- Signal declarations
terminal in_src, v_ref : electrical;
signal cmp_out : std_logic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
C1 : entity work.variable_comparator(ideal)
port map(
a => in_src,
ref => electrical_ref,
d => cmp_out
);
end TB_variable_comparator;
|
gpl-2.0
|
8999ac8230ed126c7b23b7dc8d231480
| 0.675357 | 4.141388 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1043/ent.vhdl
| 1 | 362 |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
generic (
g : natural := 8
);
port (
o1 : out std_logic;
o2 : out std_logic
);
end;
architecture a of ent is
constant x : real := real(g);
constant a : natural := g;
constant y : real := real(a);
begin
o1 <= '1' when integer(x) = 8 else '0';
o2 <= '1' when integer(y) = 8 else '0';
end;
|
gpl-2.0
|
971ff3fb174b8f7d637e56903fad1800
| 0.596685 | 2.496552 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd
| 4 | 2,270 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_chkdiv.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity check_div is
end entity check_div;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behav of check_div is
begin
checker : process is
variable bv_a, bv_b, bv_quotient, bv_remainder : bit_vector(3 downto 0);
variable div_by_zero : boolean;
begin
for a in 0 to 15 loop
for b in 0 to 15 loop
bv_a := natural_to_bv(a, bv_a'length);
bv_b := natural_to_bv(b, bv_b'length);
bv_divu(bv_a, bv_b, bv_quotient, bv_remainder, div_by_zero);
if b = 0 then
assert div_by_zero
report integer'image(a) & '/' & integer'image(b)
& ": div_by_zero not true";
else
assert not div_by_zero
report integer'image(a) & '/' & integer'image(b)
& ": div_by_zero not false";
assert bv_to_natural(bv_quotient) = a / b
report integer'image(a) & '/' & integer'image(b)
& ": quotient = " & integer'image(bv_to_natural(bv_quotient));
assert bv_to_natural(bv_remainder) = a rem b
report integer'image(a) & '/' & integer'image(b)
& ": remainder = " & integer'image(bv_to_natural(bv_remainder));
end if;
end loop;
end loop;
wait;
end process checker;
end architecture behav;
|
gpl-2.0
|
2ccdd75ee82bf16817c03c2202fdd0af
| 0.608811 | 3.649518 | false | false | false | false |
nickg/nvc
|
test/simp/allsens.vhd
| 1 | 1,794 |
entity allsens is
end entity;
architecture test of allsens is
type bv_array is array (natural range <>) of bit_vector(1 to 3);
signal x, y : bit;
signal v : bit_vector(1 to 3);
signal z : bv_array(1 to 3);
signal n : integer range v'range := 3;
begin
p0: process (all) is -- (y)
begin
x <= y;
end process;
p1: assert v(1) = '0'; -- v(1)
p2: assert v(n) = '0'; -- v, n
p3: assert z(1)(2) = '0'; -- z(1)(2)
p4: assert z(n)(2) = '0'; -- z, n
p5: assert z(2)(n) = '0'; -- z(2), n
p6: assert v(1 to 2) = "00"; -- v(1 to 2)
p7: assert v(1 to n) = "00"; -- v, n
p8: assert z(n)(1 to 2) = "00"; -- z, n
p9: assert z(1 to 2)(n) = "00"; -- z(1 to 2), n
p10: process (all) is -- n, y
begin
v(n) <= y;
end process;
p11: process (all) is -- n, y, v(1), z(1)
variable b : bit_vector(0 to 1);
begin
if n > 5 then
x <= y;
else
b(bit'pos(v(1))) := z(1)(n);
end if;
end process;
p12: process (all) is -- x, v(1), v(2)
procedure proc (signal s : out bit) is
begin
s <= v(2);
end procedure;
begin
case x is
when '0' =>
v(0) <= v(1);
when '1' =>
proc(y);
end case;
end process;
p13: process (all) is -- n, v
begin
for i in 1 to n loop
assert v(i) = '1';
end loop;
while n < 5 loop
n <= n + 1;
end loop;
end process;
p14: v <= x & y & v(2); -- x, y, v(2)
end architecture;
|
gpl-3.0
|
055c48b2c06202e29edf2d9275005a77
| 0.392977 | 3.082474 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sg_if.vhd
| 3 | 47,020 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sg_if.vhd
-- Description: This entity is the MM2S Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Master AXI Control Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
desc_fetch_done : out std_logic ; --
updt_pending : out std_logic ;
packet_in_progress : out std_logic ; --
--
-- MM2S Descriptor Update Request (from mm2s_sm) --
desc_update_done : out std_logic ; --
--
mm2s_sts_received_clr : out std_logic ; --
mm2s_sts_received : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_done : in std_logic ; --
mm2s_interr : in std_logic ; --
mm2s_slverr : in std_logic ; --
mm2s_decerr : in std_logic ; --
mm2s_tag : in std_logic_vector(3 downto 0) ; --
mm2s_halt : in std_logic ; --
--
-- Control Stream Output --
cntrlstrm_fifo_wren : out std_logic ; --
cntrlstrm_fifo_din : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : in std_logic ; --
--
--
-- MM2S Descriptor Field Output --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_new_curdesc_wren : out std_logic ; --
--
mm2s_desc_baddress : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : out std_logic ; --
mm2s_desc_sof : out std_logic ; --
mm2s_desc_cmplt : out std_logic ; --
mm2s_desc_info : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_mm2s_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(4 downto 0) := (others => '0');
-- Used to determine when Control word is coming, in order to check SOF bit.
-- This then indicates that the app fields need to be directed towards the
-- control stream fifo.
-- Word Five Count
-- Incrementing these counts by 2 as i am now sending two extra fields from BD
--constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "1011"; --"0111";
constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "0001";
-- Word Six Count
--constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0101"; --"1000";
constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0010";
-- Word Seven Count
--constant NINE_COUNT : std_logic_vector(3 downto 0) := "1010"; --"1001";
constant NINE_COUNT : std_logic_vector(3 downto 0) := "0011";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Fetch control signals for driving out control app stream
signal analyze_control : std_logic := '0';
signal redirect_app : std_logic := '0';
signal redirect_app_d1 : std_logic := '0';
signal redirect_app_re : std_logic := '0';
signal redirect_app_hold : std_logic := '0';
signal mask_fifo_write : std_logic := '0';
-- Current descriptor control and fetch throttle control
signal mm2s_new_curdesc_wren_i : std_logic := '0';
signal mm2s_pending_update : std_logic := '0';
signal mm2s_pending_ptr_updt : std_logic := '0';
-- Descriptor Update Signals
signal mm2s_complete : std_logic := '0';
signal mm2s_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_xferd_bytes_int : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Update Descriptor Pointer Holding Registers
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_64_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
-- Update Descriptor Status Holding Register
signal updt_desc_reg2 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
-- Pointer shift control
signal updt_shftenbl : std_logic := '0';
-- Update pointer stream
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Update status stream
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status control
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal packet_start : std_logic := '0';
signal packet_end : std_logic := '0';
signal mm2s_halt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cdc_d2 : std_logic := '0';
signal mm2s_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cdc_d2 : SIGNAL IS "true";
signal temp : std_logic := '0';
signal m_axis_mm2s_ftch_tlast_new : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
mm2s_desc_blength <= mm2s_desc_blength_i;
mm2s_desc_blength_v <= mm2s_desc_blength_v_i;
mm2s_desc_blength_s <= mm2s_desc_blength_s_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_mm2s_ftch_tlast_new
and m_axis_mm2s_ftch_tvalid_new;
-- pass out of module
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_mm2s_ftch_tvalid_new
and ftch_tready
and desc_fetch_req
and not mm2s_pending_update;
-- Passed curdes write out to register module
mm2s_new_curdesc_wren <= desc_fetch_done_i; --mm2s_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch1_desc_available; --m_axis_mm2s_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_d1_cdc_tig <= '0';
-- -- mm2s_halt_d2 <= '0';
-- -- else
-- mm2s_halt_d1_cdc_tig <= mm2s_halt;
-- mm2s_halt_cdc_d2 <= mm2s_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_d2 <= mm2s_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_d2 <= mm2s_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
packet_start <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_SOF_BIT) = '1'
else '0';
packet_end <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_EOF_BIT) = '1'
else '0';
REG_PACKET_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or packet_end = '1')then
packet_in_progress <= '0';
elsif(packet_start = '1')then
packet_in_progress <= '1';
end if;
end if;
end process REG_PACKET_PROGRESS;
-- Status/Control stream enabled therefore APP fields are included
GEN_FTCHIF_WITH_APP : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
-- Control Stream Ethernet TAG
constant ETHERNET_CNTRL_TAG : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH - 1 downto 0)
:= X"A000_0000";
begin
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); -- downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65);
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 5 are reserved and thus don't care
-- CR 583779, need to pass on tuser and cache information
mm2s_desc_info <= (others => '0'); --desc_reg4; -- this coincides with desc_fetch_done
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= desc_reg8;
mm2s_desc_app1 <= desc_reg9;
mm2s_desc_app2 <= desc_reg10;
mm2s_desc_app3 <= desc_reg11;
mm2s_desc_app4 <= desc_reg12;
-- Drive ready if descriptor fetch request is being made
-- If not redirecting app fields then drive ready based on sm request
-- If redirecting app fields then drive ready based on room in cntrl strm fifo
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
redirect_app <= '0';
cntrlstrm_fifo_din <= (others => '0');
cntrlstrm_fifo_wren <= '0';
end generate GEN_FTCHIF_WITH_APP;
-- Status/Control stream diabled therefore APP fields are NOT included
GEN_FTCHIF_WITHOUT_APP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7(DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
ADDR1_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR1_64BIT;
ADDR1_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR1_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- desc 4 and desc 5 are reserved and thus don't care
-- CR 583779, need to send the user and xchache info
mm2s_desc_info <= (others => '0'); --desc_reg4;
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_mm2s_ftch_tdata_mcdma_new (31 downto 0); --63 downto 32);
desc_reg5 <= m_axis_mm2s_ftch_tdata_mcdma_new (63 downto 32);
ADDR2_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_desc_curdesc_msb <= m_axis_mm2s_ftch_tdata_new (128 downto 97);
mm2s_desc_baddr_msb <= m_axis_mm2s_ftch_tdata_new (160 downto 129);
end generate ADDR2_64BIT;
ADDR2_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_desc_curdesc_msb <= (others => '0');
mm2s_desc_baddr_msb <= (others => '0');
end generate ADDR2_32BIT;
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_baddr_lsb <= desc_reg2;
-- As per new MCDMA descriptor
mm2s_desc_info <= desc_reg4; -- (31 downto 24) & desc_reg7 (23 downto 0);
mm2s_desc_blength_s_i <= "0000000" & desc_reg5(15 downto 0);
mm2s_desc_blength_v_i <= "0000000000" & desc_reg5(31 downto 19);
mm2s_desc_blength_i <= "0000000" & desc_reg6(15 downto 0);
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= '0' ; --desc_reg7(DESC_STS_CMPLTD_BIT); -- we are not considering the completed bit
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_MCDMA;
-- Drive ready if descriptor fetch request is being made
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
end generate GEN_FTCHIF_WITHOUT_APP;
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_msb & mm2s_desc_baddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_msb & mm2s_desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
mm2s_new_curdesc_wren_i <= desc_fetch_done_i;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= mm2s_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
UPDT_ADDR_64BIT : if C_M_AXI_MM2S_ADDR_WIDTH > 32 generate
begin
UPDT_DESC_WRD0_1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= mm2s_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD0_1;
end generate UPDT_ADDR_64BIT;
-----------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg1 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg1 <= DESC_LAST
& mm2s_desc_curdesc_msb;
-- Shift data out on shift enable
elsif(updt_shftenbl = '1')then
updt_desc_reg1 <= (others => '0');
end if;
end if;
end process UPDT_DESC_WRD1;
-- Shift in data from SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_mm2s_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1'
and s_axis_mm2s_updtptr_tready = '1'
else '0';
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
--*****************************************************************************
--** Status Update Logic
--*****************************************************************************
mm2s_complete <= '1'; -- Fixed at '1'
---------------------------------------------------------------------------
-- Descriptor queuing turned on in sg engine therefore need to instantiate
-- fifo to hold fetch buffer lengths. Also need to throttle fetches
-- if pointer has not been updated yet or length fifo is full
---------------------------------------------------------------------------
GEN_UPDT_FOR_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic; -- xfer'ed bytes fifo reset
signal xb_fifo_full : std_logic; -- xfer'ed bytes fifo full
begin
-----------------------------------------------------------------------
-- Need to flag a pending pointer update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
mm2s_pending_ptr_updt <= '0';
elsif (desc_fetch_done_i = '1') then --(mm2s_new_curdesc_wren_i = '1')then
mm2s_pending_ptr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pointer pending update or xferred bytes fifo full
mm2s_pending_update <= mm2s_pending_ptr_updt or xb_fifo_full;
updt_pending <= mm2s_pending_update;
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
mm2s_xferd_bytes <= (others => '0');
xb_fifo_full <= '0';
end generate GEN_MICRO_DMA;
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => desc_fetch_done_i, --mm2s_new_curdesc_wren_i ,
Data_In => mm2s_desc_blength_i ,
FIFO_Read => sts_received_re ,
Data_Out => mm2s_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
end generate GEN_NO_MICRO_DMA;
xb_fifo_reset <= not m_axi_sg_aresetn;
-- clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
mm2s_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= mm2s_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= mm2s_sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_QUEUE;
---------------------------------------------------------------------------
-- If no queue in sg engine then do not need to instantiate a
-- fifo to hold buffer lengths. Also do not need to hold off
-- fetch based on if status has been updated or not because
-- descriptors are only processed one at a time
---------------------------------------------------------------------------
GEN_UPDT_FOR_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
mm2s_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
mm2s_pending_update <= '0'; -- Not needed for the No Queue configuration
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_xferd_bytes <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
mm2s_xferd_bytes <= mm2s_desc_blength_i;
end if;
end if;
end process REG_XFERRED_BYTES;
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= mm2s_done or mm2s_interr or mm2s_decerr or mm2s_slverr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_NO_QUEUE;
-----------------------------------------------------------------------
-- Receive Status SG Update Logic
-----------------------------------------------------------------------
-- clear flag when updating status and see a tlast and target
-- (i.e. sg engine) is ready
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tlast = '1'
and updtsts_tvalid = '1'
and s_axis_mm2s_updtsts_tready = '1'
else '0';
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done
-- or datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- -- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg2 <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_reg2 <= DESC_LAST
& mm2s_tag(DATAMOVER_STS_TAGLSB_BIT) -- Desc_IOC
& mm2s_complete
& mm2s_decerr
& mm2s_slverr
& mm2s_interr
& RESERVED_STS
& mm2s_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
updtsts_tdata <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- MSB asserts last on last word of update stream
updtsts_tlast <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive tvalid
updtsts_tvalid <= updt_sts;
-- Drive update done to mm2s sm for the no queue case to indicate
-- readyd to fetch next descriptor
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
-- Update Pointer Stream
s_axis_mm2s_updtptr_tvalid <= updtptr_tvalid;
s_axis_mm2s_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_mm2s_updtptr_tdata <= updtptr_tdata ;
-- Update Status Stream
s_axis_mm2s_updtsts_tvalid <= updtsts_tvalid;
s_axis_mm2s_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
s_axis_mm2s_updtsts_tdata <= updtsts_tdata ;
-----------------------------------------------------------------------
end implementation;
|
gpl-3.0
|
6f42c8f7e25953fb2007a8ef8ce76c10
| 0.468141 | 4.027409 | false | false | false | false |
cdsteinkuehler/AXI_Reg
|
AXI_Reg_Wr.vhd
| 1 | 12,731 |
-- Copyright (C) 2015, Charles Steinkuehler
-- <charles AT steinkuehler DOT net>
-- All rights reserved
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of the copyright holder nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Reg_Pkg.all;
library lpm;
use lpm.lpm_components.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity AXI_Reg_Wr_E is
port (
clk : in std_logic;
rst : in std_logic;
-- Write Address Channel
axi_awid : in std_logic_vector(13 downto 0); -- axs_s1_awid
axi_awaddr : in std_logic_vector(13 downto 0); -- axs_s1_awaddr
axi_awlen : in std_logic_vector(7 downto 0); -- axs_s1_awlen
axi_awsize : in std_logic_vector(2 downto 0); -- axs_s1_awsize
axi_awburst : in std_logic_vector(1 downto 0); -- axs_s1_awburst
--axi_awlock : in std_logic_vector(1 downto 0);
--axi_awcache : in std_logic_vector(3 downto 0);
--axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic; -- axs_s1_awvalid
axi_awready : out std_logic := 'X'; -- axs_s1_awready
-- Write Data Channel
axi_wdata : in std_logic_vector(31 downto 0); -- axs_s1_wdata
axi_wstrb : in std_logic_vector(3 downto 0); -- axs_s1_wstrb
--axi_wlast : in std_logic;
axi_wvalid : in std_logic; -- axs_s1_wvalid
axi_wready : out std_logic := 'X'; -- axs_s1_wready
-- Write Response Channel
axi_bid : out std_logic_vector(13 downto 0) := (others => 'X'); -- axs_s1_bid
--axi_bresp : out std_logic_vector(1 downto 0);
axi_bvalid : out std_logic := 'X'; -- axs_s1_bvalid
axi_bready : in std_logic; -- axs_s1_bready
-- Register write interface
-- 2 banks of 256 register
-- 1 FIFO style burst write port
Bank1RegWr : out RegWrA_T;
Bank2RegWr : out RegWrA_T;
FIFORegWr : out FIFORegWrA_T );
end AXI_Reg_Wr_E;
architecture arch of AXI_Reg_Wr_E is
signal txa_busy : std_logic;
signal txd_busy : std_logic;
signal tx_done : std_logic;
signal tx_id : std_logic_vector(13 downto 0);
signal tx_addr : unsigned(13 downto 0);
signal tx_addr_nxt : unsigned(13 downto 0);
signal addr_inc : unsigned(13 downto 0);
signal addr_wrap : unsigned(13 downto 0);
signal addr_mask : unsigned(13 downto 0);
signal addr_align : unsigned(13 downto 0);
signal tx_len : unsigned(7 downto 0);
signal tx_size : std_logic_vector(2 downto 0);
signal tx_burst : std_logic_vector(1 downto 0);
signal num_bytes : unsigned(3 downto 0);
signal wr_addr : unsigned(13 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal wr_be : std_logic_vector(3 downto 0);
signal wr_ena : std_logic;
signal reg_addr : std_logic_vector(7 downto 0);
signal reg_data : std_logic_vector(63 downto 0);
signal reg_be : std_logic_vector(7 downto 0);
signal reg_wren : std_logic;
signal reg_we_ena : std_logic;
signal reg_we : std_logic_vector(511 downto 0);
signal dma_sel : std_logic;
signal reg_sel : std_logic;
signal fifo_sel : std_logic;
begin
axi_awready <= '1' when txa_busy='0' else '0';
axi_wready <= '1' when txd_busy='1' else '0';
axi_bid <= tx_id;
axi_bvalid <= tx_done;
with tx_burst select
tx_addr_nxt <= tx_addr when b"00", -- Fixed-address burst
addr_inc when b"01", -- Normal sequential memory
addr_wrap when b"10", -- Cache line burst
tx_addr when others; -- Reserved
with tx_size select
num_bytes <= x"1" when b"000",
x"2" when b"001",
x"4" when b"010",
x"4" when others;
with tx_size select
addr_mask <= ( others=>'1') when b"000",
(0 downto 0 => '0', others=>'1') when b"001",
(1 downto 0 => '0', others=>'1') when b"010",
(1 downto 0 => '0', others=>'1') when others;
addr_align <= tx_addr and addr_mask;
addr_inc <= addr_align + num_bytes;
--FIXME: AXI burst wrapping is complex...ignore for now.
addr_wrap <= addr_inc;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
txa_busy <= '0';
txd_busy <= '0';
tx_done <= '0';
tx_id <= (others=>'0');
tx_addr <= (others=>'0');
tx_len <= (others=>'0');
tx_size <= (others=>'0');
tx_burst <= (others=>'0');
wr_addr <= (others=>'0');
wr_data <= (others=>'0');
wr_be <= (others=>'0');
else
-- Start of write transaction
if axi_awvalid='1' and txa_busy='0' then
txd_busy <= '1';
tx_id <= axi_awid;
tx_addr <= unsigned(axi_awaddr);
tx_len <= unsigned(axi_awlen);
tx_size <= axi_awsize;
tx_burst <= axi_awburst;
-- Last data transfer
elsif txd_busy='1' and axi_wvalid='1' and tx_len=0 then
txd_busy <= '0';
-- Generic data transfer
elsif txd_busy='1' and axi_wvalid='1' then
tx_addr <= tx_addr_nxt;
tx_len <= tx_len - 1;
end if;
-- Data phase transfers
if txd_busy='1' and axi_wvalid='1' then
wr_addr <= tx_addr;
wr_data <= axi_wdata;
wr_be <= axi_wstrb;
wr_ena <= '1';
else
wr_ena <= '0';
end if;
-- Start of write transaction
if axi_awvalid='1' and txa_busy='0' then
txa_busy <= '1';
-- End of data phase, send write response
elsif txd_busy='1' and axi_wvalid='1' and tx_len=0 then
txa_busy <= '0';
tx_done <= '1';
--axi_bresp <= b00=OK, b01=EXOK, b10=Slave Error, b11=Decode Error
-- Write response accepted, we're done here
elsif tx_done='1' and axi_bready='1' then
txa_busy <= '0';
tx_done <= '0';
end if;
end if;
end if;
end process;
-- Register generation of actual register write signals
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
reg_addr <= (others=>'0');
reg_data <= (others=>'0');
reg_be <= (others=>'0');
reg_wren <= '0';
dma_sel <= '0';
reg_sel <= '0';
fifo_sel <= '0';
else
-- Convert byte write address to 64-bit QWORD address
reg_addr <= std_logic_vector(resize(wr_addr(wr_addr'left downto 3),reg_addr'length));
reg_data <= wr_data & wr_data;
if wr_addr(2)='0' then
reg_be(3 downto 0) <= wr_be;
reg_be(7 downto 4) <= (others=>'0');
else
reg_be(3 downto 0) <= (others=>'0');
reg_be(7 downto 4) <= wr_be;
end if;
reg_wren <= wr_ena;
if wr_addr(12)='0' then
if wr_addr(11)='0' then
dma_sel <= '1';
reg_sel <= '0';
fifo_sel <= '0';
else
dma_sel <= '0';
reg_sel <= '1';
fifo_sel <= '0';
end if;
else
dma_sel <= '0';
reg_sel <= '0';
fifo_sel <= '1';
end if;
end if;
end if;
end process;
Bank1RegWr.addr <= reg_addr;
Bank1RegWr.data <= reg_data;
Bank1RegWr.be <= reg_be;
Bank1RegWr.we <= reg_we(255 downto 0);
Bank1RegWr.wren <= reg_wren;
Bank1RegWr.sel <= dma_sel;
Bank2RegWr.addr <= reg_addr;
Bank2RegWr.data <= reg_data;
Bank2RegWr.be <= reg_be;
Bank2RegWr.we <= reg_we(511 downto 256);
Bank2RegWr.wren <= reg_wren;
Bank2RegWr.sel <= reg_sel;
FIFORegWr.addr <= reg_addr(1 downto 0);
FIFORegWr.data <= reg_data;
FIFORegWr.be <= reg_be;
FIFORegWr.wren <= reg_wren;
FIFORegWr.sel <= fifo_sel;
reg_we_ena <= '1' when wr_ena='1' and wr_addr(12)='0' else '0';
reg_we_decode : lpm_decode
generic map (
LPM_PIPELINE => 1,
LPM_WIDTH => 9,
LPM_DECODES => 512)
port map(
clock => clk,
data => std_logic_vector(wr_addr(11 downto 3)),
enable => reg_we_ena,
eq => reg_we);
end arch;
|
bsd-3-clause
|
cd44c14817237e67a119b35e86fce106
| 0.49729 | 3.948821 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug035/arith_prng.vhdl
| 4 | 11,682 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Module: Pseudo-Random Number Generator (PRNG).
--
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- The number sequence includes the value all-zeros, but not all-ones.
-- Synchronized Reset is used.
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library PoC;
use PoC.utils.all;
entity arith_prng is
generic (
BITS : positive;
SEED : std_logic_vector := "0"
);
port (
clk : in std_logic;
rst : in std_logic; -- reset value to initial seed
got : in std_logic; -- the current value has been got, and a new value should be calculated
val : out std_logic_vector(BITS - 1 downto 0) -- the pseudo-random number
);
end arith_prng;
architecture rtl of arith_prng is
subtype T_TAPPOSITION is T_NATVEC(0 TO 4);
type T_TAPPOSITION_VECTOR is array (natural range <>) of T_TAPPOSITION;
-- Tap positions are taken from Xilinx Application Note 052 (XAPP052)
constant C_TAPPOSITION_LIST : T_TAPPOSITION_VECTOR(3 to 168) := (
3 => (0 => 2, others => 0),
4 => (0 => 3, others => 0),
5 => (0 => 3, others => 0),
6 => (0 => 5, others => 0),
7 => (0 => 6, others => 0),
8 => (0 => 6, 1 => 5, 2 => 4, others => 0),
9 => (0 => 5, others => 0),
10 => (0 => 7, others => 0),
11 => (0 => 9, others => 0),
12 => (0 => 6, 1 => 4, 2 => 1, others => 0),
13 => (0 => 4, 1 => 3, 2 => 1, others => 0),
14 => (0 => 5, 1 => 3, 2 => 1, others => 0),
15 => (0 => 14, others => 0),
16 => (0 => 15, 1 => 13, 2 => 4, others => 0),
17 => (0 => 14, others => 0),
18 => (0 => 11, others => 0),
19 => (0 => 6, 1 => 2, 2 => 1, others => 0),
20 => (0 => 17, others => 0),
21 => (0 => 19, others => 0),
22 => (0 => 21, others => 0),
23 => (0 => 18, others => 0),
24 => (0 => 23, 1 => 22, 2 => 17, others => 0),
25 => (0 => 22, others => 0),
26 => (0 => 6, 1 => 2, 2 => 1, others => 0),
27 => (0 => 5, 1 => 2, 2 => 1, others => 0),
28 => (0 => 25, others => 0),
29 => (0 => 27, others => 0),
30 => (0 => 6, 1 => 4, 2 => 1, others => 0),
31 => (0 => 28, others => 0),
32 => (0 => 22, 1 => 2, 2 => 1, others => 0),
33 => (0 => 2, others => 0),
34 => (0 => 27, 1 => 2, 2 => 1, others => 0),
35 => (0 => 33, others => 0),
36 => (0 => 25, others => 0),
37 => (0 => 5, 1 => 4, 2 => 3, 3 => 2, 4 => 1),
38 => (0 => 6, 1 => 5, 2 => 1, others => 0),
39 => (0 => 35, others => 0),
40 => (0 => 38, 1 => 21, 2 => 19, others => 0),
41 => (0 => 38, others => 0),
42 => (0 => 41, 1 => 20, 2 => 19, others => 0),
43 => (0 => 42, 1 => 38, 2 => 37, others => 0),
44 => (0 => 43, 1 => 18, 2 => 17, others => 0),
45 => (0 => 44, 1 => 42, 2 => 41, others => 0),
46 => (0 => 45, 1 => 26, 2 => 25, others => 0),
47 => (0 => 42, others => 0),
48 => (0 => 47, 1 => 21, 2 => 20, others => 0),
49 => (0 => 4, others => 0),
50 => (0 => 49, 1 => 24, 2 => 23, others => 0),
51 => (0 => 50, 1 => 36, 2 => 35, others => 0),
52 => (0 => 49, others => 0),
53 => (0 => 52, 1 => 38, 2 => 37, others => 0),
54 => (0 => 53, 1 => 18, 2 => 17, others => 0),
55 => (0 => 31, others => 0),
56 => (0 => 55, 1 => 35, 2 => 34, others => 0),
57 => (0 => 5, others => 0),
58 => (0 => 39, others => 0),
59 => (0 => 58, 1 => 38, 2 => 37, others => 0),
60 => (0 => 59, others => 0),
61 => (0 => 60, 1 => 46, 2 => 45, others => 0),
62 => (0 => 61, 1 => 6, 2 => 5, others => 0),
63 => (0 => 62, others => 0),
64 => (0 => 63, 1 => 61, 2 => 60, others => 0),
65 => (0 => 47, others => 0),
66 => (0 => 65, 1 => 57, 2 => 56, others => 0),
67 => (0 => 66, 1 => 58, 2 => 57, others => 0),
68 => (0 => 59, others => 0),
69 => (0 => 67, 1 => 42, 2 => 40, others => 0),
70 => (0 => 69, 1 => 55, 2 => 54, others => 0),
71 => (0 => 65, others => 0),
72 => (0 => 66, 1 => 25, 2 => 19, others => 0),
73 => (0 => 48, others => 0),
74 => (0 => 73, 1 => 59, 2 => 58, others => 0),
75 => (0 => 74, 1 => 65, 2 => 64, others => 0),
76 => (0 => 75, 1 => 41, 2 => 40, others => 0),
77 => (0 => 76, 1 => 47, 2 => 46, others => 0),
78 => (0 => 77, 1 => 59, 2 => 58, others => 0),
79 => (0 => 7, others => 0),
80 => (0 => 79, 1 => 43, 2 => 42, others => 0),
81 => (0 => 77, others => 0),
82 => (0 => 79, 1 => 47, 2 => 44, others => 0),
83 => (0 => 82, 1 => 38, 2 => 37, others => 0),
84 => (0 => 71, others => 0),
85 => (0 => 84, 1 => 58, 2 => 57, others => 0),
86 => (0 => 85, 1 => 74, 2 => 73, others => 0),
87 => (0 => 74, others => 0),
88 => (0 => 87, 1 => 17, 2 => 16, others => 0),
89 => (0 => 51, others => 0),
90 => (0 => 89, 1 => 72, 2 => 71, others => 0),
91 => (0 => 90, 1 => 8, 2 => 7, others => 0),
92 => (0 => 91, 1 => 80, 2 => 79, others => 0),
93 => (0 => 91, others => 0),
94 => (0 => 73, others => 0),
95 => (0 => 84, others => 0),
96 => (0 => 94, 1 => 49, 2 => 47, others => 0),
97 => (0 => 91, others => 0),
98 => (0 => 87, others => 0),
99 => (0 => 97, 1 => 54, 2 => 52, others => 0),
100 => (0 => 63, others => 0),
101 => (0 => 100, 1 => 95, 2 => 94, others => 0),
102 => (0 => 101, 1 => 36, 2 => 35, others => 0),
103 => (0 => 94, others => 0),
104 => (0 => 103, 1 => 94, 2 => 93, others => 0),
105 => (0 => 89, others => 0),
106 => (0 => 91, others => 0),
107 => (0 => 105, 1 => 44, 2 => 42, others => 0),
108 => (0 => 77, others => 0),
109 => (0 => 108, 1 => 103, 2 => 102, others => 0),
110 => (0 => 109, 1 => 98, 2 => 97, others => 0),
111 => (0 => 101, others => 0),
112 => (0 => 110, 1 => 69, 2 => 67, others => 0),
113 => (0 => 104, others => 0),
114 => (0 => 113, 1 => 33, 2 => 32, others => 0),
115 => (0 => 114, 1 => 101, 2 => 100, others => 0),
116 => (0 => 115, 1 => 46, 2 => 45, others => 0),
117 => (0 => 115, 1 => 99, 2 => 97, others => 0),
118 => (0 => 85, others => 0),
119 => (0 => 111, others => 0),
120 => (0 => 113, 1 => 9, 2 => 2, others => 0),
121 => (0 => 103, others => 0),
122 => (0 => 121, 1 => 63, 2 => 62, others => 0),
123 => (0 => 121, others => 0),
124 => (0 => 87, others => 0),
125 => (0 => 124, 1 => 18, 2 => 17, others => 0),
126 => (0 => 125, 1 => 90, 2 => 89, others => 0),
127 => (0 => 126, others => 0),
128 => (0 => 126, 1 => 101, 2 => 99, others => 0),
129 => (0 => 124, others => 0),
130 => (0 => 127, others => 0),
131 => (0 => 130, 1 => 84, 2 => 83, others => 0),
132 => (0 => 103, others => 0),
133 => (0 => 132, 1 => 82, 2 => 81, others => 0),
134 => (0 => 77, others => 0),
135 => (0 => 124, others => 0),
136 => (0 => 135, 1 => 11, 2 => 10, others => 0),
137 => (0 => 116, others => 0),
138 => (0 => 137, 1 => 131, 2 => 130, others => 0),
139 => (0 => 136, 1 => 134, 2 => 131, others => 0),
140 => (0 => 111, others => 0),
141 => (0 => 140, 1 => 110, 2 => 109, others => 0),
142 => (0 => 121, others => 0),
143 => (0 => 142, 1 => 123, 2 => 122, others => 0),
144 => (0 => 143, 1 => 75, 2 => 74, others => 0),
145 => (0 => 93, others => 0),
146 => (0 => 145, 1 => 87, 2 => 86, others => 0),
147 => (0 => 146, 1 => 110, 2 => 109, others => 0),
148 => (0 => 121, others => 0),
149 => (0 => 148, 1 => 40, 2 => 39, others => 0),
150 => (0 => 97, others => 0),
151 => (0 => 148, others => 0),
152 => (0 => 151, 1 => 87, 2 => 86, others => 0),
153 => (0 => 152, others => 0),
154 => (0 => 152, 1 => 27, 2 => 25, others => 0),
155 => (0 => 154, 1 => 124, 2 => 123, others => 0),
156 => (0 => 155, 1 => 41, 2 => 40, others => 0),
157 => (0 => 156, 1 => 131, 2 => 130, others => 0),
158 => (0 => 157, 1 => 132, 2 => 131, others => 0),
159 => (0 => 128, others => 0),
160 => (0 => 159, 1 => 142, 2 => 141, others => 0),
161 => (0 => 143, others => 0),
162 => (0 => 161, 1 => 75, 2 => 74, others => 0),
163 => (0 => 162, 1 => 104, 2 => 103, others => 0),
164 => (0 => 163, 1 => 151, 2 => 150, others => 0),
165 => (0 => 164, 1 => 135, 2 => 134, others => 0),
166 => (0 => 165, 1 => 128, 2 => 127, others => 0),
167 => (0 => 161, others => 0),
168 => (0 => 166, 1 => 153, 2 => 151, others => 0)
);
constant C_TAPPOSITIONS : T_TAPPOSITION := C_TAPPOSITION_LIST(BITS);
-- The current value
signal bit1_nxt : std_logic;
signal val_r : std_logic_vector(BITS downto 1) := resize(SEED, BITS);
begin -- rtl
assert ((3 <= BITS) and (BITS <= 168)) report "Width not yet supported." severity failure;
-----------------------------------------------------------------------------
-- Datapath
-----------------------------------------------------------------------------
-- XNOR used so that all-zero is valid and all-one is forbidden.
process(val_r)
variable temp : std_logic;
begin
temp := val_r(val_r'left);
for i in 0 to 4 loop
if (C_TAPPOSITIONS(i) > 0) then
temp := temp xnor val_r(C_TAPPOSITIONS(i));
end if;
end loop;
bit1_nxt <= temp;
end process;
-----------------------------------------------------------------------------
-- Register
-----------------------------------------------------------------------------
process (clk)
begin -- process
if rising_edge(clk) then
if rst = '1' then
val_r <= resize(SEED, BITS);
elsif got = '1' then
val_r <= val_r(val_r'left - 1 downto 1) & bit1_nxt;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
val <= val_r;
end rtl;
|
gpl-2.0
|
92de79dca10afab5d055c33014e1fc05
| 0.388033 | 2.633454 | false | false | false | false |
mistryalok/FPGA
|
Xilinx/ISE/Basics/JK_flipflop/T_flipflop.vhd
| 1 | 1,194 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:50:36 05/02/2013
-- Design Name:
-- Module Name: T_flipflop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity T_flipflop is
Port (clk : in std_logic;
T : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end T_flipflop;
architecture Behavioral of T_flipflop is
begin
process(T,clk)
variable temp : std_logic;
begin
temp = Q;
Q <= '0';
Qn <= '0';
case T is
when '1' => Q <= not temp;
when others => null;
end case;
temp := not Q;
Qn <= temp;
end process;
end Behavioral;
|
gpl-3.0
|
c4a6863759fd47438dd77c2124225f50
| 0.529313 | 3.57485 | false | false | false | false |
nickg/nvc
|
test/sem/genpack.vhd
| 1 | 3,553 |
package myfixed is
generic ( whole : natural; frac : natural ); -- OK
constant width : natural := whole + frac; -- OK
type fixed_t is array (1 to width) of bit; -- OK
function "+"(x, y : fixed_t) return fixed_t; -- OK
end package;
package body myfixed is
function "+"(x, y : fixed_t) return fixed_t is
variable result : fixed_t;
begin
for i in 1 to width loop
result(i) := x(i) or y(i);
end loop;
return result;
end function;
end package body;
-------------------------------------------------------------------------------
package my_consts is
constant x : integer := 5;
constant y : integer := 6;
end package;
-------------------------------------------------------------------------------
use work.my_consts.all;
package myfixed_4_8 is new work.myfixed generic map ( x, y ); -- OK
-------------------------------------------------------------------------------
entity ent is
end entity;
architecture test of ent is
package myfixed_2_4 is new work.myfixed generic map (2, 4); -- OK
package bad1 is new work.ent generic map (2, 4); -- Error
package bad2 is new std.standard generic map (2, 4); -- Error
package bad3 is new work.not_here generic map (2, 4); -- Error
package bad4 is new work.myfixed generic map (2); -- Error
constant c : natural := myfixed_2_4.width; -- OK
constant d : myfixed_2_4.fixed_t := (others => '0'); -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package myfloat is
generic ( package fixed_pkg is new work.myfixed generic map (<>) ); -- OK
use fixed_pkg.width; -- OK
end package;
package body myfloat is
use fixed_pkg.all; -- OK
constant k : natural := whole; -- OK
function add(a, b : fixed_t) return fixed_t is
begin
return a + b; -- OK
end function;
end package body;
-------------------------------------------------------------------------------
package bad is
generic ( package bad_std is new std.standard generic map (<>) ); -- Error
end package;
-------------------------------------------------------------------------------
package my_poly1 is new work.myfloat generic map ( fixed_pkg => not_here); -- Error
-------------------------------------------------------------------------------
architecture test2 of ent is
package p1 is new work.myfloat
generic map ( fixed_pkg => work.myfixed_4_8 ); -- OK
package p2 is new work.myfloat
generic map ( fixed_pkg => p1 ); -- Error
package p3 is new work.myfloat
generic map ( fixed_pkg => std.standard ); -- Error
package p4 is new work.bad
generic map ( bad_std => work.myfixed_4_8 ); -- Error
begin
end architecture;
-------------------------------------------------------------------------------
package ptr_pkg is
generic ( type t );
type ptr is access t;
end package;
-------------------------------------------------------------------------------
package int_ptr_pkg is new work.ptr_pkg
generic map ( t => integer );
-------------------------------------------------------------------------------
use work.int_ptr_pkg;
architecture test3 of ent is
procedure p is
variable v : int_ptr_pkg.ptr;
begin
v := new integer; -- OK
int_ptr_pkg.deallocate(v); -- OK
end procedure;
begin
end architecture;
|
gpl-3.0
|
8459528f9f55f497cc3db972c667db06
| 0.462426 | 4.419154 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff02/dff08b.vhdl
| 1 | 530 |
library ieee;
use ieee.std_logic_1164.all;
entity dff08b is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic;
en : std_logic;
rst : std_logic);
end dff08b;
architecture behav of dff08b is
signal p : std_logic_vector(7 downto 0) := x"aa";
begin
process (clk, rst) is
begin
if en = '0' then
null;
elsif rst = '1' then
p <= x"00";
elsif rising_edge (clk) then
p <= d;
end if;
end process;
q <= p;
end behav;
|
gpl-2.0
|
f212f6383c7f331676064d0bea3de0b7
| 0.573585 | 3.011364 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd
| 4 | 2,662 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1717.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p13n01i01717ent IS
END c09s02b00x00p13n01i01717ent;
ARCHITECTURE c09s02b00x00p13n01i01717arch OF c09s02b00x00p13n01i01717ent IS
-- Local signals.
signal A, B : BIT := '0';
BEGIN
TESTING: PROCESS
-- Local variables.
variable STARTED: BOOLEAN := FALSE;
variable OldTime: TIME := 250 ns;
variable OldInt : INTEGER := 13;
variable OldA,
OldB : BIT;
variable I : INTEGER;
BEGIN
-- Initialize variables for this first pass.
if (NOT(STARTED)) then
OldTime := NOW;
OldInt := 47;
OldA := A;
OldB := B;
I := 0;
STARTED := TRUE;
elsif (I > 15) then
assert NOT(I = 16)
report "***PASSED TEST: c09s02b00x00p13n01i01717"
severity NOTE;
assert (I = 16)
report "***FAILED TEST: c09s02b00x00p13n01i01717 - The execution of a process statement consists of the repetitive execution of its sequence of statements."
severity ERROR;
wait;
end if;
-- Verify that no variables, time or signals have changed.
assert( OldInt = 47 ) severity ERROR;
assert( OldTime = NOW ) severity ERROR;
assert( OldA = A ) severity ERROR;
assert( OldB = B ) severity ERROR;
I := I + 1;
END PROCESS TESTING;
-- This process merely makes assignments to the signals A and B.
ASSIGN_PROCESS: process
begin
A <= '1' ;
B <= '1';
wait;
end process;
END c09s02b00x00p13n01i01717arch;
|
gpl-2.0
|
a338b0654c3107061f185220b9598bd2
| 0.629977 | 3.770538 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
| 4 | 1,602 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
|
gpl-2.0
|
b9e79f5c48a96f7c59927f179c250995
| 0.644195 | 3.985075 | false | false | false | false |
nickg/nvc
|
test/regress/issue415.vhd
| 1 | 2,126 |
library ieee;
use ieee.std_logic_1164.all;
entity bug5 is
port(
clk : in std_logic;
addr : std_logic_vector
);
end bug5;
architecture behavioral of bug5 is
-- This complains with stack trace:
-- Fatal: signal cannot have unconstrained array type
signal last_addr_s : std_logic_vector(addr'range);
-- This is fine
-- signal last_addr : std_logic_vector(addr'high downto addr'low);
begin
process(clk)
-- This causes SIGABRT
variable last_addr : std_logic_vector(addr'range);
-- This is fine
-- variable last_addr : std_logic_vector(addr'high downto addr'low);
type int_arr is array (integer range <>) of integer;
type chunk_item is record
memory : boolean;
data : int_arr(0 to 1);
end record;
constant chunk_empty : chunk_item := (false, (others => -1));
type mem_arr is array (integer range <>) of chunk_item;
-- The line below complains with stack trace:
-- Fatal: attempt to add to already finished block 0
variable mem2 : mem_arr(0 to 1) := (others => chunk_empty);
-- This is fine (including with the assigment below)
-- variable mem2 : mem_arr(0 to 1);
begin
if rising_edge(clk) then
if addr = (addr'range => '0') then
mem2 := (others => chunk_empty);
end if;
last_addr_s <= addr;
end if;
end process;
check: process is
begin
wait for 5 ns;
assert last_addr_s = X"00000000000001";
wait;
end process;
end behavioral;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue415 is
end issue415;
architecture behavioral of issue415 is
signal clk : std_logic := '0';
signal addr : std_logic_vector(55 downto 0);
begin
bug2_i: entity work.bug5
port map (
clk => clk,
addr => addr
);
stim: process is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
addr <= X"00000000000001";
wait for 1 ns;
clk <= '1';
wait for 1 ns;
wait;
end process;
end behavioral;
|
gpl-3.0
|
0454045384555152d9c39b1d6e8556b7
| 0.599247 | 3.579125 | false | false | false | false |
nickg/nvc
|
test/regress/bounds32.vhd
| 1 | 574 |
entity bounds32 is
end entity;
architecture test of bounds32 is
type rec is record
x : bit_vector;
end record;
signal s : rec(x(1 to 3));
signal n : integer := 4;
signal v : bit_vector(1 to 10) := (others => '1');
begin
main: process is
begin
assert s.x = "000";
assert s = (x => "000");
s.x <= "101";
wait for 1 ns;
assert s.x = "101";
assert s = (x => "101");
s <= (x => v(1 to n)); -- Error
wait for 1 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
720171d021e506fec9519f6ce54e7013
| 0.484321 | 3.457831 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1273/tb_assert4.vhdl
| 1 | 1,020 |
entity tb_assert4 is
generic (with_err : boolean := False);
end tb_assert4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_assert4 is
signal v : std_logic_Vector (7 downto 0);
signal en : std_logic := '0';
signal clk : std_logic;
signal res : std_logic;
begin
dut: entity work.assert4
port map (v, en, clk, res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en <= '1';
v <= b"0010_0000";
pulse;
assert res = '0' severity failure;
v <= b"0010_0001";
pulse;
assert res = '1' severity failure;
v <= b"0010_0011";
pulse;
assert res = '0' severity failure;
v <= b"0010_0010";
pulse;
assert res = '1' severity failure;
en <= '0';
v <= x"00";
pulse;
assert res = '1' severity failure;
-- Trigger an error.
if with_err then
en <= '1';
pulse;
end if;
wait;
end process;
end behav;
|
gpl-2.0
|
1a5b56aee2c388159e7b847f123a7947
| 0.558824 | 3.290323 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd
| 4 | 1,525 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
gpl-2.0
|
789297a6064306012c5df06d3aedee80
| 0.584262 | 4.034392 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1264/repro.vhdl
| 1 | 490 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro is
port (r : out std_logic);
end repro;
architecture beh of repro is
begin
r <= '1';
assert (unsigned'(b"1001_0001") srl 1) = b"0100_1000";
assert (unsigned'(b"1001_0001") sll 1) = b"0010_0010";
assert (signed'(b"1001_0001") srl 1) = b"0100_1000";
assert (signed'(b"1001_0001") sll 1) = b"0010_0010";
-- assert false report to_bstring(signed'(b"1001_0001") srl 1);
end architecture beh;
|
gpl-2.0
|
61447a5ae3724dd017781a6c6403f94d
| 0.661224 | 2.882353 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1069/tdp_ram_single.vhdl
| 1 | 2,793 |
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 12;
WIDTH_A : positive := 8;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
byteen_a : in std_logic_vector(WIDTH_A/COL_WIDTH - 1 downto 0);
addr_a : in std_logic_vector(ADDRWIDTH_A - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH_A - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH_A - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
function log2(val : INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
function eq_assert(x : integer; y : integer) return integer is
begin
assert x = y;
return x;
end function eq_assert;
constant COLS_A : positive := WIDTH_A / COL_WIDTH;
constant COLS_B : positive := WIDTH_B / COL_WIDTH;
constant TOTAL_COLS : positive := eq_assert(COLS_A * 2 ** ADDRWIDTH_A, COLS_B * 2 ** ADDRWIDTH_B);
constant EXTRA_ADDR_BITS_A : positive := log2(COLS_A);
constant EXTRA_ADDR_BITS_B : positive := log2(COLS_B);
type ram_t is array(0 to TOTAL_COLS - 1) of std_logic_vector(COL_WIDTH - 1 downto 0);
shared variable store : ram_t := (others => (others => '0'));
signal reg_a : std_logic_vector(WIDTH_A - 1 downto 0);
begin
assert WIDTH_A mod COL_WIDTH = 0 and
WIDTH_B mod COL_WIDTH = 0 and
2 ** (ADDRWIDTH_A + EXTRA_ADDR_BITS_A) = TOTAL_COLS and
2 ** (ADDRWIDTH_B + EXTRA_ADDR_BITS_B) = TOTAL_COLS
report "Both WIDTH_A and WIDTH_B have to be a power-of-two multiple of COL_WIDTH"
severity failure;
process(clk_a)
begin
if rising_edge(clk_a) then
for i in 0 to COLS_A - 1 loop
if write_a = '1' and byteen_a(i) = '1' then
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A))) :=
data_write_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_a = '1' then
reg_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A)));
end if;
end loop;
data_read_a <= reg_a;
end if;
end process;
end behavioral;
|
gpl-2.0
|
9714e72402ec183915b6d064c0d8db9f
| 0.535983 | 3.478207 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd
| 4 | 2,437 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1070.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01070ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
SUBTYPE A6 IS A (1 TO 6);
SUBTYPE A8 IS A (1 TO 8);
FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (1,2,3,4,5,6);
ELSE
IF (a=3) THEN
RETURN (11,22,33,44,55,66);
ELSE
RETURN (111,222,333,444,555,666);
END IF;
END IF;
END;
END c06s04b00x00p03n01i01070ent;
ARCHITECTURE c06s04b00x00p03n01i01070arch OF c06s04b00x00p03n01i01070ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,3)(1);
q(2) := func1(0,3)(2);
q(3) := func1(3,0)(3);
q(4) := func1(0,3)(4);
q(5) := func1(3,3)(5);
q(6) := func1(3,0)(6);
q(7) := func1(3,3)(3);
q(8) := func1(0,3)(1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***PASSED TEST: c06s04b00x00p03n01i01070"
severity NOTE;
assert (q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***FAILED TEST: c06s04b00x00p03n01i01070 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01070arch;
|
gpl-2.0
|
50dc54cf784b4971e6de7bdb8794b33e
| 0.609766 | 3.050063 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue317/PoC/src/common/math.vhdl
| 2 | 3,169 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Math extension package.
--
-- Description:
-- -------------------------------------
-- This package provides additional math functions.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package math is
-- figurate numbers
function squareNumber(N : natural) return natural;
function cubicNumber(N : natural) return natural;
function triangularNumber(N : natural) return natural;
-- coefficients
-- binomial coefficient (N choose K)
function binomialCoefficient(N : positive; K : positive) return positive;
-- greatest common divisor (gcd)
function greatestCommonDivisor(N1 : positive; N2 : positive) return positive;
-- least common multiple (lcm)
function leastCommonMultiple(N1 : positive; N2 : positive) return positive;
end package;
package body math is
-- figurate numbers
function squareNumber(N : natural) return natural is
begin
return N*N;
end function;
function cubicNumber(N : natural) return natural is
begin
return N*N*N;
end function;
function triangularNumber(N : natural) return natural is
variable T : natural;
begin
return (N * (N + 1) / 2);
end function;
-- coefficients
function binomialCoefficient(N : positive; K : positive) return positive is
variable Result : positive;
begin
Result := 1;
for i in 1 to K loop
Result := Result * (((N + 1) - i) / i);
end loop;
return Result;
end function;
-- greatest common divisor (gcd)
function greatestCommonDivisor(N1 : positive; N2 : positive) return positive is
variable M1 : positive;
variable M2 : natural;
variable Remainer : natural;
begin
M1 := imax(N1, N2);
M2 := imin(N1, N2);
while M2 /= 0 loop
Remainer := M1 mod M2;
M1 := M2;
M2 := Remainer;
end loop;
return M1;
end function;
-- least common multiple (lcm)
function leastCommonMultiple(N1 : positive; N2 : positive) return positive is
begin
return ((N1 * N2) / greatestCommonDivisor(N1, N2));
end function;
end package body;
|
gpl-2.0
|
7c71a3ea11dc1a086a4325a49d448826
| 0.646576 | 3.667824 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/lsp27/mwe.vhdl
| 1 | 2,087 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
generic (
skip : integer := 10
);
port (
nreset : in std_logic;
clk : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic
);
end mwe;
architecture behav of mwe is
type shared_counter is protected
procedure reset;
procedure increment;
impure function value return integer;
impure function pulsed return boolean;
end protected shared_counter;
type shared_counter is protected body
variable cnt : integer range 0 to skip-1 := 0;
variable flag_pulse : boolean := false;
procedure reset is
begin
cnt := 0;
flag_pulse := false;
end reset;
procedure increment is
begin
if cnt < skip-1 then
cnt := cnt + 1;
else
cnt := 0;
flag_pulse := true;
report "Pulse detected";
end if;
end increment;
impure function value return integer is
begin
return cnt;
end function value;
impure function pulsed return boolean is
variable pulsed_state : boolean;
begin
pulsed_state := flag_pulse;
flag_pulse := false;
return pulsed_state;
end function pulsed;
end protected body shared_counter;
shared variable shrd_cnt : shared_counter;
begin
output:process(clk,nreset)
begin
if nreset /= '1' then
shrd_cnt.reset;
pulse_out <= '0';
elsif rising_edge(clk) then
pulse_out <= '0';
if shrd_cnt.pulsed then
pulse_out <= '1';
end if;
end if;
end process;
pulse_cnt_update:process(nreset,pulse_in)
begin
if nreset = '1' then
if pulse_in = '1' then
shrd_cnt.increment;
end if;
end if ;
end process;
end behav;
|
gpl-2.0
|
16c940e4c4847823974be15fc0a0fce3
| 0.523239 | 4.56674 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue44/loopfilter.vhdl
| 2 | 1,903 |
-- loopfilter.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity loopfilter is
port(clk, reset: in std_logic;
mult_error_op:in signed(38 downto 0);
f_desired: in unsigned(5 downto 0);
f_word_output: out unsigned(5 downto 0));
end loopfilter;
architecture loopfilter_arch of loopfilter is
signal beta_e, alpha_e: signed(45 downto 0);
constant alpha: signed(7 downto 0) := "01110011";
constant beta: signed(7 downto 0) := "00011010";
constant plus_one: signed(alpha_e'range) := ('0', others => '1');
component q_one_dot_fp_multiplier is
generic (a_word_size, b_word_size:integer);
port(a: in signed(a_word_size-1 downto 0);
b: in signed(b_word_size-1 downto 0);
mult_out: out signed(a_word_size + b_word_size -2 downto 0));
end component;
begin
M0: q_one_dot_fp_multiplier generic map(a_word_size => beta'length, b_word_size => mult_error_op'length)
port map(beta, mult_error_op,beta_e );
M1: q_one_dot_fp_multiplier generic map(a_word_size => alpha'length, b_word_size => mult_error_op'length)
port map(alpha, mult_error_op, alpha_e);
ADDERS : process(clk, reset)
variable freq_add_var : signed(beta_e'range);
variable n_total_var: signed(alpha_e'range);
variable temp: signed(n_total_var'range);
begin
if reset = '1' then
freq_add_var := (others => '0');
freq_add_var(42 downto 37) := signed(std_logic_vector(f_desired));
n_total_var := (others => '0');
elsif rising_edge(clk) then
freq_add_var := freq_add_var + beta_e;
n_total_var := freq_add_var + alpha_e;
end if;
if n_total_var(n_total_var'length -1) = '1' then
temp := plus_one + n_total_var;
else
temp := n_total_var;
end if;
f_word_output <= unsigned(temp(42 downto 37));
end process;
end loopfilter_arch;
|
gpl-2.0
|
644e96080559cbf8cef33c06560adc65
| 0.630583 | 3.074313 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd
| 4 | 3,323 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc639.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:14 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:28 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00639ent IS
END c03s04b01x00p01n01i00639ent;
ARCHITECTURE c03s04b01x00p01n01i00639arch OF c03s04b01x00p01n01i00639ent IS
type four_value is ('Z','0','1','X');
subtype binary is four_value range '0' to '1';
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_module is
record
enable : binary;
memory_number : primary_memory;
end record;
type primary_memory_module_file is file of primary_memory_module;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
constant C45 : primary_memory_module := ('1',C44);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : primary_memory_module_file open read_mode is "iofile.43";
variable v : primary_memory_module;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C45) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00639"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00639 - File reading operation (primary_memory_module file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00639arch;
|
gpl-2.0
|
74e2b14b6e66c01b608f47e5f792b937
| 0.554017 | 3.900235 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue465/e.vhdl
| 1 | 771 |
entity e is end entity;
architecture h of e is
type r1 is record a :integer; end record;
type r2 is record b :integer; end record;
type r3 is record a :r1 ; end record;
type r4 is record a :r2 ; end record;
function f(a :integer := 1) return r3 is begin return (a=>(a=>a)); end function;
function f(a :integer := 2) return r4 is begin return (a=>(b=>a)); end function;
constant c1 :integer := f.a.a;
constant c2 :integer := f.a.b;
constant c3 :integer := f(3).a.a;
constant c4 :integer := f(4).a.b;
begin
assert false report integer'image(c1) severity note;
assert false report integer'image(c2) severity note;
assert false report integer'image(c3) severity note;
assert false report integer'image(c4) severity note;
end architecture;
|
gpl-2.0
|
357605d566cf69a3f2ec283479a9e3c3
| 0.687419 | 3.225941 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd
| 3 | 50,564 |
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Write (S2MM) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. This module buffers write data and provides status and
-- control features such that the DataMover Write Master is only allowed
-- to post AXI WRite Requests if the associated write data needed to complete
-- the Write Data transfer is present in the Data FIFO. In addition, the Write
-- side logic is such that Write transfer requests can be pipelined to the
-- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data
-- transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_wr_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
-- C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- -- Indicates the max burst length being used by the external
-- -- AXI4 Master for each AXI4 transfer request.
-- C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- -- Indicates if the external Master is utilizing a DRE on
-- -- the stream input to this module.
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 16;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs -----------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
-------------------------------------------------------------------------
-- Slave Stream Input ------------------------------------------------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
sin2sf_error : In std_logic; --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. --
-----------------------------------------------------------------------------------
-- DataMover Write Side Address Pipelining Control Interface ----------------------
--
ok_to_post_wr_addr : Out Std_logic; --
-- Indicates that the internal FIFO has enough data --
-- physically present to supply one more max length --
-- burst transfer or a completion burst --
-- (tlast asserted) --
--
wr_addr_posted : In std_logic; --
-- Indication that a write address has been posted to AXI4 --
--
--
wr_xfer_cmplt : In Std_logic; --
-- Indicates that the Datamover has completed a Write Data --
-- transfer on the AXI4 --
--
--
wr_ld_nxt_len : in std_logic; --
-- Active high pulse indicating a new transfer LEN qualifier --
-- has been queued to the DataMover Write Data Controller --
--
wr_len : in std_logic_vector(7 downto 0); --
-- The actual LEN qualifier value that has been queued to the --
-- DataMover Write Data Controller --
-----------------------------------------------------------------------------------
-- Write Side Stream Out to DataMover S2MM ----------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic; --
-- Write LAST output to the Stream Master --
--
sf2sout_error : Out std_logic --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
);
end entity axi_datamover_wr_sf;
architecture implementation of axi_datamover_wr_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant EOP_ERR_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
-- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
--WSTB_WIDTH +
TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
-- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
-- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
-- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
signal sig_sf2sout_eop_err_out : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
sf2sout_error <= sig_sf2sout_eop_err_out ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_good_fifo_write <= sig_good_sin_strm_dbeat;
sig_strm_sin_ready <= not(sig_data_fifo_full);
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_error &
sin2sf_tlast &
-- sin2sf_tkeep &
sin2sf_tdata;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_err_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
-- Generate the stream ready
sig_strm_sin_ready <= not(lsig_packer_full) or
lsig_good_push2fifo ;
-- Format the FIFO input data
sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit
lsig_tlast_or &
lsig_combined_data ; -- LS Bits
-- Generate a write to the Data FIFO input
sig_push_data_fifo <= lsig_packer_full;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_sin_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sin_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_sin_strm_dbeat and
(sin2sf_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_sin_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice for the packer.
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= sin2sf_tdata;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1
sin2sf_error; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or
--lsig_partial_eop_err_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register outputs into a single
-- vector for input to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Input attachments
-- sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= sin2sf_error &
-- sin2sf_tlast &
-- sin2sf_tkeep &
-- sin2sf_tdata;
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
-- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
-- TSTRB_OUT_LSB_INDEX);
-- When this Store and Forward is enabled, the Write Data Controller ignores the
-- TKEEP input so this is not sent through the FIFO.
sig_sf2sout_tkeep <= (others => '1');
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ;
-- FIFO Rd/WR Controls
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
-- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
sig_incr_uncom_wrcnt <= sig_good_fifo_write;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
-- The LEN FIFO stores the xfer lengths needed for each queued
-- write transfer in the DataMover S2MM Write Data Controller.
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
|
gpl-3.0
|
59354cccb4b14a5b2cfcc94250a5a820
| 0.418697 | 4.994962 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dispout01/tb_rec03.vhdl
| 1 | 481 |
entity tb_rec03 is
end tb_rec03;
library ieee;
use ieee.std_logic_1164.all;
use work.rec03_pkg.all;
architecture behav of tb_rec03 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec03
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a => s0, b => '0') severity failure;
inp <= '0';
wait for 1 ns;
assert r = (a => s3, b => '1') severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
bd283fa1cd7bd9d21c5083dcb945a180
| 0.596674 | 2.95092 | false | false | false | false |
nickg/nvc
|
test/regress/case13.vhd
| 1 | 742 |
entity case13 is
end entity;
architecture test of case13 is
function get_bits (n : natural; b : bit) return bit_vector is
variable v : bit_vector(1 to n);
begin
v := (others => b);
return v;
end function;
signal n : natural := 3;
signal b : bit;
begin
p1: process (n, b) is
begin
case get_bits(n, b) is
when "111" => report "ones";
when "000" => report "zeros";
when others => assert false;
end case;
end process;
stim: process is
begin
b <= '1';
wait for 0 ns;
n <= 5;
wait for 1 ns;
assert false report "should not reach here!";
wait;
end process;
end architecture;
|
gpl-3.0
|
6ee637d2eee5e18d06d259d31f76a0f9
| 0.522911 | 3.84456 | false | false | false | false |
nickg/nvc
|
test/regress/alias14.vhd
| 1 | 908 |
entity alias14 is
end entity;
architecture test of alias14 is
type point is record
x, y : integer;
end record;
type point_vec is array (natural range <>) of point;
type sig_type is record
points : point_vec;
end record;
signal s1 : sig_type(points(1 to 4));
alias s1p1x is s1.points(1).x;
type nest_type is record
sub : sig_type;
end record;
signal s2 : nest_type(sub(points(1 to 2)));
alias s2p is s2.sub.points;
begin
p1: process is
begin
s1.points <= ((1, 2), (3, 4), (5, 6), (7, 8));
wait for 1 ns;
assert s1p1x = 1;
s1p1x <= 5;
wait for 1 ns;
assert s1.points = ((5, 2), (3, 4), (5, 6), (7, 8));
s2p <= ((1, 2), (3, 4));
wait for 1 ns;
assert s2p(1).x = 1;
assert s2.sub.points(2).y = 4;
wait;
end process;
end architecture;
|
gpl-3.0
|
4d4518f97e9fd179c7bac473842ad665
| 0.52533 | 3.036789 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd
| 4 | 2,276 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2969.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02969ent IS
END c02s03b01x00p02n02i02969ent;
ARCHITECTURE c02s03b01x00p02n02i02969arch OF c02s03b01x00p02n02i02969ent IS
type newt is (one,two,three,four);
function "mod" (constant c1,c2 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of left operator"
severity failure;
assert (c2=20)
report "Error in association of right operator"
severity failure;
assert NOT( c1=10 and c2=20 )
report "***PASSED TEST: c02s03b01x00p02n02i02969"
severity NOTE;
assert ( c1=10 and c2=20 )
report "***FAILED TEST: c02s03b01x00p02n02i02969 - Error in association of operands."
severity ERROR;
return three;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1 := two;
assert (n1=two)
report "Error in initial conditions detected"
severity failure;
n1:= 10 mod 20;
assert (n1=three)
report "Error in call to operloaded operator"
severity failure;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02969arch;
|
gpl-2.0
|
778bbe9151d77739bc4b8856ec0bb5f3
| 0.665202 | 3.670968 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd
| 4 | 2,102 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc402.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p11n01i00402ent IS
END c03s02b01x01p11n01i00402ent;
ARCHITECTURE c03s02b01x01p11n01i00402arch OF c03s02b01x01p11n01i00402ent IS
function WR_OR(Input : BIT_VECTOR) return BIT is
begin
for I in Input'Range loop
if Input(I) = '1' then
return '1';
end if;
end loop;
end;
BEGIN
TESTING: PROCESS
variable V1 : BIT_VECTOR(0 to 3) := "0101" ;
variable V2 : BIT;
BEGIN
V2 := WR_OR(V1) ; -- No_failure_here
assert NOT(V2 = '1')
report "***PASSED TEST: c03s02b01x01p11n01i00402"
severity NOTE;
assert ( V2 = '1' )
report "***FAILED TEST: c03s02b01x01p11n01i00402 - For a formal parameter of a subprogram that is of an unconstrained array type, the index ranges are obtained from the corresponding association element in the applicable subprogram call."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p11n01i00402arch;
|
gpl-2.0
|
f86e60d751a6b6bba1b1e1b8d85f2c87
| 0.666508 | 3.681261 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd
| 4 | 2,452 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_12 is
end entity ch_05_12;
----------------------------------------------------------------
architecture test of ch_05_12 is
signal top_a, bottom_a : bit := '0';
signal top_y, bottom_y : bit;
begin
block_05_3_m : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => top_a, y => top_y );
begin
-- code from book:
inv : process (a) is
begin
y <= inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_05_3_m;
----------------
block_05_3_n : block is
port ( a : in bit; y : out bit := '1' );
port map ( a => bottom_a, y => bottom_y);
begin
-- code from book:
inv : process (a) is
begin
y <= reject 2 ns inertial not a after 3 ns;
end process inv;
-- end of code from book
end block block_05_3_n;
----------------
stimulus_05_3_m_n : process is
begin
top_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 8 ns;
bottom_a <= '1' after 1 ns,
'0' after 6 ns,
'1' after 9 ns,
'0' after 11.5 ns,
'1' after 16 ns,
'0' after 18 ns,
'1' after 19 ns,
'0' after 20 ns;
wait;
end process stimulus_05_3_m_n;
end architecture test;
|
gpl-2.0
|
f539bdb94240ce32a1f2646e8ac0453b
| 0.510604 | 3.855346 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/convolution_2D/solution1/syn/vhdl/doImgProc_KERNEL_BUS_s_axi.vhd
| 4 | 14,313 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doImgProc_KERNEL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
kernel_address0 :in STD_LOGIC_VECTOR(3 downto 0);
kernel_ce0 :in STD_LOGIC;
kernel_q0 :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity doImgProc_KERNEL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x10 ~
-- 0x1f : Memory 'kernel' (3 * 8b)
-- Word n : bit [ 7: 0] - kernel[4n]
-- bit [15: 8] - kernel[4n+1]
-- bit [23:16] - kernel[4n+2]
-- bit [31:24] - kernel[4n+3]
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doImgProc_KERNEL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_KERNEL_BASE : INTEGER := 16#10#;
constant ADDR_KERNEL_HIGH : INTEGER := 16#1f#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- memory signals
signal int_kernel_address0 : UNSIGNED(1 downto 0);
signal int_kernel_ce0 : STD_LOGIC;
signal int_kernel_we0 : STD_LOGIC;
signal int_kernel_be0 : UNSIGNED(3 downto 0);
signal int_kernel_d0 : UNSIGNED(31 downto 0);
signal int_kernel_q0 : UNSIGNED(31 downto 0);
signal int_kernel_address1 : UNSIGNED(1 downto 0);
signal int_kernel_ce1 : STD_LOGIC;
signal int_kernel_we1 : STD_LOGIC;
signal int_kernel_be1 : UNSIGNED(3 downto 0);
signal int_kernel_d1 : UNSIGNED(31 downto 0);
signal int_kernel_q1 : UNSIGNED(31 downto 0);
signal int_kernel_read : STD_LOGIC;
signal int_kernel_write : STD_LOGIC;
signal int_kernel_shift : UNSIGNED(1 downto 0);
component doImgProc_KERNEL_BUS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end component doImgProc_KERNEL_BUS_s_axi_ram;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 1;
m := 2;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
begin
-- ----------------------- Instantiation------------------
-- int_kernel
int_kernel : doImgProc_KERNEL_BUS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 3,
AWIDTH => log2(3))
port map (
clk0 => ACLK,
address0 => int_kernel_address0,
ce0 => int_kernel_ce0,
we0 => int_kernel_we0,
be0 => int_kernel_be0,
d0 => int_kernel_d0,
q0 => int_kernel_q0,
clk1 => ACLK,
address1 => int_kernel_address1,
ce1 => int_kernel_ce1,
we1 => int_kernel_we1,
be1 => int_kernel_be1,
d1 => int_kernel_d1,
q1 => int_kernel_q1);
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) and (int_kernel_read = '0') else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
elsif (int_kernel_read = '1') then
rdata_data <= int_kernel_q1;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
-- ----------------------- Memory logic ------------------
-- kernel
int_kernel_address0 <= SHIFT_RIGHT(UNSIGNED(kernel_address0), 2)(1 downto 0);
int_kernel_ce0 <= kernel_ce0;
int_kernel_we0 <= '0';
int_kernel_be0 <= (others => '0');
int_kernel_d0 <= (others => '0');
kernel_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_kernel_q0, TO_INTEGER(int_kernel_shift) * 8)(7 downto 0));
int_kernel_address1 <= raddr(3 downto 2) when ar_hs = '1' else waddr(3 downto 2);
int_kernel_ce1 <= '1' when ar_hs = '1' or (int_kernel_write = '1' and WVALID = '1') else '0';
int_kernel_we1 <= '1' when int_kernel_write = '1' and WVALID = '1' else '0';
int_kernel_be1 <= UNSIGNED(WSTRB);
int_kernel_d1 <= UNSIGNED(WDATA);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_kernel_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_KERNEL_BASE and raddr <= ADDR_KERNEL_HIGH) then
int_kernel_read <= '1';
else
int_kernel_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_kernel_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_KERNEL_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_KERNEL_HIGH) then
int_kernel_write <= '1';
elsif (WVALID = '1') then
int_kernel_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (kernel_ce0 = '1') then
int_kernel_shift <= UNSIGNED(kernel_address0(1 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity doImgProc_KERNEL_BUS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end entity doImgProc_KERNEL_BUS_s_axi_ram;
architecture behave of doImgProc_KERNEL_BUS_s_axi_ram is
signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0);
signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0);
type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0);
shared variable mem : RAM_T := (others => (others => '0'));
begin
process (address0)
begin
address0_tmp <= address0;
--synthesis translate_off
if (address0 > DEPTH-1) then
address0_tmp <= (others => '0');
else
address0_tmp <= address0;
end if;
--synthesis translate_on
end process;
process (address1)
begin
address1_tmp <= address1;
--synthesis translate_off
if (address1 > DEPTH-1) then
address1_tmp <= (others => '0');
else
address1_tmp <= address1;
end if;
--synthesis translate_on
end process;
--read port 0
process (clk0) begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1') then
q0 <= mem(to_integer(address0_tmp));
end if;
end if;
end process;
--read port 1
process (clk1) begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1') then
q1 <= mem(to_integer(address1_tmp));
end if;
end if;
end process;
gen_write : for i in 0 to BYTES - 1 generate
begin
--write port 0
process (clk0)
begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1' and we0 = '1' and be0(i) = '1') then
mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i);
end if;
end if;
end process;
--write port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1' and we1 = '1' and be1(i) = '1') then
mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i);
end if;
end if;
end process;
end generate;
end architecture behave;
|
gpl-3.0
|
c31b716f47a01724dfdbe9da602344a9
| 0.483127 | 3.680381 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue317/PoC/src/common/fileio.v08.vhdl
| 2 | 7,805 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: File I/O-related Functions.
--
-- Description:
-- -------------------------------------
-- .. TODO:: No documentation available.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library PoC;
use PoC.my_project.all;
use PoC.utils.all;
use PoC.strings.all;
use PoC.ProtectedTypes.all;
package FileIO is
subtype T_LOGFILE_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE;
-- Constant declarations
constant C_LINEBREAK : string;
-- ===========================================================================
type T_LOGFILE is protected
procedure OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE);
impure function OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS;
procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE);
impure function IsOpen return boolean;
procedure CloseFile;
procedure Print(str : string);
procedure PrintLine(str : string := "");
procedure Flush;
-- procedure WriteLine(LineBuffer : inout LINE);
end protected;
-- ===========================================================================
type T_FILE is protected
procedure OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE);
impure function OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS;
procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE);
impure function IsOpen return boolean;
procedure CloseFile;
procedure Print(str : string);
procedure PrintLine(str : string := "");
procedure Flush;
-- procedure WriteLine(LineBuffer : inout LINE);
end protected;
type T_STDOUT is protected
procedure Print(str : string);
procedure PrintLine(str : string := "");
procedure Flush;
end protected;
end package;
package body FileIO is
constant C_LINEBREAK : string := ite(str_equal(MY_OPERATING_SYSTEM, "WINDOWS"), (CR & LF), (1 => LF));
-- ===========================================================================
file Global_LogFile : TEXT;
-- shared variable LogFile_IsOpen : P_BOOLEAN;
-- shared variable LogFile : T_LOGFILE;
-- shared variable StdOut : T_STDOUT;
-- shared variable LogFile_IsMirrored : P_BOOLEAN;
-- ===========================================================================
type T_LOGFILE is protected body
variable LineBuffer : LINE;
variable Local_IsOpen : boolean;
variable Local_FileName : string(1 to 256);
procedure OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is
variable Status : FILE_OPEN_STATUS;
begin
OpenFile(Status, FileName, OpenKind);
end procedure;
impure function OpenFile(FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
variable Status : FILE_OPEN_STATUS;
begin
OpenFile(Status, FileName, OpenKind);
return Status;
end function;
procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : T_LOGFILE_OPEN_KIND := WRITE_MODE) is
variable Status_i : FILE_OPEN_STATUS;
begin
if not Local_IsOpen then
file_open(Status_i, Global_LogFile, FileName, OpenKind);
Local_IsOpen := Status_i = OPEN_OK;
Local_FileName := resize(FileName, Local_FileName'length);
Status := Status_i;
else
report "Global log file '" & str_trim(Local_FileName) & "' is already open." severity ERROR;
end if;
end procedure;
impure function IsOpen return boolean is
begin
return Local_IsOpen;
end function;
procedure CloseFile is
begin
if Local_IsOpen then
file_close(Global_LogFile);
Local_IsOpen := FALSE;
end if;
end procedure;
procedure WriteLine(LineBuffer : inout LINE) is
begin
if not Local_IsOpen then
writeline(OUTPUT, LineBuffer);
-- elsif (LogFile_IsMirrored.Get = TRUE) then
-- tee(Global_LogFile, LineBuffer);
else
writeline(Global_LogFile, LineBuffer);
end if ;
end procedure;
procedure Print(str : string) is
begin
write(LineBuffer, str);
end procedure;
procedure PrintLine(str : string := "") is
begin
write(LineBuffer, str);
WriteLine(LineBuffer);
end procedure;
procedure Flush is
begin
WriteLine(LineBuffer);
end procedure;
end protected body;
type T_FILE is protected body
file LocalFile : TEXT;
variable LineBuffer : LINE;
variable Local_IsOpen : boolean;
variable Local_FileName : string(1 to 256);
procedure OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is
variable Status : FILE_OPEN_STATUS;
begin
OpenFile(Status, FileName, OpenKind);
end procedure;
impure function OpenFile(FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
variable Status : FILE_OPEN_STATUS;
begin
OpenFile(Status, FileName, OpenKind);
return Status;
end function;
impure function IsOpen return boolean is
begin
return Local_IsOpen;
end function;
procedure OpenFile(Status : out FILE_OPEN_STATUS; FileName : string; OpenKind : FILE_OPEN_KIND := WRITE_MODE) is
variable Status_i : FILE_OPEN_STATUS;
begin
if not Local_IsOpen then
file_open(Status_i, LocalFile, FileName, OpenKind);
Local_IsOpen := Status_i = OPEN_OK;
Local_FileName := resize(FileName, Local_FileName'length);
Status := Status_i;
else
report "File '" & str_trim(Local_FileName) & "' is already open." severity ERROR;
end if;
end procedure;
procedure CloseFile is
begin
if Local_IsOpen then
file_close(LocalFile);
Local_IsOpen := FALSE;
end if;
end procedure;
procedure WriteLine(LineBuffer : inout LINE) is
begin
if not Local_IsOpen then
report "File is not open." severity ERROR;
else
writeline(LocalFile, LineBuffer);
end if ;
end procedure;
procedure Print(str : string) is
begin
write(LineBuffer, str);
end procedure;
procedure PrintLine(str : string := "") is
begin
write(LineBuffer, str);
WriteLine(LineBuffer);
end procedure;
procedure Flush is
begin
WriteLine(LineBuffer);
end procedure;
end protected body;
type T_STDOUT is protected body
variable LineBuffer : LINE;
procedure Print(str : string) is
begin
write(LineBuffer, str);
end procedure;
procedure PrintLine(str : string := "") is
begin
write(LineBuffer, str);
writeline(OUTPUT, LineBuffer);
end procedure;
procedure Flush is
begin
writeline(OUTPUT, LineBuffer);
end procedure;
end protected body;
end package body;
|
gpl-2.0
|
7a521bd5222bc775ce324dc217283bf7
| 0.647021 | 3.748799 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd
| 4 | 2,556 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity instruction_interpreter is
end entity instruction_interpreter;
library ieee; use ieee.numeric_bit.all;
architecture test of instruction_interpreter is
subtype word is unsigned(31 downto 0);
signal address_bus, data_bus_in : word := X"0000_0000";
signal mem_read, mem_request, mem_ready : bit := '0';
begin
-- code from book
instruction_interpreter : process is
variable mem_address_reg, mem_data_reg,
prog_counter, instr_reg, accumulator, index_reg : word;
-- . . .
-- not in book
type opcode_type is (load_mem);
constant opcode : opcode_type := load_mem;
constant displacement : word := X"0000_0010";
-- end not in book
procedure read_memory is
begin
address_bus <= mem_address_reg;
mem_read <= '1';
mem_request <= '1';
wait until mem_ready = '1';
mem_data_reg := data_bus_in;
mem_request <= '0';
wait until mem_ready = '0';
end procedure read_memory;
begin
-- . . . -- initialization
loop
-- fetch next instruction
mem_address_reg := prog_counter;
read_memory; -- call procedure
instr_reg := mem_data_reg;
-- . . .
case opcode is
-- . . .
when load_mem =>
mem_address_reg := index_reg + displacement;
read_memory; -- call procedure
accumulator := mem_data_reg;
-- . . .
end case;
end loop;
end process instruction_interpreter;
-- end code from book
memory : process is
begin
wait until mem_request = '1';
data_bus_in <= X"1111_1111";
mem_ready <= '1';
wait until mem_request = '0';
mem_ready <= '0';
end process memory;
end architecture test;
|
gpl-2.0
|
aa882a6d6837ab7659fed4da0a64a5a0
| 0.631064 | 3.968944 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue672/SQRTb.vhd
| 1 | 2,653 |
-------------------------------------------------------------------------------
-- walter d. gallegos
-- www.waltergallegos.com
-- Programable Logic & Software
-- Consultoria y Diseno
--
-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos
--
-------------------------------------------------------------------------------
-- Autor : WDG
-- Fecha : 2018-09-21
-- Archivo : SPITb.vhd
-- Notas :
--
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL;
ENTITY SQRTb IS
END SQRTb;
ARCHITECTURE TB OF SQRTb IS
CONSTANT tCyc : TIME := 50 ns;
COMPONENT SQR
PORT (
CLOCK : IN std_logic;
DIN : IN std_logic_vector(31 downto 0);
VIN : IN std_logic;
DOUT : OUT std_logic_vector(31 downto 0);
VOUT : OUT std_logic
);
END COMPONENT SQR;
SIGNAL clock, vIn, vOut : STD_LOGIC;
SIGNAL dIn, dOut : STD_LOGIC_VECTOR (31 DOWNTO 0);
PROCEDURE Transfer(
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL clock : IN STD_LOGIC;
SIGNAL di : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL vOut : IN STD_LOGIC;
SIGNAL vIn : OUT STD_LOGIC) IS
BEGIN
WAIT UNTIL rising_edge(CLOCK);
WAIT FOR 1 ns; di <= d;
WAIT FOR 1 ns; Vin <= '1';
WAIT FOR tCyc; vIn <= '0';
WAIT FOR 1 ns;
WAIT UNTIL vOut = '1';
END PROCEDURE Transfer;
BEGIN
ClockGen : PROCESS
BEGIN
clock <= '0'; WAIT FOR tCyc/2;
clock <= '1'; WAIT FOR tCyc/2;
END PROCESS ClockGen;
A0 : SQR
PORT MAP (
CLOCK => clock,
DIN => dIn,
VIN => vIn,
DOUT => dOut,
VOUT => vOut
);
Stim : PROCESS
BEGIN
vIn <= '0';
WAIT FOR 100 ns; Transfer(x"00002000", clock, dIn, vOut, vIn );
WAIT FOR 200 ns; Transfer(x"00003000", clock, dIn, vOut, vIn );
WAIT FOR 100 ns; Transfer(x"00004000", clock, dIn, vOut, vIn );
WAIT FOR 100 ns; Transfer(x"08004000", clock, dIn, vOut, vIn );
WAIT;
END PROCESS Stim;
END TB;
CONFIGURATION Default OF SQRTb IS
FOR TB
FOR A0 : SQR
USE ENTITY work.SQR(REV0);
END FOR;
END FOR;
END Default;
|
gpl-2.0
|
c5fab3c45aaa5e60a6feb1902494e544
| 0.444026 | 4.399668 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd
| 4 | 1,694 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_30.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
library widget_cells, wasp_lib;
architecture cell_based of filter is
-- declaration of signals, etc
-- . . .
-- not in book
signal clk, filter_clk, accum_en, carry : bit;
signal sum, alu_op1, alu_op2, result : bit_vector(31 downto 0);
-- end not in book
begin
clk_pad : entity wasp_lib.in_pad
port map ( i => clk, z => filter_clk );
accum : entity widget_cells.reg32
port map ( en => accum_en, clk => filter_clk, d => sum,
q => result );
alu : entity work.adder
port map ( a => alu_op1, b => alu_op2, y => sum, c => carry );
-- other component instantiations
-- . . .
end architecture cell_based;
|
gpl-2.0
|
eb38760efef976c68f6c20ac8417042f
| 0.612751 | 3.798206 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue530/repro2.vhdl
| 1 | 1,083 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity submodule is
port (
clk : in std_logic;
arg : in std_logic_vector(15 downto 0);
res : out std_logic_vector(15 downto 0)
);
end submodule;
architecture behav of submodule is
begin
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sliced_ex is
port (
clk : in std_logic;
arg_a : in signed(7 downto 0);
arg_b : in signed(7 downto 0);
res_a : out signed(7 downto 0);
res_b : out signed(7 downto 0)
);
end sliced_ex;
architecture rtl of sliced_ex is
signal tmp : signed(15 downto 0);
begin
SUB_MODULE : entity work.submodule
port map (
clk => clk,
arg( 7 downto 0) => std_logic_vector(arg_a),
arg(15 downto 8) => std_logic_vector(arg_b),
-- The casting of a sliced output causes an exception.
-- Casting of the entire output bus does work
-- signed(res) => tmp -- (this would work)
signed(res( 7 downto 0)) => res_a,
signed(res(15 downto 8)) => res_b
);
end rtl;
|
gpl-2.0
|
2540c43ad6b810c7f56c2577e84b0436
| 0.632502 | 3.157434 | false | false | false | false |
nickg/nvc
|
test/regress/vests23.vhd
| 1 | 22,985 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests23 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END vests23;
ARCHITECTURE c01s01b01x01p05n02i00749arch OF vests23 IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st := (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a :record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record := (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) ;
signal V2 : severity_level_vector(zero to fifteen);
signal V3 : integer_vector(zero to fifteen) ;
signal V4 : real_vector(zero to fifteen) ;
signal V5 : time_vector (zero to fifteen);
signal V6 : natural_vector(zero to fifteen);
signal V7 : positive_vector(zero to fifteen);
signal V8 : boolean_cons_vector;
signal V9 : severity_level_cons_vector ;
signal V10 : integer_cons_vector;
signal V11 : real_cons_vector;
signal V12 : time_cons_vector ;
signal V13 : natural_cons_vector ;
signal V14 : positive_cons_vector ;
signal V15 : boolean_cons_vectorofvector ;
signal V16 : severity_level_cons_vectorofvector;
signal V17 : integer_cons_vectorofvector;
signal V18 : real_cons_vectorofvector;
signal V19 : time_cons_vectorofvector;
signal V20 : natural_cons_vectorofvector;
signal V21 : positive_cons_vectorofvector;
signal V22 : record_std_package;
signal V23 : record_cons_array ;
signal V24 : record_cons_arrayofarray ;
signal V25 : boolean_vector_st ;
signal V26 : severity_level_vector_st ;
signal V27 : integer_vector_st ;
signal V28 : real_vector_st ;
signal V29 : time_vector_st ;
signal V30 : natural_vector_st ;
signal V31 : positive_vector_st ;
signal V32 : record_array_st ;
signal V33 : record_array_st ;
signal V34 : record_array_new ;
signal V35 : record_of_records ;
signal V36 : byte ;
signal V37 : word ;
signal V41 : boolean_vector_range ;
signal V42 : severity_level_vector_range ;
signal V43 : integer_vector_range ;
signal V44 : real_vector_range ;
signal V45 : time_vector_range ;
signal V46 : natural_vector_range ;
signal V47 : positive_vector_range ;
signal V48 : array_rec_std(zero to seven) ;
signal V49 : array_rec_cons(zero to seven) ;
signal V50 : array_rec_rec(zero to seven) ;
signal V51 : record_of_arr_of_record ;
BEGIN
V1 <= (zero to fifteen => C1);
V2 <= (zero to fifteen => C4);
V3 <= (zero to fifteen => C5);
V4 <= (zero to fifteen => C6);
V5 <= (zero to fifteen => C7);
V6 <= (zero to fifteen => C8);
V7 <= (zero to fifteen => C9);
V8 <= C19;
V9 <= C20;
V10 <= C21;
V11 <= C22;
V12 <= C23;
V13 <= C24;
V14 <= C25;
V15 <= C26;
V16 <= C27;
V17 <= C28;
V18 <= C29;
V19 <= C30;
V20 <= C31;
V21 <= C32;
V22 <= C50;
V23 <= C51;
V24 <= C53;
V25 <= C70;
V26 <= C71;
V27 <= C72;
V28 <= C73;
V29 <= C74;
V30 <= C75;
V31 <= C76;
V32 <= C54a;
V33 <= C54a;
V34 <= C54b;
V35 <= C55;
V36 <= C60;
V37 <= C61;
V41 <= C78;
V42 <= C79;
V43 <= C80;
V44 <= C81;
V45 <= C82;
V46 <= C83;
V47 <= C84;
V48 <= C85;
V49 <= C86;
V50 <= C88;
V51 <= C102;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00749"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00749arch;
|
gpl-3.0
|
a26f8e08a933f7f02e7f8e56f52f47c6
| 0.545878 | 3.718052 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1237/mwe.vhdl
| 1 | 456 |
library ieee;
use ieee.std_logic_1164.all;
entity MWE is
end MWE;
architecture test of MWE is
constant P : integer := 1;
signal my_sig : std_logic_vector(P downto 0);
begin
block2: if P = 2 generate
my_sig(2) <= '1';
end generate;
block1: if P = 1 generate
my_sig(1) <= '1';
end generate;
-- even this block alone breaks during analysis
blockf: if false generate
my_sig(2) <= '1';
end generate;
end architecture;
|
gpl-2.0
|
ec6382501000bdeb66f11d0e9caf0ef3
| 0.640351 | 3.102041 | false | false | false | false |
nickg/nvc
|
test/regress/issue397.vhd
| 1 | 777 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity issue397 is
end issue397;
architecture behav of issue397 is
begin
process
variable i: integer;
variable r: real;
begin
r := 0.9;
i := integer(r);
assert i = 1 report real'image(r) & " cast to integer gives " & integer'image(i);
r := 0.3;
i := integer(r);
assert i = 0 report real'image(r) & " cast to integer gives " & integer'image(i);
report real'image(log2(real(8)));
r := floor(log2(real(8)));
i := integer(r);
assert i = 3 report "floor(log2(real(8))) cast to integer gives "
& integer'image(i) severity warning; -- TODO
wait;
end process;
end behav;
|
gpl-3.0
|
dabac5dc3f02b503649062c6cca0ac29
| 0.585586 | 3.306383 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/ticket89/repro.vhdl
| 3 | 350 |
entity repro is
end repro;
architecture behav of repro is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (0 ns);
end process;
process
begin
s <= 3;
wait for 1 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
|
gpl-2.0
|
dabad17b49013dacb86ebd0dae32bbe7
| 0.56 | 3.271028 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd
| 4 | 4,169 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3076.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03076pkg is
type integer_cons_vector is array (15 downto 0) of integer;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
constant C19 : integer_cons_vectorofvector := (others => (others => 3));
end c12s06b02x00p06n01i03076pkg;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent_a IS
PORT
(
F1: OUT integer ;
F3: IN integer_cons_vectorofvector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03076ent_a;
ARCHITECTURE c12s06b02x00p06n01i03076arch_a OF c12s06b02x00p06n01i03076ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03076arch_a;
use work.c12s06b02x00p06n01i03076pkg.all;
ENTITY c12s06b02x00p06n01i03076ent IS
END c12s06b02x00p06n01i03076ent;
ARCHITECTURE c12s06b02x00p06n01i03076arch OF c12s06b02x00p06n01i03076ent IS
function scalar_complex(s : integer) return integer_cons_vectorofvector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN integer_cons_vectorofvector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03076ent_a(c12s06b02x00p06n01i03076arch_a);
signal S1 : integer_cons_vectorofvector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03076"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03076 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03076arch;
|
gpl-2.0
|
8c75c683276dbc94deedeee94f488c95
| 0.666827 | 3.348594 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd
| 4 | 5,742 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.mechanical_systems.all;
entity inline_20a is
end entity inline_20a;
architecture test of inline_20a is
signal trigger, discharge, clk : bit;
constant capacitance : real := 1.0e-9;
begin
block_1 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
begin
-- code from book
i_cap == capacitance * v_cap'dot;
--
trigger_reset : process (trigger) is
begin
if trigger = '1' then
break v_cap => 0.0;
end if;
end process trigger_reset;
-- end code from book
end block block_1;
block_2 : block is
constant mass : real := 1.0;
terminal n : translational_v;
quantity v across n;
quantity applied_force : real;
quantity acceleration : real;
quantity vx, vy : real;
begin
acceleration == v'dot;
-- code from book
applied_force == mass * acceleration;
-- end code from book
process is
begin
-- code from book
break acceleration'integ => - acceleration'integ;
--
break vx => 0.0, vy => 0.0;
-- end code from book
wait;
end process;
end block block_2;
block_3 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
begin
i_cap == capacitance * v_cap'dot;
-- code from book
trigger_reset : process (trigger) is
begin
break v_cap => 0.0 when trigger = '1';
end process trigger_reset;
-- end code from book
end block block_3;
block_4 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
quantity charge : real;
begin
-- code from book
charge == capacitance * v_cap;
i_cap == charge'dot;
--
trigger_reset : process (trigger) is
begin
if trigger = '1' then
break for charge use v_cap => 0.0;
end if;
end process trigger_reset;
-- end code from book
end block block_4;
block_5 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
quantity charge : real;
begin
charge == capacitance * v_cap;
i_cap == charge'dot;
-- code from book
trigger_reset : process (trigger) is
begin
break for charge use v_cap => 0.0 when trigger = '1';
end process trigger_reset;
-- end code from book
end block block_5;
block_6 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
quantity cap_charge : real;
begin
cap_charge == capacitance * v_cap;
i_cap == cap_charge'dot;
-- code from book
discharge_cap : break cap_charge => 0.0
on clk when discharge = '1' and clk = '1';
-- end code from book
end block block_6;
block_7 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
quantity cap_charge : real;
begin
cap_charge == capacitance * v_cap;
i_cap == cap_charge'dot;
-- code from book
discharge_cap : process is
begin
break cap_charge => 0.0 when discharge = '1' and clk = '1';
wait on clk;
end process discharge_cap;
-- end code from book
end block block_7;
block_8 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
quantity charge : real;
begin
charge == capacitance * v_cap;
i_cap == charge'dot;
-- code from book
trigger_reset : break for charge use v_cap => 0.0 when trigger = '1';
-- end code from book
end block block_8;
block_9 : block is
terminal cap : electrical;
quantity v_cap across i_cap through cap;
quantity charge : real;
begin
charge == capacitance * v_cap;
i_cap == charge'dot;
-- code from book
trigger_reset : process is
begin
break for charge use v_cap => 0.0 when trigger = '1';
wait on trigger;
end process trigger_reset;
-- end code from book
end block block_9;
block_10 : block is
quantity q : real;
constant new_q : real := 0.0;
begin
-- code from book
useless_break : break q => new_q when q < 0.0 or q > 3.0;
-- end code from book
end block block_10;
block_11 : block is
quantity q : real;
constant new_q : real := 0.0;
begin
-- code from book
useless_break : process is
begin
break q => new_q when q < 0.0 or q > 3.0;
wait;
end process useless_break;
-- end code from book
end block block_11;
block_12 : block is
quantity q : real;
constant new_q : real := 0.0;
begin
-- code from book
correct_break : break q => new_q on q'above(0.0), q'above(3.0)
when q < 0.0 or q > 3.0;
-- end code from book
end block block_12;
end architecture test;
|
gpl-2.0
|
fa64c6dbd8f45cef8bdf33d4eaf860a6
| 0.609718 | 3.845948 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug017/call6.vhdl
| 2 | 342 |
entity call6 is
end;
architecture behav of call6 is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
begin
process
variable v : integer := 2;
begin
check ("bac");
wait for 2 ns;
check ((1 => 'e', 2 => 'a', 3 => 'c'));
report "SUCCESS";
wait;
end process;
end behav;
|
gpl-2.0
|
5257edef7abdf85a824326a9ec0a3181
| 0.555556 | 3.226415 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/iassoc01/iassoc03.vhdl
| 1 | 536 |
use work.pkg.all;
entity riassoc03 is
port (v : nat_arr (1 to 2);
res : out natural);
end riassoc03;
architecture behav of riassoc03 is
begin
process (v)
variable t : natural;
begin
t := 0;
for i in v'range loop
t := t + v (i);
end loop;
res <= t;
end process;
end behav;
entity iassoc03 is
port (a, b : natural;
res : out natural);
end iassoc03;
architecture behav of iassoc03 is
begin
inst : entity work.riassoc03
port map (v (1) => a, v (2) => b, res => res);
end behav;
|
gpl-2.0
|
622be24a2bc07343851ba5176bcc028b
| 0.600746 | 3.134503 | false | false | false | false |
nickg/nvc
|
test/regress/record28.vhd
| 1 | 1,033 |
package config is
constant width : integer;
end package;
-------------------------------------------------------------------------------
use work.config.all;
package types is
-- type pair is record
-- x, y : integer;
-- end record;
-- type pair_vec is array (natural range <>) of pair;
type rec is record
v : bit_vector(1 to width); -- OK
end record;
end package;
-------------------------------------------------------------------------------
package body config is
constant width : integer := 2;
end package body;
-------------------------------------------------------------------------------
entity record28 is
end entity;
use work.types.all;
architecture test of record28 is
signal r, s : rec;
begin
main: process is
begin
assert r.v'length = 2;
r <= ( v => "10" ) after 1 ns;
wait for 2 ns;
assert s.v = "10";
wait;
end process;
process (r) is
begin
s <= r;
end process;
end architecture;
|
gpl-3.0
|
a23ef03fe91cce6a6e2bec561eba6d7b
| 0.443369 | 4.491304 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/output01/tb_output01.vhdl
| 1 | 455 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_output01 is
end tb_output01;
architecture behav of tb_output01 is
signal i : std_logic;
signal o : std_logic_vector (1 downto 0);
begin
inst: entity work.output01
port map (i => i, o => o);
process
begin
i <= '0';
wait for 1 ns;
assert o = "10" severity failure;
i <= '1';
wait for 1 ns;
assert o = "01" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
c7c997862140655c8e1c324126327855
| 0.621978 | 3.159722 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/arr01/arr10.vhdl
| 1 | 659 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arr10 is
port (val : std_logic_vector(3 downto 0);
res : out natural);
end arr10;
architecture behav of arr10 is
function find (s : string; c : character) return natural is
begin
for i in s'range loop
if s (i) = c then
return i;
end if;
end loop;
return 0;
end find;
constant str1 : string := "hello world";
constant pos1 : natural := find (str1, 'w');
alias str2 : string (str1'length downto 1) is str1;
constant pos2 : natural := find (str2, 'w');
begin
assert pos1 = 7;
assert pos2 = 5;
res <= pos1;
end behav;
|
gpl-2.0
|
10f603156bf669feb42ef87b24ba83eb
| 0.626707 | 3.214634 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_Top_0/pr_region_default_Top_0_inst.vhd
| 1 | 8,997 |
component pr_region_default_Top_0 is
port (
clock : in std_logic := 'X'; -- clk
io_M_AXI_0_AWID : out std_logic_vector(5 downto 0); -- awid
io_M_AXI_0_AWUSER : out std_logic_vector(31 downto 0); -- awuser
io_M_AXI_0_AWADDR : out std_logic_vector(31 downto 0); -- awaddr
io_M_AXI_0_AWLEN : out std_logic_vector(7 downto 0); -- awlen
io_M_AXI_0_AWSIZE : out std_logic_vector(2 downto 0); -- awsize
io_M_AXI_0_AWBURST : out std_logic_vector(1 downto 0); -- awburst
io_M_AXI_0_AWLOCK : out std_logic; -- awlock
io_M_AXI_0_AWCACHE : out std_logic_vector(3 downto 0); -- awcache
io_M_AXI_0_AWPROT : out std_logic_vector(2 downto 0); -- awprot
io_M_AXI_0_AWQOS : out std_logic_vector(3 downto 0); -- awqos
io_M_AXI_0_AWVALID : out std_logic; -- awvalid
io_M_AXI_0_AWREADY : in std_logic := 'X'; -- awready
io_M_AXI_0_ARID : out std_logic_vector(5 downto 0); -- arid
io_M_AXI_0_ARUSER : out std_logic_vector(31 downto 0); -- aruser
io_M_AXI_0_ARADDR : out std_logic_vector(31 downto 0); -- araddr
io_M_AXI_0_ARLEN : out std_logic_vector(7 downto 0); -- arlen
io_M_AXI_0_ARSIZE : out std_logic_vector(2 downto 0); -- arsize
io_M_AXI_0_ARBURST : out std_logic_vector(1 downto 0); -- arburst
io_M_AXI_0_ARLOCK : out std_logic; -- arlock
io_M_AXI_0_ARCACHE : out std_logic_vector(3 downto 0); -- arcache
io_M_AXI_0_ARPROT : out std_logic_vector(2 downto 0); -- arprot
io_M_AXI_0_ARQOS : out std_logic_vector(3 downto 0); -- arqos
io_M_AXI_0_ARVALID : out std_logic; -- arvalid
io_M_AXI_0_ARREADY : in std_logic := 'X'; -- arready
io_M_AXI_0_WDATA : out std_logic_vector(511 downto 0); -- wdata
io_M_AXI_0_WSTRB : out std_logic_vector(63 downto 0); -- wstrb
io_M_AXI_0_WLAST : out std_logic; -- wlast
io_M_AXI_0_WVALID : out std_logic; -- wvalid
io_M_AXI_0_WREADY : in std_logic := 'X'; -- wready
io_M_AXI_0_RID : in std_logic_vector(5 downto 0) := (others => 'X'); -- rid
io_M_AXI_0_RUSER : in std_logic_vector(31 downto 0) := (others => 'X'); -- ruser
io_M_AXI_0_RDATA : in std_logic_vector(511 downto 0) := (others => 'X'); -- rdata
io_M_AXI_0_RRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- rresp
io_M_AXI_0_RLAST : in std_logic := 'X'; -- rlast
io_M_AXI_0_RVALID : in std_logic := 'X'; -- rvalid
io_M_AXI_0_RREADY : out std_logic; -- rready
io_M_AXI_0_BID : in std_logic_vector(5 downto 0) := (others => 'X'); -- bid
io_M_AXI_0_BUSER : in std_logic_vector(31 downto 0) := (others => 'X'); -- buser
io_M_AXI_0_BRESP : in std_logic_vector(1 downto 0) := (others => 'X'); -- bresp
io_M_AXI_0_BVALID : in std_logic := 'X'; -- bvalid
io_M_AXI_0_BREADY : out std_logic; -- bready
io_S_AVALON_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address
io_S_AVALON_readdata : out std_logic_vector(31 downto 0); -- readdata
io_S_AVALON_chipselect : in std_logic := 'X'; -- chipselect
io_S_AVALON_write : in std_logic := 'X'; -- write
io_S_AVALON_read : in std_logic := 'X'; -- read
io_S_AVALON_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reset : in std_logic := 'X' -- reset
);
end component pr_region_default_Top_0;
u0 : component pr_region_default_Top_0
port map (
clock => CONNECTED_TO_clock, -- clock.clk
io_M_AXI_0_AWID => CONNECTED_TO_io_M_AXI_0_AWID, -- io_M_AXI_0.awid
io_M_AXI_0_AWUSER => CONNECTED_TO_io_M_AXI_0_AWUSER, -- .awuser
io_M_AXI_0_AWADDR => CONNECTED_TO_io_M_AXI_0_AWADDR, -- .awaddr
io_M_AXI_0_AWLEN => CONNECTED_TO_io_M_AXI_0_AWLEN, -- .awlen
io_M_AXI_0_AWSIZE => CONNECTED_TO_io_M_AXI_0_AWSIZE, -- .awsize
io_M_AXI_0_AWBURST => CONNECTED_TO_io_M_AXI_0_AWBURST, -- .awburst
io_M_AXI_0_AWLOCK => CONNECTED_TO_io_M_AXI_0_AWLOCK, -- .awlock
io_M_AXI_0_AWCACHE => CONNECTED_TO_io_M_AXI_0_AWCACHE, -- .awcache
io_M_AXI_0_AWPROT => CONNECTED_TO_io_M_AXI_0_AWPROT, -- .awprot
io_M_AXI_0_AWQOS => CONNECTED_TO_io_M_AXI_0_AWQOS, -- .awqos
io_M_AXI_0_AWVALID => CONNECTED_TO_io_M_AXI_0_AWVALID, -- .awvalid
io_M_AXI_0_AWREADY => CONNECTED_TO_io_M_AXI_0_AWREADY, -- .awready
io_M_AXI_0_ARID => CONNECTED_TO_io_M_AXI_0_ARID, -- .arid
io_M_AXI_0_ARUSER => CONNECTED_TO_io_M_AXI_0_ARUSER, -- .aruser
io_M_AXI_0_ARADDR => CONNECTED_TO_io_M_AXI_0_ARADDR, -- .araddr
io_M_AXI_0_ARLEN => CONNECTED_TO_io_M_AXI_0_ARLEN, -- .arlen
io_M_AXI_0_ARSIZE => CONNECTED_TO_io_M_AXI_0_ARSIZE, -- .arsize
io_M_AXI_0_ARBURST => CONNECTED_TO_io_M_AXI_0_ARBURST, -- .arburst
io_M_AXI_0_ARLOCK => CONNECTED_TO_io_M_AXI_0_ARLOCK, -- .arlock
io_M_AXI_0_ARCACHE => CONNECTED_TO_io_M_AXI_0_ARCACHE, -- .arcache
io_M_AXI_0_ARPROT => CONNECTED_TO_io_M_AXI_0_ARPROT, -- .arprot
io_M_AXI_0_ARQOS => CONNECTED_TO_io_M_AXI_0_ARQOS, -- .arqos
io_M_AXI_0_ARVALID => CONNECTED_TO_io_M_AXI_0_ARVALID, -- .arvalid
io_M_AXI_0_ARREADY => CONNECTED_TO_io_M_AXI_0_ARREADY, -- .arready
io_M_AXI_0_WDATA => CONNECTED_TO_io_M_AXI_0_WDATA, -- .wdata
io_M_AXI_0_WSTRB => CONNECTED_TO_io_M_AXI_0_WSTRB, -- .wstrb
io_M_AXI_0_WLAST => CONNECTED_TO_io_M_AXI_0_WLAST, -- .wlast
io_M_AXI_0_WVALID => CONNECTED_TO_io_M_AXI_0_WVALID, -- .wvalid
io_M_AXI_0_WREADY => CONNECTED_TO_io_M_AXI_0_WREADY, -- .wready
io_M_AXI_0_RID => CONNECTED_TO_io_M_AXI_0_RID, -- .rid
io_M_AXI_0_RUSER => CONNECTED_TO_io_M_AXI_0_RUSER, -- .ruser
io_M_AXI_0_RDATA => CONNECTED_TO_io_M_AXI_0_RDATA, -- .rdata
io_M_AXI_0_RRESP => CONNECTED_TO_io_M_AXI_0_RRESP, -- .rresp
io_M_AXI_0_RLAST => CONNECTED_TO_io_M_AXI_0_RLAST, -- .rlast
io_M_AXI_0_RVALID => CONNECTED_TO_io_M_AXI_0_RVALID, -- .rvalid
io_M_AXI_0_RREADY => CONNECTED_TO_io_M_AXI_0_RREADY, -- .rready
io_M_AXI_0_BID => CONNECTED_TO_io_M_AXI_0_BID, -- .bid
io_M_AXI_0_BUSER => CONNECTED_TO_io_M_AXI_0_BUSER, -- .buser
io_M_AXI_0_BRESP => CONNECTED_TO_io_M_AXI_0_BRESP, -- .bresp
io_M_AXI_0_BVALID => CONNECTED_TO_io_M_AXI_0_BVALID, -- .bvalid
io_M_AXI_0_BREADY => CONNECTED_TO_io_M_AXI_0_BREADY, -- .bready
io_S_AVALON_address => CONNECTED_TO_io_S_AVALON_address, -- io_S_AVALON.address
io_S_AVALON_readdata => CONNECTED_TO_io_S_AVALON_readdata, -- .readdata
io_S_AVALON_chipselect => CONNECTED_TO_io_S_AVALON_chipselect, -- .chipselect
io_S_AVALON_write => CONNECTED_TO_io_S_AVALON_write, -- .write
io_S_AVALON_read => CONNECTED_TO_io_S_AVALON_read, -- .read
io_S_AVALON_writedata => CONNECTED_TO_io_S_AVALON_writedata, -- .writedata
reset => CONNECTED_TO_reset -- reset.reset
);
|
mit
|
588157cec1b6db3c2770ec69f334f691
| 0.459264 | 3.118544 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug17309/master_testbench3.vhdl
| 3 | 10,645 |
-------------------------------------------------------------------------------
-- Master testbench version 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity master_testbench3 is
-- Nada !
end master_testbench3;
use work.polyamplib.all;
architecture master_testbench3_arch of master_testbench3 is
shared variable running : boolean := true; -- Run testbench when true
-- Global signals
signal fastclk : std_logic := '0';
signal resync : std_logic := '0';
signal adc_data_0 : std_logic_vector(23 downto 0); -- Bus from AD-interface
signal adc_data_1 : std_logic_vector(23 downto 0); -- to mux
signal fifo_write : std_logic;
signal fifo_input : std_logic_vector(31 downto 0);
signal fifo_output : std_logic_vector(31 downto 0);
signal id_code : unsigned(3 downto 0);
signal id_code_i : unsigned(3 downto 0);
signal fifo_isempty : std_logic;
signal fifo_meter : unsigned(7 downto 0);
signal fifo_half_full : std_logic := '0';
signal enable_adcvalues : std_logic := '0'; -- Enable automatic emission of values
signal not_enable_adcvalues : std_logic;
-- Clocks
signal clk24M : std_logic := '0';
signal clk4M : std_logic := '0';
signal clk2M : std_logic := '0';
-- Channel 0
signal advalue_0 : signed(23 downto 0) := to_signed(192, 24); --Input to ADC
signal adclk_0 : std_logic;
signal ad_ser_data_0 : std_logic;
signal n_drdy_0 : std_logic;
signal n_sync_0 : std_logic;
signal adi_busy_0 : std_logic;
-- Channel 1
signal advalue_1 : signed(23 downto 0) := to_signed(193, 24);
signal adclk_1 : std_logic;
signal ad_ser_data_1 : std_logic;
signal n_drdy_1 : std_logic;
signal n_sync_1 : std_logic;
signal adi_busy_1 : std_logic;
-- Spi interface
signal addr_data : std_logic_vector(31 downto 0); -- Received command/data
signal exec_cmd : std_logic := '0';
signal fifo_read : std_logic := '0';
signal start_adcs : std_logic := '0';
signal stop_adcs : std_logic := '0';
signal mosi : std_logic := '0';
signal miso : std_logic;
signal sck : std_logic := '1';
signal en_adc : std_logic := '1'; -- Active low
signal en_incl : std_logic := '1'; -- Active low
signal incl_miso : std_logic := '0';
signal incl_mosi : std_logic;
signal incl_sck : std_logic;
signal incl_ena : std_logic;
-- Simulation
signal data_to_spi : std_logic_vector(31 downto 0);
signal data_from_spi : std_logic_vector(31 downto 0);
signal start : std_logic := '0';
signal spim_busy : std_logic := '0';
signal signal_running : std_logic := '1';
begin -- master_testbench3_arch
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
adc0 : ads1271_model port map (
analog_in => advalue_0,
clk => adclk_0,
sclk => adclk_0,
n_sync => n_sync_0,
din => '0',
dout => ad_ser_data_0,
n_drdy => n_drdy_0);
adc1 : ads1271_model port map (
analog_in => advalue_1,
clk => adclk_1,
sclk => adclk_1,
n_sync => n_sync_1,
din => '0',
dout => ad_ser_data_1,
n_drdy => n_drdy_1);
adi0 : interface_ads1271 port map (
fastclk => fastclk,
adclk => adclk_0,
resync => resync,
ser_data => ad_ser_data_0,
n_drdy => n_drdy_0,
data_out => adc_data_0,
nsync => n_sync_0,
busy => adi_busy_0);
adi1 : interface_ads1271 port map (
fastclk => fastclk,
adclk => adclk_1,
resync => resync,
ser_data => ad_ser_data_1,
n_drdy => n_drdy_1,
data_out => adc_data_1,
nsync => n_sync_1,
busy => adi_busy_1);
msm : master_state_machine port map (
fastclk => fastclk,
enable_lo8 => enable_adcvalues,
busy_n_vec(0) => adi_busy_0,
busy_n_vec(1) => adi_busy_1,
busy_n_vec(11 downto 2) => "1111111110", -- Not used in testbench
id_code => id_code,
fifo_write => fifo_write);
adck0 : clockmux port map (
clk24M => clk24M,
clk4M => clk4M,
clk2M => clk2M,
clk1M => '0',
clk512k => '0',
clk256k => '0',
clk128k => '0',
sel => "110", -- 24 MHz clock => 48 ksa/s
clkout => adclk_0);
adck1 : clockmux port map (
clk24M => clk24M,
clk4M => clk4M,
clk2M => clk2M,
clk1M => '0',
clk512k => '0',
clk256k => '0',
clk128k => '0',
sel => "100", -- 2 MHz clock => 4 ksa/s
clkout => adclk_1);
fifo : fifo_ft_memory port map (
clock => fastclk,
sclr => not_enable_adcvalues, -- fifo_sclr @@@@@@@@@@
datain => fifo_input,
wrreq => fifo_write,
rdreq => fifo_read,
dataout => fifo_output,
empty => fifo_isempty,
meter => fifo_meter);
sync : sync_logic_2 port map (
start_adcs => start_adcs,
stop_adcs => stop_adcs,
reset => '0',
hwsync => '0',
fastclk => fastclk,
enable_adcvalues => enable_adcvalues);
spis : spi_slave_burst port map (
fastclk => fastclk,
spi_tx => fifo_output,
spi_rx => addr_data,
-- spi_op => spi_op,
exec_cmd => exec_cmd,
fifo_read => fifo_read,
mosi => mosi,
miso => miso,
sck => sck,
en_adc => en_adc,
en_incl => en_incl,
incl_miso => incl_miso,
incl_mosi => incl_mosi,
incl_sck => incl_sck,
incl_ena => incl_ena);
cmd : command_decoder port map (
addr_data => addr_data,
decode => exec_cmd,
fastclk => fastclk,
resync_adc => resync,
start_adcs => start_adcs,
stop_adcs => stop_adcs);
-- empty_fifo => fifo_sclr); -- fifo_sclr / open
spim : spi_master port map (
miso => miso,
mosi => mosi,
sck => sck,
en_adval => en_adc,
en_incl => en_incl,
data_to_spi => data_to_spi,
data_from_spi => data_from_spi,
start => start,
busy => spim_busy,
running => signal_running);
-----------------------------------------------------------------------------
-- Here comes the code
-----------------------------------------------------------------------------
id_code_i <= id_code + 1; -- Skip NULL command/address
fifo_half_full <= fifo_meter(6); -- >= 64
not_enable_adcvalues <= not enable_adcvalues;
with id_code select
fifo_input(23 downto 0) <=
adc_data_0 when "0000",
adc_data_1 when "0001",
"000000000000000000000000" when others;
fifo_input(27 downto 24) <= "0000" when fifo_isempty = '1' else std_logic_vector(id_code_i);
fifo_input(31 downto 28) <= "0000";
-----------------------------------------------------------------------------
fetch_data : process
begin -- process fetch_data
data_to_spi <= "00000001000000000000000000000100"; -- sel_adclk0
wait for 2500 ns;
start <= '1';
wait until spim_busy = '1';
start <= '0';
wait until spim_busy = '0';
wait for 1 us;
data_to_spi <= "00000010000000000000000000000100"; -- sel_adclk1
wait for 7 us;
start <= '1';
wait until spim_busy = '1';
start <= '0';
wait until spim_busy = '0';
wait for 1 us;
-- data_to_spi <= "00000000000000000000000000000000"; -- Null command
data_to_spi <= "00001001000000000000000000000000"; -- resync
-- wait for 15 us;
wait for 1 us;
start <= '1';
wait until spim_busy = '1';
start <= '0';
wait until spim_busy = '0';
wait for 1 us;
data_to_spi <= "00001011000000000000000000000000"; -- Start AD-conv.
-- wait for 15 us;
wait for 1 us;
start <= '1';
wait until spim_busy = '1';
start <= '0';
wait until spim_busy = '0';
wait for 1 us;
for j in 1 to 250 loop
data_to_spi <= "00000000000000000000000000000000"; -- Null command
-- wait for 15 us;
wait for 2 us;
start <= '1';
wait until spim_busy = '1';
start <= '0';
wait until spim_busy = '0';
wait for 1 us;
end loop; -- j
wait for 2000 us;
for j in 1 to 250 loop
data_to_spi <= "00000000000000000000000000000000"; -- Null command
-- wait for 15 us;
wait for 2 us;
start <= '1';
wait until spim_busy = '1';
start <= '0';
wait until spim_busy = '0';
wait for 1 us;
end loop; -- j
wait;
end process fetch_data;
-----------------------------------------------------------------------------
main_timing : process
begin -- process main_timing
wait for 6 ms; -- Run during this time
signal_running <= '0';
running := false;
wait;
end process main_timing;
-----------------------------------------------------------------------------
osc_fastclk : process
begin -- process osc_fastclk
while running = true loop
fastclk <= '0';
wait for 10173 ps;
fastclk <= '1';
wait for 10173 ps;
end loop;
wait for 10 ns;
wait;
end process osc_fastclk;
-----------------------------------------------------------------------------
osc24M : process
begin -- process osc24M
while running = true loop
clk24M <= '0';
wait for 20345 ps;
clk24M <= '1';
wait for 20345 ps;
end loop;
wait for 10 ns;
wait;
end process osc24M;
-----------------------------------------------------------------------------
osc4M : process
begin -- process osc4M
while running = true loop
clk4M <= '0';
wait for 122 ns;
clk4M <= '1';
wait for 122 ns;
end loop;
wait for 10 ns;
wait;
end process osc4M;
-----------------------------------------------------------------------------
osc2M : process
begin -- process osc2M
while running = true loop
clk2M <= '0';
wait for 244 ns;
clk2M <= '1';
wait for 244 ns;
end loop;
wait for 10 ns;
wait;
end process osc2M;
end master_testbench3_arch;
|
gpl-2.0
|
ea60ba07c880163a4f7a85b6c3281132
| 0.489338 | 3.643053 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_sm.vhd
| 7 | 41,813 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
|
gpl-3.0
|
d66510be8f60d298cf607ca92b960f66
| 0.399589 | 4.608509 | false | false | false | false |
nickg/nvc
|
test/regress/array11.vhd
| 1 | 821 |
entity array11 is
end entity;
architecture test of array11 is
type rec is record
x : integer_vector;
end record;
type rec_vec is array (natural range <>) of rec;
function sum_all (r : rec_vec) return integer is
variable result : integer := 0;
begin
for i in r'range loop
for j in r(i).x'range loop
result := result + r(i).x(j);
end loop;
end loop;
return result;
end function;
signal s : rec_vec(1 to 2)(x(1 to 3));
begin
p1: process is
begin
s <= ( ( x => (1, 2, 3) ),
( x => (4, 5, 6) ) );
wait for 1 ns;
assert sum_all(s) = 21;
s(1).x(1) <= 5;
wait for 1 ns;
assert sum_all(s) = 25;
wait;
end process;
end architecture;
|
gpl-3.0
|
4650dfc3ece8a4e78060de3bd8547e93
| 0.498173 | 3.493617 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue736/tb_simple_fsm.vhdl
| 1 | 2,102 |
--Standard Library
library ieee;
--Standard Packages
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_simple_fsm is
end tb_simple_fsm;
architecture tb of tb_simple_fsm is
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal valid : std_logic := '0';
signal invalid : std_logic := '0';
-- Simulation support
signal clock_ena : boolean := false;
constant C_CLK_PERIOD : time := 10 ns;
-------------------------------------------------------------------------------
-- Clock generator procedure
-------------------------------------------------------------------------------
procedure clock_gen(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time
) is
variable v_first_half_clk_period : time := clock_period / 2;
begin
loop
if not clock_ena then
wait until clock_ena;
end if;
wait for v_first_half_clk_period;
clock_signal <= not clock_signal;
wait for (clock_period - v_first_half_clk_period);
clock_signal <= not clock_signal;
end loop;
end;
begin
clock_gen(clk, clock_ena, C_CLK_PERIOD);
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
dut : entity work.simple_fsm
port map (
clk => clk,
rst => rst,
valid => valid,
invalid => invalid);
p_main : process
begin
wait for 100 ns;
rst <= '1';
wait for 100 ns;
clock_ena <= true;
wait for 100 ns;
valid <= '1';
wait for 100 ns;
valid <= '0';
wait for 100 ns;
invalid <= '1';
wait for 100 ns;
invalid <= '0';
wait for 100 ns;
rst <= '0';
wait for 100 ns;
valid <= '1';
wait for 100 ns;
valid <= '0';
wait for 100 ns;
invalid <= '1';
wait for 100 ns;
invalid <= '0';
wait for 100 ns;
-- end sim
clock_ena <= false;
wait;
end process;
end tb;
|
gpl-2.0
|
1ae11cd22337409af42a2eb2d8c04239
| 0.47764 | 3.981061 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd
| 4 | 8,659 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mem-fl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all,
std.textio.all;
architecture file_loaded of memory is
begin
mem_behavior : process is
constant high_address : natural := mem_size - 1;
type memory_array is
array (natural range 0 to high_address / 4) of dlx_bv_word;
variable mem : memory_array;
variable byte_address, word_address : natural;
variable write_access : boolean;
procedure load is
file binary_file : text open read_mode is load_file_name;
variable L : line;
variable ch : character;
variable line_number : natural := 0;
variable addr : natural;
variable word : dlx_bv_word;
procedure read_hex_natural ( L : inout line; n : out natural ) is
variable result : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
result := result*16 + character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
result := result*16 + character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
result := result*16 + character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number) severity error;
end if;
end loop;
n := result;
end read_hex_natural;
procedure read_hex_word ( L : inout line; word : out dlx_bv_word ) is
variable digit : natural;
variable r : natural := 0;
begin
for i in 1 to 8 loop
read(L, ch);
if '0' <= ch and ch <= '9' then
digit := character'pos(ch) - character'pos('0');
elsif 'A' <= ch and ch <= 'F' then
digit := character'pos(ch) - character'pos('A') + 10;
elsif 'a' <= ch and ch <= 'f' then
digit := character'pos(ch) - character'pos('a') + 10;
else
report "Format error in file " & load_file_name
& " on line " & integer'image(line_number)
severity error;
end if;
word(r to r+3) := natural_to_bv(digit, 4);
r := r + 4;
end loop;
end read_hex_word;
begin
while not endfile(binary_file) loop
readline(binary_file, L);
line_number := line_number + 1;
read_hex_natural(L, addr);
read(L, ch); -- the space between addr and data
read_hex_word(L, word);
mem(addr / 4) := word;
end loop;
end load;
procedure do_write is
subtype ls_2_bits is bit_vector(1 downto 0);
begin
case width is
when dlx_mem_width_word =>
mem(word_address) := to_bitvector(d);
when dlx_mem_width_halfword =>
if To_bit(a(1)) = '0' then -- ms half word
mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
else -- ls half word
mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
end if;
when dlx_mem_width_byte =>
case ls_2_bits'(To_bitvector(a(1 downto 0))) is
when b"00" =>
mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
when b"01" =>
mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
when b"10" =>
mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
when b"11" =>
mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
end case;
when others =>
report "illegal width indicator in write" severity error;
end case;
end do_write;
procedure do_read is
begin
d <= To_X01( mem(word_address) );
end do_read;
begin
load; -- read binary memory image into memory array
-- initialize outputs
d <= disabled_dlx_word;
ready <= '0';
-- process memory cycles
loop
-- wait for a command, valid on leading edge of phi2
wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
-- decode address and perform command if selected
byte_address := bv_to_natural(To_bitvector(a));
write_access := To_bit(write_enable) = '1';
if byte_address <= high_address then
word_address := byte_address / 4;
if write_access then -- write cycle
do_write;
wait for Tac_first; -- write access time, 1st cycle
else -- read cycle
wait for Tac_first; -- read access time, 1st cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
-- do subsequent cycles in burst
while To_bit(burst) = '1' loop
word_address := (word_address + 1) mod (mem_size / 4);
wait until rising_edge(phi2);
if write_access then -- write cycle
do_write;
wait for Tac_burst; -- write access time, burst cycle
else -- read cycle
wait for Tac_burst; -- read access time, burst cycle
do_read;
end if;
-- ready synchronous with phi2
wait until rising_edge(phi2);
ready <= '1' after Tpd_clk_out;
wait until falling_edge(phi2);
ready <= '0' after Tpd_clk_out;
end loop;
if not write_access then -- was read
d <= disabled_dlx_word after Tpd_clk_out;
end if;
end if;
end loop;
end process mem_behavior;
end architecture file_loaded;
|
gpl-2.0
|
f3bc2ff4027fde609896d79af1905b65
| 0.429611 | 4.928287 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd
| 4 | 1,856 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity dac_10_bit is
port ( signal bus_in : in std_ulogic_vector(9 downto 0);
signal clk : in std_ulogic;
terminal analog_out : electrical );
end entity dac_10_bit;
----------------------------------------------------------------
architecture behavioral of dac_10_bit is
constant v_max : real := 5.0;
signal s_out : real := 0.0;
quantity v_out across i_out through analog_out to electrical_ref;
begin
convert : process is
variable v_sum : real;
variable delta_v : real;
begin
wait until clk'event and (clk = '1' or clk = 'H');
v_sum := 0.0;
delta_v := v_max;
for i in bus_in'range loop
delta_v := delta_v / 2.0;
if bus_in(i) = '1' or bus_in(i) = 'H' then
v_sum := v_sum + delta_v;
end if;
end loop;
s_out <= v_sum;
end process convert;
v_out == s_out'ramp(100.0E-9);
end architecture behavioral;
|
gpl-2.0
|
f84c9636b075a99a3ddb4c6fd64b9d97
| 0.633082 | 3.689861 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/synth34/tb_repro_rng1.vhdl
| 1 | 607 |
entity tb_repro_rng1 is
end tb_repro_rng1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro_rng1 is
signal clk : std_logic;
signal a : natural range 0 to 7;
signal b : natural range 0 to 7;
begin
dut: entity work.repro_rng1
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= 1;
pulse;
assert b = 1 severity failure;
a <= 6;
pulse;
assert b = 6 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
a55e3fc74f267636c913d904b4348cc9
| 0.586491 | 3.281081 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1025/tb_ent.vhdl
| 1 | 714 |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal counter : natural;
signal rst : std_logic;
begin
dut: entity work.ent
port map (
rst => rst,
clk => clk,
counter => counter);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert counter = 0 severity failure;
rst <= '0';
pulse;
assert counter = 1 severity failure;
pulse;
assert counter = 2 severity failure;
pulse;
assert counter = 3 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
76dd6f986fa915720301a236f44d7af2
| 0.592437 | 3.699482 | false | false | false | false |
nickg/nvc
|
test/regress/case14.vhd
| 1 | 1,546 |
package my_package is
type slv_1_t is array (natural range <>) of bit_vector;
type slv_2_t is array (natural range <>,natural range <>) of bit_vector;
subtype my_mat_t is slv_2_t(0 to 4-1,0 to 4-1)(8-1 downto 0);
function my_function_f(arg0 : my_mat_t; constant arg2 : natural range 0 to 4-1) return slv_2_t;
end package my_package;
package body my_package is
function my_function_f(arg0 : my_mat_t; constant arg2 : natural range 0 to 4-1) return slv_2_t is
variable retval : arg0'subtype;
variable my_var_v : slv_1_t(0 to 4-1)(8-1+3 downto 0);
begin
L1: for indI in retval'range(1) loop
L2: for indJ in retval'range(2) loop
case indJ=arg2 is
when false => null;
when true =>
L3: for indK in 8 to 10 loop
-- Crash here due to control flow in case expression
case my_var_v(indI)(indK downto indK) is
when B"0" => report "zero";
when B"1" => report "one";
when others => NULL;
end case;
end loop;
when others => NULL;
end case;
end loop;
end loop;
return retval;
end function my_function_f;
end package body;
-------------------------------------------------------------------------------
entity case14 is
end entity;
use work.my_package.all;
architecture test of case14 is
begin
p1: process is
variable v : my_mat_t;
begin
wait for 1 ns;
assert my_function_f(v, 0) = v;
wait;
end process;
end architecture;
|
gpl-3.0
|
ec6c4bf3ba6b0f2ba749b997312bc746
| 0.56727 | 3.397802 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xil_defaultlib/doHistStretch_ap_fmul_2_max_dsp_32.vhd
| 2 | 10,800 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
|
gpl-3.0
|
4f893810aa62889bc4d5cc5e59f50130
| 0.632685 | 3.219076 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd
| 4 | 1,783 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity fg_a_09 is
end entity fg_a_09;
library ieee; use ieee.std_logic_1164.all;
architecture test of fg_a_09 is
signal clk25M, resetl : std_ulogic;
signal data, odat : std_ulogic_vector(7 downto 0);
begin
-- code from book
wrong_way : process ( clk25M, resetl, data )
begin
if resetl = '0' then
odat <= B"0000_0000";
elsif rising_edge(clk25M) then
odat <= data;
elsif data = B"0000_0000" then
odat <= B"0000_0001";
end if;
end process wrong_way;
-- end code from book
data <= odat(6 downto 0) & '0';
clk_gen : process is
begin
clk25M <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
resetl <= '1', '0' after 20 ns, '1' after 60 ns;
end architecture test;
|
gpl-2.0
|
aac7c139d239ab4d4dea9d11a6c48be2
| 0.618059 | 3.623984 | false | false | false | false |
nickg/nvc
|
test/lower/tounsigned.vhd
| 1 | 595 |
package p is
type UNSIGNED is array (NATURAL range <>) of bit;
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
end package;
package body p is
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
mainloop: for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then -- Mod should be replaced with rem
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
return RESULT;
end TO_UNSIGNED;
end package body;
|
gpl-3.0
|
c6f793380fe13c93ab78b49392401e3f
| 0.633613 | 3.584337 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/mem01/sram05.vhdl
| 1 | 821 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram05 is
port (
rst : std_logic;
clk_i : std_logic;
addr_i : std_logic_vector(3 downto 0);
data_i : std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
wen_i : std_logic);
end sram05;
architecture behav of sram05 is
begin
process (clk_i, addr_i)
type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
variable mem : mem_type;
variable addr : natural range mem_type'range;
begin
if rising_edge(clk_i) then
if rst = '1' then
null;
else
addr := to_integer (unsigned (addr_i));
if wen_i = '1' then
mem (addr) := data_i;
end if;
data_o <= mem (addr);
end if;
end if;
end process;
end behav;
|
gpl-2.0
|
386e21b1767d2cc2b8e6670e6e878cf6
| 0.590743 | 3.098113 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_100M_0/sim/design_1_rst_processing_system7_0_100M_0.vhd
| 1 | 5,938 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
|
gpl-3.0
|
7a9d277880879c7afb78b4ff9b137169
| 0.708993 | 3.56851 | false | false | false | false |
lfmunoz/vhdl
|
types.vhd
| 1 | 5,888 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
--
--
--
-- How to use?
--note this line.The package is compiled to this directory by default.
--so don't forget to include this directory.
--library work;
--this line also is must.This includes the particular package into your program.
--use work.test_pkg.all;
--
--
--
--
----------------------------------------------------------------------------------------------------
-- LIBRARIES
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
----------------------------------------------------------------------------------------------------
-- PACKGE
----------------------------------------------------------------------------------------------------
package types is
type bus002 is array(natural range <>) of std_logic_vector( 1 downto 0);
type bus004 is array(natural range <>) of std_logic_vector( 3 downto 0);
type bus005 is array(natural range <>) of std_logic_vector( 4 downto 0);
type bus006 is array(natural range <>) of std_logic_vector( 5 downto 0);
type bus007 is array(natural range <>) of std_logic_vector( 6 downto 0);
type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0);
type bus009 is array(natural range <>) of std_logic_vector( 8 downto 0);
type bus010 is array(natural range <>) of std_logic_vector( 9 downto 0);
type bus011 is array(natural range <>) of std_logic_vector( 10 downto 0);
type bus012 is array(natural range <>) of std_logic_vector( 11 downto 0);
type bus013 is array(natural range <>) of std_logic_vector( 12 downto 0);
type bus014 is array(natural range <>) of std_logic_vector( 13 downto 0);
type bus015 is array(natural range <>) of std_logic_vector( 14 downto 0);
type bus016 is array(natural range <>) of std_logic_vector( 15 downto 0);
type bus017 is array(natural range <>) of std_logic_vector( 16 downto 0);
type bus018 is array(natural range <>) of std_logic_vector( 17 downto 0);
type bus019 is array(natural range <>) of std_logic_vector( 18 downto 0);
type bus020 is array(natural range <>) of std_logic_vector( 19 downto 0);
type bus021 is array(natural range <>) of std_logic_vector( 20 downto 0);
type bus022 is array(natural range <>) of std_logic_vector( 21 downto 0);
type bus023 is array(natural range <>) of std_logic_vector( 22 downto 0);
type bus024 is array(natural range <>) of std_logic_vector( 23 downto 0);
type bus025 is array(natural range <>) of std_logic_vector( 24 downto 0);
type bus026 is array(natural range <>) of std_logic_vector( 25 downto 0);
type bus027 is array(natural range <>) of std_logic_vector( 26 downto 0);
type bus028 is array(natural range <>) of std_logic_vector( 27 downto 0);
type bus029 is array(natural range <>) of std_logic_vector( 28 downto 0);
type bus030 is array(natural range <>) of std_logic_vector( 29 downto 0);
type bus031 is array(natural range <>) of std_logic_vector( 30 downto 0);
type bus032 is array(natural range <>) of std_logic_vector( 31 downto 0);
type bus064 is array(natural range <>) of std_logic_vector( 63 downto 0);
type bus128 is array(natural range <>) of std_logic_vector(127 downto 0);
type bus256 is array(natural range <>) of std_logic_vector(255 downto 0);
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
--***************************************************************************************************
end types;
--***************************************************************************************************
----------------------------------------------------------------------------------------------------
-- PACKGE BODY
----------------------------------------------------------------------------------------------------
package body types is
function reverse_any_vector (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end;
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
--**************************************************************************************************
end types;
--***************************************************************************************************
|
mit
|
4ce43a6d5103dd1ea6b1159614f2978a
| 0.548404 | 3.823377 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd
| 4 | 2,499 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end entity D_flipflop;
architecture behavioral of D_flipflop is
begin
q <= d when clk'event and clk = '1';
end architecture behavioral;
entity inverter is
port ( a : in bit; y : out bit );
end entity inverter;
architecture behavioral of inverter is
begin
y <= not a;
end architecture behavioral;
-- code from book
entity count2 is
port ( clk : in bit; q0, q1 : buffer bit );
end entity count2;
--------------------------------------------------
architecture buffered_outputs of count2 is
component D_flipflop is
port ( clk, d : in bit; q : buffer bit );
end component D_flipflop;
component inverter is
port ( a : in bit; y : out bit );
end component inverter;
signal q0_n, q1_n : bit;
begin
bit0 : component D_flipflop
port map ( clk => clk, d => q0_n, q => q0 );
inv0 : component inverter
port map ( a => q0, y => q0_n );
bit1 : component D_flipflop
port map ( clk => q0_n, d => q1_n, q => q1 );
inv1 : component inverter
port map ( a => q1, y => q1_n );
end architecture buffered_outputs;
-- end code from book
entity fg_21_01 is
end entity fg_21_01;
architecture test of fg_21_01 is
signal clk, q0, q1 : bit;
begin
dut : entity work.count2(buffered_outputs)
port map ( clk => clk, q0 => q0, q1 => q1 );
clk_gen : clk <= not clk after 10 ns;
end architecture test;
|
gpl-2.0
|
a89d6aa2bc77eaa301c04f8f8f84e2db
| 0.607443 | 3.702222 | false | false | false | false |
nickg/nvc
|
test/regress/array9.vhd
| 1 | 2,979 |
-- From UVVM uvvm_util/src/methods_pkg.vhd
-- License: Apache 2.0
--
package p1 is
type t_byte_endianness is (LOWER_BYTE_LEFT, FIRST_BYTE_LEFT, LOWER_BYTE_RIGHT, FIRST_BYTE_RIGHT) ;
type t_slv_array is array(natural range <>) of bit_vector ;
subtype t_byte_array is t_slv_array(open)(7 downto 0) ;
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_slv_array;
end package ;
package body p1 is
-- Converts a t_byte_array (any direction) to a t_slv_array (same direction)
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_slv_array is
constant c_num_words : integer := byte_array'length/bytes_in_word;
variable v_ascending_array : t_slv_array(0 to c_num_words-1)((8*bytes_in_word)-1 downto 0);
variable v_descending_array : t_slv_array(c_num_words-1 downto 0)((8*bytes_in_word)-1 downto 0);
variable v_byte_idx : integer := 0;
begin
for slv_idx in 0 to c_num_words-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for byte_in_word in bytes_in_word downto 1 loop
v_ascending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_descending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for byte_in_word in 1 to bytes_in_word loop
v_ascending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_descending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
end if;
end loop;
if byte_array'ascending then
return v_ascending_array;
else -- byte array is descending
return v_descending_array;
end if;
end function;
end package body ;
entity array9 is end entity ;
use work.p1.all;
architecture arch of array9 is
signal s : t_byte_array(0 to 3) := ( X"44", X"55", X"66", X"77" );
begin
process
begin
report to_string(convert_byte_array_to_slv_array(s, 1)(0));
assert convert_byte_array_to_slv_array(s, 1) = s;
assert convert_byte_array_to_slv_array(s, 2) = (X"4455", X"6677");
assert convert_byte_array_to_slv_array(s, 4) = (0 => X"44556677");
std.env.stop ;
end process;
end architecture ;
|
gpl-3.0
|
e7b7ee4b71ffbcc395bba73dd907573b
| 0.59718 | 3.245098 | false | false | false | false |
nickg/nvc
|
test/regress/case10.vhd
| 1 | 604 |
entity case10 is
end entity;
architecture test of case10 is
type my_enum is (a, b, c);
signal e : my_enum;
signal i : natural;
begin
update: process (i) is
begin
case i is
when my_enum'pos(a) => e <= a;
when my_enum'pos(b) => e <= b;
when my_enum'pos(c) => e <= c;
when others => null;
end case;
end process;
main: process is
begin
i <= 0;
wait for 1 ns;
assert e = a;
i <= 2;
wait for 1 ns;
assert e = c;
wait;
end process;
end architecture;
|
gpl-3.0
|
2d2f02fac938069c2fec99c0f09abbe8
| 0.480132 | 3.511628 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1250/theunit.vhdl
| 1 | 653 |
library ieee;
use ieee.std_logic_1164.all;
entity theunit is
port (dout : out std_ulogic);
end;
architecture rtl of theunit is
subtype thenum_t is integer range 0 to 1;
type rec_t is record
-- NOTE: changing order of these members prevents crash
data0 : std_ulogic;
bankm : std_ulogic_vector(thenum_t);
end record;
signal r : rec_t;
begin
thecomb : process(r)
variable v : rec_t;
variable thenum : thenum_t := 1;
begin
v.data0 := '1';
v.bankm := (others => '1');
-- NOTE: removing any of the lines below prevents crash
v.bankm(thenum) := '0';
r <= v;
dout <= r.data0;
end process;
end;
|
gpl-2.0
|
ddf25f5d5359096a157be6f5b4ebd600
| 0.629403 | 3.154589 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd
| 4 | 57,853 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc754.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00754pkg is
subtype hi_to_low_range is integer range 0 to 7;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(0 to 15);
b:severity_level_vector(0 to 15);
c:integer_vector(0 to 15);
d:real_vector(0 to 15);
e:time_vector(0 to 15);
f:natural_vector(0 to 15);
g:positive_vector(0 to 15);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(0 to 7);
b: array_rec_cons(0 to 7);
c: array_rec_rec(0 to 7);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
constant size :integer := 7;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range 1 to 10;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78 : boolean_vector_range := (others => C1);
constant C79 : severity_level_vector_range := (others => C4) ;
constant C80 : integer_vector_range :=(others => C5) ;
constant C81 : real_vector_range :=(others => C6);
constant C82 : time_vector_range :=(others => C7);
constant C83 : natural_vector_range :=(others => C8);
constant C84 : positive_vector_range :=(others => C9);
constant C85 : array_rec_std(0 to 7) :=(others => C50) ;
constant C86 : array_rec_cons (0 to 7) :=(others => C51);
constant C88 : array_rec_rec(0 to 7) :=(others => C55);
constant C102 : record_of_arr_of_record:= (C85,C86,C88);
end c01s01b01x01p05n02i00754pkg;
use work.c01s01b01x01p05n02i00754pkg.all;
ENTITY c01s01b01x01p05n02i00754ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
port(
S1 : boolean_vector(zero to fifteen);
S2 : severity_level_vector(zero to fifteen);
S3 : integer_vector(zero to fifteen);
S4 : real_vector(zero to fifteen);
S5 : time_vector (zero to fifteen);
S6 : natural_vector(zero to fifteen);
S7 : positive_vector(zero to fifteen);
S8 : boolean_cons_vector;
S9 : severity_level_cons_vector ;
S10 : integer_cons_vector;
S11 : real_cons_vector;
S12 : time_cons_vector ;
S13 : natural_cons_vector ;
S14 : positive_cons_vector ;
S15 : boolean_cons_vectorofvector;
S16 : severity_level_cons_vectorofvector;
S17 : integer_cons_vectorofvector;
S18 : real_cons_vectorofvector;
S19 : time_cons_vectorofvector;
S20 : natural_cons_vectorofvector;
S21 : positive_cons_vectorofvector;
S22 : record_std_package;
S23 : record_cons_array;
S24 : record_cons_arrayofarray ;
S25 : boolean_vector_st;
S26 : severity_level_vector_st;
S27 : integer_vector_st;
S28 : real_vector_st;
S29 : time_vector_st;
S30 : natural_vector_st;
S31 : positive_vector_st;
S32 : record_array_st;
S33 : record_array_st;
S34 : record_array_new;
S35 : record_of_records;
S36 : byte;
S37 : word;
S38 : current_vector(zero to three);
S39 : resistance_vector(zero to three);
S40 : delay;
S41 : boolean_vector_range;
S42 : severity_level_vector_range ;
S43 : integer_vector_range ;
S44 : real_vector_range ;
S45 : time_vector_range ;
S46 : natural_vector_range ;
S47 : positive_vector_range ;
S48 : array_rec_std(zero to seven);
S49 : array_rec_cons(zero to seven);
S50 : array_rec_rec(zero to seven);
S51 : record_of_arr_of_record
);
END c01s01b01x01p05n02i00754ent;
ARCHITECTURE c01s01b01x01p05n02i00754arch OF c01s01b01x01p05n02i00754ent IS
BEGIN
assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity error;
assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity error;
assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity error;
assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity error;
assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity error;
assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity error;
assert (S9'left = 15) report " severity_level_cons_vector error in the left generic value" severity error;
assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity error;
assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity error;
assert (S12'left = 15) report " time_cons_vector error in the left generic value" severity error;
assert (S13'left = 15) report " natural_cons_vector error in the left generic value" severity error;
assert (S14'left = 15) report " positive_cons_vector error in the left generic value" severity error;
assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity error;
assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity error;
assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity error;
assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity error;
assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity error;
assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity error;
assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity error;
assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity error;
assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity error;
assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S24.a'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.b'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.c'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.d'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.e'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.f'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.g'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity error;
assert (S26'left = 0) report " severity_level_vector_st error in the left generic value" severity error;
assert (S27'left = 0) report " integer_vector_st error in the left generic value" severity error;
assert (S28'left = 0) report " real_vector_st error in the left generic value" severity error;
assert (S29'left = 0) report " time_vector_st error in the left generic value" severity error;
assert (S30'left = 0) report " natural_vector_st error in the left generic value" severity error;
assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity error;
assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S36'left = 0) report " byte error in the left generic value" severity error;
assert (S37'left = 0) report " word error in the left generic value" severity error;
assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity error;
assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity error;
--assert (S40'left = 1) report " delay error in the left generic value" severity error;
assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity error;
assert (S42'left = 0) report " severity_level_vector_range error in the left generic value" severity error;
assert (S43'left = 0) report " integer_vector_range error in the left generic value" severity error;
assert (S44'left = 0) report " real_vector_range error in the left generic value" severity error;
assert (S45'left = 0) report " time_vector_range error in the left generic value" severity error;
assert (S46'left = 0) report " natural_vector_range error in the left generic value" severity error;
assert (S47'left = 0) report " positive_vector_range error in the left generic value" severity error;
assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity error;
assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity error;
assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity error;
assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity error;
assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity error;
assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity error;
assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity error;
assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity error;
assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity error;
assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity error;
assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity error;
assert (S9'right = 0) report " severity_level_cons_vector error in the right generic value" severity error;
assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity error;
assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity error;
assert (S12'right = 0) report " time_cons_vector error in the right generic value" severity error;
assert (S13'right = 0) report " natural_cons_vector error in the right generic value" severity error;
assert (S14'right = 0) report " positive_cons_vector error in the right generic value" severity error;
assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity error;
assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity error;
assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity error;
assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity error;
assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity error;
assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity error;
assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity error;
assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity error;
assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity error;
assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S24.a'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.b'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.c'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.d'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.e'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.f'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.g'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity error;
assert (S26'right = 15) report " severity_level_vector_st error in the right generic value" severity error;
assert (S27'right = 15) report " integer_vector_st error in the right generic value" severity error;
assert (S28'right = 15) report " real_vector_st error in the right generic value" severity error;
assert (S29'right = 15) report " time_vector_st error in the right generic value" severity error;
assert (S30'right = 15) report " natural_vector_st error in the right generic value" severity error;
assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity error;
assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S36'right = 7) report " byte error in the right generic value" severity error;
assert (S37'right = 15) report " word error in the right generic value" severity error;
assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity error;
assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity error;
--assert (S40'right = 1) report " delay error in the right generic value" severity error;
assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity error;
assert (S42'right = 7) report " severity_level_vector_range error in the right generic value" severity error;
assert (S43'right = 7) report " integer_vector_range error in the right generic value" severity error;
assert (S44'right = 7) report " real_vector_range error in the right generic value" severity error;
assert (S45'right = 7) report " time_vector_range error in the right generic value" severity error;
assert (S46'right = 7) report " natural_vector_range error in the right generic value" severity error;
assert (S47'right = 7) report " positive_vector_range error in the right generic value" severity error;
assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity error;
assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity error;
assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity error;
assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity error;
assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity error;
assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity error;
assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity error;
assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity error;
assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity error;
assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity error;
assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity error;
assert (S9'length = 16) report " severity_level_cons_vector error in the length generic value" severity error;
assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity error;
assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity error;
assert (S12'length = 16) report " time_cons_vector error in the length generic value" severity error;
assert (S13'length = 16) report " natural_cons_vector error in the length generic value" severity error;
assert (S14'length = 16) report " positive_cons_vector error in the length generic value" severity error;
assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity error;
assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity error;
assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity error;
assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity error;
assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity error;
assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity error;
assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity error;
assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity error;
assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity error;
assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S24.a'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.b'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.c'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.d'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.e'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.f'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.g'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity error;
assert (S26'length = 16) report " severity_level_vector_st error in the length generic value" severity error;
assert (S27'length = 16) report " integer_vector_st error in the length generic value" severity error;
assert (S28'length = 16) report " real_vector_st error in the length generic value" severity error;
assert (S29'length = 16) report " time_vector_st error in the length generic value" severity error;
assert (S30'length = 16) report " natural_vector_st error in the length generic value" severity error;
assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity error;
assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S36'length = 8) report " byte error in the length generic value" severity error;
assert (S37'length = 16) report " word error in the length generic value" severity error;
assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity error;
assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity error;
--assert (S40'length = 1) report " delay error in the length generic value" severity error;
assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity error;
assert (S42'length = 8) report " severity_level_vector_range error in the length generic value" severity error;
assert (S43'length = 8) report " integer_vector_range error in the length generic value" severity error;
assert (S44'length = 8) report " real_vector_range error in the length generic value" severity error;
assert (S45'length = 8) report " time_vector_range error in the length generic value" severity error;
assert (S46'length = 8) report " natural_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " positive_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity error;
assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity error;
assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity error;
assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
TESTING: PROCESS
BEGIN
assert NOT( (S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***PASSED TEST: c01s01b01x01p05n02i00754"
severity NOTE;
assert ((S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***FAILED TEST: c01s01b01x01p05n02i00754 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00754arch;
|
gpl-2.0
|
333d8d7c7a56eb5a71cbde540e2f7506
| 0.565243 | 3.631929 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue418/tc749-2.vhdl
| 1 | 3,419 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY tc749 IS
generic(
zero : integer := 0;
seven: integer := 7;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1
);
END tc749;
ARCHITECTURE arch OF tc749 IS
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type array_rec_cons is array (integer range <>) of record_cons_array;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C86: array_rec_cons (0 to 7) :=(others => C51);
signal V49 : array_rec_cons(zero to seven) ;
BEGIN
V49 <= C86;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert V49= C86 report " error in initializing S49" severity error;
wait;
END PROCESS TESTING;
END arch;
|
gpl-2.0
|
01a8933ba88b42de12bd971cfcf6a5d3
| 0.592278 | 3.858916 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/mem01/tb_sram03.vhdl
| 1 | 976 |
entity tb_sram03 is
end tb_sram03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_sram03 is
signal addr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal wen : std_logic;
signal clk : std_logic;
begin
dut: entity work.sram03
port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat,
wen_i => wen);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
addr <= "0000";
wdat <= x"03";
wen <= '1';
pulse;
wdat <= x"41";
pulse;
assert rdat = x"03" severity failure;
addr <= "0100";
wdat <= x"07";
wait for 1 ns;
pulse;
pulse;
assert rdat = x"07" severity failure;
addr <= "0000";
wen <= '0';
pulse;
assert rdat = x"41" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
b753cc355d666a04bd29fba50deec00f
| 0.567623 | 3.275168 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_intrpt.vhd
| 7 | 28,217 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
gpl-3.0
|
7d0365ccd5f3fb202db2987eda18b38f
| 0.46557 | 4.041392 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd
| 4 | 10,804 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc748.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00748pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
procedure P1(inp : boolean_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out boolean_vector) ;
procedure P2(inp : bit_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out bit_vector) ;
procedure P3(inp : string; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out string);
procedure P4(inp : severity_level_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out severity_level_vector);
procedure P5(inp : integer_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out integer_vector) ;
procedure P6(inp : real_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out real_vector) ;
procedure P7(inp : time_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out time_vector) ;
procedure P8(inp : natural_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out natural_vector) ;
procedure P9(inp : positive_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out positive_vector) ;
procedure P10(inp : array_rec_std; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out array_rec_std) ;
end c01s01b01x01p05n02i00748pkg;
package body c01s01b01x01p05n02i00748pkg is
procedure P1(inp : boolean_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out boolean_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
ot := inp;
end P1;
procedure P2(inp : bit_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out bit_vector) is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
ot := inp;
end P2;
procedure P3(inp : string; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out string) is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
ot := inp;
end P3;
procedure P4(inp : severity_level_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out severity_level_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
ot := inp;
end P4;
procedure P5(inp : integer_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out integer_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
ot := inp;
end P5;
procedure P6(inp : real_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out real_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
ot := inp;
end P6;
procedure P7(inp : time_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out time_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
ot := inp;
end P7;
procedure P8(inp : natural_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out natural_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
ot := inp;
end P8;
procedure P9(inp : positive_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out positive_vector) is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
ot := inp;
end P9;
procedure P10(inp : array_rec_std; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out array_rec_std) is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
ot := inp;
end P10;
end c01s01b01x01p05n02i00748pkg;
use work.c01s01b01x01p05n02i00748pkg.all;
ENTITY c01s01b01x01p05n02i00748ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00748ent;
ARCHITECTURE c01s01b01x01p05n02i00748arch OF c01s01b01x01p05n02i00748ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean_vector(zero to fifteen);
variable var4 : severity_level_vector(zero to fifteen);
variable var5 : integer_vector(zero to fifteen);
variable var6 : real_vector(zero to fifteen);
variable var7 : time_vector(zero to fifteen);
variable var8 : natural_vector(zero to fifteen);
variable var9 : positive_vector(zero to fifteen);
variable var2 : bit_vector(zero to three);
variable var3 : string(one to seven);
variable var48: array_rec_std(zero to seven);
BEGIN
P1(S1,zero,one,three,seven,fifteen,var1);
P2(S9,zero,one,three,seven,fifteen,var2);
P3(S8,zero,one,three,seven,fifteen,var3);
P4(S2,zero,one,three,seven,fifteen,var4);
P5(S3,zero,one,three,seven,fifteen,var5);
P6(S4,zero,one,three,seven,fifteen,var6);
P7(S5,zero,one,three,seven,fifteen,var7);
P8(S6,zero,one,three,seven,fifteen,var8);
P9(S7,zero,one,three,seven,fifteen,var9);
P10(S48,zero,one,three,seven,fifteen,var48);
wait for 1 ns;
assert(var1(0) = true) report"wrong assignment of S1" severity error;
assert(var2(0) = '0') report"wrong assignment of S2" severity error;
assert(var3(1) = 's') report"wrong assignment of S3" severity error;
assert(var4(0) = note) report"wrong assignment of S4" severity error;
assert(var5(0) = 3) report"wrong assignment of S5" severity error;
assert(var6(0) = 3.0) report"wrong assignment of S6" severity error;
assert(var7(0) = 3 ns) report"wrong assignment of S7" severity error;
assert(var8(0) = 1) report"wrong assignment of S8" severity error;
assert(var9(0) = 1) report"wrong assignment of S9" severity error;
assert(var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong assignment of S10" severity error;
assert NOT( (var1(0) = true) and
(var2(0) = '0') and
(var3(1) = 's') and
(var4(0) = note) and
(var5(0) = 3) and
(var6(0) = 3.0) and
(var7(0) = 3 ns) and
(var8(0) = 1) and
(var9(0) = 1) and
(var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) )
report "***PASSED TEST: c01s01b01x01p05n02i00748"
severity NOTE;
assert ( (var1(0) = true) and
(var2(0) = '0') and
(var3(1) = 's') and
(var4(0) = note) and
(var5(0) = 3) and
(var6(0) = 3.0) and
(var7(0) = 3 ns) and
(var8(0) = 1) and
(var9(0) = 1) and
(var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) )
report "***FAILED TEST: c01s01b01x01p05n02i00748 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00748arch;
|
gpl-2.0
|
1dcdbc619d90811302b1e7423d7dda25
| 0.606072 | 3.231828 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug0104/alt2.vhdl
| 1 | 1,687 |
library ieee;
use ieee.std_logic_1164.all;
entity delay is
port (
clk : in std_logic;
reset: in std_logic;
start: in std_logic;
done: out std_logic
);
end entity delay;
architecture fast of delay is -- The reader is unenlightened as to fast/slow
begin
end architecture fast;
architecture slow of delay is
begin
end architecture slow;
library ieee;
use ieee.std_logic_1164.all;
entity dut is
generic (
SPEED : string := "fast"
);
port(
clk : in std_logic;
reset: in std_logic;
start: in std_logic;
done: out std_logic);
end entity dut;
architecture dutarch of dut is
-- component delay is -- component declaration not needed or used here.
-- port (
-- clk : in std_logic;
-- reset: in std_logic;
-- start: in std_logic;
-- done: out std_logic
-- );
-- end component delay;
begin
d1g:
if l1: SPEED = "fast" generate
d1: -- The alternative labels, if any, within an if generate statement or a
-- case generate statement shall all be distinct. 11.8 Generate statements
entity work.delay(fast)
port map (
clk => clk,
reset => reset,
start => start,
done => done
);
else l1: generate
d1: -- This isn't a distinct label in the else alternative
entity work.delay(slow)
port map (
clk => clk,
reset => reset,
start => start,
done => done
);
end generate;
end architecture dutarch;
|
gpl-2.0
|
e45360fb5393ed5c081553a0db58d8ae
| 0.541197 | 4.09466 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1021/tb_test.vhdl
| 1 | 2,386 |
entity tb_test is
generic(
ROW_BITS : integer := 4;
WIDTH : integer := 64
);
end tb_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test is
signal clk : std_logic;
signal rd_addr : std_logic_vector(ROW_BITS - 1 downto 0);
signal rd_data : std_logic_vector(WIDTH - 1 downto 0);
signal wr_en : std_logic;
signal wr_sel : std_logic_vector(WIDTH/8 - 1 downto 0);
signal wr_addr : std_logic_vector(ROW_BITS - 1 downto 0);
signal wr_data : std_logic_vector(WIDTH - 1 downto 0);
begin
dut: entity work.test
generic map (
ROW_BITS => ROW_BITS,
WIDTH => WIDTH)
port map (
clk => clk,
rd_addr => rd_addr,
rd_data => rd_data,
wr_en => wr_en,
wr_sel => wr_sel,
wr_addr => wr_addr,
wr_data => wr_data);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rd_addr <= x"0";
wr_addr <= x"0";
wr_data <= x"01_23_45_67_89_ab_cd_ef";
wr_sel <= x"ff";
wr_en <= '1';
pulse;
-- Simple read.
rd_addr <= x"0";
-- And write at a different address.
wr_addr <= x"1";
wr_data <= x"ff_ee_dd_cc_bb_aa_99_88";
wr_en <= '1';
wr_sel <= x"ff";
pulse;
assert rd_data = x"01_23_45_67_89_ab_cd_ef" severity failure;
rd_addr <= x"1";
-- Partial write
wr_addr <= x"0";
wr_data <= x"00_ee_00_00_00_00_00_00";
wr_sel <= x"40";
pulse;
assert rd_data = x"ff_ee_dd_cc_bb_aa_99_88" severity failure;
-- Check result.
rd_addr <= x"0";
wr_en <= '0';
pulse;
assert rd_data = x"01_ee_45_67_89_ab_cd_ef" severity failure;
-- Check that read is synchronous with clock.
rd_addr <= x"1";
assert rd_data = x"01_ee_45_67_89_ab_cd_ef" severity failure;
-- Check that read occurs before write.
wr_addr <= x"1";
wr_data <= x"f0_00_00_00_00_00_00_00";
wr_sel <= x"80";
rd_addr <= x"1";
wr_en <= '1';
pulse;
assert rd_data = x"ff_ee_dd_cc_bb_aa_99_88" severity failure;
wr_en <= '0';
wr_data <= x"00_00_00_00_00_00_00_00";
wr_sel <= x"ff";
pulse;
assert rd_data = x"f0_ee_dd_cc_bb_aa_99_88" severity failure;
pulse;
assert rd_data = x"f0_ee_dd_cc_bb_aa_99_88" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
2084ddb9bd0f2511e21ebfb64a0dcad3
| 0.547779 | 2.745685 | false | false | false | false |
nickg/nvc
|
test/parse/external.vhd
| 1 | 710 |
entity external is
end entity;
architecture test of external is
begin
main: process is
variable i : integer;
begin
i := <<signal foo.bar : integer>>; -- OK
i := << constant x.y.z : integer >>; -- OK
i := <<variable aye.bee : integer>>; -- OK
i := << constant .x.y.z : integer>>; -- OK
i := << constant ^.^.foo : integer >>; -- OK
i := << constant @work.pack.foo : integer >>; -- OK
i := << signal g(0).x(1).baz : integer >>; -- OK
end process;
p2: process is
alias sig is <<signal i_test.sig : bit_vector(1 downto 0)>>;
begin
sig(0) <= '1'; -- OK
end process;
end architecture;
|
gpl-3.0
|
4f3cb52df2bd8748b95c0b8686d2c056
| 0.495775 | 3.567839 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd
| 4 | 1,838 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity addu is
end entity addu;
architecture test of addu is
subtype word32 is bit_vector(31 downto 0);
-- code in book
procedure addu ( a, b : in word32;
result : out word32; overflow : out boolean ) is
variable sum : word32;
variable carry : bit := '0';
begin
for index in sum'reverse_range loop
sum(index) := a(index) xor b(index) xor carry;
carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) );
end loop;
result := sum;
overflow := carry = '1';
end procedure addu;
-- end code in book
begin
stimulus : process is
-- code in book (in text)
variable PC, next_PC : word32;
variable overflow_flag : boolean;
-- . . .
-- end code in book
begin
PC := X"0000_0010";
-- code in book (in text)
addu ( PC, X"0000_0004", next_PC, overflow_flag);
-- end code in book
PC := X"FFFF_FFFC";
addu ( PC, X"0000_0004", next_PC, overflow_flag);
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
ce2bac4fb6fc03475f896cf13723758e
| 0.656692 | 3.797521 | false | false | false | false |
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