repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
tgingold/ghdl
|
testsuite/gna/issue707/ent.vhdl
| 1 | 442 |
entity ent is
end entity;
architecture a of ent is
subtype my_low_rng is integer range 0 to 1;
subtype my_high_rng is integer range 2 to 3;
-- constant my_good_booleans : boolean_vector(0 to 3) :=
-- (0 to 1 => true, 2 to 3 => false);
constant my_bad_booleans : boolean_vector(0 to 3) :=
(my_low_rng => true, my_high_rng => false);
begin
process begin
report "Hello world" severity note;
wait;
end process;
end;
|
gpl-2.0
|
524d6a44b9a1129e5be4325ad6ec2bd3
| 0.653846 | 3.090909 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd
| 4 | 2,295 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1139.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01139ent IS
END c06s05b00x00p05n02i01139ent;
ARCHITECTURE c06s05b00x00p05n02i01139arch OF c06s05b00x00p05n02i01139ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ABASE is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is ABASE(ENUM1 range M1 to M5);
function F(i : integer) return ENUM1 is
begin
return M2;
end F;
function G(j : integer) return ENUM1 is
begin
return M4;
end G;
variable ii : integer;
variable jj : integer;
variable V1 : A1 ; -- := (others=>TRUE);
variable V4 : A1 ; -- := (others=>TRUE);
variable V2, V3: ENUM1;
BEGIN
V1(M1 to M3) := V1(F(ii) to G(jj));
assert NOT(V1(M1 to M3)=(false,false,false))
report "***PASSED TEST: c06s05b00x00p05n02i01139"
severity NOTE;
assert (V1(M1 to M3)=(false,false,false))
report "***FAILED TEST: c06s05b00x00p05n02i01139 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01139arch;
|
gpl-2.0
|
063fefe025b38e3cd44602cfaa0101a1
| 0.657081 | 3.525346 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd
| 4 | 2,022 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p09n03i00343ent IS
END c03s02b01x00p09n03i00343ent;
ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS
type M1 is array (1 to 4) of BIT;
signal X1 : M1;
BEGIN
TESTING: PROCESS
BEGIN
X1(1) <= '0' after 10 ns;
X1(2) <= '1' after 20 ns;
X1(3) <= '1' after 30 ns;
X1(4) <= '0' after 40 ns; -- No_failure_here
wait for 50 ns;
assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***PASSED TEST: c03s02b01x00p09n03i00343"
severity NOTE;
assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p09n03i00343arch;
|
gpl-2.0
|
6b97ce9040705af5de9dbe3a88f004e1
| 0.650841 | 3.358804 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/issue202/repro_err.vhdl
| 2 | 1,215 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
entity e is
end entity;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Meta : std_logic_vector(31 downto 0);
Data : T_DATA_VECTOR(15 downto 0);
end record;
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is
begin
return TRUE;
end function;
function to_string(vector : T_SCOREBOARD_DATA) return string is
begin
return "to_string";
end function;
package P_Scoreboard is new OSVVM.ScoreboardGenericPkg
generic map (
ExpectedType => T_SCOREBOARD_DATA,
ActualType => T_SCOREBOARD_DATA,
Match => match,
expected_to_string => to_string,
actual_to_string => to_string
);
alias T_SCOREBOARD is P_Scoreboard.ScoreBoardPType
shared variable ScoreBoard : T_SCOREBOARD; -- this causes the error message
begin
process
variable v : t_scoreboard_data;
begin
ScoreBoard.Push(v);
wait;
end process;
end architecture;
|
gpl-2.0
|
5a6a0d13ef01e6c47596a3a4344829c7
| 0.669136 | 3.693009 | false | false | false | false |
nickg/nvc
|
test/regress/wait15.vhd
| 1 | 598 |
entity wait15 is
end entity;
architecture test of wait15 is
type wait_spec_t is record
delay : delay_length;
end record;
type wait_array_t is array (natural range <>) of wait_spec_t;
constant wait_list : wait_array_t := ( (delay => 1 ns),
(delay => 2 ns),
(delay => 5 us ) );
begin
process is
begin
for w in wait_list'range loop
wait for wait_list(w).delay;
end loop;
assert now = 5003 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
adfa1e87c6f6db1b9ab6883c6a1de7a0
| 0.506689 | 4.181818 | false | false | false | false |
lfmunoz/vhdl
|
templates/simulation/fmc160_model/i2c_slave_model.vhd
| 2 | 11,933 |
--------------------------------------------------------------------/
---- ----
---- WISHBONE rev.B2 compliant synthesizable I2C Slave model ----
---- ----
---- ----
---- Authors: Richard Herveille ([email protected]) www.asics.ws ----
---- John Sheahan ([email protected]) ----
---- ----
---- Downloaded from: http:--www.opencores.org/projects/i2c/ ----
---- ----
--------------------------------------------------------------------/
---- ----
---- Copyright (C) 2001,2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
--------------------------------------------------------------------/
-- CVS Log
--
-- $Id: i2c_slave_model.v,v 1.6 2005/02/28 11:33:48 rherveille Exp $
--
-- $Date: 2005/02/28 11:33:48 $
-- $Revision: 1.6 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_slave_model.v,v $
-- Revision 1.6 2005/02/28 11:33:48 rherveille
-- Fixed Tsu:sta timing check.
-- Added Thd:sta timing check.
--
-- Revision 1.5 2003/12/05 11:05:19 rherveille
-- Fixed slave address MSB='1' bug
--
-- Revision 1.4 2003/09/11 08:25:37 rherveille
-- Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
--
-- Revision 1.3 2002/10/30 18:11:06 rherveille
-- Added timing tests to i2c_model.
-- Updated testbench.
--
-- Revision 1.2 2002/03/17 10:26:38 rherveille
-- Fixed some race conditions in the i2c-slave model.
-- Added debug information.
-- Added headers.
--
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
entity i2c_slave_model is
generic (
I2C_ADR : std_logic_vector(6 downto 0) := "1010111"
);
port (
scl : in std_logic;
sda : inout std_logic
);
end i2c_slave_model;
architecture syn of i2c_slave_model is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant debug :std_logic := '1';
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
type std_2d is array(natural range <>) of std_logic_vector(7 downto 0);
type i2s_slave_sm_type is (idle, slave_ack, get_mem_adr, gma_ack, data, data_ack);
signal state :i2s_slave_sm_type:=idle;
signal mem :std_2d(15 downto 0);
signal mem_adr :std_logic_vector(7 downto 0);
signal mem_do :std_logic_vector(7 downto 0);
signal sr :std_logic_vector(7 downto 0);
signal bit_cnt :std_logic_vector(2 downto 0);
signal sta : std_logic;
signal d_sta : std_logic;
signal sto : std_logic;
signal d_sto :std_logic;
signal i2c_reset :std_logic;
signal sda_o :std_logic:='1';
signal sda_dly :std_logic;
signal ld : std_logic;
signal acc_done :std_logic;
signal my_adr :std_logic;
signal rw :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
shift_reg: process(scl)
begin
if( scl'event and (scl = '1' or scl = 'H')) then
if (sda = '1' or sda = 'H') then
sr <= sr(6 downto 0) & '1' after 1 ns;
else
sr <= sr(6 downto 0) & '0' after 1 ns;
end if;
if (ld = '1') then
bit_cnt <= (others =>'1') after 1 ns;
else
bit_cnt <= bit_cnt - 1 after 1 ns;
end if;
end if;
end process;
detct_proc: process(sda, scl)
begin
if( sda'event and sda = '0' ) then
if(scl = '1' or scl = 'H') then
sta <= '1' after 1 ns;
d_sta <= '0' after 1 ns;
sto <= '0' after 1 ns;
if(debug = '1') then
report("DEBUG i2c_slave; start condition detected ");
end if;
else
sta <= '0' after 1 ns;
end if;
elsif( sda'event and (sda = '1' or sda = 'H')) then
if(scl = '1' or scl = 'H') then
sta <= '0' after 1 ns;
sto <= '1' after 1 ns;
if(debug = '1') then
report("DEBUG i2c_slave; stop condition detected");
end if;
else
sto <= '0' after 1 ns;
end if;
elsif ( scl'event and (scl = '1' or scl = 'H')) then
d_sta <= sta after 1 ns;
end if;
end process;
sm_proc: process(scl, sto)
variable rw_var :std_logic;
begin
if( (scl'event and scl = '0') or (sto'event and sto = '0')) then
if (sto = '1' or( sta = '1' and d_sta= '0')) then
state <= idle after 1 ns;
sda_o <= '1' after 1 ns;
ld <= '1' after 1 ns;
else
sda_o <= '1' after 1 ns;
ld <= '0' after 1 ns;
case state is
when idle =>
if(acc_done = '1' and my_adr= '1') then
state <= slave_ack after 1 ns;
rw <= sr(0) after 1 ns;
rw_var := sr(0);
sda_o <= '0' after 1 ns;
if (debug = '1' and sr(0) = '1') then
report("DEBUG i2c_slave; command byte received (read)" );
elsif (debug = '1' and sr(0) = '0') then
report("DEBUG i2c_slave; command byte received (write)" );
end if;
if (rw_var = '1') then
mem_do <= mem(conv_integer(mem_adr)) after 1 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block read from address ");
end if;
end if;
end if;
when slave_ack =>
if (rw = '1') then
state <= data after 1 ns;
sda_o <= mem_do(7) after 1 ns;
else
state <= get_mem_adr after 1 ns;
ld <= '1' after 1 ns;
end if;
when get_mem_adr =>
if (acc_done = '1') then
state <= gma_ack after 1 ns;
mem_adr <= sr after 1 ns;
if (sr <= conv_std_logic_vector(15,7)) then
sda_o <= '0' after 1 ns;
else
sda_o <= '1' after 1 ns;
end if;
if (debug = '1') then
report ("DEBUG i2c_slave; address received. ");
end if;
end if;
when gma_ack =>
state <= data after 1 ns;
ld <= '1' after 1 ns;
when data =>
if(rw = '1') then
sda_o <= mem_do(7) after 1 ns;
end if;
if(acc_done = '1') then
state <= data_ack after 1 ns;
mem_adr <= mem_adr + 1 after 2 ns;
if (rw= '1'and mem_adr <= conv_std_logic_vector(15,7)) then
sda_o <= '1' after 3 ns;
else
sda_o <= '0' after 1 ns;
end if;
if(rw= '1') then
mem_do <= mem(conv_integer(mem_adr)) after 3 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block read");
end if;
end if;
if (rw= '0') then
mem(conv_integer(mem_adr)) <= sr after 1 ns;
if (debug = '1') then
report ("DEBUG i2c_slave; data block write ");
end if;
end if;
end if;
when data_ack =>
ld <= '1' after 1 ns;
if (rw= '1') then
if (sda = '1' or sda = 'H') then
state <= idle after 1 ns;
sda_o <= '1' after 1 ns;
else
state <= data after 1 ns;
sda_o <= mem_do(7) after 1 ns;
end if;
else
state <= data after 1 ns;
sda_o <= '1' after 1 ns;
end if;
end case;
end if;
elsif( scl'event and (scl = '1' or scl = 'H')) then
if (acc_done = '0' and rw = '1') then
mem_do <= mem_do(6 downto 0) & '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
my_adr <= '1' when sr(7 downto 1) = i2c_adr else '0'; --detect if it is our address
acc_done <= not or_reduce(bit_cnt); --generate access done signal
-- generate delayed version of sda
-- this model assumes a hold time for sda after the falling edge of scl.
-- According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
-- with regards to scl. If the data changes coincident with the clock, the
-- acknowledge is missed
-- Fix by Michael Sosnoski
sda_dly <= '1' after 1 ns when sda = '1' or sda = 'H' else '0' after 1 ns;
--generate i2c_reset signal
i2c_reset <= sta or sto;
-- generate tri-states
sda <= '0' when sda_o = '0' else 'Z';
-------------------
-------------------
end syn;
|
mit
|
96a5a180940a74130a788864062172bb
| 0.413475 | 4.046456 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug090/crash7.vhdl
| 1 | 1,732 |
library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component dff is
generic (len : natural := 8);
port (clk : in std_logic;
st_n : in std_logic;
d : std_logic_vector (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end component;
begin
mydff : entity work.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
dff2 : dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
chkr: process (clk)
begin
if rst_n = '0' then
null;
elsif rising_edge (clk) then
assert dout = dout2 report "incoherence" severity failure;
end if;
end process chkr;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start%of tb"(severity note;
for i in din'range loop
din(i) <= '0';
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
|
gpl-2.0
|
4f6fd006fc8dd66ba4b748055e0a2c0d
| 0.572748 | 3.189687 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_queue.vhd
| 7 | 41,099 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
--use axi_sg_v4_1_2.axi_sg_afifo_autord.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
-- Channel Control --
desc1_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
desc2_flush : in std_logic ; --
ftch1_active : in std_logic ; --
ftch2_active : in std_logic ; --
ftch1_queue_empty : out std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch1_queue_full : out std_logic ; --
ftch2_queue_full : out std_logic ; --
ftch1_pause : out std_logic ; --
ftch2_pause : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing1_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
sof_ftch_desc : in std_logic ;
m_axis1_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
--
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_64_cdma : in std_logic_vector --
(31 downto 0) ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
data_concat_tlast : in std_logic ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_aclk : in std_logic ; --
m_axis_ftch1_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch1_tvalid : out std_logic ; --
m_axis_ftch1_tready : in std_logic ; --
m_axis_ftch1_tlast : out std_logic ; --
m_axis_ftch1_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch1_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch1_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
m_axis_ftch2_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch2_tvalid : out std_logic ; --
m_axis_ftch2_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch2_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch2_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
m_axis_ftch2_tready : in std_logic ; --
m_axis_ftch2_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Number of words deep fifo needs to be
-- 6 is subtracted as BD address are always 16 word aligned
constant FIFO_WIDTH : integer := (128*C_ENABLE_CDMA + 97*(1-C_ENABLE_CDMA) -6);
constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2*C_ENABLE_MULTI_CHANNEL;
--constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
-- * C_SG_WORDS_TO_FETCH1));
constant FETCH_QUEUE_DEPTH : integer := 16;
-- Select between BRAM or Logic Memory Type
constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG_WORDS_TO_FETCH1 > 16);
constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1);
constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1;
constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461
constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH;
constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1));
-- Select between BRAM or Logic Memory Type
constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1 > 16);
constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1);
constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1;
constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant DESC2QUEUE_VECT_WIDTH : integer := 4;
--constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
--constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461
constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tvalid_new : std_logic := '0';
signal ftch_tdata : std_logic_vector
(31 downto 0) := (others => '0');
signal ftch_tdata_new, reg1, reg2 : std_logic_vector
(FIFO_WIDTH-1 downto 0) := (others => '0');
signal ftch_tdata_new_64, reg1_64, reg2_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal ftch_tdata_new_bd, reg2_bd_64, reg1_bd_64 : std_logic_vector (31 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tlast_new : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal ftch_tready_ch1 : std_logic := '0';
signal ftch_tready_ch2 : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-- FIFO signals
signal queue_rden2 : std_logic := '0';
signal queue_rden2_new : std_logic := '0';
signal queue_wren2 : std_logic := '0';
signal queue_wren2_new : std_logic := '0';
signal queue_empty2 : std_logic := '0';
signal queue_empty2_new : std_logic := '0';
signal queue_rden : std_logic := '0';
signal queue_rden_new : std_logic := '0';
signal queue_wren : std_logic := '0';
signal queue_wren_new : std_logic := '0';
signal queue_empty : std_logic := '0';
signal queue_empty_new : std_logic := '0';
signal queue_dout_valid : std_logic := '0';
signal queue_dout2_valid : std_logic := '0';
signal queue_full_new : std_logic := '0';
signal queue_full2_new : std_logic := '0';
signal queue_full, queue_full2 : std_logic := '0';
signal queue_din_new : std_logic_vector
(127 downto 0) := (others => '0');
signal queue_dout_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_dout2_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout2_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout2_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout2_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_din : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout2 : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_sinit : std_logic := '0';
signal queue_sinit2 : std_logic := '0';
signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal ftch_no_room : std_logic;
signal ftch_active : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal sof_ftch_desc_del : std_logic;
signal sof_ftch_desc_del1 : std_logic;
signal sof_ftch_desc_pulse : std_logic;
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal xfer_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1'))then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
ftch_active <= ftch1_active or ftch2_active;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
CURRENT_BD_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(32+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_64;
CURRENT_BD_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_32;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
m_axis_ftch1_tdata_mcdma_new <= (others => '0');
m_axis_ftch2_tdata_mcdma_new <= (others => '0');
COUNTER_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
counter <= (others => '0');
elsif (m_axis_mm2s_tvalid = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process COUNTER_PROCESS;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate
begin
CDMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (63 downto 0) <= data_concat_64_cdma & data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate CDMA_FIELDS_64;
ftch_tdata_new (95 downto 0) <= data_concat;
-- BD is always 16 word aligned
ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6);
end generate CDMA_FIELDS;
DMA_FIELDS : if C_ENABLE_CDMA = 0 generate
begin
DMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (31 downto 0) <= data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate DMA_FIELDS_64;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
-- BD is always 16 word aligned
ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6);
end generate DMA_FIELDS;
ftch_tvalid_new <= data_concat_valid and ftch_active;
ftch_tlast_new <= data_concat_tlast and ftch_active;
GEN_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_rden_new = '1') then
queue_empty_new <= '1';
queue_full_new <= '0';
elsif (queue_wren_new = '1') then
queue_empty_new <= '0';
queue_full_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
reg1 <= (others => '0');
reg1_64 <= (others => '0');
reg1_bd_64 <= (others => '0');
elsif (queue_wren_new = '1') then
reg1 <= ftch_tdata_new;
reg1_64 <= ftch_tdata_new_64;
reg1_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
queue_dout_new <= (others => '0');
queue_dout_new_64 <= (others => '0');
queue_dout_new_bd <= (others => '0');
elsif (queue_rden_new = '1') then
queue_dout_new <= reg1;
queue_dout_new_64 <= reg1_64;
queue_dout_new_bd <= reg1_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_dout_valid = '1') then
queue_dout_valid <= '0';
elsif (queue_rden_new = '1') then
queue_dout_valid <= '1';
end if;
end if;
end process;
MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH1_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren_new ,
Rd_en => queue_rden_new ,
Dout => queue_dout_mcdma_new ,
Full => open, --queue_full_new ,
Empty => open, --queue_empty_new ,
Almost_full => open ,
Data_count => open, --queue_dcount_new ,
Rd_ack => open, --queue_dout_valid, --open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new;
end generate MCDMA_MM2S;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate
begin
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_2.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
end generate GEN_MM2S;
GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_rden2_new = '1') then
queue_empty2_new <= '1';
queue_full2_new <= '0';
elsif (queue_wren2_new = '1') then
queue_empty2_new <= '0';
queue_full2_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
reg2 <= (others => '0');
reg2_64 <= (others => '0');
reg2_bd_64 <= (others => '0');
elsif (queue_wren2_new = '1') then
reg2 <= ftch_tdata_new;
reg2_64 <= ftch_tdata_new_64;
reg2_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
queue_dout2_new <= (others => '0');
queue_dout2_new_64 <= (others => '0');
queue_dout2_new_bd <= (others => '0');
elsif (queue_rden2_new = '1') then
queue_dout2_new <= reg2;
queue_dout2_new_64 <= reg2_64;
queue_dout2_new_bd <= reg2_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_dout2_valid = '1') then
queue_dout2_valid <= '0';
elsif (queue_rden2_new = '1') then
queue_dout2_valid <= '1';
end if;
end if;
end process;
MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH2_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit2 ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren2_new ,
Rd_en => queue_rden2_new ,
Dout => queue_dout2_new ,
Full => open, --queue_full2_new ,
Empty => open, --queue_empty2_new ,
Almost_full => open ,
Data_count => queue_dcount2_new ,
Rd_ack => open, --queue_dout2_valid ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new;
end generate MCDMA_S2MM;
end generate GEN_S2MM;
-----------------------------------------------------------------------
-- Internal Side
-----------------------------------------------------------------------
-- Drive tready with fifo not full
ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2;
-- Following is the APP data that goes into APP FIFO
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate
begin
--queue_full_new <= '1' when (queue_dcount_new = "00100") else '0';
queue_sinit <= desc1_flush or not m_axi_sg_aresetn;
ftch_tready_ch1 <= (not queue_full and ftch1_active);
m_axis1_mm2s_tready <= ftch_tready_ch1;
-- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched.
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch1_active;
-- Wr_en of BD FIFO
queue_wren_new <= not queue_full_new
and ftch_tvalid_new
and ftch1_active;
ftch1_queue_empty <= queue_empty_new;
ftch1_queue_full <= queue_full_new;
ftch1_pause <= queue_full_new;
-- RD_en of APP FIFO based on empty and tready
-- RD_EN of BD FIFO based on empty and tready
queue_rden_new <= not queue_empty_new
and m_axis_ftch1_tready;
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle);
-- below signal triggers the fetch of BD in MM2S Mngr
m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
FTCH_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new_bd & queue_dout_new_64 & queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64;
FTCH_FIELDS_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32;
writing1_curdesc_out <= writing_curdesc and ftch1_active;
NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NOCONTROL_STREAM_ASST;
end generate GEN_CH1_CTRL;
GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
ftch_tready_ch1 <= '0';
m_axis1_mm2s_tready <= '0';
-- Write to fifo if it is not full and data is valid
queue_wren <= '0';
ftch1_queue_empty <= '0';
ftch1_queue_full <= '0';
ftch1_pause <= '0';
queue_rden <= '0';
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
writing1_curdesc_out <= '0';
m_axis_ftch1_tdata_new <= (others => '0');
m_axis_ftch1_tvalid_new <= '0';
m_axis_ftch1_desc_available <= '0';
end generate GEN_NO_CH1_CTRL;
GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate
begin
queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn;
ftch_tready_ch2 <= (not queue_full2_new and ftch2_active);
m_axis2_mm2s_tready <= ftch_tready_ch2;
queue_wren2 <= '0';
-- Wr_en for S2MM BD FIFO
queue_wren2_new <= not queue_full2_new
and ftch_tvalid_new
and ftch2_active;
--queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
ftch2_queue_empty <= queue_empty2_new;
ftch2_queue_full <= queue_full2_new;
ftch2_pause <= queue_full2_new;
queue_rden2 <= '0';
-- Rd_en for S2MM BD FIFO
queue_rden2_new <= not queue_empty2_new
and m_axis_ftch2_tready;
m_axis_ftch2_tvalid <= '0';
m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle);
m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
FTCH_FIELDS_64_2 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new_bd & queue_dout2_new_64 & queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64_2;
FTCH_FIELDS_32_2 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32_2;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
end generate GEN_CH2_CTRL;
GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate
begin
ftch_tready_ch2 <= '0';
m_axis2_mm2s_tready <= '0';
queue_wren2 <= '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
--ftch_queue_empty <= queue_empty; CR 621600
ftch2_queue_empty <= '0';
ftch2_queue_full <= '0';
ftch2_pause <= '0';
queue_rden2 <= '0';
m_axis_ftch2_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
m_axis_ftch2_tdata_new <= (others => '0');
m_axis_ftch2_tvalid_new <= '0';
writing2_curdesc_out <= '0';
m_axis_ftch2_desc_available <= '0';
end generate GEN_NO_CH2_CTRL;
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
|
gpl-3.0
|
289ae21becc9cf502952094c5cf9fb52
| 0.476143 | 3.680398 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/func01/func01.vhdl
| 1 | 629 |
library ieee;
use ieee.std_logic_1164.all;
entity func01 is
generic (l : natural := 3);
port (a : std_logic_vector (7 downto 0);
sel : std_logic;
b : out std_logic_vector (7 downto 0));
end func01;
architecture behav of func01 is
function gen_mask (len : natural) return std_logic_vector is
variable res : std_logic_vector (7 downto 0);
begin
res := (others => '0');
res (len downto 0) := (others => '1');
return res;
end gen_mask;
begin
process (a, sel)
begin
if sel = '1' then
b <= a and gen_mask (l);
else
b <= a;
end if;
end process;
end behav;
|
gpl-2.0
|
0e90019deba6652a41c9b4df42828649
| 0.588235 | 3.209184 | false | false | false | false |
nickg/nvc
|
test/regress/driver12.vhd
| 1 | 1,583 |
library ieee;
use ieee.std_logic_1164.all;
package pack is
type rec is record
x : std_logic;
y : std_logic_vector(2 downto 0);
end record;
function init_signals return rec;
end package;
package body pack is
function init_signals return rec is
begin
return (x => 'Z', y => "000");
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( p : inout rec := init_signals );
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of sub is
begin
p1: process is
begin
assert p.x = '0';
assert p.y = "000";
wait for 1 ns;
assert p.x = '1';
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sub2 is
port ( x : out std_logic := '0';
y : in std_logic_vector(2 downto 0) );
end entity;
architecture test of sub2 is
begin
x <= '0', '1' after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity driver12 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of driver12 is
signal s : std_logic;
signal t : std_logic_vector(2 downto 0);
begin
u1: entity work.sub
port map (
p.x => s,
p.y => t );
u2: entity work.sub2
port map (
x => s,
y => t );
end architecture;
|
gpl-3.0
|
7b5c0554f0226b6159fa2d3ab28e2f39
| 0.497789 | 3.842233 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug042/centerconfig_works.vhdl
| 2 | 2,253 |
library ieee;
use ieee.std_logic_1164.all;
entity CenterConfig is
generic (
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
center_height: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
center_width: out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0)
);
end entity CenterConfig;
architecture foo of centerconfig is
begin
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity instance is
-- generic (
-- CENTERHEIGHT: integer := 16;
-- CENTERWIDTH: integer := 16
-- );
end entity;
architecture fum of instance is
constant CENTERHEIGHT: integer := 32; -- 16;
constant CENTERWIDTH: integer := 32; -- 16;
constant C_S_AXI_DATA_WIDTH: integer := 32;
constant C_S_AXI_ADDR_WIDTH: integer := 4;
component centerconfig is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
center_height:
out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
center_width:
out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0)
);
end component;
signal std_center_height: std_logic_vector (CENTERHEIGHT - 1 downto 0);
signal std_center_width: std_logic_vector (CENTERWIDTH - 1 downto 0);
begin
Config:
CenterConfig
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
--center_height(std_center_height'range) => std_center_height,
center_height(std_center_height'LEFT downto
std_center_height'RIGHT) => std_center_height,
-- center_height(C_S_AXI_DATA_WIDTH-1 downto std_center_height'length) => open,
-- not working, not elegant
-- center_width(std_center_width'range) => std_center_width
center_width(std_center_width'LEFT downto
std_center_width'RIGHT) => std_center_width
);
end architecture;
|
gpl-2.0
|
4187ee499567d59239d7dcc1d22e3c0b
| 0.575233 | 3.610577 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/dispout01/tb_rec04.vhdl
| 1 | 489 |
entity tb_rec04 is
end tb_rec04;
library ieee;
use ieee.std_logic_1164.all;
use work.rec04_pkg.all;
architecture behav of tb_rec04 is
signal inp : std_logic;
signal r : myrec;
begin
dut: entity work.rec04
port map (inp => inp, o => r);
process
begin
inp <= '1';
wait for 1 ns;
assert r = (a => "0001", b => '0') severity failure;
inp <= '0';
wait for 1 ns;
assert r = (a => "1000", b => '1') severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
9058846dd5b57552dde1ff6d83dcf82b
| 0.595092 | 3 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue1138/wbcrc_syn.vhdl
| 1 | 1,852 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.all;
--library ghdl_test;
-- use ghdl_test.crc_pkg.all;
use work.crc_pkg.all;
entity wbCrc_syn is
generic( yes_G : std_logic :='1'
; fClkSys_Hz_G : integer := 100e6
; isSimul_G : boolean := false
; wbDataWidth_G : integer := 8
; wbAddrWidth_G : integer := 32
; wbTgaWidth_G : integer := 1
; wbTgcWidth_G : integer := 1
; wbTgdWidth_G : integer := 1
; crcDefault_G : String := "CRC-32/CCITT-FALSE"
);
port( clk_i : in std_ulogic;
rx_is_dat_i : in std_ulogic_vector( wbDataWidth_G - 1 downto 0 );
rx_is_adr_i : in std_ulogic_vector( wbAddrWidth_G - 1 downto 0 );
rx_is_sel_i : in std_ulogic_vector( wbDataWidth_G / 8 - 1 downto 0 );
rx_is_loc_i : in std_ulogic;
rx_is_cyc_i : in std_ulogic;
rx_is_stb_i : in std_ulogic;
rx_is_we_i : in std_ulogic;
rx_os_ack_o : out std_ulogic;
rx_os_stl_o : out std_ulogic;
rx_os_err_o : out std_ulogic;
tx_os_cyc_o : out std_ulogic;
tx_os_stb_o : out std_ulogic;
tx_os_we_o : out std_ulogic;
tx_os_dat_o : out std_ulogic_vector( getCrc32Param( crcDefault_G , 8 ).poly'length - 1 downto 0 );
tx_os_cti_o : out std_ulogic_vector(2 downto 0) ;
tx_os_sel_o : out std_ulogic_vector( wbDataWidth_G / 8 - 1 downto 0 );
tx_os_loc_o : out std_ulogic;
tx_is_ack_i : in std_ulogic
);
end wbCrc_syn;
architecture rtl of wbCrc_syn is
begin
end rtl;
|
gpl-2.0
|
ea23e7828c78ee532e9b7af54dd7327c
| 0.49514 | 3.016287 | false | false | false | false |
mistryalok/FPGA
|
Xilinx/ISE/Basics/RSFlipflop/RS.vhd
| 1 | 1,371 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:04:36 04/04/2013
-- Design Name:
-- Module Name: RSFF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RSFF is
Port ( clk : in std_logic;
reset : in std_logic;
set : in std_logic;
R : in std_logic;
S : in std_logic;
Q : out std_logic;
Qn : out std_logic);
end RSFF;
architecture Behavioral of RSFF is
begin
process(clk)
begin
if(set='1')then
Q <= '1';
Qn <= '0';
elsif (Reset='1') then
Q <= '0';
Qn <= '1';
elsif(clk='1' and clk'event)then
if(S='1') then
Q <= S;
Qn <= not S;
elsif(R='0') then
Q <= R;
Qn <= not R;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f8cdbef228d3da196a30143b77481d88
| 0.487965 | 3.4275 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
| 4 | 5,210 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bus_monitor_pkg is
type stats_type is record
ifetch_freq, write_freq, read_freq : real;
end record stats_type;
component bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end component bus_monitor;
end package bus_monitor_pkg;
use work.bus_monitor_pkg.all;
entity bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end entity bus_monitor;
architecture general_purpose of bus_monitor is
begin
access_monitor : process is
variable access_count, ifetch_count,
write_count, read_count : natural := 0;
use std.textio;
variable L : textio.line;
begin
wait until mem_req = '1';
if ifetch = '1' then
ifetch_count := ifetch_count + 1;
if verbose then
textio.write(L, string'("Ifetch"));
textio.writeline(textio.output, L);
end if;
elsif write = '1' then
write_count := write_count + 1;
if verbose then
textio.write(L, string'("Write"));
textio.writeline(textio.output, L);
end if;
else
read_count := read_count + 1;
if verbose then
textio.write(L, string'("Read"));
textio.writeline(textio.output, L);
end if;
end if;
access_count := access_count + 1;
bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
bus_stats.write_freq <= real(write_count) / real(access_count);
bus_stats.read_freq <= real(read_count) / real(access_count);
if dump_stats and access_count mod 5 = 0 then
textio.write(L, string'("Ifetch frequency = "));
textio.write(L, real(ifetch_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Write frequency = "));
textio.write(L, real(write_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Read frequency = "));
textio.write(L, real(read_count) / real(access_count));
textio.writeline(textio.output, L);
end if;
end process access_monitor;
end architecture general_purpose;
-- code from book (in text)
entity computer_system is
generic ( instrumented : boolean := false );
port ( -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity computer_system;
-- end code from book
-- code from book
architecture block_level of computer_system is
-- . . . -- type and component declarations for cpu and memory, etc.
signal clock : bit; -- the system clock
signal mem_req : bit; -- cpu access request to memory
signal ifetch : bit; -- indicates access is to fetch an instruction
signal write : bit; -- indicates access is a write
-- . . . -- other signal declarations
begin
-- . . . -- component instances for cpu and memory, etc.
instrumentation : if instrumented generate
use work.bus_monitor_pkg;
signal bus_stats : bus_monitor_pkg.stats_type;
begin
cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
port map ( mem_req, ifetch, write, bus_stats );
end generate instrumentation;
-- not in book
stimulus : process is
begin
ifetch <= '1'; write <= '0';
mem_req <= '1', '0' after 10 ns;
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '1';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
wait;
end process stimulus;
-- end not in book
end architecture block_level;
-- end code from book
|
gpl-2.0
|
5fd4750a0f1346e6d3a51749feea5966
| 0.612668 | 3.625609 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd
| 4 | 1,603 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- Voltage Pulse Source (Includes Frequency Domain settings)
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity src_constant is
generic ( level : real := 1.0; -- Constant output value (V)
ac_mag : real := 1.0; -- AC magnitude
ac_phase : real := 0.0 ); -- AC phase (degrees)
port ( quantity output : out real );
end entity src_constant;
architecture ideal of src_constant is
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
begin
if domain = quiescent_domain or domain = time_domain use
output == level;
else
output == ac_spec; -- used for frequency (AC) analysis
end use;
end architecture ideal;
|
gpl-2.0
|
f2f0406bf4585ad30c3720bffe6478c4
| 0.703681 | 3.997506 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1122/repro2.vhdl
| 1 | 357 |
entity repro2 is
port (clk : bit;
rst : bit;
d : bit;
q : out bit);
end repro2;
architecture behav of repro2 is
constant c : bit := '1';
signal s : bit := c;
begin
process (clk)
begin
if rst = '1' then
s <= c;
elsif clk = '1' and clk'event then
s <= d;
end if;
end process;
q <= s;
end behav;
|
gpl-2.0
|
809392e8128a65597a7305213964ccdc
| 0.515406 | 3.131579 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug040/outdata_comp_hpos.vhd
| 2 | 1,476 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity outdata_comp_hpos is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end outdata_comp_hpos;
architecture augh of outdata_comp_hpos is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
|
gpl-2.0
|
4e3e7ce0d2891d6195c9e0f7a75e8339
| 0.672764 | 2.911243 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/axi_to_stellarip/stellarcmd_to_axilite.vhd
| 1 | 11,892 |
-------------------------------------------------------------------------------------
-- FILE NAME : .vhd
-- AUTHOR : Luis F. Munoz
-- COMPANY : 4DSP
-- UNITS : Entity - toplevel_template
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- This entity converts from an AXI-Lite interface to a 4DSP StellarIP Command interface.
--
-- A StellarIP command has the following format
-- [ Command word (4-bits) | Address (28-bits) | Data (32-bits) ]
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
library xil_defaultlib;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity stellarcmd_to_axilite is
port (
rst : in std_logic;
-- axi-lite: global
s_axi_aclk : in std_logic;
-- s_axi_aresetn : in std_logic;
-- axi-lite: write address channel
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- axi-lite: write data channel
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- axi-lite: write response channel
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- axi-lite: read address channel
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- axi-lite: read channel
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- 4DSP StellarIP Command Interface
cmd_clk : out std_logic;
cmd_out : out std_logic_vector(63 downto 0);
cmd_out_val : out std_logic;
cmd_in : in std_logic_vector(63 downto 0);
cmd_in_val : in std_logic
);
end stellarcmd_to_axilite;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of stellarcmd_to_axilite is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal state : BUS_ACCESS_STATES;
--signal rst : std_logic := '1';
signal start : std_logic;
-- write channel
signal s_axi_bresp_i : std_logic_vector(1 downto 0);
signal s_axi_bvalid_i : std_logic;
-- read channel
signal s_axi_rvalid_i : std_logic;
signal s_axi_rresp_i : std_logic_vector(1 downto 0);
signal s_axi_rdata_i : std_logic_vector(31 downto 0);
signal write_ack_reg : std_logic;
signal write_ack : std_logic;
signal read_ack_reg : std_logic;
signal read_ack : std_logic;
signal wr_done : std_logic;
signal rd_done : std_logic;
signal read_data : std_logic_vector(31 downto 0);
signal read_valid : std_logic;
--***********************************************************************************
begin
--***********************************************************************************
cmd_clk <= S_AXI_ACLK;
-- start signal will be used to latch the incoming address
start <= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID)) when (state = SM_IDLE) else
'0';
-------------------------------------------------------------------------------
-- StellarIP Command Out Interface
-------------------------------------------------------------------------------
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if rst = '1' then
cmd_out <= (others=>'0');
cmd_out_val <= '0';
else
if S_AXI_ARVALID = '1' then
cmd_out <= CMD_RD & s_axi_araddr(27 downto 0) & x"00000000";
else
cmd_out <= CMD_WR & S_AXI_AWADDR(27 downto 0) & S_AXI_WDATA(31 downto 0);
end if;
if start = '1' then
cmd_out_val <= '1';
else
cmd_out_val <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- StellarIP Command In Interface
-------------------------------------------------------------------------------
read_valid <= '1' when cmd_in_val = '1' and cmd_in(63 downto 60) = CMD_RD_ACK else
'0';
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if rst = '1' then
read_data <= (others=>'0');
else
if cmd_in_val = '1' then
read_data <= cmd_in(31 downto 0);
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Write Ready
-------------------------------------------------------------------------------
-- Acknowledge the write
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if rst = '1' then
write_ack_reg <= '0';
write_ack <= '0';
else
write_ack_reg <= write_ack;
write_ack <= start and not write_ack_reg;
end if;
end if;
end process;
inst_delay_bit_wr:
entity xil_defaultlib.delay_bit
port map (
clk => S_AXI_ACLK,
rst => rst,
bit_in => write_ack,
bit_out => wr_done
);
-- port connections
s_axi_wready <= wr_done; -- data channel
s_axi_awready <= wr_done; -- address channel
-------------------------------------------------------------------------------
-- Read Ready
-------------------------------------------------------------------------------
-- Acknowledge the read
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if rst = '1' then
read_ack_reg <= '0';
read_ack <= '0';
else
read_ack_reg <= read_ack;
read_ack <= read_valid and not read_ack_reg;
end if;
end if;
end process;
inst_delay_bit_rd:
entity xil_defaultlib.delay_bit
port map (
clk => S_AXI_ACLK,
rst => rst,
bit_in => read_ack,
bit_out => rd_done
);
-- port connections
s_axi_arready <= rd_done; -- address channel
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE =>
if (S_AXI_ARVALID = '1') then -- read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ =>
if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=>
if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP =>
if ((S_AXI_BVALID_I and S_AXI_BREADY) or (S_AXI_RVALID_I and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
when OTHERS =>
state <= SM_IDLE;
end case;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Read Data / Read Response Logic
-------------------------------------------------------------------------------
-- generate the read valid (s_axi_rvalid)
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process;
-- (s_axi_rresp / s_axi_rdata)
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= "00";
s_axi_rdata_i <= read_data;
end if;
end if;
end process;
-- port connections
s_axi_rresp <= s_axi_rresp_i;
s_axi_rdata <= s_axi_rdata_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-------------------------------------------------------------------------------
-- Write Response Logic
-------------------------------------------------------------------------------
-- write response command (s_axi_bresp)
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= "00";
end if;
end if;
end process;
-- write response valid signal (s_axi_bvalid)
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process;
-- port connections
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_BRESP <= s_axi_bresp_i;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
b6b55af71f9bb23fc7c4db105d319d8e
| 0.387824 | 4.18585 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd
| 4 | 9,623 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1010.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c06s03b00x00p10n01i01010pkg IS
--
-- This packages contains declarations of User attributes
--
-- ----------------------------------------------------------------------
--
TYPE RESISTANCE IS RANGE 0 TO 1E9
UNITS
pf;
nf = 1000 pf;
mf = 1000 nf;
END UNITS;
TYPE t_logic IS (
U, D,
Z0, Z1, ZDX, DZX, ZX,
W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
);
--
-- Scalar types Declarations
--
SUBTYPE st_scl1 IS BOOLEAN;
SUBTYPE st_scl2 IS BIT;
SUBTYPE st_scl3 IS CHARACTER;
SUBTYPE st_scl4 IS INTEGER;
SUBTYPE st_scl5 IS REAL;
SUBTYPE st_scl6 IS TIME;
SUBTYPE st_scl7 IS RESISTANCE;
SUBTYPE st_scl8 IS t_logic;
--
-- character string types
--
SUBTYPE st_str1 IS STRING;
SUBTYPE st_str2 IS STRING (1 TO 4);
--
-- Scalar types with a range constraint
--
SUBTYPE cst_scl1 IS BOOLEAN RANGE TRUE TO TRUE;
SUBTYPE cst_scl2 IS BIT RANGE '0' TO '0';
SUBTYPE cst_scl3 IS CHARACTER RANGE 'a' TO 'z';
SUBTYPE cst_scl4 IS INTEGER RANGE 10 DOWNTO 0;
SUBTYPE cst_scl5 IS REAL RANGE 0.0 TO 10.0;
SUBTYPE cst_scl6 IS TIME RANGE 0 fs TO 10 ns;
SUBTYPE cst_scl7 IS RESISTANCE RANGE 0 pf TO 10000 pf;
SUBTYPE cst_scl8 IS t_logic RANGE F0 TO FX;
-- -----------------------------------------------------------------------------------------
-- Attribute Declarations
-- -----------------------------------------------------------------------------------------
--
ATTRIBUTE atr_scl1 : st_scl1;
ATTRIBUTE atr_scl2 : st_scl2;
ATTRIBUTE atr_scl3 : st_scl3;
ATTRIBUTE atr_scl4 : st_scl4;
ATTRIBUTE atr_scl5 : st_scl5;
ATTRIBUTE atr_scl6 : st_scl6;
ATTRIBUTE atr_scl7 : st_scl7;
ATTRIBUTE atr_scl8 : st_scl8;
ATTRIBUTE atr_str1 : st_str1;
ATTRIBUTE atr_str2 : st_str2;
ATTRIBUTE cat_scl1 : cst_scl1;
ATTRIBUTE cat_scl2 : cst_scl2;
ATTRIBUTE cat_scl3 : cst_scl3;
ATTRIBUTE cat_scl4 : cst_scl4;
ATTRIBUTE cat_scl5 : cst_scl5;
ATTRIBUTE cat_scl6 : cst_scl6;
ATTRIBUTE cat_scl7 : cst_scl7;
ATTRIBUTE cat_scl8 : cst_scl8;
END;
USE WORK.c06s03b00x00p10n01i01010pkg.all;
ENTITY c06s03b00x00p10n01i01010ent IS
END c06s03b00x00p10n01i01010ent;
USE WORK.c06s03b00x00p10n01i01010pkg.all;
ENTITY c06s03b00x00p10n01i01010ent_a IS
GENERIC ( gene_1 : cst_scl7;
gene_2 : st_str2 );
PORT ( port_1 : cst_scl7;
port_2 : st_str2 );
--
ATTRIBUTE atr_scl1 OF port_1: SIGNAL IS TRUE;
ATTRIBUTE atr_scl2 OF port_1: SIGNAL IS '0';
ATTRIBUTE atr_scl3 OF port_1: SIGNAL IS 'z';
ATTRIBUTE atr_scl4 OF port_1: SIGNAL IS 0;
ATTRIBUTE atr_scl5 OF port_1: SIGNAL IS 10.0;
ATTRIBUTE atr_scl6 OF port_1: SIGNAL IS 10 ns;
ATTRIBUTE atr_scl7 OF port_1: SIGNAL IS 10000 pf;
ATTRIBUTE atr_scl8 OF port_1: SIGNAL IS FX;
ATTRIBUTE atr_str1 OF port_1: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF port_1: SIGNAL IS "XXXX";
--
ATTRIBUTE cat_scl1 OF port_1: SIGNAL IS TRUE;
--
ATTRIBUTE atr_scl1 OF port_2: SIGNAL IS TRUE;
ATTRIBUTE atr_str1 OF port_2: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF port_2: SIGNAL IS "XXXX";
ATTRIBUTE cat_scl1 OF port_2: SIGNAL IS TRUE;
--
ATTRIBUTE atr_scl1 OF gene_1: CONSTANT IS TRUE;
ATTRIBUTE atr_str1 OF gene_1: CONSTANT IS "signal";
ATTRIBUTE atr_str2 OF gene_1: CONSTANT IS "XXXX";
ATTRIBUTE cat_scl1 OF gene_1: CONSTANT IS TRUE;
--
ATTRIBUTE atr_scl1 OF gene_2: CONSTANT IS TRUE;
ATTRIBUTE atr_str1 OF gene_2: CONSTANT IS "signal";
ATTRIBUTE atr_str2 OF gene_2: CONSTANT IS "XXXX";
ATTRIBUTE cat_scl1 OF gene_2: CONSTANT IS TRUE;
END c06s03b00x00p10n01i01010ent_a;
-----------------------------------------------------------------------
-- ARCHITECTURAL DECLARATION
-----------------------------------------------------------------------
ARCHITECTURE c06s03b00x00p10n01i01010arch_a OF c06s03b00x00p10n01i01010ent_a IS
SIGNAL sign_1 : cst_scl7;
SIGNAL sign_2 : st_str2;
--
ATTRIBUTE atr_scl1 OF sign_1: SIGNAL IS TRUE;
ATTRIBUTE atr_scl2 OF sign_1: SIGNAL IS '0';
ATTRIBUTE atr_scl3 OF sign_1: SIGNAL IS 'z';
ATTRIBUTE atr_scl4 OF sign_1: SIGNAL IS 0;
ATTRIBUTE atr_scl5 OF sign_1: SIGNAL IS 10.0;
ATTRIBUTE atr_scl6 OF sign_1: SIGNAL IS 10 ns;
ATTRIBUTE atr_scl7 OF sign_1: SIGNAL IS 10000 pf;
ATTRIBUTE atr_scl8 OF sign_1: SIGNAL IS FX;
ATTRIBUTE atr_str1 OF sign_1: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF sign_1: SIGNAL IS "XXXX";
--
ATTRIBUTE cat_scl1 OF sign_1: SIGNAL IS TRUE;
--
ATTRIBUTE atr_scl1 OF sign_2: SIGNAL IS TRUE;
ATTRIBUTE atr_str1 OF sign_2: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF sign_2: SIGNAL IS "XXXX";
ATTRIBUTE cat_scl1 OF sign_2: SIGNAL IS TRUE;
--
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( port_1'atr_scl1 = TRUE and
port_1'atr_scl2 = '0' and
port_1'atr_scl3 = 'z' and
port_1'atr_scl4 = 0 and
port_1'atr_scl5 = 10.0 and
port_1'atr_scl6 = 10 ns and
port_1'atr_scl7 = 10000 pf and
port_1'atr_scl8 = FX and
port_1'atr_str1 = "signal" and
port_1'atr_str2 = "XXXX" and
port_1'cat_scl1 = TRUE and
port_2'atr_scl1 = TRUE and
port_2'atr_str1 = "signal" and
port_2'atr_str2 = "XXXX" and
port_2'cat_scl1 = TRUE and
gene_1'atr_scl1 = TRUE and
gene_1'atr_str1 = "signal" and
gene_1'atr_str2 = "XXXX" and
gene_1'cat_scl1 = TRUE and
gene_2'atr_scl1 = TRUE and
gene_2'atr_str1 = "signal" and
gene_2'atr_str2 = "XXXX" and
gene_2'cat_scl1 = TRUE )
report "***PASSED TEST: c06s03b00x00p10n01i01010"
severity NOTE;
assert ( port_1'atr_scl1 = TRUE and
port_1'atr_scl2 = '0' and
port_1'atr_scl3 = 'z' and
port_1'atr_scl4 = 0 and
port_1'atr_scl5 = 10.0 and
port_1'atr_scl6 = 10 ns and
port_1'atr_scl7 = 10000 pf and
port_1'atr_scl8 = FX and
port_1'atr_str1 = "signal" and
port_1'atr_str2 = "XXXX" and
port_1'cat_scl1 = TRUE and
port_2'atr_scl1 = TRUE and
port_2'atr_str1 = "signal" and
port_2'atr_str2 = "XXXX" and
port_2'cat_scl1 = TRUE and
gene_1'atr_scl1 = TRUE and
gene_1'atr_str1 = "signal" and
gene_1'atr_str2 = "XXXX" and
gene_1'cat_scl1 = TRUE and
gene_2'atr_scl1 = TRUE and
gene_2'atr_str1 = "signal" and
gene_2'atr_str2 = "XXXX" and
gene_2'cat_scl1 = TRUE )
report "***FAILED TEST: c06s03b00x00p10n01i01010 - An expanded name denotes an entity, the prefix denotes a construct that is ports, signals and generics."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01010arch_a;
ARCHITECTURE c06s03b00x00p10n01i01010arch OF c06s03b00x00p10n01i01010ent IS
COMPONENT c06s03b00x00p10n01i01010ent_a
GENERIC ( gene_1 : cst_scl7;
gene_2 : st_str2 );
PORT ( port_1 : cst_scl7;
port_2 : st_str2 );
END COMPONENT;
FOR SUB : c06s03b00x00p10n01i01010ent_a USE ENTITY work.c06s03b00x00p10n01i01010ent_a(c06s03b00x00p10n01i01010arch_a);
SIGNAL s1 : cst_scl7;
SIGNAL s2 : st_str2;
BEGIN
SUB : c06s03b00x00p10n01i01010ent_a GENERIC MAP ( 10 pf, "ABCD" )
PORT MAP ( s1, s2 );
END c06s03b00x00p10n01i01010arch;
|
gpl-2.0
|
7e737a675e2a57c1ca4c48bf155904e8
| 0.551907 | 3.269793 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/mem01/tb_dpram3.vhdl
| 1 | 1,045 |
entity tb_dpram3 is
end tb_dpram3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dpram3 is
signal raddr : std_logic_vector(3 downto 0);
signal rdat : std_logic_vector(7 downto 0);
signal waddr : std_logic_vector(3 downto 0);
signal wdat : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
dut: entity work.dpram3
port map (raddr => raddr, rdat => rdat, waddr => waddr, wdat => wdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
raddr <= "0000";
waddr <= x"a";
wdat <= x"5a";
pulse;
raddr <= x"a";
waddr <= x"7";
wdat <= x"87";
pulse;
assert rdat = x"5a" severity failure;
raddr <= x"7";
waddr <= x"1";
wdat <= x"e1";
pulse;
assert rdat = x"87" severity failure;
raddr <= x"1";
waddr <= x"3";
wdat <= x"c3";
pulse;
assert rdat = x"e1" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
bf22dc38001ebf8a9306f8bc92faee87
| 0.564593 | 3.245342 | false | false | false | false |
nickg/nvc
|
test/simp/issue574.vhd
| 1 | 403 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test is
type t_memory_map_array is array (natural range 0 to 10) of natural;
constant C_VER : unsigned(4 downto 0) := "00001";
constant C_MEMORY_MAP_ITEM_DEFAULT : natural := 0;
constant C_MEMORY_MAP_DEFAULT : t_memory_map_array := (
to_integer(C_VER) => 1,
others => C_MEMORY_MAP_ITEM_DEFAULT);
end package;
|
gpl-3.0
|
789a481b967b594f731dfbef06085cf7
| 0.692308 | 3.05303 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/issue1319/ent.vhdl
| 1 | 1,456 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity ent is
port (
insn_i : in std_ulogic_vector(31 downto 0);
ispr1_o : out std_ulogic_vector(5 downto 0);
ispr2_o : out std_ulogic_vector(5 downto 0)
);
end entity ent;
architecture behaviour of ent is
-- SPR numbers
subtype spr_num_t is integer range 0 to 1023;
function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
constant SPR_XER : spr_num_t := 1;
constant SPR_LR : spr_num_t := 8;
constant SPR_CTR : spr_num_t := 9;
-- Extended GPR indice (can hold an SPR)
subtype gspr_index_t is std_ulogic_vector(5 downto 0);
function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
begin
return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
end;
function fast_spr_num(spr: spr_num_t) return gspr_index_t is
variable n : integer range 0 to 31;
begin
case spr is
when SPR_LR =>
n := 0;
when SPR_CTR =>
n:= 1;
when SPR_XER =>
n := 12;
when others =>
n := 0;
return "000000";
end case;
return "1" & std_ulogic_vector(to_unsigned(n, 5));
end;
begin
decode1_1: process(all)
begin
ispr1_o <= fast_spr_num(decode_spr_num(insn_i));
ispr2_o <= fast_spr_num(SPR_XER);
end process;
end architecture behaviour;
|
gpl-2.0
|
04bcd7c013f4446b506ab1bdafc1b8f0
| 0.60783 | 3.097872 | false | false | false | false |
hubertokf/VHDL-Fast-Adders
|
RCA/16bits/RCA/Reg16Bit.vhd
| 5 | 550 |
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Reg16Bit is
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end Reg16Bit;
architecture strc_Reg16Bit of Reg16Bit is
signal Temp: std_logic_vector(15 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
end if;
end process;
valOut <= Temp;
end strc_Reg16Bit;
|
mit
|
83b9a88b0067aa9b3f721f59422d4baa
| 0.687273 | 2.820513 | false | false | false | false |
lfmunoz/vhdl
|
templates/simulation/fmc160_model/cpld/fmc160_cpld.vhd
| 1 | 12,814 |
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity fmc160_cpld is
port (
CLK4MHZ : in std_logic;
I2C_SCL : in std_logic;
I2C_SDA : inout std_logic;
I2C_GA0 : in std_logic;
I2C_GA1 : in std_logic;
PG_C2M : in std_logic;
PG_M2C : out std_logic;
PS_EN : in std_logic;
PS_PG : in std_logic;
CPLD_LED : out std_logic;
REF_EN : out std_logic; --0=OFF/1=ON
REF_SEL : out std_logic; --0=EXT REF/1=INT REF
EXT_CLK_REF_SEL : out std_logic; --0=EXT CLK/1=EXT REF
DAC_CLK_SEL : out std_logic; --0=PLL/1=EXT
ADC_CLK_SEL : out std_logic; --0=PLL/1=DIV
SYNCSRC_SEL0 : out std_logic;
SYNCSRC_SEL1 : out std_logic;
SCLK_PLL : out std_logic;
SDI_PLL : out std_logic;
LE_PLL : out std_logic;
CE_PLL : out std_logic;
PDBRF_PLL : out std_logic;
PLL_MUXOUT : in std_logic;
PLL_LD : in std_logic;
ADC_SCLK : out std_logic;
ADC_SDI : out std_logic;
ADC_SDO : in std_logic;
ADC_CS_L : out std_logic;
ADC_CAL_DLY : out std_logic;
ADC_ND_MODE : out std_logic;
ADC_CAL : out std_logic;
ADC_CAL_RUN : in std_logic;
ADC_I_PD : out std_logic;
ADC_Q_PD : out std_logic;
ADC_TP_MODE : out std_logic;
ADC_DDRPH : out std_logic;
ADC_DES : out std_logic;
ADC_ECE_L : out std_logic;
DAC_SCLK : out std_logic;
DAC_SDIO : inout std_logic;
DAC_CS_L : out std_logic;
DAC_IRQ : in std_logic;
DAC_RESET : out std_logic;
EEPROM_WP : out std_logic;
VM_N_INT : in std_logic;
FRONT_IO_HDMI0 : in std_logic;
FRONT_IO_HDMI1 : in std_logic;
FRONT_IO_HDMI2 : in std_logic;
FRONT_IO_HDMI3 : in std_logic
);
end fmc160_cpld;
architecture fmc160_cpld_syn of fmc160_cpld is
----------------------------------------------------------------------------------------------------
-- Components
----------------------------------------------------------------------------------------------------
component i2cSlave
port (
i2c_address : in std_logic_vector(7 downto 1);
clk : in std_logic;
rst : in std_logic;
sda : inout std_logic;
scl : in std_logic;
regaddr : out std_logic_vector(7 downto 0);
datain : in std_logic_vector(7 downto 0);
writeen : out std_logic;
dataout : out std_logic_vector(7 downto 0)
);
end component;
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_COMMAND : std_logic_vector(7 downto 0) := x"00";
constant ADDR_CONTROL : std_logic_vector(7 downto 0) := x"01";
constant ADDR_VERSION : std_logic_vector(7 downto 0) := x"03";
constant ADDR_I2C_DATA_0 : std_logic_vector(7 downto 0) := x"04";
constant ADDR_I2C_DATA_1 : std_logic_vector(7 downto 0) := x"05";
constant ADDR_I2C_DATA_2 : std_logic_vector(7 downto 0) := x"06";
constant ADDR_I2C_DATA_3 : std_logic_vector(7 downto 0) := x"07";
constant VERSION : std_logic_vector(7 downto 0) := x"2A";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal i2c_address : std_logic_vector(7 downto 1);
signal rst_cnt : integer range 0 to 63 := 0;
signal rst : std_logic := '1';
signal regaddr : std_logic_vector(7 downto 0);
signal datain : std_logic_vector(7 downto 0);
signal writeen : std_logic;
signal dataout : std_logic_vector(7 downto 0);
signal reg_control : std_logic_vector(7 downto 0);
signal spi_dval : std_logic;
signal spi_data : std_logic_vector(31 downto 0);
signal clk_dval : std_logic;
signal adc_dval : std_logic;
signal dac_dval : std_logic;
signal shift : std_logic_vector(31 downto 0);
signal clk_cnt : integer range 0 to 3;
signal ser_cnt : integer range 0 to 33;
signal spi_sclk : std_logic;
signal spi_sdo : std_logic;
signal spi_rw : std_logic; -- 0=Write, 1=Read
signal hiz : std_logic;
begin
----------------------------------------------------------------------------------------------------
-- Set slave address
----------------------------------------------------------------------------------------------------
i2c_address <= "01111" & i2c_ga1 & i2c_ga0;
--i2c_address <= "01111" & '0' & '0'; --i2c_ga1 & i2c_ga0;
----------------------------------------------------------------------------------------------------
-- Reset logic
----------------------------------------------------------------------------------------------------
process (clk4mhz)
begin
if (rising_edge(clk4mhz)) then
if (rst_cnt < 63) then
rst_cnt <= rst_cnt + 1;
rst <= '1';
else
rst_cnt <= rst_cnt;
rst <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- I2C Salve control
----------------------------------------------------------------------------------------------------
i2cSlave_inst : i2cSlave
port map (
i2c_address => i2c_address,
clk => clk4mhz,
rst => rst,
sda => i2c_sda,
scl => i2c_scl,
regaddr => regaddr,
datain => datain,
writeen => writeen,
dataout => dataout
);
----------------------------------------------------------------------------------------------------
-- Write Registers
----------------------------------------------------------------------------------------------------
process (rst, clk4mhz)
begin
if (rst = '1') then
reg_control <= "00000000";
clk_dval <= '0';
adc_dval <= '0';
dac_dval <= '0';
spi_dval <= '0';
spi_data <= (others => '0');
elsif (rising_edge(clk4mhz)) then
-- Command register
if (writeen = '1' and regaddr = ADDR_COMMAND) then
clk_dval <= dataout(0);
adc_dval <= dataout(1);
dac_dval <= dataout(2);
spi_dval <= or_reduce(dataout(2 downto 0));
else
spi_dval <= '0';
end if;
-- Control register
if (writeen = '1' and regaddr = ADDR_CONTROL) then
reg_control <= dataout;
end if;
-- SPI register LSB
if (writeen = '1' and regaddr = ADDR_I2C_DATA_0) then
spi_data( 7 downto 0) <= dataout;
end if;
-- SPI register 2nd byte
if (writeen = '1' and regaddr = ADDR_I2C_DATA_1) then
spi_data(15 downto 8) <= dataout;
end if;
-- SPI register 3rd byte
if (writeen = '1' and regaddr = ADDR_I2C_DATA_2) then
spi_data(23 downto 16) <= dataout;
end if;
-- SPI register MSB
if (writeen = '1' and regaddr = ADDR_I2C_DATA_3) then
spi_data(31 downto 24) <= dataout;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Read Registers
----------------------------------------------------------------------------------------------------
datain <=
reg_control when regaddr = ADDR_CONTROL else
VERSION when regaddr = ADDR_VERSION else
shift( 7 downto 0) when regaddr = ADDR_I2C_DATA_0 else
shift(15 downto 8) when regaddr = ADDR_I2C_DATA_1 else
(others => '0');
----------------------------------------------------------------------------------------------------
-- Program SPI configurations
----------------------------------------------------------------------------------------------------
process (rst, clk4mhz)
begin
if (rst = '1') then
clk_cnt <= 0;
ser_cnt <= 0;
LE_PLL <= '1';
ADC_CS_L <= '1';
DAC_CS_L <= '1';
spi_sclk <= '0';
shift <= (others => '0');
spi_rw <= '0';
hiz <= '0';
elsif (rising_edge(clk4mhz)) then
if (spi_dval = '1' or clk_cnt = 3) then
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end if;
if (spi_dval = '1' and clk_dval = '1') then
ser_cnt <= 32+1;
elsif (spi_dval = '1' and adc_dval = '1') then
ser_cnt <= 24+1;
elsif (spi_dval = '1' and dac_dval = '1') then
ser_cnt <= 16+1;
elsif (clk_cnt = 0 and ser_cnt /= 0) then
ser_cnt <= ser_cnt - 1;
end if;
if (ser_cnt /= 0) then
LE_PLL <= not clk_dval;
ADC_CS_L <= not adc_dval;
DAC_CS_L <= not dac_dval;
else
LE_PLL <= '1';
ADC_CS_L <= '1';
DAC_CS_L <= '1';
end if;
--Generate SPI Clock
if (ser_cnt /= 0 and clk_cnt = 1) then
spi_sclk <= '1';
elsif (ser_cnt /= 0 and clk_cnt = 3) then
spi_sclk <= '0';
end if;
--Shift register (SDI out, SDO in)
if (spi_dval = '1' and clk_dval = '1') then
shift <= spi_data;
elsif (spi_dval = '1' and adc_dval = '1') then
shift <= spi_data(23 downto 0) & x"00";
elsif (spi_dval = '1' and dac_dval = '1') then
shift <= spi_data(15 downto 0) & x"0000";
elsif (ser_cnt /= 0 and clk_cnt = 3) then
shift <= shift(30 downto 0) & spi_sdo;
end if;
--Determine if the SDO pin need to go Hi-Z during read cycle
if (spi_dval = '1' and dac_dval = '1' and spi_data(15) = '1') then
spi_rw <= '1';
elsif (ser_cnt = 0) then
spi_rw <= '0';
end if;
--Generate control signal that make the SDO pin Hi-Z
--Only DAC uses 3 wire interface (CLK cannot read back, ADC uses 4 wire interface)
if (spi_rw = '1' and ser_cnt = 9 and clk_cnt = 3) then
hiz <= '1';
elsif (spi_rw = '0') then
hiz <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Slave SDO selection
----------------------------------------------------------------------------------------------------
spi_sdo <= ADC_SDO when adc_dval = '1' else DAC_SDIO;
----------------------------------------------------------------------------------------------------
-- Map outputs
-- 0 1
--reg_control(0) INT REF EXT REF
--reg_control(1) INT CLK EXT CLK
--reg_control(2) PLL /1 PLL /2
----------------------------------------------------------------------------------------------------
PG_M2C <= PG_C2M and PS_PG;
CPLD_LED <= PLL_LD;
REF_EN <= not reg_control(0); --0=REF OFF/1=REF ON
REF_SEL <= not reg_control(0); --0=EXT REF/1=INT REF
EXT_CLK_REF_SEL <= reg_control(0); --0=EXT CLK/1=EXT REF
DAC_CLK_SEL <= reg_control(1); --0=PLL/1=EXT
ADC_CLK_SEL <= reg_control(2); --0=PLL/1=DIV
SYNCSRC_SEL0 <= reg_control(3);
SYNCSRC_SEL1 <= reg_control(4);
--
--
EEPROM_WP <= not reg_control(7);
SCLK_PLL <= spi_sclk;
SDI_PLL <= shift(31);
CE_PLL <= '1'; --'0' for power down ADF4351
PDBRF_PLL <= not reg_control(1); --'0' mutes RF output
ADC_SCLK <= spi_sclk;
ADC_SDI <= shift(31);
ADC_CAL_DLY <= '0';
ADC_ND_MODE <= '0'; --0=1:2 mode / 1=1:1 mode
ADC_CAL <= '0'; --OR'd with SPI setting in ECM
ADC_I_PD <= '0'; --OR'd with SPI setting in ECM
ADC_Q_PD <= '0'; --OR'd with SPI setting in ECM
ADC_TP_MODE <= '0'; --Ignored in ECM
ADC_DDRPH <= '0'; --Ignored in ECM
ADC_DES <= '0'; --Ignored in ECM
ADC_ECE_L <= '0'; --Enable ECM
DAC_SCLK <= spi_sclk;
DAC_SDIO <= shift(31) when hiz = '0' else 'Z';
DAC_RESET <= '0';
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc160_cpld_syn;
|
mit
|
f16e9b3ba2e0fe2df80c7f59973c5ed3
| 0.413454 | 3.595398 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd
| 4 | 2,533 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
use work.fg_16_04.all;
-- code from book (in text)
entity tri_state_reg is
port ( d : in resolved_byte;
q : out resolved_byte bus;
clock, out_enable : in bit );
end entity tri_state_reg;
-- end code from book
-- code from book
architecture behavioral of tri_state_reg is
begin
reg_behavior : process (d, clock, out_enable) is
variable stored_byte : byte;
begin
if clock'event and clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
end process reg_behavior;
end architecture behavioral;
-- end code from book
use work.fg_16_04.all;
entity fg_16_05 is
end entity fg_16_05;
architecture test of fg_16_05 is
signal d1, d2, q : resolved_byte := X"00";
signal clk1, clk2, oe1, oe2 : bit := '0';
begin
dut1 : entity work.tri_state_reg(behavioral)
port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
dut2 : entity work.tri_state_reg(behavioral)
port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
stimulus : process is
begin
d1 <= X"11"; clk1 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns; wait for 10 ns;
d2 <= X"21"; clk2 <= '1', '0' after 5 ns; wait for 10 ns;
oe2 <= '1', '0' after 5 ns; wait for 10 ns;
oe1 <= '1', '0' after 5 ns;
oe2 <= '1', '0' after 5 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
1db98f38c49349a044062153b319ce21
| 0.592973 | 3.427605 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd
| 7 | 24,940 |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal ftch_tdata_new_64 : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd (31 downto 0);
ADDR641 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 <= data_concat_64 & current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate ADDR641;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data((C_M_AXI_SG_ADDR_WIDTH-32)+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_2.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
|
gpl-3.0
|
93624fe38a8ba5a085b9a5881ac6adde
| 0.44563 | 4.171266 | false | false | false | false |
nickg/nvc
|
test/regress/issue571.vhd
| 1 | 2,250 |
package pack is
type sl2d_t is array(natural range <>, natural range <>) of bit;
type slv_7_0_t is array(natural range <>) of bit_vector(7 downto 0);
constant size_log2 : integer := 15;
subtype ram_bank_t is slv_7_0_t(0 to (2**size_log2) - 1);
type ram_t is array(0 to 0) of ram_bank_t;
constant ram_init : ram_t :=
( -- 4 banks...
0 => ( -- 32768 bytes per bank...
X"11",X"22",X"33",X"44",X"55",X"66",X"77",X"88",others => X"00"));
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity dpram is
generic (
width : integer;
depth_log2 : integer;
init : sl2d_t := (0 downto 1 => (0 downto 1 => '0')) );
end entity;
architecture test of dpram is
subtype ram_word_t is bit_vector(width-1 downto 0);
type ram_t is array(natural range <>) of ram_word_t;
function ram_init return ram_t is
variable r : ram_t(0 to (2**depth_log2)-1);
begin
r := (others => (others => '0'));
if init'high = r'high then
for i in 0 to r'length-1 loop
for j in 0 to width-1 loop
r(i)(j) := init(i, j);
end loop;
end loop;
end if;
return r;
end function ram_init;
shared variable ram : ram_t(0 to (2**depth_log2)-1) := ram_init;
begin
check: process is
begin
assert ram(0) = X"11";
assert ram(1) = X"22";
assert ram(2) = X"33";
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity issue571 is
end entity;
use work.pack.all;
architecture test of issue571 is
function rambank2sl2d (constant x : ram_bank_t) return sl2d_t is
variable r : sl2d_t(0 to (2**(size_log2))-1, 7 downto 0);
begin
for i in 0 to r'length-1 loop
for j in 0 to 7 loop
r(i,j) := x(i)(j);
end loop;
end loop;
return r;
end function rambank2sl2d;
begin
g: for i in 0 to 0 generate
u: entity work.dpram
generic map (
width => 8,
depth_log2 => size_log2,
init => rambank2sl2d(ram_init(i)) );
end generate;
end architecture;
|
gpl-3.0
|
d5f33940eed2875b0377736a74617a84
| 0.517333 | 3.29429 | false | false | false | false |
nickg/nvc
|
test/regress/bounds22.vhd
| 1 | 1,848 |
package pack is
type int_vector is array (natural range <>) of natural;
function spread_ints (x : integer) return int_vector;
end package;
package body pack is
function spread_ints (x : integer) return int_vector is
variable r : int_vector(1 to 6);
begin
for i in r'range loop
r(i) := x;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( o1 : out int_vector(1 to 5);
i1 : in integer;
i2 : in int_vector(1 to 5) );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = 0;
assert i2 = (1 to 5 => 0);
o1 <= (1, 2, 3, 4, 5);
wait for 1 ns;
assert i1 = 150;
assert i2 = (1 to 5 => 42);
o1(1) <= 10;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity bounds22 is
end entity;
use work.pack.all;
architecture test of bounds22 is
signal x : integer;
signal y : int_vector(1 to 5);
signal q : natural;
function sum_ints(v : in int_vector) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
begin
uut: entity work.sub
port map ( sum_ints(o1) => x,
i1 => sum_ints(y),
i2 => spread_ints(q) ); -- Error
p2: process is
begin
assert x = 0;
y <= (10, 20, 30, 40, 50);
q <= 42;
wait for 1 ns;
assert x = 15;
wait for 1 ns;
assert x = 24;
wait;
end process;
end architecture;
|
gpl-3.0
|
462b559a05aca44d65d34f58128426e8
| 0.482143 | 3.802469 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1324/st.vhdl
| 1 | 449 |
entity st is
end;
architecture behav of st is
shared variable cnt : natural := 2;
impure function f return natural is
begin
cnt := cnt + 1;
return cnt;
end f;
signal s1, s2, s3 : bit_vector (1 to f) := (others => '0');
begin
assert false report "s1'length=" & natural'image (s1'length);
assert false report "s2'length=" & natural'image (s2'length);
assert false report "s3'length=" & natural'image (s3'length);
end behav;
|
gpl-2.0
|
f986eb12f14819a7f5f288aadede3d9a
| 0.659243 | 3.230216 | false | false | false | false |
nickg/nvc
|
test/regress/force1.vhd
| 1 | 738 |
entity force1 is
end entity;
architecture test of force1 is
signal s : natural;
begin
p1: s <= 1 after 1 ns, 2 after 2 ns, 3 after 3 ns, 4 after 4 ns;
p2: process is
begin
assert s = 0;
wait for 1 ns;
assert s = 1;
assert s'active;
s <= force 42;
assert s = 1;
wait for 0 ns;
assert s'active;
assert s'event;
assert s = 42;
wait for 0 ns;
assert not s'active;
wait for 2 ns;
assert s = 42;
s <= release;
assert s = 42;
wait for 0 ns;
assert s'active;
assert s = 3;
wait for 0 ns;
assert not s'active;
wait;
end process;
end architecture;
|
gpl-3.0
|
3030edf3234201fb487ab4d4e49f18fa
| 0.501355 | 3.727273 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd
| 4 | 2,104 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc498.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00498ent IS
END c03s02b02x00p02n01i00498ent;
ARCHITECTURE c03s02b02x00p02n01i00498arch OF c03s02b02x00p02n01i00498ent IS
type Month_name is (jan, dec);
type Date is
record
Day : integer range 1 to 31;
Month : Month_name;
Year : integer range 0 to 4000;
end record;
BEGIN
TESTING: PROCESS
variable k : Date;
BEGIN
k.Day := 16;
k.Month := jan;
k.Year := 1993;
assert NOT(k.Day=16 and k.Month=jan and k.Year =1993)
report "***PASSED TEST: c03s02b02x00p02n01i00498"
severity NOTE;
assert (k.Day=16 and k.Month=jan and k.Year =1993)
report "***FAILED TEST: c03s02b02x00p02n01i00498 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00498arch;
|
gpl-2.0
|
d7c69d21fb88deb963d104e0fef2bec4
| 0.661122 | 3.621343 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/bug019/PoC/src/common/debug.vhdl
| 4 | 3,177 |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Debug helper functions.
--
-- Description:
-- ------------------------------------
-- This file declares a debug helper function to export enum encodings as a
-- ChipScope readable token file (*.tok).
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
use STD.TextIO.all;
library PoC;
use PoC.strings.all;
package debug is
impure function dbg_ExportEncoding(Name : STRING; encodings : string; tokenFileName : STRING) return BOOLEAN;
end package;
package body debug is
impure function dbg_ExportEncoding(Name : STRING; encodings : string; tokenFileName : STRING) return BOOLEAN is
file tokenFile : TEXT open WRITE_MODE is tokenFileName;
variable cnt, base : integer;
variable l : line;
begin
report "Exporting encoding of '" & Name & "' to '" & tokenFileName & "'..." severity note;
report "dbg_ExportEncoding: '" & encodings & "'" severity note;
-- write file header
write(l, STRING'("# Encoding file for '" & Name & "'")); writeline(tokenFile, l);
write(l, STRING'("#")); writeline(tokenFile, l);
write(l, STRING'("# ChipScope Token File Version")); writeline(tokenFile, l);
write(l, STRING'("@FILE_VERSION=1.0.0")); writeline(tokenFile, l);
write(l, STRING'("#")); writeline(tokenFile, l);
write(l, STRING'("# Default token value")); writeline(tokenFile, l);
write(l, STRING'("@DEFAULT_TOKEN=")); writeline(tokenFile, l);
write(l, STRING'("#")); writeline(tokenFile, l);
-- write state entires
cnt := 0;
base := encodings'left;
for i in encodings'range loop
if encodings(i) = ';' then
-- Leave the str_trim call in!
-- Otherwise, the new parser of ISE 14.7 fails to slice properly.
write(l, str_trim(encodings(base to i-1)));
write(l, character'('='));
write(l, raw_format_nat_hex(cnt));
writeline(tokenFile, l);
cnt := cnt + 1;
base := i+1;
end if;
end loop;
file_close(tokenFile);
return true;
end function;
end package body;
|
gpl-2.0
|
7ae52300f7a192a7d7b953ffe8153712
| 0.60214 | 3.961347 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1179/bug.vhdl
| 1 | 409 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
port(
m0 : out positive;
m1 : out positive
);
end bug;
architecture behav of bug is
constant A : positive := 4;
constant B : positive := 1100;
constant C : positive := to_integer(A * to_unsigned(B, 11));
constant D : positive := to_integer(to_unsigned(B, 11) * A);
begin
m0 <= c;
m1 <= d;
end architecture;
|
gpl-2.0
|
e715de11ceac13c4dfa89c47f08b282e
| 0.657702 | 2.840278 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
| 4 | 14,843 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control
--
-- Transfer Function:
--
-- pos_t_out = R*sin(theta)
--
-- Where pos_t = output translational position,
-- R = horn radius,
-- theta_in = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity ctl_horn_e is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta_in : electrical; -- input port
terminal pos_t_out : electrical); -- output port
end entity ctl_horn_e;
architecture bhv of ctl_horn_e is
quantity vin across theta_in to electrical_ref;
quantity vout across iout through pos_t_out to electrical_ref;
begin -- bhv
vout == R*sin(vin);
end bhv;
--
-------------------------------------------------------------------------------
-- Rudder Model
--
-- Transfer Function:
--
-- theta_out = arcsin(pos_t_in/R)
--
-- Where pos_t_in = input translational position,
-- R = horn radius,
-- theta_out = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity rudder_horn_e is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos_t_in : electrical; -- input port
terminal theta_out : electrical); -- output port
end entity rudder_horn_e;
architecture bhv of rudder_horn_e is
quantity vin across pos_t_in to electrical_ref;
quantity vout across iout through theta_out to electrical_ref;
begin -- bhv
vout == arcsin(vin/R);
end bhv;
--
-------------------------------------------------------------------------------
-- Integrator
--
-- Transfer Function:
--
-- k
-- H(s) = ---------
-- s
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity integ_1_e is
generic (
k: real := 1.0; -- Gain
init: real := 0.0); -- Initial value of output
port (terminal input: electrical;
terminal output: electrical);
end entity integ_1_e;
architecture simple of integ_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
begin
vin_temp == vin;
IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
vout == init;
ELSE
vout == k*vin_temp'INTEG;
END USE;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lpf_1_e is
generic (
fp : real; -- pole freq
gain : real := 1.0); -- filter gain
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_1_e;
architecture simple of lpf_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant wp : real := math_2_pi*fp;
constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (wp, 1.0);
quantity vin_temp : real;
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_S_Domain is
end TB_CS2_S_Domain;
architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
-- Component declarations
-- Signal declarations
terminal comp_in : electrical;
terminal ctl_horn_out : electrical;
terminal err_limit_in : electrical;
terminal error : electrical;
terminal gear_out : electrical;
terminal integ_out : electrical;
terminal load_trq : electrical;
terminal mtr_fb : electrical;
terminal mtr_gen_trq : electrical;
terminal mtr_in : electrical;
terminal mtr_out : electrical;
terminal pos_fb : electrical;
terminal rudder : electrical;
terminal rudder_in : electrical;
terminal src_in : electrical;
terminal XSIG010043 : electrical;
terminal XSIG010044 : electrical;
terminal XSIG010046 : electrical;
terminal XSIG010050 : electrical;
begin
-- Signal assignments
-- Component instances
v_source : entity work.v_sine(ideal)
generic map(
amplitude => 4.8,
freq => 1.0
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
sum_pos : entity work.sum2_e(simple)
port map(
in1 => src_in,
in2 => pos_fb,
output => error
);
loop_comp : entity work.lead_lag_e(simple)
generic map(
f1 => 5.0,
k => 4000.0,
f2 => 20000.0
)
port map(
input => comp_in,
output => err_limit_in
);
pos_fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => rudder_in,
output => pos_fb
);
mech_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 1.05,
limit_low => -1.05
)
port map(
input => integ_out,
output => rudder_in
);
gear_box_horn : entity work.ctl_horn_e(bhv)
port map(
theta_in => rudder_in,
pos_t_out => ctl_horn_out
);
rudder_horn : entity work.rudder_horn_e(bhv)
port map(
pos_t_in => ctl_horn_out,
theta_out => rudder
);
mtr_Kt : entity work.gain_e(simple)
generic map(
k => 3.43e-3
)
port map(
input => XSIG010044,
output => mtr_gen_trq
);
gear_box : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => mtr_out,
output => gear_out
);
mtr_Ke : entity work.gain_e(simple)
generic map(
k => -3.43e-3
)
port map(
input => mtr_out,
output => mtr_fb
);
sum_mtr_in : entity work.sum2_e(simple)
port map(
in1 => mtr_in,
in2 => mtr_fb,
output => XSIG010043
);
sum_load_trq : entity work.sum2_e(simple)
port map(
in1 => mtr_gen_trq,
in2 => load_trq,
output => XSIG010046
);
integrator : entity work.integ_1_e(simple)
generic map(
k => 1.0
)
port map(
input => gear_out,
output => integ_out
);
rudder_trq : entity work.gain_e(simple)
generic map(
k => -0.2
)
port map(
input => XSIG010050,
output => load_trq
);
trq_fb_gain : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => rudder_in,
output => XSIG010050
);
mtr_elec_pole : entity work.lpf_1_e(simple)
generic map(
gain => 0.4545,
fp => 172.48
)
port map(
input => XSIG010043,
output => XSIG010044
);
mtr_mech_pole : entity work.lpf_1_e(simple)
generic map(
gain => 177.67e3,
fp => 5.33
)
port map(
input => XSIG010046,
output => mtr_out
);
loop_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => comp_in
);
err_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => err_limit_in,
output => mtr_in
);
end TB_CS2_S_Domain;
|
gpl-2.0
|
fbf5d3f74168887c4e5ee6bfca1a6fa1
| 0.548946 | 3.894778 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue715/LRAM.vhdl
| 1 | 2,572 |
-------------------------------------------------------------------------------
--
-- walter d. gallegos
-- www.waltergallegos.com
-- Programmable Logic Consulting
--
-- Este archivo y documentacion son propiedad intelectual de Walter D. Gallegos
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.ALL;
USE STD.TextIO.ALL;
ENTITY LRAM IS
GENERIC ( size : INTEGER := 14; fName : STRING := "IntDemo.mem"; startAdr : INTEGER := 0);
PORT (
CLOCK : IN STD_LOGIC;
WR : IN STD_LOGIC;
BEA : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
DIA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DOA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADRA : IN STD_LOGIC_VECTOR (size-1 DOWNTO 0);
DOB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ADRB : IN STD_LOGIC_VECTOR (size-1 DOWNTO 0)
);
END LRAM;
ARCHITECTURE WDG0 OF LRAM IS
CONSTANT depth : INTEGER := (2**size)-1;
TYPE LocalRAMDesc IS ARRAY (0 TO depth) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
IMPURE FUNCTION Init (fName : STRING) RETURN LocalRAMDesc IS
FILE f : TEXT OPEN READ_MODE IS fName;
VARIABLE l : LINE;
VARIABLE b : STD_LOGIC_VECTOR(31 DOWNTO 0);
VARIABLE m : LocalRAMDesc := (OTHERS => (OTHERS => '0'));
BEGIN
FOR i IN startAdr TO depth LOOP
EXIT WHEN endfile(f);
IF (i = depth) THEN
REPORT "LRAM : Error memory full " SEVERITY FAILURE;
END IF;
readline(f, l); hread(l, b);
m(i) := STD_LOGIC_VECTOR(RESIZE(UNSIGNED(b), 32));
END LOOP;
REPORT ("LRAM : loaded from " & fName & LF) SEVERITY NOTE;
RETURN m;
END FUNCTION;
SIGNAL LocalRAM : LocalRAMDesc := Init(fName);
SIGNAL data, code : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- XILINX ATTRIBUTE
ATTRIBUTE ram_style : STRING;
ATTRIBUTE ram_style OF LocalRAM : SIGNAL IS "block";
-- XILINX END ATTRIBUTE
BEGIN
CodeDataMemory : PROCESS(CLOCK)
BEGIN
IF rising_edge(CLOCK) THEN
FOR i IN DIA'RANGE LOOP
IF (BEA(i/8) AND WR)= '1' THEN
LocalRAM(TO_INTEGER(UNSIGNED(ADRA)))(i) <= DIA(i);
END IF;
END LOOP;
data <= LocalRAM(TO_INTEGER(UNSIGNED(ADRA)));
code <= LocalRAM(TO_INTEGER(UNSIGNED(ADRB)));
END IF;
END PROCESS CodeDataMemory;
DOA <= data;
DOB <= code;
END WDG0;
|
gpl-2.0
|
dfde5b3c3e033053346b613bb45e7c54
| 0.535381 | 4 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug04/test.vhdl
| 3 | 1,424 |
library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.is_x;
package std_logic_warning is
function EQ_BUT_NOT_META(l, r : std_logic) return boolean;
end package;
package body std_logic_warning is
use ieee.std_logic_1164."=";
function EQ_BUT_NOT_META(l, r : std_logic) return boolean is
begin
if is_x(l) or is_x(r) then
report "std_logic_warning.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return l = r; -- std_logic_1164."="(l, r);
end function;
end package body;
library ieee;
use ieee.std_logic_1164.std_ulogic;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.all;
use work.std_logic_warning.all;
entity warning_test is
end entity;
architecture foo of warning_test is
signal a: std_logic;
signal b: std_logic;
begin
UNLABELLED:
process
begin
wait for 1 ns;
a <= 'X';
wait for 1 ns;
b <= '1';
wait for 1 ns;
a <= '0';
wait for 1 ns;
b <= '0';
wait;
end process;
MONITOR:
process (a,b)
begin
assert EQ_BUT_NOT_META(a,b) = TRUE
report "a = b " & "( " & std_logic'image(a)
& "=" & std_logic'image(b) & " )"
severity NOTE;
end process;
end architecture;
|
gpl-2.0
|
b339dd92c530780eec5553b03154560a
| 0.553371 | 3.358491 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd
| 4 | 2,770 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc627.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:46 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:09 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:25 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00627ent IS
END c03s04b01x00p01n01i00627ent;
ARCHITECTURE c03s04b01x00p01n01i00627arch OF c03s04b01x00p01n01i00627ent IS
type four_value is ('Z','0','1','X');
type four_value_file is file of four_value;
constant C38 : four_value := 'X';
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_file open read_mode is "iofile.36";
variable v : four_value;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00627"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00627 - File reading operation (four_value file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00627arch;
|
gpl-2.0
|
d21005a937c8819bca2252800d2a9772
| 0.551986 | 3.874126 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd
| 4 | 8,036 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00761pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00761pkg;
use work.c01s01b01x01p05n02i00761pkg.ALL;
ENTITY c01s01b01x01p05n02i00761ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen : integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
port(
Vgen1 : boolean := true;
Vgen2 : bit := '1';
Vgen3 : character := 's';
Vgen4 : severity_level:= note;
Vgen5 : integer := 3;
Vgen6 : real := 3.0;
Vgen7 : time := 3 ns;
Vgen8 : natural := 1;
Vgen9 : positive := 1;
Vgen70 : boolean_vector_st :=(others => true);
Vgen71 : severity_level_vector_st :=(others => note);
Vgen72 : integer_vector_st :=(others => 3);
Vgen73 : real_vector_st :=(others => 3.0);
Vgen74 : time_vector_st :=(others => 3 ns);
Vgen75 : natural_vector_st :=(others => 1);
Vgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00761ent;
ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00761"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00761arch;
|
gpl-2.0
|
f459a443e030141428ec32772583393b
| 0.593703 | 3.826667 | false | false | false | false |
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/external_logo_module/ICON_GEN_ST.vhd
| 1 | 24,908 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
LIBRARY altera_mf;
-- ---------------------
Entity ICON_GEN_ST is
-- ---------------------
generic ( NB_BITS_SYMB : natural:=10 );
port ( VID_RST : in std_logic -- Pixel Clock
; VID_CLK : in std_logic -- Asynchronous Reset
-- Avalon Video Streaming Video
; VID_RDY : in std_logic -- Input Ready signal
; VID_SOP : out std_logic -- Start of Packet
; VID_DAV : out std_logic -- Data Valid
; VID_DATA : out std_logic_vector((NB_BITS_SYMB*3*2)-1 downto 0) -- Video Data
; VID_EOP : out std_logic -- End of Packet
);
-- ------------------------
End entity ICON_GEN_ST;
-- ------------------------
-- -----------------------------------
Architecture RTL of ICON_GEN_ST is
-- -----------------------------------
constant OUTPUT_REG : boolean:=true;
constant BLANK_DUR : natural:=5; -- blanking used
constant NB_PIX_CLK : natural:=2;
-- Nibble size : 4 bits (used to describe the Control Packet content)
constant NIBBLE_SIZE : natural:=4;
-- Initial resolution : 160 x 90
--constant LOGO_SIZE_X : natural:=160;
--constant LOGO_SIZE_Y : natural:=90;
constant LOGO_SIZE_X : natural:=306;
constant LOGO_SIZE_Y : natural:=191;
constant iWIDTH : std_logic_vector(15 downto 0):=std_logic_vector(to_unsigned(LOGO_SIZE_X,16));
constant iHEIGHT : std_logic_vector(15 downto 0):=std_logic_vector(to_unsigned(LOGO_SIZE_Y,16));
constant iTYPE : std_logic_vector(3 downto 0):=x"3"; -- Progressive Image
component altsyncram
generic (
operation_mode : string := "BIDIR_DUAL_PORT";
-- port a parameters
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
-- registering parameters
-- port a read parameters
outdata_reg_a : string := "UNREGISTERED";
-- clearing parameters
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
-- clearing parameters
-- port a write parameters
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a : string := "NONE";
-- clear for the byte enable port reigsters which are clocked by clk0
byteena_aclr_a : string := "NONE";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_a : integer := 1;
-- port b parameters
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
-- registering parameters
-- port b read parameters
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
-- clearing parameters
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b : string := "NONE";
-- registering parameters
-- port b write parameters
indata_reg_b : string := "CLOCK1";
wrcontrol_wraddress_reg_b : string := "CLOCK1";
-- registering parameter for the byte enable reister for port b
byteena_reg_b : string := "CLOCK1";
-- clearing parameters
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b : string := "NONE";
address_aclr_b : string := "NONE";
-- clear parameter for byte enable port register
byteena_aclr_b : string := "NONE";
-- StratixII only : to bypass clock enable or using clock enable
clock_enable_input_a : string := "NORMAL";
clock_enable_output_a : string := "NORMAL";
clock_enable_input_b : string := "NORMAL";
clock_enable_output_b : string := "NORMAL";
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
width_byteena_b : integer := 1;
-- clock enable setting for the core
clock_enable_core_a : string := "USE_INPUT_CLKEN";
clock_enable_core_b : string := "USE_INPUT_CLKEN";
-- read-during-write-same-port setting
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
-- ECC status ports setting
enable_ecc : string := "FALSE";
ecc_pipeline_stage_enabled : string := "FALSE";
width_eccstatus : integer := 3;
-- global parameters
-- width of a byte for byte enables
byte_size : integer := 0;
read_during_write_mode_mixed_ports: string := "DONT_CARE";
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
ram_block_type : string := "AUTO";
-- determine whether LE support is turned on or off for altsyncram
implement_in_les : string := "OFF";
-- determine whether RAM would be power up to uninitialized or not
power_up_uninitialized : string := "FALSE";
sim_show_memory_data_in_port_b_layout : string := "OFF";
-- general operation parameters
init_file : string := "UNUSED";
init_file_layout : string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family : string := "Stratix";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram" );
port (
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
address_a : in std_logic_vector(widthad_a - 1 downto 0);
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
clock0 : in std_logic := '1';
clock1 : in std_logic := 'Z';
clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';
clocken2 : in std_logic := '1';
clocken3 : in std_logic := '1';
aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z');
addressstall_a : in std_logic := '0';
addressstall_b : in std_logic := '0';
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0);
eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') );
end component;
-- named subtypes used of the Output Control Header
-- Width management
subtype WIDTH_15_12 is natural range NIBBLE_SIZE + (0*NB_BITS_SYMB) - 1 downto 0*NB_BITS_SYMB;
subtype WIDTH_11_08 is natural range NIBBLE_SIZE + (1*NB_BITS_SYMB) - 1 downto 1*NB_BITS_SYMB;
subtype WIDTH_07_04 is natural range NIBBLE_SIZE + (2*NB_BITS_SYMB) - 1 downto 2*NB_BITS_SYMB;
subtype WIDTH_03_00 is natural range NIBBLE_SIZE + (3*NB_BITS_SYMB) - 1 downto 3*NB_BITS_SYMB;
-- Height management
subtype HEIGHT_15_12 is natural range NIBBLE_SIZE + (4*NB_BITS_SYMB) - 1 downto 4*NB_BITS_SYMB;
subtype HEIGHT_11_08 is natural range NIBBLE_SIZE + (5*NB_BITS_SYMB) - 1 downto 5*NB_BITS_SYMB;
subtype HEIGHT_07_04 is natural range NIBBLE_SIZE + (0*NB_BITS_SYMB) - 1 downto 0*NB_BITS_SYMB;
subtype HEIGHT_03_00 is natural range NIBBLE_SIZE + (1*NB_BITS_SYMB) - 1 downto 1*NB_BITS_SYMB;
subtype CTRL_TYPE is natural range NIBBLE_SIZE + (2*NB_BITS_SYMB) - 1 downto 2*NB_BITS_SYMB;
Type FSM_t is ( IDLE
, CTRL_HEADER_ID
, CTRL_HEADER_END
, DATA_HEADER
, SEND_BLANK
, SEND_LINE
);
signal FSM, GOTO : FSM_t;
constant MIF_FILE_NAME_R : string:="./ip/external_logo_module/rawlogo_r.mif";
constant MIF_FILE_NAME_G : string:="./ip/external_logo_module/rawlogo_g.mif";
constant MIF_FILE_NAME_B : string:="./ip/external_logo_module/rawlogo_b.mif";
signal CNT_X : unsigned(7 downto 0); -- size of lines
signal CNT_Y : unsigned(7 downto 0); -- number of lines
signal CNT_BL : natural range 0 to BLANK_DUR-2;
signal iVID_SOP : std_logic;
signal iVID_DAV : std_logic;
signal iVID_EOP : std_logic;
signal iVID_RDY : std_logic;
signal iVID_DATA : std_logic_vector(VID_DATA'range);
signal iVID_DATA2 : std_logic_vector(VID_DATA'range);
signal RAM_ADDR : std_logic_vector(14 downto 0);
signal RAM_DATA_R : std_logic_vector(15 downto 0);
signal RAM_DATA_G : std_logic_vector(15 downto 0);
signal RAM_DATA_B : std_logic_vector(15 downto 0);
-----\
Begin
-----/
-- --------------------------------------
-- 2 Pixels in // managed per clock cycle
-- --------------------------------------
-- Image Generation
GEN_proc : process(VID_RST, VID_CLK)
variable RAM_PIX : natural range 0 to LOGO_SIZE_X-1;
variable RAM_LIN : natural range 0 to LOGO_SIZE_Y-1;
begin
if VID_RST='1' then
FSM <= IDLE;
GOTO <= IDLE;
iVID_SOP <= '0';
iVID_DAV <= '0';
iVID_DATA <= (others => '0');
iVID_EOP <= '0';
CNT_X <= (others => '0');
CNT_Y <= (others => '0');
CNT_BL <= 0 ;
RAM_ADDR <= (others => '0');
RAM_PIX := 0 ;
RAM_LIN := 0 ;
elsif rising_edge(VID_CLK) then
iVID_SOP <= '0';
iVID_DAV <= '0';
iVID_EOP <= '0';
case FSM is
-- Wait for the Ready input
when IDLE =>
CNT_X <= (others => '0');
CNT_Y <= (others => '0');
iVID_SOP <= '0';
iVID_DAV <= '0';
iVID_EOP <= '0';
RAM_PIX := 0 ;
RAM_LIN := 0 ;
if iVID_RDY='1' then -- readyLatency=1
FSM <= CTRL_HEADER_ID;
iVID_SOP <= '1'; -- First word of the Control Packet
iVID_DAV <= '1';
iVID_DATA <= (others => '0');
iVID_DATA(3 downto 0) <= (others => '1'); -- Packet Type Identifier
end if;
-- Header ID
when CTRL_HEADER_ID =>
if iVID_RDY='1' then
FSM <= CTRL_HEADER_END;
iVID_SOP <= '0';
iVID_DAV <= '1';
iVID_EOP <= '0';
iVID_DATA <= (others => '0');
-- First Pixel : Width
iVID_DATA(WIDTH_07_04) <= iWIDTH((2*NIBBLE_SIZE)-1 downto (1*NIBBLE_SIZE));
iVID_DATA(WIDTH_11_08) <= iWIDTH((3*NIBBLE_SIZE)-1 downto (2*NIBBLE_SIZE));
iVID_DATA(WIDTH_15_12) <= iWIDTH((4*NIBBLE_SIZE)-1 downto (3*NIBBLE_SIZE));
-- 2nd Pixel : Width & Height
iVID_DATA(HEIGHT_11_08) <= iHEIGHT((3*NIBBLE_SIZE)-1 downto (2*NIBBLE_SIZE));
iVID_DATA(HEIGHT_15_12) <= iHEIGHT((4*NIBBLE_SIZE)-1 downto (3*NIBBLE_SIZE));
iVID_DATA( WIDTH_03_00) <= iWIDTH ((1*NIBBLE_SIZE)-1 downto (0*NIBBLE_SIZE));
end if;
-- End of the Control Packet
when CTRL_HEADER_END =>
if iVID_RDY='1' then
FSM <= DATA_HEADER;
iVID_SOP <= '0';
iVID_DAV <= '1';
iVID_EOP <= '1';
iVID_DATA <= (others => '0');
-- Height (end) & Type
iVID_DATA(CTRL_TYPE) <= x"3";
iVID_DATA(HEIGHT_03_00) <= iHEIGHT((1*NIBBLE_SIZE)-1 downto (0*NIBBLE_SIZE));
iVID_DATA(HEIGHT_07_04) <= iHEIGHT((2*NIBBLE_SIZE)-1 downto (1*NIBBLE_SIZE));
end if;
-- Data Header
when DATA_HEADER =>
if iVID_RDY='1' then
FSM <= SEND_BLANK;
GOTO <= SEND_LINE;
iVID_SOP <= '1';
iVID_DAV <= '1';
iVID_DATA <= (others => '0');
end if;
-- Blanking phase - wait state between active lines
when SEND_BLANK =>
if CNT_BL=BLANK_DUR-2 then
CNT_BL <= 0 ;
RAM_PIX := 0;
FSM <= GOTO;
else
CNT_BL <= CNT_BL + 1;
end if;
RAM_ADDR <= std_logic_vector(to_unsigned((RAM_LIN*(LOGO_SIZE_X/2)), RAM_ADDR'length));
-- Send the active line
when SEND_LINE =>
iVID_DAV <= iVID_RDY;
iVID_DATA <= (others => '0');
-- 1st Pixel
iVID_DATA((01*NB_BITS_SYMB)-1 downto 00*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_B(07 downto 00);
iVID_DATA((02*NB_BITS_SYMB)-1 downto 01*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_G(07 downto 00);
iVID_DATA((03*NB_BITS_SYMB)-1 downto 02*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_R(07 downto 00);
-- 2nd Pixel
iVID_DATA((04*NB_BITS_SYMB)-1 downto 03*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_B(15 downto 08);
iVID_DATA((05*NB_BITS_SYMB)-1 downto 04*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_G(15 downto 08);
iVID_DATA((06*NB_BITS_SYMB)-1 downto 05*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_R(15 downto 08);
-- Test Pattern Output (combinational)
if iVID_RDY='1' then
-- Display icon from RAM
if RAM_PIX/=((LOGO_SIZE_X/NB_PIX_CLK)-1) then
RAM_PIX := RAM_PIX + 1;
end if;
RAM_ADDR <= std_logic_vector(to_unsigned(((RAM_LIN*(LOGO_SIZE_X/2)) + RAM_PIX), RAM_ADDR'length));
-- Line / Image progression
if CNT_Y=(LOGO_SIZE_Y-1) and CNT_X=((LOGO_SIZE_X/2)-1) then -- last pixel of the image
FSM <= SEND_BLANK;
GOTO <= IDLE;
iVID_DAV <= '1';
iVID_EOP <= '1';
CNT_X <= (others => '0');
elsif CNT_X=(LOGO_SIZE_X/2) then -- End of line
FSM <= SEND_BLANK;
GOTO <= SEND_LINE;
iVID_DAV <= '0';
CNT_Y <= CNT_Y + 1;
CNT_X <= (others => '0');
if RAM_LIN/=(LOGO_SIZE_Y-1) then
RAM_LIN := RAM_LIN + 1;
end if;
else
CNT_X <= CNT_X + 1;
end if;
end if;
end case;
end if;
end process GEN_proc;
-- Red Pixel Values
RAM_LOGO_R_inst : altsyncram
generic map ( clock_enable_input_a => "BYPASS"
, clock_enable_output_a => "BYPASS"
, init_file => MIF_FILE_NAME_R
, intended_device_family => "Arria 10"
, lpm_hint => "ENABLE_RUNTIME_MOD=NO"
, lpm_type => "altsyncram"
, numwords_a => 32768
, operation_mode => "SINGLE_PORT"
, outdata_aclr_a => "NONE"
, outdata_reg_a => "UNREGISTERED"
, power_up_uninitialized => "FALSE"
, ram_block_type => "M20K"
, read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ"
, widthad_a => 15
, width_a => 16
, width_byteena_a => 1
)
port map ( address_a => RAM_ADDR
, clock0 => VID_CLK
, data_a => (others => '0')
, wren_a => '0'
, q_a => RAM_DATA_R
);
-- Green Pixel Values
RAM_LOGO_G_inst : altsyncram
generic map ( clock_enable_input_a => "BYPASS"
, clock_enable_output_a => "BYPASS"
, init_file => MIF_FILE_NAME_G
, intended_device_family => "Arria 10"
, lpm_hint => "ENABLE_RUNTIME_MOD=NO"
, lpm_type => "altsyncram"
, numwords_a => 32768
, operation_mode => "SINGLE_PORT"
, outdata_aclr_a => "NONE"
, outdata_reg_a => "UNREGISTERED"
, power_up_uninitialized => "FALSE"
, ram_block_type => "M20K"
, read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ"
, widthad_a => 15
, width_a => 16
, width_byteena_a => 1
)
port map ( address_a => RAM_ADDR
, clock0 => VID_CLK
, data_a => (others => '0')
, wren_a => '0'
, q_a => RAM_DATA_G
);
-- Blue Pixel Values
RAM_LOGO_B_inst : altsyncram
generic map ( clock_enable_input_a => "BYPASS"
, clock_enable_output_a => "BYPASS"
, init_file => MIF_FILE_NAME_B
, intended_device_family => "Arria 10"
, lpm_hint => "ENABLE_RUNTIME_MOD=NO"
, lpm_type => "altsyncram"
, numwords_a => 32768
, operation_mode => "SINGLE_PORT"
, outdata_aclr_a => "NONE"
, outdata_reg_a => "UNREGISTERED"
, power_up_uninitialized => "FALSE"
, ram_block_type => "M20K"
, read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ"
, widthad_a => 15
, width_a => 16
, width_byteena_a => 1
)
port map ( address_a => RAM_ADDR
, clock0 => VID_CLK
, data_a => (others => '0')
, wren_a => '0'
, q_a => RAM_DATA_B
);
-- Video Pixels
-- ------------
DATA_proc : process(RAM_DATA_R, RAM_DATA_G, RAM_DATA_B, FSM, iVID_DATA)
begin
if FSM=SEND_LINE then
iVID_DATA2 <= (others => '0');
-- 1st Pixel
iVID_DATA2((01*NB_BITS_SYMB)-1 downto 00*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_B(07 downto 00);
iVID_DATA2((02*NB_BITS_SYMB)-1 downto 01*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_G(07 downto 00);
iVID_DATA2((03*NB_BITS_SYMB)-1 downto 02*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_R(07 downto 00);
-- 2nd Pixel
iVID_DATA2((04*NB_BITS_SYMB)-1 downto 03*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_B(15 downto 08);
iVID_DATA2((05*NB_BITS_SYMB)-1 downto 04*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_G(15 downto 08);
iVID_DATA2((06*NB_BITS_SYMB)-1 downto 05*NB_BITS_SYMB+(NB_BITS_SYMB-8)) <= RAM_DATA_R(15 downto 08);
else
iVID_DATA2 <= iVID_DATA;
end if;
end process DATA_proc;
-- Combinational output stage
COMB_OUT_GEN : if not OUTPUT_REG generate
-- Input ready signal
iVID_RDY <= VID_RDY;
-- Streaming interface
VID_SOP <= iVID_SOP;
VID_EOP <= iVID_EOP;
VID_DAV <= iVID_DAV;
VID_DATA <= iVID_DATA2;
end generate COMB_OUT_GEN;
-- Registered output stage
REG_OUT_GEN : if OUTPUT_REG generate
constant MAX_WIDTH : natural:=160;
-- Buffer dimension
constant BUFFER_DEPTH_LOG2 : natural:=NATURAL(CEIL(LOG2(real(MAX_WIDTH))));
constant BUFFER_DEPTH : natural:=2**BUFFER_DEPTH_LOG2;
-- FIFO Fillrate used to deassert SINK_READY output
constant ALMOST_FULL : natural:=128;
component scfifo
generic (
add_ram_output_register : string := "OFF";
allow_rwcycle_when_full : string := "OFF";
almost_empty_value : natural := 0;
almost_full_value : natural := 0;
intended_device_family : string := "unused";
enable_ecc : string := "FALSE";
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_width : natural;
lpm_widthu : natural := 1;
overflow_checking : string := "ON";
ram_block_type : string := "AUTO";
underflow_checking : string := "ON";
use_eab : string := "ON";
lpm_hint : string := "UNUSED";
lpm_type : string := "scfifo"
);
port(
aclr : in std_logic := '0';
almost_empty : out std_logic;
almost_full : out std_logic;
clock : in std_logic;
data : in std_logic_vector(lpm_width-1 downto 0);
eccstatus : out std_logic_vector(1 downto 0);
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(lpm_width-1 downto 0);
rdreq : in std_logic;
sclr : in std_logic := '0';
usedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrreq : in std_logic
);
end component;
-- Buffer Signals
signal WE_EN : std_logic;
signal WR_DIN : std_logic_vector(((2*3*NB_BITS_SYMB)+1) downto 0);
signal FIFO_RD : std_logic;
signal FIFO_OUT : std_logic_vector(((2*3*NB_BITS_SYMB)+1) downto 0);
signal FIFO_EMPTY : std_logic;
signal FIFO_NB : std_logic_vector(BUFFER_DEPTH_LOG2-1 downto 0);
-----
Begin
-----
-- Video Data Buffer
ADAPT_BUFFER : scfifo
generic map ( add_ram_output_register => "ON"
, allow_rwcycle_when_full => "OFF"
, intended_device_family => "Arria 10"
, enable_ecc => "FALSE"
, lpm_numwords => 256
, lpm_showahead => "ON"
, lpm_width => 62
, lpm_widthu => 8
, overflow_checking => "ON"
, ram_block_type => "AUTO"
, underflow_checking => "ON"
, use_eab => "ON"
, lpm_hint => "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE"
, lpm_type => "scfifo"
)
port map ( data => WR_DIN
, wrreq => WE_EN
, rdreq => FIFO_RD
, clock => VID_CLK
, aclr => VID_RST
, q => FIFO_OUT
, usedw => FIFO_NB
, full => open
, empty => FIFO_EMPTY
);
-- Fifo Read requests
FIFO_RD <= (not FIFO_EMPTY) and VID_RDY;
-- Output stage
OUT_proc : process(VID_RST, VID_CLK)
begin
if VID_RST='1' then
iVID_RDY <= '1';
WE_EN <= '0';
WR_DIN <= (others => '0');
VID_DAV <= '0';
VID_EOP <= '0';
VID_SOP <= '0';
VID_DATA <= (others => '0');
elsif rising_edge(VID_CLK) then
-- Ready to RAM reader
iVID_RDY <= '1';
if (unsigned(FIFO_NB) > ALMOST_FULL) then
iVID_RDY <= '0';
end if;
-- Data to store
WE_EN <= iVID_DAV;
WR_DIN <= iVID_SOP & iVID_DATA2 & iVID_EOP;
-- Output signals
VID_SOP <= '0';
VID_DAV <= '0';
VID_EOP <= '0';
if FIFO_RD='1' then
VID_DAV <= '1';
VID_SOP <= FIFO_OUT(FIFO_OUT'high);
VID_EOP <= FIFO_OUT(FIFO_OUT'low);
VID_DATA <= FIFO_OUT(FIFO_OUT'high-1 downto FIFO_OUT'low+1);
end if;
end if;
end process OUT_proc;
end generate REG_OUT_GEN;
-- ---------------------
End architecture RTL;
-- ---------------------
|
mit
|
2aa5e3a436e00cb04355ca58002d7192
| 0.470732 | 3.793482 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1239/repro3.vhdl
| 1 | 460 |
library ieee;
use ieee.std_logic_1164.all;
entity repro3 is
generic (
constant DIN_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 12
);
end repro3;
architecture Behav of repro3 is
type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DIN_WIDTH - 1 downto 0);
signal FIFO_ROW_1 : FIFO_Memory;
begin
FIFO_ROW_1<= (FIFO_ROW_1 'range=> (FIFO_ROW_1 'range=>'0'));
end Behav;
|
gpl-2.0
|
40c7c98d28f2e6c23de9533fd2d06fd0
| 0.608696 | 3.216783 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue880/psl.vhdl
| 1 | 684 |
entity psl is
end;
architecture behav of psl is
signal a, b, c : bit;
signal clk : bit;
subtype wf_type is bit_vector (0 to 7);
constant wave_a : wf_type := "10010100";
constant wave_b : wf_type := "01001010";
constant wave_c : wf_type := "00100101";
begin
process
begin
for i in wf_type'range loop
clk <= '0';
wait for 1 ns;
a <= wave_a (i);
b <= wave_b (i);
c <= wave_c (i);
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
-- psl default clock is (clk'event and clk = '1');
-- psl a1: assume always a |=> b;
-- psl a2: assume always a -> eventually! c;
-- psl c1: cover {a;b;c};
end behav;
|
gpl-2.0
|
9e501cf93942bb6b7cf3f898ccebfb58
| 0.555556 | 3.095023 | false | false | false | false |
nickg/nvc
|
test/regress/genpack8.vhd
| 1 | 1,761 |
package gen_counter is
generic ( type t;
one, zero : t;
function "+"(x, y : t) return t is <>;
function "-"(x, y : t) return t is <> );
type counter is protected
procedure increment;
procedure decrement;
impure function value return t;
end protected;
shared variable var : counter;
end package;
package body gen_counter is
type counter is protected body
variable val : t := zero;
procedure increment is
begin
val := val + one;
end procedure;
procedure decrement is
begin
val := val - one;
end procedure;
impure function value return t is
begin
return val;
end function;
end protected body;
end package body;
-------------------------------------------------------------------------------
package int_counter is new work.gen_counter
generic map ( t => integer, one => 1, zero => 0 );
-------------------------------------------------------------------------------
use work.int_counter;
entity genpack8 is
end entity;
architecture test of genpack8 is
package real_counter is new work.gen_counter
generic map (t => real, one => 1.0, zero => 0.0 );
begin
main: process is
begin
assert int_counter.var.value = 0;
int_counter.var.increment;
int_counter.var.increment;
int_counter.var.decrement;
assert int_counter.var.value = 1;
assert real_counter.var.value = 0.0;
real_counter.var.increment;
real_counter.var.increment;
real_counter.var.decrement;
assert real_counter.var.value = 1.0;
wait;
end process;
end architecture;
|
gpl-3.0
|
d31698605b7de4e85f628caf9996ed71
| 0.531516 | 4.53866 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd
| 4 | 2,216 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_ch_16_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_16_05 is
end entity ch_16_05;
----------------------------------------------------------------
architecture test of ch_16_05 is
subtype word is bit_vector(0 to 31);
type word_array is array (integer range <>) of word;
function resolve_words ( words : word_array ) return word is
begin
if words'length > 0 then
return words(words'left);
else
return X"00000000";
end if;
end function resolve_words;
subtype resolved_word is resolve_words word;
-- code from book:
signal source_bus_1, source_bus_2 : resolved_word bus;
signal address_bus : resolved_word bus;
disconnect all : resolved_word after 2 ns;
-- end of code from book
signal s : word;
signal g : boolean;
begin
b : block (g) is
begin
source_bus_1 <= guarded s after 4 ns;
source_bus_2 <= guarded s after 4 ns;
address_bus <= guarded s after 4 ns;
end block b;
stimulus : process is
begin
s <= X"DDDDDDDD";
wait for 10 ns;
g <= true;
wait for 10 ns;
s <= X"AAAAAAAA";
wait for 10 ns;
g <= false;
wait for 10 ns;
s <= X"11111111";
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
6c5f2b16aed75121d1c108bf6d9a7dde
| 0.608755 | 3.915194 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/arr01/tb_arr06.vhdl
| 1 | 1,000 |
entity tb_arr06 is
end tb_arr06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr06 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr06
port map (clk => clk, val => val, res => res, par => par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
val <= x"a0";
pulse;
val <= x"71";
pulse;
val <= x"82";
pulse;
val <= x"23";
pulse;
val <= x"fe";
pulse;
assert res = x"a0" severity failure;
val <= x"e4";
pulse;
assert res = x"71" severity failure;
val <= x"c5";
pulse;
assert res = x"82" severity failure;
val <= x"f6";
pulse;
assert res = x"23" severity failure;
val <= x"57";
pulse;
assert res = x"fe" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
a6008d925e87399ad159a3f09de6b1f0
| 0.561 | 3.184713 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/output01/tb_output07.vhdl
| 1 | 677 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_output07 is
end tb_output07;
architecture behav of tb_output07 is
signal i : std_logic;
signal clk : std_logic;
signal o : std_logic_vector (1 downto 0);
begin
inst: entity work.output07
port map (clk => clk, i => i, o => o);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
wait for 1 ns;
assert o = "10" severity failure;
i <= '1';
pulse;
assert o = "01" severity failure;
i <= '0';
pulse;
assert o = "10" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
145749363ac65946d7d9b758874b7e04
| 0.577548 | 3.286408 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd
| 4 | 5,268 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
use qsim.qsim_types.all, random.random.all;
architecture queue_net of disk_system is
constant disk_cache_miss_rate : real := 0.2;
constant num_disks : positive := 2;
constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
:= ( others => disk_cache_miss_rate / real(num_disks) );
signal info_detail_control : info_detail_type := none;
signal new_job, cpu_queue_in, cpu_in, cpu_out,
quantum_expired, job_done, requesting_disk,
disk_cache_hit, request_done : arc_type;
signal disk_cache_miss, disk_done : arc_vector(1 to num_disks);
signal cpu_ready : boolean;
begin
new_jobs : entity source
generic map ( name => "new_jobs",
distribution => exponential,
mean_inter_arrival_time => 2 sec,
seed => sample_seeds(1),
time_unit => ms,
info_file_name => "new_jobs.dat" )
port map ( out_arc => new_job,
info_detail => info_detail_control );
cpu_join : entity join
generic map ( name => "cpu_join",
time_unit => ms,
info_file_name => "cpu_join.dat" )
port map ( in_arc(1) => quantum_expired,
in_arc(2) => new_job,
in_arc(3) => request_done,
out_arc => cpu_queue_in,
info_detail => info_detail_control );
cpu_queue : entity queue
generic map ( name => "cpu_queue",
time_unit => ms,
info_file_name => "cpu_queue.dat" )
port map ( in_arc => cpu_queue_in,
out_arc => cpu_in,
out_ready => cpu_ready,
info_detail => info_detail_control );
cpu : entity server
generic map ( name => "cpu",
distribution => uniform,
mean_service_time => 50 ms,
seed => sample_seeds(2),
time_unit => ms,
info_file_name => "cpu.dat" )
port map ( in_arc => cpu_in,
in_ready => cpu_ready,
out_arc => cpu_out,
info_detail => info_detail_control );
cpu_fork : entity fork
generic map ( name => "cpu_fork",
probabilities => ( 1 => 0.5, 2 => 0.45 ),
seed => sample_seeds(3),
time_unit => ms,
info_file_name => "cpu_fork.dat" )
port map ( in_arc => cpu_out,
out_arc(1) => quantum_expired,
out_arc(2) => requesting_disk,
out_arc(3) => job_done,
info_detail => info_detail_control );
job_sink : entity sink
generic map ( name => "job_sink",
time_unit => ms,
info_file_name => "job_sink.dat" )
port map ( in_arc => job_done,
info_detail => info_detail_control );
disk_cache_fork : entity fork
generic map ( name => "disk_cache_fork",
probabilities => disk_cache_fork_probabilities,
seed => sample_seeds(4),
time_unit => ms,
info_file_name => "disk_cache_fork.dat" )
port map ( in_arc => requesting_disk,
out_arc(1 to num_disks) => disk_cache_miss,
out_arc(num_disks + 1) => disk_cache_hit,
info_detail => info_detail_control );
disk_array : for disk_index in 1 to num_disks generate
constant disk_index_str : string := integer'image(disk_index);
signal disk_in : arc_type;
signal disk_ready : boolean;
begin
disk_queue : entity queue
generic map ( name => "disk_queue_" & disk_index_str,
time_unit => ms,
info_file_name => "disk_queue_" & disk_index_str & ".dat" )
port map ( in_arc => disk_cache_miss(disk_index),
out_arc => disk_in,
out_ready => disk_ready,
info_detail => info_detail_control );
disk : entity server
generic map ( name => "disk_" & disk_index_str,
distribution => exponential,
mean_service_time => 15 ms,
seed => sample_seeds(4 + disk_index),
time_unit => ms,
info_file_name => "disk_" & disk_index_str & ".dat" )
port map ( in_arc => disk_in,
in_ready => disk_ready,
out_arc => disk_done(disk_index),
info_detail => info_detail_control );
end generate disk_array;
disk_cache_join : entity join
generic map ( name => "disk_cache_join",
time_unit => ms,
info_file_name => "disk_cache_join.dat" )
port map ( in_arc(1 to num_disks) => disk_done,
in_arc(num_disks + 1) => disk_cache_hit,
out_arc => request_done,
info_detail => info_detail_control );
end architecture queue_net;
|
gpl-2.0
|
b0cdd8756d2c277f8c67b4f2263654ac
| 0.595672 | 3.468071 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue563/counter.vhdl
| 1 | 737 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
port (
key0: in std_logic;
key3: in std_logic;
counter_out: out std_logic_vector(3 downto 0)
);
end counter;
architecture arch_counter of counter is
signal c: std_logic_vector(0 to 3) := (others => '0');
begin
process(key0, key3)
begin
if (rising_edge(key0)) then
c <= std_logic_vector(unsigned(c) + 1);
if (unsigned(c) = 9) then
c <= "0000";
end if;
end if;
if (rising_edge(key3)) then
c <= std_logic_vector(unsigned(c) - 1);
if (unsigned(c) = "1111") then
c <= "1000";
end if;
end if;
end process;
counter_out <= c;
end arch_counter ; -- arch_counter
|
gpl-2.0
|
972bccb0869ee002c8611d0a36b8c2d8
| 0.592944 | 3.032922 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd
| 4 | 1,795 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1807.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p07n01i01807ent IS
END c07s01b00x00p07n01i01807ent;
ARCHITECTURE c07s01b00x00p07n01i01807arch OF c07s01b00x00p07n01i01807ent IS
signal POS : integer;
signal P1 : integer := 2;
signal P2 : integer := 2;
BEGIN
TESTING: PROCESS
BEGIN
POS <= P1 ** P2 after 20 ns;
wait for 35 ns;
assert NOT(POS = 4)
report "***PASSED TEST: c07s01b00x00p07n01i01807"
severity NOTE;
assert (POS = 4)
report "***FAILED TEST: c07s01b00x00p07n01i01807 - Primary**primary test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p07n01i01807arch;
|
gpl-2.0
|
b4dc16b6c8e0648f71b06019ddf750ab
| 0.662396 | 3.670757 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
| 4 | 2,633 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity read_array_write_data is
end entity read_array_write_data;
architecture writer of read_array_write_data is
begin
process is
type integer_file is file of integer;
file data_file : integer_file open write_mode is "coeff-data";
begin
write(data_file, 0);
write(data_file, 1);
write(data_file, 2);
write(data_file, 3);
write(data_file, 4);
write(data_file, 5);
write(data_file, 6);
write(data_file, 7);
write(data_file, 8);
write(data_file, 9);
write(data_file, 10);
write(data_file, 11);
write(data_file, 12);
write(data_file, 13);
write(data_file, 14);
write(data_file, 15);
write(data_file, 16);
write(data_file, 17);
write(data_file, 18);
wait;
end process;
end architecture writer;
entity read_array is
end entity read_array;
architecture test of read_array is
begin
process is
-- code from book (in text)
type integer_vector is array (integer range <>) of integer;
-- end code from book
-- code from book (in Figure)
impure function read_array ( file_name : string; array_length : natural )
return integer_vector is
type integer_file is file of integer;
file data_file : integer_file open read_mode is file_name;
variable result : integer_vector(1 to array_length) := (others => 0);
variable index : integer := 1;
begin
while not endfile(data_file) and index <= array_length loop
read(data_file, result(index));
index := index + 1;
end loop;
return result;
end function read_array;
-- end code from book
-- code from book (in text)
constant coeffs : integer_vector := read_array("coeff-data", 16);
-- end code from book
begin
wait;
end process;
end architecture test;
|
gpl-2.0
|
6c14c31a5e7bfab1bf827dc53ed041b0
| 0.661983 | 3.799423 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0.vhd
| 6 | 16,918 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dWNC5O/skI155KAp5KOWoF7PAEoSa9dlQ4BEGvYf9rcCz/XPmDGb9cHdFk41xW/13JPFb1vvJI0y
paR+PkKOQw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
arDqe1SZUVXvjYDvQFyp018Qo3kBxAQuqhz4XaALefjTfUVxHLOl0QMJ32OBFkyD4ASVDy0y26uw
p1WfQag4myDUgw9X1tg1EkSAjiY2T+bS46vpr/V1iSmCBLeMocwUSy+S6/j8P6sKpKVBIwYNIUk+
GeQaTfzT2jus4jLVuYk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LqZHaa/fqNZRMwLiq21bMdfwLQhhsi3+RWh3hUoB3NQuMju+GhGuY4MooZizud9d3j38An+LHEsr
GDrcO/p36+T8vsJNZV7Ufn94KQBBbqctMH8grLiOOYRChU9QJegXc4CDvx7EpF95l1JQ7AYhUc9m
BP637BC0zMrYW9oD9CA+HzYHObkLlwfKUJUa5Z9Gy/gRbRwROFmMiHl+pwV8bGzX77zFUBYh3AmU
ipbAakCJdSPqhrMWtt2EhngRToN7G+1BVQ/CiA7w2ILV+Itzzt5MfEy1C3HjrlzXl51xB32BWGPz
cV4O0htiI8hqTkuOzWq9nCem+ECxavU2KZ3BPg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hl3RtgC3zulj1VBs/uKvPoBXU8IVq31Yn6TPJRPRncW3nwHlMNJjYlyG2Q6bIzixu4iWyHB/ZIHE
5gG8ea3nTO9nr3GqLifJ9msptoTv+MyyZatl294Xr44J6xsXMQ3wJxbBNjUqgn7k7sbogIV78RUM
TVWUJAXxrDcDKI89s2M=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
skw9tNQE1FYb2zddMb2x0Xv3aQBe+FTXsJkPGfwdyXRKljpuw2ofmzjM05rUP1jDryQRbTtcu8Dh
dD3xnSiXkvMjtSrAPZciwjTkVxxCHTNTshjgHiMAWWR/iLuWdsgBT0JqfSHbGB1Bi4mTjh9x7oVO
QYiPIzYyrgsvEVXMyA41XK/6Dvb2pnfqmGXyfQIu7JCvoIQKoTyIAfADRTtAp+pPXpUMu0h+quR+
urUNKn9hxxJ5BNgZbN53EXWHkiNCNV4bBXOgYFLdKkTahF9QNd9xZhbKYYyKomacpiLjvG1YMXv2
28nKiejJmdm4L2LPF6MoBAYk8x00rX1VY1faLg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10784)
`protect data_block
BHyLwSnyIU79ty3AfPjH/wNZb8sme5llLRagWEJwaiB3Wy8JV2XvJG2zLeqtHOwGcUrz4ssHY9E2
Zw1gZjkKuNXy2EDFzkFZ4CnZpM3dWhU0JHbjPa6IAecG1DB+Z6HrC3xwi0rjole/2pGD9aQK+TjX
HVw/1YfyX4hBUEPJGQqZQBKRKPY1Skep5k56+SblaVc2EOP1ngPVuHqzVjaXM7k9FUg/pa5CuYym
ceVQZSXcYc4dBs6DFOCdHd32D7q5PIz3DnGBBAeB3VLCEuEisn+HkCWatHi2W2k/s7gpMh4SRw6l
I2Hg4VXXTPA52ItO2UQ9RToj3cWJaoTD6lp3jfJLKES4oqFGdolk+8KmcJYbNVTWMzUOtSwgLCal
rmqT0Uil3KkcX9oCaVeWe76bw/+HQpm7FUiAUkOGbpPH/6zx+H8mYuxj0iOpDItJMdwNcgm8ZTfC
8oA4W07+M6UvKVYedym9D3yLIIqWFrjxIA9xgKcp/yFWasF+OtssbULCoX26m30W2le2HnqFlzKl
e0S0YKGMnnq2mFTMMbsudsFi6weaS/8NBIY5Uu58kZYUvmIwvfo9eOY9SW/Apc0EeDmtpzcrcTe7
IfMmCgTAEWX1h2xcx8OaCwmT0lY0LikRsgqqYt8SMl2HSGGmj6hcEdxBD0K9uMJVehXi1wHyG/8e
IGdBXxntCDRfUYpwL0WSXNoiy0y6sQI5ZdxYJWVX0YJ5JZTxipaRjK752OESHriTTC4Z9MmEoT6I
n7ulyv+JGYpB3EEKDdw4QMHeyzWU4MNJE3Rbyz0VYBqxnGgrUox6YafmT9fHV8vK1dM0RGL66kgp
AqPOmGA4GcqOI+KQLsM8oAlzjWm+4HDOpyRft+ABVXjCAjaVc5baVSGheynI1uLpHxj3P2LRf6iT
GudS3L9yWOCTCa9eAcilfArYuew42SHIYPrbzUhxipTGFExvD0QUNWniQ3vjXg1r9y4oV+8F6lyf
Gc7RKMOKCihpmtBh60Yc32fjmBClnqGmsoupaxBugIUFqM6u3zVq3RbDzxQ9RPOT2l9sEW1pjGgV
LTGFhwtolun1G4tjH8N56q6uIFEP1LekVCcEB7oq3EAEF1bPnT0MKsT6gCJ5hjBzdvIfn4QITGl4
jRucj45pw7eAjSpzoDD3hzKxBKRwb+Si+5NbGfZsgmPVED704rrq0ty0ashp/dQV+sZGkh8F+Xq7
VkKIYj8j1nHKDq8LZuPJtYVSkcaUnFv/rxnOiy/1QfNWw4Rs5hW+MvaEs+JRT8iUkZ/t8IO/tdU0
8PWjclHxV7A1QIR6m2sz0B20wEPN0/ndyrEtkyftpzZYjpF85PhLKpVZ3d5fTg1RDEy+ATgeg8Rg
qKXTmbncNvXSLp9IxRhv6NkfzKih8ODM6yfMizs/dx/0rmNAfoDTCqL+1SgaiXR5hFc/TUTVQjs9
KWwSmixbBj1U56jGV6TetWRuL5YzOzQTtEFc8DP9Jqu1CPTjvBCiAS7BMta9puniptTSsyvW91pA
xYTR3Ri0KQNSRRGMMb1F0LaxKTEFEWFNVHX4DiJOiIe+6gB/z3WjY9YP2aMChvklS4wWkwBt+tky
rGw+CaXmgMrMzHD7ICXTbOLWBBC/NFXyt7kp3R4JbEKgr1cdfqS0RXf0iCcWvlL4RqBsnuCW1ivV
V8c9yHOdZCW2PM1dEwtQHQvEOgbKRZSjZEWG2CPY9PofWiN0Pb1dZffdauDfYEmnzbbICPImTtH4
xeQ8OEvNqn29mxilH+pWRGOaiyw3XTZX8wAfym39LZRDk+8k8qmvKDOQrnGjFE23uXK4xEFjTkHt
kQsha5pe4HD8rRC6tbhP/xdZNRoACqE0vhuC6W4Be+aQjUzfvGxZLEFAiPUnvS5MF5DqDghyRCaR
2K1Y9a0eBpu0TXhchaBs4X/4ONGA9LamzrcCnLhDZMJKeQeBPh6ZXtdFxwDngOwcjDpCpm79AGgy
xlC/UBZTwSITQlJnvRkBVQlUkHN9o5jZzuyjiNfwXc10FcNjtidVhUieaPUM98zDiDrfi/u9MDMs
LlefQisgDMkezpQtn3AkawLfSDA+zyeSGrFk/F0A5Cq6fbXBZ8V9Jv1y5fKmUbtoxo6dGUdAqwTn
vecw527FNX1tpPEy+P15ep3jSamnFSgIDPmJ5iAZweZiWJ7g08Ej6i0hB6wsRs86GkO5PIgrq9N8
9zgdBZLy3bd47mbXFpSHv9Ml71DlS0MNo1sUOdVtEHsb2+RAC0WJv6vK7GlaKg6bzG6xT+p2ZtIq
jtZNRtJeIdEfRY1WCVkii07fV9MagjzUU9No9NSidsvnpqh0jyQWH0yOL74pZcCA+BILv9++O9Ev
yLr+aCLw/sUqr2l3QH3RjAQgqRKwL/vL6kjKqajNtjJ86t7ZhPcolp2vdNJ5T+33cz6b1+FUes9y
HsExunBHylzYxiilJc0hM+jMtMTkUMTVWJDfR48zH80mlSgs2WuqonUJpsq3M19vV4HcvNlBFIp3
gviasvsF0S7GFbAYm+dTeo+c7lBLgKZ6crijW3lAWFJQZ5IEIYxQlHnzt7Meo9MjsMy7Ph62ipvZ
rtrOJZ56YPBMsHQRfhE1dbRkPmTcQjXLqjyY3YwtpJCqFXDQLRiEzO7+nioDgUjT4i0doOY3+wNY
LAnNLSXfn44CraZ1goQ8KoF+pP6BXWbhio50LeMlMGrWjBkRANVwfjYZNUDQ0kg+hsPuz9P34v2k
9pXJt0eou+BGDEpNK326kM2XL94SjxMZHwPW/ExAF2C0jFqi9rI1X9bw1u2/Mbl8sDGJuIqeEXeH
492DXp94gx1oRNsvk6X+QkeLQAt9Mfn5aRd2gmy/Mj3nBL434NPMKsQDrJCjadeGUwnXacZf+dVz
2ZP20WodX8TUaK4ouaWIzSDSsicof67mhlRLkCc/+pD/ZfdCNbZhW0kALRoP/fMQHz9KbwVO/Dv4
NppwwaxBm+ONB1tKpu+0/7PY2bjFaLRBA8rA+41jCAsjaNB0ZUASAHnPN5f+BwbOmfpfXH82g+0T
JMegVbvCNfdI+hME8M77d9K/kBupxY1br9Pouffqe4B2Dgcig11VEKyJhjkVN97wJ8ZBObCkEKzg
EjvZOOkOEfxdDFQO+jJGvyxHdbrogojpz2Nk34P3z+WTu5vmhSCrhA1t18I1EvkJId9fSqyu4br3
l7GmF8mixMo22JjXkvOWPaQNOSU1Wese0bc5ZcyDuYzclpw7oGltdXyqGja1q7Lfh8jp09LtcBC/
gWxSf8a2Ckn8E0tuG6wZsij9Tix6TperbV2SpKWavvRzOMZNzndvvu0zB8qA+KTcThCPRfynXzee
AmgqCoF5voTjkyVscGmah+gI8/n99n5fkIKnqCZdPscsKhRTZU8/4NfCp3xldOxjIR7Ex8+mdz+I
kCFgcrUMKx+h7KJivYTExJhtNWIwqlw8Ap4UGNVNEVxJk8L50We1zEJxaq57CYZvJwXEc9ktJEJP
RFMoaGYzYofkuGrIHPapP6+fOvFWW1GNNvgRLPUlnqO99c8ItpRXy023tBD/3x2gF3GncJeLp62+
31tL2y6fQ/W2VHuAYpMDgzl5z2h1TyNHkON59jnUzkCCiKzL2tXdfBfa4Vpq3HgVsiHcL/dkAc+8
1vDwPRoOejll3c0TW/9CUnZfpdiPGjAxAUVC6ZHY13x+IIanNV21ZCTDoQ2k78TRXqKlGKNJ87X1
VG88tP6evbKvkADCHSPIakugeOVbukXCR2hoIg7X3kmsH/iAuZTuDhaZOTEH37s3wSoZwyCQNgBx
3SiA8yVtfEKwncXwusn7azL+sQrY9dyyaMJN2rcrsm7oDkua+YnLcA4jWUDtrWV5xDCWy890LL9p
u9TJPtZ2Luk03jYChJKymO9UM0bgZX/ybXijUjAsCGAE5GuhaT554v3u5fdYepY4I8nXK6ab07+a
I2ODlvpkRhzmalfziOQ34QINOkefr3102TUvBpUjqjvxCCPui7RTUqzQ2KlxeHZzp/jN/vMpf5oA
Sm8JqpBQQbDY/mmxm3F4/gBr+3+M4uO/IqBGLiltg+xYHXFx7trSlusZeJjh6aMalAkIynXw+sbR
lAeJUJ5IPzzRBUvGbEVcRBP7qSuxkpSZOHcTrcSvEIgH97nmYdvYdEanmW+PVE3hXQIptC23mH7D
k+dneNNwbYcyPXDG12k7BHsGvfcgaVXYkbRWlG2bjk2ZXeHumQsQSsFO1cUeOXD7aeKMtyfHuIea
XUKmdQbsNbMX6epw/u4O4lsBNY/wYNBgeavti34b4R/Z07ksF5ey1hmRlH/2OIoSJyFxZvrfTFss
KIlILKuif4pfp+lBmaXSCXLD4diTIHYeHLpzkvQ9yiElH7FE4rDr0hT03dkZH34tB9P+jNP3N7Vp
7JaRjdjhGfo9uoGhY3Anq/SNAtDBsJUJDuZwj15a2kyQKxL129QrAONJ+QAvKl5HXtcimMn+pzRU
jx4+MfGcgqyomxVd7MIozIb+8X29RXdSMt98EJ59DT1xqNMpbha604KyYuS0/2U7MNFWtjTX8Eou
/nSsj7yuEAhGyZ4pef+VfO1lZ2FzPNfGhVsipTIYtg/6e3d1sqR/0hnUKFjFtBqTKAIWa/wV/adY
bwqBMVmZuJuoDj4dRXjUMw+4MK3YN6bA4ZuILIHZ0UHJURTeCh5v2hc6izJCeSNHpd+dAxV1lfyw
vLrHaxT32VFcn3ITx1c7I31d9ZztrOLehimR8N7lLFDfpGYk0ousHM6uh8Fe6HlKKHjesRtbLG6N
+FDxo82ZTUVqRSBVCfl4pmcN/jbuRNZGPPb0W40DODbCUmMoA1q3lP5lC0KQmv3V7UL6TLxaVuM4
qNaeM+j4iOmCAv4HM1rek+5RZuVNythckyCvJY6eW2ko+HzamxoVbOpjz40MKPpxn9gxf1pPdHMP
3B4dZT67LCz0uXEBMaIoKFhC4ljMzjn7iqdz7teL+aC8hxBeLL4qZCk7oQbIQ6rVFneIClSNpmPO
xtaod1TpeunF6SdHCJQUZrTFVJHZnbh/4kdOpZf9nuC6YvgnoqoqGUPXh/gjfXxKVsR+20KaKbl6
lzhDjDacXYki04uh5ruHHLgjX+dJCrftTHqq5tdHoZaVw6tdLqlUF4SQbtE4Dvjopo8+0WRWsP5S
i1g4b5ATdoE8s79Mhac2RMROMdkOehInxlgyD2cyVfo4fUks/8HH8OFZpq9MLZTMeGgpWxsbblcp
2WmP59ixMCv2hSNk94rIH3A28UEUZ0f3DFVujoi9Q+SE+aGGFVXBriPZQ1RuY/TM2tjA++MuTby9
5oEl5pybfDZ7qke27Yd1zyMMDwdvSaKNVKoghXImioC0mRuIZ0EWlzMwKAzWS5eHwxYUxLWo0dsj
KXFjtC/hyuze5yAmKJ4x6h3OfC/LO+N4ImBcZTr4rd45DrJeEFUBE5T+l0N3MTyC1h0Lx86b7WWo
XlJuXgMAxsnbrGLfBMsCr1tV4+VqBXsKv8WcS1ldU8EyPqeKa02g5tEmjCZlHU0JbAwHhzrH4ar3
z6vtShWzazoi6MmrCF/MCs8hsTVqrCUflu29CRN/A4qd3rEUUxHVlwJZJ05CjqkmXFJQDFGQnHOd
AQLQZtmCeSZCjjN78lIv9JVTPAVx86MycOS2EsjJWodDeXIfvUi3okKFBE/vl+HL+D+msLS1/Cbg
vkDxPngqCYIxt5fAZo1mL3i4BMWvVvpC7k+otqj7DuAs9kqUqHxHNp6wDsIcdYL03WDNChnnWSva
8mDv4y4cdEfVIPePhY/N6bM73Qxwz6xHrHoYGblZsXKnUTXRpjgVkQkVnFblAVGa4/6jH8BS+M6H
FcLH0JswTZwPGWwZ0bGjEEt7Mr8525MS9jthmPOn2mKG7tTzg1twrrPiFg7hDUJrJCyqgdOYxaP5
x7rKhRinYL8it6/PDAt4KqoWTlruUQDVD5HPIk0PHwybbgLWz+o8ZkKFsUZUTWQKxkyqBylfw8Jy
KeL0Ubo6LHGh1gj2vW40ZUa6jHN3jOdVNcngi23xgHuHNM7ME3gJNs9fu8Lkw7yWTb6uQIxjoqQy
Ugnru/2h/zmKVU16vuYO4opkdgi65rQjPBRXSXlaLHWG6JOr0Z019W8kCjRNFqRee3Km5arEHqQV
83If/HgQCLfZm73jYCi7aHv9QFKYV+/Hnlusg1nlKoQU4LwXMNpb3D9R/hHbZjib9r2zQYWeHnkT
Sbgn/MY4W1Hpz4CEJ05OWzUUiwTVclQ8P/U4iHpOhfd0pnyKya5hD21cI2dzaa4iP8qtI3aw7yt5
R9koT6tHwrHuAAnR/Xrmps98OVfkSlrLj1zeMIBkHP99WVy1BON3q8DrglFkta5GLAOLhpk5emRy
/BLexaKizyfeJjHbIjImpVqAnZ5w+oqWmtefefoGnTU4pSAhUu6PAiH+3ai81ezZHvbrY9JdnO2E
dAji87iNhlwpZGTV7+O4D2rjwlWS04SOnMYjqp0nCSmzmNiA0C73/3J+LgEJ8aYj7RGGGrMTAl5S
rDUxN0ouQK+5XXdqdSOPD+Z4aq/GmDfQkjvTiazaWITB+gFBJ9RWtfiroPqSGVfVbQ5jcD0vxf0P
FLgjqJqVjt65uu2F49goTbSk7hK+1j5MPjsg9VoV+jDtnS82aI21Ym1qKupT988x7VoZpBJWl8Gf
hq/S+RsYlIEfudVuqqQM7J13q+Frt3SbFZb9Ae9HagptkmqBvWrjvs+ulah/dTeizqnOvFT3F0q2
eMbWuWxJX5STlsCmyJXYKQ8bcJItJ3YwAoxqqcLAcO5baQXNdJpPJZOhEqMpO1+SOdhJpyvINvmv
bp6987RZabo4DH/F/NORt/KJyVxeZPeClX7AxfykN0VC5FJ1lQdJRkmdIPB/NDWyvc/G1zj7dxF0
XgYgw6AjF3tpguFYjExuUR1oPFFX2QFIGG66b4WrBG17rpNVPy6FMe0vgGs+16HqabaVBcGVNcfc
CGVtxpnKCudjSMAaCJQP5lJcoOfiZjSuvTpGyKLPBc13Cv3skArbjcxPkrZcVflKFy6/JlTKxJTF
a2wsaLGdESUaoZ9PGpGi1odAJywFDOcL3h3mOW73yzlp03a0WWc3h9aycV+BYyEKzyUzqVLL0U4s
mj+xhtxvns/JEUOMfM/WKCVkbuDW73C7MRk8/dfFWuOB1OdFaZu4DRN1Z3/qWGhFZ7Z7OCPtdViN
PnwXm/GWgZuzY7L7lPSg3bnp+UeGjI/hSf8pR6/XvoCZsMAuPL+eQmn9Q+kYqDvifDPMZH0RY/cq
81EVHEopVerMZOAB0OTb/nIucVRm5vBstzA53b+whEh09MX6suoW5K2pZQVvud82WdKbtOLzeNe3
3xuqFM+LZIeqrdiX7aqhUDnPczvA3y5+HVPVSDd9PxgZPfjcjNm0BHims5FZf5WB/dBRgw5VyaTO
LTyKUcWK0j6hQjj3YDEUrIZKBuiUn9NExh9x2w9HqHqQrQCb1iHXz2QlwNSwzJWS7yPzNYx2tJFb
65aMnxl72E2ZOMU74ig3vIHO8oid7P5YSxw2EUgwcLtggCJzgTktWQ7Mer88PN7jnM1WJoz6Iwp6
A69Xqlsr8DtGtm07t0D+FQBLwoDON+KGtQlQXSydFv0w0ufl20As4KyDIpiCEjqP1bIHG2wfU10C
z5Mc5mD/rcbHwOtsdhKDNezQlcLezVqhseRIkBnIF0h9yXA0N2nzLID3g10Z6W9F0CkHBRAtVX2M
9Ts3tdRqDDu8muZKOiUWlUD244sMOuAI3TTuMSGhjUTrHkHVN6+hspZArfuN3x0WGH6dz0V005bj
QKYaX/ItiWksdXSGJ8FMJ7uV/YjMjeQEKhIYsOQV1Mv1PmpWhePNLjQm+jmR7M+iZIwSX8IhBtjp
+8j1SkrjLoFy3xAB0eXiTW7OwJp/ViAyVZdZ2miox/+oUx28BVZSZW/F9VHfElV6/E4Ki+2+D2Mr
c54QTOBFaz8DvuHzqi0Augv6y2KinXWACd720tYOjpCSfGgzw+kB3ogYvMaIME1pXJDIEGoSxmnP
e+6x/GB+ks8glYSWN2MTn5BeTrnO+XDkX+dPzkc662mKZ3UY4eWHxiBg04iB0Gic+RJ9NOE5zaid
KZ9K2LBlqdBkC/mlJzFsUz9IEn4YFGsahtpR/Lo2SKqV98bFnVToRdHFCJsZ5JmjNfM5loscnv7g
F3ssskvsDi5LEotlYYoRSVtRRXLFKYV3lQJiVwLYgaIxc4AvOQqQ/ArqPMgvhRVfCxUmQGg0kYLy
evKX1ZB98nZ0mZjMxEwFxF4oXcwJp7lDiEClFJ96svXDLD2s85aHguGM5h4e7n0IRebbFAsWgoul
EZi0LDnpPbhXsZdKYW9sz+LMgQuRMgPGXD//iVyHUgVsCT7AaWV68irzqF+XJQCl9zpcyixZbCqR
xCOX/BVwpOu149Fgq6Ex5D1Na+iYc3QHbBkQmYDuidww0+07ihwcFaru9h9sSxyDOFeZedYXvOwZ
G8Gy8j/GRNBv48wrvTBcoArK1WNTicEpP00GDYO9cVODSot/drMudS60/h3+fU85EpriZJXsdU5R
ip+yhG3WdXI9iuJADeskM/P4p7EDnNRPKUpV0v50E1k1T2uBSQxHx2G/vrpjW+rZM5HmLRXFf14V
+opuWUCFnM77y2pv5WLvo4IYfHrgaHBImSBCxQSWxU5Gw6d9oBN+lBvzKmAqnPDyrsyoE25UH59d
ijYkvzFXcnr/Ceev0Jb6Z4LGjL2/zSzgfPdoVZoHLDGFRb0+u8gbv2fkMw7UNMpLSFLzIKTJ52Ao
X5rQOlzwb0qwpyNAhZ8qMJey3Ex0m/AJws1HSo5uEAj08Ui8RhWQwf1U4S9EG9Np908JQtW2Jfck
MAqTzSCZYs2LGA8Kkr+ka+wLRy/Pq5NlPHZ5cvv4ITyoXUZMRL1Y7VZtCeE5HB6hBjGE4UenJvha
0w+7yGIV7IIU5v5bA9jjHaPFTnW5hVeGDpW6cUj1CLNsOCqMHRLuHICi3Qo33y24BcbxlDpfoftI
n+/xyifDLAtAmBp89UBZqIX41HqCGmo/45ZE/NcvI/jcGmNZFFUmJ/LoWKLAhAMTNK7qU2nrAIGD
VS4q+ZRj1Ar6MVXoTJwFfx4teUHQDUGU+8bMl5icp4vYHNTR07wQahZvXyrXUDcqgCVXFCfZwJ9M
BhqFhXq8QsCXL5ojzTMrteZbd6Zo0aXtXQjuMFrnjgR8Ei11cvCRw4qq0Uc2YXD5i1AhOgneSCfd
MPsxM+Wl1JRc2nxEyJreg1uM/ccZoIAP+vswosVULG08gTYEHBzYNhmaExR1P4zX5ef38p88gGQp
tkGxWIfLybCwmAkiO49mDlCRPzQ7Fq7YERKMmfV4LFyV1UwwqmzBfjTLJfVB1RaFJ7v2kR22Ybp9
PBkViwPVM8w8jtpIht5J7Z4bfrsdk8zqpxKjDeKbAp2p4baxMPiRAXaQigjxeEB1QXZFljf7o4my
ojTQ9fFicq8I7hOeAKsswswXC9XTigCdl0KeyPs5my6qpfEfsxMET534mCcYpMZV77QGhNiooZZi
+v5KI9pC8DejAa6yqNezJep3i+87OwzVGY0z/0K9W+h3/7aLfkhB4PhkJxMpOnSPNSCmp31Aa+WO
W6QwGSh0j9qDcgc6IjUEzX4blFlsYjuMeB1ENi05SWNCnaQxW+j0WuKkpRDJvHfS8smh2Qer9LHA
ODQJiYAFO0hcPZFTz6vfz7BbXLkyCf4ctjA8hySo4+FEiEjTAM3updY3qUHau0i5pqW4+femKvcq
84LAtJKBW0XIo18IZ5ZTHbKChND0sJ/jY2mqRhCELaR7dsdq9NRe7AckWPp5Uc4XwaA9VY4eMAkc
J4uIeSG6+fSdw0NLJl078AQQDzNmdJagk13FN/UKqSexK6dvzleAsDkbezanwiwa4Q3Y7hXj89Em
na3b6qyryFKFaqv9Ja3FbPkBzO3VrhgPvJ6itV0yEa1GbLm6Rtgq4eOxF6HhGVHc8N6FjUbEfDvW
4Oj6awuJSNKgKg430S/qn/Lv3mVxYbpPwEj1aoE/w63EzmTNJ2NVviv54Anrt9PJTDRqQIdKr10+
jN9j49taP3r/Ew0/8spaJK2x3R+xx0QYOCEt8grM/znB0svci4nnAKDXXblnIL8vPML1cna4zwt6
fBuHO/mAirAP6lx6IW2S8cf53GQGIRU6a3w9Yb1O2QqpvHwiu5vm0z2rKCQYYY1rJdrdbQbjGKSc
+BCNQ138a2AKukQrDSiFsqc5ah9dxHWFUSagfuq6UEkApXcUjmJDSleuGMQEE2D3Q/G48gPcxPQp
akQd6uYPryvdmrm7sjv2E0yAtd8YW4MxmsPyhJK1wBvV0E1/LhY/KzIgLlAJlg+JwiZi1gMMNH4v
sUiV95cSqvnzv2VfghEHMvCCaeDdVyeP4bwBdNoi2LGQBDxrNmg8JjtrHz9ALnpsAm2kc/5PqwY9
LIguB39ykdx2sWzgwXc8Y30GW8wAn3Hn1XhyzJrE4jSG2oqz2KIFX9adlzCfa2jBsHM6A1PK0/mY
mN2FWjDEgsmHXYi5plyv+l3WeCgkE2nPwrCrVTkmYxK97YnC6ebJdgLx8sJfjqwklU37VJ2t5VoN
zRH3S/WoLry8K7Ewe+iYZy2ktY87WzS7zz2qyrOeLD23U2eeBFyeR40jkOjtHmZxLKNjJjF9rywA
oSxgp+4jxRFUxoMuMX4qSpsKwn/FhMbI7ksnOAZnSpkTlld/BoiNUFsiJBwqEzqZtB9hxi8KkTpl
zELqa2VcNU+vO51hGQlXmLViIHojmTNjW8XZrW4CQG0HMlOHrJkzdupudC0vwuB9nSBkcyLaDflX
QkNXveWhgUTC8xlknRmawgXOHEkz+b1Cg4K5wtYWOI5kwfBsjvjjYUbTOm8jWEt8Jcxhecl1eMTQ
rbvUuI/bVQLL7WjxU8JDYjykOfoVixEVn4Fkze/bZuDOQckzZcqahUVTK874+PwggfWzLh4Ve2wo
c/Q5WaX/Xs7Ov9QThy0iUKHWg3GXOZV1z+JsGYCGU6eYDnVqBBcnJpFSKk2nSR/YXlEInmFOc/Yz
sfkZjZ+xe3EoWJQwfyjPtls1Prjtjs85PEGS9GNdX9G7Ax98CsV7KdpZVs6KPHEx7ZAFFTNEr/UD
2xijuK4ItoUfUdiS+y3UeFwt7/esnMie0W7TUEbATyTE+NEktt8JlDygvUSBs7m4wwnniCr24bea
v4h9+tIJ61LDFVWy3wXJgkYMv5JrupfKEX9kU3J8t4bH1awtFhD6hJeL1NMrQqI7PVU9DhMMX9uK
RWGFkTUWOJPOKH7luIYzj9nG2lxgfGJ7UeSKdC7vNR5gC/Zpp/pBVKQahRLrG9GNwohc0VvRgypN
c6BedB/RXos5IfdV1Y5p5TD9W0+ShczIVlRz4GDeIEVExN4tYnyApR1WUHl8y+7ExSjyUQrCx2Jy
5utmtGtjZnNPfDUGhdU22CaMI/TaXYH1VNdfg6QW/uqR3MRKXgsKU1ZdMMj1nyCIwj2/9tCfB2DM
KQSVY1vf4DC1ncy3Q007iGWvtik7y6SmZHWRKLuuszbr1VjK4PlcwrO1jshvwqT5VJytulVPzk8u
It+7MkKtaM2mpaKx874eJ2QoXIbPfkXMV+714Vz1ccNbBfxLyqztVcDFYoLxB1l6e3Yhcj63pnhB
9qOAYmS53EER9F9kcFvgtybuWBTZ6JIN3cJpbuZAgKjosJG3Onw5XgDL+G+o1mb0f8nuwIwu2qhZ
ojHR5NTStQKyCtjea1S0+J7hrEUWhh4i+9rEZsc9VzoHnCLBYsrPGKy5kqrrYxwKGq5chI0uLj3b
WwrucmU1bC1rh9WvKsmQQB0vmddIZ4K96caaJMxo+gYUUVQa7C30xE9qjFdjEXqxLvMw4a5lDKQu
SrbJgH2SdiOEql/i6whMc3f0Ezl2sDkTGIhosH/tRpK3B8FWpp34qia7wtAjdeQo+ymr1adV25Iv
GlwLHzJjzFx2egtt0B7CaKqVZDQKIqV5pH63vNb8BLHk2apAbXiYZFvBv/v0G7XBIvz0JU5qanJ2
QBKuAAapCVxMd12yCGKDo+jV55IcTaRRlY5yHCnpAAWn3Qm5sQmy5eiAeE5GJEv0fjlwc5exxDoS
eGtEj0YELKKJs8JXn6UQ4+UH1pmCMRgw4BJWEE9XtxO5P8GdwoZWqab6c46uFkf81c06DGyratqA
LnDxRxA1TqTPRmbCU0xrn7HqlOElhR9xhohhETMIQKGVuHrujda4gcIW01xIfjlcZ6OmJaUNDMRD
nHh1MkN/TWYOp44rx1Eyhdnxss25PNd8NaB0U0wyMEieTjU6TnuDg4b2CLrkSntP+T8Sskk/HlhW
fYcTW6CqW/vCOyWn3okNPt3HcB3T5Rq16jf2Nt7X078WLH9jPD4nxWvxy24vPxR0IzLMeHvTCUTs
JjrWVFfXWrA962+JLy6gywVCda4N7SFigLL8xxvXMKdRrXLc0pIn8A70kEFoy5FHDMMu/E9PWkN7
laQ4Z92g0HEfn5BM0DQyAY4q2qP8IEeN9YdHNUg3ul/qbxVJb4dRy4dJ77UBJyAeunxevBR+SCDK
ATBlmwNqs2nuUrKwt2mBxjHBi0kriPFyGsCqlS0z5EgnBgE0s8G6sPAbZyn1gpcMAAb1TqQMn6px
IbxK70bfmE3JQf0TK+NEHUj1jFBKiXbjtj3VkaUrxfQfQxLeqar9sEKZjZ0y7MN+/ifBu4uRenZp
5Pk0KIFUYjqEztS56szdqM+GRxUMFdd1BTm57JiulQjMIVK6adfwYc9qBWit8TbqV6EAWiexup0i
31A6ZDApkUxNotizOD5oPHqpzygYGWeJFkN2RtBH91FuCOTHK82TOPGouDIPKiTaaz2pEVIDwvff
vRHNmBgKEDmvM6RRJB5bMu/TVdzkmwvPiVS1MJvVk3o91UcFsVk/37jXywsF6MaADpY9WNjx91KJ
Y3AdUDg8jGHHtkzjTZxFS55ifvomgaRmec+kP1UgzwqdiZe4awF63p6mfWyB6CWuv/dhN6H8wXx2
TrF+abenWWYcSi1sNmscQ7k2WDkpgCvcxTuQbKapTaZH3ZVQH0D88CdpvdhFfHb05m8dJDdfnFDr
1FlcYhA3N+eTUfTd9qLlNg1hZMjmP7Uuk7pddGluhAK6/mbvC/MsZzKd9F9um+i9YkJI4INm19ny
6tg4Y+NZXUC6kdXJ1InGIexr3RE/+pqNo/8pP6EWq+4jUuFz7DTB94KOlF3kKZtF0LVZBuw439Be
W+bNAtInQy092Ld30n1QA1XsVnY6GDrJcHs37PcXcvsmNv7rqkADkDg6gdMy/g1lsZgxf4LUNJWD
xbxWxUktdYIv+o+WYTq5FwowRBE9RI8jghcAjV8vq5ryoIWEgp44W5dLiuGXEyyXrXkFBIS3zuk7
mIChZwMJPVgZVox/hBcXrWpJ2q5aCJrwnqieC4rA5QHPw2fIsAYRWOTAAcHOThVpVw+gb0pXRPGp
KLMxWoLSUiyJjtCI7dpq5YhiDEwbOyQXiPlSc1HErDQGNcoS5GwjMomdghTUo1oPhJ9qWaA7UPep
cEMX4A+TmIaEkC+m2xetrf1VG3wcOtwXLrwM0/4HYG1g2L1DofowOZoT4SUm1c9QQ2AOMmggUspF
udOVpaAuCG49OEWIohvxTi4idelTTqQBywuiCNCFV/gkl7GqurHlCsEGTYaZNbiZ2R/YcQJHj1O1
mm/F3wAnomvYBb1O7L8LPYjI++wUYY7OQJQNHnZiZgJ7wUPXUIiY4RBZqdlb/uOk/aTOB3TkiFgu
gUGzjTh0eX1obdw/TjUpQXS1WlQd59QYmCjPhk9LbbSVv2kCTU63jvSa+YLMtiiT8SNaye8kivzm
FajNMSLf+Y6meaMxmkqTYVpLA82vmYdHY8nGb2Sgk+2bBpp50gdHOCxCtcIuRUWyhy4PHyxDMaH7
hKYuvlB9CaocMG7InT8iPVPWM5dSLF9/g2Jvi/CGaOlvmR1P6gg+iG4K61h6LB4HMGmEFsa8/fkV
f8fKS9CvhKGGtCFxsqo2GROGyrUvg+Dk1D7R2tgWwc+QrvIJl/NA0fEbwcMDwGbFM9zbmcOadgWe
eFGbVfUiurnFi9/lxNtmTXQm+A+uxz4MAsebHQ1DcjZRo+67Luq9w5qGcC6Qxp7QZr9HXitOqUC1
bVwrtWUfdl5CiXnFekZpZkJEP1Xy5oVepQKxcHWWbu3YnjY44I2MaOLNgALO+67LpVx8DMahkSO0
RaQqcfOwp2BLJAEZigJCRk7w0TKsY+2o+QnPc4Whg6Htovq7hN79ViCTuS8tVTBI+fzI6+zIPdR4
w9MQm5k+K4q/RlA=
`protect end_protected
|
mit
|
290c1f315364533832faeba25ae4207d
| 0.938823 | 1.889646 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd
| 4 | 3,073 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity control_section is
end entity control_section;
-- end not in book
architecture structural of control_section is
component reg is
generic ( width : positive );
port ( clk : in std_logic;
d : in std_logic_vector(0 to width - 1);
q : out std_logic_vector(0 to width - 1) );
end component reg;
for flag_reg : reg
use entity work.reg(gate_level)
port map ( clock => clk, data_in => d, data_out => q );
-- . . .
-- not in book
signal clock_phase1, zero_result, neg_result, overflow_result,
zero_flag, neg_flag, overflow_flag : std_logic;
-- end not in book
begin
flag_reg : component reg
generic map ( width => 3 )
port map ( clk => clock_phase1,
d(0) => zero_result, d(1) => neg_result,
d(2) => overflow_result,
q(0) => zero_flag, q(1) => neg_flag,
q(2) => overflow_flag );
-- . . .
-- not in book
stimulus : process is
begin
clock_phase1 <= '0';
zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
clock_phase1 <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture structural;
|
gpl-2.0
|
35971609d9f2319c3b475677d6d5a791
| 0.615034 | 3.369518 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd
| 4 | 3,016 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_11a is
end entity inline_11a;
architecture test of inline_11a is
constant v_pos : voltage := 15.0;
constant v_neg : voltage := -15.0;
terminal input : electrical;
quantity v_in across input;
quantity v_amplified : voltage;
constant gain : real := 1.0;
constant threshold_voltage : voltage := 0.6;
constant k : real := 0.0125;
terminal gate, source, drain : electrical;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgs across gate to source;
quantity vgd across gate to drain;
constant r_charge : resistance := 10_000.0;
constant r_discharge : resistance := 10_000.0;
constant charging : boolean := true;
terminal cap, plus, minus : electrical;
quantity v_plus := 10.0 across plus;
quantity v_minus := 0.0 across minus;
quantity v_cap across cap;
quantity i_charge through plus to cap;
quantity i_discharge through cap to minus;
begin
-- code from book
if v_in * gain > v_pos use -- incorrect
v_amplified == v_pos;
elsif v_in * gain < v_neg use -- incorrect
v_amplified == v_neg;
else
v_amplified == gain * v_in;
end use;
--
if vds'above(0.0) use -- transistor is forward biased
if not vgs'above(threshold_voltage) use -- cutoff region
ids == 0.0;
elsif vds'above(vgs - threshold_voltage) use -- saturation region
ids == 0.5 * k * (vgs - threshold_voltage)**2;
else -- linear/triode region
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end use;
else -- transistor is reverse biased
if not vgd 'above(threshold_voltage) use -- cutoff region
ids == 0.0;
elsif vsd'above(vgd - threshold_voltage) use -- saturation region
ids == -0.5 * k * (vgd - threshold_voltage)**2;
else -- linear/triode region
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end use;
end use;
--
if charging use
i_charge == ( v_plus - v_cap ) / r_charge;
i_discharge == 0.0;
else
i_charge == 0.0;
i_discharge == ( v_cap - v_minus ) / r_discharge;
end use;
-- end code from book
end architecture test;
|
gpl-2.0
|
9447ab1b0b3c72c84c834f6065127400
| 0.668103 | 3.68254 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd
| 4 | 2,284 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity zmux is
end entity zmux;
library util; use util.stimulus_generators.all;
architecture test of zmux is
signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
signal functional_z, equivalent_z : bit;
begin
functional_mux : block is
port ( z : out bit );
port map ( z => functional_z );
begin
-- code from book
zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
d1 when sel1 = '0' and sel0 = '1' else
d2 when sel1 = '1' and sel0 = '0' else
d3;
-- end code from book
end block functional_mux;
--------------------------------------------------
equivalent_mux : block is
port ( z : out bit );
port map ( z => equivalent_z );
begin
-- code from book
zmux : process is
begin
if sel1 = '0' and sel0 = '0' then
z <= d0;
elsif sel1 = '0' and sel0 = '1' then
z <= d1;
elsif sel1 = '1' and sel0 = '0' then
z <= d2;
else
z <= d3;
end if;
wait on d0, d1, d2, d3, sel0, sel1;
end process zmux;
-- end code from book
end block equivalent_mux;
--------------------------------------------------
stimulus :
all_possible_values( bv(0) => sel0, bv(1) => sel1,
bv(2) => d0, bv(3) => d1,
bv(4) => d2, bv(5) => d3,
delay_between_values => 10 ns );
verifier :
assert functional_z = equivalent_z
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
fab13eb1bf4fe8d9a91d48d41aeb3fc8
| 0.591944 | 3.666132 | false | false | false | false |
nickg/nvc
|
test/regress/record16.vhd
| 1 | 678 |
entity record16 is
end entity;
architecture test of record16 is
type rec is record
x : bit;
y : integer;
end record;
signal r : rec := ('1', 0);
procedure drive(signal s : out integer; value : in integer) is
begin
s <= value;
end procedure;
procedure read(signal s : in integer; value : out integer) is
begin
value := s;
end procedure;
begin
process is
variable x : integer;
begin
drive(r.y, 123);
wait for 1 ns;
assert r.y = 123;
read(r.y, x);
--report integer'image(x);
--assert x = 123;
wait;
end process;
end architecture;
|
gpl-3.0
|
00cf7667545168321c3e6973df016584
| 0.547198 | 3.874286 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue1137/testbench.vhdl
| 1 | 2,064 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity testbench is
end entity;
architecture simu of testbench is
-- Dummy control
signal clk : std_logic := '0';
signal simu_clock_enable : std_logic := '1';
-- Dummy source signal
signal data_src : std_logic_vector(1 downto 0) := "00";
-- Three destination signals
signal data_dst1 : std_logic_vector(1 downto 0) := "11";
signal data_dst2 : std_logic_vector(1 downto 0) := "11";
signal data_dst3 : std_logic_vector(1 downto 0) := "11";
signal data_dst4 : std_logic_vector(1 downto 0) := "11";
begin
-- Solution 1
-- THIS WORKS
process(all)
variable idx : integer;
begin
for c in 0 to 1 loop
idx := c;
data_dst1(idx) <= data_src(idx);
end loop;
end process;
-- Solution 2
-- FIXME THIS DOES NOT WORK, CREATES XXX
gen2 : for c in 0 to 1 generate
process(all)
variable idx : integer;
begin
idx := c;
data_dst2(idx) <= data_src(idx);
end process;
end generate;
-- Solution 4
-- THIS WORKS
gen4 : for c in 0 to 1 generate
process(all)
constant idx : integer := c;
begin
data_dst4(idx) <= data_src(idx);
end process;
end generate;
-- Solution 3
-- THIS WORKS
gen3 : for c in 0 to 1 generate
constant idx : integer := c;
begin
data_dst3(idx) <= data_src(idx);
end generate;
-- Dummy clock generation
clk <= (not clk) and simu_clock_enable after 5 ns;
-- Main testbench process
process
-- To print simulation messages
variable l : line;
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
write(l, string'("Result 1 : "));
write(l, to_string(data_dst1));
writeline(output, l);
write(l, string'("Result 2 : "));
write(l, to_string(data_dst2));
writeline(output, l);
write(l, string'("Result 3 : "));
write(l, to_string(data_dst3));
writeline(output, l);
write(l, string'("Result 4 : "));
write(l, to_string(data_dst4));
writeline(output, l);
simu_clock_enable <= '0';
end process;
end architecture;
|
gpl-2.0
|
665b9ce6f44f1f6e096c68232af18da4
| 0.641473 | 2.894811 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot
|
DE2Botv3Fall16Main/DIG_IN.vhd
| 1 | 879 |
-- DIG_IN.VHD (a peripheral module for SCOMP)
-- This module reads digital inputs directly, without debouncing
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY DIG_IN IS
PORT(
CS : IN STD_LOGIC;
DI : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DIG_IN;
ARCHITECTURE a OF DIG_IN IS
SIGNAL B_DI : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
-- Use LPM function to create bidirectional I/O data bus
IO_BUS: lpm_bustri
GENERIC MAP (
lpm_width => 16
)
PORT MAP (
data => B_DI,
enabledt => CS,
tridata => IO_DATA
);
PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(CS);
B_DI <= DI; -- sample the input on the rising edge of CS
END PROCESS;
END a;
|
mit
|
ee82b29b03b488c16521a7d0598288ed
| 0.577929 | 3.558704 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd
| 4 | 1,752 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1299.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p06n01i01299ent IS
END c08s04b00x00p06n01i01299ent;
ARCHITECTURE c08s04b00x00p06n01i01299arch OF c08s04b00x00p06n01i01299ent IS
signal X : integer := 5;
signal Y : integer := 3;
BEGIN
TESTING: PROCESS
BEGIN
Y <= X;
wait for 1 ns;
assert NOT( Y=5 )
report "***PASSED TEST: c08s04b00x00p06n01i01299"
severity NOTE;
assert ( Y=5 )
report "***FAILED TEST: c08s04b00x00p06n01i01299 - Signal assignment in a process block."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p06n01i01299arch;
|
gpl-2.0
|
c63e3e8d5cd594a8888c39b6d96cc576
| 0.66153 | 3.634855 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/issue964/tb_ent.vhdl
| 1 | 947 |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal dout : std_logic;
signal enable : std_logic;
signal reset : std_logic;
begin
dut: entity work.ent
port map (
enable => enable,
reset => reset,
q => dout,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
enable <= '1';
reset <= '1';
pulse;
assert dout = '0' severity failure;
enable <= '1';
reset <= '0';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '0' severity failure;
pulse;
assert dout = '1' severity failure;
enable <= '0';
pulse;
assert dout = '1' severity failure;
enable <= '1';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
94414e5c504e16ab104a69f92a1608e8
| 0.561774 | 3.56015 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff02/tb_dff08.vhdl
| 1 | 1,133 |
entity tb_dff08 is
end tb_dff08;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08 is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08
port map (
q => dout,
d => din,
en => en,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
en <= '1';
pulse;
assert dout = x"00" severity failure;
rst <= '0';
din <= x"38";
pulse;
assert dout = x"38" severity failure;
din <= x"af";
pulse;
assert dout = x"af" severity failure;
en <= '0';
din <= x"b3";
pulse;
assert dout = x"af" severity failure;
en <= '0';
rst <= '1';
din <= x"b4";
pulse;
assert dout = x"af" severity failure;
en <= '1';
rst <= '1';
din <= x"b5";
pulse;
assert dout = x"00" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ac8b81f4ec66a9279eed1321b2f28e00
| 0.53045 | 3.22792 | false | false | false | false |
nickg/nvc
|
test/sem/scope.vhd
| 1 | 7,780 |
package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.pack2;
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out pack2.my_int1 ); -- OK
end entity;
-------------------------------------------------------------------------------
architecture a of no_use_clause is
type my_int1 is range 10 to 50;
begin
process is
begin
-- Should fail as types have same name but from different packages
b <= a;
end process;
process is
variable v : pack2.my_int1;
begin
b <= v; -- OK
end process;
process is
variable v : my_int1;
begin
-- Should fail as local my_int1 distinct from pack1.my_int1
v := a;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack1.all;
entity foo is
generic ( g : my_int1 );
port ( p : in my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of foo is
-- Architecture decls exist in same scope as entity so this should
-- generate an error
signal g : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture b of foo is
-- Should also generate an error
signal p : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture c of foo is
begin
-- This is OK as processes define a new scope
process is
variable p : my_int1;
variable g : my_int1;
begin
g := 6;
p := 2;
wait for 1 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
entity overload is
port (
SI: in bit;
SO: out bit
);
end ;
architecture behave of overload is
begin
foo_inst:
SO <= SI;
end behave;
-------------------------------------------------------------------------------
use work.all; -- OK
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out my_int1 ); -- Error
end entity;
-------------------------------------------------------------------------------
package pack3 is
type my_enum is (E1, E2, E3);
end package;
-------------------------------------------------------------------------------
use work.pack3.all;
package pack4 is
type my_enum_array is array (integer range <>) of my_enum;
end package;
-------------------------------------------------------------------------------
use work.pack4.all;
architecture a of foo is
signal x : my_enum_array(1 to 3); -- OK
signal y : my_enum_array(1 to 3) := (others => E1);
-- Error: E1 not visible
begin
end architecture;
-------------------------------------------------------------------------------
package pack5 is
function func1(x : integer) return boolean;
function func2(x : integer) return boolean;
function "and"(x, y : integer) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack5.func1;
architecture a2 of foo is
begin
process is
begin
assert func1(4); -- OK
assert func2(5); -- Error
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack5.not_here; -- Error
architecture a3 of foo is
begin
end architecture;
-------------------------------------------------------------------------------
entity bar is
end entity;
architecture a4 of bar is
begin
process is
use work.pack1.all;
variable x : my_int1; -- OK
begin
x := 5;
end process;
process is
variable x : my_int1; -- Error
begin
end process;
b: block is
use work.pack1;
signal x : pack1.my_int1; -- OK
begin
end block;
end architecture;
-------------------------------------------------------------------------------
use work.pack5."and";
architecture a5 of bar is
begin
process is
begin
assert 1 and 2; -- OK
assert work.pack5."and"(1, 2); -- OK
assert pack5."and"(1, 2); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
package pack6 is
component bar is
end component;
end package;
-------------------------------------------------------------------------------
use work.pack6.all;
architecture a6 of bar is
begin
process is
begin
report bar'path_name; -- OK (references entity)
end process;
end architecture;
-------------------------------------------------------------------------------
use foo.bar.all; -- Error
architecture a7 of bar is
begin
end architecture;
-------------------------------------------------------------------------------
package pack7 is
function foo(x : in integer) return boolean;
function foo(y : in real) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack7.foo;
architecture issue62 of bar is
begin
process is
begin
assert foo(integer'(1)); -- OK
assert foo(real'(1.6)); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
use work.all;
use work.pack1.all;
architecture issue63 of bar is
signal x : my_int1; -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package pack8 is
function min(x, y : in integer) return integer;
end package;
-------------------------------------------------------------------------------
use work.pack8.all; -- OK
architecture unit_decl_crash of bar is
begin
process is
variable x : integer := min(1, 2); -- OK
begin
end process;
end architecture;
-------------------------------------------------------------------------------
architecture labels of bar is
signal mySignalVector: bit_vector (7 downto 0);
signal myOtherSignal: bit := '1';
begin
process
begin
L1:
for i in 0 to 9 loop
for i in 0 to 7 loop
mySignalVector(i) <= myOtherSignal;
report "outer loop i = " & integer'image(L1.i);
report "inner loop i = " & integer'image(i);
report integer'image(L1.x); -- Error
end loop;
end loop;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
architecture more_labels of bar is
begin
p1: process is
variable x : boolean;
begin
p1.x := true; -- OK
for x in 1 to 10 loop
p1.x := false; -- OK
end loop;
end process;
b1: block is
constant x : integer := 2;
begin
process is
variable x : boolean;
begin
x := true; -- OK
assert b1.x = 2; -- OK
end process;
end block;
end architecture;
|
gpl-3.0
|
9ba552aee6b8d567b8c44924a28d11ec
| 0.405013 | 4.829299 | false | false | false | false |
nickg/nvc
|
test/regress/driver11.vhd
| 1 | 890 |
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port ( x : inout std_logic );
end entity;
architecture test of sub is
begin
p1: process is
begin
x <= '1';
wait for 1 ns;
x <= '0';
wait for 0 ns;
assert x'active;
assert not x'event;
assert x = 'U';
x <= 'L';
wait for 0 ns;
assert x'active;
assert not x'event;
assert x = 'U';
assert x = x'last_value;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity driver11 is
end entity;
architecture test of driver11 is
signal y : std_logic;
begin
u: entity work.sub port map ( y );
p2: process is
begin
y <= 'U';
wait;
end process;
end architecture;
|
gpl-3.0
|
999bea18e1b7a368846490f532fe1186
| 0.498876 | 3.771186 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug090/hang8.vhdl
| 1 | 1,182 |
library ieee;
use ieee.s_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report 2start of tb" severity note;
for i in 0 to 10 loop
group i is
when 0 | 3 =>
for i in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 =>ehav;
|
gpl-2.0
|
4a957cc9b8b09bfd8c6693b7ce5a061e
| 0.587986 | 3.338983 | false | false | false | false |
nickg/nvc
|
test/parse/names2.vhd
| 1 | 913 |
entity names2 is
end entity;
architecture test of names2 is
type array1 is array (natural range <>) of integer;
type array2 is array (natural range <>) of array1(1 to 10);
type array3 is array (natural range <>) of array2(1 to 10);
type rec is record
x : array1(1 to 3);
y : integer;
end record;
function get_array3(n : integer) return array3;
function get_array2 return array2;
procedure do_rec(x : in rec);
type pt is protected
function get_array1(n : integer) return array1;
end protected;
begin
p1: process is
variable p : pt;
begin
assert get_array3(1)(2)(2)(3) = 1; -- OK
--assert get_array2(2)(3) = 1; -- OK (not yet)
assert p.get_array1(1)(2) = 1; -- OK
end process;
p2: process is
begin
do_rec(x.x => (1, 2, 3), x.y => 5); -- OK
end process;
end architecture;
|
gpl-3.0
|
83fbb6093a61882404f47fda23e73526
| 0.58379 | 3.32 | false | false | false | false |
nickg/nvc
|
test/regress/driver13.vhd
| 1 | 1,545 |
entity driver13 is
end entity;
architecture test of driver13 is
constant MAX_NAME_LENGTH : positive := 20;
type t_channel is (NA, ALL_CHANNELS, RX, TX);
type t_record_unresolved is record
trigger : bit;
vvc_name : string(1 to MAX_NAME_LENGTH);
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_record_unresolved := (
trigger => '0',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_record_drivers is array (natural range <> ) of t_record_unresolved;
function resolved ( input : t_record_drivers) return t_record_unresolved;
subtype t_record is resolved t_record_unresolved;
function resolved ( input : t_record_drivers) return t_record_unresolved is
variable v_result : t_record_unresolved := input(input'low);
begin
for i in input'range loop
report to_string(i) & ": trigger=" & to_string(input(i).trigger)
& " vvc_name=" & input(i).vvc_name;
assert input(i).vvc_name(1 to 5) = "hello"
or input(i).vvc_name(1 to 5) = "world"
or input(i).vvc_name(1 to 5) = (1 to 5 => NUL);
end loop;
return v_result;
end resolved;
signal s : t_record;
begin
p1: s <= ('0', ("hello", others => NUL), 1, RX);
p2: s <= ('1', ("world", others => NUL), 2, TX);
end architecture;
|
gpl-3.0
|
b798a725d780514b4ebc2b03122836f4
| 0.556634 | 3.593023 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd
| 4 | 1,647 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_01.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_01 is
end entity ch_03_01;
architecture test of ch_03_01 is
signal en : bit := '0';
signal data_in : integer := 0;
begin
process_3_1_a : process (en, data_in) is
variable stored_value : integer := 0;
begin
-- code from book:
if en = '1' then
stored_value := data_in;
end if;
-- end of code from book
end process process_3_1_a;
stimulus : process is
begin
en <= '1' after 10 ns, '0' after 20 ns;
data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
2f4b318d2980d07cbd51e55c09e32640
| 0.601093 | 3.893617 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
| 4 | 2,278 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity CalcBuckParams_wa is
generic ( Vin : voltage := 42.0; -- input voltage [Volts]
Vout : voltage := 4.8; -- output voltage [Volts]
Vd : voltage := 0.7; -- diode Voltage [Volts]
Imin : current := 15.0e-3; -- min output current [Amps]
Vripple : voltage := 100.0e-3; -- output voltage ripple [Volts]
Resr : resistance := 50.0e-3 );
port ( quantity Fsw : in real; -- switching frequency [Hz]
quantity Lmin : out inductance; -- minimum inductance [Henries]
quantity Cmin : out capacitance); -- minimum capacitance [Farads]
end entity CalcBuckParams_wa ;
----------------------------------------------------------------
architecture ideal of CalcBuckParams_wa is
constant D : real := (Vout + Vd)/(Vin + 1.0e-9); -- Duty Cycle
quantity Ts : real; -- Period
quantity Ton : real; -- On Time
quantity Fxo, Fp1, Fp2, Fz : real;
begin -- architecture behavioral
Ts == 1.0/(Fsw+1.0e-9);
Ton == D*Ts;
Lmin == (Vin - Vout) * Ton/(2.0*Imin);
Cmin == (2.0*Imin)/(8.0*Fsw*Vripple+1.0e-9);
-- Calculate compensator parameters
Fxo == Fsw/5.0; -- desired crossover frequency
Fp1 == Fxo * 1.5;
Fp2 == 1.0/(math_2_pi*Resr*Cmin*4.0+1.0e-9);
Fz == 1.0/(math_2_pi*sqrt(Lmin*Cmin*4.0)+1.0e-9);
end architecture ideal;
|
gpl-2.0
|
ba40afa2f5bda775714de46bab825c20
| 0.627744 | 3.531783 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/arr01/tb_arr02.vhdl
| 1 | 477 |
entity tb_arr02 is
end tb_arr02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr02 is
signal v : std_logic_vector(7 downto 0);
signal h : std_logic_vector(3 downto 0);
signal l : std_logic_vector(3 downto 0);
begin
dut: entity work.arr02
port map (v => v, h => h, l => l);
process
begin
v <= x"a7";
wait for 1 ns;
assert h = x"a" severity failure;
assert l = x"7" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
7396d0907a04fa1e84007d45d5afe4de
| 0.639413 | 2.98125 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1219/tb_top.vhdl
| 1 | 637 |
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal addr : std_logic_vector (1 downto 0);
signal data : std_logic_vector (2 downto 0);
begin
dut: entity work.top
port map (clk, addr, data);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
addr <= "00";
pulse;
assert data = "001" severity failure;
addr <= "10";
pulse;
assert data = "100" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
c1f1c560fb5aac233f98e0a6df516469
| 0.585557 | 3.424731 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd
| 4 | 1,984 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1206.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n04i01206ent IS
END c08s01b00x00p08n04i01206ent;
ARCHITECTURE c08s01b00x00p08n04i01206arch OF c08s01b00x00p08n04i01206ent IS
signal cll : integer := 0;
signal del : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
cll <= 5 after 55 ns;
del <= 5 after 55 ns;
wait until (cll = 5 or del = 5);
assert NOT( cll=5 )
report "***PASSED TEST: c08s01b00x00p08n04i01206"
severity NOTE;
assert ( cll=5 )
report "***FAILED TEST: c08s01b00x00p08n04i01206 - if no sensitivity clause appears, the sensitivity set will contain the signals denoted by the longest static prefix of each signal name that appears as a primary in the condition of the condirion clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n04i01206arch;
|
gpl-2.0
|
a882d0f9775c1ebfe3130c50c9eb4e3a
| 0.673891 | 3.708411 | false | true | false | false |
tgingold/ghdl
|
testsuite/gna/bug23165/mwe2/mwe.vhd
| 3 | 853 |
library ieee;
use ieee.std_logic_1164.all;
entity mwe is
end mwe;
architecture lulz of mwe is
type sig_t is array (0 to 1) of std_logic_vector(1 downto 0);
signal sigw : sig_t := (others => (others => '0'));
signal sigf : sig_t := (others => (others => '0'));
signal clk : std_logic := '0';
begin
clk <= not clk after 50 ns;
sigw(0) <= (others => '1');
sigf(0) <= (others => '1');
fail : process
variable i : integer range 0 to 0 := 0;
variable j : integer range 1 to 1 := 1;
begin
wait until rising_edge(clk);
sigf(j) <= sigf(i);
end process;
work : process
begin
wait until rising_edge(clk);
sigw(1) <= sigw(0);
end process;
process (sigf)
begin
report "sigf(1) = " & std_logic'image (sigf (0)(1));
assert now = 0 ns or sigf (0) = "XX" severity failure;
end process;
end lulz;
|
gpl-2.0
|
088920ab63ad4c3c240be18c138dc279
| 0.588511 | 2.778502 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/bug073/adder_tb2.vhdl
| 1 | 1,870 |
-- A testbench has no ports.
entity adder_tb2 is
end adder_tb2;
architecture behav of adder_tb2 is
-- Declaration of the component that will be instantiated.
component adder
port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
end component;
-- Specifies which entity is bound with the component.
for adder_0: adder use entity work.adder;
signal i0, i1, ci, s, co : bit;
begin
-- Component instantiation.
adder_0: entity work.adder port map (i0 => i0, i1 => i1, ci => ci,
s => s, co => co);
-- This process does the real job.
process
type pattern_type is record
-- The inputs of the adder.
i0, i1, ci : bit;
-- The expected outputs of the adder.
s, co : bit;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '0', '0', '0', '0'),
('0', '0', '1', '1', '0'),
('0', '1', '0', '1', '0'),
('0', '1', '1', '0', '1'),
('1', '0', '0', '1', '0'),
('1', '0', '1', '0', '1'),
('1', '1', '0', '0', '1'),
('1', '1', '1', '1', '1'));
begin
-- Check each pattern.
for i in patterns'range loop
-- Set the inputs.
i0 <= patterns(i).i0;
i1 <= patterns(i).i1;
ci <= patterns(i).ci;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert s = patterns(i).s
report "bad sum value" severity error;
assert co = patterns(i).co
report "bad carry out value" severity error;
end loop;
assert false report "end of test" severity note;
-- Wait forever; this will finish the simulation.
wait;
end process;
end behav;
|
gpl-2.0
|
b6c7ee25db8423c3944c5106be6a12d0
| 0.509626 | 3.469388 | false | false | false | false |
tgingold/ghdl
|
libraries/ieee2008/math_real.vhdl
| 3 | 21,134 |
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright IEEE P1076 WG. Licensed Apache 2.0";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
|
gpl-2.0
|
6da7f5d53b193683d09643ff60471ab9
| 0.498486 | 3.657667 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue618/e1.vhdl
| 1 | 220 |
entity e1 is end entity;
architecture a of e1 is
type t is range 0 to 1;
constant c :t := 7 - 6;
begin
assert c = 3 report "c /= 3" severity note;
assert c = t(3) report "c /= 3" severity note;
end architecture;
|
gpl-2.0
|
eeee2e5ca87e1e0ac9e8c45e7163a46d
| 0.65 | 3.098592 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue50/idct.d/sub_159.vhd
| 2 | 1,740 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_159 is
port (
gt : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end sub_159;
architecture augh of sub_159 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
gt <= not(tmp_le);
end architecture;
|
gpl-2.0
|
b737e7f908eb0fff2cc86f3979b06589
| 0.626437 | 2.597015 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue30/basicblocks.vhdl
| 2 | 192,556 |
library ieee;
use ieee.std_logic_1164.all;
package basicblocks_definitions is
constant period: time := 10 ns;
constant half_period: time := period / 2;
constant reset_time: time := 11 ns;
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.basicblocks_definitions.all;
-- FOR SIMULATION ONLY. NOT FOR PRODUCTION.
entity clkgen is
port(
clk_out: out std_logic;
resetn: out std_logic := '0'
);
end;
-- Tested 2016/01/19 with ghdl. works.
architecture struct_clkgen of clkgen is
begin
process begin
resetn <= '1' after reset_time;
clk_out <= '1';
wait for half_period;
clk_out <= '0';
wait for half_period;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity incrementer is
port(
input: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end;
-- tested with ghdl for N = 16 starting 2016/01/22, finished ?, works.
architecture struct_incrementer of incrementer is
begin
sum <= input xor carry_in;
carry_out <= input and carry_in;
end;
library ieee;
use ieee.std_logic_1164.all;
entity andNbit is
generic(
N: positive
);
port(
input: in std_logic_vector((N-1) downto 0);
y: out std_logic
);
end;
-- Tested as part of counter testing. Works.
architecture struct_andNbit of andNbit is
signal and_vector: std_logic_vector(N downto 0);
begin
and_vector(0) <= '1';
and_generator:
for i in 1 to N generate
and_vector(i) <= and_vector(i-1) and input(i-1);
end generate and_generator;
y <= and_vector(N);
end;
library ieee;
use ieee.std_logic_1164.all;
entity orNbit is
generic(
N: positive
);
port(
input: in std_logic_vector((N-1) downto 0);
y: out std_logic
);
end;
architecture struct_orNbit of orNbit is
signal or_vector: std_logic_vector(N downto 0);
begin
or_vector(0) <= '0';
or_generator:
for i in 1 to N generate
or_vector(i) <= or_vector(i-1) or input(i-1);
end generate or_generator;
y <= or_vector(N);
end;
library ieee;
use ieee.std_logic_1164.all;
entity incrementerN is
generic(
N: positive
);
port(
input: in std_logic_vector((N-1) downto 0);
carry_in: in std_logic;
sum: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end;
-- tested with ghdl at N = 16 starting 2016/01/22, finished ?, works.
architecture struct_incrementerN of incrementerN is
component incrementer is
port(
input: in std_logic;
carry_in: in std_logic;
sum: out std_logic;
carry_out: out std_logic
);
end component;
signal carry: std_logic_vector(N downto 0);
signal result: std_logic_vector((N-1) downto 0);
begin
carry(0) <= carry_in;
u1: for i in (N-1) downto 0 generate
u: incrementer port map(
input => input(i),
carry_in => carry(i),
sum => result(i),
carry_out => carry(i + 1)
);
end generate;
carry_out <= carry(N);
sum <= result;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x16 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
address: in std_logic_vector(3 downto 0)
);
end;
architecture struct_decoder1x16 of decoder1x16 is
begin
with address select y0 <= data when x"0", '0' when others;
with address select y1 <= data when x"1", '0' when others;
with address select y2 <= data when x"2", '0' when others;
with address select y3 <= data when x"3", '0' when others;
with address select y4 <= data when x"4", '0' when others;
with address select y5 <= data when x"5", '0' when others;
with address select y6 <= data when x"6", '0' when others;
with address select y7 <= data when x"7", '0' when others;
with address select y8 <= data when x"8", '0' when others;
with address select y9 <= data when x"9", '0' when others;
with address select y10 <= data when x"a", '0' when others;
with address select y11 <= data when x"b", '0' when others;
with address select y12 <= data when x"c", '0' when others;
with address select y13 <= data when x"d", '0' when others;
with address select y14 <= data when x"e", '0' when others;
with address select y15 <= data when x"f", '0' when others;
end;
-- For reasons unknown, ghdl appears to ignore the generic definition of N in this and only
-- this architecture. Error messages are generated at line 129 onwards. No unusual characters
-- found in the file where the first error message is generated.
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx16 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0);
y2: out std_logic_vector((N-1) downto 0);
y3: out std_logic_vector((N-1) downto 0);
y4: out std_logic_vector((N-1) downto 0);
y5: out std_logic_vector((N-1) downto 0);
y6: out std_logic_vector((N-1) downto 0);
y7: out std_logic_vector((N-1) downto 0);
y8: out std_logic_vector((N-1) downto 0);
y9: out std_logic_vector((N-1) downto 0);
y10: out std_logic_vector((N-1) downto 0);
y11: out std_logic_vector((N-1) downto 0);
y12: out std_logic_vector((N-1) downto 0);
y13: out std_logic_vector((N-1) downto 0);
y14: out std_logic_vector((N-1) downto 0);
y15: out std_logic_vector((N-1) downto 0);
address: in std_logic_vector(3 downto 0)
);
end;
architecture struct_decoderNx16 of decoderNx16 is
component decoder1x16 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
address: in std_logic_vector(3 downto 0)
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: decoder1x16 port map(
data => data(i),
y0 => y0(i),
y1 => y1(i),
y2 => y2(i),
y3 => y3(i),
y4 => y4(i),
y5 => y5(i),
y6 => y6(i),
y7 => y7(i),
y8 => y8(i),
y9 => y9(i),
y10 => y10(i),
y11 => y11(i),
y12 => y12(i),
y13 => y13(i),
y14 => y14(i),
y15 => y15(i),
address => address
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x2 is
port(
data: in std_logic;
selector: in std_logic;
y0: out std_logic;
y1: out std_logic
);
end;
-- Tested 2015/12/04 with Modelsim. Works.
architecture struct_decoder1x2 of decoder1x2 is
begin
with selector select y0 <= data when '0', '0' when others;
with selector select y1 <= data when '1', '0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx2 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/27 at N = 8 with modelsim. works.
-- tested 2016/01/23 at N = 8 with ghdl. works.
architecture struct_decoderNx2 of decoderNx2 is
component decoder1x2 is
port(
data: in std_logic;
selector: in std_logic;
y0: out std_logic;
y1: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: decoder1x2 port map(
data => data(i),
selector => selector,
y0 => y0(i),
y1 => y1(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder2x1oe is
port(
data0, data1: in std_logic;
selector: in std_logic;
enable: in std_logic;
output: out std_logic
);
end;
-- tested during testing of encoder2xNoe, works.
architecture struct_encoder2x1oe of encoder2x1oe is
begin
with selector select
output <= (data0 and enable) when '0',
(data1 and enable) when '1',
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder2xN_oe is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
enable: in std_logic;
output: out std_logic_vector((N-1) downto 0)
);
end;
architecture struct_encoder2xN_oe of encoder2xN_oe is
component encoder2x1oe is
port(
data0: in std_logic;
data1: in std_logic;
selector: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder2x1oe port map(
data0 => data0(i),
data1 => data1(i),
selector => selector,
enable => enable,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder2x1 is
port(
data0: in std_logic;
data1: in std_logic;
selector: in std_logic;
output: out std_logic
);
end;
-- tested during double register pair testing 2015/12/03. Works.
architecture struct_encoder2x1 of encoder2x1 is
begin
with selector select
output <= data0 when '0',
data1 when '1',
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder2xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
selector: in std_logic;
output: out std_logic_vector((N-1) downto 0)
);
end;
-- tested during double register pair testing 2015/12/03. Works for N = 8.
-- also tested during alu testing. works there too.
architecture struct_encoder2xN of encoder2xN is
component encoder2x1 is
port(
data0: in std_logic;
data1: in std_logic;
selector: in std_logic;
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder2x1 port map(
data0 => data0(i),
data1 => data1(i),
selector => selector,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity synchronous_latch is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end;
-- Tested 2016/11/21, works on Modelsim simulator.
architecture struct_synchronous_latch of synchronous_latch is
begin
process(rstn, clock, clock_enable)
variable datum: std_logic;
begin
if rstn = '0' then
datum := '0';
elsif rising_edge(clock) then
if clock_enable = '1' then
datum := d;
end if;
end if;
q <= datum;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
-- library altera;
-- use altera.altera_primitives_components.all;
entity synchronous_latchN is
generic(
N: positive
);
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic_vector((N-1) downto 0);
q: out std_logic_vector((N-1) downto 0)
);
end;
-- Tested 2016/11/21, works on Modelsim simulator.
architecture struct_synchronous_latchN of synchronous_latchN is
component synchronous_latch is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
begin
u1: for i in 0 to (N-1) generate
u: synchronous_latch port map(
rstn => rstn,
clock => clock,
clock_enable => clock_enable,
d => d(i),
q => q(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity synchronous_latch_oe is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
oe: in std_logic;
d: in std_logic;
q: out std_logic
);
end;
-- tested 2015/12/27 as part of testing synchronous_latchN_oe. works.
architecture struct_synchronous_latch_oe of synchronous_latch_oe is
begin
process(rstn, clock, clock_enable, oe)
variable datum: std_logic;
begin
if rstn = '0' then
datum := '0';
elsif rising_edge(clock) then
if clock_enable = '1' then
datum := d;
end if;
end if;
if oe = '1' then
q <= datum;
else
q <= 'Z';
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity synchronous_latchN_oe is
generic(
N: positive
);
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
oe: in std_logic;
d: in std_logic_vector((N-1) downto 0);
q: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/27, N = 8 with modelsim. works.
architecture struct_synchronous_latchN_oe of synchronous_latchN_oe is
component synchronous_latch_oe is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
oe: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: synchronous_latch_oe port map(
rstn => rstn,
clock => clock,
clock_enable => clock_enable,
oe => oe,
d => d(i),
q => q(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity synchronous_latch_autoclear is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end;
-- Tested 2016/11/21, works on Modelsim simulator.
architecture struct_synchronous_latch_autoclear of synchronous_latch_autoclear is
begin
process(rstn, clock)
variable datum: std_logic;
begin
if rstn = '0' then
datum := '0';
elsif rising_edge(clock) then
if clock_enable = '1' then
if datum = '1' then
datum := '0';
else
datum := d;
end if;
else
datum := '0';
end if;
end if;
q <= datum;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder4x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
address: in std_logic_vector(1 downto 0);
output: out std_logic
);
end;
-- tested 2015/12/26 with modelsim as part of encoder4xN, works.
architecture struct_encoder4x1 of encoder4x1 is
begin
with address select
output <= data0 when "00",
data1 when "01",
data2 when "10",
data3 when "11",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder4xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(1 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/26 with modelsim at N = 16, works.
architecture struct_encoder4xN of encoder4xN is
component encoder4x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
address: in std_logic_vector(1 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder4x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder8x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
address: in std_logic_vector(2 downto 0);
output: out std_logic
);
end;
-- tested 2015/12/26 as part of encoder8xN with modelsim, works.
architecture struct_encoder8x1 of encoder8x1 is
begin
with address select
output <= data0 when "000",
data1 when "001",
data2 when "010",
data3 when "011",
data4 when "100",
data5 when "101",
data6 when "110",
data7 when "111",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder8xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(2 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/26 for N = 8 with modelsim, works.
architecture struct_encoder8xN of encoder8xN is
component encoder8x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
address: in std_logic_vector(2 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder8x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
data4 => data4(i),
data5 => data5(i),
data6 => data6(i),
data7 => data7(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x8 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
address: in std_logic_vector(2 downto 0)
);
end;
-- tested 2015/12/30 with modelsim as part of decoderNx8, works.
architecture struct_decoder1x8 of decoder1x8 is
begin
with address select y0 <= data when "000", '0' when others;
with address select y1 <= data when "001", '0' when others;
with address select y2 <= data when "010", '0' when others;
with address select y3 <= data when "011", '0' when others;
with address select y4 <= data when "100", '0' when others;
with address select y5 <= data when "101", '0' when others;
with address select y6 <= data when "110", '0' when others;
with address select y7 <= data when "111", '0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx8 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0);
y2: out std_logic_vector((N-1) downto 0);
y3: out std_logic_vector((N-1) downto 0);
y4: out std_logic_vector((N-1) downto 0);
y5: out std_logic_vector((N-1) downto 0);
y6: out std_logic_vector((N-1) downto 0);
y7: out std_logic_vector((N-1) downto 0);
address: in std_logic_vector(2 downto 0)
);
end;
-- tested 2015/12/30 with modelsim, works.
architecture struct_decoderNx8 of decoderNx8 is
component decoder1x8 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
address: in std_logic_vector(2 downto 0)
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: decoder1x8 port map(
data => data(i),
y0 => y0(i),
y1 => y1(i),
y2 => y2(i),
y3 => y3(i),
y4 => y4(i),
y5 => y5(i),
y6 => y6(i),
y7 => y7(i),
address=> address
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder16x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
address: in std_logic_vector(3 downto 0);
output: out std_logic
);
end;
-- tested with Modelsim 2015/12/24 as part of encoder16xN, works with N = 8.
architecture struct_encoder16x1 of encoder16x1 is
begin
with address select
output <= data0 when "0000",
data1 when "0001",
data2 when "0010",
data3 when "0011",
data4 when "0100",
data5 when "0101",
data6 when "0110",
data7 when "0111",
data8 when "1000",
data9 when "1001",
data10 when "1010",
data11 when "1011",
data12 when "1100",
data13 when "1101",
data14 when "1110",
data15 when "1111",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder16xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(3 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
-- tested with Modelsim 2015/12/24, works with N = 8.
architecture struct_encoder16xN of encoder16xN is
component encoder16x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
address: in std_logic_vector(3 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder16x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
data4 => data4(i),
data5 => data5(i),
data6 => data6(i),
data7 => data7(i),
data8 => data8(i),
data9 => data9(i),
data10 => data10(i),
data11 => data11(i),
data12 => data12(i),
data13 => data13(i),
data14 => data14(i),
data15 => data15(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder32x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
address: in std_logic_vector(4 downto 0);
output: out std_logic
);
end;
-- tested 2015/12/24 as part of testing encoder32xN. Works.
architecture struct_encoder32x1 of encoder32x1 is
begin
with address select
output <= data0 when "00000",
data1 when "00001",
data2 when "00010",
data3 when "00011",
data4 when "00100",
data5 when "00101",
data6 when "00110",
data7 when "00111",
data8 when "01000",
data9 when "01001",
data10 when "01010",
data11 when "01011",
data12 when "01100",
data13 when "01101",
data14 when "01110",
data15 when "01111",
data16 when "10000",
data17 when "10001",
data18 when "10010",
data19 when "10011",
data20 when "10100",
data21 when "10101",
data22 when "10110",
data23 when "10111",
data24 when "11000",
data25 when "11001",
data26 when "11010",
data27 when "11011",
data28 when "11100",
data29 when "11101",
data30 when "11110",
data31 when "11111",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder32xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(4 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/24 with N = 8. Works.
architecture struct_encoder32xN of encoder32xN is
component encoder32x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
address: in std_logic_vector(4 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder32x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
data4 => data4(i),
data5 => data5(i),
data6 => data6(i),
data7 => data7(i),
data8 => data8(i),
data9 => data9(i),
data10 => data10(i),
data11 => data11(i),
data12 => data12(i),
data13 => data13(i),
data14 => data14(i),
data15 => data15(i),
data16 => data16(i),
data17 => data17(i),
data18 => data18(i),
data19 => data19(i),
data20 => data20(i),
data21 => data21(i),
data22 => data22(i),
data23 => data23(i),
data24 => data24(i),
data25 => data25(i),
data26 => data26(i),
data27 => data27(i),
data28 => data28(i),
data29 => data29(i),
data30 => data30(i),
data31 => data31(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity tristate is
port(
a: in std_logic;
enable: in std_logic;
y: out std_logic
);
end;
-- tested 2015/12/27 with modelsim as part of tristateN testing. works.
-- tested 2016/01/23 with ghdl as part of tristateN testing. works.
architecture struct_tristate of tristate is
begin
y <= a when enable = '1' else 'Z';
end;
library ieee;
use ieee.std_logic_1164.all;
entity tristateN is
generic(
N: positive
);
port(
a: in std_logic_vector((N-1) downto 0);
enable: in std_logic;
y: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/27 at N = 16 with modelsim. works.
-- tested 2016/01/23 at N = 16 with ghdl. works.
architecture struct_tristateN of tristateN is
component tristate is
port(
a: in std_logic;
enable: in std_logic;
y: out std_logic
);
end component;
begin
u1: for i in 0 to (N-1) generate
u: tristate port map(
a => a(i),
enable => enable,
y => y(i)
);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity toggle_ff is
port(
clk: in std_logic;
clock_enable: in std_logic;
resetn: in std_logic;
q: out std_logic
);
end;
-- tested 2015/12/26 with modelsim, works.
architecture struct_toggle_ff of toggle_ff is
component synchronous_latch is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
component synchronous_latch_autoclear is
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
component encoder2x1 is
port(
data0: in std_logic;
data1: in std_logic;
selector: in std_logic;
output: out std_logic
);
end component;
signal toggle_output: std_logic;
signal toggle_clock: std_logic;
signal flipflop_data: std_logic;
signal not_toggle_output: std_logic;
signal notclock: std_logic;
begin
u1: synchronous_latch port map(
rstn => resetn,
clock => clk,
clock_enable => toggle_clock,
d => flipflop_data,
q => toggle_output
);
u2: encoder2x1 port map(
data0 => toggle_output,
data1 => not_toggle_output,
selector => toggle_clock,
output => flipflop_data
);
u3: synchronous_latch_autoclear port map(
rstn => resetn,
clock => notclock,
clock_enable => clock_enable,
d => clock_enable,
q => toggle_clock
);
not_toggle_output <= not toggle_output;
notclock <= not clk;
q <= toggle_output;
end;
library ieee;
use ieee.std_logic_1164.all;
entity magnitude is
port(
a, b: in std_logic;
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end;
-- tested 2015/12/26 with modelsim, works.
architecture struct_magnitude of magnitude is
signal equals: std_logic;
signal less: std_logic;
begin
equals <= not (a xor b);
less <= (not a) and b;
gt <= equals nor less;
equal <= equals;
lt <= less;
end;
library ieee;
use ieee.std_logic_1164.all;
entity magnitudeN is
generic(
N: positive
);
port(
a, b: in std_logic_vector((N-1) downto 0);
equal: out std_logic;
lt: out std_logic; -- '1' if a < b
gt: out std_logic -- '1' if a > b
);
end;
--tested with ghdl 2016/01/26, works.
architecture struct_magnitudeN of magnitudeN is
signal equals: std_logic_vector((N-1) downto 0);
signal less: std_logic_vector((N-1) downto 0);
begin
equals(N-1) <= not (a(N-1) xor b(N-1));
less (N-1) <= (not a(N-1)) and b(N-1);
u1: for i in (N-1) downto 1 generate
equals(i-1) <= equals(i) and (not (a(i-1) xor b(i-1)));
less(i-1) <= less(i) or (((not a(i-1)) and b(i-1)) and equals(i));
end generate u1;
equal <= equals(0);
lt <= less(0);
gt <= equals(0) nor less(0);
end;
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude2 is
--port(
-- a, b: in std_logic_vector(1 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--
--architecture struct_magnitude2 of magnitude2 is
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(1),
-- b => b(1),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude port map(
-- a => a(0),
-- b => b(0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
--
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude3 is
--port(
-- a, b: in std_logic_vector(2 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--
--architecture struct_magnitude3 of magnitude3 is
--component magnitude2 is
--port(
-- a, b: in std_logic_vector(1 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(2),
-- b => b(2),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude2 port map(
-- a => a(1 downto 0),
-- b => b(1 downto 0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
--
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude4 is
--port(
-- a, b: in std_logic_vector(3 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--
--architecture struct_magnitude4 of magnitude4 is
--component magnitude3 is
--port(
-- a, b: in std_logic_vector(2 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(3),
-- b => b(3),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude3 port map(
-- a => a(2 downto 0),
-- b => b(2 downto 0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
--
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude5 is
--port(
-- a, b: in std_logic_vector(4 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--
--architecture struct_magnitude5 of magnitude5 is
--component magnitude4 is
--port(
-- a, b: in std_logic_vector(3 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(4),
-- b => b(4),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude4 port map(
-- a => a(3 downto 0),
-- b => b(3 downto 0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
--
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude6 is
--port(
-- a, b: in std_logic_vector(5 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--
--architecture struct_magnitude6 of magnitude6 is
--component magnitude5 is
--port(
-- a, b: in std_logic_vector(4 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(5),
-- b => b(5),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude5 port map(
-- a => a(4 downto 0),
-- b => b(4 downto 0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
--
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude7 is
--port(
-- a, b: in std_logic_vector(6 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--
--architecture struct_magnitude7 of magnitude7 is
--component magnitude6 is
--port(
-- a, b: in std_logic_vector(5 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(6),
-- b => b(6),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude6 port map(
-- a => a(5 downto 0),
-- b => b(5 downto 0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
--
--library ieee;
--use ieee.std_logic_1164.all;
--
--entity magnitude8 is
--port(
-- a, b: in std_logic_vector(7 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end;
--
---- tested 2015/12/26 with modelsim, works.
--architecture struct_magnitude8 of magnitude8 is
--component magnitude7 is
--port(
-- a, b: in std_logic_vector(6 downto 0);
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--component magnitude is
--port(
-- a, b: in std_logic;
-- equal: out std_logic;
-- lt: out std_logic; -- '1' if a < b
-- gt: out std_logic -- '1' if a > b
--);
--end component;
--
--signal high_equals: std_logic;
--signal high_lt: std_logic;
--signal high_gt: std_logic;
--
--signal low_equals: std_logic;
--signal low_lt: std_logic;
--signal low_gt: std_logic;
--
--signal equals: std_logic;
--signal less: std_logic;
--
--begin
-- u1: magnitude port map(
-- a => a(7),
-- b => b(7),
-- equal => high_equals,
-- lt => high_lt,
-- gt => high_gt
-- );
--
-- u2: magnitude7 port map(
-- a => a(6 downto 0),
-- b => b(6 downto 0),
-- equal => low_equals,
-- lt => low_lt,
-- gt => low_gt
-- );
--
-- equals <= high_equals and low_equals;
-- less <= high_lt or (high_equals and low_lt);
-- gt <= equals nor less;
-- equal <= equals;
-- lt <= less;
--end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder64x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
data32: in std_logic;
data33: in std_logic;
data34: in std_logic;
data35: in std_logic;
data36: in std_logic;
data37: in std_logic;
data38: in std_logic;
data39: in std_logic;
data40: in std_logic;
data41: in std_logic;
data42: in std_logic;
data43: in std_logic;
data44: in std_logic;
data45: in std_logic;
data46: in std_logic;
data47: in std_logic;
data48: in std_logic;
data49: in std_logic;
data50: in std_logic;
data51: in std_logic;
data52: in std_logic;
data53: in std_logic;
data54: in std_logic;
data55: in std_logic;
data56: in std_logic;
data57: in std_logic;
data58: in std_logic;
data59: in std_logic;
data60: in std_logic;
data61: in std_logic;
data62: in std_logic;
data63: in std_logic;
address: in std_logic_vector(5 downto 0);
output: out std_logic
);
end;
-- tested 2015/12/24 with modelsim as part of encoder64xN. works.
architecture struct_encoder64x1 of encoder64x1 is
begin
with address select
output <=
data0 when "000000",
data1 when "000001",
data2 when "000010",
data3 when "000011",
data4 when "000100",
data5 when "000101",
data6 when "000110",
data7 when "000111",
data8 when "001000",
data9 when "001001",
data10 when "001010",
data11 when "001011",
data12 when "001100",
data13 when "001101",
data14 when "001110",
data15 when "001111",
data16 when "010000",
data17 when "010001",
data18 when "010010",
data19 when "010011",
data20 when "010100",
data21 when "010101",
data22 when "010110",
data23 when "010111",
data24 when "011000",
data25 when "011001",
data26 when "011010",
data27 when "011011",
data28 when "011100",
data29 when "011101",
data30 when "011110",
data31 when "011111",
data32 when "100000",
data33 when "100001",
data34 when "100010",
data35 when "100011",
data36 when "100100",
data37 when "100101",
data38 when "100110",
data39 when "100111",
data40 when "101000",
data41 when "101001",
data42 when "101010",
data43 when "101011",
data44 when "101100",
data45 when "101101",
data46 when "101110",
data47 when "101111",
data48 when "110000",
data49 when "110001",
data50 when "110010",
data51 when "110011",
data52 when "110100",
data53 when "110101",
data54 when "110110",
data55 when "110111",
data56 when "111000",
data57 when "111001",
data58 when "111010",
data59 when "111011",
data60 when "111100",
data61 when "111101",
data62 when "111110",
data63 when "111111",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder64xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
data32: in std_logic_vector((N-1) downto 0);
data33: in std_logic_vector((N-1) downto 0);
data34: in std_logic_vector((N-1) downto 0);
data35: in std_logic_vector((N-1) downto 0);
data36: in std_logic_vector((N-1) downto 0);
data37: in std_logic_vector((N-1) downto 0);
data38: in std_logic_vector((N-1) downto 0);
data39: in std_logic_vector((N-1) downto 0);
data40: in std_logic_vector((N-1) downto 0);
data41: in std_logic_vector((N-1) downto 0);
data42: in std_logic_vector((N-1) downto 0);
data43: in std_logic_vector((N-1) downto 0);
data44: in std_logic_vector((N-1) downto 0);
data45: in std_logic_vector((N-1) downto 0);
data46: in std_logic_vector((N-1) downto 0);
data47: in std_logic_vector((N-1) downto 0);
data48: in std_logic_vector((N-1) downto 0);
data49: in std_logic_vector((N-1) downto 0);
data50: in std_logic_vector((N-1) downto 0);
data51: in std_logic_vector((N-1) downto 0);
data52: in std_logic_vector((N-1) downto 0);
data53: in std_logic_vector((N-1) downto 0);
data54: in std_logic_vector((N-1) downto 0);
data55: in std_logic_vector((N-1) downto 0);
data56: in std_logic_vector((N-1) downto 0);
data57: in std_logic_vector((N-1) downto 0);
data58: in std_logic_vector((N-1) downto 0);
data59: in std_logic_vector((N-1) downto 0);
data60: in std_logic_vector((N-1) downto 0);
data61: in std_logic_vector((N-1) downto 0);
data62: in std_logic_vector((N-1) downto 0);
data63: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(5 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
-- tested 2015/12/24 with modelsim and N = 8. works.
architecture struct_encoder64xN of encoder64xN is
component encoder64x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
data32: in std_logic;
data33: in std_logic;
data34: in std_logic;
data35: in std_logic;
data36: in std_logic;
data37: in std_logic;
data38: in std_logic;
data39: in std_logic;
data40: in std_logic;
data41: in std_logic;
data42: in std_logic;
data43: in std_logic;
data44: in std_logic;
data45: in std_logic;
data46: in std_logic;
data47: in std_logic;
data48: in std_logic;
data49: in std_logic;
data50: in std_logic;
data51: in std_logic;
data52: in std_logic;
data53: in std_logic;
data54: in std_logic;
data55: in std_logic;
data56: in std_logic;
data57: in std_logic;
data58: in std_logic;
data59: in std_logic;
data60: in std_logic;
data61: in std_logic;
data62: in std_logic;
data63: in std_logic;
address: in std_logic_vector(5 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in 0 to (N-1) generate
u: encoder64x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
data4 => data4(i),
data5 => data5(i),
data6 => data6(i),
data7 => data7(i),
data8 => data8(i),
data9 => data9(i),
data10 => data10(i),
data11 => data11(i),
data12 => data12(i),
data13 => data13(i),
data14 => data14(i),
data15 => data15(i),
data16 => data16(i),
data17 => data17(i),
data18 => data18(i),
data19 => data19(i),
data20 => data20(i),
data21 => data21(i),
data22 => data22(i),
data23 => data23(i),
data24 => data24(i),
data25 => data25(i),
data26 => data26(i),
data27 => data27(i),
data28 => data28(i),
data29 => data29(i),
data30 => data30(i),
data31 => data31(i),
data32 => data32(i),
data33 => data33(i),
data34 => data34(i),
data35 => data35(i),
data36 => data36(i),
data37 => data37(i),
data38 => data38(i),
data39 => data39(i),
data40 => data40(i),
data41 => data41(i),
data42 => data42(i),
data43 => data43(i),
data44 => data44(i),
data45 => data45(i),
data46 => data46(i),
data47 => data47(i),
data48 => data48(i),
data49 => data49(i),
data50 => data50(i),
data51 => data51(i),
data52 => data52(i),
data53 => data53(i),
data54 => data54(i),
data55 => data55(i),
data56 => data56(i),
data57 => data57(i),
data58 => data58(i),
data59 => data59(i),
data60 => data60(i),
data61 => data61(i),
data62 => data62(i),
data63 => data63(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x64 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
y32: out std_logic;
y33: out std_logic;
y34: out std_logic;
y35: out std_logic;
y36: out std_logic;
y37: out std_logic;
y38: out std_logic;
y39: out std_logic;
y40: out std_logic;
y41: out std_logic;
y42: out std_logic;
y43: out std_logic;
y44: out std_logic;
y45: out std_logic;
y46: out std_logic;
y47: out std_logic;
y48: out std_logic;
y49: out std_logic;
y50: out std_logic;
y51: out std_logic;
y52: out std_logic;
y53: out std_logic;
y54: out std_logic;
y55: out std_logic;
y56: out std_logic;
y57: out std_logic;
y58: out std_logic;
y59: out std_logic;
y60: out std_logic;
y61: out std_logic;
y62: out std_logic;
y63: out std_logic;
address: in std_logic_vector(5 downto 0)
);
end;
-- tested 2015/12/26 as part of decoderNx64 using modelsim. works.
architecture struct_decoder1x64 of decoder1x64 is
begin
with address select y0 <= data when "000000", '0' when others;
with address select y1 <= data when "000001", '0' when others;
with address select y2 <= data when "000010", '0' when others;
with address select y3 <= data when "000011", '0' when others;
with address select y4 <= data when "000100", '0' when others;
with address select y5 <= data when "000101", '0' when others;
with address select y6 <= data when "000110", '0' when others;
with address select y7 <= data when "000111", '0' when others;
with address select y8 <= data when "001000", '0' when others;
with address select y9 <= data when "001001", '0' when others;
with address select y10 <= data when "001010", '0' when others;
with address select y11 <= data when "001011", '0' when others;
with address select y12 <= data when "001100", '0' when others;
with address select y13 <= data when "001101", '0' when others;
with address select y14 <= data when "001110", '0' when others;
with address select y15 <= data when "001111", '0' when others;
with address select y16 <= data when "010000", '0' when others;
with address select y17 <= data when "010001", '0' when others;
with address select y18 <= data when "010010", '0' when others;
with address select y19 <= data when "010011", '0' when others;
with address select y20 <= data when "010100", '0' when others;
with address select y21 <= data when "010101", '0' when others;
with address select y22 <= data when "010110", '0' when others;
with address select y23 <= data when "010111", '0' when others;
with address select y24 <= data when "011000", '0' when others;
with address select y25 <= data when "011001", '0' when others;
with address select y26 <= data when "011010", '0' when others;
with address select y27 <= data when "011011", '0' when others;
with address select y28 <= data when "011100", '0' when others;
with address select y29 <= data when "011101", '0' when others;
with address select y30 <= data when "011110", '0' when others;
with address select y31 <= data when "011111", '0' when others;
with address select y32 <= data when "100000", '0' when others;
with address select y33 <= data when "100001", '0' when others;
with address select y34 <= data when "100010", '0' when others;
with address select y35 <= data when "100011", '0' when others;
with address select y36 <= data when "100100", '0' when others;
with address select y37 <= data when "100101", '0' when others;
with address select y38 <= data when "100110", '0' when others;
with address select y39 <= data when "100111", '0' when others;
with address select y40 <= data when "101000", '0' when others;
with address select y41 <= data when "101001", '0' when others;
with address select y42 <= data when "101010", '0' when others;
with address select y43 <= data when "101011", '0' when others;
with address select y44 <= data when "101100", '0' when others;
with address select y45 <= data when "101101", '0' when others;
with address select y46 <= data when "101110", '0' when others;
with address select y47 <= data when "101111", '0' when others;
with address select y48 <= data when "110000", '0' when others;
with address select y49 <= data when "110001", '0' when others;
with address select y50 <= data when "110010", '0' when others;
with address select y51 <= data when "110011", '0' when others;
with address select y52 <= data when "110100", '0' when others;
with address select y53 <= data when "110101", '0' when others;
with address select y54 <= data when "110110", '0' when others;
with address select y55 <= data when "110111", '0' when others;
with address select y56 <= data when "111000", '0' when others;
with address select y57 <= data when "111001", '0' when others;
with address select y58 <= data when "111010", '0' when others;
with address select y59 <= data when "111011", '0' when others;
with address select y60 <= data when "111100", '0' when others;
with address select y61 <= data when "111101", '0' when others;
with address select y62 <= data when "111110", '0' when others;
with address select y63 <= data when "111111", '0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx64 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0);
y2: out std_logic_vector((N-1) downto 0);
y3: out std_logic_vector((N-1) downto 0);
y4: out std_logic_vector((N-1) downto 0);
y5: out std_logic_vector((N-1) downto 0);
y6: out std_logic_vector((N-1) downto 0);
y7: out std_logic_vector((N-1) downto 0);
y8: out std_logic_vector((N-1) downto 0);
y9: out std_logic_vector((N-1) downto 0);
y10: out std_logic_vector((N-1) downto 0);
y11: out std_logic_vector((N-1) downto 0);
y12: out std_logic_vector((N-1) downto 0);
y13: out std_logic_vector((N-1) downto 0);
y14: out std_logic_vector((N-1) downto 0);
y15: out std_logic_vector((N-1) downto 0);
y16: out std_logic_vector((N-1) downto 0);
y17: out std_logic_vector((N-1) downto 0);
y18: out std_logic_vector((N-1) downto 0);
y19: out std_logic_vector((N-1) downto 0);
y20: out std_logic_vector((N-1) downto 0);
y21: out std_logic_vector((N-1) downto 0);
y22: out std_logic_vector((N-1) downto 0);
y23: out std_logic_vector((N-1) downto 0);
y24: out std_logic_vector((N-1) downto 0);
y25: out std_logic_vector((N-1) downto 0);
y26: out std_logic_vector((N-1) downto 0);
y27: out std_logic_vector((N-1) downto 0);
y28: out std_logic_vector((N-1) downto 0);
y29: out std_logic_vector((N-1) downto 0);
y30: out std_logic_vector((N-1) downto 0);
y31: out std_logic_vector((N-1) downto 0);
y32: out std_logic_vector((N-1) downto 0);
y33: out std_logic_vector((N-1) downto 0);
y34: out std_logic_vector((N-1) downto 0);
y35: out std_logic_vector((N-1) downto 0);
y36: out std_logic_vector((N-1) downto 0);
y37: out std_logic_vector((N-1) downto 0);
y38: out std_logic_vector((N-1) downto 0);
y39: out std_logic_vector((N-1) downto 0);
y40: out std_logic_vector((N-1) downto 0);
y41: out std_logic_vector((N-1) downto 0);
y42: out std_logic_vector((N-1) downto 0);
y43: out std_logic_vector((N-1) downto 0);
y44: out std_logic_vector((N-1) downto 0);
y45: out std_logic_vector((N-1) downto 0);
y46: out std_logic_vector((N-1) downto 0);
y47: out std_logic_vector((N-1) downto 0);
y48: out std_logic_vector((N-1) downto 0);
y49: out std_logic_vector((N-1) downto 0);
y50: out std_logic_vector((N-1) downto 0);
y51: out std_logic_vector((N-1) downto 0);
y52: out std_logic_vector((N-1) downto 0);
y53: out std_logic_vector((N-1) downto 0);
y54: out std_logic_vector((N-1) downto 0);
y55: out std_logic_vector((N-1) downto 0);
y56: out std_logic_vector((N-1) downto 0);
y57: out std_logic_vector((N-1) downto 0);
y58: out std_logic_vector((N-1) downto 0);
y59: out std_logic_vector((N-1) downto 0);
y60: out std_logic_vector((N-1) downto 0);
y61: out std_logic_vector((N-1) downto 0);
y62: out std_logic_vector((N-1) downto 0);
y63: out std_logic_vector((N-1) downto 0);
address: in std_logic_vector(5 downto 0)
);
end;
-- tested 2015/12/26 with N = 8 using modelsim. works.
architecture struct_decoderNx64 of decoderNx64 is
component decoder1x64 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
y32: out std_logic;
y33: out std_logic;
y34: out std_logic;
y35: out std_logic;
y36: out std_logic;
y37: out std_logic;
y38: out std_logic;
y39: out std_logic;
y40: out std_logic;
y41: out std_logic;
y42: out std_logic;
y43: out std_logic;
y44: out std_logic;
y45: out std_logic;
y46: out std_logic;
y47: out std_logic;
y48: out std_logic;
y49: out std_logic;
y50: out std_logic;
y51: out std_logic;
y52: out std_logic;
y53: out std_logic;
y54: out std_logic;
y55: out std_logic;
y56: out std_logic;
y57: out std_logic;
y58: out std_logic;
y59: out std_logic;
y60: out std_logic;
y61: out std_logic;
y62: out std_logic;
y63: out std_logic;
address: in std_logic_vector(5 downto 0)
);
end component;
begin
u1: for i in 0 to (N-1) generate
u: decoder1x64 port map(
data => data(i),
y0 => y0(i),
y1 => y1(i),
y2 => y2(i),
y3 => y3(i),
y4 => y4(i),
y5 => y5(i),
y6 => y6(i),
y7 => y7(i),
y8 => y8(i),
y9 => y9(i),
y10 => y10(i),
y11 => y11(i),
y12 => y12(i),
y13 => y13(i),
y14 => y14(i),
y15 => y15(i),
y16 => y16(i),
y17 => y17(i),
y18 => y18(i),
y19 => y19(i),
y20 => y20(i),
y21 => y21(i),
y22 => y22(i),
y23 => y23(i),
y24 => y24(i),
y25 => y25(i),
y26 => y26(i),
y27 => y27(i),
y28 => y28(i),
y29 => y29(i),
y30 => y30(i),
y31 => y31(i),
y32 => y32(i),
y33 => y33(i),
y34 => y34(i),
y35 => y35(i),
y36 => y36(i),
y37 => y37(i),
y38 => y38(i),
y39 => y39(i),
y40 => y40(i),
y41 => y41(i),
y42 => y42(i),
y43 => y43(i),
y44 => y44(i),
y45 => y45(i),
y46 => y46(i),
y47 => y47(i),
y48 => y48(i),
y49 => y49(i),
y50 => y50(i),
y51 => y51(i),
y52 => y52(i),
y53 => y53(i),
y54 => y54(i),
y55 => y55(i),
y56 => y56(i),
y57 => y57(i),
y58 => y58(i),
y59 => y59(i),
y60 => y60(i),
y61 => y61(i),
y62 => y62(i),
y63 => y63(i),
address => address
);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x32 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
address: in std_logic_vector(4 downto 0)
);
end;
-- tested 2015/12/25 as part of decoderNx32 with modelsim, works.
architecture struct_decoder1x32 of decoder1x32 is
begin
with address select y0 <= data when "00000", '0' when others;
with address select y1 <= data when "00001", '0' when others;
with address select y2 <= data when "00010", '0' when others;
with address select y3 <= data when "00011", '0' when others;
with address select y4 <= data when "00100", '0' when others;
with address select y5 <= data when "00101", '0' when others;
with address select y6 <= data when "00110", '0' when others;
with address select y7 <= data when "00111", '0' when others;
with address select y8 <= data when "01000", '0' when others;
with address select y9 <= data when "01001", '0' when others;
with address select y10 <= data when "01010", '0' when others;
with address select y11 <= data when "01011", '0' when others;
with address select y12 <= data when "01100", '0' when others;
with address select y13 <= data when "01101", '0' when others;
with address select y14 <= data when "01110", '0' when others;
with address select y15 <= data when "01111", '0' when others;
with address select y16 <= data when "10000", '0' when others;
with address select y17 <= data when "10001", '0' when others;
with address select y18 <= data when "10010", '0' when others;
with address select y19 <= data when "10011", '0' when others;
with address select y20 <= data when "10100", '0' when others;
with address select y21 <= data when "10101", '0' when others;
with address select y22 <= data when "10110", '0' when others;
with address select y23 <= data when "10111", '0' when others;
with address select y24 <= data when "11000", '0' when others;
with address select y25 <= data when "11001", '0' when others;
with address select y26 <= data when "11010", '0' when others;
with address select y27 <= data when "11011", '0' when others;
with address select y28 <= data when "11100", '0' when others;
with address select y29 <= data when "11101", '0' when others;
with address select y30 <= data when "11110", '0' when others;
with address select y31 <= data when "11111", '0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx32 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0);
y2: out std_logic_vector((N-1) downto 0);
y3: out std_logic_vector((N-1) downto 0);
y4: out std_logic_vector((N-1) downto 0);
y5: out std_logic_vector((N-1) downto 0);
y6: out std_logic_vector((N-1) downto 0);
y7: out std_logic_vector((N-1) downto 0);
y8: out std_logic_vector((N-1) downto 0);
y9: out std_logic_vector((N-1) downto 0);
y10: out std_logic_vector((N-1) downto 0);
y11: out std_logic_vector((N-1) downto 0);
y12: out std_logic_vector((N-1) downto 0);
y13: out std_logic_vector((N-1) downto 0);
y14: out std_logic_vector((N-1) downto 0);
y15: out std_logic_vector((N-1) downto 0);
y16: out std_logic_vector((N-1) downto 0);
y17: out std_logic_vector((N-1) downto 0);
y18: out std_logic_vector((N-1) downto 0);
y19: out std_logic_vector((N-1) downto 0);
y20: out std_logic_vector((N-1) downto 0);
y21: out std_logic_vector((N-1) downto 0);
y22: out std_logic_vector((N-1) downto 0);
y23: out std_logic_vector((N-1) downto 0);
y24: out std_logic_vector((N-1) downto 0);
y25: out std_logic_vector((N-1) downto 0);
y26: out std_logic_vector((N-1) downto 0);
y27: out std_logic_vector((N-1) downto 0);
y28: out std_logic_vector((N-1) downto 0);
y29: out std_logic_vector((N-1) downto 0);
y30: out std_logic_vector((N-1) downto 0);
y31: out std_logic_vector((N-1) downto 0);
address: in std_logic_vector(4 downto 0)
);
end;
-- tested 2015/12/25 with modelsim and N = 8, works.
-- reverified with correct report statements 2015/12/26, works.
architecture struct_decoderNx32 of decoderNx32 is
component decoder1x32 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
address: in std_logic_vector(4 downto 0)
);
end component;
begin
u1: for i in 0 to (N-1) generate
u: decoder1x32 port map(
data => data(i),
y0 => y0(i),
y1 => y1(i),
y2 => y2(i),
y3 => y3(i),
y4 => y4(i),
y5 => y5(i),
y6 => y6(i),
y7 => y7(i),
y8 => y8(i),
y9 => y9(i),
y10 => y10(i),
y11 => y11(i),
y12 => y12(i),
y13 => y13(i),
y14 => y14(i),
y15 => y15(i),
y16 => y16(i),
y17 => y17(i),
y18 => y18(i),
y19 => y19(i),
y20 => y20(i),
y21 => y21(i),
y22 => y22(i),
y23 => y23(i),
y24 => y24(i),
y25 => y25(i),
y26 => y26(i),
y27 => y27(i),
y28 => y28(i),
y29 => y29(i),
y30 => y30(i),
y31 => y31(i),
address => address
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder128x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
data32: in std_logic;
data33: in std_logic;
data34: in std_logic;
data35: in std_logic;
data36: in std_logic;
data37: in std_logic;
data38: in std_logic;
data39: in std_logic;
data40: in std_logic;
data41: in std_logic;
data42: in std_logic;
data43: in std_logic;
data44: in std_logic;
data45: in std_logic;
data46: in std_logic;
data47: in std_logic;
data48: in std_logic;
data49: in std_logic;
data50: in std_logic;
data51: in std_logic;
data52: in std_logic;
data53: in std_logic;
data54: in std_logic;
data55: in std_logic;
data56: in std_logic;
data57: in std_logic;
data58: in std_logic;
data59: in std_logic;
data60: in std_logic;
data61: in std_logic;
data62: in std_logic;
data63: in std_logic;
data64: in std_logic;
data65: in std_logic;
data66: in std_logic;
data67: in std_logic;
data68: in std_logic;
data69: in std_logic;
data70: in std_logic;
data71: in std_logic;
data72: in std_logic;
data73: in std_logic;
data74: in std_logic;
data75: in std_logic;
data76: in std_logic;
data77: in std_logic;
data78: in std_logic;
data79: in std_logic;
data80: in std_logic;
data81: in std_logic;
data82: in std_logic;
data83: in std_logic;
data84: in std_logic;
data85: in std_logic;
data86: in std_logic;
data87: in std_logic;
data88: in std_logic;
data89: in std_logic;
data90: in std_logic;
data91: in std_logic;
data92: in std_logic;
data93: in std_logic;
data94: in std_logic;
data95: in std_logic;
data96: in std_logic;
data97: in std_logic;
data98: in std_logic;
data99: in std_logic;
data100: in std_logic;
data101: in std_logic;
data102: in std_logic;
data103: in std_logic;
data104: in std_logic;
data105: in std_logic;
data106: in std_logic;
data107: in std_logic;
data108: in std_logic;
data109: in std_logic;
data110: in std_logic;
data111: in std_logic;
data112: in std_logic;
data113: in std_logic;
data114: in std_logic;
data115: in std_logic;
data116: in std_logic;
data117: in std_logic;
data118: in std_logic;
data119: in std_logic;
data120: in std_logic;
data121: in std_logic;
data122: in std_logic;
data123: in std_logic;
data124: in std_logic;
data125: in std_logic;
data126: in std_logic;
data127: in std_logic;
address: in std_logic_vector(6 downto 0);
output: out std_logic
);
end;
architecture struct_encoder128x1 of encoder128x1 is
begin
with address select
output <=
data0 when "0000000",
data1 when "0000001",
data2 when "0000010",
data3 when "0000011",
data4 when "0000100",
data5 when "0000101",
data6 when "0000110",
data7 when "0000111",
data8 when "0001000",
data9 when "0001001",
data10 when "0001010",
data11 when "0001011",
data12 when "0001100",
data13 when "0001101",
data14 when "0001110",
data15 when "0001111",
data16 when "0010000",
data17 when "0010001",
data18 when "0010010",
data19 when "0010011",
data20 when "0010100",
data21 when "0010101",
data22 when "0010110",
data23 when "0010111",
data24 when "0011000",
data25 when "0011001",
data26 when "0011010",
data27 when "0011011",
data28 when "0011100",
data29 when "0011101",
data30 when "0011110",
data31 when "0011111",
data32 when "0100000",
data33 when "0100001",
data34 when "0100010",
data35 when "0100011",
data36 when "0100100",
data37 when "0100101",
data38 when "0100110",
data39 when "0100111",
data40 when "0101000",
data41 when "0101001",
data42 when "0101010",
data43 when "0101011",
data44 when "0101100",
data45 when "0101101",
data46 when "0101110",
data47 when "0101111",
data48 when "0110000",
data49 when "0110001",
data50 when "0110010",
data51 when "0110011",
data52 when "0110100",
data53 when "0110101",
data54 when "0110110",
data55 when "0110111",
data56 when "0111000",
data57 when "0111001",
data58 when "0111010",
data59 when "0111011",
data60 when "0111100",
data61 when "0111101",
data62 when "0111110",
data63 when "0111111",
data64 when "1000000",
data65 when "1000001",
data66 when "1000010",
data67 when "1000011",
data68 when "1000100",
data69 when "1000101",
data70 when "1000110",
data71 when "1000111",
data72 when "1001000",
data73 when "1001001",
data74 when "1001010",
data75 when "1001011",
data76 when "1001100",
data77 when "1001101",
data78 when "1001110",
data79 when "1001111",
data80 when "1010000",
data81 when "1010001",
data82 when "1010010",
data83 when "1010011",
data84 when "1010100",
data85 when "1010101",
data86 when "1010110",
data87 when "1010111",
data88 when "1011000",
data89 when "1011001",
data90 when "1011010",
data91 when "1011011",
data92 when "1011100",
data93 when "1011101",
data94 when "1011110",
data95 when "1011111",
data96 when "1100000",
data97 when "1100001",
data98 when "1100010",
data99 when "1100011",
data100 when "1100100",
data101 when "1100101",
data102 when "1100110",
data103 when "1100111",
data104 when "1101000",
data105 when "1101001",
data106 when "1101010",
data107 when "1101011",
data108 when "1101100",
data109 when "1101101",
data110 when "1101110",
data111 when "1101111",
data112 when "1110000",
data113 when "1110001",
data114 when "1110010",
data115 when "1110011",
data116 when "1110100",
data117 when "1110101",
data118 when "1110110",
data119 when "1110111",
data120 when "1111000",
data121 when "1111001",
data122 when "1111010",
data123 when "1111011",
data124 when "1111100",
data125 when "1111101",
data126 when "1111110",
data127 when "1111111",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder128xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
data32: in std_logic_vector((N-1) downto 0);
data33: in std_logic_vector((N-1) downto 0);
data34: in std_logic_vector((N-1) downto 0);
data35: in std_logic_vector((N-1) downto 0);
data36: in std_logic_vector((N-1) downto 0);
data37: in std_logic_vector((N-1) downto 0);
data38: in std_logic_vector((N-1) downto 0);
data39: in std_logic_vector((N-1) downto 0);
data40: in std_logic_vector((N-1) downto 0);
data41: in std_logic_vector((N-1) downto 0);
data42: in std_logic_vector((N-1) downto 0);
data43: in std_logic_vector((N-1) downto 0);
data44: in std_logic_vector((N-1) downto 0);
data45: in std_logic_vector((N-1) downto 0);
data46: in std_logic_vector((N-1) downto 0);
data47: in std_logic_vector((N-1) downto 0);
data48: in std_logic_vector((N-1) downto 0);
data49: in std_logic_vector((N-1) downto 0);
data50: in std_logic_vector((N-1) downto 0);
data51: in std_logic_vector((N-1) downto 0);
data52: in std_logic_vector((N-1) downto 0);
data53: in std_logic_vector((N-1) downto 0);
data54: in std_logic_vector((N-1) downto 0);
data55: in std_logic_vector((N-1) downto 0);
data56: in std_logic_vector((N-1) downto 0);
data57: in std_logic_vector((N-1) downto 0);
data58: in std_logic_vector((N-1) downto 0);
data59: in std_logic_vector((N-1) downto 0);
data60: in std_logic_vector((N-1) downto 0);
data61: in std_logic_vector((N-1) downto 0);
data62: in std_logic_vector((N-1) downto 0);
data63: in std_logic_vector((N-1) downto 0);
data64: in std_logic_vector((N-1) downto 0);
data65: in std_logic_vector((N-1) downto 0);
data66: in std_logic_vector((N-1) downto 0);
data67: in std_logic_vector((N-1) downto 0);
data68: in std_logic_vector((N-1) downto 0);
data69: in std_logic_vector((N-1) downto 0);
data70: in std_logic_vector((N-1) downto 0);
data71: in std_logic_vector((N-1) downto 0);
data72: in std_logic_vector((N-1) downto 0);
data73: in std_logic_vector((N-1) downto 0);
data74: in std_logic_vector((N-1) downto 0);
data75: in std_logic_vector((N-1) downto 0);
data76: in std_logic_vector((N-1) downto 0);
data77: in std_logic_vector((N-1) downto 0);
data78: in std_logic_vector((N-1) downto 0);
data79: in std_logic_vector((N-1) downto 0);
data80: in std_logic_vector((N-1) downto 0);
data81: in std_logic_vector((N-1) downto 0);
data82: in std_logic_vector((N-1) downto 0);
data83: in std_logic_vector((N-1) downto 0);
data84: in std_logic_vector((N-1) downto 0);
data85: in std_logic_vector((N-1) downto 0);
data86: in std_logic_vector((N-1) downto 0);
data87: in std_logic_vector((N-1) downto 0);
data88: in std_logic_vector((N-1) downto 0);
data89: in std_logic_vector((N-1) downto 0);
data90: in std_logic_vector((N-1) downto 0);
data91: in std_logic_vector((N-1) downto 0);
data92: in std_logic_vector((N-1) downto 0);
data93: in std_logic_vector((N-1) downto 0);
data94: in std_logic_vector((N-1) downto 0);
data95: in std_logic_vector((N-1) downto 0);
data96: in std_logic_vector((N-1) downto 0);
data97: in std_logic_vector((N-1) downto 0);
data98: in std_logic_vector((N-1) downto 0);
data99: in std_logic_vector((N-1) downto 0);
data100: in std_logic_vector((N-1) downto 0);
data101: in std_logic_vector((N-1) downto 0);
data102: in std_logic_vector((N-1) downto 0);
data103: in std_logic_vector((N-1) downto 0);
data104: in std_logic_vector((N-1) downto 0);
data105: in std_logic_vector((N-1) downto 0);
data106: in std_logic_vector((N-1) downto 0);
data107: in std_logic_vector((N-1) downto 0);
data108: in std_logic_vector((N-1) downto 0);
data109: in std_logic_vector((N-1) downto 0);
data110: in std_logic_vector((N-1) downto 0);
data111: in std_logic_vector((N-1) downto 0);
data112: in std_logic_vector((N-1) downto 0);
data113: in std_logic_vector((N-1) downto 0);
data114: in std_logic_vector((N-1) downto 0);
data115: in std_logic_vector((N-1) downto 0);
data116: in std_logic_vector((N-1) downto 0);
data117: in std_logic_vector((N-1) downto 0);
data118: in std_logic_vector((N-1) downto 0);
data119: in std_logic_vector((N-1) downto 0);
data120: in std_logic_vector((N-1) downto 0);
data121: in std_logic_vector((N-1) downto 0);
data122: in std_logic_vector((N-1) downto 0);
data123: in std_logic_vector((N-1) downto 0);
data124: in std_logic_vector((N-1) downto 0);
data125: in std_logic_vector((N-1) downto 0);
data126: in std_logic_vector((N-1) downto 0);
data127: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(6 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
architecture struct_encoder128xN of encoder128xN is
component encoder128x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
data32: in std_logic;
data33: in std_logic;
data34: in std_logic;
data35: in std_logic;
data36: in std_logic;
data37: in std_logic;
data38: in std_logic;
data39: in std_logic;
data40: in std_logic;
data41: in std_logic;
data42: in std_logic;
data43: in std_logic;
data44: in std_logic;
data45: in std_logic;
data46: in std_logic;
data47: in std_logic;
data48: in std_logic;
data49: in std_logic;
data50: in std_logic;
data51: in std_logic;
data52: in std_logic;
data53: in std_logic;
data54: in std_logic;
data55: in std_logic;
data56: in std_logic;
data57: in std_logic;
data58: in std_logic;
data59: in std_logic;
data60: in std_logic;
data61: in std_logic;
data62: in std_logic;
data63: in std_logic;
data64: in std_logic;
data65: in std_logic;
data66: in std_logic;
data67: in std_logic;
data68: in std_logic;
data69: in std_logic;
data70: in std_logic;
data71: in std_logic;
data72: in std_logic;
data73: in std_logic;
data74: in std_logic;
data75: in std_logic;
data76: in std_logic;
data77: in std_logic;
data78: in std_logic;
data79: in std_logic;
data80: in std_logic;
data81: in std_logic;
data82: in std_logic;
data83: in std_logic;
data84: in std_logic;
data85: in std_logic;
data86: in std_logic;
data87: in std_logic;
data88: in std_logic;
data89: in std_logic;
data90: in std_logic;
data91: in std_logic;
data92: in std_logic;
data93: in std_logic;
data94: in std_logic;
data95: in std_logic;
data96: in std_logic;
data97: in std_logic;
data98: in std_logic;
data99: in std_logic;
data100: in std_logic;
data101: in std_logic;
data102: in std_logic;
data103: in std_logic;
data104: in std_logic;
data105: in std_logic;
data106: in std_logic;
data107: in std_logic;
data108: in std_logic;
data109: in std_logic;
data110: in std_logic;
data111: in std_logic;
data112: in std_logic;
data113: in std_logic;
data114: in std_logic;
data115: in std_logic;
data116: in std_logic;
data117: in std_logic;
data118: in std_logic;
data119: in std_logic;
data120: in std_logic;
data121: in std_logic;
data122: in std_logic;
data123: in std_logic;
data124: in std_logic;
data125: in std_logic;
data126: in std_logic;
data127: in std_logic;
address: in std_logic_vector(6 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder128x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
data4 => data4(i),
data5 => data5(i),
data6 => data6(i),
data7 => data7(i),
data8 => data8(i),
data9 => data9(i),
data10 => data10(i),
data11 => data11(i),
data12 => data12(i),
data13 => data13(i),
data14 => data14(i),
data15 => data15(i),
data16 => data16(i),
data17 => data17(i),
data18 => data18(i),
data19 => data19(i),
data20 => data20(i),
data21 => data21(i),
data22 => data22(i),
data23 => data23(i),
data24 => data24(i),
data25 => data25(i),
data26 => data26(i),
data27 => data27(i),
data28 => data28(i),
data29 => data29(i),
data30 => data30(i),
data31 => data31(i),
data32 => data32(i),
data33 => data33(i),
data34 => data34(i),
data35 => data35(i),
data36 => data36(i),
data37 => data37(i),
data38 => data38(i),
data39 => data39(i),
data40 => data40(i),
data41 => data41(i),
data42 => data42(i),
data43 => data43(i),
data44 => data44(i),
data45 => data45(i),
data46 => data46(i),
data47 => data47(i),
data48 => data48(i),
data49 => data49(i),
data50 => data50(i),
data51 => data51(i),
data52 => data52(i),
data53 => data53(i),
data54 => data54(i),
data55 => data55(i),
data56 => data56(i),
data57 => data57(i),
data58 => data58(i),
data59 => data59(i),
data60 => data60(i),
data61 => data61(i),
data62 => data62(i),
data63 => data63(i),
data64 => data64(i),
data65 => data65(i),
data66 => data66(i),
data67 => data67(i),
data68 => data68(i),
data69 => data69(i),
data70 => data70(i),
data71 => data71(i),
data72 => data72(i),
data73 => data73(i),
data74 => data74(i),
data75 => data75(i),
data76 => data76(i),
data77 => data77(i),
data78 => data78(i),
data79 => data79(i),
data80 => data80(i),
data81 => data81(i),
data82 => data82(i),
data83 => data83(i),
data84 => data84(i),
data85 => data85(i),
data86 => data86(i),
data87 => data87(i),
data88 => data88(i),
data89 => data89(i),
data90 => data90(i),
data91 => data91(i),
data92 => data92(i),
data93 => data93(i),
data94 => data94(i),
data95 => data95(i),
data96 => data96(i),
data97 => data97(i),
data98 => data98(i),
data99 => data99(i),
data100 => data100(i),
data101 => data101(i),
data102 => data102(i),
data103 => data103(i),
data104 => data104(i),
data105 => data105(i),
data106 => data106(i),
data107 => data107(i),
data108 => data108(i),
data109 => data109(i),
data110 => data110(i),
data111 => data111(i),
data112 => data112(i),
data113 => data113(i),
data114 => data114(i),
data115 => data115(i),
data116 => data116(i),
data117 => data117(i),
data118 => data118(i),
data119 => data119(i),
data120 => data120(i),
data121 => data121(i),
data122 => data122(i),
data123 => data123(i),
data124 => data124(i),
data125 => data125(i),
data126 => data126(i),
data127 => data127(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x128 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
y32: out std_logic;
y33: out std_logic;
y34: out std_logic;
y35: out std_logic;
y36: out std_logic;
y37: out std_logic;
y38: out std_logic;
y39: out std_logic;
y40: out std_logic;
y41: out std_logic;
y42: out std_logic;
y43: out std_logic;
y44: out std_logic;
y45: out std_logic;
y46: out std_logic;
y47: out std_logic;
y48: out std_logic;
y49: out std_logic;
y50: out std_logic;
y51: out std_logic;
y52: out std_logic;
y53: out std_logic;
y54: out std_logic;
y55: out std_logic;
y56: out std_logic;
y57: out std_logic;
y58: out std_logic;
y59: out std_logic;
y60: out std_logic;
y61: out std_logic;
y62: out std_logic;
y63: out std_logic;
y64: out std_logic;
y65: out std_logic;
y66: out std_logic;
y67: out std_logic;
y68: out std_logic;
y69: out std_logic;
y70: out std_logic;
y71: out std_logic;
y72: out std_logic;
y73: out std_logic;
y74: out std_logic;
y75: out std_logic;
y76: out std_logic;
y77: out std_logic;
y78: out std_logic;
y79: out std_logic;
y80: out std_logic;
y81: out std_logic;
y82: out std_logic;
y83: out std_logic;
y84: out std_logic;
y85: out std_logic;
y86: out std_logic;
y87: out std_logic;
y88: out std_logic;
y89: out std_logic;
y90: out std_logic;
y91: out std_logic;
y92: out std_logic;
y93: out std_logic;
y94: out std_logic;
y95: out std_logic;
y96: out std_logic;
y97: out std_logic;
y98: out std_logic;
y99: out std_logic;
y100: out std_logic;
y101: out std_logic;
y102: out std_logic;
y103: out std_logic;
y104: out std_logic;
y105: out std_logic;
y106: out std_logic;
y107: out std_logic;
y108: out std_logic;
y109: out std_logic;
y110: out std_logic;
y111: out std_logic;
y112: out std_logic;
y113: out std_logic;
y114: out std_logic;
y115: out std_logic;
y116: out std_logic;
y117: out std_logic;
y118: out std_logic;
y119: out std_logic;
y120: out std_logic;
y121: out std_logic;
y122: out std_logic;
y123: out std_logic;
y124: out std_logic;
y125: out std_logic;
y126: out std_logic;
y127: out std_logic;
address: in std_logic_vector(6 downto 0)
);
end;
architecture struct_decoder1x128 of decoder1x128 is
begin
y0 <= data when address = "0000000" else '0';
y1 <= data when address = "0000001" else '0';
y2 <= data when address = "0000010" else '0';
y3 <= data when address = "0000011" else '0';
y4 <= data when address = "0000100" else '0';
y5 <= data when address = "0000101" else '0';
y6 <= data when address = "0000110" else '0';
y7 <= data when address = "0000111" else '0';
y8 <= data when address = "0001000" else '0';
y9 <= data when address = "0001001" else '0';
y10 <= data when address = "0001010" else '0';
y11 <= data when address = "0001011" else '0';
y12 <= data when address = "0001100" else '0';
y13 <= data when address = "0001101" else '0';
y14 <= data when address = "0001110" else '0';
y15 <= data when address = "0001111" else '0';
y16 <= data when address = "0010000" else '0';
y17 <= data when address = "0010001" else '0';
y18 <= data when address = "0010010" else '0';
y19 <= data when address = "0010011" else '0';
y20 <= data when address = "0010100" else '0';
y21 <= data when address = "0010101" else '0';
y22 <= data when address = "0010110" else '0';
y23 <= data when address = "0010111" else '0';
y24 <= data when address = "0011000" else '0';
y25 <= data when address = "0011001" else '0';
y26 <= data when address = "0011010" else '0';
y27 <= data when address = "0011011" else '0';
y28 <= data when address = "0011100" else '0';
y29 <= data when address = "0011101" else '0';
y30 <= data when address = "0011110" else '0';
y31 <= data when address = "0011111" else '0';
y32 <= data when address = "0100000" else '0';
y33 <= data when address = "0100001" else '0';
y34 <= data when address = "0100010" else '0';
y35 <= data when address = "0100011" else '0';
y36 <= data when address = "0100100" else '0';
y37 <= data when address = "0100101" else '0';
y38 <= data when address = "0100110" else '0';
y39 <= data when address = "0100111" else '0';
y40 <= data when address = "0101000" else '0';
y41 <= data when address = "0101001" else '0';
y42 <= data when address = "0101010" else '0';
y43 <= data when address = "0101011" else '0';
y44 <= data when address = "0101100" else '0';
y45 <= data when address = "0101101" else '0';
y46 <= data when address = "0101110" else '0';
y47 <= data when address = "0101111" else '0';
y48 <= data when address = "0110000" else '0';
y49 <= data when address = "0110001" else '0';
y50 <= data when address = "0110010" else '0';
y51 <= data when address = "0110011" else '0';
y52 <= data when address = "0110100" else '0';
y53 <= data when address = "0110101" else '0';
y54 <= data when address = "0110110" else '0';
y55 <= data when address = "0110111" else '0';
y56 <= data when address = "0111000" else '0';
y57 <= data when address = "0111001" else '0';
y58 <= data when address = "0111010" else '0';
y59 <= data when address = "0111011" else '0';
y60 <= data when address = "0111100" else '0';
y61 <= data when address = "0111101" else '0';
y62 <= data when address = "0111110" else '0';
y63 <= data when address = "0111111" else '0';
y64 <= data when address = "1000000" else '0';
y65 <= data when address = "1000001" else '0';
y66 <= data when address = "1000010" else '0';
y67 <= data when address = "1000011" else '0';
y68 <= data when address = "1000100" else '0';
y69 <= data when address = "1000101" else '0';
y70 <= data when address = "1000110" else '0';
y71 <= data when address = "1000111" else '0';
y72 <= data when address = "1001000" else '0';
y73 <= data when address = "1001001" else '0';
y74 <= data when address = "1001010" else '0';
y75 <= data when address = "1001011" else '0';
y76 <= data when address = "1001100" else '0';
y77 <= data when address = "1001101" else '0';
y78 <= data when address = "1001110" else '0';
y79 <= data when address = "1001111" else '0';
y80 <= data when address = "1010000" else '0';
y81 <= data when address = "1010001" else '0';
y82 <= data when address = "1010010" else '0';
y83 <= data when address = "1010011" else '0';
y84 <= data when address = "1010100" else '0';
y85 <= data when address = "1010101" else '0';
y86 <= data when address = "1010110" else '0';
y87 <= data when address = "1010111" else '0';
y88 <= data when address = "1011000" else '0';
y89 <= data when address = "1011001" else '0';
y90 <= data when address = "1011010" else '0';
y91 <= data when address = "1011011" else '0';
y92 <= data when address = "1011100" else '0';
y93 <= data when address = "1011101" else '0';
y94 <= data when address = "1011110" else '0';
y95 <= data when address = "1011111" else '0';
y96 <= data when address = "1100000" else '0';
y97 <= data when address = "1100001" else '0';
y98 <= data when address = "1100010" else '0';
y99 <= data when address = "1100011" else '0';
y100 <= data when address = "1100100" else '0';
y101 <= data when address = "1100101" else '0';
y102 <= data when address = "1100110" else '0';
y103 <= data when address = "1100111" else '0';
y104 <= data when address = "1101000" else '0';
y105 <= data when address = "1101001" else '0';
y106 <= data when address = "1101010" else '0';
y107 <= data when address = "1101011" else '0';
y108 <= data when address = "1101100" else '0';
y109 <= data when address = "1101101" else '0';
y110 <= data when address = "1101110" else '0';
y111 <= data when address = "1101111" else '0';
y112 <= data when address = "1110000" else '0';
y113 <= data when address = "1110001" else '0';
y114 <= data when address = "1110010" else '0';
y115 <= data when address = "1110011" else '0';
y116 <= data when address = "1110100" else '0';
y117 <= data when address = "1110101" else '0';
y118 <= data when address = "1110110" else '0';
y119 <= data when address = "1110111" else '0';
y120 <= data when address = "1111000" else '0';
y121 <= data when address = "1111001" else '0';
y122 <= data when address = "1111010" else '0';
y123 <= data when address = "1111011" else '0';
y124 <= data when address = "1111100" else '0';
y125 <= data when address = "1111101" else '0';
y126 <= data when address = "1111110" else '0';
y127 <= data when address = "1111111" else '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx128 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0);
y2: out std_logic_vector((N-1) downto 0);
y3: out std_logic_vector((N-1) downto 0);
y4: out std_logic_vector((N-1) downto 0);
y5: out std_logic_vector((N-1) downto 0);
y6: out std_logic_vector((N-1) downto 0);
y7: out std_logic_vector((N-1) downto 0);
y8: out std_logic_vector((N-1) downto 0);
y9: out std_logic_vector((N-1) downto 0);
y10: out std_logic_vector((N-1) downto 0);
y11: out std_logic_vector((N-1) downto 0);
y12: out std_logic_vector((N-1) downto 0);
y13: out std_logic_vector((N-1) downto 0);
y14: out std_logic_vector((N-1) downto 0);
y15: out std_logic_vector((N-1) downto 0);
y16: out std_logic_vector((N-1) downto 0);
y17: out std_logic_vector((N-1) downto 0);
y18: out std_logic_vector((N-1) downto 0);
y19: out std_logic_vector((N-1) downto 0);
y20: out std_logic_vector((N-1) downto 0);
y21: out std_logic_vector((N-1) downto 0);
y22: out std_logic_vector((N-1) downto 0);
y23: out std_logic_vector((N-1) downto 0);
y24: out std_logic_vector((N-1) downto 0);
y25: out std_logic_vector((N-1) downto 0);
y26: out std_logic_vector((N-1) downto 0);
y27: out std_logic_vector((N-1) downto 0);
y28: out std_logic_vector((N-1) downto 0);
y29: out std_logic_vector((N-1) downto 0);
y30: out std_logic_vector((N-1) downto 0);
y31: out std_logic_vector((N-1) downto 0);
y32: out std_logic_vector((N-1) downto 0);
y33: out std_logic_vector((N-1) downto 0);
y34: out std_logic_vector((N-1) downto 0);
y35: out std_logic_vector((N-1) downto 0);
y36: out std_logic_vector((N-1) downto 0);
y37: out std_logic_vector((N-1) downto 0);
y38: out std_logic_vector((N-1) downto 0);
y39: out std_logic_vector((N-1) downto 0);
y40: out std_logic_vector((N-1) downto 0);
y41: out std_logic_vector((N-1) downto 0);
y42: out std_logic_vector((N-1) downto 0);
y43: out std_logic_vector((N-1) downto 0);
y44: out std_logic_vector((N-1) downto 0);
y45: out std_logic_vector((N-1) downto 0);
y46: out std_logic_vector((N-1) downto 0);
y47: out std_logic_vector((N-1) downto 0);
y48: out std_logic_vector((N-1) downto 0);
y49: out std_logic_vector((N-1) downto 0);
y50: out std_logic_vector((N-1) downto 0);
y51: out std_logic_vector((N-1) downto 0);
y52: out std_logic_vector((N-1) downto 0);
y53: out std_logic_vector((N-1) downto 0);
y54: out std_logic_vector((N-1) downto 0);
y55: out std_logic_vector((N-1) downto 0);
y56: out std_logic_vector((N-1) downto 0);
y57: out std_logic_vector((N-1) downto 0);
y58: out std_logic_vector((N-1) downto 0);
y59: out std_logic_vector((N-1) downto 0);
y60: out std_logic_vector((N-1) downto 0);
y61: out std_logic_vector((N-1) downto 0);
y62: out std_logic_vector((N-1) downto 0);
y63: out std_logic_vector((N-1) downto 0);
y64: out std_logic_vector((N-1) downto 0);
y65: out std_logic_vector((N-1) downto 0);
y66: out std_logic_vector((N-1) downto 0);
y67: out std_logic_vector((N-1) downto 0);
y68: out std_logic_vector((N-1) downto 0);
y69: out std_logic_vector((N-1) downto 0);
y70: out std_logic_vector((N-1) downto 0);
y71: out std_logic_vector((N-1) downto 0);
y72: out std_logic_vector((N-1) downto 0);
y73: out std_logic_vector((N-1) downto 0);
y74: out std_logic_vector((N-1) downto 0);
y75: out std_logic_vector((N-1) downto 0);
y76: out std_logic_vector((N-1) downto 0);
y77: out std_logic_vector((N-1) downto 0);
y78: out std_logic_vector((N-1) downto 0);
y79: out std_logic_vector((N-1) downto 0);
y80: out std_logic_vector((N-1) downto 0);
y81: out std_logic_vector((N-1) downto 0);
y82: out std_logic_vector((N-1) downto 0);
y83: out std_logic_vector((N-1) downto 0);
y84: out std_logic_vector((N-1) downto 0);
y85: out std_logic_vector((N-1) downto 0);
y86: out std_logic_vector((N-1) downto 0);
y87: out std_logic_vector((N-1) downto 0);
y88: out std_logic_vector((N-1) downto 0);
y89: out std_logic_vector((N-1) downto 0);
y90: out std_logic_vector((N-1) downto 0);
y91: out std_logic_vector((N-1) downto 0);
y92: out std_logic_vector((N-1) downto 0);
y93: out std_logic_vector((N-1) downto 0);
y94: out std_logic_vector((N-1) downto 0);
y95: out std_logic_vector((N-1) downto 0);
y96: out std_logic_vector((N-1) downto 0);
y97: out std_logic_vector((N-1) downto 0);
y98: out std_logic_vector((N-1) downto 0);
y99: out std_logic_vector((N-1) downto 0);
y100: out std_logic_vector((N-1) downto 0);
y101: out std_logic_vector((N-1) downto 0);
y102: out std_logic_vector((N-1) downto 0);
y103: out std_logic_vector((N-1) downto 0);
y104: out std_logic_vector((N-1) downto 0);
y105: out std_logic_vector((N-1) downto 0);
y106: out std_logic_vector((N-1) downto 0);
y107: out std_logic_vector((N-1) downto 0);
y108: out std_logic_vector((N-1) downto 0);
y109: out std_logic_vector((N-1) downto 0);
y110: out std_logic_vector((N-1) downto 0);
y111: out std_logic_vector((N-1) downto 0);
y112: out std_logic_vector((N-1) downto 0);
y113: out std_logic_vector((N-1) downto 0);
y114: out std_logic_vector((N-1) downto 0);
y115: out std_logic_vector((N-1) downto 0);
y116: out std_logic_vector((N-1) downto 0);
y117: out std_logic_vector((N-1) downto 0);
y118: out std_logic_vector((N-1) downto 0);
y119: out std_logic_vector((N-1) downto 0);
y120: out std_logic_vector((N-1) downto 0);
y121: out std_logic_vector((N-1) downto 0);
y122: out std_logic_vector((N-1) downto 0);
y123: out std_logic_vector((N-1) downto 0);
y124: out std_logic_vector((N-1) downto 0);
y125: out std_logic_vector((N-1) downto 0);
y126: out std_logic_vector((N-1) downto 0);
y127: out std_logic_vector((N-1) downto 0);
address: in std_logic_vector(6 downto 0)
);
end;
architecture struct_decoderNx128 of decoderNx128 is
component decoder1x128 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
y32: out std_logic;
y33: out std_logic;
y34: out std_logic;
y35: out std_logic;
y36: out std_logic;
y37: out std_logic;
y38: out std_logic;
y39: out std_logic;
y40: out std_logic;
y41: out std_logic;
y42: out std_logic;
y43: out std_logic;
y44: out std_logic;
y45: out std_logic;
y46: out std_logic;
y47: out std_logic;
y48: out std_logic;
y49: out std_logic;
y50: out std_logic;
y51: out std_logic;
y52: out std_logic;
y53: out std_logic;
y54: out std_logic;
y55: out std_logic;
y56: out std_logic;
y57: out std_logic;
y58: out std_logic;
y59: out std_logic;
y60: out std_logic;
y61: out std_logic;
y62: out std_logic;
y63: out std_logic;
y64: out std_logic;
y65: out std_logic;
y66: out std_logic;
y67: out std_logic;
y68: out std_logic;
y69: out std_logic;
y70: out std_logic;
y71: out std_logic;
y72: out std_logic;
y73: out std_logic;
y74: out std_logic;
y75: out std_logic;
y76: out std_logic;
y77: out std_logic;
y78: out std_logic;
y79: out std_logic;
y80: out std_logic;
y81: out std_logic;
y82: out std_logic;
y83: out std_logic;
y84: out std_logic;
y85: out std_logic;
y86: out std_logic;
y87: out std_logic;
y88: out std_logic;
y89: out std_logic;
y90: out std_logic;
y91: out std_logic;
y92: out std_logic;
y93: out std_logic;
y94: out std_logic;
y95: out std_logic;
y96: out std_logic;
y97: out std_logic;
y98: out std_logic;
y99: out std_logic;
y100: out std_logic;
y101: out std_logic;
y102: out std_logic;
y103: out std_logic;
y104: out std_logic;
y105: out std_logic;
y106: out std_logic;
y107: out std_logic;
y108: out std_logic;
y109: out std_logic;
y110: out std_logic;
y111: out std_logic;
y112: out std_logic;
y113: out std_logic;
y114: out std_logic;
y115: out std_logic;
y116: out std_logic;
y117: out std_logic;
y118: out std_logic;
y119: out std_logic;
y120: out std_logic;
y121: out std_logic;
y122: out std_logic;
y123: out std_logic;
y124: out std_logic;
y125: out std_logic;
y126: out std_logic;
y127: out std_logic;
address: in std_logic_vector(6 downto 0)
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: decoder1x128 port map(
data => data(i),
y0 => y0(i),
y1 => y1(i),
y2 => y2(i),
y3 => y3(i),
y4 => y4(i),
y5 => y5(i),
y6 => y6(i),
y7 => y7(i),
y8 => y8(i),
y9 => y9(i),
y10 => y10(i),
y11 => y11(i),
y12 => y12(i),
y13 => y13(i),
y14 => y14(i),
y15 => y15(i),
y16 => y16(i),
y17 => y17(i),
y18 => y18(i),
y19 => y19(i),
y20 => y20(i),
y21 => y21(i),
y22 => y22(i),
y23 => y23(i),
y24 => y24(i),
y25 => y25(i),
y26 => y26(i),
y27 => y27(i),
y28 => y28(i),
y29 => y29(i),
y30 => y30(i),
y31 => y31(i),
y32 => y32(i),
y33 => y33(i),
y34 => y34(i),
y35 => y35(i),
y36 => y36(i),
y37 => y37(i),
y38 => y38(i),
y39 => y39(i),
y40 => y40(i),
y41 => y41(i),
y42 => y42(i),
y43 => y43(i),
y44 => y44(i),
y45 => y45(i),
y46 => y46(i),
y47 => y47(i),
y48 => y48(i),
y49 => y49(i),
y50 => y50(i),
y51 => y51(i),
y52 => y52(i),
y53 => y53(i),
y54 => y54(i),
y55 => y55(i),
y56 => y56(i),
y57 => y57(i),
y58 => y58(i),
y59 => y59(i),
y60 => y60(i),
y61 => y61(i),
y62 => y62(i),
y63 => y63(i),
y64 => y64(i),
y65 => y65(i),
y66 => y66(i),
y67 => y67(i),
y68 => y68(i),
y69 => y69(i),
y70 => y70(i),
y71 => y71(i),
y72 => y72(i),
y73 => y73(i),
y74 => y74(i),
y75 => y75(i),
y76 => y76(i),
y77 => y77(i),
y78 => y78(i),
y79 => y79(i),
y80 => y80(i),
y81 => y81(i),
y82 => y82(i),
y83 => y83(i),
y84 => y84(i),
y85 => y85(i),
y86 => y86(i),
y87 => y87(i),
y88 => y88(i),
y89 => y89(i),
y90 => y90(i),
y91 => y91(i),
y92 => y92(i),
y93 => y93(i),
y94 => y94(i),
y95 => y95(i),
y96 => y96(i),
y97 => y97(i),
y98 => y98(i),
y99 => y99(i),
y100 => y100(i),
y101 => y101(i),
y102 => y102(i),
y103 => y103(i),
y104 => y104(i),
y105 => y105(i),
y106 => y106(i),
y107 => y107(i),
y108 => y108(i),
y109 => y109(i),
y110 => y110(i),
y111 => y111(i),
y112 => y112(i),
y113 => y113(i),
y114 => y114(i),
y115 => y115(i),
y116 => y116(i),
y117 => y117(i),
y118 => y118(i),
y119 => y119(i),
y120 => y120(i),
y121 => y121(i),
y122 => y122(i),
y123 => y123(i),
y124 => y124(i),
y125 => y125(i),
y126 => y126(i),
y127 => y127(i),
address => address
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder256x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
data32: in std_logic;
data33: in std_logic;
data34: in std_logic;
data35: in std_logic;
data36: in std_logic;
data37: in std_logic;
data38: in std_logic;
data39: in std_logic;
data40: in std_logic;
data41: in std_logic;
data42: in std_logic;
data43: in std_logic;
data44: in std_logic;
data45: in std_logic;
data46: in std_logic;
data47: in std_logic;
data48: in std_logic;
data49: in std_logic;
data50: in std_logic;
data51: in std_logic;
data52: in std_logic;
data53: in std_logic;
data54: in std_logic;
data55: in std_logic;
data56: in std_logic;
data57: in std_logic;
data58: in std_logic;
data59: in std_logic;
data60: in std_logic;
data61: in std_logic;
data62: in std_logic;
data63: in std_logic;
data64: in std_logic;
data65: in std_logic;
data66: in std_logic;
data67: in std_logic;
data68: in std_logic;
data69: in std_logic;
data70: in std_logic;
data71: in std_logic;
data72: in std_logic;
data73: in std_logic;
data74: in std_logic;
data75: in std_logic;
data76: in std_logic;
data77: in std_logic;
data78: in std_logic;
data79: in std_logic;
data80: in std_logic;
data81: in std_logic;
data82: in std_logic;
data83: in std_logic;
data84: in std_logic;
data85: in std_logic;
data86: in std_logic;
data87: in std_logic;
data88: in std_logic;
data89: in std_logic;
data90: in std_logic;
data91: in std_logic;
data92: in std_logic;
data93: in std_logic;
data94: in std_logic;
data95: in std_logic;
data96: in std_logic;
data97: in std_logic;
data98: in std_logic;
data99: in std_logic;
data100: in std_logic;
data101: in std_logic;
data102: in std_logic;
data103: in std_logic;
data104: in std_logic;
data105: in std_logic;
data106: in std_logic;
data107: in std_logic;
data108: in std_logic;
data109: in std_logic;
data110: in std_logic;
data111: in std_logic;
data112: in std_logic;
data113: in std_logic;
data114: in std_logic;
data115: in std_logic;
data116: in std_logic;
data117: in std_logic;
data118: in std_logic;
data119: in std_logic;
data120: in std_logic;
data121: in std_logic;
data122: in std_logic;
data123: in std_logic;
data124: in std_logic;
data125: in std_logic;
data126: in std_logic;
data127: in std_logic;
data128: in std_logic;
data129: in std_logic;
data130: in std_logic;
data131: in std_logic;
data132: in std_logic;
data133: in std_logic;
data134: in std_logic;
data135: in std_logic;
data136: in std_logic;
data137: in std_logic;
data138: in std_logic;
data139: in std_logic;
data140: in std_logic;
data141: in std_logic;
data142: in std_logic;
data143: in std_logic;
data144: in std_logic;
data145: in std_logic;
data146: in std_logic;
data147: in std_logic;
data148: in std_logic;
data149: in std_logic;
data150: in std_logic;
data151: in std_logic;
data152: in std_logic;
data153: in std_logic;
data154: in std_logic;
data155: in std_logic;
data156: in std_logic;
data157: in std_logic;
data158: in std_logic;
data159: in std_logic;
data160: in std_logic;
data161: in std_logic;
data162: in std_logic;
data163: in std_logic;
data164: in std_logic;
data165: in std_logic;
data166: in std_logic;
data167: in std_logic;
data168: in std_logic;
data169: in std_logic;
data170: in std_logic;
data171: in std_logic;
data172: in std_logic;
data173: in std_logic;
data174: in std_logic;
data175: in std_logic;
data176: in std_logic;
data177: in std_logic;
data178: in std_logic;
data179: in std_logic;
data180: in std_logic;
data181: in std_logic;
data182: in std_logic;
data183: in std_logic;
data184: in std_logic;
data185: in std_logic;
data186: in std_logic;
data187: in std_logic;
data188: in std_logic;
data189: in std_logic;
data190: in std_logic;
data191: in std_logic;
data192: in std_logic;
data193: in std_logic;
data194: in std_logic;
data195: in std_logic;
data196: in std_logic;
data197: in std_logic;
data198: in std_logic;
data199: in std_logic;
data200: in std_logic;
data201: in std_logic;
data202: in std_logic;
data203: in std_logic;
data204: in std_logic;
data205: in std_logic;
data206: in std_logic;
data207: in std_logic;
data208: in std_logic;
data209: in std_logic;
data210: in std_logic;
data211: in std_logic;
data212: in std_logic;
data213: in std_logic;
data214: in std_logic;
data215: in std_logic;
data216: in std_logic;
data217: in std_logic;
data218: in std_logic;
data219: in std_logic;
data220: in std_logic;
data221: in std_logic;
data222: in std_logic;
data223: in std_logic;
data224: in std_logic;
data225: in std_logic;
data226: in std_logic;
data227: in std_logic;
data228: in std_logic;
data229: in std_logic;
data230: in std_logic;
data231: in std_logic;
data232: in std_logic;
data233: in std_logic;
data234: in std_logic;
data235: in std_logic;
data236: in std_logic;
data237: in std_logic;
data238: in std_logic;
data239: in std_logic;
data240: in std_logic;
data241: in std_logic;
data242: in std_logic;
data243: in std_logic;
data244: in std_logic;
data245: in std_logic;
data246: in std_logic;
data247: in std_logic;
data248: in std_logic;
data249: in std_logic;
data250: in std_logic;
data251: in std_logic;
data252: in std_logic;
data253: in std_logic;
data254: in std_logic;
data255: in std_logic;
address: in std_logic_vector(7 downto 0);
output: out std_logic
);
end;
architecture struct_encoder256x1 of encoder256x1 is
begin
with address select
output <=
data0 when "00000000",
data1 when "00000001",
data2 when "00000010",
data3 when "00000011",
data4 when "00000100",
data5 when "00000101",
data6 when "00000110",
data7 when "00000111",
data8 when "00001000",
data9 when "00001001",
data10 when "00001010",
data11 when "00001011",
data12 when "00001100",
data13 when "00001101",
data14 when "00001110",
data15 when "00001111",
data16 when "00010000",
data17 when "00010001",
data18 when "00010010",
data19 when "00010011",
data20 when "00010100",
data21 when "00010101",
data22 when "00010110",
data23 when "00010111",
data24 when "00011000",
data25 when "00011001",
data26 when "00011010",
data27 when "00011011",
data28 when "00011100",
data29 when "00011101",
data30 when "00011110",
data31 when "00011111",
data32 when "00100000",
data33 when "00100001",
data34 when "00100010",
data35 when "00100011",
data36 when "00100100",
data37 when "00100101",
data38 when "00100110",
data39 when "00100111",
data40 when "00101000",
data41 when "00101001",
data42 when "00101010",
data43 when "00101011",
data44 when "00101100",
data45 when "00101101",
data46 when "00101110",
data47 when "00101111",
data48 when "00110000",
data49 when "00110001",
data50 when "00110010",
data51 when "00110011",
data52 when "00110100",
data53 when "00110101",
data54 when "00110110",
data55 when "00110111",
data56 when "00111000",
data57 when "00111001",
data58 when "00111010",
data59 when "00111011",
data60 when "00111100",
data61 when "00111101",
data62 when "00111110",
data63 when "00111111",
data64 when "01000000",
data65 when "01000001",
data66 when "01000010",
data67 when "01000011",
data68 when "01000100",
data69 when "01000101",
data70 when "01000110",
data71 when "01000111",
data72 when "01001000",
data73 when "01001001",
data74 when "01001010",
data75 when "01001011",
data76 when "01001100",
data77 when "01001101",
data78 when "01001110",
data79 when "01001111",
data80 when "01010000",
data81 when "01010001",
data82 when "01010010",
data83 when "01010011",
data84 when "01010100",
data85 when "01010101",
data86 when "01010110",
data87 when "01010111",
data88 when "01011000",
data89 when "01011001",
data90 when "01011010",
data91 when "01011011",
data92 when "01011100",
data93 when "01011101",
data94 when "01011110",
data95 when "01011111",
data96 when "01100000",
data97 when "01100001",
data98 when "01100010",
data99 when "01100011",
data100 when "01100100",
data101 when "01100101",
data102 when "01100110",
data103 when "01100111",
data104 when "01101000",
data105 when "01101001",
data106 when "01101010",
data107 when "01101011",
data108 when "01101100",
data109 when "01101101",
data110 when "01101110",
data111 when "01101111",
data112 when "01110000",
data113 when "01110001",
data114 when "01110010",
data115 when "01110011",
data116 when "01110100",
data117 when "01110101",
data118 when "01110110",
data119 when "01110111",
data120 when "01111000",
data121 when "01111001",
data122 when "01111010",
data123 when "01111011",
data124 when "01111100",
data125 when "01111101",
data126 when "01111110",
data127 when "01111111",
data128 when "10000000",
data129 when "10000001",
data130 when "10000010",
data131 when "10000011",
data132 when "10000100",
data133 when "10000101",
data134 when "10000110",
data135 when "10000111",
data136 when "10001000",
data137 when "10001001",
data138 when "10001010",
data139 when "10001011",
data140 when "10001100",
data141 when "10001101",
data142 when "10001110",
data143 when "10001111",
data144 when "10010000",
data145 when "10010001",
data146 when "10010010",
data147 when "10010011",
data148 when "10010100",
data149 when "10010101",
data150 when "10010110",
data151 when "10010111",
data152 when "10011000",
data153 when "10011001",
data154 when "10011010",
data155 when "10011011",
data156 when "10011100",
data157 when "10011101",
data158 when "10011110",
data159 when "10011111",
data160 when "10100000",
data161 when "10100001",
data162 when "10100010",
data163 when "10100011",
data164 when "10100100",
data165 when "10100101",
data166 when "10100110",
data167 when "10100111",
data168 when "10101000",
data169 when "10101001",
data170 when "10101010",
data171 when "10101011",
data172 when "10101100",
data173 when "10101101",
data174 when "10101110",
data175 when "10101111",
data176 when "10110000",
data177 when "10110001",
data178 when "10110010",
data179 when "10110011",
data180 when "10110100",
data181 when "10110101",
data182 when "10110110",
data183 when "10110111",
data184 when "10111000",
data185 when "10111001",
data186 when "10111010",
data187 when "10111011",
data188 when "10111100",
data189 when "10111101",
data190 when "10111110",
data191 when "10111111",
data192 when "11000000",
data193 when "11000001",
data194 when "11000010",
data195 when "11000011",
data196 when "11000100",
data197 when "11000101",
data198 when "11000110",
data199 when "11000111",
data200 when "11001000",
data201 when "11001001",
data202 when "11001010",
data203 when "11001011",
data204 when "11001100",
data205 when "11001101",
data206 when "11001110",
data207 when "11001111",
data208 when "11010000",
data209 when "11010001",
data210 when "11010010",
data211 when "11010011",
data212 when "11010100",
data213 when "11010101",
data214 when "11010110",
data215 when "11010111",
data216 when "11011000",
data217 when "11011001",
data218 when "11011010",
data219 when "11011011",
data220 when "11011100",
data221 when "11011101",
data222 when "11011110",
data223 when "11011111",
data224 when "11100000",
data225 when "11100001",
data226 when "11100010",
data227 when "11100011",
data228 when "11100100",
data229 when "11100101",
data230 when "11100110",
data231 when "11100111",
data232 when "11101000",
data233 when "11101001",
data234 when "11101010",
data235 when "11101011",
data236 when "11101100",
data237 when "11101101",
data238 when "11101110",
data239 when "11101111",
data240 when "11110000",
data241 when "11110001",
data242 when "11110010",
data243 when "11110011",
data244 when "11110100",
data245 when "11110101",
data246 when "11110110",
data247 when "11110111",
data248 when "11111000",
data249 when "11111001",
data250 when "11111010",
data251 when "11111011",
data252 when "11111100",
data253 when "11111101",
data254 when "11111110",
data255 when "11111111",
'0' when others;
end;
library ieee;
use ieee.std_logic_1164.all;
entity encoder256xN is
generic(
N: positive
);
port(
data0: in std_logic_vector((N-1) downto 0);
data1: in std_logic_vector((N-1) downto 0);
data2: in std_logic_vector((N-1) downto 0);
data3: in std_logic_vector((N-1) downto 0);
data4: in std_logic_vector((N-1) downto 0);
data5: in std_logic_vector((N-1) downto 0);
data6: in std_logic_vector((N-1) downto 0);
data7: in std_logic_vector((N-1) downto 0);
data8: in std_logic_vector((N-1) downto 0);
data9: in std_logic_vector((N-1) downto 0);
data10: in std_logic_vector((N-1) downto 0);
data11: in std_logic_vector((N-1) downto 0);
data12: in std_logic_vector((N-1) downto 0);
data13: in std_logic_vector((N-1) downto 0);
data14: in std_logic_vector((N-1) downto 0);
data15: in std_logic_vector((N-1) downto 0);
data16: in std_logic_vector((N-1) downto 0);
data17: in std_logic_vector((N-1) downto 0);
data18: in std_logic_vector((N-1) downto 0);
data19: in std_logic_vector((N-1) downto 0);
data20: in std_logic_vector((N-1) downto 0);
data21: in std_logic_vector((N-1) downto 0);
data22: in std_logic_vector((N-1) downto 0);
data23: in std_logic_vector((N-1) downto 0);
data24: in std_logic_vector((N-1) downto 0);
data25: in std_logic_vector((N-1) downto 0);
data26: in std_logic_vector((N-1) downto 0);
data27: in std_logic_vector((N-1) downto 0);
data28: in std_logic_vector((N-1) downto 0);
data29: in std_logic_vector((N-1) downto 0);
data30: in std_logic_vector((N-1) downto 0);
data31: in std_logic_vector((N-1) downto 0);
data32: in std_logic_vector((N-1) downto 0);
data33: in std_logic_vector((N-1) downto 0);
data34: in std_logic_vector((N-1) downto 0);
data35: in std_logic_vector((N-1) downto 0);
data36: in std_logic_vector((N-1) downto 0);
data37: in std_logic_vector((N-1) downto 0);
data38: in std_logic_vector((N-1) downto 0);
data39: in std_logic_vector((N-1) downto 0);
data40: in std_logic_vector((N-1) downto 0);
data41: in std_logic_vector((N-1) downto 0);
data42: in std_logic_vector((N-1) downto 0);
data43: in std_logic_vector((N-1) downto 0);
data44: in std_logic_vector((N-1) downto 0);
data45: in std_logic_vector((N-1) downto 0);
data46: in std_logic_vector((N-1) downto 0);
data47: in std_logic_vector((N-1) downto 0);
data48: in std_logic_vector((N-1) downto 0);
data49: in std_logic_vector((N-1) downto 0);
data50: in std_logic_vector((N-1) downto 0);
data51: in std_logic_vector((N-1) downto 0);
data52: in std_logic_vector((N-1) downto 0);
data53: in std_logic_vector((N-1) downto 0);
data54: in std_logic_vector((N-1) downto 0);
data55: in std_logic_vector((N-1) downto 0);
data56: in std_logic_vector((N-1) downto 0);
data57: in std_logic_vector((N-1) downto 0);
data58: in std_logic_vector((N-1) downto 0);
data59: in std_logic_vector((N-1) downto 0);
data60: in std_logic_vector((N-1) downto 0);
data61: in std_logic_vector((N-1) downto 0);
data62: in std_logic_vector((N-1) downto 0);
data63: in std_logic_vector((N-1) downto 0);
data64: in std_logic_vector((N-1) downto 0);
data65: in std_logic_vector((N-1) downto 0);
data66: in std_logic_vector((N-1) downto 0);
data67: in std_logic_vector((N-1) downto 0);
data68: in std_logic_vector((N-1) downto 0);
data69: in std_logic_vector((N-1) downto 0);
data70: in std_logic_vector((N-1) downto 0);
data71: in std_logic_vector((N-1) downto 0);
data72: in std_logic_vector((N-1) downto 0);
data73: in std_logic_vector((N-1) downto 0);
data74: in std_logic_vector((N-1) downto 0);
data75: in std_logic_vector((N-1) downto 0);
data76: in std_logic_vector((N-1) downto 0);
data77: in std_logic_vector((N-1) downto 0);
data78: in std_logic_vector((N-1) downto 0);
data79: in std_logic_vector((N-1) downto 0);
data80: in std_logic_vector((N-1) downto 0);
data81: in std_logic_vector((N-1) downto 0);
data82: in std_logic_vector((N-1) downto 0);
data83: in std_logic_vector((N-1) downto 0);
data84: in std_logic_vector((N-1) downto 0);
data85: in std_logic_vector((N-1) downto 0);
data86: in std_logic_vector((N-1) downto 0);
data87: in std_logic_vector((N-1) downto 0);
data88: in std_logic_vector((N-1) downto 0);
data89: in std_logic_vector((N-1) downto 0);
data90: in std_logic_vector((N-1) downto 0);
data91: in std_logic_vector((N-1) downto 0);
data92: in std_logic_vector((N-1) downto 0);
data93: in std_logic_vector((N-1) downto 0);
data94: in std_logic_vector((N-1) downto 0);
data95: in std_logic_vector((N-1) downto 0);
data96: in std_logic_vector((N-1) downto 0);
data97: in std_logic_vector((N-1) downto 0);
data98: in std_logic_vector((N-1) downto 0);
data99: in std_logic_vector((N-1) downto 0);
data100: in std_logic_vector((N-1) downto 0);
data101: in std_logic_vector((N-1) downto 0);
data102: in std_logic_vector((N-1) downto 0);
data103: in std_logic_vector((N-1) downto 0);
data104: in std_logic_vector((N-1) downto 0);
data105: in std_logic_vector((N-1) downto 0);
data106: in std_logic_vector((N-1) downto 0);
data107: in std_logic_vector((N-1) downto 0);
data108: in std_logic_vector((N-1) downto 0);
data109: in std_logic_vector((N-1) downto 0);
data110: in std_logic_vector((N-1) downto 0);
data111: in std_logic_vector((N-1) downto 0);
data112: in std_logic_vector((N-1) downto 0);
data113: in std_logic_vector((N-1) downto 0);
data114: in std_logic_vector((N-1) downto 0);
data115: in std_logic_vector((N-1) downto 0);
data116: in std_logic_vector((N-1) downto 0);
data117: in std_logic_vector((N-1) downto 0);
data118: in std_logic_vector((N-1) downto 0);
data119: in std_logic_vector((N-1) downto 0);
data120: in std_logic_vector((N-1) downto 0);
data121: in std_logic_vector((N-1) downto 0);
data122: in std_logic_vector((N-1) downto 0);
data123: in std_logic_vector((N-1) downto 0);
data124: in std_logic_vector((N-1) downto 0);
data125: in std_logic_vector((N-1) downto 0);
data126: in std_logic_vector((N-1) downto 0);
data127: in std_logic_vector((N-1) downto 0);
data128: in std_logic_vector((N-1) downto 0);
data129: in std_logic_vector((N-1) downto 0);
data130: in std_logic_vector((N-1) downto 0);
data131: in std_logic_vector((N-1) downto 0);
data132: in std_logic_vector((N-1) downto 0);
data133: in std_logic_vector((N-1) downto 0);
data134: in std_logic_vector((N-1) downto 0);
data135: in std_logic_vector((N-1) downto 0);
data136: in std_logic_vector((N-1) downto 0);
data137: in std_logic_vector((N-1) downto 0);
data138: in std_logic_vector((N-1) downto 0);
data139: in std_logic_vector((N-1) downto 0);
data140: in std_logic_vector((N-1) downto 0);
data141: in std_logic_vector((N-1) downto 0);
data142: in std_logic_vector((N-1) downto 0);
data143: in std_logic_vector((N-1) downto 0);
data144: in std_logic_vector((N-1) downto 0);
data145: in std_logic_vector((N-1) downto 0);
data146: in std_logic_vector((N-1) downto 0);
data147: in std_logic_vector((N-1) downto 0);
data148: in std_logic_vector((N-1) downto 0);
data149: in std_logic_vector((N-1) downto 0);
data150: in std_logic_vector((N-1) downto 0);
data151: in std_logic_vector((N-1) downto 0);
data152: in std_logic_vector((N-1) downto 0);
data153: in std_logic_vector((N-1) downto 0);
data154: in std_logic_vector((N-1) downto 0);
data155: in std_logic_vector((N-1) downto 0);
data156: in std_logic_vector((N-1) downto 0);
data157: in std_logic_vector((N-1) downto 0);
data158: in std_logic_vector((N-1) downto 0);
data159: in std_logic_vector((N-1) downto 0);
data160: in std_logic_vector((N-1) downto 0);
data161: in std_logic_vector((N-1) downto 0);
data162: in std_logic_vector((N-1) downto 0);
data163: in std_logic_vector((N-1) downto 0);
data164: in std_logic_vector((N-1) downto 0);
data165: in std_logic_vector((N-1) downto 0);
data166: in std_logic_vector((N-1) downto 0);
data167: in std_logic_vector((N-1) downto 0);
data168: in std_logic_vector((N-1) downto 0);
data169: in std_logic_vector((N-1) downto 0);
data170: in std_logic_vector((N-1) downto 0);
data171: in std_logic_vector((N-1) downto 0);
data172: in std_logic_vector((N-1) downto 0);
data173: in std_logic_vector((N-1) downto 0);
data174: in std_logic_vector((N-1) downto 0);
data175: in std_logic_vector((N-1) downto 0);
data176: in std_logic_vector((N-1) downto 0);
data177: in std_logic_vector((N-1) downto 0);
data178: in std_logic_vector((N-1) downto 0);
data179: in std_logic_vector((N-1) downto 0);
data180: in std_logic_vector((N-1) downto 0);
data181: in std_logic_vector((N-1) downto 0);
data182: in std_logic_vector((N-1) downto 0);
data183: in std_logic_vector((N-1) downto 0);
data184: in std_logic_vector((N-1) downto 0);
data185: in std_logic_vector((N-1) downto 0);
data186: in std_logic_vector((N-1) downto 0);
data187: in std_logic_vector((N-1) downto 0);
data188: in std_logic_vector((N-1) downto 0);
data189: in std_logic_vector((N-1) downto 0);
data190: in std_logic_vector((N-1) downto 0);
data191: in std_logic_vector((N-1) downto 0);
data192: in std_logic_vector((N-1) downto 0);
data193: in std_logic_vector((N-1) downto 0);
data194: in std_logic_vector((N-1) downto 0);
data195: in std_logic_vector((N-1) downto 0);
data196: in std_logic_vector((N-1) downto 0);
data197: in std_logic_vector((N-1) downto 0);
data198: in std_logic_vector((N-1) downto 0);
data199: in std_logic_vector((N-1) downto 0);
data200: in std_logic_vector((N-1) downto 0);
data201: in std_logic_vector((N-1) downto 0);
data202: in std_logic_vector((N-1) downto 0);
data203: in std_logic_vector((N-1) downto 0);
data204: in std_logic_vector((N-1) downto 0);
data205: in std_logic_vector((N-1) downto 0);
data206: in std_logic_vector((N-1) downto 0);
data207: in std_logic_vector((N-1) downto 0);
data208: in std_logic_vector((N-1) downto 0);
data209: in std_logic_vector((N-1) downto 0);
data210: in std_logic_vector((N-1) downto 0);
data211: in std_logic_vector((N-1) downto 0);
data212: in std_logic_vector((N-1) downto 0);
data213: in std_logic_vector((N-1) downto 0);
data214: in std_logic_vector((N-1) downto 0);
data215: in std_logic_vector((N-1) downto 0);
data216: in std_logic_vector((N-1) downto 0);
data217: in std_logic_vector((N-1) downto 0);
data218: in std_logic_vector((N-1) downto 0);
data219: in std_logic_vector((N-1) downto 0);
data220: in std_logic_vector((N-1) downto 0);
data221: in std_logic_vector((N-1) downto 0);
data222: in std_logic_vector((N-1) downto 0);
data223: in std_logic_vector((N-1) downto 0);
data224: in std_logic_vector((N-1) downto 0);
data225: in std_logic_vector((N-1) downto 0);
data226: in std_logic_vector((N-1) downto 0);
data227: in std_logic_vector((N-1) downto 0);
data228: in std_logic_vector((N-1) downto 0);
data229: in std_logic_vector((N-1) downto 0);
data230: in std_logic_vector((N-1) downto 0);
data231: in std_logic_vector((N-1) downto 0);
data232: in std_logic_vector((N-1) downto 0);
data233: in std_logic_vector((N-1) downto 0);
data234: in std_logic_vector((N-1) downto 0);
data235: in std_logic_vector((N-1) downto 0);
data236: in std_logic_vector((N-1) downto 0);
data237: in std_logic_vector((N-1) downto 0);
data238: in std_logic_vector((N-1) downto 0);
data239: in std_logic_vector((N-1) downto 0);
data240: in std_logic_vector((N-1) downto 0);
data241: in std_logic_vector((N-1) downto 0);
data242: in std_logic_vector((N-1) downto 0);
data243: in std_logic_vector((N-1) downto 0);
data244: in std_logic_vector((N-1) downto 0);
data245: in std_logic_vector((N-1) downto 0);
data246: in std_logic_vector((N-1) downto 0);
data247: in std_logic_vector((N-1) downto 0);
data248: in std_logic_vector((N-1) downto 0);
data249: in std_logic_vector((N-1) downto 0);
data250: in std_logic_vector((N-1) downto 0);
data251: in std_logic_vector((N-1) downto 0);
data252: in std_logic_vector((N-1) downto 0);
data253: in std_logic_vector((N-1) downto 0);
data254: in std_logic_vector((N-1) downto 0);
data255: in std_logic_vector((N-1) downto 0);
address: in std_logic_vector(7 downto 0);
output: out std_logic_vector((N-1) downto 0)
);
end;
architecture struct_encoder256xN of encoder256xN is
component encoder256x1 is
port(
data0: in std_logic;
data1: in std_logic;
data2: in std_logic;
data3: in std_logic;
data4: in std_logic;
data5: in std_logic;
data6: in std_logic;
data7: in std_logic;
data8: in std_logic;
data9: in std_logic;
data10: in std_logic;
data11: in std_logic;
data12: in std_logic;
data13: in std_logic;
data14: in std_logic;
data15: in std_logic;
data16: in std_logic;
data17: in std_logic;
data18: in std_logic;
data19: in std_logic;
data20: in std_logic;
data21: in std_logic;
data22: in std_logic;
data23: in std_logic;
data24: in std_logic;
data25: in std_logic;
data26: in std_logic;
data27: in std_logic;
data28: in std_logic;
data29: in std_logic;
data30: in std_logic;
data31: in std_logic;
data32: in std_logic;
data33: in std_logic;
data34: in std_logic;
data35: in std_logic;
data36: in std_logic;
data37: in std_logic;
data38: in std_logic;
data39: in std_logic;
data40: in std_logic;
data41: in std_logic;
data42: in std_logic;
data43: in std_logic;
data44: in std_logic;
data45: in std_logic;
data46: in std_logic;
data47: in std_logic;
data48: in std_logic;
data49: in std_logic;
data50: in std_logic;
data51: in std_logic;
data52: in std_logic;
data53: in std_logic;
data54: in std_logic;
data55: in std_logic;
data56: in std_logic;
data57: in std_logic;
data58: in std_logic;
data59: in std_logic;
data60: in std_logic;
data61: in std_logic;
data62: in std_logic;
data63: in std_logic;
data64: in std_logic;
data65: in std_logic;
data66: in std_logic;
data67: in std_logic;
data68: in std_logic;
data69: in std_logic;
data70: in std_logic;
data71: in std_logic;
data72: in std_logic;
data73: in std_logic;
data74: in std_logic;
data75: in std_logic;
data76: in std_logic;
data77: in std_logic;
data78: in std_logic;
data79: in std_logic;
data80: in std_logic;
data81: in std_logic;
data82: in std_logic;
data83: in std_logic;
data84: in std_logic;
data85: in std_logic;
data86: in std_logic;
data87: in std_logic;
data88: in std_logic;
data89: in std_logic;
data90: in std_logic;
data91: in std_logic;
data92: in std_logic;
data93: in std_logic;
data94: in std_logic;
data95: in std_logic;
data96: in std_logic;
data97: in std_logic;
data98: in std_logic;
data99: in std_logic;
data100: in std_logic;
data101: in std_logic;
data102: in std_logic;
data103: in std_logic;
data104: in std_logic;
data105: in std_logic;
data106: in std_logic;
data107: in std_logic;
data108: in std_logic;
data109: in std_logic;
data110: in std_logic;
data111: in std_logic;
data112: in std_logic;
data113: in std_logic;
data114: in std_logic;
data115: in std_logic;
data116: in std_logic;
data117: in std_logic;
data118: in std_logic;
data119: in std_logic;
data120: in std_logic;
data121: in std_logic;
data122: in std_logic;
data123: in std_logic;
data124: in std_logic;
data125: in std_logic;
data126: in std_logic;
data127: in std_logic;
data128: in std_logic;
data129: in std_logic;
data130: in std_logic;
data131: in std_logic;
data132: in std_logic;
data133: in std_logic;
data134: in std_logic;
data135: in std_logic;
data136: in std_logic;
data137: in std_logic;
data138: in std_logic;
data139: in std_logic;
data140: in std_logic;
data141: in std_logic;
data142: in std_logic;
data143: in std_logic;
data144: in std_logic;
data145: in std_logic;
data146: in std_logic;
data147: in std_logic;
data148: in std_logic;
data149: in std_logic;
data150: in std_logic;
data151: in std_logic;
data152: in std_logic;
data153: in std_logic;
data154: in std_logic;
data155: in std_logic;
data156: in std_logic;
data157: in std_logic;
data158: in std_logic;
data159: in std_logic;
data160: in std_logic;
data161: in std_logic;
data162: in std_logic;
data163: in std_logic;
data164: in std_logic;
data165: in std_logic;
data166: in std_logic;
data167: in std_logic;
data168: in std_logic;
data169: in std_logic;
data170: in std_logic;
data171: in std_logic;
data172: in std_logic;
data173: in std_logic;
data174: in std_logic;
data175: in std_logic;
data176: in std_logic;
data177: in std_logic;
data178: in std_logic;
data179: in std_logic;
data180: in std_logic;
data181: in std_logic;
data182: in std_logic;
data183: in std_logic;
data184: in std_logic;
data185: in std_logic;
data186: in std_logic;
data187: in std_logic;
data188: in std_logic;
data189: in std_logic;
data190: in std_logic;
data191: in std_logic;
data192: in std_logic;
data193: in std_logic;
data194: in std_logic;
data195: in std_logic;
data196: in std_logic;
data197: in std_logic;
data198: in std_logic;
data199: in std_logic;
data200: in std_logic;
data201: in std_logic;
data202: in std_logic;
data203: in std_logic;
data204: in std_logic;
data205: in std_logic;
data206: in std_logic;
data207: in std_logic;
data208: in std_logic;
data209: in std_logic;
data210: in std_logic;
data211: in std_logic;
data212: in std_logic;
data213: in std_logic;
data214: in std_logic;
data215: in std_logic;
data216: in std_logic;
data217: in std_logic;
data218: in std_logic;
data219: in std_logic;
data220: in std_logic;
data221: in std_logic;
data222: in std_logic;
data223: in std_logic;
data224: in std_logic;
data225: in std_logic;
data226: in std_logic;
data227: in std_logic;
data228: in std_logic;
data229: in std_logic;
data230: in std_logic;
data231: in std_logic;
data232: in std_logic;
data233: in std_logic;
data234: in std_logic;
data235: in std_logic;
data236: in std_logic;
data237: in std_logic;
data238: in std_logic;
data239: in std_logic;
data240: in std_logic;
data241: in std_logic;
data242: in std_logic;
data243: in std_logic;
data244: in std_logic;
data245: in std_logic;
data246: in std_logic;
data247: in std_logic;
data248: in std_logic;
data249: in std_logic;
data250: in std_logic;
data251: in std_logic;
data252: in std_logic;
data253: in std_logic;
data254: in std_logic;
data255: in std_logic;
address: in std_logic_vector(7 downto 0);
output: out std_logic
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: encoder256x1 port map(
data0 => data0(i),
data1 => data1(i),
data2 => data2(i),
data3 => data3(i),
data4 => data4(i),
data5 => data5(i),
data6 => data6(i),
data7 => data7(i),
data8 => data8(i),
data9 => data9(i),
data10 => data10(i),
data11 => data11(i),
data12 => data12(i),
data13 => data13(i),
data14 => data14(i),
data15 => data15(i),
data16 => data16(i),
data17 => data17(i),
data18 => data18(i),
data19 => data19(i),
data20 => data20(i),
data21 => data21(i),
data22 => data22(i),
data23 => data23(i),
data24 => data24(i),
data25 => data25(i),
data26 => data26(i),
data27 => data27(i),
data28 => data28(i),
data29 => data29(i),
data30 => data30(i),
data31 => data31(i),
data32 => data32(i),
data33 => data33(i),
data34 => data34(i),
data35 => data35(i),
data36 => data36(i),
data37 => data37(i),
data38 => data38(i),
data39 => data39(i),
data40 => data40(i),
data41 => data41(i),
data42 => data42(i),
data43 => data43(i),
data44 => data44(i),
data45 => data45(i),
data46 => data46(i),
data47 => data47(i),
data48 => data48(i),
data49 => data49(i),
data50 => data50(i),
data51 => data51(i),
data52 => data52(i),
data53 => data53(i),
data54 => data54(i),
data55 => data55(i),
data56 => data56(i),
data57 => data57(i),
data58 => data58(i),
data59 => data59(i),
data60 => data60(i),
data61 => data61(i),
data62 => data62(i),
data63 => data63(i),
data64 => data64(i),
data65 => data65(i),
data66 => data66(i),
data67 => data67(i),
data68 => data68(i),
data69 => data69(i),
data70 => data70(i),
data71 => data71(i),
data72 => data72(i),
data73 => data73(i),
data74 => data74(i),
data75 => data75(i),
data76 => data76(i),
data77 => data77(i),
data78 => data78(i),
data79 => data79(i),
data80 => data80(i),
data81 => data81(i),
data82 => data82(i),
data83 => data83(i),
data84 => data84(i),
data85 => data85(i),
data86 => data86(i),
data87 => data87(i),
data88 => data88(i),
data89 => data89(i),
data90 => data90(i),
data91 => data91(i),
data92 => data92(i),
data93 => data93(i),
data94 => data94(i),
data95 => data95(i),
data96 => data96(i),
data97 => data97(i),
data98 => data98(i),
data99 => data99(i),
data100 => data100(i),
data101 => data101(i),
data102 => data102(i),
data103 => data103(i),
data104 => data104(i),
data105 => data105(i),
data106 => data106(i),
data107 => data107(i),
data108 => data108(i),
data109 => data109(i),
data110 => data110(i),
data111 => data111(i),
data112 => data112(i),
data113 => data113(i),
data114 => data114(i),
data115 => data115(i),
data116 => data116(i),
data117 => data117(i),
data118 => data118(i),
data119 => data119(i),
data120 => data120(i),
data121 => data121(i),
data122 => data122(i),
data123 => data123(i),
data124 => data124(i),
data125 => data125(i),
data126 => data126(i),
data127 => data127(i),
data128 => data128(i),
data129 => data129(i),
data130 => data130(i),
data131 => data131(i),
data132 => data132(i),
data133 => data133(i),
data134 => data134(i),
data135 => data135(i),
data136 => data136(i),
data137 => data137(i),
data138 => data138(i),
data139 => data139(i),
data140 => data140(i),
data141 => data141(i),
data142 => data142(i),
data143 => data143(i),
data144 => data144(i),
data145 => data145(i),
data146 => data146(i),
data147 => data147(i),
data148 => data148(i),
data149 => data149(i),
data150 => data150(i),
data151 => data151(i),
data152 => data152(i),
data153 => data153(i),
data154 => data154(i),
data155 => data155(i),
data156 => data156(i),
data157 => data157(i),
data158 => data158(i),
data159 => data159(i),
data160 => data160(i),
data161 => data161(i),
data162 => data162(i),
data163 => data163(i),
data164 => data164(i),
data165 => data165(i),
data166 => data166(i),
data167 => data167(i),
data168 => data168(i),
data169 => data169(i),
data170 => data170(i),
data171 => data171(i),
data172 => data172(i),
data173 => data173(i),
data174 => data174(i),
data175 => data175(i),
data176 => data176(i),
data177 => data177(i),
data178 => data178(i),
data179 => data179(i),
data180 => data180(i),
data181 => data181(i),
data182 => data182(i),
data183 => data183(i),
data184 => data184(i),
data185 => data185(i),
data186 => data186(i),
data187 => data187(i),
data188 => data188(i),
data189 => data189(i),
data190 => data190(i),
data191 => data191(i),
data192 => data192(i),
data193 => data193(i),
data194 => data194(i),
data195 => data195(i),
data196 => data196(i),
data197 => data197(i),
data198 => data198(i),
data199 => data199(i),
data200 => data200(i),
data201 => data201(i),
data202 => data202(i),
data203 => data203(i),
data204 => data204(i),
data205 => data205(i),
data206 => data206(i),
data207 => data207(i),
data208 => data208(i),
data209 => data209(i),
data210 => data210(i),
data211 => data211(i),
data212 => data212(i),
data213 => data213(i),
data214 => data214(i),
data215 => data215(i),
data216 => data216(i),
data217 => data217(i),
data218 => data218(i),
data219 => data219(i),
data220 => data220(i),
data221 => data221(i),
data222 => data222(i),
data223 => data223(i),
data224 => data224(i),
data225 => data225(i),
data226 => data226(i),
data227 => data227(i),
data228 => data228(i),
data229 => data229(i),
data230 => data230(i),
data231 => data231(i),
data232 => data232(i),
data233 => data233(i),
data234 => data234(i),
data235 => data235(i),
data236 => data236(i),
data237 => data237(i),
data238 => data238(i),
data239 => data239(i),
data240 => data240(i),
data241 => data241(i),
data242 => data242(i),
data243 => data243(i),
data244 => data244(i),
data245 => data245(i),
data246 => data246(i),
data247 => data247(i),
data248 => data248(i),
data249 => data249(i),
data250 => data250(i),
data251 => data251(i),
data252 => data252(i),
data253 => data253(i),
data254 => data254(i),
data255 => data255(i),
address => address,
output => output(i)
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoder1x256 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
y32: out std_logic;
y33: out std_logic;
y34: out std_logic;
y35: out std_logic;
y36: out std_logic;
y37: out std_logic;
y38: out std_logic;
y39: out std_logic;
y40: out std_logic;
y41: out std_logic;
y42: out std_logic;
y43: out std_logic;
y44: out std_logic;
y45: out std_logic;
y46: out std_logic;
y47: out std_logic;
y48: out std_logic;
y49: out std_logic;
y50: out std_logic;
y51: out std_logic;
y52: out std_logic;
y53: out std_logic;
y54: out std_logic;
y55: out std_logic;
y56: out std_logic;
y57: out std_logic;
y58: out std_logic;
y59: out std_logic;
y60: out std_logic;
y61: out std_logic;
y62: out std_logic;
y63: out std_logic;
y64: out std_logic;
y65: out std_logic;
y66: out std_logic;
y67: out std_logic;
y68: out std_logic;
y69: out std_logic;
y70: out std_logic;
y71: out std_logic;
y72: out std_logic;
y73: out std_logic;
y74: out std_logic;
y75: out std_logic;
y76: out std_logic;
y77: out std_logic;
y78: out std_logic;
y79: out std_logic;
y80: out std_logic;
y81: out std_logic;
y82: out std_logic;
y83: out std_logic;
y84: out std_logic;
y85: out std_logic;
y86: out std_logic;
y87: out std_logic;
y88: out std_logic;
y89: out std_logic;
y90: out std_logic;
y91: out std_logic;
y92: out std_logic;
y93: out std_logic;
y94: out std_logic;
y95: out std_logic;
y96: out std_logic;
y97: out std_logic;
y98: out std_logic;
y99: out std_logic;
y100: out std_logic;
y101: out std_logic;
y102: out std_logic;
y103: out std_logic;
y104: out std_logic;
y105: out std_logic;
y106: out std_logic;
y107: out std_logic;
y108: out std_logic;
y109: out std_logic;
y110: out std_logic;
y111: out std_logic;
y112: out std_logic;
y113: out std_logic;
y114: out std_logic;
y115: out std_logic;
y116: out std_logic;
y117: out std_logic;
y118: out std_logic;
y119: out std_logic;
y120: out std_logic;
y121: out std_logic;
y122: out std_logic;
y123: out std_logic;
y124: out std_logic;
y125: out std_logic;
y126: out std_logic;
y127: out std_logic;
y128: out std_logic;
y129: out std_logic;
y130: out std_logic;
y131: out std_logic;
y132: out std_logic;
y133: out std_logic;
y134: out std_logic;
y135: out std_logic;
y136: out std_logic;
y137: out std_logic;
y138: out std_logic;
y139: out std_logic;
y140: out std_logic;
y141: out std_logic;
y142: out std_logic;
y143: out std_logic;
y144: out std_logic;
y145: out std_logic;
y146: out std_logic;
y147: out std_logic;
y148: out std_logic;
y149: out std_logic;
y150: out std_logic;
y151: out std_logic;
y152: out std_logic;
y153: out std_logic;
y154: out std_logic;
y155: out std_logic;
y156: out std_logic;
y157: out std_logic;
y158: out std_logic;
y159: out std_logic;
y160: out std_logic;
y161: out std_logic;
y162: out std_logic;
y163: out std_logic;
y164: out std_logic;
y165: out std_logic;
y166: out std_logic;
y167: out std_logic;
y168: out std_logic;
y169: out std_logic;
y170: out std_logic;
y171: out std_logic;
y172: out std_logic;
y173: out std_logic;
y174: out std_logic;
y175: out std_logic;
y176: out std_logic;
y177: out std_logic;
y178: out std_logic;
y179: out std_logic;
y180: out std_logic;
y181: out std_logic;
y182: out std_logic;
y183: out std_logic;
y184: out std_logic;
y185: out std_logic;
y186: out std_logic;
y187: out std_logic;
y188: out std_logic;
y189: out std_logic;
y190: out std_logic;
y191: out std_logic;
y192: out std_logic;
y193: out std_logic;
y194: out std_logic;
y195: out std_logic;
y196: out std_logic;
y197: out std_logic;
y198: out std_logic;
y199: out std_logic;
y200: out std_logic;
y201: out std_logic;
y202: out std_logic;
y203: out std_logic;
y204: out std_logic;
y205: out std_logic;
y206: out std_logic;
y207: out std_logic;
y208: out std_logic;
y209: out std_logic;
y210: out std_logic;
y211: out std_logic;
y212: out std_logic;
y213: out std_logic;
y214: out std_logic;
y215: out std_logic;
y216: out std_logic;
y217: out std_logic;
y218: out std_logic;
y219: out std_logic;
y220: out std_logic;
y221: out std_logic;
y222: out std_logic;
y223: out std_logic;
y224: out std_logic;
y225: out std_logic;
y226: out std_logic;
y227: out std_logic;
y228: out std_logic;
y229: out std_logic;
y230: out std_logic;
y231: out std_logic;
y232: out std_logic;
y233: out std_logic;
y234: out std_logic;
y235: out std_logic;
y236: out std_logic;
y237: out std_logic;
y238: out std_logic;
y239: out std_logic;
y240: out std_logic;
y241: out std_logic;
y242: out std_logic;
y243: out std_logic;
y244: out std_logic;
y245: out std_logic;
y246: out std_logic;
y247: out std_logic;
y248: out std_logic;
y249: out std_logic;
y250: out std_logic;
y251: out std_logic;
y252: out std_logic;
y253: out std_logic;
y254: out std_logic;
y255: out std_logic;
address: in std_logic_vector(7 downto 0)
);
end;
architecture struct_decoder1x256 of decoder1x256 is
begin
y0 <= data when address = "00000000" else '0';
y1 <= data when address = "00000001" else '0';
y2 <= data when address = "00000010" else '0';
y3 <= data when address = "00000011" else '0';
y4 <= data when address = "00000100" else '0';
y5 <= data when address = "00000101" else '0';
y6 <= data when address = "00000110" else '0';
y7 <= data when address = "00000111" else '0';
y8 <= data when address = "00001000" else '0';
y9 <= data when address = "00001001" else '0';
y10 <= data when address = "00001010" else '0';
y11 <= data when address = "00001011" else '0';
y12 <= data when address = "00001100" else '0';
y13 <= data when address = "00001101" else '0';
y14 <= data when address = "00001110" else '0';
y15 <= data when address = "00001111" else '0';
y16 <= data when address = "00010000" else '0';
y17 <= data when address = "00010001" else '0';
y18 <= data when address = "00010010" else '0';
y19 <= data when address = "00010011" else '0';
y20 <= data when address = "00010100" else '0';
y21 <= data when address = "00010101" else '0';
y22 <= data when address = "00010110" else '0';
y23 <= data when address = "00010111" else '0';
y24 <= data when address = "00011000" else '0';
y25 <= data when address = "00011001" else '0';
y26 <= data when address = "00011010" else '0';
y27 <= data when address = "00011011" else '0';
y28 <= data when address = "00011100" else '0';
y29 <= data when address = "00011101" else '0';
y30 <= data when address = "00011110" else '0';
y31 <= data when address = "00011111" else '0';
y32 <= data when address = "00100000" else '0';
y33 <= data when address = "00100001" else '0';
y34 <= data when address = "00100010" else '0';
y35 <= data when address = "00100011" else '0';
y36 <= data when address = "00100100" else '0';
y37 <= data when address = "00100101" else '0';
y38 <= data when address = "00100110" else '0';
y39 <= data when address = "00100111" else '0';
y40 <= data when address = "00101000" else '0';
y41 <= data when address = "00101001" else '0';
y42 <= data when address = "00101010" else '0';
y43 <= data when address = "00101011" else '0';
y44 <= data when address = "00101100" else '0';
y45 <= data when address = "00101101" else '0';
y46 <= data when address = "00101110" else '0';
y47 <= data when address = "00101111" else '0';
y48 <= data when address = "00110000" else '0';
y49 <= data when address = "00110001" else '0';
y50 <= data when address = "00110010" else '0';
y51 <= data when address = "00110011" else '0';
y52 <= data when address = "00110100" else '0';
y53 <= data when address = "00110101" else '0';
y54 <= data when address = "00110110" else '0';
y55 <= data when address = "00110111" else '0';
y56 <= data when address = "00111000" else '0';
y57 <= data when address = "00111001" else '0';
y58 <= data when address = "00111010" else '0';
y59 <= data when address = "00111011" else '0';
y60 <= data when address = "00111100" else '0';
y61 <= data when address = "00111101" else '0';
y62 <= data when address = "00111110" else '0';
y63 <= data when address = "00111111" else '0';
y64 <= data when address = "01000000" else '0';
y65 <= data when address = "01000001" else '0';
y66 <= data when address = "01000010" else '0';
y67 <= data when address = "01000011" else '0';
y68 <= data when address = "01000100" else '0';
y69 <= data when address = "01000101" else '0';
y70 <= data when address = "01000110" else '0';
y71 <= data when address = "01000111" else '0';
y72 <= data when address = "01001000" else '0';
y73 <= data when address = "01001001" else '0';
y74 <= data when address = "01001010" else '0';
y75 <= data when address = "01001011" else '0';
y76 <= data when address = "01001100" else '0';
y77 <= data when address = "01001101" else '0';
y78 <= data when address = "01001110" else '0';
y79 <= data when address = "01001111" else '0';
y80 <= data when address = "01010000" else '0';
y81 <= data when address = "01010001" else '0';
y82 <= data when address = "01010010" else '0';
y83 <= data when address = "01010011" else '0';
y84 <= data when address = "01010100" else '0';
y85 <= data when address = "01010101" else '0';
y86 <= data when address = "01010110" else '0';
y87 <= data when address = "01010111" else '0';
y88 <= data when address = "01011000" else '0';
y89 <= data when address = "01011001" else '0';
y90 <= data when address = "01011010" else '0';
y91 <= data when address = "01011011" else '0';
y92 <= data when address = "01011100" else '0';
y93 <= data when address = "01011101" else '0';
y94 <= data when address = "01011110" else '0';
y95 <= data when address = "01011111" else '0';
y96 <= data when address = "01100000" else '0';
y97 <= data when address = "01100001" else '0';
y98 <= data when address = "01100010" else '0';
y99 <= data when address = "01100011" else '0';
y100 <= data when address = "01100100" else '0';
y101 <= data when address = "01100101" else '0';
y102 <= data when address = "01100110" else '0';
y103 <= data when address = "01100111" else '0';
y104 <= data when address = "01101000" else '0';
y105 <= data when address = "01101001" else '0';
y106 <= data when address = "01101010" else '0';
y107 <= data when address = "01101011" else '0';
y108 <= data when address = "01101100" else '0';
y109 <= data when address = "01101101" else '0';
y110 <= data when address = "01101110" else '0';
y111 <= data when address = "01101111" else '0';
y112 <= data when address = "01110000" else '0';
y113 <= data when address = "01110001" else '0';
y114 <= data when address = "01110010" else '0';
y115 <= data when address = "01110011" else '0';
y116 <= data when address = "01110100" else '0';
y117 <= data when address = "01110101" else '0';
y118 <= data when address = "01110110" else '0';
y119 <= data when address = "01110111" else '0';
y120 <= data when address = "01111000" else '0';
y121 <= data when address = "01111001" else '0';
y122 <= data when address = "01111010" else '0';
y123 <= data when address = "01111011" else '0';
y124 <= data when address = "01111100" else '0';
y125 <= data when address = "01111101" else '0';
y126 <= data when address = "01111110" else '0';
y127 <= data when address = "01111111" else '0';
y128 <= data when address = "10000000" else '0';
y129 <= data when address = "10000001" else '0';
y130 <= data when address = "10000010" else '0';
y131 <= data when address = "10000011" else '0';
y132 <= data when address = "10000100" else '0';
y133 <= data when address = "10000101" else '0';
y134 <= data when address = "10000110" else '0';
y135 <= data when address = "10000111" else '0';
y136 <= data when address = "10001000" else '0';
y137 <= data when address = "10001001" else '0';
y138 <= data when address = "10001010" else '0';
y139 <= data when address = "10001011" else '0';
y140 <= data when address = "10001100" else '0';
y141 <= data when address = "10001101" else '0';
y142 <= data when address = "10001110" else '0';
y143 <= data when address = "10001111" else '0';
y144 <= data when address = "10010000" else '0';
y145 <= data when address = "10010001" else '0';
y146 <= data when address = "10010010" else '0';
y147 <= data when address = "10010011" else '0';
y148 <= data when address = "10010100" else '0';
y149 <= data when address = "10010101" else '0';
y150 <= data when address = "10010110" else '0';
y151 <= data when address = "10010111" else '0';
y152 <= data when address = "10011000" else '0';
y153 <= data when address = "10011001" else '0';
y154 <= data when address = "10011010" else '0';
y155 <= data when address = "10011011" else '0';
y156 <= data when address = "10011100" else '0';
y157 <= data when address = "10011101" else '0';
y158 <= data when address = "10011110" else '0';
y159 <= data when address = "10011111" else '0';
y160 <= data when address = "10100000" else '0';
y161 <= data when address = "10100001" else '0';
y162 <= data when address = "10100010" else '0';
y163 <= data when address = "10100011" else '0';
y164 <= data when address = "10100100" else '0';
y165 <= data when address = "10100101" else '0';
y166 <= data when address = "10100110" else '0';
y167 <= data when address = "10100111" else '0';
y168 <= data when address = "10101000" else '0';
y169 <= data when address = "10101001" else '0';
y170 <= data when address = "10101010" else '0';
y171 <= data when address = "10101011" else '0';
y172 <= data when address = "10101100" else '0';
y173 <= data when address = "10101101" else '0';
y174 <= data when address = "10101110" else '0';
y175 <= data when address = "10101111" else '0';
y176 <= data when address = "10110000" else '0';
y177 <= data when address = "10110001" else '0';
y178 <= data when address = "10110010" else '0';
y179 <= data when address = "10110011" else '0';
y180 <= data when address = "10110100" else '0';
y181 <= data when address = "10110101" else '0';
y182 <= data when address = "10110110" else '0';
y183 <= data when address = "10110111" else '0';
y184 <= data when address = "10111000" else '0';
y185 <= data when address = "10111001" else '0';
y186 <= data when address = "10111010" else '0';
y187 <= data when address = "10111011" else '0';
y188 <= data when address = "10111100" else '0';
y189 <= data when address = "10111101" else '0';
y190 <= data when address = "10111110" else '0';
y191 <= data when address = "10111111" else '0';
y192 <= data when address = "11000000" else '0';
y193 <= data when address = "11000001" else '0';
y194 <= data when address = "11000010" else '0';
y195 <= data when address = "11000011" else '0';
y196 <= data when address = "11000100" else '0';
y197 <= data when address = "11000101" else '0';
y198 <= data when address = "11000110" else '0';
y199 <= data when address = "11000111" else '0';
y200 <= data when address = "11001000" else '0';
y201 <= data when address = "11001001" else '0';
y202 <= data when address = "11001010" else '0';
y203 <= data when address = "11001011" else '0';
y204 <= data when address = "11001100" else '0';
y205 <= data when address = "11001101" else '0';
y206 <= data when address = "11001110" else '0';
y207 <= data when address = "11001111" else '0';
y208 <= data when address = "11010000" else '0';
y209 <= data when address = "11010001" else '0';
y210 <= data when address = "11010010" else '0';
y211 <= data when address = "11010011" else '0';
y212 <= data when address = "11010100" else '0';
y213 <= data when address = "11010101" else '0';
y214 <= data when address = "11010110" else '0';
y215 <= data when address = "11010111" else '0';
y216 <= data when address = "11011000" else '0';
y217 <= data when address = "11011001" else '0';
y218 <= data when address = "11011010" else '0';
y219 <= data when address = "11011011" else '0';
y220 <= data when address = "11011100" else '0';
y221 <= data when address = "11011101" else '0';
y222 <= data when address = "11011110" else '0';
y223 <= data when address = "11011111" else '0';
y224 <= data when address = "11100000" else '0';
y225 <= data when address = "11100001" else '0';
y226 <= data when address = "11100010" else '0';
y227 <= data when address = "11100011" else '0';
y228 <= data when address = "11100100" else '0';
y229 <= data when address = "11100101" else '0';
y230 <= data when address = "11100110" else '0';
y231 <= data when address = "11100111" else '0';
y232 <= data when address = "11101000" else '0';
y233 <= data when address = "11101001" else '0';
y234 <= data when address = "11101010" else '0';
y235 <= data when address = "11101011" else '0';
y236 <= data when address = "11101100" else '0';
y237 <= data when address = "11101101" else '0';
y238 <= data when address = "11101110" else '0';
y239 <= data when address = "11101111" else '0';
y240 <= data when address = "11110000" else '0';
y241 <= data when address = "11110001" else '0';
y242 <= data when address = "11110010" else '0';
y243 <= data when address = "11110011" else '0';
y244 <= data when address = "11110100" else '0';
y245 <= data when address = "11110101" else '0';
y246 <= data when address = "11110110" else '0';
y247 <= data when address = "11110111" else '0';
y248 <= data when address = "11111000" else '0';
y249 <= data when address = "11111001" else '0';
y250 <= data when address = "11111010" else '0';
y251 <= data when address = "11111011" else '0';
y252 <= data when address = "11111100" else '0';
y253 <= data when address = "11111101" else '0';
y254 <= data when address = "11111110" else '0';
y255 <= data when address = "11111111" else '0';
end;
library ieee;
use ieee.std_logic_1164.all;
entity decoderNx256 is
generic(
N: positive
);
port(
data: in std_logic_vector((N-1) downto 0);
y0: out std_logic_vector((N-1) downto 0);
y1: out std_logic_vector((N-1) downto 0);
y2: out std_logic_vector((N-1) downto 0);
y3: out std_logic_vector((N-1) downto 0);
y4: out std_logic_vector((N-1) downto 0);
y5: out std_logic_vector((N-1) downto 0);
y6: out std_logic_vector((N-1) downto 0);
y7: out std_logic_vector((N-1) downto 0);
y8: out std_logic_vector((N-1) downto 0);
y9: out std_logic_vector((N-1) downto 0);
y10: out std_logic_vector((N-1) downto 0);
y11: out std_logic_vector((N-1) downto 0);
y12: out std_logic_vector((N-1) downto 0);
y13: out std_logic_vector((N-1) downto 0);
y14: out std_logic_vector((N-1) downto 0);
y15: out std_logic_vector((N-1) downto 0);
y16: out std_logic_vector((N-1) downto 0);
y17: out std_logic_vector((N-1) downto 0);
y18: out std_logic_vector((N-1) downto 0);
y19: out std_logic_vector((N-1) downto 0);
y20: out std_logic_vector((N-1) downto 0);
y21: out std_logic_vector((N-1) downto 0);
y22: out std_logic_vector((N-1) downto 0);
y23: out std_logic_vector((N-1) downto 0);
y24: out std_logic_vector((N-1) downto 0);
y25: out std_logic_vector((N-1) downto 0);
y26: out std_logic_vector((N-1) downto 0);
y27: out std_logic_vector((N-1) downto 0);
y28: out std_logic_vector((N-1) downto 0);
y29: out std_logic_vector((N-1) downto 0);
y30: out std_logic_vector((N-1) downto 0);
y31: out std_logic_vector((N-1) downto 0);
y32: out std_logic_vector((N-1) downto 0);
y33: out std_logic_vector((N-1) downto 0);
y34: out std_logic_vector((N-1) downto 0);
y35: out std_logic_vector((N-1) downto 0);
y36: out std_logic_vector((N-1) downto 0);
y37: out std_logic_vector((N-1) downto 0);
y38: out std_logic_vector((N-1) downto 0);
y39: out std_logic_vector((N-1) downto 0);
y40: out std_logic_vector((N-1) downto 0);
y41: out std_logic_vector((N-1) downto 0);
y42: out std_logic_vector((N-1) downto 0);
y43: out std_logic_vector((N-1) downto 0);
y44: out std_logic_vector((N-1) downto 0);
y45: out std_logic_vector((N-1) downto 0);
y46: out std_logic_vector((N-1) downto 0);
y47: out std_logic_vector((N-1) downto 0);
y48: out std_logic_vector((N-1) downto 0);
y49: out std_logic_vector((N-1) downto 0);
y50: out std_logic_vector((N-1) downto 0);
y51: out std_logic_vector((N-1) downto 0);
y52: out std_logic_vector((N-1) downto 0);
y53: out std_logic_vector((N-1) downto 0);
y54: out std_logic_vector((N-1) downto 0);
y55: out std_logic_vector((N-1) downto 0);
y56: out std_logic_vector((N-1) downto 0);
y57: out std_logic_vector((N-1) downto 0);
y58: out std_logic_vector((N-1) downto 0);
y59: out std_logic_vector((N-1) downto 0);
y60: out std_logic_vector((N-1) downto 0);
y61: out std_logic_vector((N-1) downto 0);
y62: out std_logic_vector((N-1) downto 0);
y63: out std_logic_vector((N-1) downto 0);
y64: out std_logic_vector((N-1) downto 0);
y65: out std_logic_vector((N-1) downto 0);
y66: out std_logic_vector((N-1) downto 0);
y67: out std_logic_vector((N-1) downto 0);
y68: out std_logic_vector((N-1) downto 0);
y69: out std_logic_vector((N-1) downto 0);
y70: out std_logic_vector((N-1) downto 0);
y71: out std_logic_vector((N-1) downto 0);
y72: out std_logic_vector((N-1) downto 0);
y73: out std_logic_vector((N-1) downto 0);
y74: out std_logic_vector((N-1) downto 0);
y75: out std_logic_vector((N-1) downto 0);
y76: out std_logic_vector((N-1) downto 0);
y77: out std_logic_vector((N-1) downto 0);
y78: out std_logic_vector((N-1) downto 0);
y79: out std_logic_vector((N-1) downto 0);
y80: out std_logic_vector((N-1) downto 0);
y81: out std_logic_vector((N-1) downto 0);
y82: out std_logic_vector((N-1) downto 0);
y83: out std_logic_vector((N-1) downto 0);
y84: out std_logic_vector((N-1) downto 0);
y85: out std_logic_vector((N-1) downto 0);
y86: out std_logic_vector((N-1) downto 0);
y87: out std_logic_vector((N-1) downto 0);
y88: out std_logic_vector((N-1) downto 0);
y89: out std_logic_vector((N-1) downto 0);
y90: out std_logic_vector((N-1) downto 0);
y91: out std_logic_vector((N-1) downto 0);
y92: out std_logic_vector((N-1) downto 0);
y93: out std_logic_vector((N-1) downto 0);
y94: out std_logic_vector((N-1) downto 0);
y95: out std_logic_vector((N-1) downto 0);
y96: out std_logic_vector((N-1) downto 0);
y97: out std_logic_vector((N-1) downto 0);
y98: out std_logic_vector((N-1) downto 0);
y99: out std_logic_vector((N-1) downto 0);
y100: out std_logic_vector((N-1) downto 0);
y101: out std_logic_vector((N-1) downto 0);
y102: out std_logic_vector((N-1) downto 0);
y103: out std_logic_vector((N-1) downto 0);
y104: out std_logic_vector((N-1) downto 0);
y105: out std_logic_vector((N-1) downto 0);
y106: out std_logic_vector((N-1) downto 0);
y107: out std_logic_vector((N-1) downto 0);
y108: out std_logic_vector((N-1) downto 0);
y109: out std_logic_vector((N-1) downto 0);
y110: out std_logic_vector((N-1) downto 0);
y111: out std_logic_vector((N-1) downto 0);
y112: out std_logic_vector((N-1) downto 0);
y113: out std_logic_vector((N-1) downto 0);
y114: out std_logic_vector((N-1) downto 0);
y115: out std_logic_vector((N-1) downto 0);
y116: out std_logic_vector((N-1) downto 0);
y117: out std_logic_vector((N-1) downto 0);
y118: out std_logic_vector((N-1) downto 0);
y119: out std_logic_vector((N-1) downto 0);
y120: out std_logic_vector((N-1) downto 0);
y121: out std_logic_vector((N-1) downto 0);
y122: out std_logic_vector((N-1) downto 0);
y123: out std_logic_vector((N-1) downto 0);
y124: out std_logic_vector((N-1) downto 0);
y125: out std_logic_vector((N-1) downto 0);
y126: out std_logic_vector((N-1) downto 0);
y127: out std_logic_vector((N-1) downto 0);
y128: out std_logic_vector((N-1) downto 0);
y129: out std_logic_vector((N-1) downto 0);
y130: out std_logic_vector((N-1) downto 0);
y131: out std_logic_vector((N-1) downto 0);
y132: out std_logic_vector((N-1) downto 0);
y133: out std_logic_vector((N-1) downto 0);
y134: out std_logic_vector((N-1) downto 0);
y135: out std_logic_vector((N-1) downto 0);
y136: out std_logic_vector((N-1) downto 0);
y137: out std_logic_vector((N-1) downto 0);
y138: out std_logic_vector((N-1) downto 0);
y139: out std_logic_vector((N-1) downto 0);
y140: out std_logic_vector((N-1) downto 0);
y141: out std_logic_vector((N-1) downto 0);
y142: out std_logic_vector((N-1) downto 0);
y143: out std_logic_vector((N-1) downto 0);
y144: out std_logic_vector((N-1) downto 0);
y145: out std_logic_vector((N-1) downto 0);
y146: out std_logic_vector((N-1) downto 0);
y147: out std_logic_vector((N-1) downto 0);
y148: out std_logic_vector((N-1) downto 0);
y149: out std_logic_vector((N-1) downto 0);
y150: out std_logic_vector((N-1) downto 0);
y151: out std_logic_vector((N-1) downto 0);
y152: out std_logic_vector((N-1) downto 0);
y153: out std_logic_vector((N-1) downto 0);
y154: out std_logic_vector((N-1) downto 0);
y155: out std_logic_vector((N-1) downto 0);
y156: out std_logic_vector((N-1) downto 0);
y157: out std_logic_vector((N-1) downto 0);
y158: out std_logic_vector((N-1) downto 0);
y159: out std_logic_vector((N-1) downto 0);
y160: out std_logic_vector((N-1) downto 0);
y161: out std_logic_vector((N-1) downto 0);
y162: out std_logic_vector((N-1) downto 0);
y163: out std_logic_vector((N-1) downto 0);
y164: out std_logic_vector((N-1) downto 0);
y165: out std_logic_vector((N-1) downto 0);
y166: out std_logic_vector((N-1) downto 0);
y167: out std_logic_vector((N-1) downto 0);
y168: out std_logic_vector((N-1) downto 0);
y169: out std_logic_vector((N-1) downto 0);
y170: out std_logic_vector((N-1) downto 0);
y171: out std_logic_vector((N-1) downto 0);
y172: out std_logic_vector((N-1) downto 0);
y173: out std_logic_vector((N-1) downto 0);
y174: out std_logic_vector((N-1) downto 0);
y175: out std_logic_vector((N-1) downto 0);
y176: out std_logic_vector((N-1) downto 0);
y177: out std_logic_vector((N-1) downto 0);
y178: out std_logic_vector((N-1) downto 0);
y179: out std_logic_vector((N-1) downto 0);
y180: out std_logic_vector((N-1) downto 0);
y181: out std_logic_vector((N-1) downto 0);
y182: out std_logic_vector((N-1) downto 0);
y183: out std_logic_vector((N-1) downto 0);
y184: out std_logic_vector((N-1) downto 0);
y185: out std_logic_vector((N-1) downto 0);
y186: out std_logic_vector((N-1) downto 0);
y187: out std_logic_vector((N-1) downto 0);
y188: out std_logic_vector((N-1) downto 0);
y189: out std_logic_vector((N-1) downto 0);
y190: out std_logic_vector((N-1) downto 0);
y191: out std_logic_vector((N-1) downto 0);
y192: out std_logic_vector((N-1) downto 0);
y193: out std_logic_vector((N-1) downto 0);
y194: out std_logic_vector((N-1) downto 0);
y195: out std_logic_vector((N-1) downto 0);
y196: out std_logic_vector((N-1) downto 0);
y197: out std_logic_vector((N-1) downto 0);
y198: out std_logic_vector((N-1) downto 0);
y199: out std_logic_vector((N-1) downto 0);
y200: out std_logic_vector((N-1) downto 0);
y201: out std_logic_vector((N-1) downto 0);
y202: out std_logic_vector((N-1) downto 0);
y203: out std_logic_vector((N-1) downto 0);
y204: out std_logic_vector((N-1) downto 0);
y205: out std_logic_vector((N-1) downto 0);
y206: out std_logic_vector((N-1) downto 0);
y207: out std_logic_vector((N-1) downto 0);
y208: out std_logic_vector((N-1) downto 0);
y209: out std_logic_vector((N-1) downto 0);
y210: out std_logic_vector((N-1) downto 0);
y211: out std_logic_vector((N-1) downto 0);
y212: out std_logic_vector((N-1) downto 0);
y213: out std_logic_vector((N-1) downto 0);
y214: out std_logic_vector((N-1) downto 0);
y215: out std_logic_vector((N-1) downto 0);
y216: out std_logic_vector((N-1) downto 0);
y217: out std_logic_vector((N-1) downto 0);
y218: out std_logic_vector((N-1) downto 0);
y219: out std_logic_vector((N-1) downto 0);
y220: out std_logic_vector((N-1) downto 0);
y221: out std_logic_vector((N-1) downto 0);
y222: out std_logic_vector((N-1) downto 0);
y223: out std_logic_vector((N-1) downto 0);
y224: out std_logic_vector((N-1) downto 0);
y225: out std_logic_vector((N-1) downto 0);
y226: out std_logic_vector((N-1) downto 0);
y227: out std_logic_vector((N-1) downto 0);
y228: out std_logic_vector((N-1) downto 0);
y229: out std_logic_vector((N-1) downto 0);
y230: out std_logic_vector((N-1) downto 0);
y231: out std_logic_vector((N-1) downto 0);
y232: out std_logic_vector((N-1) downto 0);
y233: out std_logic_vector((N-1) downto 0);
y234: out std_logic_vector((N-1) downto 0);
y235: out std_logic_vector((N-1) downto 0);
y236: out std_logic_vector((N-1) downto 0);
y237: out std_logic_vector((N-1) downto 0);
y238: out std_logic_vector((N-1) downto 0);
y239: out std_logic_vector((N-1) downto 0);
y240: out std_logic_vector((N-1) downto 0);
y241: out std_logic_vector((N-1) downto 0);
y242: out std_logic_vector((N-1) downto 0);
y243: out std_logic_vector((N-1) downto 0);
y244: out std_logic_vector((N-1) downto 0);
y245: out std_logic_vector((N-1) downto 0);
y246: out std_logic_vector((N-1) downto 0);
y247: out std_logic_vector((N-1) downto 0);
y248: out std_logic_vector((N-1) downto 0);
y249: out std_logic_vector((N-1) downto 0);
y250: out std_logic_vector((N-1) downto 0);
y251: out std_logic_vector((N-1) downto 0);
y252: out std_logic_vector((N-1) downto 0);
y253: out std_logic_vector((N-1) downto 0);
y254: out std_logic_vector((N-1) downto 0);
y255: out std_logic_vector((N-1) downto 0);
address: in std_logic_vector(7 downto 0)
);
end;
architecture struct_decoderNx256 of decoderNx256 is
component decoder1x256 is
port(
data: in std_logic;
y0: out std_logic;
y1: out std_logic;
y2: out std_logic;
y3: out std_logic;
y4: out std_logic;
y5: out std_logic;
y6: out std_logic;
y7: out std_logic;
y8: out std_logic;
y9: out std_logic;
y10: out std_logic;
y11: out std_logic;
y12: out std_logic;
y13: out std_logic;
y14: out std_logic;
y15: out std_logic;
y16: out std_logic;
y17: out std_logic;
y18: out std_logic;
y19: out std_logic;
y20: out std_logic;
y21: out std_logic;
y22: out std_logic;
y23: out std_logic;
y24: out std_logic;
y25: out std_logic;
y26: out std_logic;
y27: out std_logic;
y28: out std_logic;
y29: out std_logic;
y30: out std_logic;
y31: out std_logic;
y32: out std_logic;
y33: out std_logic;
y34: out std_logic;
y35: out std_logic;
y36: out std_logic;
y37: out std_logic;
y38: out std_logic;
y39: out std_logic;
y40: out std_logic;
y41: out std_logic;
y42: out std_logic;
y43: out std_logic;
y44: out std_logic;
y45: out std_logic;
y46: out std_logic;
y47: out std_logic;
y48: out std_logic;
y49: out std_logic;
y50: out std_logic;
y51: out std_logic;
y52: out std_logic;
y53: out std_logic;
y54: out std_logic;
y55: out std_logic;
y56: out std_logic;
y57: out std_logic;
y58: out std_logic;
y59: out std_logic;
y60: out std_logic;
y61: out std_logic;
y62: out std_logic;
y63: out std_logic;
y64: out std_logic;
y65: out std_logic;
y66: out std_logic;
y67: out std_logic;
y68: out std_logic;
y69: out std_logic;
y70: out std_logic;
y71: out std_logic;
y72: out std_logic;
y73: out std_logic;
y74: out std_logic;
y75: out std_logic;
y76: out std_logic;
y77: out std_logic;
y78: out std_logic;
y79: out std_logic;
y80: out std_logic;
y81: out std_logic;
y82: out std_logic;
y83: out std_logic;
y84: out std_logic;
y85: out std_logic;
y86: out std_logic;
y87: out std_logic;
y88: out std_logic;
y89: out std_logic;
y90: out std_logic;
y91: out std_logic;
y92: out std_logic;
y93: out std_logic;
y94: out std_logic;
y95: out std_logic;
y96: out std_logic;
y97: out std_logic;
y98: out std_logic;
y99: out std_logic;
y100: out std_logic;
y101: out std_logic;
y102: out std_logic;
y103: out std_logic;
y104: out std_logic;
y105: out std_logic;
y106: out std_logic;
y107: out std_logic;
y108: out std_logic;
y109: out std_logic;
y110: out std_logic;
y111: out std_logic;
y112: out std_logic;
y113: out std_logic;
y114: out std_logic;
y115: out std_logic;
y116: out std_logic;
y117: out std_logic;
y118: out std_logic;
y119: out std_logic;
y120: out std_logic;
y121: out std_logic;
y122: out std_logic;
y123: out std_logic;
y124: out std_logic;
y125: out std_logic;
y126: out std_logic;
y127: out std_logic;
y128: out std_logic;
y129: out std_logic;
y130: out std_logic;
y131: out std_logic;
y132: out std_logic;
y133: out std_logic;
y134: out std_logic;
y135: out std_logic;
y136: out std_logic;
y137: out std_logic;
y138: out std_logic;
y139: out std_logic;
y140: out std_logic;
y141: out std_logic;
y142: out std_logic;
y143: out std_logic;
y144: out std_logic;
y145: out std_logic;
y146: out std_logic;
y147: out std_logic;
y148: out std_logic;
y149: out std_logic;
y150: out std_logic;
y151: out std_logic;
y152: out std_logic;
y153: out std_logic;
y154: out std_logic;
y155: out std_logic;
y156: out std_logic;
y157: out std_logic;
y158: out std_logic;
y159: out std_logic;
y160: out std_logic;
y161: out std_logic;
y162: out std_logic;
y163: out std_logic;
y164: out std_logic;
y165: out std_logic;
y166: out std_logic;
y167: out std_logic;
y168: out std_logic;
y169: out std_logic;
y170: out std_logic;
y171: out std_logic;
y172: out std_logic;
y173: out std_logic;
y174: out std_logic;
y175: out std_logic;
y176: out std_logic;
y177: out std_logic;
y178: out std_logic;
y179: out std_logic;
y180: out std_logic;
y181: out std_logic;
y182: out std_logic;
y183: out std_logic;
y184: out std_logic;
y185: out std_logic;
y186: out std_logic;
y187: out std_logic;
y188: out std_logic;
y189: out std_logic;
y190: out std_logic;
y191: out std_logic;
y192: out std_logic;
y193: out std_logic;
y194: out std_logic;
y195: out std_logic;
y196: out std_logic;
y197: out std_logic;
y198: out std_logic;
y199: out std_logic;
y200: out std_logic;
y201: out std_logic;
y202: out std_logic;
y203: out std_logic;
y204: out std_logic;
y205: out std_logic;
y206: out std_logic;
y207: out std_logic;
y208: out std_logic;
y209: out std_logic;
y210: out std_logic;
y211: out std_logic;
y212: out std_logic;
y213: out std_logic;
y214: out std_logic;
y215: out std_logic;
y216: out std_logic;
y217: out std_logic;
y218: out std_logic;
y219: out std_logic;
y220: out std_logic;
y221: out std_logic;
y222: out std_logic;
y223: out std_logic;
y224: out std_logic;
y225: out std_logic;
y226: out std_logic;
y227: out std_logic;
y228: out std_logic;
y229: out std_logic;
y230: out std_logic;
y231: out std_logic;
y232: out std_logic;
y233: out std_logic;
y234: out std_logic;
y235: out std_logic;
y236: out std_logic;
y237: out std_logic;
y238: out std_logic;
y239: out std_logic;
y240: out std_logic;
y241: out std_logic;
y242: out std_logic;
y243: out std_logic;
y244: out std_logic;
y245: out std_logic;
y246: out std_logic;
y247: out std_logic;
y248: out std_logic;
y249: out std_logic;
y250: out std_logic;
y251: out std_logic;
y252: out std_logic;
y253: out std_logic;
y254: out std_logic;
y255: out std_logic;
address: in std_logic_vector(7 downto 0)
);
end component;
begin
u1: for i in (N-1) downto 0 generate
u: decoder1x256 port map(
data => data(i),
y0 => y0(i),
y1 => y1(i),
y2 => y2(i),
y3 => y3(i),
y4 => y4(i),
y5 => y5(i),
y6 => y6(i),
y7 => y7(i),
y8 => y8(i),
y9 => y9(i),
y10 => y10(i),
y11 => y11(i),
y12 => y12(i),
y13 => y13(i),
y14 => y14(i),
y15 => y15(i),
y16 => y16(i),
y17 => y17(i),
y18 => y18(i),
y19 => y19(i),
y20 => y20(i),
y21 => y21(i),
y22 => y22(i),
y23 => y23(i),
y24 => y24(i),
y25 => y25(i),
y26 => y26(i),
y27 => y27(i),
y28 => y28(i),
y29 => y29(i),
y30 => y30(i),
y31 => y31(i),
y32 => y32(i),
y33 => y33(i),
y34 => y34(i),
y35 => y35(i),
y36 => y36(i),
y37 => y37(i),
y38 => y38(i),
y39 => y39(i),
y40 => y40(i),
y41 => y41(i),
y42 => y42(i),
y43 => y43(i),
y44 => y44(i),
y45 => y45(i),
y46 => y46(i),
y47 => y47(i),
y48 => y48(i),
y49 => y49(i),
y50 => y50(i),
y51 => y51(i),
y52 => y52(i),
y53 => y53(i),
y54 => y54(i),
y55 => y55(i),
y56 => y56(i),
y57 => y57(i),
y58 => y58(i),
y59 => y59(i),
y60 => y60(i),
y61 => y61(i),
y62 => y62(i),
y63 => y63(i),
y64 => y64(i),
y65 => y65(i),
y66 => y66(i),
y67 => y67(i),
y68 => y68(i),
y69 => y69(i),
y70 => y70(i),
y71 => y71(i),
y72 => y72(i),
y73 => y73(i),
y74 => y74(i),
y75 => y75(i),
y76 => y76(i),
y77 => y77(i),
y78 => y78(i),
y79 => y79(i),
y80 => y80(i),
y81 => y81(i),
y82 => y82(i),
y83 => y83(i),
y84 => y84(i),
y85 => y85(i),
y86 => y86(i),
y87 => y87(i),
y88 => y88(i),
y89 => y89(i),
y90 => y90(i),
y91 => y91(i),
y92 => y92(i),
y93 => y93(i),
y94 => y94(i),
y95 => y95(i),
y96 => y96(i),
y97 => y97(i),
y98 => y98(i),
y99 => y99(i),
y100 => y100(i),
y101 => y101(i),
y102 => y102(i),
y103 => y103(i),
y104 => y104(i),
y105 => y105(i),
y106 => y106(i),
y107 => y107(i),
y108 => y108(i),
y109 => y109(i),
y110 => y110(i),
y111 => y111(i),
y112 => y112(i),
y113 => y113(i),
y114 => y114(i),
y115 => y115(i),
y116 => y116(i),
y117 => y117(i),
y118 => y118(i),
y119 => y119(i),
y120 => y120(i),
y121 => y121(i),
y122 => y122(i),
y123 => y123(i),
y124 => y124(i),
y125 => y125(i),
y126 => y126(i),
y127 => y127(i),
y128 => y128(i),
y129 => y129(i),
y130 => y130(i),
y131 => y131(i),
y132 => y132(i),
y133 => y133(i),
y134 => y134(i),
y135 => y135(i),
y136 => y136(i),
y137 => y137(i),
y138 => y138(i),
y139 => y139(i),
y140 => y140(i),
y141 => y141(i),
y142 => y142(i),
y143 => y143(i),
y144 => y144(i),
y145 => y145(i),
y146 => y146(i),
y147 => y147(i),
y148 => y148(i),
y149 => y149(i),
y150 => y150(i),
y151 => y151(i),
y152 => y152(i),
y153 => y153(i),
y154 => y154(i),
y155 => y155(i),
y156 => y156(i),
y157 => y157(i),
y158 => y158(i),
y159 => y159(i),
y160 => y160(i),
y161 => y161(i),
y162 => y162(i),
y163 => y163(i),
y164 => y164(i),
y165 => y165(i),
y166 => y166(i),
y167 => y167(i),
y168 => y168(i),
y169 => y169(i),
y170 => y170(i),
y171 => y171(i),
y172 => y172(i),
y173 => y173(i),
y174 => y174(i),
y175 => y175(i),
y176 => y176(i),
y177 => y177(i),
y178 => y178(i),
y179 => y179(i),
y180 => y180(i),
y181 => y181(i),
y182 => y182(i),
y183 => y183(i),
y184 => y184(i),
y185 => y185(i),
y186 => y186(i),
y187 => y187(i),
y188 => y188(i),
y189 => y189(i),
y190 => y190(i),
y191 => y191(i),
y192 => y192(i),
y193 => y193(i),
y194 => y194(i),
y195 => y195(i),
y196 => y196(i),
y197 => y197(i),
y198 => y198(i),
y199 => y199(i),
y200 => y200(i),
y201 => y201(i),
y202 => y202(i),
y203 => y203(i),
y204 => y204(i),
y205 => y205(i),
y206 => y206(i),
y207 => y207(i),
y208 => y208(i),
y209 => y209(i),
y210 => y210(i),
y211 => y211(i),
y212 => y212(i),
y213 => y213(i),
y214 => y214(i),
y215 => y215(i),
y216 => y216(i),
y217 => y217(i),
y218 => y218(i),
y219 => y219(i),
y220 => y220(i),
y221 => y221(i),
y222 => y222(i),
y223 => y223(i),
y224 => y224(i),
y225 => y225(i),
y226 => y226(i),
y227 => y227(i),
y228 => y228(i),
y229 => y229(i),
y230 => y230(i),
y231 => y231(i),
y232 => y232(i),
y233 => y233(i),
y234 => y234(i),
y235 => y235(i),
y236 => y236(i),
y237 => y237(i),
y238 => y238(i),
y239 => y239(i),
y240 => y240(i),
y241 => y241(i),
y242 => y242(i),
y243 => y243(i),
y244 => y244(i),
y245 => y245(i),
y246 => y246(i),
y247 => y247(i),
y248 => y248(i),
y249 => y249(i),
y250 => y250(i),
y251 => y251(i),
y252 => y252(i),
y253 => y253(i),
y254 => y254(i),
y255 => y255(i),
address => address
);
end generate u1;
end;
library ieee;
use ieee.std_logic_1164.all;
entity counterN is
generic(
N: positive
);
port(
clock: in std_logic;
carry_in: in std_logic;
clock_enable: in std_logic;
resetn: in std_logic;
output: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end;
architecture struct_counterN of counterN is
component incrementerN is
generic(
N: positive
);
port(
input: in std_logic_vector((N-1) downto 0);
carry_in: in std_logic;
sum: out std_logic_vector((N-1) downto 0);
carry_out: out std_logic
);
end component;
component andNbit is
generic(
N: positive
);
port(
input: in std_logic_vector((N-1) downto 0);
y: out std_logic
);
end component;
component synchronous_latchN is
generic(
N: positive
);
port(
rstn: in std_logic;
clock: in std_logic;
clock_enable: in std_logic;
d: in std_logic_vector((N-1) downto 0);
q: out std_logic_vector((N-1) downto 0)
);
end component;
signal counter_out: std_logic_vector(N downto 0);
signal incrementer_out: std_logic_vector(N downto 0);
signal all_ones: std_logic;
begin
u1: incrementerN
generic map(
N => N
)
port map(
input => counter_out((N-1) downto 0),
carry_in => carry_in,
sum => incrementer_out((N-1) downto 0),
carry_out => incrementer_out(N)
);
u2: synchronous_latchN
generic map(
N => (N + 1)
)
port map(
rstn => resetn,
clock => clock,
clock_enable => clock_enable,
d => incrementer_out,
q => counter_out
);
u3: andNbit
generic map(
N => N
)
port map(
input => counter_out((N-1) downto 0),
y => all_ones
);
carry_out <= all_ones and carry_in;
output <= counter_out((N-1) downto 0);
end;
|
gpl-2.0
|
24d8dd422a323be0fba0654f16ee4d28
| 0.631473 | 2.189779 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd
| 4 | 10,240 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc863.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00863pkg_b is
constant zero : integer ;
constant one : integer ;
constant two : integer ;
constant three: integer ;
constant four : integer ;
constant five : integer ;
constant six : integer ;
constant seven: integer ;
constant eight: integer ;
constant nine : integer ;
constant fifteen: integer;
end c01s03b01x00p12n01i00863pkg_b;
package body c01s03b01x00p12n01i00863pkg_b is
constant zero : integer := 0;
constant one : integer := 1;
constant two : integer := 2;
constant three: integer := 3;
constant four : integer := 4;
constant five : integer := 5;
constant six : integer := 6;
constant seven: integer := 7;
constant eight: integer := 8;
constant nine : integer := 9;
constant fifteen:integer:= 15;
end c01s03b01x00p12n01i00863pkg_b;
use work.c01s03b01x00p12n01i00863pkg_b.all;
package c01s03b01x00p12n01i00863pkg_a is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
signal Sin1 : bit_vector(zero to five) ;
signal Sin2 : boolean_vector(zero to five) ;
signal Sin4 : severity_level_vector(zero to five) ;
signal Sin5 : integer_vector(zero to five) ;
signal Sin6 : real_vector(zero to five) ;
signal Sin7 : time_vector(zero to five) ;
signal Sin8 : natural_vector(zero to five) ;
signal Sin9 : positive_vector(zero to five) ;
signal Sin10: array_rec_std(zero to five) ;
end c01s03b01x00p12n01i00863pkg_a;
use work.c01s03b01x00p12n01i00863pkg_a.all;
use work.c01s03b01x00p12n01i00863pkg_b.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00863pkg_a.all;
use work.c01s03b01x00p12n01i00863pkg_b.all;
ENTITY c01s03b01x00p12n01i00863ent IS
END c01s03b01x00p12n01i00863ent;
ARCHITECTURE c01s03b01x00p12n01i00863arch OF c01s03b01x00p12n01i00863ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00863"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00863 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00863arch;
configuration c01s03b01x00p12n01i00863cfg of c01s03b01x00p12n01i00863ent is
for c01s03b01x00p12n01i00863arch
for K
for T5:test use configuration work.testbench;
end for;
for G(3)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(0 to 2)
for all:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
|
gpl-2.0
|
6076d60387a1ed8f7828a82a3b64037a
| 0.592773 | 3.356277 | false | true | false | false |
tgingold/ghdl
|
testsuite/synth/dff02/tb_dff09.vhdl
| 1 | 865 |
entity tb_dff09 is
end tb_dff09;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff09 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (3 downto 0);
signal dout : std_logic_vector (3 downto 0);
begin
dut: entity work.dff09
port map (
q => dout,
d => din,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '1';
pulse;
assert dout = x"0" severity failure;
rst <= '0';
din <= x"3";
pulse;
assert dout = x"3" severity failure;
din <= x"a";
pulse;
assert dout = x"a" severity failure;
rst <= '1';
din <= x"5";
pulse;
assert dout = x"0" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
ff3521a392bc36f3b7bd446c9d079145
| 0.554913 | 3.288973 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue779/tvm_pkg.vhdl
| 1 | 1,814 |
library ieee;
use ieee.std_logic_1164.all;
library ipbus;
package ipbus_tvm_pkg is
--===============================================================================================
-- Types and constants for IPbus TVM
--===============================================================================================
constant C_SCOPE : string := "IPbus TVM";
type t_ipbus_transaction_type_id is (
READ,
WRITE,
NON_INC_READ, -- Non-incrementing read
NON_INC_WRITE, -- Non-incrementing write
RMW_BITS, -- Read/modify/write bits
RMW_SUM, -- Read/modify/write sum
CONF_SPACE_READ, -- Configuration space read
CONF_SPACE_WRITE -- Configuration space write
);
type t_ipbus_transaction_info_code is (
REQ_HANDLED_SUCCESSFULLY, -- Request handled successfully by target
BAD_HEADER,
RESERVED_0x2,
RESERVED_0x3,
BUS_ERROR_ON_READ,
BUS_ERROR_ON_WRITE,
BUS_TIMEOUT_ON_READ,
BUS_TIMEOUT_ON_WRITE,
RESERVED_0x8,
RESERVED_0x9,
RESERVED_0xA,
RESERVED_0xB,
RESERVED_0xC,
RESERVED_0xD,
RESERVED_0xE,
OUTBOUND_REQUEST
);
type t_ipbus_tranaction_header is
record
protocol_version : natural;
transaction_id : natural;
words : natural;
type_id : t_ipbus_transaction_type_id;
info_code : t_ipbus_transaction_info_code;
end record;
type t_ipbus_transaction is
record
header : t_ipbus_tranaction_header;
_body : t_slv_array;
end record;
end package ipbus_tvm_pkg;
--=================================================================================================
--=================================================================================================
package body ipbus_tvm_pkg is
end package body ipbus_tvm_pkg;
|
gpl-2.0
|
30ca00589e90134d5c20f1a217681ecd
| 0.507718 | 4.228438 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd
| 3 | 11,936 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
gpl-3.0
|
6d2145bbd1aaff0b545253b3ec822ce4
| 0.454675 | 4.420741 | false | false | false | false |
nickg/nvc
|
test/regress/elab21.vhd
| 1 | 1,007 |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec := (0, 0);
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
e7d0cd5c54d73e219d24e6431ed195bd
| 0.405164 | 3.675182 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd
| 4 | 5,858 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1205.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s01b00x00p08n03i01205pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c08s01b00x00p08n03i01205pkg;
package body c08s01b00x00p08n03i01205pkg is
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c08s01b00x00p08n03i01205pkg;
use work.c08s01b00x00p08n03i01205pkg.all;
entity c08s01b00x00p08n03i01205ent_a is
generic ( GenOne : in INTEGER ; GenTwo :INTEGER);
end c08s01b00x00p08n03i01205ent_a;
-------------------------------------------------------------------------
architecture c08s01b00x00p08n03i01205arch_a of c08s01b00x00p08n03i01205ent_a is
-- Type definitions.
type WORD2 is array( 0 to 31 ) of SWITCH_LEVEL;
-- Local signals.
signal A, B : WORD;
signal UnResolved : WORD2;
begin
TEST_PROCESS: process
-- Constant declarations.
constant One : INTEGER := 1;
constant Two : INTEGER := 2;
-- Local variables.
variable ShouldBeTime : TIME;
variable I : INTEGER;
variable k : integer := 0;
begin
-- Test locally static signals.
A( 1 ) <= 'X' after 10 ns;
A( 2 ) <= 'X' after 5 ns;
ShouldBeTime := NOW + 10 ns;
wait on A(1);
-- Should wake up when the A(1) assignment takes place.
assert (A(1) = 'X');
assert (ShouldBeTime = NOW);
if (A(1) /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
-- Perform same test, but with a constant.
A( One ) <= '1' after 10 ns;
A( Two ) <= '1' after 5 ns;
ShouldBeTime := NOW + 10 ns;
wait on A(One);
-- Should wake up when the A(1) assignment takes place.
assert (A(One) = '1');
assert (ShouldBeTime = NOW);
if (A(One) /= '1' and ShouldBeTime /= Now) then
k := 1;
end if;
-- Perform same test, but with a generic. (globally static)
A( GenOne ) <= 'X' after 10 ns;
A( GenTwo ) <= 'X' after 5 ns;
ShouldBeTime := NOW + 10 ns;
wait on A(GenOne);
-- Should wake up when the A(1) assignment takes place.
assert (A(GenOne) = 'X');
assert (ShouldBeTime = NOW);
if (A(GenOne) /= 'X' and ShouldBeTime /= Now) then
k := 1;
end if;
-- Perform same test, but assigning to the whole thing.
A <= ('1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1') after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on A(GenOne);
-- Should wake up when the all assignments take place.
assert (A(GenOne) = '1');
assert (ShouldBeTime = NOW);
if (A(GenOne) /= '1' and ShouldBeTime /= Now) then
k := 1;
end if;
-- Now, perform same test but assigning to a composite
-- signal which is NOT resolved at the scalar subelement
-- level.
UnResolved <= ('1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1','1','1','1','1','1','1','1','1',
'1','1') after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on UnResolved(GenOne);
-- Should wake up when the all assignments take place.
assert (UnResolved(GenOne) = '1');
assert (ShouldBeTime = NOW);
if (UnResolved(GenOne) /= '1' and ShouldBeTime /= Now) then
k := 1;
end if;
assert NOT(k = 0)
report "***PASSED TEST: c08s01b00x00p08n03i01205"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c08s01b00x00p08n03i01205 - All statically indexed signal names (both locally and globally static) may be used in the sensitivity clause of a wait statement."
severity ERROR;
wait;
end process TEST_PROCESS;
end c08s01b00x00p08n03i01205arch_a;
use work.c08s01b00x00p08n03i01205pkg.all;
ENTITY c08s01b00x00p08n03i01205ent IS
END c08s01b00x00p08n03i01205ent;
ARCHITECTURE c08s01b00x00p08n03i01205arch OF c08s01b00x00p08n03i01205ent IS
component c08s01b00x00p08n03i01205ent_a
generic( GenOne : in INTEGER; GenTwo : INTEGER );
end component;
for T1 : c08s01b00x00p08n03i01205ent_a use entity work.c08s01b00x00p08n03i01205ent_a(c08s01b00x00p08n03i01205arch_a);
BEGIN
T1 : c08s01b00x00p08n03i01205ent_a generic map ( 1, 2 );
END c08s01b00x00p08n03i01205arch;
|
gpl-2.0
|
2360bb58f2b302c7677f23f37c3d4b98
| 0.604131 | 3.366667 | false | true | false | false |
nickg/nvc
|
test/regress/shift1.vhd
| 1 | 1,365 |
entity shift1 is
end entity;
architecture test of shift1 is
begin
process is
variable b : bit_vector(3 downto 0);
variable c : bit_vector(0 to 3);
variable d : bit_vector(0 to -1);
begin
b := "1011";
c := "1011";
wait for 1 ns;
assert (b sll 1) = "0110";
assert (c sll 1) = "0110";
assert (b srl 1) = "0101";
assert (c srl 1) = "0101";
assert (b sla 1) = "0111";
assert (c sla 1) = "0111";
assert (b sra 1) = "1101";
assert (c sra 1) = "1101";
assert (b rol 2) = "1110";
assert (c rol 2) = "1110";
assert (b ror 1) = "1101";
assert (c ror 1) = "1101";
assert (b srl -1) = "0110";
assert (c srl -1) = "0110";
assert (b sll -1) = "0101";
assert (c sll -1) = "0101";
assert (b sra -1) = "0111";
assert (c sra -1) = "0111";
assert (b sla -1) = "1101";
assert (c sla -1) = "1101";
assert (b ror -2) = "1110";
assert (c ror -2) = "1110";
assert (b rol -1) = "1101";
assert (c rol -1) = "1101";
assert (c rol -5) = "1101";
assert (d sll 1) = d; -- Null array
b := "0001";
wait for 1 ns;
assert (b sll -4) = "0000";
wait;
end process;
end architecture;
|
gpl-3.0
|
39b90ba6dee3ab478854fdaa1fa0aecd
| 0.449084 | 3.273381 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd
| 4 | 2,533 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1507.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p16n01i01507ent IS
END c08s08b00x00p16n01i01507ent;
ARCHITECTURE c08s08b00x00p16n01i01507arch OF c08s08b00x00p16n01i01507ent IS
BEGIN
TESTING: PROCESS
variable s1, s2, s3, s4, s5, s6 : INTEGER := 0;
BEGIN
for i in 1 to 1000 loop
case i is
when 1 => s1 := s1 + 1;
when 2 | 3 => s2 := s2 + 1;
when 4 to 100 => s3 := s3 + 1;
when 200 to 201 | 300 to 350 => s4 := s4 + 1;
when 400 to 450 => s5 := s5 + 1;
when others => s6 := s6 + 1;
end case;
end loop;
wait for 5 ns;
assert NOT( s1 = 1 and
s2 = 2 and
s3 = 97 and
s4 = 2 + 51 and
s5 = 51 and
s6 = 1000 - (s1+s2+s3+s4+s5) )
report "***PASSED TEST: c08s08b00x00p16n01i01507"
severity NOTE;
assert ( s1 = 1 and
s2 = 2 and
s3 = 97 and
s4 = 2 + 51 and
s5 = 51 and
s6 = 1000 - (s1+s2+s3+s4+s5) )
report "***FAILED TEST: c08s08b00x00p16n01i01507 - Case statement execution test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p16n01i01507arch;
|
gpl-2.0
|
81cc34e985f8d547c66f9fd87329d06f
| 0.545993 | 3.582744 | false | true | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1484.vhd
| 4 | 1,884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1484.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p04n03i01484ent IS
END c08s08b00x00p04n03i01484ent;
ARCHITECTURE c08s08b00x00p04n03i01484arch OF c08s08b00x00p04n03i01484ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable i : integer := 2;
BEGIN
case i is
when 2 => k = 5;
when true => NULL;
when others => NULL;
end case;
assert NOT( k = 5 )
report "***PASSED TEST: c08s08b00x00p04n03i01484"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s08b00x00p04n03i01484 - The case statement alternatives must be of the same type as the expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p04n03i01484arch;
|
gpl-2.0
|
ae8eec0c4980798f6cbd93d62a9db48f
| 0.652335 | 3.715976 | false | true | false | false |
snow4life/PipelinedDLX
|
ID_SIGN_EXT.vhd
| 1 | 643 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ID_SIGN_EXT is
port( INPUT: in std_logic_vector(15 downto 0);
SIGN_EXT_CONTROL: in std_logic;
OUTPUT: out std_logic_vector(31 downto 0));
end ID_SIGN_EXT;
architecture BEHAVIORAL of ID_SIGN_EXT is
begin
SIGN_EXTENSION_PROCESS: process(INPUT, SIGN_EXT_CONTROL)
begin
if SIGN_EXT_CONTROL = '0' then
-- unsigned
OUTPUT(31 downto 16) <= (others => '0');
OUTPUT(15 downto 0) <= INPUT;
else
-- signed
OUTPUT(31 downto 16) <= (31 downto 16 => INPUT(15));
OUTPUT(15 downto 0) <= INPUT;
end if;
end process;
end BEHAVIORAL;
|
lgpl-2.1
|
cf9ee911958f164f554eaf85cb04e63c
| 0.667185 | 2.845133 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/dff02/tb_dff08c.vhdl
| 1 | 1,199 |
entity tb_dff08c is
end tb_dff08c;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08c is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08c
port map (
q => dout,
d => din,
en => en,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = x"aa" severity failure;
rst <= '1';
en <= '1';
pulse;
assert dout = x"aa" severity failure;
rst <= '0';
din <= x"38";
pulse;
assert dout = x"38" severity failure;
din <= x"af";
pulse;
assert dout = x"af" severity failure;
en <= '0';
din <= x"b3";
pulse;
assert dout = x"af" severity failure;
en <= '0';
rst <= '1';
din <= x"b4";
pulse;
assert dout = x"af" severity failure;
en <= '1';
rst <= '1';
din <= x"b5";
pulse;
assert dout = x"aa" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
83fd21fe71ab8f7d0ad60ca33c99e522
| 0.53628 | 3.223118 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/issue1058/tb_ent.vhdl
| 1 | 412 |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal v : std_logic_vector (31 downto 0);
begin
dut: entity work.ent
port map (clk => clk, o => v);
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert v = x"8000_0000" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
d7557e162c810a7a9aed38853898ea6b
| 0.621359 | 3.097744 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue663/ent.vhdl
| 1 | 1,296 |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end entity ent;
architecture a of ent is
signal clk : std_logic := '0';
signal check_stable_in_1 : std_logic_vector(1 to 5) := "00000";
alias check_stable_start_event_1 : std_logic is check_stable_in_1(1);
alias check_stable_end_event_1 : std_logic is check_stable_in_1(2);
alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
signal check_stable_en_1 : std_logic;
signal en, start_event, end_event, expr : std_logic := '1';
procedure check_stable(
signal clock : in std_logic;
signal en : in std_logic;
signal start_event : in std_logic;
signal end_event : in std_logic;
signal expr : in std_logic_vector) is
begin
wait until (falling_edge(clock) or rising_edge(clock)) and (to_x01(en) = '1');
end;
begin
clock : process is
begin
clk <= '1', '0' after 5 ns;
wait;
end process clock;
check_stable_1 : check_stable(clk,
check_stable_en_1,
check_stable_start_event_1,
check_stable_end_event_1,
check_stable_expr_1);
end architecture;
|
gpl-2.0
|
4b5f26d076995271e6fb7734512d6210
| 0.567901 | 3.428571 | false | false | false | false |
nickg/nvc
|
test/regress/block2.vhd
| 1 | 518 |
entity block2 is
end entity;
architecture test of block2 is
signal x, y : integer;
begin
b1: block is
generic ( g1 : integer );
generic map ( g1 => 5 );
port ( i : in integer; o : out integer );
port map ( i => x, o => y );
begin
o <= i + g1;
end block;
stim: process is
begin
x <= 1;
wait for 1 ns;
assert y = 6;
x <= 10;
wait for 1 ns;
assert y = 15;
wait;
end process;
end architecture;
|
gpl-3.0
|
f665595c3e867db06f7743331c9bbb62
| 0.480695 | 3.647887 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reset.vhd
| 3 | 39,337 |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
gpl-3.0
|
870b46bec13e0964b801891d0ae0ab87
| 0.461576 | 4.131604 | false | false | false | false |
nickg/nvc
|
test/regress/textio4.vhd
| 1 | 5,567 |
entity textio4 is
end entity;
use std.textio.all;
architecture test of textio4 is
begin
check_int: process is
variable l : line;
variable x : integer;
variable good : boolean;
variable c : character;
begin
l := new string'(" 123,5");
read(l, x, good);
assert good;
assert x = 123;
assert l.all(l'left) = ',';
read(l, x, good);
assert not good;
assert l.all(l'left) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(l'left) = '5';
read(l, x, good);
assert good;
assert x = 5;
assert l.all'length = 0;
deallocate(l);
report "Negative integers";
l := new string'(" -123,-5");
read(l, x, good);
assert good;
assert x = -123;
assert l.all(l'left) = ',';
read(l, x, good);
assert not good;
assert l.all(l'left) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(l'left) = '-';
read(l, x, good);
assert good;
assert x = -5;
assert l.all'length = 0;
deallocate(l);
report "Integers min and max";
l := new string'(integer'image(integer'low) & "," & integer'image(integer'high));
read(l, x, good);
assert good;
assert x = integer'low;
read(l, c, good);
assert good;
read(l, x, good);
assert good;
assert x = integer'high;
assert l.all'length = 0;
deallocate(l);
report "Negative integer not good with single minus";
l := new string'("-,100");
read(l, x, good);
assert not good;
assert l.all(1) = '-';
read(l, c, good);
assert good;
assert c = '-';
read(l, c, good);
assert good;
assert c = ',';
read(l, x, good);
assert good;
assert x = 100;
assert l.all'length = 0;
deallocate(l);
report "Negative integer with minus in the middle";
l := new string'("10-10");
read(l, x, good);
assert good;
assert x = 10;
read(l, x, good);
assert good;
assert x = -10;
assert l.all'length = 0;
deallocate(l);
wait;
end process;
check_bool: process is
variable l : line;
variable x : boolean;
variable good : boolean;
variable c : character;
begin
l := new string'(" true,false");
read(l, x, good);
assert good;
assert x = true;
assert l.all(l'left) = ',';
read(l, x, good);
assert not good;
assert l.all(l'left) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(l'left) = 'f';
read(l, x, good);
assert good;
assert x = false;
assert l.all'length = 0;
deallocate(l);
wait;
end process;
check_real: process is
variable l : line;
variable x : real;
variable good : boolean;
variable c : character;
begin
l := new string'(" 5.152,61.4,5.");
read(l, x, good);
assert good;
assert x > 5.151 and x < 5.153;
assert l.all(l'left) = ',';
read(l, x, good);
assert not good;
assert l.all(l'left) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(l'left) = '6';
read(l, x, good);
assert good;
assert x > 61.39 and x < 61.41;
read(l, c, good);
assert good;
assert c = ',';
assert l.all(l'left) = '5';
read(l, x, good);
assert not good;
deallocate(l);
wait;
end process;
check_bit_vector: process is
variable l : line;
variable x : bit_vector(1 to 4);
variable y : bit_vector(7 downto 0);
variable good : boolean;
variable c : character;
begin
l := new string'(" 1010 110 11111");
read(l, x, good);
assert good;
assert x = "1010";
assert l.all(l'left) = ' ';
read(l, x(1 to 3), good);
assert good;
assert l.all(l'left) = ' ';
read(l, x, good);
assert good;
assert x = "1111";
assert l.all(l'left) = '1';
deallocate(l);
l := new string'("1 1 0 0 0 0 1 1");
read(l, y, good);
assert good;
assert y = "11000011";
deallocate(l);
wait;
end process;
check_bit: process is
variable l : line;
variable b : bit;
variable good : boolean;
begin
l := new string'(" 1 0x");
read(l, b, good);
assert good;
assert b = '1';
read(l, b);
assert good;
assert b = '0';
read(l, b, good);
assert not good;
deallocate(l);
wait;
end process;
check_time: process is
variable l : line;
variable t : time;
variable good : boolean;
begin
l := new string'(" 1 ns 15 sec 1 HR");
read(l, t, good);
assert good;
assert t = 1 ns;
read(l, t, good);
assert good;
assert t = 15 sec;
read(l, t, good);
assert good;
assert t = 1 hr;
read(l, t, good);
assert not good;
deallocate(l);
wait;
end process;
end architecture;
|
gpl-3.0
|
24a0ca80d99741415b93dd9c15245526
| 0.467038 | 3.741263 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/packer_12bit/packer_128.vhd
| 1 | 6,929 |
-------------------------------------------------------------------------------------
-- FILE NAME : packer_128.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity - packer_128
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : Jan 10, 2015
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- 16-bits as 8 samples =128-bits
-- 12-bits as 8 samples =96-bits
-- 12-bits * 8 samples * 4 cycles = 384-bits
-- 16-bits * 8 samples * 3 cycles = 384-bits
-- When val_in = '1', this entity will accept 4 chuncks of 128-bits unpacked and output
-- 3 chucks of 128-bits packed.
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity packer_128 is
port (
clk_in : in std_logic;
rst_in : in std_logic;
val_in : in std_logic;
data_in : in std_logic_vector(127 downto 0);
val_out : out std_logic;
data_out : out std_logic_vector(127 downto 0);
test_mode : in std_logic
);
end packer_128;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of packer_128 is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type state_machine is (state0, state1, state2, state3);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal sm_reg : state_machine;
signal reg0 : std_logic_vector(127 downto 0);
signal sample0 : std_logic_vector(11 downto 0);
signal sample1 : std_logic_vector(11 downto 0);
signal sample2 : std_logic_vector(11 downto 0);
signal sample3 : std_logic_vector(11 downto 0);
signal sample4 : std_logic_vector(11 downto 0);
signal sample5 : std_logic_vector(11 downto 0);
signal sample6 : std_logic_vector(11 downto 0);
signal sample7 : std_logic_vector(11 downto 0);
signal sample0_cnt : std_logic_vector(11 downto 0);
signal sample1_cnt : std_logic_vector(11 downto 0);
signal sample2_cnt : std_logic_vector(11 downto 0);
signal sample3_cnt : std_logic_vector(11 downto 0);
signal sample4_cnt : std_logic_vector(11 downto 0);
signal sample5_cnt : std_logic_vector(11 downto 0);
signal sample6_cnt : std_logic_vector(11 downto 0);
signal sample7_cnt : std_logic_vector(11 downto 0);
signal counter : std_logic_vector(11 downto 0);
signal valid_reg : std_logic;
signal zero_32 : std_logic_vector(31 downto 0);
signal zero_64 : std_logic_vector(63 downto 0);
signal zero_96 : std_logic_vector(95 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
zero_96 <= (others=>'0');
zero_64 <= (others=>'0');
zero_32 <= (others=>'0');
-- Genereate a counting test pattern
process(clk_in, rst_in)
begin
if rst_in = '1' then
counter <= (others=>'0');
elsif rising_edge(clk_in) then
if val_in = '1' then
counter <= counter + 8;
end if;
end if;
end process;
sample0_cnt <= counter + 0;
sample1_cnt <= counter + 1;
sample2_cnt <= counter + 2;
sample3_cnt <= counter + 3;
sample4_cnt <= counter + 4;
sample5_cnt <= counter + 5;
sample6_cnt <= counter + 6;
sample7_cnt <= counter + 7;
-- select between test pattern or input data
process(clk_in)
begin
if rising_edge(clk_in) then
valid_reg <= val_in;
if test_mode = '0' then
sample0 <= data_in(11 downto 0);
sample1 <= data_in(27 downto 16);
sample2 <= data_in(43 downto 32);
sample3 <= data_in(59 downto 48);
sample4 <= data_in(75 downto 64);
sample5 <= data_in(91 downto 80);
sample6 <= data_in(107 downto 96);
sample7 <= data_in(123 downto 112);
else
sample0 <= sample0_cnt;
sample1 <= sample1_cnt;
sample2 <= sample2_cnt;
sample3 <= sample3_cnt;
sample4 <= sample4_cnt;
sample5 <= sample5_cnt;
sample6 <= sample6_cnt;
sample7 <= sample7_cnt;
end if;
end if;
end process;
-- packing state machine
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
data_out <= (others=>'0');
val_out <= '0';
reg0 <= (others=>'0');
sm_reg <= state0;
else
--default
val_out <= '0';
case sm_reg is
when state0 =>
if valid_reg = '1' then
sm_reg <= state1;
reg0 <= zero_32 & sample7 & sample6 & sample5 &
sample4 & sample3 & sample2 & sample1 & sample0;
end if;
when state1 =>
sm_reg <= state2;
val_out <= '1';
data_out <= sample2(7 downto 0) & sample1 & sample0 & reg0(95 downto 0);
reg0 <= zero_64 & sample7 & sample6 & sample5 &
sample4 & sample3 & sample2(11 downto 8);
when state2 =>
sm_reg <= state3;
val_out <= '1';
data_out <= sample5(3 downto 0) & sample4 & sample3 & sample2 &
sample1 & sample0 & reg0(63 downto 0);
reg0 <= zero_96 & sample7 & sample6 & sample5(11 downto 4);
when state3 =>
sm_reg <= state0;
val_out <= '1';
data_out <= sample7 & sample6 & sample5 & sample4 & sample3 &
sample2 & sample1 & sample0 & reg0(31 downto 0);
when others =>
sm_reg <= state0;
end case;
end if;
end if;
end process;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
mit
|
403e212b9c42ed8b1eda429de4ed4daf
| 0.440179 | 4.095154 | false | false | false | false |
tgingold/ghdl
|
testsuite/synth/cnt01/tb_cnt01.vhdl
| 1 | 1,273 |
entity tb_cnt01 is
end tb_cnt01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cnt01 is
signal clk : std_logic;
signal rst : std_logic;
signal clr : std_logic;
signal en : std_logic;
signal cnt : std_logic_vector (9 downto 0);
begin
dut: entity work.cnt01
port map (clock => clk, reset => rst, clear_count => clr,
enable => en, counter_out => cnt);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
clk <= '0';
clr <= '0';
en <= '0';
rst <= '1';
wait for 1 ns;
assert cnt = "0000000000" severity failure;
rst <= '0';
pulse;
assert cnt = "0000000000" severity failure;
en <= '1';
pulse;
assert cnt = "0000000001" severity failure;
en <= '0';
pulse;
assert cnt = "0000000001" severity failure;
en <= '1';
pulse;
assert cnt = "0000000010" severity failure;
en <= '1';
pulse;
assert cnt = "0000000011" severity failure;
en <= '1';
clr <= '1';
pulse;
assert cnt = "0000000000" severity failure;
en <= '1';
clr <= '0';
pulse;
assert cnt = "0000000001" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
130d899bc64023239f34c8a15f42a9c8
| 0.563236 | 3.536111 | false | false | false | false |
tgingold/ghdl
|
testsuite/gna/issue243/test.vhdl
| 2 | 469 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_pkg IS
SUBTYPE test_t IS std_ulogic_vector(7 DOWNTO 0);
TYPE test_array_t IS ARRAY (natural RANGE <>) OF test_t;
END PACKAGE test_pkg;
LIBRARY work;
USE work.test_pkg.ALL;
ENTITY test IS
PORT (
a : IN test_array_t(0 TO 4) := (OTHERS => (OTHERS => '0'));
b : IN test_array_t(0 TO 4) := ((OTHERS => (OTHERS => '0'))));
END ENTITY test;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
|
gpl-2.0
|
6ead6fd65590d7a43dbc467a4c2f2a17
| 0.652452 | 2.987261 | false | true | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rd_sf.vhd
| 3 | 75,602 |
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_10.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
gpl-3.0
|
13e61ee2ee67438b055fe3a791b00feb
| 0.425624 | 4.844108 | false | false | false | false |
nickg/nvc
|
test/lower/arith1.vhd
| 1 | 801 |
entity arith1 is
end entity;
architecture test of arith1 is
begin
p1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod x = 2;
assert 5 rem x = 2;
assert (-5) rem x = -2;
assert (-5) mod x = 2;
assert x = +x;
assert 0 - x > 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
c847b8fde1d5f932803dccf8dcbafec0
| 0.425718 | 3.513158 | false | false | false | false |
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/convolution_2D/solution1/syn/vhdl/doImgProc.vhd
| 4 | 111,599 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity doImgProc is
generic (
C_S_AXI_CRTL_BUS_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_CRTL_BUS_DATA_WIDTH : INTEGER := 32;
C_S_AXI_KERNEL_BUS_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_KERNEL_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0);
inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0);
outStream_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TKEEP : OUT STD_LOGIC_VECTOR (0 downto 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR (0 downto 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR (1 downto 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
outStream_TID : OUT STD_LOGIC_VECTOR (4 downto 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR (5 downto 0);
s_axi_CRTL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CRTL_BUS_WVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CRTL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_CRTL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CRTL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CRTL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CRTL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_RREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CRTL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CRTL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_CRTL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CRTL_BUS_BREADY : IN STD_LOGIC;
s_axi_CRTL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC;
s_axi_KERNEL_BUS_AWVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_KERNEL_BUS_WVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_WREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0);
s_axi_KERNEL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_KERNEL_BUS_ARVALID : IN STD_LOGIC;
s_axi_KERNEL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_KERNEL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_KERNEL_BUS_RVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_RREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_KERNEL_BUS_DATA_WIDTH-1 downto 0);
s_axi_KERNEL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_KERNEL_BUS_BVALID : OUT STD_LOGIC;
s_axi_KERNEL_BUS_BREADY : IN STD_LOGIC;
s_axi_KERNEL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0) );
end;
architecture behav of doImgProc is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"doImgProc,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.340000,HLS_SYN_LAT=2359816,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=9,HLS_SYN_FF=1034,HLS_SYN_LUT=1363}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_ST_pp0_stg0_fsm_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_ST_pp0_stg1_fsm_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_ST_pp0_stg2_fsm_3 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
constant ap_ST_pp0_stg3_fsm_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
constant ap_ST_pp0_stg4_fsm_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
constant ap_ST_pp0_stg5_fsm_6 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
constant ap_ST_pp0_stg6_fsm_7 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
constant ap_ST_pp0_stg7_fsm_8 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
constant ap_ST_pp0_stg8_fsm_9 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
constant ap_ST_st17_fsm_10 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv19_1 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000001";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv64_2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_const_lv64_3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000011";
constant ap_const_lv64_4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_const_lv64_5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000101";
constant ap_const_lv64_6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000110";
constant ap_const_lv64_7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000111";
constant ap_const_lv64_8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv19_40001 : STD_LOGIC_VECTOR (18 downto 0) := "1000000000000000001";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_1FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000111111111";
constant ap_const_lv19_201 : STD_LOGIC_VECTOR (18 downto 0) := "0000000001000000001";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv10_201 : STD_LOGIC_VECTOR (9 downto 0) := "1000000001";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_28 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal kernel_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal kernel_ce0 : STD_LOGIC;
signal kernel_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal operation : STD_LOGIC_VECTOR (31 downto 0);
signal inStream_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_pp0_stg1_fsm_2 : STD_LOGIC;
signal ap_sig_65 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal exitcond1_reg_1305 : STD_LOGIC_VECTOR (0 downto 0);
signal outStream_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_pp0_stg5_fsm_6 : STD_LOGIC;
signal ap_sig_82 : BOOLEAN;
signal tmp_12_reg_1347 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st17_fsm_10 : STD_LOGIC;
signal ap_sig_95 : BOOLEAN;
signal exitcond_fu_1224_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_id_V_reg_406 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_user_V_reg_419 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_strb_V_reg_432 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_keep_V_reg_445 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_dest_V_reg_458 : STD_LOGIC_VECTOR (5 downto 0);
signal col_assign_reg_471 : STD_LOGIC_VECTOR (31 downto 0);
signal idxRow_reg_482 : STD_LOGIC_VECTOR (31 downto 0);
signal pixConvolved_reg_493 : STD_LOGIC_VECTOR (31 downto 0);
signal countWait_reg_505 : STD_LOGIC_VECTOR (18 downto 0);
signal reg_527 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_188 : BOOLEAN;
signal ap_sig_cseq_ST_pp0_stg4_fsm_5 : STD_LOGIC;
signal ap_sig_198 : BOOLEAN;
signal ap_sig_cseq_ST_pp0_stg7_fsm_8 : STD_LOGIC;
signal ap_sig_208 : BOOLEAN;
signal reg_531 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_pp0_stg2_fsm_3 : STD_LOGIC;
signal ap_sig_219 : BOOLEAN;
signal ap_sig_ioackin_outStream_TREADY : STD_LOGIC;
signal ap_sig_cseq_ST_pp0_stg8_fsm_9 : STD_LOGIC;
signal ap_sig_237 : BOOLEAN;
signal lineBuff_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_535 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_pp0_stg3_fsm_4 : STD_LOGIC;
signal ap_sig_249 : BOOLEAN;
signal lineBuff_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_540 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_pp0_stg6_fsm_7 : STD_LOGIC;
signal ap_sig_260 : BOOLEAN;
signal ap_sig_cseq_ST_pp0_stg0_fsm_1 : STD_LOGIC;
signal ap_sig_270 : BOOLEAN;
signal sel_tmp2_fu_544_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_1290 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_fu_550_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_reg_1295 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_1300 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_fu_562_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_568_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_reg_1309 : STD_LOGIC_VECTOR (63 downto 0);
signal lineBuff_val_1_addr_reg_1314 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_2_addr_reg_1319 : STD_LOGIC_VECTOR (8 downto 0);
signal or_cond_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_1324 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_612_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_reg_1332 : STD_LOGIC_VECTOR (0 downto 0);
signal idxCol_1_fu_630_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal idxCol_1_reg_1337 : STD_LOGIC_VECTOR (31 downto 0);
signal idxRow_1_fu_638_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal idxRow_1_reg_1342 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_646_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_fu_652_p2 : STD_LOGIC_VECTOR (18 downto 0);
signal phitmp_reg_1351 : STD_LOGIC_VECTOR (18 downto 0);
signal tmp_keep_V_1_reg_1356 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_strb_V_1_reg_1362 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_1_reg_1368 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_id_V_1_reg_1374 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_dest_V_1_reg_1380 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 : STD_LOGIC_VECTOR (5 downto 0);
signal col_assign_1_0_2_fu_703_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal col_assign_1_0_2_reg_1396 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp3_fu_716_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_reg_1421 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_fu_728_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_reg_1426 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp9_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp9_reg_1431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 : STD_LOGIC_VECTOR (0 downto 0);
signal pixConvolved_2_fu_752_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal pixConvolved_2_reg_1436 : STD_LOGIC_VECTOR (31 downto 0);
signal lineBuff_val_0_load_1_reg_1441 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_1_load_1_reg_1451 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_1_load_2_reg_1456 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_2_load_1_reg_1466 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_2_load_2_reg_1471 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_0_fu_773_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_0_0_reg_1481 : STD_LOGIC_VECTOR (15 downto 0);
signal lineBuff_val_1_load_3_reg_1486 : STD_LOGIC_VECTOR (7 downto 0);
signal lineBuff_val_2_load_3_reg_1491 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_fu_779_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_reg_1496 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp4_fu_796_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp4_reg_1504 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_15_fu_801_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_reg_1509 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_2_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_0_2_reg_1517 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_16_fu_819_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_16_reg_1522 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_0_fu_830_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_1_0_reg_1530 : STD_LOGIC_VECTOR (15 downto 0);
signal valInWindow_0_minVal_1_0_2_i_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_0_2_i_reg_1535 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_reg_1541 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_0_2_i_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_0_2_i_reg_1549 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_1_1_reg_1555 : STD_LOGIC_VECTOR (15 downto 0);
signal valInWindow_0_minVal_1_1_i_fu_901_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_1_i_reg_1560 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_fu_907_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_reg_1566 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_1_i_fu_915_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_1_i_reg_1574 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_2_fu_928_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_1_2_reg_1580 : STD_LOGIC_VECTOR (15 downto 0);
signal valInWindow_0_minVal_1_1_1_i_fu_938_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_1_1_i_reg_1585 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_fu_944_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_reg_1591 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_1_1_i_fu_952_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_1_1_i_reg_1599 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_0_fu_965_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_2_0_reg_1605 : STD_LOGIC_VECTOR (15 downto 0);
signal valInWindow_0_minVal_1_1_2_i_fu_975_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_1_2_i_reg_1610 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_20_fu_981_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_20_reg_1616 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_1_2_i_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_1_2_i_reg_1624 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp1_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp1_reg_1630 : STD_LOGIC_VECTOR (15 downto 0);
signal valInWindow_0_minVal_1_2_i_fu_1017_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_2_i_reg_1635 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_21_fu_1023_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_21_reg_1641 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_2_i_fu_1031_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_2_i_reg_1649 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_2_fu_1044_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_2_2_reg_1655 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_fu_1054_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_reg_1660 : STD_LOGIC_VECTOR (15 downto 0);
signal valInWindow_0_minVal_1_2_1_i_fu_1063_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_2_1_i_reg_1665 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_22_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_22_reg_1671 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_maxVal_1_2_1_i_reg_1679 : STD_LOGIC_VECTOR (7 downto 0);
signal valOutput_fu_1097_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal valOutput_reg_1685 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_6_reg_1690 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_1695 : STD_LOGIC_VECTOR (12 downto 0);
signal sel_tmp10_fu_1147_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp10_reg_1700 : STD_LOGIC_VECTOR (7 downto 0);
signal countWait_2_fu_1230_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal lineBuff_val_0_address0 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_0_ce0 : STD_LOGIC;
signal lineBuff_val_0_we0 : STD_LOGIC;
signal lineBuff_val_0_address1 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_0_ce1 : STD_LOGIC;
signal lineBuff_val_1_address0 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_1_ce0 : STD_LOGIC;
signal lineBuff_val_1_we0 : STD_LOGIC;
signal lineBuff_val_1_address1 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_1_ce1 : STD_LOGIC;
signal lineBuff_val_2_address0 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_2_ce0 : STD_LOGIC;
signal lineBuff_val_2_we0 : STD_LOGIC;
signal lineBuff_val_2_address1 : STD_LOGIC_VECTOR (8 downto 0);
signal lineBuff_val_2_ce1 : STD_LOGIC;
signal col_assign_phi_fu_475_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal idxRow_phi_fu_486_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal pixConvolved_phi_fu_497_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal countWait_phi_fu_509_p4 : STD_LOGIC_VECTOR (18 downto 0);
signal countWait_1_reg_516 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_7_fu_683_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_25_0_1_fu_696_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_25_0_2_fu_759_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_data_V_fu_1217_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ioackin_outStream_TREADY : STD_LOGIC := '0';
signal tmp_3_fu_574_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_4_fu_590_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal icmp_fu_584_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp4_fu_600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal idxCol_fu_618_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal idxRow_2_fu_624_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal pixConvolved_3_fu_690_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp1_fu_709_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp4_fu_720_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp7_fu_732_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal pixConvolved_1_fu_744_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal window_val_0_0_fu_773_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_0_fu_773_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_fu_790_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_fu_790_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_1_fu_790_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_0_2_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_0_2_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_0_fu_830_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_0_fu_830_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_0_1_i_fu_836_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal valInWindow_0_minVal_1_0_1_i_fu_840_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_0_2_i_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_0_1_i_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal valInWindow_0_maxVal_1_0_1_i_fu_866_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_11_0_2_i_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal window_val_1_1_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_1_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_1_i_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_i_fu_911_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal window_val_1_2_fu_928_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_1_2_fu_928_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_1_1_i_fu_934_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_1_i_fu_948_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal window_val_2_0_fu_965_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_0_fu_965_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_1_2_i_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_1_2_i_fu_985_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal window_val_2_1_fu_1002_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_fu_1002_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_1_fu_1002_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_2_i_fu_1013_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_2_i_fu_1027_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal window_val_2_2_fu_1044_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal window_val_2_2_fu_1044_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp2_fu_1050_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_2_1_i_fu_1059_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_2_1_i_fu_1073_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_1083_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp6_fu_1087_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp7_fu_1092_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_2_2_i_fu_1120_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_2_2_i_fu_1130_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal valInWindow_0_minVal_1_2_2_i_fu_1124_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp_fu_1140_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_tr_fu_1154_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal p_neg_fu_1157_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_8_fu_1163_p4 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_cast_fu_1173_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_1_fu_1177_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_2_fu_1180_p2 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_10_cast_fu_1186_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal valOutput_1_fu_1190_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_13_fu_1201_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_1197_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_s_fu_1209_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
signal window_val_0_0_fu_773_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_0_1_fu_790_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_0_2_fu_813_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_1_0_fu_830_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_1_1_fu_891_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_1_2_fu_928_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_2_0_fu_965_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_2_1_fu_1002_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal window_val_2_2_fu_1044_p10 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_sig_1220 : BOOLEAN;
component doImgProc_lineBuff_val_0 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (8 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (8 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component doImgProc_CRTL_BUS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
operation : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component doImgProc_KERNEL_BUS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
kernel_address0 : IN STD_LOGIC_VECTOR (3 downto 0);
kernel_ce0 : IN STD_LOGIC;
kernel_q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
doImgProc_CRTL_BUS_s_axi_U : component doImgProc_CRTL_BUS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CRTL_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CRTL_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_CRTL_BUS_AWVALID,
AWREADY => s_axi_CRTL_BUS_AWREADY,
AWADDR => s_axi_CRTL_BUS_AWADDR,
WVALID => s_axi_CRTL_BUS_WVALID,
WREADY => s_axi_CRTL_BUS_WREADY,
WDATA => s_axi_CRTL_BUS_WDATA,
WSTRB => s_axi_CRTL_BUS_WSTRB,
ARVALID => s_axi_CRTL_BUS_ARVALID,
ARREADY => s_axi_CRTL_BUS_ARREADY,
ARADDR => s_axi_CRTL_BUS_ARADDR,
RVALID => s_axi_CRTL_BUS_RVALID,
RREADY => s_axi_CRTL_BUS_RREADY,
RDATA => s_axi_CRTL_BUS_RDATA,
RRESP => s_axi_CRTL_BUS_RRESP,
BVALID => s_axi_CRTL_BUS_BVALID,
BREADY => s_axi_CRTL_BUS_BREADY,
BRESP => s_axi_CRTL_BUS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
operation => operation);
doImgProc_KERNEL_BUS_s_axi_U : component doImgProc_KERNEL_BUS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_KERNEL_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_KERNEL_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_KERNEL_BUS_AWVALID,
AWREADY => s_axi_KERNEL_BUS_AWREADY,
AWADDR => s_axi_KERNEL_BUS_AWADDR,
WVALID => s_axi_KERNEL_BUS_WVALID,
WREADY => s_axi_KERNEL_BUS_WREADY,
WDATA => s_axi_KERNEL_BUS_WDATA,
WSTRB => s_axi_KERNEL_BUS_WSTRB,
ARVALID => s_axi_KERNEL_BUS_ARVALID,
ARREADY => s_axi_KERNEL_BUS_ARREADY,
ARADDR => s_axi_KERNEL_BUS_ARADDR,
RVALID => s_axi_KERNEL_BUS_RVALID,
RREADY => s_axi_KERNEL_BUS_RREADY,
RDATA => s_axi_KERNEL_BUS_RDATA,
RRESP => s_axi_KERNEL_BUS_RRESP,
BVALID => s_axi_KERNEL_BUS_BVALID,
BREADY => s_axi_KERNEL_BUS_BREADY,
BRESP => s_axi_KERNEL_BUS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
kernel_address0 => kernel_address0,
kernel_ce0 => kernel_ce0,
kernel_q0 => kernel_q0);
lineBuff_val_0_U : component doImgProc_lineBuff_val_0
generic map (
DataWidth => 8,
AddressRange => 512,
AddressWidth => 9)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => lineBuff_val_0_address0,
ce0 => lineBuff_val_0_ce0,
we0 => lineBuff_val_0_we0,
d0 => lineBuff_val_1_q0,
q0 => lineBuff_val_0_q0,
address1 => lineBuff_val_0_address1,
ce1 => lineBuff_val_0_ce1,
q1 => lineBuff_val_0_q1);
lineBuff_val_1_U : component doImgProc_lineBuff_val_0
generic map (
DataWidth => 8,
AddressRange => 512,
AddressWidth => 9)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => lineBuff_val_1_address0,
ce0 => lineBuff_val_1_ce0,
we0 => lineBuff_val_1_we0,
d0 => lineBuff_val_2_q0,
q0 => lineBuff_val_1_q0,
address1 => lineBuff_val_1_address1,
ce1 => lineBuff_val_1_ce1,
q1 => lineBuff_val_1_q1);
lineBuff_val_2_U : component doImgProc_lineBuff_val_0
generic map (
DataWidth => 8,
AddressRange => 512,
AddressWidth => 9)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => lineBuff_val_2_address0,
ce0 => lineBuff_val_2_ce0,
we0 => lineBuff_val_2_we0,
d0 => inStream_TDATA,
q0 => lineBuff_val_2_q0,
address1 => lineBuff_val_2_address1,
ce1 => lineBuff_val_2_ce1,
q1 => lineBuff_val_2_q1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_outStream_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0;
else
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))))) then
ap_reg_ioackin_outStream_TREADY <= ap_const_logic_0;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_1 = outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_1 = outStream_TREADY)))) then
ap_reg_ioackin_outStream_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and not((exitcond1_reg_1305 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
col_assign_reg_471_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
col_assign_reg_471 <= idxCol_1_reg_1337;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
col_assign_reg_471 <= ap_const_lv32_0;
end if;
end if;
end process;
countWait_1_reg_516_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)))) then
countWait_1_reg_516 <= ap_const_lv10_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
countWait_1_reg_516 <= countWait_2_fu_1230_p2;
end if;
end if;
end process;
countWait_reg_505_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
countWait_reg_505 <= phitmp_reg_1351;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
countWait_reg_505 <= ap_const_lv19_1;
end if;
end if;
end process;
idxRow_reg_482_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
idxRow_reg_482 <= idxRow_1_reg_1342;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
idxRow_reg_482 <= ap_const_lv32_0;
end if;
end if;
end process;
pixConvolved_reg_493_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
pixConvolved_reg_493 <= pixConvolved_2_reg_1436;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
pixConvolved_reg_493 <= ap_const_lv32_0;
end if;
end if;
end process;
reg_535_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_1220) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then
reg_535 <= lineBuff_val_0_q1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then
reg_535 <= lineBuff_val_0_q0;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then
ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1 <= exitcond1_reg_1305;
ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1 <= tmp_12_reg_1347;
exitcond1_reg_1305 <= exitcond1_fu_562_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1 <= sel_tmp3_reg_1421;
ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1 <= sel_tmp6_reg_1426;
ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1 <= sel_tmp9_reg_1431;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then
ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1 <= tmp_dest_V_1_reg_1380;
ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1 <= tmp_id_V_1_reg_1374;
ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1 <= tmp_keep_V_1_reg_1356;
ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1 <= tmp_strb_V_1_reg_1362;
ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1 <= tmp_user_V_1_reg_1368;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then
col_assign_1_0_2_reg_1396 <= col_assign_1_0_2_fu_703_p2;
sel_tmp3_reg_1421 <= sel_tmp3_fu_716_p2;
sel_tmp6_reg_1426 <= sel_tmp6_fu_728_p2;
sel_tmp9_reg_1431 <= sel_tmp9_fu_740_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then
idxCol_1_reg_1337 <= idxCol_1_fu_630_p3;
idxRow_1_reg_1342 <= idxRow_1_fu_638_p3;
phitmp_reg_1351 <= phitmp_fu_652_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4))) then
lineBuff_val_0_load_1_reg_1441 <= lineBuff_val_0_q1;
lineBuff_val_1_load_1_reg_1451 <= lineBuff_val_1_q0;
lineBuff_val_1_load_2_reg_1456 <= lineBuff_val_1_q1;
lineBuff_val_2_load_1_reg_1466 <= lineBuff_val_2_q0;
lineBuff_val_2_load_2_reg_1471 <= lineBuff_val_2_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = exitcond1_fu_562_p2))) then
lineBuff_val_1_addr_reg_1314 <= tmp_s_fu_568_p1(9 - 1 downto 0);
lineBuff_val_2_addr_reg_1319 <= tmp_s_fu_568_p1(9 - 1 downto 0);
or_cond_reg_1324 <= or_cond_fu_606_p2;
tmp_11_reg_1332 <= tmp_11_fu_612_p2;
tmp_12_reg_1347 <= tmp_12_fu_646_p2;
tmp_s_reg_1309(31 downto 0) <= tmp_s_fu_568_p1(31 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then
lineBuff_val_1_load_3_reg_1486 <= lineBuff_val_1_q1;
lineBuff_val_2_load_3_reg_1491 <= lineBuff_val_2_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3))) then
pixConvolved_2_reg_1436 <= pixConvolved_2_fu_752_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)))) then
reg_527 <= kernel_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)))) then
reg_531 <= kernel_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then
reg_540 <= kernel_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then
sel_tmp10_reg_1700 <= sel_tmp10_fu_1147_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
sel_tmp2_reg_1290 <= sel_tmp2_fu_544_p2;
sel_tmp5_reg_1295 <= sel_tmp5_fu_550_p2;
sel_tmp8_reg_1300 <= sel_tmp8_fu_556_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
tmp1_reg_1630 <= tmp1_fu_1008_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then
tmp3_reg_1660 <= tmp3_fu_1054_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = sel_tmp9_reg_1431)))) then
tmp4_reg_1504 <= tmp4_fu_796_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then
tmp_14_reg_1496 <= tmp_14_fu_779_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then
tmp_15_reg_1509 <= tmp_15_fu_801_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then
tmp_16_reg_1522 <= tmp_16_fu_819_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then
tmp_17_reg_1541 <= tmp_17_fu_858_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then
tmp_18_reg_1566 <= tmp_18_fu_907_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431))) then
tmp_19_reg_1591 <= tmp_19_fu_944_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
tmp_20_reg_1616 <= tmp_20_fu_981_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
tmp_21_reg_1641 <= tmp_21_fu_1023_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1))) then
tmp_22_reg_1671 <= tmp_22_fu_1069_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1)))) then
tmp_6_reg_1690 <= valOutput_fu_1097_p2(15 downto 15);
tmp_9_reg_1695 <= valOutput_fu_1097_p2(15 downto 3);
valOutput_reg_1685 <= valOutput_fu_1097_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)))) then
tmp_dest_V_1_reg_1380 <= inStream_TDEST;
tmp_id_V_1_reg_1374 <= inStream_TID;
tmp_keep_V_1_reg_1356 <= inStream_TKEEP;
tmp_strb_V_1_reg_1362 <= inStream_TSTRB;
tmp_user_V_1_reg_1368 <= inStream_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
tmp_dest_V_reg_458 <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1;
tmp_id_V_reg_406 <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1;
tmp_keep_V_reg_445 <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1;
tmp_strb_V_reg_432 <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1;
tmp_user_V_reg_419 <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then
valInWindow_0_maxVal_1_0_2_i_reg_1549 <= valInWindow_0_maxVal_1_0_2_i_fu_877_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then
valInWindow_0_maxVal_1_1_1_i_reg_1599 <= valInWindow_0_maxVal_1_1_1_i_fu_952_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
valInWindow_0_maxVal_1_1_2_i_reg_1624 <= valInWindow_0_maxVal_1_1_2_i_fu_989_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)))) then
valInWindow_0_maxVal_1_1_i_reg_1574 <= valInWindow_0_maxVal_1_1_i_fu_915_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1)))) then
valInWindow_0_maxVal_1_2_1_i_reg_1679 <= valInWindow_0_maxVal_1_2_1_i_fu_1077_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and (ap_const_lv1_0 = sel_tmp6_reg_1426) and not((ap_const_lv1_0 = sel_tmp3_reg_1421)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
valInWindow_0_maxVal_1_2_i_reg_1649 <= valInWindow_0_maxVal_1_2_i_fu_1031_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then
valInWindow_0_minVal_1_0_2_i_reg_1535 <= valInWindow_0_minVal_1_0_2_i_fu_851_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then
valInWindow_0_minVal_1_1_1_i_reg_1585 <= valInWindow_0_minVal_1_1_1_i_fu_938_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
valInWindow_0_minVal_1_1_2_i_reg_1610 <= valInWindow_0_minVal_1_1_2_i_fu_975_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)))) then
valInWindow_0_minVal_1_1_i_reg_1560 <= valInWindow_0_minVal_1_1_i_fu_901_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1) and (ap_const_lv1_0 = ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1) and not((ap_const_lv1_0 = ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1)))) then
valInWindow_0_minVal_1_2_1_i_reg_1665 <= valInWindow_0_minVal_1_2_1_i_fu_1063_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = sel_tmp9_reg_1431) and not((ap_const_lv1_0 = sel_tmp6_reg_1426)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
valInWindow_0_minVal_1_2_i_reg_1635 <= valInWindow_0_minVal_1_2_i_fu_1017_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5))) then
window_val_0_0_reg_1481 <= window_val_0_0_fu_773_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7))) then
window_val_0_2_reg_1517 <= window_val_0_2_fu_813_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8))) then
window_val_1_0_reg_1530 <= window_val_1_0_fu_830_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9))) then
window_val_1_1_reg_1555 <= window_val_1_1_fu_891_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
window_val_1_2_reg_1580 <= window_val_1_2_fu_928_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188)) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
window_val_2_0_reg_1605 <= window_val_2_0_fu_965_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
window_val_2_2_reg_1655 <= window_val_2_2_fu_1044_p2;
end if;
end if;
end process;
tmp_s_reg_1309(63 downto 32) <= "00000000000000000000000000000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, exitcond_fu_1224_p2, ap_sig_188, ap_sig_ioackin_outStream_TREADY, exitcond1_fu_562_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_pp0_stg0_fsm_1 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_const_lv1_0 = exitcond1_fu_562_p2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2;
else
ap_NS_fsm <= ap_ST_st17_fsm_10;
end if;
when ap_ST_pp0_stg1_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_2;
end if;
when ap_ST_pp0_stg2_fsm_3 =>
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_4;
when ap_ST_pp0_stg3_fsm_4 =>
ap_NS_fsm <= ap_ST_pp0_stg4_fsm_5;
when ap_ST_pp0_stg4_fsm_5 =>
ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6;
when ap_ST_pp0_stg5_fsm_6 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))))) then
ap_NS_fsm <= ap_ST_pp0_stg6_fsm_7;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_NS_fsm <= ap_ST_st17_fsm_10;
else
ap_NS_fsm <= ap_ST_pp0_stg5_fsm_6;
end if;
when ap_ST_pp0_stg6_fsm_7 =>
ap_NS_fsm <= ap_ST_pp0_stg7_fsm_8;
when ap_ST_pp0_stg7_fsm_8 =>
ap_NS_fsm <= ap_ST_pp0_stg8_fsm_9;
when ap_ST_pp0_stg8_fsm_9 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1;
when ap_ST_st17_fsm_10 =>
if ((not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((ap_const_lv1_0 = exitcond_fu_1224_p2) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))))) then
ap_NS_fsm <= ap_ST_st17_fsm_10;
else
ap_NS_fsm <= ap_ST_st17_fsm_10;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXX";
end case;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_sig_ioackin_outStream_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and not(((ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY))) and not((ap_const_lv1_0 = exitcond_fu_1224_p2)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_1220_assign_proc : process(ap_reg_ppiten_pp0_it0, exitcond1_reg_1305)
begin
ap_sig_1220 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0));
end process;
ap_sig_188_assign_proc : process(inStream_TVALID, exitcond1_reg_1305)
begin
ap_sig_188 <= ((exitcond1_reg_1305 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0));
end process;
ap_sig_198_assign_proc : process(ap_CS_fsm)
begin
ap_sig_198 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
ap_sig_208_assign_proc : process(ap_CS_fsm)
begin
ap_sig_208 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
ap_sig_219_assign_proc : process(ap_CS_fsm)
begin
ap_sig_219 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
ap_sig_237_assign_proc : process(ap_CS_fsm)
begin
ap_sig_237 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
ap_sig_249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_249 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
ap_sig_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_260 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
ap_sig_270_assign_proc : process(ap_CS_fsm)
begin
ap_sig_270 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
ap_sig_28_assign_proc : process(ap_CS_fsm)
begin
ap_sig_28 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_65_assign_proc : process(ap_CS_fsm)
begin
ap_sig_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
ap_sig_82_assign_proc : process(ap_CS_fsm)
begin
ap_sig_82 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
ap_sig_95_assign_proc : process(ap_CS_fsm)
begin
ap_sig_95 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
ap_sig_cseq_ST_pp0_stg0_fsm_1_assign_proc : process(ap_sig_270)
begin
if (ap_sig_270) then
ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg1_fsm_2_assign_proc : process(ap_sig_65)
begin
if (ap_sig_65) then
ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg1_fsm_2 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg2_fsm_3_assign_proc : process(ap_sig_219)
begin
if (ap_sig_219) then
ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg2_fsm_3 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg3_fsm_4_assign_proc : process(ap_sig_249)
begin
if (ap_sig_249) then
ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg3_fsm_4 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg4_fsm_5_assign_proc : process(ap_sig_198)
begin
if (ap_sig_198) then
ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg4_fsm_5 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg5_fsm_6_assign_proc : process(ap_sig_82)
begin
if (ap_sig_82) then
ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg5_fsm_6 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg6_fsm_7_assign_proc : process(ap_sig_260)
begin
if (ap_sig_260) then
ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg6_fsm_7 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg7_fsm_8_assign_proc : process(ap_sig_208)
begin
if (ap_sig_208) then
ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg7_fsm_8 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_pp0_stg8_fsm_9_assign_proc : process(ap_sig_237)
begin
if (ap_sig_237) then
ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg8_fsm_9 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st17_fsm_10_assign_proc : process(ap_sig_95)
begin
if (ap_sig_95) then
ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_10 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_28)
begin
if (ap_sig_28) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_outStream_TREADY_assign_proc : process(outStream_TREADY, ap_reg_ioackin_outStream_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) then
ap_sig_ioackin_outStream_TREADY <= outStream_TREADY;
else
ap_sig_ioackin_outStream_TREADY <= ap_const_logic_1;
end if;
end process;
col_assign_1_0_2_fu_703_p2 <= std_logic_vector(unsigned(ap_const_lv32_2) + unsigned(pixConvolved_phi_fu_497_p4));
col_assign_phi_fu_475_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, col_assign_reg_471, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxCol_1_reg_1337)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
col_assign_phi_fu_475_p4 <= idxCol_1_reg_1337;
else
col_assign_phi_fu_475_p4 <= col_assign_reg_471;
end if;
end process;
countWait_2_fu_1230_p2 <= std_logic_vector(unsigned(countWait_1_reg_516) + unsigned(ap_const_lv10_1));
countWait_phi_fu_509_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, countWait_reg_505, ap_sig_cseq_ST_pp0_stg0_fsm_1, phitmp_reg_1351)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
countWait_phi_fu_509_p4 <= phitmp_reg_1351;
else
countWait_phi_fu_509_p4 <= countWait_reg_505;
end if;
end process;
exitcond1_fu_562_p2 <= "1" when (countWait_phi_fu_509_p4 = ap_const_lv19_40001) else "0";
exitcond_fu_1224_p2 <= "1" when (countWait_1_reg_516 = ap_const_lv10_201) else "0";
icmp4_fu_600_p2 <= "1" when (signed(tmp_4_fu_590_p4) > signed(ap_const_lv31_0)) else "0";
icmp_fu_584_p2 <= "1" when (signed(tmp_3_fu_574_p4) > signed(ap_const_lv31_0)) else "0";
idxCol_1_fu_630_p3 <=
idxCol_fu_618_p2 when (tmp_11_fu_612_p2(0) = '1') else
ap_const_lv32_0;
idxCol_fu_618_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(col_assign_phi_fu_475_p4));
idxRow_1_fu_638_p3 <=
idxRow_phi_fu_486_p4 when (tmp_11_fu_612_p2(0) = '1') else
idxRow_2_fu_624_p2;
idxRow_2_fu_624_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(idxRow_phi_fu_486_p4));
idxRow_phi_fu_486_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, exitcond1_reg_1305, idxRow_reg_482, ap_sig_cseq_ST_pp0_stg0_fsm_1, idxRow_1_reg_1342)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (exitcond1_reg_1305 = ap_const_lv1_0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1))) then
idxRow_phi_fu_486_p4 <= idxRow_1_reg_1342;
else
idxRow_phi_fu_486_p4 <= idxRow_reg_482;
end if;
end process;
inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0))) then
inStream_TDATA_blk_n <= inStream_TVALID;
else
inStream_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then
inStream_TREADY <= ap_const_logic_1;
else
inStream_TREADY <= ap_const_logic_0;
end if;
end process;
kernel_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) then
kernel_address0 <= ap_const_lv64_8(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) then
kernel_address0 <= ap_const_lv64_7(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) then
kernel_address0 <= ap_const_lv64_6(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6)) then
kernel_address0 <= ap_const_lv64_5(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) then
kernel_address0 <= ap_const_lv64_4(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then
kernel_address0 <= ap_const_lv64_3(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
kernel_address0 <= ap_const_lv64_2(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then
kernel_address0 <= ap_const_lv64_1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then
kernel_address0 <= ap_const_lv64_0(4 - 1 downto 0);
else
kernel_address0 <= "XXXX";
end if;
else
kernel_address0 <= "XXXX";
end if;
end process;
kernel_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_188, ap_sig_cseq_ST_pp0_stg4_fsm_5, ap_sig_cseq_ST_pp0_stg7_fsm_8, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_ioackin_outStream_TREADY, ap_sig_cseq_ST_pp0_stg8_fsm_9, ap_sig_cseq_ST_pp0_stg3_fsm_4, ap_sig_cseq_ST_pp0_stg6_fsm_7, ap_sig_cseq_ST_pp0_stg0_fsm_1)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg4_fsm_5)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg7_fsm_8)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_sig_ioackin_outStream_TREADY)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg8_fsm_9)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg6_fsm_7)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then
kernel_ce0 <= ap_const_logic_1;
else
kernel_ce0 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_0_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, tmp_s_reg_1309, tmp_7_fu_683_p1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then
lineBuff_val_0_address0 <= tmp_s_reg_1309(9 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
lineBuff_val_0_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0);
else
lineBuff_val_0_address0 <= "XXXXXXXXX";
end if;
else
lineBuff_val_0_address0 <= "XXXXXXXXX";
end if;
end process;
lineBuff_val_0_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then
lineBuff_val_0_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
lineBuff_val_0_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0);
else
lineBuff_val_0_address1 <= "XXXXXXXXX";
end if;
else
lineBuff_val_0_address1 <= "XXXXXXXXX";
end if;
end process;
lineBuff_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)))) then
lineBuff_val_0_ce0 <= ap_const_logic_1;
else
lineBuff_val_0_ce0 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_0_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then
lineBuff_val_0_ce1 <= ap_const_logic_1;
else
lineBuff_val_0_ce1 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_0_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then
lineBuff_val_0_we0 <= ap_const_logic_1;
else
lineBuff_val_0_we0 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_1_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_1_addr_reg_1314, tmp_7_fu_683_p1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then
lineBuff_val_1_address0 <= lineBuff_val_1_addr_reg_1314;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
lineBuff_val_1_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then
lineBuff_val_1_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0);
else
lineBuff_val_1_address0 <= "XXXXXXXXX";
end if;
else
lineBuff_val_1_address0 <= "XXXXXXXXX";
end if;
end process;
lineBuff_val_1_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then
lineBuff_val_1_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
lineBuff_val_1_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0);
else
lineBuff_val_1_address1 <= "XXXXXXXXX";
end if;
else
lineBuff_val_1_address1 <= "XXXXXXXXX";
end if;
end process;
lineBuff_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then
lineBuff_val_1_ce0 <= ap_const_logic_1;
else
lineBuff_val_1_ce0 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_1_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then
lineBuff_val_1_ce1 <= ap_const_logic_1;
else
lineBuff_val_1_ce1 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_1_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then
lineBuff_val_1_we0 <= ap_const_logic_1;
else
lineBuff_val_1_we0 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_2_address0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1, tmp_s_fu_568_p1, lineBuff_val_2_addr_reg_1319, tmp_7_fu_683_p1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2)) then
lineBuff_val_2_address0 <= lineBuff_val_2_addr_reg_1319;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
lineBuff_val_2_address0 <= tmp_7_fu_683_p1(9 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then
lineBuff_val_2_address0 <= tmp_s_fu_568_p1(9 - 1 downto 0);
else
lineBuff_val_2_address0 <= "XXXXXXXXX";
end if;
else
lineBuff_val_2_address0 <= "XXXXXXXXX";
end if;
end process;
lineBuff_val_2_address1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4, tmp_25_0_1_fu_696_p1, tmp_25_0_2_fu_759_p1)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)) then
lineBuff_val_2_address1 <= tmp_25_0_2_fu_759_p1(9 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) then
lineBuff_val_2_address1 <= tmp_25_0_1_fu_696_p1(9 - 1 downto 0);
else
lineBuff_val_2_address1 <= "XXXXXXXXX";
end if;
else
lineBuff_val_2_address1 <= "XXXXXXXXX";
end if;
end process;
lineBuff_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, ap_sig_188, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg0_fsm_1)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)))) then
lineBuff_val_2_ce0 <= ap_const_logic_1;
else
lineBuff_val_2_ce0 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_2_ce1_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_sig_cseq_ST_pp0_stg3_fsm_4)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg3_fsm_4)))) then
lineBuff_val_2_ce1 <= ap_const_logic_1;
else
lineBuff_val_2_ce1 <= ap_const_logic_0;
end if;
end process;
lineBuff_val_2_we0_assign_proc : process(ap_sig_cseq_ST_pp0_stg1_fsm_2, ap_reg_ppiten_pp0_it0, exitcond1_reg_1305, ap_sig_188)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg1_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_reg_1305 = ap_const_lv1_0) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and ap_sig_188))))) then
lineBuff_val_2_we0 <= ap_const_logic_1;
else
lineBuff_val_2_we0 <= ap_const_logic_0;
end if;
end process;
or_cond_fu_606_p2 <= (icmp_fu_584_p2 and icmp4_fu_600_p2);
outStream_TDATA_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_data_V_fu_1217_p3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TDATA <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TDATA <= tmp_data_V_fu_1217_p3;
else
outStream_TDATA <= "XXXXXXXX";
end if;
end process;
outStream_TDATA_blk_n_assign_proc : process(outStream_TREADY, ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2)))) then
outStream_TDATA_blk_n <= outStream_TREADY;
else
outStream_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
outStream_TDEST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_dest_V_reg_458, ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TDEST <= tmp_dest_V_reg_458;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TDEST <= ap_reg_ppstg_tmp_dest_V_1_reg_1380_pp0_iter1;
else
outStream_TDEST <= "XXXXXX";
end if;
end process;
outStream_TID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_id_V_reg_406, ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TID <= tmp_id_V_reg_406;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TID <= ap_reg_ppstg_tmp_id_V_1_reg_1374_pp0_iter1;
else
outStream_TID <= "XXXXX";
end if;
end process;
outStream_TKEEP_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_keep_V_reg_445, ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TKEEP <= tmp_keep_V_reg_445;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TKEEP <= ap_reg_ppstg_tmp_keep_V_1_reg_1356_pp0_iter1;
else
outStream_TKEEP <= "X";
end if;
end process;
outStream_TLAST_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, countWait_1_reg_516)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TLAST <= countWait_1_reg_516(9 downto 9);
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TLAST <= ap_const_lv1_0;
else
outStream_TLAST <= "X";
end if;
end process;
outStream_TSTRB_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_strb_V_reg_432, ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TSTRB <= tmp_strb_V_reg_432;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TSTRB <= ap_reg_ppstg_tmp_strb_V_1_reg_1362_pp0_iter1;
else
outStream_TSTRB <= "X";
end if;
end process;
outStream_TUSER_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, tmp_user_V_reg_419, ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2))) then
outStream_TUSER <= tmp_user_V_reg_419;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)))) then
outStream_TUSER <= ap_reg_ppstg_tmp_user_V_1_reg_1368_pp0_iter1;
else
outStream_TUSER <= "XX";
end if;
end process;
outStream_TVALID_assign_proc : process(ap_reg_ppiten_pp0_it1, ap_sig_cseq_ST_pp0_stg5_fsm_6, ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1, ap_sig_cseq_ST_st17_fsm_10, exitcond_fu_1224_p2, ap_reg_ioackin_outStream_TREADY)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg5_fsm_6) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_12_reg_1347_pp0_iter1)) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_10) and (ap_const_lv1_0 = exitcond_fu_1224_p2) and (ap_const_logic_0 = ap_reg_ioackin_outStream_TREADY)))) then
outStream_TVALID <= ap_const_logic_1;
else
outStream_TVALID <= ap_const_logic_0;
end if;
end process;
p_neg_fu_1157_p2 <= std_logic_vector(unsigned(ap_const_lv17_0) - unsigned(tmp_18_tr_fu_1154_p1));
p_s_fu_1209_p3 <=
ap_const_lv8_0 when (tmp_13_fu_1201_p3(0) = '1') else
tmp_10_fu_1197_p1;
phitmp_fu_652_p2 <= std_logic_vector(unsigned(countWait_phi_fu_509_p4) + unsigned(ap_const_lv19_1));
pixConvolved_1_fu_744_p3 <=
pixConvolved_3_fu_690_p2 when (sel_tmp9_fu_740_p2(0) = '1') else
sel_tmp7_fu_732_p3;
pixConvolved_2_fu_752_p3 <=
pixConvolved_1_fu_744_p3 when (tmp_11_reg_1332(0) = '1') else
ap_const_lv32_0;
pixConvolved_3_fu_690_p2 <= std_logic_vector(unsigned(ap_const_lv32_1) + unsigned(pixConvolved_phi_fu_497_p4));
pixConvolved_phi_fu_497_p4_assign_proc : process(ap_reg_ppiten_pp0_it1, pixConvolved_reg_493, ap_sig_cseq_ST_pp0_stg2_fsm_3, ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1, pixConvolved_2_reg_1436)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg2_fsm_3) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond1_reg_1305_pp0_iter1))) then
pixConvolved_phi_fu_497_p4 <= pixConvolved_2_reg_1436;
else
pixConvolved_phi_fu_497_p4 <= pixConvolved_reg_493;
end if;
end process;
sel_tmp10_fu_1147_p3 <=
valInWindow_0_minVal_1_2_2_i_fu_1124_p3 when (ap_reg_ppstg_sel_tmp6_reg_1426_pp0_iter1(0) = '1') else
sel_tmp_fu_1140_p3;
sel_tmp1_fu_709_p3 <=
pixConvolved_3_fu_690_p2 when (or_cond_reg_1324(0) = '1') else
pixConvolved_phi_fu_497_p4;
sel_tmp2_fu_544_p2 <= "1" when (operation = ap_const_lv32_2) else "0";
sel_tmp3_fu_716_p2 <= (or_cond_reg_1324 and sel_tmp2_reg_1290);
sel_tmp4_fu_720_p3 <=
pixConvolved_3_fu_690_p2 when (sel_tmp3_fu_716_p2(0) = '1') else
sel_tmp1_fu_709_p3;
sel_tmp5_fu_550_p2 <= "1" when (operation = ap_const_lv32_1) else "0";
sel_tmp6_fu_728_p2 <= (or_cond_reg_1324 and sel_tmp5_reg_1295);
sel_tmp7_fu_732_p3 <=
pixConvolved_3_fu_690_p2 when (sel_tmp6_fu_728_p2(0) = '1') else
sel_tmp4_fu_720_p3;
sel_tmp8_fu_556_p2 <= "1" when (operation = ap_const_lv32_0) else "0";
sel_tmp9_fu_740_p2 <= (or_cond_reg_1324 and sel_tmp8_reg_1300);
sel_tmp_fu_1140_p3 <=
valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 when (ap_reg_ppstg_sel_tmp3_reg_1421_pp0_iter1(0) = '1') else
ap_const_lv8_0;
tmp1_fu_1008_p2 <= std_logic_vector(unsigned(window_val_2_1_fu_1002_p2) + unsigned(window_val_2_0_reg_1605));
tmp2_fu_1050_p2 <= std_logic_vector(unsigned(window_val_1_1_reg_1555) + unsigned(window_val_1_2_reg_1580));
tmp3_fu_1054_p2 <= std_logic_vector(unsigned(tmp1_reg_1630) + unsigned(tmp2_fu_1050_p2));
tmp4_fu_796_p2 <= std_logic_vector(unsigned(window_val_0_0_reg_1481) + unsigned(window_val_0_1_fu_790_p2));
tmp5_fu_1083_p2 <= std_logic_vector(unsigned(window_val_2_2_reg_1655) + unsigned(window_val_0_2_reg_1517));
tmp6_fu_1087_p2 <= std_logic_vector(unsigned(window_val_1_0_reg_1530) + unsigned(tmp5_fu_1083_p2));
tmp7_fu_1092_p2 <= std_logic_vector(unsigned(tmp4_reg_1504) + unsigned(tmp6_fu_1087_p2));
tmp_10_cast_fu_1186_p1 <= std_logic_vector(resize(unsigned(tmp_1_fu_1177_p1),15));
tmp_10_fu_1197_p1 <= valOutput_1_fu_1190_p3(8 - 1 downto 0);
tmp_11_0_1_i_fu_862_p2 <= "1" when (unsigned(tmp_15_reg_1509) > unsigned(tmp_14_reg_1496)) else "0";
tmp_11_0_2_i_fu_872_p2 <= "1" when (unsigned(tmp_16_reg_1522) > unsigned(valInWindow_0_maxVal_1_0_1_i_fu_866_p3)) else "0";
tmp_11_1_1_i_fu_948_p2 <= "1" when (unsigned(tmp_18_reg_1566) > unsigned(valInWindow_0_maxVal_1_1_i_reg_1574)) else "0";
tmp_11_1_2_i_fu_985_p2 <= "1" when (unsigned(tmp_19_reg_1591) > unsigned(valInWindow_0_maxVal_1_1_1_i_reg_1599)) else "0";
tmp_11_1_i_fu_911_p2 <= "1" when (unsigned(tmp_17_reg_1541) > unsigned(valInWindow_0_maxVal_1_0_2_i_reg_1549)) else "0";
tmp_11_2_1_i_fu_1073_p2 <= "1" when (unsigned(tmp_21_reg_1641) > unsigned(valInWindow_0_maxVal_1_2_i_reg_1649)) else "0";
tmp_11_2_2_i_fu_1130_p2 <= "1" when (unsigned(tmp_22_reg_1671) > unsigned(valInWindow_0_maxVal_1_2_1_i_reg_1679)) else "0";
tmp_11_2_i_fu_1027_p2 <= "1" when (unsigned(tmp_20_reg_1616) > unsigned(valInWindow_0_maxVal_1_1_2_i_reg_1624)) else "0";
tmp_11_fu_612_p2 <= "1" when (signed(col_assign_phi_fu_475_p4) < signed(ap_const_lv32_1FF)) else "0";
tmp_12_fu_646_p2 <= "1" when (unsigned(countWait_phi_fu_509_p4) > unsigned(ap_const_lv19_201)) else "0";
tmp_13_fu_1201_p3 <= valOutput_1_fu_1190_p3(14 downto 14);
tmp_14_fu_779_p1 <= window_val_0_0_fu_773_p2(8 - 1 downto 0);
tmp_15_fu_801_p1 <= window_val_0_1_fu_790_p2(8 - 1 downto 0);
tmp_16_fu_819_p1 <= window_val_0_2_fu_813_p2(8 - 1 downto 0);
tmp_17_fu_858_p1 <= window_val_1_0_fu_830_p2(8 - 1 downto 0);
tmp_18_fu_907_p1 <= window_val_1_1_fu_891_p2(8 - 1 downto 0);
tmp_18_tr_fu_1154_p1 <= std_logic_vector(resize(signed(valOutput_reg_1685),17));
tmp_19_fu_944_p1 <= window_val_1_2_fu_928_p2(8 - 1 downto 0);
tmp_1_fu_1177_p1 <= std_logic_vector(resize(signed(tmp_9_reg_1695),14));
tmp_20_fu_981_p1 <= window_val_2_0_fu_965_p2(8 - 1 downto 0);
tmp_21_fu_1023_p1 <= window_val_2_1_fu_1002_p2(8 - 1 downto 0);
tmp_22_fu_1069_p1 <= window_val_2_2_fu_1044_p2(8 - 1 downto 0);
tmp_25_0_1_fu_696_p1 <= std_logic_vector(resize(unsigned(pixConvolved_3_fu_690_p2),64));
tmp_25_0_2_fu_759_p1 <= std_logic_vector(resize(unsigned(col_assign_1_0_2_reg_1396),64));
tmp_2_fu_1180_p2 <= std_logic_vector(unsigned(ap_const_lv15_0) - unsigned(tmp_7_cast_fu_1173_p1));
tmp_3_fu_574_p4 <= idxRow_phi_fu_486_p4(31 downto 1);
tmp_4_fu_590_p4 <= col_assign_phi_fu_475_p4(31 downto 1);
tmp_5_0_1_i_fu_836_p2 <= "1" when (unsigned(tmp_15_reg_1509) < unsigned(tmp_14_reg_1496)) else "0";
tmp_5_0_2_i_fu_846_p2 <= "1" when (unsigned(tmp_16_reg_1522) < unsigned(valInWindow_0_minVal_1_0_1_i_fu_840_p3)) else "0";
tmp_5_1_1_i_fu_934_p2 <= "1" when (unsigned(tmp_18_reg_1566) < unsigned(valInWindow_0_minVal_1_1_i_reg_1560)) else "0";
tmp_5_1_2_i_fu_971_p2 <= "1" when (unsigned(tmp_19_reg_1591) < unsigned(valInWindow_0_minVal_1_1_1_i_reg_1585)) else "0";
tmp_5_1_i_fu_897_p2 <= "1" when (unsigned(tmp_17_reg_1541) < unsigned(valInWindow_0_minVal_1_0_2_i_reg_1535)) else "0";
tmp_5_2_1_i_fu_1059_p2 <= "1" when (unsigned(tmp_21_reg_1641) < unsigned(valInWindow_0_minVal_1_2_i_reg_1635)) else "0";
tmp_5_2_2_i_fu_1120_p2 <= "1" when (unsigned(tmp_22_reg_1671) < unsigned(valInWindow_0_minVal_1_2_1_i_reg_1665)) else "0";
tmp_5_2_i_fu_1013_p2 <= "1" when (unsigned(tmp_20_reg_1616) < unsigned(valInWindow_0_minVal_1_1_2_i_reg_1610)) else "0";
tmp_7_cast_fu_1173_p1 <= std_logic_vector(resize(unsigned(tmp_8_fu_1163_p4),15));
tmp_7_fu_683_p1 <= std_logic_vector(resize(unsigned(pixConvolved_phi_fu_497_p4),64));
tmp_8_fu_1163_p4 <= p_neg_fu_1157_p2(16 downto 3);
tmp_data_V_fu_1217_p3 <=
p_s_fu_1209_p3 when (ap_reg_ppstg_sel_tmp9_reg_1431_pp0_iter1(0) = '1') else
sel_tmp10_reg_1700;
tmp_s_fu_568_p1 <= std_logic_vector(resize(unsigned(col_assign_phi_fu_475_p4),64));
valInWindow_0_maxVal_1_0_1_i_fu_866_p3 <=
tmp_15_reg_1509 when (tmp_11_0_1_i_fu_862_p2(0) = '1') else
tmp_14_reg_1496;
valInWindow_0_maxVal_1_0_2_i_fu_877_p3 <=
tmp_16_reg_1522 when (tmp_11_0_2_i_fu_872_p2(0) = '1') else
valInWindow_0_maxVal_1_0_1_i_fu_866_p3;
valInWindow_0_maxVal_1_1_1_i_fu_952_p3 <=
tmp_18_reg_1566 when (tmp_11_1_1_i_fu_948_p2(0) = '1') else
valInWindow_0_maxVal_1_1_i_reg_1574;
valInWindow_0_maxVal_1_1_2_i_fu_989_p3 <=
tmp_19_reg_1591 when (tmp_11_1_2_i_fu_985_p2(0) = '1') else
valInWindow_0_maxVal_1_1_1_i_reg_1599;
valInWindow_0_maxVal_1_1_i_fu_915_p3 <=
tmp_17_reg_1541 when (tmp_11_1_i_fu_911_p2(0) = '1') else
valInWindow_0_maxVal_1_0_2_i_reg_1549;
valInWindow_0_maxVal_1_2_1_i_fu_1077_p3 <=
tmp_21_reg_1641 when (tmp_11_2_1_i_fu_1073_p2(0) = '1') else
valInWindow_0_maxVal_1_2_i_reg_1649;
valInWindow_0_maxVal_1_2_2_i_fu_1134_p3 <=
tmp_22_reg_1671 when (tmp_11_2_2_i_fu_1130_p2(0) = '1') else
valInWindow_0_maxVal_1_2_1_i_reg_1679;
valInWindow_0_maxVal_1_2_i_fu_1031_p3 <=
tmp_20_reg_1616 when (tmp_11_2_i_fu_1027_p2(0) = '1') else
valInWindow_0_maxVal_1_1_2_i_reg_1624;
valInWindow_0_minVal_1_0_1_i_fu_840_p3 <=
tmp_15_reg_1509 when (tmp_5_0_1_i_fu_836_p2(0) = '1') else
tmp_14_reg_1496;
valInWindow_0_minVal_1_0_2_i_fu_851_p3 <=
tmp_16_reg_1522 when (tmp_5_0_2_i_fu_846_p2(0) = '1') else
valInWindow_0_minVal_1_0_1_i_fu_840_p3;
valInWindow_0_minVal_1_1_1_i_fu_938_p3 <=
tmp_18_reg_1566 when (tmp_5_1_1_i_fu_934_p2(0) = '1') else
valInWindow_0_minVal_1_1_i_reg_1560;
valInWindow_0_minVal_1_1_2_i_fu_975_p3 <=
tmp_19_reg_1591 when (tmp_5_1_2_i_fu_971_p2(0) = '1') else
valInWindow_0_minVal_1_1_1_i_reg_1585;
valInWindow_0_minVal_1_1_i_fu_901_p3 <=
tmp_17_reg_1541 when (tmp_5_1_i_fu_897_p2(0) = '1') else
valInWindow_0_minVal_1_0_2_i_reg_1535;
valInWindow_0_minVal_1_2_1_i_fu_1063_p3 <=
tmp_21_reg_1641 when (tmp_5_2_1_i_fu_1059_p2(0) = '1') else
valInWindow_0_minVal_1_2_i_reg_1635;
valInWindow_0_minVal_1_2_2_i_fu_1124_p3 <=
tmp_22_reg_1671 when (tmp_5_2_2_i_fu_1120_p2(0) = '1') else
valInWindow_0_minVal_1_2_1_i_reg_1665;
valInWindow_0_minVal_1_2_i_fu_1017_p3 <=
tmp_20_reg_1616 when (tmp_5_2_i_fu_1013_p2(0) = '1') else
valInWindow_0_minVal_1_1_2_i_reg_1610;
valOutput_1_fu_1190_p3 <=
tmp_2_fu_1180_p2 when (tmp_6_reg_1690(0) = '1') else
tmp_10_cast_fu_1186_p1;
valOutput_fu_1097_p2 <= std_logic_vector(unsigned(tmp3_reg_1660) + unsigned(tmp7_fu_1092_p2));
window_val_0_0_fu_773_p0 <= reg_527;
window_val_0_0_fu_773_p1 <= window_val_0_0_fu_773_p10(8 - 1 downto 0);
window_val_0_0_fu_773_p10 <= std_logic_vector(resize(unsigned(reg_535),16));
window_val_0_0_fu_773_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_0_fu_773_p0) * signed('0' &window_val_0_0_fu_773_p1))), 16));
window_val_0_1_fu_790_p0 <= reg_531;
window_val_0_1_fu_790_p1 <= window_val_0_1_fu_790_p10(8 - 1 downto 0);
window_val_0_1_fu_790_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_0_load_1_reg_1441),16));
window_val_0_1_fu_790_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_1_fu_790_p0) * signed('0' &window_val_0_1_fu_790_p1))), 16));
window_val_0_2_fu_813_p0 <= reg_540;
window_val_0_2_fu_813_p1 <= window_val_0_2_fu_813_p10(8 - 1 downto 0);
window_val_0_2_fu_813_p10 <= std_logic_vector(resize(unsigned(reg_535),16));
window_val_0_2_fu_813_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_0_2_fu_813_p0) * signed('0' &window_val_0_2_fu_813_p1))), 16));
window_val_1_0_fu_830_p0 <= reg_527;
window_val_1_0_fu_830_p1 <= window_val_1_0_fu_830_p10(8 - 1 downto 0);
window_val_1_0_fu_830_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_1_reg_1451),16));
window_val_1_0_fu_830_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_0_fu_830_p0) * signed('0' &window_val_1_0_fu_830_p1))), 16));
window_val_1_1_fu_891_p0 <= reg_531;
window_val_1_1_fu_891_p1 <= window_val_1_1_fu_891_p10(8 - 1 downto 0);
window_val_1_1_fu_891_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_2_reg_1456),16));
window_val_1_1_fu_891_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_1_fu_891_p0) * signed('0' &window_val_1_1_fu_891_p1))), 16));
window_val_1_2_fu_928_p0 <= reg_540;
window_val_1_2_fu_928_p1 <= window_val_1_2_fu_928_p10(8 - 1 downto 0);
window_val_1_2_fu_928_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_1_load_3_reg_1486),16));
window_val_1_2_fu_928_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_1_2_fu_928_p0) * signed('0' &window_val_1_2_fu_928_p1))), 16));
window_val_2_0_fu_965_p0 <= reg_527;
window_val_2_0_fu_965_p1 <= window_val_2_0_fu_965_p10(8 - 1 downto 0);
window_val_2_0_fu_965_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_1_reg_1466),16));
window_val_2_0_fu_965_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_0_fu_965_p0) * signed('0' &window_val_2_0_fu_965_p1))), 16));
window_val_2_1_fu_1002_p0 <= reg_531;
window_val_2_1_fu_1002_p1 <= window_val_2_1_fu_1002_p10(8 - 1 downto 0);
window_val_2_1_fu_1002_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_2_reg_1471),16));
window_val_2_1_fu_1002_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_1_fu_1002_p0) * signed('0' &window_val_2_1_fu_1002_p1))), 16));
window_val_2_2_fu_1044_p0 <= reg_540;
window_val_2_2_fu_1044_p1 <= window_val_2_2_fu_1044_p10(8 - 1 downto 0);
window_val_2_2_fu_1044_p10 <= std_logic_vector(resize(unsigned(lineBuff_val_2_load_3_reg_1491),16));
window_val_2_2_fu_1044_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(window_val_2_2_fu_1044_p0) * signed('0' &window_val_2_2_fu_1044_p1))), 16));
end behav;
|
gpl-3.0
|
56377b9806317ccdac0e481113f6db3e
| 0.611197 | 2.672518 | false | false | false | false |
lfmunoz/vhdl
|
ip_blocks/sip_check_data/ip_block_ctrl.vhd
| 1 | 8,769 |
-------------------------------------------------------------------------------------
-- FILE NAME : .vhd
-- AUTHOR :
-- COMPANY : 4DSP
-- ITEM : 1
-- UNITS : Entity -
-- architecture -
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- Specified libraries
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- Entity declaration
-------------------------------------------------------------------------------------
entity ip_block_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
cmd_busy : out std_logic;
reg0 : out std_logic_vector(31 downto 0); -- out
reg1 : out std_logic_vector(31 downto 0); --out
reg2 : in std_logic_vector(31 downto 0); --in
reg3 : in std_logic_vector(31 downto 0); --in
reg4 : in std_logic_vector(31 downto 0); --in
reg5 : in std_logic_vector(31 downto 0); --in
reg6 : in std_logic_vector(31 downto 0); --in
reg7 : in std_logic_vector(31 downto 0); --in
reg8 : in std_logic_vector(31 downto 0); --in
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end ip_block_ctrl;
-------------------------------------------------------------------------------------
-- Architecture declaration
-------------------------------------------------------------------------------------
architecture Behavioral of ip_block_ctrl is
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_REG0 : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_REG1 : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_REG2 : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_REG3 : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_REG4 : std_logic_vector(31 downto 0) := x"00000004";
constant ADDR_REG5 : std_logic_vector(31 downto 0) := x"00000005";
constant ADDR_REG6 : std_logic_vector(31 downto 0) := x"00000006";
constant ADDR_REG7 : std_logic_vector(31 downto 0) := x"00000007";
constant ADDR_REG8 : std_logic_vector(31 downto 0) := x"00000008";
constant ADDR_REG9 : std_logic_vector(31 downto 0) := x"00000009";
constant ADDR_REGA : std_logic_vector(31 downto 0) := x"0000000A";
constant ADDR_REGB : std_logic_vector(31 downto 0) := x"0000000B";
constant ADDR_REGC : std_logic_vector(31 downto 0) := x"0000000C";
constant ADDR_REGD : std_logic_vector(31 downto 0) := x"0000000D";
constant ADDR_REGE : std_logic_vector(31 downto 0) := x"0000000E";
constant ADDR_REGF : std_logic_vector(31 downto 0) := x"0000000F";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal register0 : std_logic_vector(31 downto 0);
signal register1 : std_logic_vector(31 downto 0);
signal register2 : std_logic_vector(31 downto 0);
signal register3 : std_logic_vector(31 downto 0);
signal register4 : std_logic_vector(31 downto 0);
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal register9 : std_logic_vector(31 downto 0);
signal registerA : std_logic_vector(31 downto 0);
--*************************************************************************************************
begin
--*************************************************************************************************
reg0 <= register0;
reg1 <= register1;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
stellar_cmd_inst:
entity work.stellar_generic_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => mbx_in_val,
mbx_in_reg => mbx_in_reg
);
cmd_busy <= '0';
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
in_reg_val <= '0';
in_reg <= (others => '0');
register0 <= (others=>'0');
register1 <= (others=>'0');
elsif (rising_edge(clk_cmd)) then
------------------------------------------------------------
-- Write
------------------------------------------------------------
if (out_reg_val = '1' and out_reg_addr = ADDR_REG0) then
register0 <= out_reg;
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_REG1) then
register1 <= out_reg;
end if;
------------------------------------------------------------
-- Read
------------------------------------------------------------
if (in_reg_req = '1' and in_reg_addr = ADDR_REG0) then
in_reg_val <= '1';
in_reg <= register0;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG1) then
in_reg_val <= '1';
in_reg <= register1;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG2) then
in_reg_val <= '1';
in_reg <= reg2;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG3) then
in_reg_val <= '1';
in_reg <= reg3;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG4) then
in_reg_val <= '1';
in_reg <= reg4;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG5) then
in_reg_val <= '1';
in_reg <= reg5;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG6) then
in_reg_val <= '1';
in_reg <= reg6;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG7) then
in_reg_val <= '1';
in_reg <= reg7;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG8) then
in_reg_val <= '1';
in_reg <= reg8;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
--*************************************************************************************************
end Behavioral;
--*************************************************************************************************
|
mit
|
000f66fa8aa0f8e9dc71e2b2de58455d
| 0.409739 | 4.130476 | false | false | false | false |
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd
| 4 | 2,978 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc741.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n01i00741ent_a is
generic (
constant gc1 : in integer;
constant gc2 : in real;
constant gc3 : in boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00741ent_a;
architecture c01s01b01x01p04n01i00741arch_a of c01s01b01x01p04n01i00741ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00741"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00741 - Simple generic association in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00741arch_a;
ENTITY c01s01b01x01p04n01i00741ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00741ent;
ARCHITECTURE c01s01b01x01p04n01i00741arch OF c01s01b01x01p04n01i00741ent IS
constant c1 : integer := 33;
constant c2 : real := 1.23557;
constant c3 : boolean := FALSE;
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : real;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00741ent_a(c01s01b01x01p04n01i00741arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (5, 0.1234, TRUE)
port map (ee1,ee2);
END c01s01b01x01p04n01i00741arch;
|
gpl-2.0
|
430064fd5057586d997759c31f8c898c
| 0.645064 | 3.411226 | false | false | false | false |
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