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Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd | 7 | 39,579 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
-- ch2_updt_curdesc_wren : out std_logic ; --
-- ch2_updt_curdesc : out std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_INCLUDE_MM2S => C_INCLUDE_CH1 ,
C_INCLUDE_S2MM => C_INCLUDE_CH2 ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
-- updt2_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt2_curdesc => ch2_updt_curdesc ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
updt2_active => ch2_updt_active ,
updt2_queue_empty => ch2_updt_queue_empty ,
updt2_ioc => ch2_updt_ioc ,
updt2_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma2_interr => ch2_dma_interr ,
dma2_slverr => ch2_dma_slverr ,
dma2_decerr => ch2_dma_decerr ,
dma2_interr_set => ch2_dma_interr_set ,
dma2_slverr_set => ch2_dma_slverr_set ,
dma2_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Update Pointer Stream
s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready ,
-- m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch1_updt_tready ,
-- S2MM Stream Out To DataMover
-- m_axis2_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis2_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis2_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_NO_QUEUE;
-- Channel 1 NOT included therefore tie ch1 outputs off
--GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
--begin
-- ch1_updt_curdesc_wren <= '0';
-- ch1_updt_curdesc <= (others => '0');
-- ch1_updt_queue_empty <= '1';
-- ch1_updt_ioc <= '0';
-- ch1_dma_interr <= '0';
-- ch1_dma_slverr <= '0';
-- ch1_dma_decerr <= '0';
-- m_axis_ch1_updt_tdata <= (others => '0');
-- m_axis_ch1_updt_tlast <= '0';
-- m_axis_ch1_updt_tvalid <= '0';
-- s_axis_ch1_updtptr_tready <= '0';
-- s_axis_ch1_updtsts_tready <= '0';
--end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
--GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
--
--begin
--
-- --*************************************************************************
-- --** CHANNEL 2 - DESCRIPTOR QUEUE **
-- --*************************************************************************
-- -- If Descriptor Update queueing enabled then instantiate Queue Logic
-- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
-- begin
-- ---------------------------------------------------------------------------
-- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_queue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
-- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
-- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_QUEUE;
--
--
-- --*****************************************************************************
-- --** CHANNEL 2 - NO DESCRIPTOR QUEUE **
-- --*****************************************************************************
--
-- -- No update queue enabled, therefore map internal stream logic
-- -- directly to channel port.
-- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
-- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_noqueue
-- generic map(
-- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
-- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
-- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
-- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
-- )
-- port map(
-- ---------------------------------------------------------------
-- -- AXI Scatter Gather Interface
-- ---------------------------------------------------------------
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- --********************************--
-- --** Control and Status **--
-- --********************************--
-- updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- updt_curdesc => ch2_updt_curdesc ,
-- updt_active => ch2_updt_active ,
-- updt_queue_empty => ch2_updt_queue_empty ,
-- updt_ioc => ch2_updt_ioc ,
-- updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
--
-- dma_interr => ch2_dma_interr ,
-- dma_slverr => ch2_dma_slverr ,
-- dma_decerr => ch2_dma_decerr ,
-- dma_interr_set => ch2_dma_interr_set ,
-- dma_slverr_set => ch2_dma_slverr_set ,
-- dma_decerr_set => ch2_dma_decerr_set ,
--
-- --********************************--
-- --** Update Interfaces In **--
-- --********************************--
-- -- Update Pointer Stream
-- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
-- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
-- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
-- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
--
-- -- Update Status Stream
-- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
-- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
-- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
-- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--
-- --********************************--
-- --** Update Interfaces Out **--
-- --********************************--
-- -- S2MM Stream Out To DataMover
-- m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
-- m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
-- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
-- m_axis_updt_tready => m_axis_ch2_updt_tready
-- );
--
-- end generate GEN_CH2_NO_QUEUE;
--
--end generate GEN_CH2_UPDATE_Q_IF;
--
---- Channel 2 NOT included therefore tie ch2 outputs off
--GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
--begin
-- ch2_updt_curdesc_wren <= '0';
-- ch2_updt_curdesc <= (others => '0');
-- ch2_updt_queue_empty <= '1';
--
-- ch2_updt_ioc <= '0';
-- ch2_dma_interr <= '0';
-- ch2_dma_slverr <= '0';
-- ch2_dma_decerr <= '0';
--
-- m_axis_ch2_updt_tdata <= (others => '0');
-- m_axis_ch2_updt_tlast <= '0';
-- m_axis_ch2_updt_tvalid <= '0';
--
-- s_axis_ch2_updtptr_tready <= '0';
-- s_axis_ch2_updtsts_tready <= '0';
--
--end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
--TO_DATAMVR_MUX : process(ch1_updt_active,
-- ch2_updt_active,
-- m_axis_ch1_updt_tdata,
-- m_axis_ch1_updt_tlast,
-- m_axis_ch1_updt_tvalid,
-- m_axis_ch2_updt_tdata,
-- m_axis_ch2_updt_tlast,
-- m_axis_ch2_updt_tvalid)
-- begin
-- if(ch1_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
-- elsif(ch2_updt_active = '1')then
-- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
-- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
-- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
-- else
-- s_axis_s2mm_tdata <= (others => '0');
-- s_axis_s2mm_tlast <= '0';
-- s_axis_s2mm_tvalid <= '0';
-- end if;
-- end process TO_DATAMVR_MUX;
--
--m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
--m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
--
end implementation;
| gpl-3.0 | e6b1be5a9ed94411acb36f7ecbe9932d | 0.352055 | 4.661837 | false | false | false | false |
tgingold/ghdl | testsuite/synth/psl01/cover2.vhdl | 1 | 497 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cover2 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end cover2;
architecture behav of cover2 is
signal val : unsigned (3 downto 0);
default clock is rising_edge(clk);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
cover {val = 10};
end behav;
| gpl-2.0 | ce0110a6cff2c0dcd5d9985922a7204e | 0.62173 | 3.14557 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split6.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split6 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split6;
architecture augh of output_split6 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 0c09c8c0c001cf195c9cdd490cf25d24 | 0.673759 | 2.895277 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1295/psl_next_event_a.vhdl | 1 | 1,804 | library ieee;
use ieee.std_logic_1164.all;
entity sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end entity sequencer;
architecture rtl of sequencer is
signal index : natural := seq'low;
signal ch : character;
function to_bit (a : in character) return std_logic is
variable ret : std_logic;
begin
case a is
when '0' | '_' => ret := '0';
when '1' | '-' => ret := '1';
when others => ret := 'X';
end case;
return ret;
end function to_bit;
begin
process (clk) is
begin
if rising_edge(clk) then
if (index < seq'high) then
index <= index + 1;
end if;
end if;
end process;
ch <= seq(index);
data <= to_bit(ch);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity psl_next_event_a is
end entity psl_next_event_a;
architecture psl of psl_next_event_a is
signal clk : std_logic := '0';
component sequencer is
generic (
seq : string
);
port (
clk : in std_logic;
data : out std_logic
);
end component sequencer;
signal a, b, c : std_logic;
begin
-- 012345678901234
SEQ_A : sequencer generic map ("_-______________-____") port map (clk, a);
SEQ_B : sequencer generic map ("--___--__----________") port map (clk, b);
SEQ_C : sequencer generic map ("_____-___---_____----") port map (clk, c);
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
assert_NEXT_EVENT_a : assert always ((a and b) -> next_event_a(c)[1 to 4](b));
process
begin
for i in 1 to 2*20 loop
wait for 1 ns;
clk <= not clk;
end loop;
wait;
end process;
end architecture psl;
| gpl-2.0 | f2c7c443480f864cb3a138efef6283c6 | 0.562639 | 3.469231 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/vector.d/pkg_tb.vhd | 2 | 1,772 | --test bench written by alban bourge @ tima
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_tb is
--fsm state types
type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
--context descriptor
subtype context_t is std_logic_vector(1 downto 0);
--argument width and type of fsm instruction
constant ARG_WIDTH : integer := 8;
subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0);
type instruction is
record
state : state_t;
context_uut : context_t;
arg : argument_t;
end record;
--reset instruction
constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0'));
--ram instruction
type ram_instruction is
record
sel : std_logic;
we : std_logic;
addr_up : std_logic;
addr_z : std_logic;
end record;
constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0');
--assert unit instruction
type assert_instruction is
record
en_feed : std_logic;
en_check : std_logic;
end record;
constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0');
--size of instruction table defined by PC_SIZE i.e. width of program counter
constant PC_SIZE : integer := 5;
type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction;
--constraint fixed by unit under test (augh dependant)
--##CONSTRAINTS_START##--
subtype stdin_vector is std_logic_vector(31 downto 0);
subtype stdout_vector is std_logic_vector(31 downto 0);
subtype cp_vector is std_logic_vector(63 downto 0);
--##CONSTRAINTS_END##--
--assert_uut vector number counter size
constant VEC_NO_SIZE : integer := 20;
end pkg_tb;
| gpl-2.0 | 24c03ef2c7210f6b9459550d1e65a726 | 0.676072 | 3.119718 | false | false | false | false |
nickg/nvc | test/elab/issue184.vhd | 5 | 345 | entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
| gpl-3.0 | 0b7805ef087845bcebd56def96fc71ab | 0.617391 | 3.45 | false | true | false | false |
tgingold/ghdl | testsuite/synth/uassoc01/uassoc01.vhdl | 1 | 730 | library ieee;
use ieee.std_logic_1164.all;
entity uassoc01_sub is
port (i : std_logic_vector;
o : out std_logic_vector);
end uassoc01_sub;
architecture behav of uassoc01_sub is
begin
o <= not i;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity uassoc01 is
port (i1 : std_logic_vector(3 downto 0);
i2 : std_logic_vector(7 downto 0);
o : out std_logic_vector(3 downto 0));
end uassoc01;
architecture rtl of uassoc01 is
signal o1: std_logic_vector(3 downto 0);
signal o2: std_logic_vector(7 downto 0);
begin
dut1: entity work.uassoc01_sub
port map (i => i1, o => o1);
dut2: entity work.uassoc01_sub
port map (i => i2, o => o2);
o <= o1 xor o2 (3 downto 0);
end rtl;
| gpl-2.0 | fa69cde662b4dd6339c450e6ff8b9fa5 | 0.658904 | 2.885375 | false | false | false | false |
tgingold/ghdl | testsuite/synth/aggr02/tb_targ01.vhdl | 1 | 550 | entity tb_targ01 is
end tb_targ01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_targ01 is
signal v : std_logic_vector(2 downto 0);
signal o0 : std_logic;
signal o1 : std_logic;
signal o2 : std_logic;
begin
dut: entity work.targ01
port map (v, o0, o1, o2);
process
begin
v <= "010";
wait for 1 ns;
assert o2 = '0' and o1 = '1' and o0 = '0' severity failure;
v <= "101";
wait for 1 ns;
assert o2 = '1' and o1 = '0' and o0 = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 32c760dcea27e511c3ee8c3d9956c2f7 | 0.614545 | 2.806122 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_sitofp_4_no_dsp_32/synth/doHistStretch_ap_sitofp_4_no_dsp_32.vhd | 3 | 12,516 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_sitofp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_sitofp_4_no_dsp_32;
ARCHITECTURE doHistStretch_ap_sitofp_4_no_dsp_32_arch OF doHistStretch_ap_sitofp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_sitofp_4_no_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_sitofp_4_no_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_sitofp_4_no_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=1,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FM" &
"S=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=0,C_B_WIDTH=32,C_B_FRACTION_WIDTH=0,C_C_WIDTH=32,C_C_FRACTION_WIDTH=0,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_T" &
"HROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_sitofp_4_no_dsp_32_arch;
| gpl-3.0 | 318629f72e04078c92f899e19dbbc5c0 | 0.650447 | 3.029775 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd | 3 | 87,982 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the alignment port widths. The value should be
-- log2(C_DWIDTH)
);
port (
-- Clock and Reset inputs ---------------
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------
-- Alignment Controls ------------------------------------------------
dre_new_align : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Input Stream Interface --------------------------------------------
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Output Stream Interface -------------------------------------------
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_dre;
architecture implementation of axi_datamover_mm2s_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
signal sig_enable_input_rdy : std_logic := '0';
signal sig_input_ready : std_logic := '0';
begin --(architecture implementation)
-- Misc assignments
--dre_in_tready <= sig_input_accept ;
dre_in_tready <= sig_input_ready ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
sig_pipeline_halt <= sig_dre_tvalid_i and not(dre_out_tready);
sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt) and
sig_enable_input_rdy;
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
sig_input_ready;
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
sig_input_ready <= sig_enable_input_rdy and
not(sig_pipeline_halt) and
not(sig_input_flush_stall) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_FLOP
--
-- Process Description:
-- Just a flop for generating an input disable while reset
-- is in progress.
--
-------------------------------------------------------------
IMP_RESET_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_enable_input_rdy <= '0';
else
sig_enable_input_rdy <= '1';
end if;
end if;
end process IMP_RESET_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Register for the flush signal
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal s_case_i_64 : Integer range 0 to 7 := 0;
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
-- signal sig_cntl_state_64 : std_logic_vector(5 downto 0);
-- Signal s_case_i_64 : Integer range 0 to 7;
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0) ,
I0 => sig_input_data_reg(1) ,
I1 => sig_input_data_reg(0) ,
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
signal sig_cntl_state_32 : std_logic_vector(3 downto 0);
Signal s_case_i_32 : Integer range 0 to 3;
Signal sig_shift_case_i : std_logic_vector(1 downto 0);
Signal sig_shift_case_reg : std_logic_vector(1 downto 0);
Signal sig_final_mux_sel : std_logic_vector(3 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
signal sig_cntl_state_16 : std_logic_vector(1 downto 0);
Signal s_case_i_16 : Integer range 0 to 1;
Signal sig_shift_case_i : std_logic;
Signal sig_shift_case_reg : std_logic;
Signal sig_final_mux_sel : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_10.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| gpl-3.0 | 3d92ad5d66ddf336065d43e86d0e798a | 0.368507 | 4.598923 | false | false | false | false |
tgingold/ghdl | libraries/vital2000/memory_b.vhdl | 6 | 275,738 | -- ----------------------------------------------------------------------------
-- Title : Standard VITAL Memory Package
-- :
-- Library : Vital_Memory
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- : Ekambaram Balaji, LSI Logic Corporation
-- : Jose De Castro, Consultant
-- : Prakash Bare, GDA Technologies
-- : William Yam, LSI Logic Corporation
-- : Dennis Brophy, Model Technology
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC memory models.
-- :
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Ver:|Auth:| Date:| Changes Made:
-- 0.1 | eb |071796| First prototye as part of VITAL memory proposal
-- 0.2 | jdc |012897| Initial prototyping with proposed MTM scheme
-- 0.3 | jdc |090297| Extensive updates for TAG review (functional)
-- 0.4 | eb |091597| Changed naming conventions for VitalMemoryTable
-- | | | Added interface of VitalMemoryCrossPorts() &
-- | | | VitalMemoryViolation().
-- 0.5 | jdc |092997| Completed naming changes thoughout package body.
-- | | | Testing with simgle port test model looks ok.
-- 0.6 | jdc |121797| Major updates to the packages:
-- | | | - Implement VitalMemoryCrossPorts()
-- | | | - Use new VitalAddressValueType
-- | | | - Use new VitalCrossPortModeType enum
-- | | | - Overloading without SamePort args
-- | | | - Honor erroneous address values
-- | | | - Honor ports disabled with 'Z'
-- | | | - Implement implicit read 'M' table symbol
-- | | | - Cleanup buses to use (H DOWNTO L)
-- | | | - Message control via MsgOn,HeaderMsg,PortName
-- | | | - Tested with 1P1RW,2P2RW,4P2R2W,4P4RW cases
-- 0.7 | jdc |052698| Bug fixes to the packages:
-- | | | - Fix failure with negative Address values
-- | | | - Added debug messages for VMT table search
-- | | | - Remove 'S' for action column (only 's')
-- | | | - Remove 's' for response column (only 'S')
-- | | | - Remove 'X' for action and response columns
-- 0.8 | jdc |061298| Implemented VitalMemoryViolation()
-- | | | - Minimal functionality violation tables
-- | | | - Missing:
-- | | | - Cannot handle wide violation variables
-- | | | - Cannot handle sub-word cases
-- | | | Fixed IIC version of MemoryMatch
-- | | | Fixed 'M' vs 'm' switched on debug output
-- | | | TO BE DONE:
-- | | | - Implement 'd' corrupting a single bit
-- | | | - Implement 'D' corrupting a single bit
-- 0.9 |eb/sc|080498| Added UNDEF value for VitalPortFlagType
-- 0.10|eb/sc|080798| Added CORRUPT value for VitalPortFlagType
-- 0.11|eb/sc|081798| Added overloaded function interface for
-- | | | VitalDeclareMemory
-- 0.14| jdc |113198| Merging of memory functionality and version
-- | | | 1.4 9/17/98 of timing package from Prakash
-- 0.15| jdc |120198| Major development of VMV functionality
-- 0.16| jdc |120298| Complete VMV functionlality for initial testing
-- | | | - New ViolationTableCorruptMask() procedure
-- | | | - New MemoryTableCorruptMask() procedure
-- | | | - HandleMemoryAction():
-- | | | - Removed DataOutBus bogus output
-- | | | - Replaced DataOutTmp with DataInTmp
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'c','l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'c','l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'C','L','D','E' to use HighBit, LowBit
-- | | | - HandleDataAction():
-- | | | - Added CorruptMask input handling
-- | | | - Implemented 'd','D' using CorruptMask
-- | | | - CorruptMask on 'd','C','L','D','E'
-- | | | - CorruptMask ignored on 'l','e'
-- | | | - Changed 'l','d','e' to set PortFlag to CORRUPT
-- | | | - Changed 'L','D','E' to set PortFlag to CORRUPT
-- | | | - Changed 'l','d','e' to ignore HighBit, LowBit
-- | | | - Changed 'L','D','E' to use HighBit, LowBit
-- | | | - MemoryTableLookUp():
-- | | | - Added MsgOn table debug output
-- | | | - Uses new MemoryTableCorruptMask()
-- | | | - ViolationTableLookUp():
-- | | | - Uses new ViolationTableCorruptMask()
-- 0.17| jdc |120898| - Added VitalMemoryViolationSymbolType,
-- | | | VitalMemoryViolationTableType data
-- | | | types but not used yet (need to discuss)
-- | | | - Added overload for VitalMemoryViolation()
-- | | | which does not have array flags
-- | | | - Bug fixes for VMV functionality:
-- | | | - ViolationTableLookUp() not handling '-' in
-- | | | scalar violation matching
-- | | | - VitalMemoryViolation() now normalizes
-- | | | VFlagArrayTmp'LEFT as LSB before calling
-- | | | ViolationTableLookUp() for proper scanning
-- | | | - ViolationTableCorruptMask() had to remove
-- | | | normalization of CorruptMaskTmp and
-- | | | ViolMaskTmp for proper MSB:LSB corruption
-- | | | - HandleMemoryAction(), HandleDataAction()
-- | | | - Removed 'D','E' since not being used
-- | | | - Use XOR instead of OR for corrupt masks
-- | | | - Now 'd' is sensitive to HighBit, LowBit
-- | | | - Fixed LowBit overflow in bit writeable case
-- | | | - MemoryTableCorruptMask()
-- | | | - ViolationTableCorruptMask()
-- | | | - VitalMemoryTable()
-- | | | - VitalMemoryCrossPorts()
-- | | | - Fixed VitalMemoryViolation() failing on
-- | | | error AddressValue from earlier VMT()
-- | | | - Minor cleanup of code formatting
-- 0.18| jdc |032599| - In VitalDeclareMemory()
-- | | | - Added BinaryLoadFile formal arg and
-- | | | modified LoadMemory() to handle bin
-- | | | - Added NOCHANGE to VitalPortFlagType
-- | | | - For VitalCrossPortModeType
-- | | | - Added CpContention enum
-- | | | - In HandleDataAction()
-- | | | - Set PortFlag := NOCHANGE for 'S'
-- | | | - In HandleMemoryAction()
-- | | | - Set PortFlag := NOCHANGE for 's'
-- | | | - In VitalMemoryTable() and
-- | | | VitalMemoryViolation()
-- | | | - Honor PortFlag = NOCHANGE returned
-- | | | from HandleMemoryAction()
-- | | | - In VitalMemoryCrossPorts()
-- | | | - Fixed Address = AddressJ for all
-- | | | conditions of DoWrCont & DoCpRead
-- | | | - Handle CpContention like WrContOnly
-- | | | under CpReadOnly conditions, with
-- | | | associated memory message changes
-- | | | - Handle PortFlag = NOCHANGE like
-- | | | PortFlag = READ for actions
-- | | | - Modeling change:
-- | | | - Need to init PortFlag every delta
-- | | | PortFlag_A := (OTHES => UNDEF);
-- | | | - Updated InternalTimingCheck code
-- 0.19| jdc |042599| - Fixes for bit-writeable cases
-- | | | - Check PortFlag after HandleDataAction
-- | | | in VitalMemoryViolation()
-- 0.20| jdc |042599| - Merge PortFlag changes from Prakash
-- | | | and Willian:
-- | | | VitalMemorySchedulePathDelay()
-- | | | VitalMemoryExpandPortFlag()
-- 0.21| jdc |072199| - Changed VitalCrossPortModeType enums,
-- | | | added new CpReadAndReadContention.
-- | | | - Fixed VitalMemoryCrossPorts() parameter
-- | | | SamePortFlag to INOUT so that it can
-- | | | set CORRUPT or READ value.
-- | | | - Fixed VitalMemoryTable() where PortFlag
-- | | | setting by HandleDataAction() is being
-- | | | ignored when HandleMemoryAction() sets
-- | | | PortFlagTmp to NOCHANGE.
-- | | | - Fixed VitalMemoryViolation() to set
-- | | | all bits of PortFlag when violating.
-- 0.22| jdc |072399| - Added HIGHZ to PortFlagType. HandleData
-- | | | checks whether the previous state is HIGHZ.
-- | | | If yes then portFlag should be NOCHANGE
-- | | | for VMPD to ignore IORetain corruption.
-- | | | The idea is that the first Z should be
-- | | | propagated but later ones should be ignored.
-- | | |
-- 0.23| jdc |100499| - Took code checked in by Dennis 09/28/99
-- | | | - Changed VitalPortFlagType to record of
-- | | | new VitalPortStateType to hold current,
-- | | | previous values and separate disable.
-- | | | Also created VitalDefaultPortFlag const.
-- | | | Removed usage of PortFlag NOCHANGE
-- | | | - VitalMemoryTable() changes:
-- | | | Optimized return when all curr = prev
-- | | | AddressValue is now INOUT to optimize
-- | | | Transfer PF.MemoryCurrent to MemoryPrevious
-- | | | Transfer PF.DataCurrent to DataPrevious
-- | | | Reset PF.OutputDisable to FALSE
-- | | | Expects PortFlag init in declaration
-- | | | No need to init PortFlag every delta
-- | | | - VitalMemorySchedulePathDelay() changes:
-- | | | Initialize with VitalDefaultPortFlag
-- | | | Check PortFlag.OutputDisable
-- | | | - HandleMemoryAction() changes:
-- | | | Set value of PortFlag.MemoryCurrent
-- | | | Never set PortFlag.OutputDisable
-- | | | - HandleDataAction() changes:
-- | | | Set value of PortFlag.DataCurrent
-- | | | Set PortFlag.DataCurrent for HIGHZ
-- | | | - VitalMemoryCrossPorts() changes:
-- | | | Check/set value of PF.MemoryCurrent
-- | | | Check value of PF.OutputDisable
-- | | | - VitalMemoryViolation() changes:
-- | | | Fixed bug - not reading inout PF value
-- | | | Clean up setting of PortFlag
-- 0.24| jdc |100899| - Modified update of PF.OutputDisable
-- | | | to correctly accomodate 2P1W1R case:
-- | | | the read port should not exhibit
-- | | | IO retain corrupt when reading
-- | | | addr unrelated to addr being written.
-- 0.25| jdc |100999| - VitalMemoryViolation() change:
-- | | | Fixed bug with RDNWR mode incorrectly
-- | | | updating the PF.OutputDisable
-- 0.26| jdc |100999| - VitalMemoryCrossPorts() change:
-- | | | Fixed bugs with update of PF
-- 0.27| jdc |101499| - VitalMemoryCrossPorts() change:
-- | | | Added DoRdWrCont message (ErrMcpRdWrCo,
-- | | | Memory cross port read/write data only
-- | | | contention)
-- | | | - VitalMemoryTable() change:
-- | | | Set PF.OutputDisable := TRUE for the
-- | | | optimized cases.
-- 0.28| pb |112399| - Added 8 VMPD procedures for vector
-- | | | PathCondition support. Now the total
-- | | | number of overloadings for VMPD is 24.
-- | | | - Number of overloadings for SetupHold
-- | | | procedures increased to 5. Scalar violations
-- | | | are not supported anymore. Vector checkEnabled
-- | | | support is provided through the new overloading
-- 0.29| jdc |120999| - HandleMemoryAction() HandleDataAction()
-- | | | Reinstated 'D' and 'E' actions but
-- | | | with new PortFlagType
-- | | | - Updated file handling syntax, must compile
-- | | | with -93 syntax now.
-- 0.30| jdc |022300| - Formated for 80 column max width
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.Vital_Timing.all;
USE IEEE.Vital_Primitives.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
-- ----------------------------------------------------------------------------
PACKAGE BODY Vital_Memory IS
-- ----------------------------------------------------------------------------
-- Timing Section
-- ----------------------------------------------------------------------------
FILE LogFile : TEXT OPEN write_mode IS "delayLog";
FILE Output : TEXT OPEN write_mode IS "STD_OUTPUT";
-- Added for turning off the debug msg..
CONSTANT PrintDebugMsg : STD_ULOGIC := '0';
-- '0' - don't print in STD OUTPUT
-- '1' - print in STD OUTPUT
-- Type and constant definitions for type conversion.
TYPE MVL9_TO_CHAR_TBL IS ARRAY (STD_ULOGIC) OF character;
--constant MVL9_to_char: MVL9_TO_CHAR_TBL := "UX01ZWLH-";
CONSTANT MVL9_to_char: MVL9_TO_CHAR_TBL := "XX01ZX010";
-- ----------------------------------------------------------------------------
-- STD_LOGIC WRITE UTILITIES
-- ----------------------------------------------------------------------------
PROCEDURE WRITE(
l : INOUT line;
val : IN std_logic_vector;
justify : IN side := right;
field : IN width := 0
) IS
VARIABLE invect : std_logic_vector(val'LENGTH DOWNTO 1);
VARIABLE ins : STRING(val'LENGTH DOWNTO 1);
BEGIN
invect := val;
FOR I IN invect'length DOWNTO 1 LOOP
ins(I) := MVL9_to_char(invect(I));
END LOOP;
WRITE(L, ins, justify, field);
END;
PROCEDURE WRITE(
l : INOUT line;
val : IN std_ulogic;
justify : IN side := right;
field : in width := 0
) IS
VARIABLE ins : CHARACTER;
BEGIN
ins := MVL9_to_char(val);
WRITE(L, ins, justify, field);
END;
-- ----------------------------------------------------------------------------
PROCEDURE DelayValue(
InputTime : IN TIME ;
outline : INOUT LINE
) IS
CONSTANT header : STRING := "TIME'HIGH";
BEGIN
IF(InputTime = TIME'HIGH) THEN
WRITE(outline, header);
ELSE
WRITE(outline, InputTime);
END IF;
END DelayValue;
-- ----------------------------------------------------------------------------
PROCEDURE PrintScheduleDataArray (
ScheduleDataArray : IN VitalMemoryScheduleDataVectorType
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
VARIABLE value : TIME;
CONSTANT empty : STRING := " ";
CONSTANT header1 : STRING := "i Age PropDly RetainDly";
CONSTANT header2 : STRING := "i Sc.Value Output Lastvalue Sc.Time";
BEGIN
WRITE (outline1, empty);
WRITE (outline1, NOW);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITE (outline1, header1);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
FOR i IN ScheduleDataArray'RANGE LOOP
WRITE (outline1, i );
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).InputAge, outline1);
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).PropDelay, outline1);
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).OutputRetainDelay, outline1);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
END LOOP;
WRITE (outline1, header2);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
FOR i IN ScheduleDataArray'RANGE LOOP
WRITE (outline1, i );
WRITE (outline1, empty);
WRITE (outline1, ScheduleDataArray(i).ScheduleValue);
WRITE (outline1, empty);
WRITE (outline1, ScheduleDataArray(i).OutputData);
WRITE (outline1, empty);
WRITE (outline1, ScheduleDataArray(i).LastOutputValue );
WRITE (outline1, empty);
DelayValue(ScheduleDataArray(i).ScheduleTime, outline1);
outline2 := outline1;
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
END LOOP;
WRITE (outline1, empty);
WRITE (outline2, empty);
WRITELINE (LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (Output, outline2);
END IF;
END PrintScheduleDataArray;
-- ----------------------------------------------------------------------------
PROCEDURE PrintArcType (
ArcType : IN VitalMemoryArcType
) IS
VARIABLE outline1, outline2 : LINE;
CONSTANT empty : STRING := " ";
CONSTANT cross : STRING := "CrossArc";
CONSTANT para : STRING := "ParallelArc";
CONSTANT sub : STRING := "SubWordArc";
CONSTANT Header1 : STRING := "Path considered @ ";
CONSTANT Header2 : STRING := " is ";
BEGIN
WRITELINE (LogFile, outline1);
WRITE (outline1, header1);
WRITE (outline1, NOW);
WRITE (outline1, empty);
WRITE (outline1, header2);
WRITE (outline1, empty);
case ArcType is
WHEN CrossArc =>
WRITE (outline1, cross);
WHEN ParallelArc =>
WRITE (outline1, para);
WHEN SubwordArc =>
WRITE (outline1, sub);
END CASE;
outline2 := outline1 ;
-- Appears on STD OUT
IF (PrintDebugMsg = '1') THEN
WRITELINE (Output, outline1);
END IF;
WRITELINE (LogFile, outline2);
END PrintArcType;
-- ----------------------------------------------------------------------------
-- This returns the value picked from the delay array
-- ----------------------------------------------------------------------------
PROCEDURE PrintDelay (
outbitpos : IN INTEGER;
InputArrayLow : IN INTEGER;
InputArrayHigh : IN INTEGER;
debugprop : IN VitalTimeArrayT;
debugretain : IN VitalTimeArrayT
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
VARIABLE outline3 : LINE;
VARIABLE outline4 : LINE;
VARIABLE outline5 : LINE;
VARIABLE outline6 : LINE;
CONSTANT empty : STRING := " ";
CONSTANT empty5 : STRING := " ";
CONSTANT header1 : STRING := "Prop. delays : ";
CONSTANT header2 : STRING := "Retain delays : ";
CONSTANT header3 : STRING := "output bit : ";
BEGIN
WRITE(outline1, header3);
WRITE(outline1, outbitpos);
outline2 := outline1;
WRITELINE(LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE(output, outline2);
END IF;
WRITE(outline1, header1);
WRITE (outline1, empty5);
FOR i IN InputArrayHigh DOWNTO InputArrayLow LOOP
DelayValue(debugprop(i), outline1);
WRITE(outline1, empty);
END LOOP;
outline2 := outline1;
WRITELINE(LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE(output, outline2);
END IF;
WRITE(outline1, header2);
WRITE (outline1, empty5);
FOR i in InputArrayHigh DOWNTO InputArrayLow LOOP
DelayValue(debugretain(i), outline1);
WRITE(outline1, empty);
END LOOP;
outline2 := outline1;
WRITELINE(LogFile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE(output, outline2);
END IF;
END PrintDelay;
-- ----------------------------------------------------------------------------
PROCEDURE DebugMsg1 IS
CONSTANT header1:STRING:= "******************************************";
CONSTANT header2 :STRING:="Entering the process because of an i/p change";
variable outline1, outline2 : LINE;
BEGIN
WRITE(outline1, header1);
outline2 := outline1;
WRITELINE (Logfile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITE(outline1, header2);
outline2 := outline1;
WRITELINE (Logfile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITE(outline1, header1);
outline2 := outline1;
WRITELINE (Logfile, outline1);
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
END DebugMsg1;
-- ----------------------------------------------------------------------------
PROCEDURE ScheduleDebugMsg IS
CONSTANT header1 : STRING := "******************************************";
CONSTANT header2 : STRING := "Finished executing all the procedures";
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
BEGIN
WRITE(outline1, header1);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header2);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header1);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
END ScheduleDebugMsg;
-- ----------------------------------------------------------------------------
PROCEDURE PrintInputName(
InputSignalName : IN STRING
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
CONSTANT header1 : STRING := "***Changing input is ";
CONSTANT header2 : STRING := "(";
CONSTANT header3 : STRING := ")";
CONSTANT header4 : STRING := "****";
CONSTANT header5 : STRING := "******************************************";
CONSTANT header6 : STRING:="Entering the process because of an i/p change";
CONSTANT empty : STRING := " ";
BEGIN
WRITE(outline1, header5);
outline2 := outline1;
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
WRITE(outline1, header6);
outline2 := outline1;
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
WRITE(outline1, header5);
outline2 := outline1;
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
WRITE(outline1, header1);
WRITE(outline1, InputSignalName);
WRITE(outline1, empty);
WRITE(outline1, now);
WRITE(outline1, empty);
WRITE(outline1, header4);
WRITELINE (output, outline1);
WRITELINE (Logfile, outline2);
END PrintInputName;
-- ----------------------------------------------------------------------------
PROCEDURE PrintInputChangeTime(
ChangeTimeArray : IN VitalTimeArrayT
) IS
VARIABLE outline1 : LINE;
VARIABLE outline2 : LINE;
CONSTANT header5 : STRING := "*************************************";
CONSTANT header6 : STRING:="ChangeTime Array : ";
CONSTANT empty : STRING := " ";
BEGIN
WRITE(outline1, header5);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header6);
FOR i in ChangeTimeArray'range LOOP
WRITE(outline1, ChangeTimeArray(i));
WRITE(outline1, empty);
END LOOP;
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
WRITE(outline1, header5);
outline2 := outline1;
IF (PrintDebugMsg = '1') THEN
WRITELINE (output, outline2);
END IF;
WRITELINE (Logfile, outline1);
END PrintInputChangeTime;
-- ----------------------------------------------------------------------------
PROCEDURE PrintInputChangeTime(
ChangeTime : IN Time
) IS
VARIABLE ChangeTimeArray : VitalTimeArrayT(0 DOWNTO 0);
BEGIN
ChangeTimeArray(0) := ChangeTime;
PrintInputChangeTime(ChangeTimeArray);
END PrintInputChangeTime;
-- ----------------------------------------------------------------------------
-- for debug purpose
CONSTANT MaxNoInputBits : INTEGER := 1000;
TYPE VitalMemoryDelayType IS RECORD
PropDelay : TIME;
OutputRetainDelay : TIME;
END RECORD;
-- ----------------------------------------------------------------------------
-- PROCEDURE: IntToStr
--
-- PARAMETERS: InputInt - Integer to be converted to String.
-- ResultStr - String buffer for converted Integer
-- AppendPos - Position in buffer to place result
--
-- DESCRIPTION: This procedure is used to convert an input integer
-- into a string representation. The converted string
-- may be placed at a specific position in the result
-- buffer.
--
-- ----------------------------------------------------------------------------
PROCEDURE IntToStr (
InputInt : IN INTEGER ;
ResultStr : INOUT STRING ( 1 TO 256) ;
AppendPos : INOUT NATURAL
) IS
-- Look-up table. Given an int, we can get the character.
TYPE integer_table_type IS ARRAY (0 TO 9) OF CHARACTER ;
CONSTANT integer_table : integer_table_type :=
('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ;
-- Local variables used in this function.
VARIABLE inpVal : INTEGER := inputInt ;
VARIABLE divisor : INTEGER := 10 ;
VARIABLE tmpStrIndex : INTEGER := 1 ;
VARIABLE tmpStr : STRING ( 1 TO 256 ) ;
BEGIN
IF ( inpVal = 0 ) THEN
tmpStr(tmpStrIndex) := integer_table ( 0 ) ;
tmpStrIndex := tmpStrIndex + 1 ;
ELSE
WHILE ( inpVal > 0 ) LOOP
tmpStr(tmpStrIndex) := integer_table (inpVal mod divisor);
tmpStrIndex := tmpStrIndex + 1 ;
inpVal := inpVal / divisor ;
END LOOP ;
END IF ;
IF (appendPos /= 1 ) THEN
resultStr(appendPos) := ',' ;
appendPos := appendPos + 1 ;
END IF ;
FOR i IN tmpStrIndex-1 DOWNTO 1 LOOP
resultStr(appendPos) := tmpStr(i) ;
appendPos := appendPos + 1 ;
END LOOP ;
END IntToStr ;
-- ----------------------------------------------------------------------------
TYPE CheckType IS (
SetupCheck,
HoldCheck,
RecoveryCheck,
RemovalCheck,
PulseWidCheck,
PeriodCheck
);
TYPE CheckInfoType IS RECORD
Violation : BOOLEAN;
CheckKind : CheckType;
ObsTime : TIME;
ExpTime : TIME;
DetTime : TIME;
State : X01;
END RECORD;
TYPE LogicCvtTableType IS ARRAY (std_ulogic) OF CHARACTER;
TYPE HiLoStrType IS ARRAY (std_ulogic RANGE 'X' TO '1') OF STRING(1 TO 4);
CONSTANT LogicCvtTable : LogicCvtTableType
:= ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
CONSTANT HiLoStr : HiLoStrType := (" X ", " Low", "High" );
TYPE EdgeSymbolMatchType IS ARRAY (X01,X01,VitalEdgeSymbolType) OF BOOLEAN;
-- last value, present value, edge symbol
CONSTANT EdgeSymbolMatch : EdgeSymbolMatchType :=
(
'X' =>
( 'X'=>( OTHERS => FALSE),
'0'=>('N'|'F'|'v'|'E'|'D'|'*' => TRUE, OTHERS => FALSE ),
'1'=>('P'|'R'|'^'|'E'|'A'|'*' => TRUE, OTHERS => FALSE )
),
'0' =>
( 'X'=>( 'r'|'p'|'R'|'A'|'*' => TRUE, OTHERS => FALSE ),
'0'=>( OTHERS => FALSE ),
'1'=>( '/'|'P'|'p'|'R'|'*' => TRUE, OTHERS => FALSE )
),
'1' =>
( 'X'=>( 'f'|'n'|'F'|'D'|'*' => TRUE, OTHERS => FALSE ),
'0'=>( '\'|'N'|'n'|'F'|'*' => TRUE, OTHERS => FALSE ),
'1'=>( OTHERS => FALSE )
)
);
-- ----------------------------------------------------------------------------
FUNCTION Minimum (
CONSTANT t1, t2 : IN TIME
) RETURN TIME IS
BEGIN
IF (t1 < t2) THEN RETURN (t1); ELSE RETURN (t2); END IF;
END Minimum;
-- ----------------------------------------------------------------------------
FUNCTION Maximum (
CONSTANT t1, t2 : IN TIME
) RETURN TIME IS
BEGIN
IF (t1 < t2) THEN RETURN (t2); ELSE RETURN (t1); END IF;
END Maximum;
-- ----------------------------------------------------------------------------
-- FUNCTION: VitalMemoryCalcDelay
-- Description: Select Transition dependent Delay.
-- Used internally by VitalMemorySelectDelay.
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryCalcDelay (
CONSTANT NewVal : IN STD_ULOGIC := 'X';
CONSTANT OldVal : IN STD_ULOGIC := 'X';
CONSTANT Delay : IN VitalDelayType01ZX
) RETURN VitalMemoryDelayType IS
VARIABLE Result : VitalMemoryDelayType;
BEGIN
CASE Oldval IS
WHEN '0' | 'L' =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' =>
Result.PropDelay := Delay(tr01);
WHEN 'Z' =>
Result.PropDelay := Delay(tr0Z);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr01), Delay(tr0Z));
END CASE;
Result.OutputRetainDelay := Delay(tr0X);
WHEN '1' | 'H' =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' =>
Result.PropDelay := Delay(tr01);
WHEN 'Z' =>
Result.PropDelay := Delay(tr1Z);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr10), Delay(tr1Z));
END CASE;
Result.OutputRetainDelay := Delay(tr1X);
WHEN 'Z' =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Delay(trZ0);
WHEN '1' | 'H' =>
Result.PropDelay := Delay(trZ1);
WHEN 'Z' =>
Result.PropDelay := Maximum(Delay(tr1Z), Delay(tr0Z));
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(trZ1), Delay(trZ0));
END CASE;
Result.OutputRetainDelay := Delay(trZX);
WHEN OTHERS =>
CASE Newval IS
WHEN '0' | 'L' =>
Result.PropDelay := Maximum(Delay(tr10), Delay(trZ0));
WHEN '1' | 'H' =>
Result.PropDelay := Maximum(Delay(tr01), Delay(trZ1));
WHEN 'Z' =>
Result.PropDelay := Maximum(Delay(tr1Z), Delay(tr0Z));
WHEN OTHERS =>
Result.PropDelay := Maximum(Delay(tr10), Delay(tr01));
END CASE;
Result.OutputRetainDelay := Minimum(Delay(tr1X), Delay(tr0X));
END CASE;
RETURN Result;
END VitalMemoryCalcDelay;
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryCalcDelay (
CONSTANT NewVal : IN STD_ULOGIC := 'X';
CONSTANT OldVal : IN STD_ULOGIC := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalMemoryDelayType IS
VARIABLE Result : VitalMemoryDelayType;
BEGIN
CASE Oldval IS
WHEN '0' | 'L' =>
CASE Newval IS
WHEN '0' | 'L' => Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' => Result.PropDelay := Delay(tr01);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr01), Delay(tr10));
END CASE;
Result.OutputRetainDelay := Delay(tr0Z);
WHEN '1' | 'H' =>
CASE Newval IS
WHEN '0' | 'L' => Result.PropDelay := Delay(tr10);
WHEN '1' | 'H' => Result.PropDelay := Delay(tr01);
WHEN OTHERS =>
Result.PropDelay := Minimum(Delay(tr10), Delay(tr01));
END CASE;
Result.OutputRetainDelay := Delay(tr1Z);
WHEN OTHERS =>
Result.PropDelay := Maximum(Delay(tr10),Delay(tr01));
Result.OutputRetainDelay := Minimum(Delay(tr1Z),Delay(tr0Z));
END CASE;
RETURN Result;
END VitalMemoryCalcDelay;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryUpdateInputChangeTime (
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
VARIABLE NumBitsPerSubword : INTEGER
) IS
VARIABLE LastInputValue : STD_LOGIC_VECTOR(InputSignal'LENGTH-1 downto 0);
VARIABLE InSignalNorm : STD_LOGIC_VECTOR(InputSignal'LENGTH-1 downto 0);
VARIABLE ChangeTimeNorm : VitalTimeArrayT(InputSignal'LENGTH-1 downto 0);
VARIABLE BitsPerWord : INTEGER;
BEGIN
LastInputValue := InputSignal'LAST_VALUE;
IF NumBitsPerSubword = DefaultNumBitsPerSubword THEN
BitsPerWord := InputSignal'LENGTH;
ELSE
BitsPerWord := NumBitsPerSubword;
END IF;
FOR i IN InSignalNorm'RANGE LOOP
IF (InSignalNorm(i) /= LastInputValue(i)) THEN
ChangeTimeNorm(i/BitsPerWord) := NOW - InputSignal'LAST_EVENT;
ELSE
ChangeTimeNorm(i/BitsPerWord) := InputChangeTimeArray(i);
END IF;
END LOOP;
FOR i IN ChangeTimeNorm'RANGE LOOP
ChangeTimeNorm(i) := ChangeTimeNorm(i/BitsPerword);
END LOOP;
InputChangeTimeArray := ChangeTimeNorm;
-- for debug purpose only
PrintInputChangeTime(InputChangeTimeArray);
END VitalMemoryUpdateInputChangeTime;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryUpdateInputChangeTime
-- Description: Time since previous event for each bit of the input
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryUpdateInputChangeTime (
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR
) IS
VARIABLE LastInputValue : STD_LOGIC_VECTOR(InputSignal'RANGE) ;
BEGIN
LastInputValue := InputSignal'LAST_VALUE;
FOR i IN InputSignal'RANGE LOOP
IF (InputSignal(i) /= LastInputValue(i)) THEN
InputChangeTimeArray(i) := NOW - InputSignal'LAST_EVENT;
END IF;
END LOOP;
-- for debug purpose only
PrintInputChangeTime(InputChangeTimeArray);
END VitalMemoryUpdateInputChangeTime;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryUpdateInputChangeTime (
VARIABLE InputChangeTime : INOUT TIME;
SIGNAL InputSignal : IN STD_ULOGIC
) IS
BEGIN
InputChangeTime := NOW - InputSignal'LAST_EVENT;
-- for debug purpose only
PrintInputChangeTime(InputChangeTime);
END VitalMemoryUpdateInputChangeTime;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryExpandPortFlag (
CONSTANT PortFlag : IN VitalPortFlagVectorType;
CONSTANT NumBitsPerSubword : IN INTEGER;
VARIABLE ExpandedPortFlag : OUT VitalPortFlagVectorType
) IS
VARIABLE PortFlagNorm : VitalPortFlagVectorType(
PortFlag'LENGTH-1 downto 0) := PortFlag;
VARIABLE ExpandedPortFlagNorm : VitalPortFlagVectorType(
ExpandedPortFlag'LENGTH-1 downto 0);
VARIABLE SubwordIndex : INTEGER;
BEGIN
FOR Index IN INTEGER RANGE 0 to ExpandedPortFlag'LENGTH-1 LOOP
IF NumBitsPerSubword = DefaultNumBitsPerSubword THEN
SubwordIndex := 0;
ELSE
SubwordIndex := Index / NumBitsPerSubword;
END IF;
ExpandedPortFlagNorm(Index) := PortFlagNorm(SubWordIndex);
END LOOP;
ExpandedPortFlag := ExpandedPortFlagNorm;
END VitalMemoryExpandPortFlag;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemorySelectDelay
-- Description : Select Propagation Delay. Used internally by
-- VitalMemoryAddPathDelay.
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType01ZX
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN
) IS
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE CurRetainDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0):=InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType01ZX(
PathDelayArray'LENGTH-1 downto 0):= PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0):= ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW) AND
(OutputRetainFlag = FALSE ));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
RetainDelay:=ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH - 1 ;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
(CurPropDelay,CurRetainDelay) :=
VitalMemoryCalcDelay (
NewValue, OldValue, DelayArrayNorm(DelayArrayIndex)
);
IF (OutputRetainFlag = FALSE) THEN
CurRetainDelay := TIME'HIGH;
END IF;
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := CurRetainDelay;
IF ArcType = CrossArc THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns)THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge)THEN
PropDelay := CurPropDelay;
RetainDelay := CurRetainDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge)THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
IF (OutputRetainFlag = TRUE) THEN
IF (CurRetainDelay < RetainDelay) THEN
RetainDelay := CurRetainDelay;
END IF;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay:= RetainDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos,InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType01Z
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN
) IS
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE CurRetainDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0):=InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType01Z(
PathDelayArray'LENGTH-1 downto 0):= PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0):=ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW) AND
(OutputRetainFlag = FALSE));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
RetainDelay:=ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH-1;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
(CurPropDelay, CurRetainDelay) :=
VitalMemoryCalcDelay (
NewValue, OldValue, DelayArrayNorm(DelayArrayIndex)
);
IF (OutputRetainFlag = FALSE) THEN
CurRetainDelay := TIME'HIGH;
END IF;
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := CurRetainDelay;
IF (ArcType = CrossArc) THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns) THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge) THEN
PropDelay := CurPropDelay;
RetainDelay := CurRetainDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge) THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
IF (OutputRetainFlag = TRUE) THEN
IF (CurRetainDelay < RetainDelay) THEN
RetainDelay := CurRetainDelay;
END IF;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).OutputRetainDelay:= RetainDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos, InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType01
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE CurPathDelay : VitalMemoryDelayType;
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0):= InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType01(
PathDelayArray'LENGTH-1 downto 0):= PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0):=ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH-1;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
CurPropDelay:= VitalCalcDelay (NewValue,
OldValue, DelayArrayNorm(DelayArrayIndex));
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := TIME'HIGH;
IF (ArcType = CrossArc) THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns) THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge) THEN
PropDelay := CurPropDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge) THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos, InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- VitalDelayArrayType
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySelectDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE InputChangeTimeArray : IN VitalTimeArrayT;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE InputArrayLow : INTEGER := 0;
VARIABLE InputArrayHigh : INTEGER := 0;
VARIABLE DelayArrayIndex : INTEGER := 0;
VARIABLE NumBitsPerSubWord : INTEGER := DefaultNumBitsPerSubword;
VARIABLE NewValue : STD_ULOGIC;
VARIABLE OldValue : STD_ULOGIC;
VARIABLE OutputLength : INTEGER := 0;
VARIABLE OutArrayIndex : INTEGER;
VARIABLE PropDelay : TIME;
VARIABLE CurPropDelay : TIME;
VARIABLE InputAge : TIME;
VARIABLE CurInputAge : TIME;
VARIABLE InputChangeTimeNorm : VitalTimeArrayT(
InputChangeTimeArray'LENGTH-1 downto 0) := InputChangeTimeArray;
VARIABLE DelayArrayNorm : VitalDelayArrayType(
PathDelayArray'LENGTH-1 downto 0) := PathDelayArray;
VARIABLE ScheduleDataArrayNorm : VitalMemoryScheduleDatavectorType
(ScheduleDataArray'LENGTH-1 downto 0) := ScheduleDataArray;
-- for debug purpose
VARIABLE debugprop : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
VARIABLE debugretain : VitalTimeArrayT(MaxNoInputBits-1 downto 0);
BEGIN
-- for debug purpose
PrintArcType(ArcType);
OutputLength := ScheduleDataArray'LENGTH;
FOR OutBitPos IN 0 to (OutputLength -1) LOOP
NEXT WHEN PathConditionArray(OutBitPos) = FALSE;
NEXT WHEN ((ScheduleDataArrayNorm(OutBitPos).ScheduleValue
= ScheduleDataArrayNorm(OutBitPos).OutputData) AND
(ScheduleDataArrayNorm(OutBitPos).ScheduleTime <= NOW));
NewValue := ScheduleDataArrayNorm(OutBitPos).OutputData;
OldValue := ScheduleDataArrayNorm(OutBitPos).LastOutputValue;
PropDelay :=ScheduleDataArrayNorm(OutBitPos).PropDelay;
InputAge := ScheduleDataArrayNorm(OutBitPos).InputAge;
NumBitsPerSubWord:=ScheduleDataArrayNorm(OutBitPos).NumBitsPerSubWord;
CASE ArcType IS
WHEN ParallelArc =>
InputArrayLow := OutBitPos;
InputArrayHigh := OutBitPos;
DelayArrayIndex := OutBitPos;
WHEN CrossArc =>
InputArrayLow := 0;
InputArrayHigh := InputChangeTimeArray'LENGTH-1;
DelayArrayIndex := OutBitPos;
WHEN SubwordArc =>
InputArrayLow := OutBitPos / NumBitsPerSubWord;
InputArrayHigh := OutBitPos / NumBitsPerSubWord;
DelayArrayIndex := OutBitPos +
(OutputLength * (OutBitPos / NumBitsPerSubWord));
END CASE;
FOR i IN InputArrayLow TO InputArrayHigh LOOP
CurPropDelay := VitalCalcDelay (NewValue,
OldValue, DelayArrayNorm(DelayArrayIndex));
-- for debug purpose
debugprop(i) := CurPropDelay;
debugretain(i) := TIME'HIGH;
IF (ArcType = CrossArc) THEN
DelayArrayIndex := DelayArrayIndex + OutputLength;
END IF;
-- If there is one input change at a time, then choose the
-- delay from that input. If there is simultaneous input
-- change, then choose the minimum of propagation delays
IF (InputChangeTimeNorm(i) < 0 ns) THEN
CurInputAge := TIME'HIGH;
ELSE
CurInputAge := NOW - InputChangeTimeNorm(i);
END IF;
IF (CurInputAge < InputAge) THEN
PropDelay := CurPropDelay;
InputAge := CurInputAge;
ELSIF (CurInputAge = InputAge) THEN
IF (CurPropDelay < PropDelay) THEN
PropDelay := CurPropDelay;
END IF;
END IF;
END LOOP;
-- Store it back to data strucutre
ScheduleDataArrayNorm(OutBitPos).PropDelay := PropDelay;
ScheduleDataArrayNorm(OutBitPos).InputAge := InputAge;
-- for debug purpose
PrintDelay(outbitPos, InputArrayLow, InputArrayHigh,
debugprop, debugretain);
END LOOP;
ScheduleDataArray := ScheduleDataArrayNorm;
END VitalMemorySelectDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryInitPathDelay
-- Description: To initialize Schedule Data structure for an
-- output.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
VARIABLE OutputDataArray : IN STD_LOGIC_VECTOR;
CONSTANT NumBitsPerSubWord : IN INTEGER := DefaultNumBitsPerSubword
) IS
BEGIN
-- Initialize the ScheduleData Structure.
FOR i IN OutputDataArray'RANGE LOOP
ScheduleDataArray(i).OutputData := OutputDataArray(i);
ScheduleDataArray(i).PropDelay := TIME'HIGH;
ScheduleDataArray(i).OutputRetainDelay := TIME'HIGH;
ScheduleDataArray(i).InputAge := TIME'HIGH;
ScheduleDataArray(i).NumBitsPerSubWord := NumBitsPerSubWord;
-- Update LastOutputValue of Output if the Output has
-- already been scheduled.
IF ((ScheduleDataArray(i).ScheduleValue /= OutputDataArray(i)) AND
(ScheduleDataArray(i).ScheduleTime <= NOW)) THEN
ScheduleDataArray(i).LastOutputValue
:= ScheduleDataArray(i).ScheduleValue;
END IF;
END LOOP;
-- for debug purpose
DebugMsg1;
PrintScheduleDataArray(ScheduleDataArray);
END VitalMemoryInitPathDelay;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryInitPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
VARIABLE OutputData : IN STD_ULOGIC
) IS
VARIABLE ScheduledataArray: VitalMemoryScheduleDataVectorType
(0 downto 0);
VARIABLE OutputDataArray : STD_LOGIC_VECTOR(0 downto 0);
BEGIN
ScheduledataArray(0) := ScheduleData;
OutputDataArray(0) := OutputData;
VitalMemoryInitPathDelay (
ScheduleDataArray => ScheduleDataArray,
OutputDataArray => OutputDataArray,
NumBitsPerSubWord => DefaultNumBitsPerSubword
);
-- for debug purpose
DebugMsg1;
PrintScheduleDataArray( ScheduleDataArray);
END VitalMemoryInitPathDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryAddPathDelay
-- Description: Declare a path for one scalar/vector input to
-- the output for which Schedule Data has been
-- initialized previously.
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- #1
-- DelayType - VitalMemoryDelayType
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #2
-- DelayType - VitalMemoryDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray
);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #3
-- DelayType - VitalMemoryDelayType
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR Mem400
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #4
-- DelayType - VitalMemoryDelayType
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE ScheduleDataArray : VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #5
-- DelayType - VitalMemoryDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #6
-- DelayType - VitalMemoryDelayType
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #7
-- DelayType - VitalMemoryDelayType01
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType01(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #8
-- DelayType - VitalMemoryDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #9
-- DelayType - VitalMemoryDelayType01
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #10
-- DelayType - VitalMemoryDelayType01
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray: INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
)IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #11
-- DelayType - VitalMemoryDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE
) IS
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #12
-- DelayType - VitalMemoryDelayType01
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #13
-- DelayType - VitalMemoryDelayType01Z
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType01Z(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #14
-- DelayType - VitalMemoryDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #15
-- DelayType - VitalMemoryDelayType01Z
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm : VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0);
VARIABLE PathConditionArrayExp : VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword := ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #16
-- DelayType - VitalMemoryDelayType01Z
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
NumBitsPerSubword := ScheduleDataArray(0).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray,
InputSignal,
NumBitsPerSubword
);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #17
-- DelayType - VitalMemoryDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray,
InputSignal,
NumBitsPerSubword
);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #18
-- DelayType - VitalMemoryDelayType01Z
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01Z;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0);
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword := ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #19
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Scalar
-- Output - Scalar
-- Delay - Scalar
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelay : IN VitalDelayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE PathDelayArray : VitalDelayArrayType01ZX(0 downto 0);
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
PathDelayArray(0) := PathDelay;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #20
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray :INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #21
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Scalar
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray :INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_ULOGIC;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTime : INOUT TIME;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray: IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE
) IS
VARIABLE InputChangeTimeArray : VitalTimeArrayT(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
VitalMemoryUpdateInputChangeTime(InputChangeTime, InputSignal);
InputChangeTimeArray(0) := InputChangeTime;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #22
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Vector
-- Output - Scalar
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE ScheduleDataArray :
VitalMemoryScheduleDataVectorType(0 downto 0);
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray : VitalBoolArrayT(0 downto 0);
BEGIN
PathConditionArray(0) := PathCondition;
ScheduleDataArray(0) := ScheduleData;
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #23
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Scalar
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathCondition : IN BOOLEAN := TRUE;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArray :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
FOR i IN PathConditionArray'RANGE LOOP
PathConditionArray(i) := PathCondition;
END LOOP;
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArray, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- #24
-- DelayType - VitalMemoryDelayType01XZ
-- Input - Vector
-- Output - Vector
-- Delay - Vector
-- Condition - Vector
PROCEDURE VitalMemoryAddPathDelay (
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType;
SIGNAL InputSignal : IN STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
VARIABLE InputChangeTimeArray : INOUT VitalTimeArrayT;
CONSTANT PathDelayArray : IN VitalDelayArrayType01ZX;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT PathConditionArray : IN VitalBoolArrayT;
CONSTANT OutputRetainFlag : IN BOOLEAN := FALSE;
CONSTANT OutputRetainBehavior : IN OutputRetainBehaviorType := BitCorrupt
) IS
VARIABLE NumBitsPerSubword : INTEGER;
VARIABLE PathConditionArrayNorm :
VitalBoolArrayT(PathConditionArray'LENGTH-1 downto 0) := PathConditionArray; -- IR MEM400;
VARIABLE PathConditionArrayExp :
VitalBoolArrayT(ScheduleDataArray'LENGTH-1 downto 0);
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'RIGHT).NumBitsPerSubword;
FOR i IN PathConditionArrayExp'RANGE LOOP
PathConditionArrayExp(i) := PathConditionArrayNorm(i/NumBitsPerSubword);
END LOOP;
IF (OutputRetainBehavior = WordCorrupt AND
ArcType = ParallelArc AND
OutputRetainFlag = TRUE) THEN
VitalMemoryUpdateInputChangeTime(
InputChangeTimeArray, InputSignal,
NumBitsPerSubword);
ELSE
VitalMemoryUpdateInputChangeTime(InputChangeTimeArray, InputSignal);
END IF;
VitalMemorySelectDelay(
ScheduleDataArray, InputChangeTimeArray,
OutputSignalName, PathDelayArray,
ArcType, PathConditionArrayExp, OutputRetainFlag);
END VitalMemoryAddPathDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemorySchedulePathDelay
-- Description: Schedule Output after Propagation Delay selected
-- by checking all the paths added thru'
-- VitalMemoryAddPathDelay.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType:= VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
) IS
VARIABLE Age : TIME;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE Data : STD_ULOGIC;
BEGIN
IF (PortFlag.OutputDisable /= TRUE) THEN
FOR i IN ScheduleDataArray'RANGE LOOP
PropDelay := ScheduleDataArray(i).PropDelay;
RetainDelay := ScheduleDataArray(i).OutputRetainDelay;
NEXT WHEN PropDelay = TIME'HIGH;
Age := ScheduleDataArray(i).InputAge;
Data := ScheduleDataArray(i).OutputData;
IF (Age < RetainDelay and RetainDelay < PropDelay) THEN
OutSignal(i) <= TRANSPORT 'X' AFTER (RetainDelay - Age);
END IF;
IF (Age <= PropDelay) THEN
OutSignal(i)<= TRANSPORT OutputMap(Data)AFTER (PropDelay-Age);
ScheduleDataArray(i).ScheduleValue := Data;
ScheduleDataArray(i).ScheduleTime := NOW + PropDelay - Age;
END IF;
END LOOP;
END IF;
-- for debug purpose
PrintScheduleDataArray(ScheduleDataArray);
-- for debug purpose
ScheduleDebugMsg;
END VitalMemorySchedulePathDelay;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemorySchedulePathDelay
-- Description: Schedule Output after Propagation Delay selected
-- by checking all the paths added thru'
-- VitalMemoryAddPathDelay.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT STD_LOGIC_VECTOR;
CONSTANT OutputSignalName : IN STRING :="";
CONSTANT PortFlag : IN VitalPortFlagVectorType;
CONSTANT OutputMap : IN VitalOutputMapType:= VitalDefaultOutputMap;
VARIABLE ScheduleDataArray : INOUT VitalMemoryScheduleDataVectorType
) IS
VARIABLE Age : TIME;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE Data : STD_ULOGIC;
VARIABLE ExpandedPortFlag :
VitalPortFlagVectorType(ScheduleDataArray'RANGE);
VARIABLE NumBitsPerSubword : INTEGER;
BEGIN
NumBitsPerSubword :=
ScheduleDataArray(ScheduleDataArray'LEFT).NumBitsPerSubword;
VitalMemoryExpandPortFlag( PortFlag, NumBitsPerSubword, ExpandedPortFlag );
FOR i IN ScheduleDataArray'RANGE LOOP
NEXT WHEN ExpandedPortFlag(i).OutputDisable = TRUE;
PropDelay := ScheduleDataArray(i).PropDelay;
RetainDelay := ScheduleDataArray(i).OutputRetainDelay;
NEXT WHEN PropDelay = TIME'HIGH;
Age := ScheduleDataArray(i).InputAge;
Data := ScheduleDataArray(i).OutputData;
IF (Age < RetainDelay and RetainDelay < PropDelay) THEN
OutSignal(i) <= TRANSPORT 'X' AFTER (RetainDelay - Age);
END IF;
IF (Age <= PropDelay) THEN
OutSignal(i)<= TRANSPORT OutputMap(Data)AFTER (PropDelay-Age);
ScheduleDataArray(i).ScheduleValue := Data;
ScheduleDataArray(i).ScheduleTime := NOW + PropDelay - Age;
END IF;
END LOOP;
-- for debug purpose
PrintScheduleDataArray(ScheduleDataArray);
-- for debug purpose
ScheduleDebugMsg;
END VitalMemorySchedulePathDelay;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySchedulePathDelay (
SIGNAL OutSignal : OUT STD_ULOGIC;
CONSTANT OutputSignalName: IN STRING :="";
CONSTANT PortFlag : IN VitalPortFlagType := VitalDefaultPortFlag;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
VARIABLE ScheduleData : INOUT VitalMemoryScheduleDataType
) IS
VARIABLE Age : TIME;
VARIABLE PropDelay : TIME;
VARIABLE RetainDelay : TIME;
VARIABLE Data : STD_ULOGIC;
VARIABLE ScheduleDataArray : VitalMemoryScheduleDataVectorType (0 downto 0);
BEGIN
IF (PortFlag.OutputDisable /= TRUE) THEN
ScheduledataArray(0) := ScheduleData;
PropDelay := ScheduleDataArray(0).PropDelay;
RetainDelay := ScheduleDataArray(0).OutputRetainDelay;
Age := ScheduleDataArray(0).InputAge;
Data := ScheduleDataArray(0).OutputData;
IF (Age < RetainDelay and RetainDelay < PropDelay) THEN
OutSignal <= TRANSPORT 'X' AFTER (RetainDelay - Age);
END IF;
IF (Age <= PropDelay and PropDelay /= TIME'HIGH) THEN
OutSignal <= TRANSPORT OutputMap(Data) AFTER (PropDelay - Age);
ScheduleDataArray(0).ScheduleValue := Data;
ScheduleDataArray(0).ScheduleTime := NOW + PropDelay - Age;
END IF;
END IF;
-- for debug purpose
PrintScheduleDataArray(ScheduleDataArray);
-- for debug purpose
ScheduleDebugMsg;
END VitalMemorySchedulePathDelay;
-- ----------------------------------------------------------------------------
-- Procedure : InternalTimingCheck
-- ----------------------------------------------------------------------------
PROCEDURE InternalTimingCheck (
CONSTANT TestSignal : IN std_ulogic;
CONSTANT RefSignal : IN std_ulogic;
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
VARIABLE RefTime : IN TIME;
VARIABLE RefEdge : IN BOOLEAN;
VARIABLE TestTime : IN TIME;
VARIABLE TestEvent : IN BOOLEAN;
VARIABLE SetupEn : INOUT BOOLEAN;
VARIABLE HoldEn : INOUT BOOLEAN;
VARIABLE CheckInfo : INOUT CheckInfoType;
CONSTANT MsgOn : IN BOOLEAN
) IS
VARIABLE bias : TIME;
VARIABLE actualObsTime : TIME;
VARIABLE BC : TIME;
VARIABLE Message :LINE;
BEGIN
-- Check SETUP constraint
IF (RefEdge) THEN
IF (SetupEn) THEN
CheckInfo.ObsTime := RefTime - TestTime;
CheckInfo.State := To_X01(TestSignal);
CASE CheckInfo.State IS
WHEN '0' =>
CheckInfo.ExpTime := SetupLow;
-- start of new code IR245-246
BC := HoldHigh;
-- end of new code IR245-246
WHEN '1' =>
CheckInfo.ExpTime := SetupHigh;
-- start of new code IR245-246
BC := HoldLow;
-- end of new code IR245-246
WHEN 'X' =>
CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow);
-- start of new code IR245-246
BC := Maximum(HoldHigh,HoldLow);
-- end of new code IR245-246
END CASE;
-- added the second condition for IR 245-246
CheckInfo.Violation :=
((CheckInfo.ObsTime < CheckInfo.ExpTime)
AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns))));
-- start of new code IR245-246
IF (CheckInfo.ExpTime = 0 ns) THEN
CheckInfo.CheckKind := HoldCheck;
ELSE
CheckInfo.CheckKind := SetupCheck;
END IF;
-- end of new code IR245-246
SetupEn := FALSE;
ELSE
CheckInfo.Violation := FALSE;
END IF;
-- Check HOLD constraint
ELSIF (TestEvent) THEN
IF HoldEn THEN
CheckInfo.ObsTime := TestTime - RefTime;
CheckInfo.State := To_X01(TestSignal);
CASE CheckInfo.State IS
WHEN '0' =>
CheckInfo.ExpTime := HoldHigh;
-- new code for unnamed IR
CheckInfo.State := '1';
-- start of new code IR245-246
BC := SetupLow;
-- end of new code IR245-246
WHEN '1' =>
CheckInfo.ExpTime := HoldLow;
-- new code for unnamed IR
CheckInfo.State := '0';
-- start of new code IR245-246
BC := SetupHigh;
-- end of new code IR245-246
WHEN 'X' =>
CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow);
-- start of new code IR245-246
BC := Maximum(SetupHigh,SetupLow);
-- end of new code IR245-246
END CASE;
-- added the second condition for IR 245-246
CheckInfo.Violation :=
((CheckInfo.ObsTime < CheckInfo.ExpTime)
AND ( NOT ((CheckInfo.ObsTime = BC) and (BC = 0 ns))));
-- start of new code IR245-246
IF (CheckInfo.ExpTime = 0 ns) THEN
CheckInfo.CheckKind := SetupCheck;
ELSE
CheckInfo.CheckKind := HoldCheck;
END IF;
-- end of new code IR245-246
HoldEn := NOT CheckInfo.Violation;
ELSE
CheckInfo.Violation := FALSE;
END IF;
ELSE
CheckInfo.Violation := FALSE;
END IF;
-- Adjust report values to account for internal model delays
-- Note: TestDelay, RefDelay, TestTime, RefTime are non-negative
-- Note: bias may be negative or positive
IF MsgOn AND CheckInfo.Violation THEN
-- modified the code for correct reporting of violation in case of
-- order of signals being reversed because of internal delays
-- new variable
actualObsTime := (TestTime-TestDelay)-(RefTime-RefDelay);
bias := TestDelay - RefDelay;
IF (actualObsTime < 0 ns) THEN -- It should be a setup check
IF ( CheckInfo.CheckKind = HoldCheck) THEN
CheckInfo.CheckKind := SetupCheck;
CASE CheckInfo.State IS
WHEN '0' => CheckInfo.ExpTime := SetupLow;
WHEN '1' => CheckInfo.ExpTime := SetupHigh;
WHEN 'X' => CheckInfo.ExpTime := Maximum(SetupHigh,SetupLow);
END CASE;
END IF;
CheckInfo.ObsTime := -actualObsTime;
CheckInfo.ExpTime := CheckInfo.ExpTime + bias;
CheckInfo.DetTime := RefTime - RefDelay;
ELSE -- It should be a hold check
IF (CheckInfo.CheckKind = SetupCheck) THEN
CheckInfo.CheckKind := HoldCheck;
CASE CheckInfo.State IS
WHEN '0' =>
CheckInfo.ExpTime := HoldHigh;
CheckInfo.State := '1';
WHEN '1' =>
CheckInfo.ExpTime := HoldLow;
CheckInfo.State := '0';
WHEN 'X' =>
CheckInfo.ExpTime := Maximum(HoldHigh,HoldLow);
END CASE;
END IF;
CheckInfo.ObsTime := actualObsTime;
CheckInfo.ExpTime := CheckInfo.ExpTime - bias;
CheckInfo.DetTime := TestTime - TestDelay;
END IF;
END IF;
END InternalTimingCheck;
-- ----------------------------------------------------------------------------
-- Setup and Hold Time Check Routine
-- ----------------------------------------------------------------------------
PROCEDURE TimingArrayIndex (
SIGNAL InputSignal : IN Std_logic_vector;
CONSTANT ArrayIndexNorm : IN INTEGER;
VARIABLE Index : OUT INTEGER
) IS
BEGIN
IF (InputSignal'LEFT > InputSignal'RIGHT) THEN
Index := ArrayIndexNorm + InputSignal'RIGHT;
ELSE
Index := InputSignal'RIGHT - ArrayIndexNorm;
END IF;
END TimingArrayIndex;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
IF (NOT CheckInfo.Violation) THEN
RETURN;
END IF;
Write ( Message, HeaderMsg );
CASE CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN RecoveryCheck => Write ( Message, STRING'(" RECOVERY ") );
WHEN RemovalCheck => Write ( Message, STRING'(" REMOVAL ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END VitalMemoryReportViolation;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT TestArrayIndex : IN INTEGER;
CONSTANT RefArrayIndex : IN INTEGER;
SIGNAL TestSignal : IN std_logic_vector;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
VARIABLE i, j : INTEGER;
BEGIN
IF (NOT CheckInfo.Violation) THEN
RETURN;
END IF;
Write ( Message, HeaderMsg );
CASE CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
WHEN OTHERS => Write ( Message, STRING'(" UNKNOWN ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
TimingArrayIndex(TestSignal, TestArrayIndex, i);
CASE MsgFormat IS
WHEN Scalar =>
NULL;
WHEN VectorEnum =>
Write ( Message, '_');
Write ( Message, i);
WHEN Vector =>
Write ( Message, '(');
Write ( Message, i);
Write ( Message, ')');
END CASE;
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
IF(RefSignal'LENGTH > 0) THEN
TimingArrayIndex(RefSignal, RefArrayIndex, j);
CASE MsgFormat IS
WHEN Scalar =>
NULL;
WHEN VectorEnum =>
Write ( Message, '_');
Write ( Message, j);
WHEN Vector =>
Write ( Message, '(');
Write ( Message, j);
Write ( Message, ')');
END CASE;
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END VitalMemoryReportViolation;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryReportViolation (
CONSTANT TestSignalName : IN STRING := "";
CONSTANT RefSignalName : IN STRING := "";
CONSTANT TestArrayIndex : IN INTEGER;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT CheckInfo : IN CheckInfoType;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
IF (NOT CheckInfo.Violation) THEN
RETURN;
END IF;
Write ( Message, HeaderMsg );
CASE CheckInfo.CheckKind IS
WHEN SetupCheck => Write ( Message, STRING'(" SETUP ") );
WHEN HoldCheck => Write ( Message, STRING'(" HOLD ") );
WHEN PulseWidCheck => Write ( Message, STRING'(" PULSE WIDTH "));
WHEN PeriodCheck => Write ( Message, STRING'(" PERIOD ") );
WHEN OTHERS => Write ( Message, STRING'(" UNKNOWN ") );
END CASE;
Write ( Message, HiLoStr(CheckInfo.State) );
Write ( Message, STRING'(" VIOLATION ON ") );
Write ( Message, TestSignalName );
CASE MsgFormat IS
WHEN Scalar =>
NULL;
WHEN VectorEnum =>
Write ( Message, '_');
Write ( Message, TestArrayIndex);
WHEN Vector =>
Write ( Message, '(');
Write ( Message, TestArrayIndex);
Write ( Message, ')');
END CASE;
IF (RefSignalName'LENGTH > 0) THEN
Write ( Message, STRING'(" WITH RESPECT TO ") );
Write ( Message, RefSignalName );
END IF;
Write ( Message, ';' & LF );
Write ( Message, STRING'(" Expected := ") );
Write ( Message, CheckInfo.ExpTime);
Write ( Message, STRING'("; Observed := ") );
Write ( Message, CheckInfo.ObsTime);
Write ( Message, STRING'("; At : ") );
Write ( Message, CheckInfo.DetTime);
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END VitalMemoryReportViolation;
-- ----------------------------------------------------------------------------
FUNCTION VitalMemoryTimingDataInit
RETURN VitalMemoryTimingDataType IS
BEGIN
RETURN (FALSE, 'X', 0 ns, FALSE, 'X', 0 ns, FALSE,
NULL, NULL, NULL, NULL, NULL, NULL);
END;
-- ----------------------------------------------------------------------------
-- Procedure: VitalSetupHoldCheck
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayType;
CONSTANT SetupLow : IN VitalDelayType;
CONSTANT HoldHigh : IN VitalDelayType;
CONSTANT HoldLow : IN VitalDelayType;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE CheckEnScalar : BOOLEAN := FALSE;
VARIABLE ViolationInt : X01ArrayT(CheckEnabled'RANGE);
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : BOOLEAN;
VARIABLE TestDly : TIME := Maximum(0 ns, TestDelay);
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLast := To_X01(TestSignal);
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF (RefEdge) THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
TimingData.SetupEn := TimingData.SetupEn AND EnableSetupOnRef;
TimingData.HoldEn := EnableHoldOnRef;
END IF;
-- Detect test (data) changes and record the time of the last change
TestEvent := TimingData.TestLast /= To_X01Z(TestSignal);
TimingData.TestLast := To_X01Z(TestSignal);
IF TestEvent THEN
TimingData.SetupEn := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEn := TimingData.HoldEn AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTime := NOW;
END IF;
FOR i IN CheckEnabled'RANGE LOOP
IF CheckEnabled(i) = TRUE THEN
CheckEnScalar := TRUE;
END IF;
ViolationInt(i) := '0';
END LOOP;
IF (CheckEnScalar) THEN
InternalTimingCheck (
TestSignal => TestSignal,
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh,
SetupLow => SetupLow,
HoldHigh => HoldHigh,
HoldLow => HoldLow,
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTime,
TestEvent => TestEvent,
SetupEn => TimingData.SetupEn,
HoldEn => TimingData.HoldEn,
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName,
HeaderMsg, CheckInfo, MsgSeverity );
END IF;
IF (XOn) THEN
FOR i IN CheckEnabled'RANGE LOOP
IF CheckEnabled(i) = TRUE THEN
ViolationInt(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END IF;
Violation := ViolationInt;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF (RefEdge) THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
FOR i IN TestSignal'RANGE LOOP
TimingData.SetupEnA(i)
:= TimingData.SetupEnA(i) AND EnableSetupOnRef;
TimingData.HoldEnA(i) := EnableHoldOnRef;
END LOOP;
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTimeA(i) := NOW;
--TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
FOR i IN TestSignal'RANGE LOOP
Violation(i) := '0';
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelay(i));
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh(i),
SetupLow => SetupLow(i),
HoldHigh => HoldHigh(i),
HoldLow => HoldLow(i),
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i ,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
Violation(i) := 'X';
END IF;
END IF;
END IF;
END LOOP;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE ViolationInt : X01ArrayT(TestSignal'RANGE);
VARIABLE ViolationIntNorm: X01ArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE ViolationNorm : X01ArrayT(Violation'LENGTH-1 downto 0);
VARIABLE CheckEnInt : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE CheckEnIntNorm : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE CheckEnScalar : BOOLEAN := FALSE; --Mem IR 401
VARIABLE CheckEnabledNorm: VitalBoolArrayT(CheckEnabled'LENGTH-1 downto 0);
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF RefEdge THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
FOR i IN TestSignal'RANGE LOOP
TimingData.SetupEnA(i)
:= TimingData.SetupEnA(i) AND EnableSetupOnRef;
TimingData.HoldEnA(i) := EnableHoldOnRef;
END LOOP;
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTimeA(i) := NOW;
--TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
IF ArcType = CrossArc THEN
CheckEnScalar := FALSE;
FOR i IN CheckEnabled'RANGE LOOP
IF CheckEnabled(i) = TRUE THEN
CheckEnScalar := TRUE;
END IF;
END LOOP;
FOR i IN CheckEnInt'RANGE LOOP
CheckEnInt(i) := CheckEnScalar;
END LOOP;
ELSE
FOR i IN CheckEnIntNorm'RANGE LOOP
CheckEnIntNorm(i) := CheckEnabledNorm(i / NumBitsPerSubWord );
END LOOP;
CheckEnInt := CheckEnIntNorm;
END IF;
FOR i IN TestSignal'RANGE LOOP
ViolationInt(i) := '0';
IF (CheckEnInt(i)) THEN
TestDly := Maximum(0 ns, TestDelay(i));
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh(i),
SetupLow => SetupLow(i),
HoldHigh => HoldHigh(i),
HoldLow => HoldLow(i),
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i ,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
ViolationInt(i) := 'X';
END IF;
END IF;
END IF;
END LOOP;
IF (ViolationInt'LENGTH = Violation'LENGTH) THEN
Violation := ViolationInt;
ELSE
ViolationIntNorm := ViolationInt;
FOR i IN ViolationNorm'RANGE LOOP
ViolationNorm(i) := '0';
END LOOP;
FOR i IN ViolationIntNorm'RANGE LOOP
IF (ViolationIntNorm(i) = 'X') THEN
ViolationNorm(i / NumBitsPerSubWord) := 'X';
END IF;
END LOOP;
Violation := ViolationNorm;
END IF;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArraytype;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0);
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME;
VARIABLE bias : TIME;
VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH;
VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH;
VARIABLE NumChecks : NATURAL;
VARIABLE ViolationTest : X01ArrayT(NumTestBits-1 downto 0);
VARIABLE ViolationRef : X01ArrayT(NumRefBits-1 downto 0);
VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0)
:= TestSignal;
VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0)
:= TestDelay;
VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0)
:= RefSignal;
VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0)
:= RefDelay;
VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0)
:= SetupHigh;
VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0)
:= SetupLow;
VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0)
:= HoldHigh;
VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0)
:= HoldLow;
VARIABLE RefBitLow : NATURAL;
VARIABLE RefBitHigh : NATURAL;
VARIABLE EnArrayIndex : NATURAL;
VARIABLE TimingArrayIndex: NATURAL;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0);
TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0);
TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0);
TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0);
IF (ArcType = CrossArc) THEN
NumChecks := RefSignal'LENGTH * TestSignal'LENGTH;
ELSE
NumChecks := TestSignal'LENGTH;
END IF;
TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
FOR i IN TestSignalNorm'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignalNorm(i));
END LOOP;
FOR i IN RefSignalNorm'RANGE LOOP
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
END LOOP;
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
FOR i IN RefSignalNorm'RANGE LOOP
RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i),
To_X01(RefSignalNorm(i)), RefTransition);
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
IF (RefEdge(i)) THEN
TimingData.RefTimeA(i) := NOW;
END IF;
END LOOP;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignalNorm'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i));
TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i));
IF (TestEvent(i)) THEN
TimingData.TestTimeA(i) := NOW;
END IF;
END LOOP;
FOR i IN ViolationTest'RANGE LOOP
ViolationTest(i) := '0';
END LOOP;
FOR i IN ViolationRef'RANGE LOOP
ViolationRef(i) := '0';
END LOOP;
FOR i IN TestSignalNorm'RANGE LOOP
IF (ArcType = CrossArc) THEN
FOR j IN RefSignalNorm'RANGE LOOP
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest;
TimingData.HoldEnA(i*NumRefBits+j)
:= TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest;
END IF;
IF (RefEdge(j)) THEN
--TimingData.HoldEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef;
TimingData.SetupEnA(i*NumRefBits+j)
:= TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef;
END IF;
END LOOP;
RefBitLow := 0;
RefBitHigh := NumRefBits-1;
TimingArrayIndex := i;
ELSE
IF ArcType = SubwordArc THEN
RefBitLow := i / NumBitsPerSubWord;
TimingArrayIndex := i + NumTestBits * RefBitLow;
ELSE
RefBitLow := i;
TimingArrayIndex := i;
END IF;
RefBitHigh := RefBitLow;
IF TestEvent(i) THEN
--TimingData.SetupEnA(i) := TRUE;
--IR252
TimingData.SetupEnA(i) := EnableSetupOnTest;
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest;
END IF;
IF RefEdge(RefBitLow) THEN
--TimingData.HoldEnA(i) := TRUE;
--IR252
TimingData.HoldEnA(i) := EnableHoldOnRef;
TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef;
END IF;
END IF;
EnArrayIndex := i;
FOR j IN RefBitLow to RefBitHigh LOOP
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelayNorm(i));
RefDly := Maximum(0 ns, RefDelayNorm(j));
InternalTimingCheck (
TestSignal => TestSignalNorm(i),
RefSignal => RefSignalNorm(j),
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHighNorm(TimingArrayIndex),
SetupLow => SetupLowNorm(TimingArrayIndex),
HoldHigh => HoldHighNorm(TimingArrayIndex),
HoldLow => HoldLowNorm(TimingArrayIndex),
RefTime => TimingData.RefTimeA(j),
RefEdge => RefEdge(j),
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(EnArrayIndex),
HoldEn => TimingData.HoldEnA(EnArrayIndex),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF (CheckInfo.Violation) THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j,
TestSignal, RefSignal, HeaderMsg, CheckInfo,
MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
ViolationTest(i) := 'X';
ViolationRef(j) := 'X';
END IF;
END IF;
END IF;
TimingArrayIndex := TimingArrayIndex + NumRefBits;
EnArrayIndex := EnArrayIndex + NumRefBits;
END LOOP;
END LOOP;
IF (ArcType = CrossArc) THEN
Violation := ViolationRef;
ELSE
IF (Violation'LENGTH = ViolationRef'LENGTH) THEN
Violation := ViolationRef;
ELSE
Violation := ViolationTest;
END IF;
END IF;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArraytype;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN VitalBoolArrayT;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0);
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME;
VARIABLE bias : TIME;
VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH;
VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH;
VARIABLE NumChecks : NATURAL;
VARIABLE ViolationTest : X01ArrayT(NumTestBits-1 downto 0);
VARIABLE ViolationRef : X01ArrayT(NumRefBits-1 downto 0);
VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0)
:= TestSignal;
VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0)
:= TestDelay;
VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0)
:= RefSignal;
VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0)
:= RefDelay;
VARIABLE CheckEnNorm : VitalBoolArrayT(NumRefBits-1 downto 0)
:= CheckEnabled;
VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0)
:= SetupHigh;
VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0)
:= SetupLow;
VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0)
:= HoldHigh;
VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0)
:= HoldLow;
VARIABLE RefBitLow : NATURAL;
VARIABLE RefBitHigh : NATURAL;
VARIABLE EnArrayIndex : NATURAL;
VARIABLE TimingArrayIndex: NATURAL;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0);
TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0);
TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0);
TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0);
IF ArcType = CrossArc THEN
NumChecks := RefSignal'LENGTH * TestSignal'LENGTH;
ELSE
NumChecks := TestSignal'LENGTH;
END IF;
TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
FOR i IN TestSignalNorm'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignalNorm(i));
END LOOP;
FOR i IN RefSignalNorm'RANGE LOOP
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
END LOOP;
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
FOR i IN RefSignalNorm'RANGE LOOP
RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i),
To_X01(RefSignalNorm(i)), RefTransition);
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
IF RefEdge(i) THEN
TimingData.RefTimeA(i) := NOW;
END IF;
END LOOP;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignalNorm'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i));
TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i));
IF TestEvent(i) THEN
TimingData.TestTimeA(i) := NOW;
END IF;
END LOOP;
FOR i IN ViolationTest'RANGE LOOP
ViolationTest(i) := '0';
END LOOP;
FOR i IN ViolationRef'RANGE LOOP
ViolationRef(i) := '0';
END LOOP;
FOR i IN TestSignalNorm'RANGE LOOP
IF (ArcType = CrossArc) THEN
FOR j IN RefSignalNorm'RANGE LOOP
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest;
TimingData.HoldEnA(i*NumRefBits+j)
:= TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest;
END IF;
IF (RefEdge(j)) THEN
--TimingData.HoldEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef;
TimingData.SetupEnA(i*NumRefBits+j)
:= TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef;
END IF;
END LOOP;
RefBitLow := 0;
RefBitHigh := NumRefBits-1;
TimingArrayIndex := i;
ELSE
IF (ArcType = SubwordArc) THEN
RefBitLow := i / NumBitsPerSubWord;
TimingArrayIndex := i + NumTestBits * RefBitLow;
ELSE
RefBitLow := i;
TimingArrayIndex := i;
END IF;
RefBitHigh := RefBitLow;
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i) := TRUE;
--IR252
TimingData.SetupEnA(i) := EnableSetupOnTest;
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest;
END IF;
IF (RefEdge(RefBitLow)) THEN
--TimingData.HoldEnA(i) := TRUE;
--IR252
TimingData.HoldEnA(i) := EnableHoldOnRef;
TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef;
END IF;
END IF;
EnArrayIndex := i;
FOR j IN RefBitLow to RefBitHigh LOOP
IF (CheckEnNorm(j)) THEN
TestDly := Maximum(0 ns, TestDelayNorm(i));
RefDly := Maximum(0 ns, RefDelayNorm(j));
InternalTimingCheck (
TestSignal => TestSignalNorm(i),
RefSignal => RefSignalNorm(j),
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHighNorm(TimingArrayIndex),
SetupLow => SetupLowNorm(TimingArrayIndex),
HoldHigh => HoldHighNorm(TimingArrayIndex),
HoldLow => HoldLowNorm(TimingArrayIndex),
RefTime => TimingData.RefTimeA(j),
RefEdge => RefEdge(j),
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(EnArrayIndex),
HoldEn => TimingData.HoldEnA(EnArrayIndex),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF (CheckInfo.Violation) THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j,
TestSignal, RefSignal, HeaderMsg, CheckInfo,
MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
ViolationTest(i) := 'X';
ViolationRef(j) := 'X';
END IF;
END IF;
END IF;
TimingArrayIndex := TimingArrayIndex + NumRefBits;
EnArrayIndex := EnArrayIndex + NumRefBits;
END LOOP;
END LOOP;
IF (ArcType = CrossArc) THEN
Violation := ViolationRef;
ELSE
IF (Violation'LENGTH = ViolationRef'LENGTH) THEN
Violation := ViolationRef;
ELSE
Violation := ViolationTest;
END IF;
END IF;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
-- scalar violations not needed
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : BOOLEAN;
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'RANGE);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME := Maximum(0 ns, RefDelay);
VARIABLE bias : TIME;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(TestSignal'RANGE);
TimingData.TestTimeA := NEW VitalTimeArrayT(TestSignal'RANGE);
TimingData.HoldEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
TimingData.SetupEnA := NEW VitalBoolArrayT(TestSignal'RANGE);
FOR i IN TestSignal'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignal(i));
END LOOP;
TimingData.RefLast := To_X01(RefSignal);
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
RefEdge := EdgeSymbolMatch(TimingData.RefLast, To_X01(RefSignal),
RefTransition);
TimingData.RefLast := To_X01(RefSignal);
IF (RefEdge) THEN
TimingData.RefTime := NOW;
--TimingData.HoldEnA.all := (TestSignal'RANGE=>TRUE);
--IR252 3/23/98
FOR i IN TestSignal'RANGE LOOP
TimingData.SetupEnA(i)
:= TimingData.SetupEnA(i) AND EnableSetupOnRef;
TimingData.HoldEnA(i) := EnableHoldOnRef;
END LOOP;
END IF;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignal'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignal(i));
TimingData.TestLastA(i) := To_X01Z(TestSignal(i));
IF TestEvent(i) THEN
TimingData.SetupEnA(i) := EnableSetupOnTest ; --IR252 3/23/98
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest ;
--IR252 3/23/98
TimingData.TestTimeA(i) := NOW;
--TimingData.SetupEnA(i) := TRUE;
TimingData.TestTime := NOW;
END IF;
END LOOP;
Violation := '0';
FOR i IN TestSignal'RANGE LOOP
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelay(i));
InternalTimingCheck (
TestSignal => TestSignal(i),
RefSignal => RefSignal,
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHigh(i),
SetupLow => SetupLow(i),
HoldHigh => HoldHigh(i),
HoldLow => HoldLow(i),
RefTime => TimingData.RefTime,
RefEdge => RefEdge,
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(i),
HoldEn => TimingData.HoldEnA(i),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF CheckInfo.Violation THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i ,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
Violation := 'X';
END IF;
END IF;
END IF;
END LOOP;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemorySetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalMemoryTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
SIGNAL RefSignal : IN std_logic_vector;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN VitalDelayArraytype;
CONSTANT SetupHigh : IN VitalDelayArraytype;
CONSTANT SetupLow : IN VitalDelayArraytype;
CONSTANT HoldHigh : IN VitalDelayArraytype;
CONSTANT HoldLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT ArcType : IN VitalMemoryArcType := CrossArc;
CONSTANT NumBitsPerSubWord : IN INTEGER := 1;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType;
--IR252 3/23/98
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE;
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE;
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE
) IS
VARIABLE CheckInfo : CheckInfoType;
VARIABLE RefEdge : VitalBoolArrayT(RefSignal'LENGTH-1 downto 0);
VARIABLE TestEvent : VitalBoolArrayT(TestSignal'LENGTH-1 downto 0);
VARIABLE TestDly : TIME;
VARIABLE RefDly : TIME;
VARIABLE bias : TIME;
VARIABLE NumTestBits : NATURAL := TestSignal'LENGTH;
VARIABLE NumRefBits : NATURAL := RefSignal'LENGTH;
VARIABLE NumChecks : NATURAL;
VARIABLE TestSignalNorm : std_logic_vector(NumTestBits-1 downto 0)
:= TestSignal;
VARIABLE TestDelayNorm : VitalDelayArraytype(NumTestBits-1 downto 0)
:= TestDelay;
VARIABLE RefSignalNorm : std_logic_vector(NumRefBits-1 downto 0)
:= RefSignal;
VARIABLE RefDelayNorm : VitalDelayArraytype(NumRefBits-1 downto 0)
:= RefDelay;
VARIABLE SetupHighNorm : VitalDelayArraytype(SetupHigh'LENGTH-1 downto 0)
:= SetupHigh;
VARIABLE SetupLowNorm : VitalDelayArraytype(SetupLow'LENGTH-1 downto 0)
:= SetupLow;
VARIABLE HoldHighNorm : VitalDelayArraytype(HoldHigh'LENGTH-1 downto 0)
:= HoldHigh;
VARIABLE HoldLowNorm : VitalDelayArraytype(HoldLow'LENGTH-1 downto 0)
:= HoldLow;
VARIABLE RefBitLow : NATURAL;
VARIABLE RefBitHigh : NATURAL;
VARIABLE EnArrayIndex : NATURAL;
VARIABLE TimingArrayIndex: NATURAL;
BEGIN
-- Initialization of working area.
IF (TimingData.NotFirstFlag = FALSE) THEN
TimingData.TestLastA := NEW std_logic_vector(NumTestBits-1 downto 0);
TimingData.TestTimeA := NEW VitalTimeArrayT(NumTestBits-1 downto 0);
TimingData.RefTimeA := NEW VitalTimeArrayT(NumRefBits-1 downto 0);
TimingData.RefLastA := NEW X01ArrayT(NumRefBits-1 downto 0);
IF (ArcType = CrossArc) THEN
NumChecks := RefSignal'LENGTH * TestSignal'LENGTH;
ELSE
NumChecks := TestSignal'LENGTH;
END IF;
TimingData.HoldEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
TimingData.SetupEnA := NEW VitalBoolArrayT(NumChecks-1 downto 0);
FOR i IN TestSignalNorm'RANGE LOOP
TimingData.TestLastA(i) := To_X01(TestSignalNorm(i));
END LOOP;
FOR i IN RefSignalNorm'RANGE LOOP
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
END LOOP;
TimingData.NotFirstFlag := TRUE;
END IF;
-- Detect reference edges and record the time of the last edge
FOR i IN RefSignalNorm'RANGE LOOP
RefEdge(i) := EdgeSymbolMatch(TimingData.RefLastA(i),
To_X01(RefSignalNorm(i)), RefTransition);
TimingData.RefLastA(i) := To_X01(RefSignalNorm(i));
IF (RefEdge(i)) THEN
TimingData.RefTimeA(i) := NOW;
END IF;
END LOOP;
-- Detect test (data) changes and record the time of the last change
FOR i IN TestSignalNorm'RANGE LOOP
TestEvent(i) := TimingData.TestLastA(i) /= To_X01Z(TestSignalNorm(i));
TimingData.TestLastA(i) := To_X01Z(TestSignalNorm(i));
IF (TestEvent(i)) THEN
TimingData.TestTimeA(i) := NOW;
END IF;
END LOOP;
FOR i IN TestSignalNorm'RANGE LOOP
IF (ArcType = CrossArc) THEN
FOR j IN RefSignalNorm'RANGE LOOP
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.SetupEnA(i*NumRefBits+j) := EnableSetupOnTest;
TimingData.HoldEnA(i*NumRefBits+j)
:= TimingData.HoldEnA(i*NumRefBits+j) AND EnableHoldOnTest;
END IF;
IF (RefEdge(j)) THEN
--TimingData.HoldEnA(i*NumRefBits+j) := TRUE;
--IR252
TimingData.HoldEnA(i*NumRefBits+j) := EnableHoldOnRef;
TimingData.SetupEnA(i*NumRefBits+j)
:= TimingData.SetupEnA(i*NumRefBits+j) AND EnableSetupOnRef;
END IF;
END LOOP;
RefBitLow := 0;
RefBitHigh := NumRefBits-1;
TimingArrayIndex := i;
ELSE
IF (ArcType = SubwordArc) THEN
RefBitLow := i / NumBitsPerSubWord;
TimingArrayIndex := i + NumTestBits * RefBitLow;
ELSE
RefBitLow := i;
TimingArrayIndex := i;
END IF;
RefBitHigh := RefBitLow;
IF (TestEvent(i)) THEN
--TimingData.SetupEnA(i) := TRUE;
--IR252
TimingData.SetupEnA(i) := EnableSetupOnTest;
TimingData.HoldEnA(i) := TimingData.HoldEnA(i) AND EnableHoldOnTest;
END IF;
IF (RefEdge(RefBitLow)) THEN
--TimingData.HoldEnA(i) := TRUE;
--IR252
TimingData.HoldEnA(i) := EnableHoldOnRef;
TimingData.SetupEnA(i) := TimingData.SetupEnA(i) AND EnableSetupOnRef;
END IF;
END IF;
EnArrayIndex := i;
Violation := '0';
FOR j IN RefBitLow to RefBitHigh LOOP
IF (CheckEnabled) THEN
TestDly := Maximum(0 ns, TestDelayNorm(i));
RefDly := Maximum(0 ns, RefDelayNorm(j));
InternalTimingCheck (
TestSignal => TestSignalNorm(i),
RefSignal => RefSignalNorm(j),
TestDelay => TestDly,
RefDelay => RefDly,
SetupHigh => SetupHighNorm(TimingArrayIndex),
SetupLow => SetupLowNorm(TimingArrayIndex),
HoldHigh => HoldHighNorm(TimingArrayIndex),
HoldLow => HoldLowNorm(TimingArrayIndex),
RefTime => TimingData.RefTimeA(j),
RefEdge => RefEdge(j),
TestTime => TimingData.TestTimeA(i),
TestEvent => TestEvent(i),
SetupEn => TimingData.SetupEnA(EnArrayIndex),
HoldEn => TimingData.HoldEnA(EnArrayIndex),
CheckInfo => CheckInfo,
MsgOn => MsgOn
);
-- Report any detected violations and set return violation flag
IF (CheckInfo.Violation) THEN
IF (MsgOn) THEN
VitalMemoryReportViolation (TestSignalName, RefSignalName, i, j,
TestSignal, RefSignal, HeaderMsg, CheckInfo,
MsgFormat, MsgSeverity );
END IF;
IF (XOn) THEN
Violation := 'X';
END IF;
END IF;
END IF;
TimingArrayIndex := TimingArrayIndex + NumRefBits;
EnArrayIndex := EnArrayIndex + NumRefBits;
END LOOP;
END LOOP;
END VitalMemorySetupHoldCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
CONSTANT Period : IN VitalDelayArraytype;
CONSTANT PulseWidthHigh : IN VitalDelayArraytype;
CONSTANT PulseWidthLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
) IS
VARIABLE TestDly : VitalDelayType;
VARIABLE CheckInfo : CheckInfoType;
VARIABLE PeriodObs : VitalDelayType;
VARIABLE PulseTest : BOOLEAN;
VARIABLE PeriodTest: BOOLEAN;
VARIABLE TestValue : X01;
BEGIN
-- Initialize for no violation
Violation := '0'; --MEM IR 402
FOR i IN TestSignal'RANGE LOOP
TestDly := Maximum(0 ns, TestDelay(i));
TestValue := To_X01(TestSignal(i));
IF (PeriodData(i).NotFirstFlag = FALSE) THEN
PeriodData(i).Rise := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Fall := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Last := TestValue;
PeriodData(i).NotFirstFlag := TRUE;
END IF;
-- Initialize for no violation
-- Violation := '0'; --Mem IR 402
-- No violation possible if no test signal change
NEXT WHEN (PeriodData(i).Last = TestValue);
-- record starting pulse times
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'P')) THEN
-- Compute period times, then record the High Rise Time
PeriodObs := NOW - PeriodData(i).Rise;
PeriodData(i).Rise := NOW;
PeriodTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'N')) THEN
-- Compute period times, then record the Low Fall Time
PeriodObs := NOW - PeriodData(i).Fall;
PeriodData(i).Fall := NOW;
PeriodTest := TRUE;
ELSE
PeriodTest := FALSE;
END IF;
-- do checks on pulse ends
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'p')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Fall;
CheckInfo.ExpTime := PulseWidthLow(i);
PulseTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'n')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Rise;
CheckInfo.ExpTime := PulseWidthHigh(i);
PulseTest := TRUE;
ELSE
PulseTest := FALSE;
END IF;
IF (PulseTest AND CheckEnabled) THEN
-- Verify Pulse Width [ignore 1st edge]
IF (CheckInfo.ObsTime < CheckInfo.ExpTime) THEN
IF (XOn) THEN
Violation := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PulseWidCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := PeriodData(i).Last;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
IF (PeriodTest AND CheckEnabled) THEN
-- Verify the Period [ignore 1st edge]
CheckInfo.ObsTime := PeriodObs;
CheckInfo.ExpTime := Period(i);
IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN
IF (XOn) THEN
Violation := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PeriodCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := TestValue;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
PeriodData(i).Last := TestValue;
END LOOP;
END VitalMemoryPeriodPulseCheck;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryPeriodPulseCheck (
VARIABLE Violation : OUT X01ArrayT;
VARIABLE PeriodData : INOUT VitalPeriodDataArrayType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN VitalDelayArraytype;
CONSTANT Period : IN VitalDelayArraytype;
CONSTANT PulseWidthHigh : IN VitalDelayArraytype;
CONSTANT PulseWidthLow : IN VitalDelayArraytype;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT MsgFormat : IN VitalMemoryMsgFormatType
)IS
VARIABLE TestDly : VitalDelayType;
VARIABLE CheckInfo : CheckInfoType;
VARIABLE PeriodObs : VitalDelayType;
VARIABLE PulseTest : BOOLEAN;
VARIABLE PeriodTest: BOOLEAN;
VARIABLE TestValue : X01;
BEGIN
FOR i IN TestSignal'RANGE LOOP
TestDly := Maximum(0 ns, TestDelay(i));
TestValue := To_X01(TestSignal(i));
IF (PeriodData(i).NotFirstFlag = FALSE) THEN
PeriodData(i).Rise := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Fall := -Maximum(Period(i),
Maximum(PulseWidthHigh(i),PulseWidthLow(i)));
PeriodData(i).Last := TestValue;
PeriodData(i).NotFirstFlag := TRUE;
END IF;
-- Initialize for no violation
Violation(i) := '0';
-- No violation possible if no test signal change
NEXT WHEN (PeriodData(i).Last = TestValue);
-- record starting pulse times
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'P')) THEN
-- Compute period times, then record the High Rise Time
PeriodObs := NOW - PeriodData(i).Rise;
PeriodData(i).Rise := NOW;
PeriodTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'N')) THEN
-- Compute period times, then record the Low Fall Time
PeriodObs := NOW - PeriodData(i).Fall;
PeriodData(i).Fall := NOW;
PeriodTest := TRUE;
ELSE
PeriodTest := FALSE;
END IF;
-- do checks on pulse ends
IF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'p')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Fall;
CheckInfo.ExpTime := PulseWidthLow(i);
PulseTest := TRUE;
ELSIF (EdgeSymbolMatch(PeriodData(i).Last, TestValue, 'n')) THEN
-- Compute pulse times
CheckInfo.ObsTime := NOW - PeriodData(i).Rise;
CheckInfo.ExpTime := PulseWidthHigh(i);
PulseTest := TRUE;
ELSE
PulseTest := FALSE;
END IF;
IF (PulseTest AND CheckEnabled) THEN
-- Verify Pulse Width [ignore 1st edge]
IF (CheckInfo.ObsTime < CheckInfo.ExpTime) THEN
IF (XOn) THEN
Violation(i) := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PulseWidCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := PeriodData(i).Last;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFormat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
IF (PeriodTest AND CheckEnabled) THEN
-- Verify the Period [ignore 1st edge]
CheckInfo.ObsTime := PeriodObs;
CheckInfo.ExpTime := Period(i);
IF ( CheckInfo.ObsTime < CheckInfo.ExpTime ) THEN
IF (XOn) THEN
Violation(i) := 'X';
END IF;
IF (MsgOn) THEN
CheckInfo.Violation := TRUE;
CheckInfo.CheckKind := PeriodCheck;
CheckInfo.DetTime := NOW - TestDly;
CheckInfo.State := TestValue;
VitalMemoryReportViolation (TestSignalName, "", i,
HeaderMsg, CheckInfo, MsgFOrmat, MsgSeverity );
END IF; -- MsgOn
END IF;
END IF;
PeriodData(i).Last := TestValue;
END LOOP;
END VitalMemoryPeriodPulseCheck;
-- ----------------------------------------------------------------------------
-- Functionality Section
-- ----------------------------------------------------------------------------
-- Look-up table. Given an int, we can get the 4-bit bit_vector.
TYPE HexToBitvTableType IS ARRAY (NATURAL RANGE <>) OF
std_logic_vector(3 DOWNTO 0) ;
CONSTANT HexToBitvTable : HexToBitvTableType (0 TO 15) :=
(
"0000", "0001", "0010", "0011",
"0100", "0101", "0110", "0111",
"1000", "1001", "1010", "1011",
"1100", "1101", "1110", "1111"
) ;
-- ----------------------------------------------------------------------------
-- Misc Utilities Local Utilities
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Procedure: IsSpace
-- Parameters: ch -- input character
-- Description: Returns TRUE or FALSE depending on the input character
-- being white space or not.
-- ----------------------------------------------------------------------------
FUNCTION IsSpace (ch : character)
RETURN boolean IS
BEGIN
RETURN ((ch = ' ') OR (ch = CR) OR (ch = HT) OR (ch = NUL));
END IsSpace;
-- ----------------------------------------------------------------------------
-- Procedure: LenOfString
-- Parameters: Str -- input string
-- Description: Returns the NATURAL length of the input string.
-- as terminated by the first NUL character.
-- ----------------------------------------------------------------------------
FUNCTION LenOfString (Str : STRING)
RETURN NATURAL IS
VARIABLE StrRight : NATURAL;
BEGIN
StrRight := Str'RIGHT;
FOR i IN Str'RANGE LOOP
IF (Str(i) = NUL) THEN
StrRight := i - 1;
EXIT;
END IF;
END LOOP;
RETURN (StrRight);
END LenOfString;
-- ----------------------------------------------------------------------------
-- Procedure: HexToInt
-- Parameters: Hex -- input character or string
-- Description: Converts input character or string interpreted as a
-- hexadecimal representation to integer value.
-- ----------------------------------------------------------------------------
FUNCTION HexToInt(Hex : CHARACTER) RETURN INTEGER IS
CONSTANT HexChars : STRING := "0123456789ABCDEFabcdef";
CONSTANT XHiChar : CHARACTER := 'X';
CONSTANT XLoChar : CHARACTER := 'x';
BEGIN
IF (Hex = XLoChar OR Hex = XHiChar) THEN
RETURN (23);
END IF;
FOR i IN 1 TO 16 LOOP
IF(Hex = HexChars(i)) THEN
RETURN (i-1);
END IF;
END LOOP;
FOR i IN 17 TO 22 LOOP
IF (Hex = HexChars(i)) THEN
RETURN (i-7);
END IF;
END LOOP;
ASSERT FALSE REPORT
"Invalid character received by HexToInt function"
SEVERITY WARNING;
RETURN (0);
END HexToInt;
-- ----------------------------------------------------------------------------
FUNCTION HexToInt (Hex : STRING) RETURN INTEGER IS
VARIABLE Value : INTEGER := 0;
VARIABLE Length : INTEGER;
BEGIN
Length := LenOfString(hex);
IF (Length > 8) THEN
ASSERT FALSE REPORT
"Invalid string length received by HexToInt function"
SEVERITY WARNING;
ELSE
FOR i IN 1 TO Length LOOP
Value := Value + HexToInt(Hex(i)) * 16 ** (Length - i);
END LOOP;
END IF;
RETURN (Value);
END HexToInt;
-- ----------------------------------------------------------------------------
-- Procedure: HexToBitv
-- Parameters: Hex -- Input hex string
-- Description: Converts input hex string to a std_logic_vector
-- ----------------------------------------------------------------------------
FUNCTION HexToBitv(
Hex : STRING
) RETURN std_logic_vector is
VARIABLE Index : INTEGER := 0 ;
VARIABLE ValHexToInt : INTEGER ;
VARIABLE BitsPerHex : INTEGER := 4 ; -- Denotes no. of bits per hex char.
VARIABLE HexLen : NATURAL := (BitsPerHex * LenOfString(Hex)) ;
VARIABLE TableVal : std_logic_vector(3 DOWNTO 0) ;
VARIABLE Result : std_logic_vector(HexLen-1 DOWNTO 0) ;
BEGIN
-- Assign 4-bit wide bit vector to result directly from a look-up table.
Index := 0 ;
WHILE ( Index < HexLen ) LOOP
ValHexToInt := HexToInt( Hex((HexLen - Index)/BitsPerHex ) );
IF ( ValHexToInt = 23 ) THEN
TableVal := "XXXX";
ELSE
-- Look up from the table.
TableVal := HexToBitvTable( ValHexToInt ) ;
END IF;
-- Assign now.
Result(Index+3 DOWNTO Index) := TableVal ;
-- Get ready for next block of 4-bits.
Index := Index + 4 ;
END LOOP ;
RETURN Result ;
END HexToBitv ;
-- ----------------------------------------------------------------------------
-- Procedure: BinToBitv
-- Parameters: Bin -- Input bin string
-- Description: Converts input bin string to a std_logic_vector
-- ----------------------------------------------------------------------------
FUNCTION BinToBitv(
Bin : STRING
) RETURN std_logic_vector is
VARIABLE Index : INTEGER := 0 ;
VARIABLE Length : NATURAL := LenOfString(Bin);
VARIABLE BitVal : std_ulogic;
VARIABLE Result : std_logic_vector(Length-1 DOWNTO 0) ;
BEGIN
Index := 0 ;
WHILE ( Index < Length ) LOOP
IF (Bin(Length-Index) = '0') THEN
BitVal := '0';
ELSIF (Bin(Length-Index) = '1') THEN
BitVal := '1';
ELSE
BitVal := 'X';
END IF ;
-- Assign now.
Result(Index) := BitVal ;
Index := Index + 1 ;
END LOOP ;
RETURN Result ;
END BinToBitv ;
-- ----------------------------------------------------------------------------
-- For Memory Table Modeling
-- ----------------------------------------------------------------------------
TYPE To_MemoryCharType IS ARRAY (VitalMemorySymbolType) OF CHARACTER;
CONSTANT To_MemoryChar : To_MemoryCharType :=
( '/', '\', 'P', 'N', 'r', 'f', 'p', 'n', 'R', 'F', '^', 'v',
'E', 'A', 'D', '*', 'X', '0', '1', '-', 'B', 'Z', 'S',
'g', 'u', 'i', 'G', 'U', 'I',
'w', 's',
'c', 'l', 'd', 'e', 'C', 'L',
'M', 'm', 't' );
TYPE ValidMemoryTableInputType IS ARRAY (VitalMemorySymbolType) OF BOOLEAN;
CONSTANT ValidMemoryTableInput : ValidMemoryTableInputType :=
-- '/', '\', 'P', 'N', 'r', 'f',
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'p', 'n', 'R', 'F', '^', 'v',
TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
-- 'E', 'A', 'D', '*',
TRUE, TRUE, TRUE, TRUE,
-- 'X', '0', '1', '-', 'B', 'Z',
TRUE, TRUE, TRUE, TRUE, TRUE, FALSE,
-- 'S',
TRUE,
-- 'g', 'u', 'i', 'G', 'U', 'I',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'w', 's',
FALSE, FALSE,
-- 'c', 'l', 'd', 'e', 'C', 'L',
FALSE, FALSE, FALSE, FALSE, FALSE, FALSE,
-- 'M', 'm', 't'
FALSE, FALSE, FALSE);
TYPE MemoryTableMatchType IS ARRAY (X01,X01,VitalMemorySymbolType) OF BOOLEAN;
-- last value, present value, table symbol
CONSTANT MemoryTableMatch : MemoryTableMatchType := (
( -- X (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
-- g u i G U I
-- w s
-- c l d e, C L
-- m t
( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,TRUE, TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, FALSE,TRUE, FALSE,
TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE)
),
(-- 0 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
-- g u i G U I
-- w s
-- c l d e, C L
-- m t
( FALSE,FALSE,FALSE,FALSE,TRUE, FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
TRUE, FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE)
),
(-- 1 (lastvalue)
-- / \ P N r f
-- p n R F ^ v
-- E A D *
-- X 0 1 - B Z S
-- g u i G U I
-- w s
-- c l d e, C L
-- m t
( FALSE,FALSE,FALSE,FALSE,FALSE,TRUE ,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE,
TRUE, FALSE,FALSE,TRUE, FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,TRUE, FALSE,TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,TRUE,
FALSE,TRUE, FALSE,TRUE, TRUE, FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE),
( FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,TRUE, TRUE, TRUE, FALSE,TRUE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,
FALSE,FALSE,FALSE,FALSE,FALSE,FALSE,
FALSE,FALSE,FALSE)
)
);
-- ----------------------------------------------------------------------------
-- Error Message Types and Tables
-- ----------------------------------------------------------------------------
TYPE VitalMemoryErrorType IS (
ErrGoodAddr, -- 'g' Good address (no transition)
ErrUnknAddr, -- 'u' 'X' levels in address (no transition)
ErrInvaAddr, -- 'i' Invalid address (no transition)
ErrGoodTrAddr, -- 'G' Good address (with transition)
ErrUnknTrAddr, -- 'U' 'X' levels in address (with transition)
ErrInvaTrAddr, -- 'I' Invalid address (with transition)
ErrWrDatMem, -- 'w' Writing data to memory
ErrNoChgMem, -- 's' Retaining previous memory contents
ErrCrAllMem, -- 'c' Corrupting entire memory with 'X'
ErrCrWrdMem, -- 'l' Corrupting a word in memory with 'X'
ErrCrBitMem, -- 'd' Corrupting a single bit in memory with 'X'
ErrCrDatMem, -- 'e' Corrupting a word with 'X' based on data in
ErrCrAllSubMem,-- 'C' Corrupting a sub-word entire memory with 'X'
ErrCrWrdSubMem,-- 'L' Corrupting a sub-word in memory with 'X'
ErrCrBitSubMem,-- 'D' Corrupting a single bit of a memory sub-word with 'X'
ErrCrDatSubMem,-- 'E' Corrupting a sub-word with 'X' based on data in
ErrCrWrdOut, -- 'l' Corrupting data out with 'X'
ErrCrBitOut, -- 'd' Corrupting a single bit of data out with 'X'
ErrCrDatOut, -- 'e' Corrupting data out with 'X' based on data in
ErrCrWrdSubOut,-- 'L' Corrupting data out sub-word with 'X'
ErrCrBitSubOut,-- 'D' Corrupting a single bit of data out sub-word with 'X'
ErrCrDatSubOut,-- 'E' Corrupting data out sub-word with 'X' based on data in
ErrImplOut, -- 'M' Implicit read from memory to data out
ErrReadOut, -- 'm' Reading data from memory to data out
ErrAssgOut, -- 't' Transferring from data in to data out
ErrAsgXOut, -- 'X' Assigning unknown level to data out
ErrAsg0Out, -- '0' Assigning low level to data out
ErrAsg1Out, -- '1' Assigning high level to data out
ErrAsgZOut, -- 'Z' Assigning high impedence to data out
ErrAsgSOut, -- 'S' Keeping data out at steady value
ErrAsgXMem, -- 'X' Assigning unknown level to memory location
ErrAsg0Mem, -- '0' Assigning low level to memory location
ErrAsg1Mem, -- '1' Assigning high level to memory location
ErrAsgZMem, -- 'Z' Assigning high impedence to memory location
ErrDefMemAct, -- No memory table match, using default action
ErrInitMem, -- Initialize memory contents
ErrMcpWrCont, -- Memory cross port to same port write contention
ErrMcpCpCont, -- Memory cross port read/write data/memory contention
ErrMcpCpRead, -- Memory cross port read to same port
ErrMcpRdWrCo, -- Memory cross port read/write data only contention
ErrMcpCpWrCont,-- Memory cross port to cross port write contention
ErrUnknMemDo, -- Unknown memory action
ErrUnknDatDo, -- Unknown data action
ErrUnknSymbol, -- Illegal memory symbol
ErrLdIlgArg,
ErrLdAddrRng,
ErrLdMemInfo,
ErrLdFileEmpty,
ErrPrintString
);
TYPE VitalMemoryErrorSeverityType IS
ARRAY (VitalMemoryErrorType) OF SEVERITY_LEVEL;
CONSTANT VitalMemoryErrorSeverity :
VitalMemoryErrorSeverityType := (
ErrGoodAddr => NOTE,
ErrUnknAddr => WARNING,
ErrInvaAddr => WARNING,
ErrGoodTrAddr => NOTE,
ErrUnknTrAddr => WARNING,
ErrInvaTrAddr => WARNING,
ErrWrDatMem => NOTE,
ErrNoChgMem => NOTE,
ErrCrAllMem => WARNING,
ErrCrWrdMem => WARNING,
ErrCrBitMem => WARNING,
ErrCrDatMem => WARNING,
ErrCrAllSubMem => WARNING,
ErrCrWrdSubMem => WARNING,
ErrCrBitSubMem => WARNING,
ErrCrDatSubMem => WARNING,
ErrCrWrdOut => WARNING,
ErrCrBitOut => WARNING,
ErrCrDatOut => WARNING,
ErrCrWrdSubOut => WARNING,
ErrCrBitSubOut => WARNING,
ErrCrDatSubOut => WARNING,
ErrImplOut => NOTE,
ErrReadOut => NOTE,
ErrAssgOut => NOTE,
ErrAsgXOut => NOTE,
ErrAsg0Out => NOTE,
ErrAsg1Out => NOTE,
ErrAsgZOut => NOTE,
ErrAsgSOut => NOTE,
ErrAsgXMem => NOTE,
ErrAsg0Mem => NOTE,
ErrAsg1Mem => NOTE,
ErrAsgZMem => NOTE,
ErrDefMemAct => NOTE,
ErrInitMem => NOTE,
ErrMcpWrCont => WARNING,
ErrMcpCpCont => WARNING,
ErrMcpCpRead => WARNING,
ErrMcpRdWrCo => WARNING,
ErrMcpCpWrCont => WARNING,
ErrUnknMemDo => ERROR,
ErrUnknDatDo => ERROR,
ErrUnknSymbol => ERROR,
ErrLdIlgArg => ERROR,
ErrLdAddrRng => WARNING,
ErrLdMemInfo => NOTE,
ErrLdFileEmpty => ERROR,
ErrPrintString => WARNING
);
-- ----------------------------------------------------------------------------
CONSTANT MsgGoodAddr : STRING
:= "Good address (no transition)";
CONSTANT MsgUnknAddr : STRING
:= "Unknown address (no transition)";
CONSTANT MsgInvaAddr : STRING
:= "Invalid address (no transition)";
CONSTANT MsgGoodTrAddr : STRING
:= "Good address (with transition)";
CONSTANT MsgUnknTrAddr : STRING
:= "Unknown address (with transition)";
CONSTANT MsgInvaTrAddr : STRING
:= "Invalid address (with transition)";
CONSTANT MsgNoChgMem : STRING
:= "Retaining previous memory contents";
CONSTANT MsgWrDatMem : STRING
:= "Writing data to memory";
CONSTANT MsgCrAllMem : STRING
:= "Corrupting entire memory with 'X'";
CONSTANT MsgCrWrdMem : STRING
:= "Corrupting a word in memory with 'X'";
CONSTANT MsgCrBitMem : STRING
:= "Corrupting a single bit in memory with 'X'";
CONSTANT MsgCrDatMem : STRING
:= "Corrupting a word with 'X' based on data in";
CONSTANT MsgCrAllSubMem : STRING
:= "Corrupting a sub-word entire memory with 'X'";
CONSTANT MsgCrWrdSubMem : STRING
:= "Corrupting a sub-word in memory with 'X'";
CONSTANT MsgCrBitSubMem : STRING
:= "Corrupting a single bit of a sub-word with 'X'";
CONSTANT MsgCrDatSubMem : STRING
:= "Corrupting a sub-word with 'X' based on data in";
CONSTANT MsgCrWrdOut : STRING
:= "Corrupting data out with 'X'";
CONSTANT MsgCrBitOut : STRING
:= "Corrupting a single bit of data out with 'X'";
CONSTANT MsgCrDatOut : STRING
:= "Corrupting data out with 'X' based on data in";
CONSTANT MsgCrWrdSubOut : STRING
:= "Corrupting data out sub-word with 'X'";
CONSTANT MsgCrBitSubOut : STRING
:= "Corrupting a single bit of data out sub-word with 'X'";
CONSTANT MsgCrDatSubOut : STRING
:= "Corrupting data out sub-word with 'X' based on data in";
CONSTANT MsgImplOut : STRING
:= "Implicit read from memory to data out";
CONSTANT MsgReadOut : STRING
:= "Reading data from memory to data out";
CONSTANT MsgAssgOut : STRING
:= "Transferring from data in to data out";
CONSTANT MsgAsgXOut : STRING
:= "Assigning unknown level to data out";
CONSTANT MsgAsg0Out : STRING
:= "Assigning low level to data out";
CONSTANT MsgAsg1Out : STRING
:= "Assigning high level to data out";
CONSTANT MsgAsgZOut : STRING
:= "Assigning high impedance to data out";
CONSTANT MsgAsgSOut : STRING
:= "Keeping data out at steady value";
CONSTANT MsgAsgXMem : STRING
:= "Assigning unknown level to memory location";
CONSTANT MsgAsg0Mem : STRING
:= "Assigning low level to memory location";
CONSTANT MsgAsg1Mem : STRING
:= "Assigning high level to memory location";
CONSTANT MsgAsgZMem : STRING
:= "Assigning high impedance to memory location";
CONSTANT MsgDefMemAct : STRING
:= "No memory table match, using default action";
CONSTANT MsgInitMem : STRING
:= "Initializing memory contents";
CONSTANT MsgMcpWrCont : STRING
:= "Same port write contention";
CONSTANT MsgMcpCpCont : STRING
:= "Cross port read/write data/memory contention";
CONSTANT MsgMcpCpRead : STRING
:= "Cross port read to same port";
CONSTANT MsgMcpRdWrCo : STRING
:= "Cross port read/write data only contention";
CONSTANT MsgMcpCpWrCont : STRING
:= "Cross port write contention";
CONSTANT MsgUnknMemDo : STRING
:= "Unknown memory action";
CONSTANT MsgUnknDatDo : STRING
:= "Unknown data action";
CONSTANT MsgUnknSymbol : STRING
:= "Illegal memory symbol";
CONSTANT MsgLdIlgArg : STRING
:= "Illegal bit arguments while loading memory.";
CONSTANT MsgLdMemInfo : STRING
:= "Loading data from the file into memory.";
CONSTANT MsgLdAddrRng : STRING
:= "Address out of range while loading memory.";
CONSTANT MsgLdFileEmpty : STRING
:= "Memory load file is empty.";
CONSTANT MsgPrintString : STRING
:= "";
CONSTANT MsgUnknown : STRING
:= "Unknown error message.";
CONSTANT MsgVMT : STRING
:= "VitalMemoryTable";
CONSTANT MsgVMV : STRING
:= "VitalMemoryViolation";
CONSTANT MsgVDM : STRING
:= "VitalDeclareMemory";
CONSTANT MsgVMCP : STRING
:= "VitalMemoryCrossPorts";
-- ----------------------------------------------------------------------------
-- LOCAL Utilities
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Procedure: MemoryMessage
-- Parameters: ErrorId -- Input error code
-- Description: This function looks up the input error code and returns
-- the string value of the associated message.
-- ----------------------------------------------------------------------------
FUNCTION MemoryMessage (
CONSTANT ErrorId : IN VitalMemoryErrorType
) RETURN STRING IS
BEGIN
CASE ErrorId IS
WHEN ErrGoodAddr => RETURN MsgGoodAddr ;
WHEN ErrUnknAddr => RETURN MsgUnknAddr ;
WHEN ErrInvaAddr => RETURN MsgInvaAddr ;
WHEN ErrGoodTrAddr => RETURN MsgGoodTrAddr ;
WHEN ErrUnknTrAddr => RETURN MsgUnknTrAddr ;
WHEN ErrInvaTrAddr => RETURN MsgInvaTrAddr ;
WHEN ErrWrDatMem => RETURN MsgWrDatMem ;
WHEN ErrNoChgMem => RETURN MsgNoChgMem ;
WHEN ErrCrAllMem => RETURN MsgCrAllMem ;
WHEN ErrCrWrdMem => RETURN MsgCrWrdMem ;
WHEN ErrCrBitMem => RETURN MsgCrBitMem ;
WHEN ErrCrDatMem => RETURN MsgCrDatMem ;
WHEN ErrCrAllSubMem => RETURN MsgCrAllSubMem;
WHEN ErrCrWrdSubMem => RETURN MsgCrWrdSubMem;
WHEN ErrCrBitSubMem => RETURN MsgCrBitSubMem;
WHEN ErrCrDatSubMem => RETURN MsgCrDatSubMem;
WHEN ErrCrWrdOut => RETURN MsgCrWrdOut ;
WHEN ErrCrBitOut => RETURN MsgCrBitOut ;
WHEN ErrCrDatOut => RETURN MsgCrDatOut ;
WHEN ErrCrWrdSubOut => RETURN MsgCrWrdSubOut;
WHEN ErrCrBitSubOut => RETURN MsgCrBitSubOut;
WHEN ErrCrDatSubOut => RETURN MsgCrDatSubOut;
WHEN ErrImplOut => RETURN MsgImplOut ;
WHEN ErrReadOut => RETURN MsgReadOut ;
WHEN ErrAssgOut => RETURN MsgAssgOut ;
WHEN ErrAsgXOut => RETURN MsgAsgXOut ;
WHEN ErrAsg0Out => RETURN MsgAsg0Out ;
WHEN ErrAsg1Out => RETURN MsgAsg1Out ;
WHEN ErrAsgZOut => RETURN MsgAsgZOut ;
WHEN ErrAsgSOut => RETURN MsgAsgSOut ;
WHEN ErrAsgXMem => RETURN MsgAsgXMem ;
WHEN ErrAsg0Mem => RETURN MsgAsg0Mem ;
WHEN ErrAsg1Mem => RETURN MsgAsg1Mem ;
WHEN ErrAsgZMem => RETURN MsgAsgZMem ;
WHEN ErrDefMemAct => RETURN MsgDefMemAct ;
WHEN ErrInitMem => RETURN MsgInitMem ;
WHEN ErrMcpWrCont => RETURN MsgMcpWrCont ;
WHEN ErrMcpCpCont => RETURN MsgMcpCpCont ;
WHEN ErrMcpCpRead => RETURN MsgMcpCpRead ;
WHEN ErrMcpRdWrCo => RETURN MsgMcpRdWrCo ;
WHEN ErrMcpCpWrCont => RETURN MsgMcpCpWrCont;
WHEN ErrUnknMemDo => RETURN MsgUnknMemDo ;
WHEN ErrUnknDatDo => RETURN MsgUnknDatDo ;
WHEN ErrUnknSymbol => RETURN MsgUnknSymbol ;
WHEN ErrLdIlgArg => RETURN MsgLdIlgArg ;
WHEN ErrLdAddrRng => RETURN MsgLdAddrRng ;
WHEN ErrLdMemInfo => RETURN MsgLdMemInfo ;
WHEN ErrLdFileEmpty => RETURN MsgLdFileEmpty;
WHEN ErrPrintString => RETURN MsgPrintString;
WHEN OTHERS => RETURN MsgUnknown ;
END CASE;
END;
-- ----------------------------------------------------------------------------
-- Procedure: PrintMemoryMessage
-- Parameters: Routine -- String identifying the calling routine
-- ErrorId -- Input error code for message lookup
-- Info -- Output string or character
-- InfoStr -- Additional output string
-- Info1 -- Additional output integer
-- Info2 -- Additional output integer
-- Info3 -- Additional output integer
-- Description: This procedure prints out a memory status message
-- given the input error id and other status information.
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId)
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT Info : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT Info1 : IN STRING;
CONSTANT Info2 : IN STRING
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info1 & " " & Info2
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT Info : IN CHARACTER
) IS
BEGIN
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & Info
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT InfoStr : IN STRING;
CONSTANT Info1 : IN NATURAL
) IS
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IntToStr(Info1,TmpStr,TmpInt);
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT InfoStr : IN STRING;
CONSTANT Info1 : IN NATURAL;
CONSTANT Info2 : IN NATURAL
) IS
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IntToStr(Info1,TmpStr,TmpInt);
IntToStr(Info2,TmpStr,TmpInt);
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT ErrorId : IN VitalMemoryErrorType;
CONSTANT InfoStr : IN STRING;
CONSTANT Info1 : IN NATURAL;
CONSTANT Info2 : IN NATURAL;
CONSTANT Info3 : IN NATURAL
) IS
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IntToStr(Info1,TmpStr,TmpInt);
IntToStr(Info2,TmpStr,TmpInt);
IntToStr(Info3,TmpStr,TmpInt);
ASSERT FALSE
REPORT Routine & ": " & MemoryMessage(ErrorId) & " " & InfoStr & " " & TmpStr
SEVERITY VitalMemoryErrorSeverity(ErrorId);
END;
-- ----------------------------------------------------------------------------
PROCEDURE PrintMemoryMessage (
CONSTANT Routine : IN STRING;
CONSTANT Table : IN VitalMemoryTableType;
CONSTANT Index : IN INTEGER;
CONSTANT InfoStr : IN STRING
) IS
CONSTANT TableEntries : INTEGER := Table'LENGTH(1);
CONSTANT TableWidth : INTEGER := Table'LENGTH(2);
VARIABLE TmpStr : STRING ( 1 TO 256 ) ;
VARIABLE TmpInt : INTEGER := 1;
BEGIN
IF (Index < 0 AND Index > TableEntries-1) THEN
ASSERT FALSE
REPORT Routine & ": Memory table search failure"
SEVERITY ERROR;
END IF;
ColLoop:
FOR i IN 0 TO TableWidth-1 LOOP
IF (i >= 64) THEN
TmpStr(TmpInt) := '.';
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := '.';
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := '.';
TmpInt := TmpInt + 1;
EXIT ColLoop;
END IF;
TmpStr(TmpInt) := ''';
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := To_MemoryChar(Table(Index,i));
TmpInt := TmpInt + 1;
TmpStr(TmpInt) := ''';
TmpInt := TmpInt + 1;
IF (i < TableWidth-1) THEN
TmpStr(TmpInt) := ',';
TmpInt := TmpInt + 1;
END IF;
END LOOP;
ASSERT FALSE
REPORT Routine & ": Port=" & InfoStr & " TableRow=" & TmpStr
SEVERITY NOTE;
END;
-- ----------------------------------------------------------------------------
-- Procedure: DecodeAddress
-- Parameters: Address - Converted address.
-- AddrFlag - Flag to indicte address match
-- MemoryData - Information about memory characteristics
-- PrevAddressBus - Previous input address value
-- AddressBus - Input address value.
-- Description: This procedure is used for transforming a valid
-- address value to an integer in order to access memory.
-- It performs address bound checking as well.
-- Sets Address to -1 for unknowns
-- Sets Address to -2 for out of range
-- ----------------------------------------------------------------------------
PROCEDURE DecodeAddress (
VARIABLE Address : INOUT INTEGER;
VARIABLE AddrFlag : INOUT VitalMemorySymbolType;
VARIABLE MemoryData : IN VitalMemoryDataType;
CONSTANT PrevAddressBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector
) IS
VARIABLE Power : NATURAL;
VARIABLE AddrUnkn : BOOLEAN;
BEGIN
Power := 0;
AddrUnkn := FALSE;
-- It is assumed that always Address'LEFT represents the Most significant bit.
FOR i IN AddressBus'RANGE LOOP
Power := Power * 2;
IF (AddressBus(i) /= '1' AND AddressBus(i) /= '0') THEN
AddrUnkn := TRUE;
Power := 0;
EXIT;
ELSIF (AddressBus(i) = '1') THEN
Power := Power + 1;
END IF;
END LOOP;
Address := Power;
AddrFlag := 'g';
IF (AddrUnkn) THEN
AddrFlag := 'u'; -- unknown addr
Address := -1;
END IF;
IF ( Power > (MemoryData.NoOfWords - 1)) THEN
AddrFlag := 'i'; -- invalid addr
Address := -2;
END IF;
IF (PrevAddressBus /= AddressBus) THEN
CASE AddrFlag IS
WHEN 'g' => AddrFlag := 'G';
WHEN 'u' => AddrFlag := 'U';
WHEN 'i' => AddrFlag := 'I';
WHEN OTHERS =>
ASSERT FALSE REPORT
"DecodeAddress: Internal error. [AddrFlag]="
& To_MemoryChar(AddrFlag)
SEVERITY ERROR;
END CASE;
END IF;
END DecodeAddress;
-- ----------------------------------------------------------------------------
-- Procedure: DecodeData
-- Parameters: DataFlag - Flag to indicte data match
-- PrevDataInBus - Previous input data value
-- DataInBus - Input data value.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used for interpreting the input data
-- as a data flag for subsequent table matching.
-- ----------------------------------------------------------------------------
PROCEDURE DecodeData (
VARIABLE DataFlag : INOUT VitalMemorySymbolType;
CONSTANT PrevDataInBus : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL
) IS
VARIABLE DataUnkn : BOOLEAN := FALSE;
BEGIN
FOR i IN LowBit TO HighBit LOOP
IF DataInBus(i) /= '1' AND DataInBus(i) /= '0' THEN
DataUnkn := TRUE;
EXIT;
END IF;
END LOOP;
DataFlag := 'g';
IF (DataUnkn) THEN
DataFlag := 'u'; -- unknown addr
END IF;
IF (PrevDataInBus(HighBit DOWNTO LowBit) /=
DataInBus(HighBit DOWNTO LowBit)) THEN
CASE DataFlag IS
WHEN 'g' => DataFlag := 'G';
WHEN 'u' => DataFlag := 'U';
WHEN OTHERS =>
ASSERT FALSE REPORT
"DecodeData: Internal error. [DataFlag]="
& To_MemoryChar(DataFlag)
SEVERITY ERROR;
END CASE;
END IF;
END DecodeData;
-- ----------------------------------------------------------------------------
-- Procedure: WriteMemory
-- Parameters: MemoryPtr - Pointer to the memory array.
-- DataInBus - Input Data to be written.
-- Address - Address of the memory location.
-- BitPosition - Position of bit in memory location.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used to write to a memory location
-- on a bit/byte/word basis.
-- The high bit and low bit offset are used for byte write
-- operations.These parameters specify the data byte for write.
-- In the case of word write the complete memory word is used.
-- This procedure is overloaded for bit,byte and word write
-- memory operations.The number of parameters may vary.
-- ----------------------------------------------------------------------------
PROCEDURE WriteMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL
) IS
VARIABLE TmpData : std_logic_vector(DataInBus'LENGTH - 1 DOWNTO 0);
BEGIN
-- Address bound checking.
IF ( Address < 0 OR Address > (MemoryPtr.NoOfWords - 1)) THEN
PrintMemoryMessage ( "WriteMemory", ErrPrintString,
"Aborting write operation as address is out of range.") ;
RETURN;
END IF;
TmpData := To_UX01(DataInBus);
FOR i in LowBit to HighBit LOOP
MemoryPtr.MemoryArrayPtr(Address).all(i) := TmpData(i);
END LOOP;
END WriteMemory;
-- ----------------------------------------------------------------------------
PROCEDURE WriteMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT BitPosition : IN NATURAL
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := BitPosition;
LowBit := BitPosition;
WriteMemory (MemoryPtr, DataInBus, Address, HighBit, LowBit);
END WriteMemory;
-- ----------------------------------------------------------------------------
PROCEDURE WriteMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := MemoryPtr.NoOfBitsPerWord - 1;
LowBit := 0;
WriteMemory (MemoryPtr, DataInBus, Address, HighBit, LowBit);
END WriteMemory;
-- ----------------------------------------------------------------------------
-- Procedure: ReadMemory
-- Parameters: MemoryPtr - Pointer to the memory array.
-- DataOut - Output Data to be read in this.
-- Address - Address of the memory location.
-- BitPosition - Position of bit in memory location.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used to read from a memory location
-- on a bit/byte/word basis.
-- The high bit and low bit offset are used for byte write
-- operations.These parameters specify the data byte for
-- read.In the case of word write the complete memory word
-- is used.This procedure is overloaded for bit,byte and
-- word write memory operations.The number of parameters
-- may vary.
-- ----------------------------------------------------------------------------
PROCEDURE ReadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
VARIABLE DataOut : OUT std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL
) IS
VARIABLE DataOutTmp : std_logic_vector(MemoryPtr.NoOfBitsPerWord-1 DOWNTO 0);
VARIABLE length : NATURAL := (HighBit - LowBit + 1);
BEGIN
-- Address bound checking.
IF ( Address > (MemoryPtr.NoOfWords - 1)) THEN
PrintMemoryMessage (
"ReadMemory",ErrInvaAddr,
"[Address,NoOfWords]=",Address,MemoryPtr.NoOfWords
);
FOR i in LowBit to HighBit LOOP
DataOutTmp(i) := 'X';
END LOOP;
ELSE
FOR i in LowBit to HighBit LOOP
DataOutTmp(i) := MemoryPtr.MemoryArrayPtr (Address).all(i);
END LOOP;
END IF;
DataOut := DataOutTmp;
END ReadMemory;
-- ----------------------------------------------------------------------------
PROCEDURE ReadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
VARIABLE DataOut : OUT std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT BitPosition : IN NATURAL
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := BitPosition;
LowBit := BitPosition;
ReadMemory (MemoryPtr, DataOut, Address, HighBit, LowBit);
END ReadMemory;
-- ----------------------------------------------------------------------------
PROCEDURE ReadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
VARIABLE DataOut : OUT std_logic_vector;
CONSTANT Address : IN INTEGER
) IS
VARIABLE HighBit : NATURAL;
VARIABLE LowBit : NATURAL;
BEGIN
HighBit := MemoryPtr.NoOfBitsPerWord - 1;
LowBit := 0;
ReadMemory (MemoryPtr, DataOut, Address, HighBit, LowBit);
END ReadMemory;
-- ----------------------------------------------------------------------------
-- Procedure: LoadMemory
-- Parameters: MemoryPtr - Pointer to the memory array.
-- FileName - Name of the output file.
-- HighBit - High bit offset value.
-- LowBit - Low bit offset value.
-- Description: This procedure is used to load the contents of the memory
-- from a specified input file.
-- The high bit and low bit offset are used so that same task
-- can be used for all bit/byte/word write operations.
-- In the case of a bit write RAM the HighBit and LowBit have
-- the same value.
-- This procedure is overloaded for word write operations.
-- ----------------------------------------------------------------------------
PROCEDURE LoadMemory (
VARIABLE MemoryPtr : INOUT VitalMemoryDataType;
CONSTANT FileName : IN STRING;
CONSTANT BinaryFile : IN BOOLEAN := FALSE
) IS
FILE Fptr : TEXT OPEN read_mode IS FileName;
VARIABLE OneLine : LINE;
VARIABLE Ignore : CHARACTER;
VARIABLE Index : NATURAL := 1;
VARIABLE LineNo : NATURAL := 0;
VARIABLE Address : INTEGER := 0;
VARIABLE DataInBus : std_logic_vector(MemoryPtr.NoOfBitsPerWord-1 DOWNTO 0);
VARIABLE AddrStr : STRING(1 TO 80) ;
VARIABLE DataInStr : STRING(1 TO 255) ;
BEGIN
IF (ENDFILE(fptr)) THEN
PrintMemoryMessage (MsgVDM, ErrLdFileEmpty,
"[FileName]="&FileName);
RETURN;
END IF ;
PrintMemoryMessage (
MsgVDM,ErrLdMemInfo, "[FileName]="&FileName
);
WHILE (NOT ENDFILE(fptr)) LOOP
ReadLine(Fptr, OneLine);
LineNo := LineNo + 1 ;
-- First ignoring leading spaces.
WHILE (OneLine'LENGTH /= 0 and IsSpace(OneLine(1))) LOOP
READ (OneLine, Ignore) ; -- Ignoring the space character.
END LOOP ;
-- Note that, by now oneline has been "stripped" of its leading spaces.
IF ( OneLine(1) = '@' ) THEN
READ (OneLine, Ignore); -- Ignore the '@' character and read the string.
-- Now strip off spaces, if any, between '@' and Address string.
WHILE (OneLine'LENGTH /= 0 and IsSpace(OneLine(1))) LOOP
READ (OneLine, Ignore) ; -- Ignoring the space character.
END LOOP ;
-- Now get the string which represents the address into string variable.
Index := 1;
WHILE (OneLine'LENGTH /= 0 AND (NOT(IsSpace(OneLine(1))))) LOOP
READ(OneLine, AddrStr(Index));
Index := Index + 1;
END LOOP ;
AddrStr(Index) := NUL;
-- Now convert the hex string into a hex integer
Address := HexToInt(AddrStr) ;
ELSE
IF ( LineNo /= 1 ) THEN
Address := Address + 1;
END IF;
END IF ;
IF ( Address > (MemoryPtr.NoOfWords - 1) ) THEN
PrintMemoryMessage (MsgVDM, ErrLdAddrRng,
"[Address,lineno]=", Address, LineNo) ;
EXIT ;
END IF;
-- Now strip off spaces, between Address string and DataInBus string.
WHILE (OneLine'LENGTH /= 0 AND IsSpace(OneLine(1))) LOOP
READ (OneLine, Ignore) ; -- Ignoring the space character.
END LOOP ;
Index := 1;
WHILE (OneLine'LENGTH /= 0 AND (NOT(IsSpace(OneLine(1))))) LOOP
READ(OneLine, DataInStr(Index));
Index := Index + 1;
END LOOP ;
DataInStr(Index) := NUL;
IF (BinaryFile) THEN
DataInBus := BinToBitv (DataInStr);
ELSE
DataInBus := HexToBitv (DataInStr);
END IF ;
WriteMemory (MemoryPtr, DataInBus, Address);
END LOOP ;
END LoadMemory;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryMatch
-- Parameters: Symbol - Symbol from memory table
-- TestFlag - Interpreted data or address symbol
-- In2 - input from VitalMemoryTable procedure
-- to memory table
-- In2LastValue - Previous value of input
-- Err - TRUE if symbol is not a valid input symbol
-- ReturnValue - TRUE if match occurred
-- Description: This procedure sets ReturnValue to true if in2 matches
-- symbol (from the memory table). If symbol is an edge
-- value edge is set to true and in2 and in2LastValue are
-- checked against symbol. Err is set to true if symbol
-- is an invalid value for the input portion of the memory
-- table.
-- ----------------------------------------------------------------------------
PROCEDURE MemoryMatch (
CONSTANT Symbol : IN VitalMemorySymbolType;
CONSTANT In2 : IN std_ulogic;
CONSTANT In2LastValue : IN std_ulogic;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
IF (NOT ValidMemoryTableInput(Symbol) ) THEN
PrintMemoryMessage(MsgVMT,ErrUnknSymbol,To_MemoryChar(Symbol));
Err := TRUE;
ReturnValue := FALSE;
ELSE
ReturnValue := MemoryTableMatch(To_X01(In2LastValue), To_X01(In2), Symbol);
Err := FALSE;
END IF;
END;
-- ----------------------------------------------------------------------------
PROCEDURE MemoryMatch (
CONSTANT Symbol : IN VitalMemorySymbolType;
CONSTANT TestFlag : IN VitalMemorySymbolType;
VARIABLE Err : OUT BOOLEAN;
VARIABLE ReturnValue : OUT BOOLEAN
) IS
BEGIN
Err := FALSE;
ReturnValue := FALSE;
CASE Symbol IS
WHEN 'g'|'u'|'i'|'G'|'U'|'I'|'-'|'*'|'S' =>
IF (Symbol = TestFlag) THEN
ReturnValue := TRUE;
ELSE
CASE Symbol IS
WHEN '-' =>
ReturnValue := TRUE;
Err := FALSE;
WHEN '*' =>
IF (TestFlag = 'G' OR
TestFlag = 'U' OR
TestFlag = 'I') THEN
ReturnValue := TRUE;
Err := FALSE;
END IF;
WHEN 'S' =>
IF (TestFlag = 'g' OR
TestFlag = 'u' OR
TestFlag = 'i') THEN
ReturnValue := TRUE;
Err := FALSE;
END IF;
WHEN OTHERS =>
ReturnValue := FALSE;
END CASE;
END IF;
WHEN OTHERS =>
Err := TRUE;
RETURN;
END CASE;
END;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryTableCorruptMask
-- Description: Compute memory and data corruption masks for memory table
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableCorruptMask (
VARIABLE CorruptMask : OUT std_logic_vector;
CONSTANT Action : IN VitalMemorySymbolType;
CONSTANT EnableIndex : IN INTEGER;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER
) IS
VARIABLE CorruptMaskTmp : std_logic_vector (CorruptMask'RANGE)
:= (OTHERS => '0');
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE HighBit : INTEGER;
VARIABLE LowBit : INTEGER;
BEGIN
CASE (Action) IS
WHEN 'c'|'l'|'e' =>
-- Corrupt whole word
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
WHEN 'd'|'C'|'L'|'D'|'E' =>
-- Process corruption below
WHEN OTHERS =>
-- No data or memory corruption
CorruptMaskTmp := (OTHERS => '0');
CorruptMask := CorruptMaskTmp;
RETURN;
END CASE;
IF (Action = 'd') THEN
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
END IF;
-- Remaining are subword cases 'C', 'L', 'D', 'E'
CorruptMaskTmp := (OTHERS => '0');
LowBit := 0;
HighBit := BitsPerSubWord-1;
SubWordLoop:
FOR i IN 0 TO BitsPerEnable-1 LOOP
IF (i = EnableIndex) THEN
FOR j IN HighBit TO LowBit LOOP
CorruptMaskTmp(j) := 'X';
END LOOP;
END IF;
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END LOOP;
CorruptMask := CorruptMaskTmp;
RETURN;
END;
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableCorruptMask (
VARIABLE CorruptMask : OUT std_logic_vector;
CONSTANT Action : IN VitalMemorySymbolType
) IS
VARIABLE CorruptMaskTmp : std_logic_vector (0 TO CorruptMask'LENGTH-1)
:= (OTHERS => '0');
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE HighBit : INTEGER;
VARIABLE LowBit : INTEGER;
BEGIN
CASE (Action) IS
WHEN 'c'|'l'|'d'|'e'|'C'|'L'|'D'|'E' =>
-- Corrupt whole word
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
WHEN OTHERS =>
-- No data or memory corruption
CorruptMaskTmp := (OTHERS => '0');
CorruptMask := CorruptMaskTmp;
RETURN;
END CASE;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryTableCorruptMask
-- Description: Compute memory and data corruption masks for violation table
-- ----------------------------------------------------------------------------
PROCEDURE ViolationTableCorruptMask (
VARIABLE CorruptMask : OUT std_logic_vector;
CONSTANT Action : IN VitalMemorySymbolType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN std_logic_vector;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT TableIndex : IN INTEGER;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER
) IS
VARIABLE CorruptMaskTmp : std_logic_vector (CorruptMask'RANGE)
:= (OTHERS => '0');
VARIABLE ViolMaskTmp : std_logic_vector (CorruptMask'RANGE)
:= (OTHERS => '0');
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE HighBit : INTEGER;
VARIABLE LowBit : INTEGER;
CONSTANT ViolFlagsSize : INTEGER := ViolationFlags'LENGTH;
CONSTANT ViolFlArySize : INTEGER := ViolationFlagsArray'LENGTH;
CONSTANT TableEntries : INTEGER := ViolationTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := ViolationTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
BEGIN
CASE (Action) IS
WHEN 'c'|'l'|'e' =>
-- Corrupt whole word
CorruptMaskTmp := (OTHERS => 'X');
CorruptMask := CorruptMaskTmp;
RETURN;
WHEN 'd'|'C'|'L'|'D'|'E' =>
-- Process corruption below
WHEN OTHERS =>
-- No data or memory corruption
CorruptMaskTmp := (OTHERS => '0');
CorruptMask := CorruptMaskTmp;
RETURN;
END CASE;
RowLoop: -- Check each element of the ViolationFlags
FOR j IN 0 TO ViolFlagsSize LOOP
IF (j = ViolFlagsSize) THEN
ViolFlAryPosn := 0;
RowLoop2: -- Check relevant elements of the ViolationFlagsArray
FOR k IN 0 TO MemActionNdx - ViolFlagsSize - 1 LOOP
IF (ViolationTable(TableIndex, k + ViolFlagsSize) = 'X') THEN
MaskLoop: -- Set the 'X' bits in the violation mask
FOR m IN INTEGER RANGE 0 TO CorruptMask'LENGTH-1 LOOP
IF (m <= ViolationSizesArray(k)-1) THEN
ViolMaskTmp(m) := ViolMaskTmp(m) XOR
ViolationFlagsArray(ViolFlAryPosn+m);
ELSE
EXIT MaskLoop;
END IF;
END LOOP;
END IF;
ViolFlAryPosn := ViolFlAryPosn + ViolationSizesArray(k);
END LOOP;
ELSE
IF (ViolationTable(TableIndex, j) = 'X') THEN
ViolMaskTmp(0) := ViolMaskTmp(0) XOR ViolationFlags(j);
END IF;
END IF;
END LOOP;
IF (Action = 'd') THEN
CorruptMask := ViolMaskTmp;
RETURN;
END IF;
-- Remaining are subword cases 'C', 'L', 'D', 'E'
CorruptMaskTmp := (OTHERS => '0');
LowBit := 0;
HighBit := BitsPerSubWord-1;
SubWordLoop:
FOR i IN 0 TO BitsPerEnable-1 LOOP
IF (ViolMaskTmp(i) = 'X') THEN
FOR j IN HighBit TO LowBit LOOP
CorruptMaskTmp(j) := 'X';
END LOOP;
END IF;
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END LOOP;
CorruptMask := CorruptMaskTmp;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: MemoryTableLookUp
-- Parameters: MemoryAction - Output memory action to be performed
-- DataAction - Output data action to be performed
-- PrevControls - Previous data in for edge detection
-- PrevEnableBus - Previous enables for edge detection
-- Controls - Agregate of scalar control lines
-- EnableBus - Concatenation of vector control lines
-- EnableIndex - Current slice of vector control lines
-- AddrFlag - Matching symbol from address decoding
-- DataFlag - Matching symbol from data decoding
-- MemoryTable - Input memory action table
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
--
-- Description: This function is used to find the output of the
-- MemoryTable corresponding to a given set of inputs.
--
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableLookUp (
VARIABLE MemoryAction : OUT VitalMemorySymbolType;
VARIABLE DataAction : OUT VitalMemorySymbolType;
VARIABLE MemoryCorruptMask : OUT std_logic_vector;
VARIABLE DataCorruptMask : OUT std_logic_vector;
CONSTANT PrevControls : IN std_logic_vector;
CONSTANT Controls : IN std_logic_vector;
CONSTANT AddrFlag : IN VitalMemorySymbolType;
CONSTANT DataFlag : IN VitalMemorySymbolType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
CONSTANT ControlsSize : INTEGER := Controls'LENGTH;
CONSTANT TableEntries : INTEGER := MemoryTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := MemoryTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
CONSTANT DataInBusNdx : INTEGER := TableWidth - 3;
CONSTANT AddressBusNdx : INTEGER := TableWidth - 4;
VARIABLE AddrFlagTable : VitalMemorySymbolType;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
VARIABLE TableAlias : VitalMemoryTableType(
0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= MemoryTable;
BEGIN
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the Controls
FOR j IN 0 TO ControlsSize LOOP
IF (j = ControlsSize) THEN
-- a match occurred, now check AddrFlag, DataFlag
MemoryMatch(TableAlias(i,AddressBusNdx),AddrFlag,Err,Match);
IF (Match) THEN
MemoryMatch(TableAlias(i,DataInBusNdx),DataFlag,Err,Match);
IF (Match) THEN
MemoryTableCorruptMask (
CorruptMask => MemoryCorruptMask ,
Action => TableAlias(i, MemActionNdx)
);
MemoryTableCorruptMask (
CorruptMask => DataCorruptMask ,
Action => TableAlias(i, DatActionNdx)
);
-- get the return memory and data actions
MemoryAction := TableAlias(i, MemActionNdx);
DataAction := TableAlias(i, DatActionNdx);
-- DEBUG: The lines below report table search
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,TableAlias,i,PortName);
END IF;
-- DEBUG: The lines above report table search
RETURN;
END IF;
END IF;
ELSE
-- Match memory table inputs
MemoryMatch ( TableAlias(i,j),
Controls(j), PrevControls(j),
Err, Match);
END IF;
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
-- no match found, return default action
MemoryAction := 's'; -- no change to memory
DataAction := 'S'; -- no change to dataout
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,ErrDefMemAct,HeaderMsg,PortName);
END IF;
RETURN;
END;
-- ----------------------------------------------------------------------------
PROCEDURE MemoryTableLookUp (
VARIABLE MemoryAction : OUT VitalMemorySymbolType;
VARIABLE DataAction : OUT VitalMemorySymbolType;
VARIABLE MemoryCorruptMask : OUT std_logic_vector;
VARIABLE DataCorruptMask : OUT std_logic_vector;
CONSTANT PrevControls : IN std_logic_vector;
CONSTANT PrevEnableBus : IN std_logic_vector;
CONSTANT Controls : IN std_logic_vector;
CONSTANT EnableBus : IN std_logic_vector;
CONSTANT EnableIndex : IN INTEGER;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER;
CONSTANT AddrFlag : IN VitalMemorySymbolType;
CONSTANT DataFlag : IN VitalMemorySymbolType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
CONSTANT ControlsSize : INTEGER := Controls'LENGTH;
CONSTANT TableEntries : INTEGER := MemoryTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := MemoryTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
CONSTANT DataInBusNdx : INTEGER := TableWidth - 3;
CONSTANT AddressBusNdx : INTEGER := TableWidth - 4;
VARIABLE AddrFlagTable : VitalMemorySymbolType;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
VARIABLE TableAlias : VitalMemoryTableType(
0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= MemoryTable;
BEGIN
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the Controls
FOR j IN 0 TO ControlsSize LOOP
IF (j = ControlsSize) THEN
-- a match occurred, now check EnableBus, AddrFlag, DataFlag
IF (EnableIndex >= 0) THEN
RowLoop2: -- Check relevant elements of the EnableBus
FOR k IN 0 TO AddressBusNdx - ControlsSize - 1 LOOP
MemoryMatch ( TableAlias(i,k + ControlsSize),
EnableBus(k * BitsPerEnable + EnableIndex),
PrevEnableBus(k * BitsPerEnable + EnableIndex),
Err, Match);
EXIT RowLoop2 WHEN NOT(Match);
END LOOP;
END IF;
IF (Match) THEN
MemoryMatch(TableAlias(i,AddressBusNdx),AddrFlag,Err,Match);
IF (Match) THEN
MemoryMatch(TableAlias(i,DataInBusNdx),DataFlag,Err,Match);
IF (Match) THEN
MemoryTableCorruptMask (
CorruptMask => MemoryCorruptMask ,
Action => TableAlias(i, MemActionNdx),
EnableIndex => EnableIndex ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
MemoryTableCorruptMask (
CorruptMask => DataCorruptMask ,
Action => TableAlias(i, DatActionNdx),
EnableIndex => EnableIndex ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
-- get the return memory and data actions
MemoryAction := TableAlias(i, MemActionNdx);
DataAction := TableAlias(i, DatActionNdx);
-- DEBUG: The lines below report table search
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,TableAlias,i,PortName);
END IF;
-- DEBUG: The lines above report table search
RETURN;
END IF;
END IF;
END IF;
ELSE
-- Match memory table inputs
MemoryMatch ( TableAlias(i,j),
Controls(j), PrevControls(j),
Err, Match);
END IF;
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
-- no match found, return default action
MemoryAction := 's'; -- no change to memory
DataAction := 'S'; -- no change to dataout
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMT,ErrDefMemAct,HeaderMsg,PortName);
END IF;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: ViolationTableLookUp
-- Parameters: MemoryAction - Output memory action to be performed
-- DataAction - Output data action to be performed
-- TimingDataArray - This is currently not used (comment out)
-- ViolationArray - Aggregation of violation variables
-- ViolationTable - Input memory violation table
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
-- Description: This function is used to find the output of the
-- ViolationTable corresponding to a given set of inputs.
-- ----------------------------------------------------------------------------
PROCEDURE ViolationTableLookUp (
VARIABLE MemoryAction : OUT VitalMemorySymbolType;
VARIABLE DataAction : OUT VitalMemorySymbolType;
VARIABLE MemoryCorruptMask : OUT std_logic_vector;
VARIABLE DataCorruptMask : OUT std_logic_vector;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN std_logic_vector;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT BitsPerWord : IN INTEGER;
CONSTANT BitsPerSubWord : IN INTEGER;
CONSTANT BitsPerEnable : IN INTEGER;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
CONSTANT ViolFlagsSize : INTEGER := ViolationFlags'LENGTH;
CONSTANT ViolFlArySize : INTEGER := ViolationFlagsArray'LENGTH;
VARIABLE ViolFlAryPosn : INTEGER;
VARIABLE ViolFlAryItem : std_ulogic;
CONSTANT ViolSzArySize : INTEGER := ViolationSizesArray'LENGTH;
CONSTANT TableEntries : INTEGER := ViolationTable'LENGTH(1);
CONSTANT TableWidth : INTEGER := ViolationTable'LENGTH(2);
CONSTANT DatActionNdx : INTEGER := TableWidth - 1;
CONSTANT MemActionNdx : INTEGER := TableWidth - 2;
VARIABLE HighBit : NATURAL := 0;
VARIABLE LowBit : NATURAL := 0;
VARIABLE Match : BOOLEAN;
VARIABLE Err : BOOLEAN := FALSE;
VARIABLE TableAlias : VitalMemoryTableType(
0 TO TableEntries - 1,
0 TO TableWidth - 1)
:= ViolationTable;
BEGIN
ColLoop: -- Compare each entry in the table
FOR i IN TableAlias'RANGE(1) LOOP
RowLoop: -- Check each element of the ViolationFlags
FOR j IN 0 TO ViolFlagsSize LOOP
IF (j = ViolFlagsSize) THEN
ViolFlAryPosn := 0;
RowLoop2: -- Check relevant elements of the ViolationFlagsArray
FOR k IN 0 TO MemActionNdx - ViolFlagsSize - 1 LOOP
ViolFlAryItem := '0';
SubwordLoop: -- Check for 'X' in ViolationFlagsArray chunk
FOR s IN ViolFlAryPosn TO ViolFlAryPosn+ViolationSizesArray(k)-1 LOOP
IF (ViolationFlagsArray(s) = 'X') THEN
ViolFlAryItem := 'X';
EXIT SubwordLoop;
END IF;
END LOOP;
MemoryMatch ( TableAlias(i,k + ViolFlagsSize),
ViolFlAryItem,ViolFlAryItem,
Err, Match);
ViolFlAryPosn := ViolFlAryPosn + ViolationSizesArray(k);
EXIT RowLoop2 WHEN NOT(Match);
END LOOP;
IF (Match) THEN
-- Compute memory and data corruption masks
ViolationTableCorruptMask(
CorruptMask => MemoryCorruptMask ,
Action => TableAlias(i, MemActionNdx),
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => ViolationFlagsArray ,
ViolationSizesArray => ViolationSizesArray ,
ViolationTable => ViolationTable ,
TableIndex => i ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
ViolationTableCorruptMask(
CorruptMask => DataCorruptMask ,
Action => TableAlias(i, DatActionNdx),
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => ViolationFlagsArray ,
ViolationSizesArray => ViolationSizesArray ,
ViolationTable => ViolationTable ,
TableIndex => i ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable
);
-- get the return memory and data actions
MemoryAction := TableAlias(i, MemActionNdx);
DataAction := TableAlias(i, DatActionNdx);
-- DEBUG: The lines below report table search
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMV,TableAlias,i,PortName);
END IF;
-- DEBUG: The lines above report table search
RETURN;
END IF;
ELSE
-- Match violation table inputs
Err := FALSE;
Match := FALSE;
IF (TableAlias(i,j) /= 'X' AND
TableAlias(i,j) /= '0' AND
TableAlias(i,j) /= '-') THEN
Err := TRUE;
ELSIF (TableAlias(i,j) = '-' OR
(TableAlias(i,j) = 'X' AND ViolationFlags(j) = 'X') OR
(TableAlias(i,j) = '0' AND ViolationFlags(j) = '0')) THEN
Match := TRUE;
END IF;
END IF;
EXIT RowLoop WHEN NOT(Match);
EXIT ColLoop WHEN Err;
END LOOP RowLoop;
END LOOP ColLoop;
-- no match found, return default action
MemoryAction := 's'; -- no change to memory
DataAction := 'S'; -- no change to dataout
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMV,ErrDefMemAct,HeaderMsg,PortName);
END IF;
RETURN;
END;
-- ----------------------------------------------------------------------------
-- Procedure: HandleMemoryAction
-- Parameters: MemoryData - Pointer to memory data structure
-- PortFlag - Indicates read/write mode of port
-- CorruptMask - XOR'ed with DataInBus when corrupting
-- DataInBus - Current data bus in
-- Address - Current address integer
-- HighBit - Current address high bit
-- LowBit - Current address low bit
-- MemoryTable - Input memory action table
-- MemoryAction - Memory action to be performed
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
-- Description: This procedure performs the specified memory action on
-- the input memory data structure.
-- ----------------------------------------------------------------------------
PROCEDURE HandleMemoryAction (
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagType;
CONSTANT CorruptMask : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT MemoryAction : IN VitalMemorySymbolType;
CONSTANT CallerName : IN STRING;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE DataInTmp : std_logic_vector(DataInBus'RANGE)
:= DataInBus;
BEGIN
-- Handle the memory action
CASE MemoryAction IS
WHEN 'w' =>
-- Writing data to memory
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrWrDatMem,HeaderMsg,PortName);
END IF;
WriteMemory(MemoryData,DataInBus,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN 's' =>
-- Retaining previous memory contents
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrNoChgMem,HeaderMsg,PortName);
END IF;
-- Set memory current to quiet state
PortFlag.MemoryCurrent := READ;
WHEN 'c' =>
-- Corrupting entire memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrAllMem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => 'X');
-- No need to CorruptMask
FOR i IN 0 TO MemoryData.NoOfWords-1 LOOP
WriteMemory(MemoryData,DataInTmp,i);
END LOOP;
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'l' =>
-- Corrupting a word in memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdMem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => 'X');
-- No need to CorruptMask
WriteMemory(MemoryData,DataInTmp,Address);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'd' =>
-- Corrupting a single bit in memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'e' =>
-- Corrupting a word with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
IF (DataInTmp /= DataInBus) THEN
DataInTmp := (OTHERS => 'X');
-- No need to CorruptMask
WriteMemory(MemoryData,DataInTmp,Address);
END IF;
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'C' =>
-- Corrupting a sub-word entire memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrAllSubMem,HeaderMsg,PortName);
END IF;
FOR i IN 0 TO MemoryData.NoOfWords-1 LOOP
ReadMemory(MemoryData,DataInTmp,i);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,i,HighBit,LowBit);
END LOOP;
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'L' =>
-- Corrupting a sub-word in memory with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdSubMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'D' =>
-- Corrupting a single bit of a memory sub-word with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitSubMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
DataInTmp := DataInTmp XOR CorruptMask;
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
PortFlag.MemoryCurrent := CORRUPT;
WHEN 'E' =>
-- Corrupting a sub-word with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatSubMem,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataInTmp,Address);
IF (DataInBus(HighBit DOWNTO LowBit) /=
DataInTmp(HighBit DOWNTO LowBit)) THEN
DataInTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
WriteMemory(MemoryData,DataInTmp,Address,HighBit,LowBit);
END IF;
--PortFlag := WRITE;
PortFlag.MemoryCurrent := CORRUPT;
WHEN '0' =>
-- Assigning low level to memory location
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg0Mem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => '0');
WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN '1' =>
-- Assigning high level to memory location
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg1Mem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => '1');
WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN 'Z' =>
-- Assigning high impedence to memory location
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsgZMem,HeaderMsg,PortName);
END IF;
DataInTmp := (OTHERS => 'Z');
WriteMemory(MemoryData,DataInTmp,Address, HighBit, LowBit);
PortFlag.MemoryCurrent := WRITE;
WHEN OTHERS =>
-- Unknown memory action
PortFlag.MemoryCurrent := UNDEF;
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrUnknMemDo,HeaderMsg,PortName);
END IF;
END CASE;
-- Note: HandleMemoryAction does not change the PortFlag.OutputDisable
END;
-- ----------------------------------------------------------------------------
-- Procedure: HandleDataAction
-- Parameters: DataOutBus - Output result of the data action
-- MemoryData - Input pointer to memory data structure
-- PortFlag - Indicates read/write mode of port
-- CorruptMask - XOR'ed with DataInBus when corrupting
-- DataInBus - Current data bus in
-- Address - Current address integer
-- HighBit - Current address high bit
-- LowBit - Current address low bit
-- MemoryTable - Input memory action table
-- DataAction - Data action to be performed
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control message output
-- Description: This procedure performs the specified data action based
-- on the input memory data structure. Checks whether
-- the previous state is HighZ. If yes then portFlag
-- should be NOCHANGE for VMPD to ignore IORetain
-- corruption. The idea is that the first Z should be
-- propagated but later ones should be ignored.
-- ----------------------------------------------------------------------------
PROCEDURE HandleDataAction (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagType;
CONSTANT CorruptMask : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT Address : IN INTEGER;
CONSTANT HighBit : IN NATURAL;
CONSTANT LowBit : IN NATURAL;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT DataAction : IN VitalMemorySymbolType;
CONSTANT CallerName : IN STRING;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
BEGIN
-- Handle the data action
CASE DataAction IS
WHEN 'l' =>
-- Corrupting data out with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdOut,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => 'X');
-- No need to CorruptMask
PortFlag.DataCurrent := CORRUPT;
WHEN 'd' =>
-- Corrupting a single bit of data out with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitOut,HeaderMsg,PortName);
END IF;
DataOutTmp(HighBit DOWNTO LowBit) :=
DataOutTmp(HighBit DOWNTO LowBit) XOR
CorruptMask(HighBit DOWNTO LowBit);
PortFlag.DataCurrent := CORRUPT;
WHEN 'e' =>
-- Corrupting data out with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
IF (DataOutTmp /= DataInBus) THEN
DataOutTmp := (OTHERS => 'X');
-- No need to CorruptMask
END IF;
PortFlag.DataCurrent := CORRUPT;
WHEN 'L' =>
-- Corrupting data out sub-word with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrWrdSubOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
DataOutTmp(HighBit DOWNTO LowBit) :=
DataOutTmp(HighBit DOWNTO LowBit) XOR
CorruptMask(HighBit DOWNTO LowBit);
PortFlag.DataCurrent := CORRUPT;
WHEN 'D' =>
-- Corrupting a single bit of data out sub-word with 'X'
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrBitSubOut,HeaderMsg,PortName);
END IF;
DataOutTmp(HighBit DOWNTO LowBit) :=
DataOutTmp(HighBit DOWNTO LowBit) XOR
CorruptMask(HighBit DOWNTO LowBit);
PortFlag.DataCurrent := CORRUPT;
WHEN 'E' =>
-- Corrupting data out sub-word with 'X' based on data in
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrCrDatSubOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
IF (DataInBus(HighBit DOWNTO LowBit) /=
DataOutTmp(HighBit DOWNTO LowBit)) THEN
DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
-- No need to CorruptMask
END IF;
PortFlag.DataCurrent := CORRUPT;
WHEN 'M' =>
-- Implicit read from memory to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrImplOut,HeaderMsg,PortName);
END IF;
PortFlag.DataCurrent := READ;
WHEN 'm' =>
-- Reading data from memory to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrReadOut,HeaderMsg,PortName);
END IF;
ReadMemory(MemoryData,DataOutTmp,Address);
PortFlag.DataCurrent := READ;
WHEN 't' =>
-- Transferring from data in to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAssgOut,HeaderMsg,PortName);
END IF;
DataOutTmp := DataInBus;
PortFlag.DataCurrent := READ;
WHEN '0' =>
-- Assigning low level to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg0Out,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => '0');
PortFlag.DataCurrent := READ;
WHEN '1' =>
-- Assigning high level to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsg1Out,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => '1');
PortFlag.DataCurrent := READ;
WHEN 'Z' =>
-- Assigning high impedence to data out
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsgZOut,HeaderMsg,PortName);
END IF;
DataOutTmp := (OTHERS => 'Z');
PortFlag.DataCurrent := HIGHZ;
WHEN 'S' =>
-- Keeping data out at steady value
PortFlag.OutputDisable := TRUE;
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrAsgSOut,HeaderMsg,PortName);
END IF;
WHEN OTHERS =>
-- Unknown data action
PortFlag.DataCurrent := UNDEF;
IF (MsgOn) THEN
PrintMemoryMessage(CallerName,ErrUnknDatDo,HeaderMsg,PortName);
END IF;
END CASE;
DataOutBus(HighBit DOWNTO LowBit) := DataOutTmp(HighBit DOWNTO LowBit);
END;
-- ----------------------------------------------------------------------------
-- Memory Table Modeling Primitives
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- Procedure: VitalDeclareMemory
-- Parameters: NoOfWords - Number of words in the memory
-- NoOfBitsPerWord - Number of bits per word in memory
-- NoOfBitsPerSubWord - Number of bits per sub word
-- MemoryLoadFile - Name of data file to load
-- Description: This function is intended to be used to initialize
-- memory data declarations, i.e. to be executed duing
-- simulation elaboration time. Handles the allocation
-- and initialization of memory for the memory data.
-- Default NoOfBitsPerSubWord is NoOfBitsPerWord.
-- ----------------------------------------------------------------------------
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType IS
VARIABLE MemoryPtr : VitalMemoryDataType;
BEGIN
MemoryPtr := VitalDeclareMemory(
NoOfWords => NoOfWords,
NoOfBitsPerWord => NoOfBitsPerWord,
NoOfBitsPerSubWord => NoOfBitsPerWord,
MemoryLoadFile => MemoryLoadFile,
BinaryLoadFile => BinaryLoadFile
);
RETURN MemoryPtr;
END;
-- ----------------------------------------------------------------------------
IMPURE FUNCTION VitalDeclareMemory (
CONSTANT NoOfWords : IN POSITIVE;
CONSTANT NoOfBitsPerWord : IN POSITIVE;
CONSTANT NoOfBitsPerSubWord : IN POSITIVE;
CONSTANT MemoryLoadFile : IN string := "";
CONSTANT BinaryLoadFile : IN BOOLEAN := FALSE
) RETURN VitalMemoryDataType IS
VARIABLE MemoryPtr : VitalMemoryDataType;
VARIABLE BitsPerEnable : NATURAL
:= ((NoOfBitsPerWord-1)
/NoOfBitsPerSubWord)+1;
BEGIN
PrintMemoryMessage(MsgVDM,ErrInitMem);
MemoryPtr := new VitalMemoryArrayRecType '(
NoOfWords => NoOfWords,
NoOfBitsPerWord => NoOfBitsPerWord,
NoOfBitsPerSubWord => NoOfBitsPerSubWord,
NoOfBitsPerEnable => BitsPerEnable,
MemoryArrayPtr => NULL
);
MemoryPtr.MemoryArrayPtr
:= new MemoryArrayType (0 to MemoryPtr.NoOfWords - 1);
FOR i IN 0 TO MemoryPtr.NoOfWords - 1 LOOP
MemoryPtr.MemoryArrayPtr(i)
:= new MemoryWordType (MemoryPtr.NoOfBitsPerWord - 1 DOWNTO 0);
END LOOP;
IF (MemoryLoadFile /= "") THEN
LoadMemory (MemoryPtr, MemoryLoadFile, BinaryLoadFile);
END IF;
RETURN MemoryPtr;
END;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryTable
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PrevControls - Previous data in for edge detection
-- PrevEnableBus - Previous enables for edge detection
-- PrevDataInBus - Previous data bus for edge detection
-- PrevAddressBus - Previous address bus for edge detection
-- PortFlag - Indicates port operating mode
-- PortFlagArray - Vector form of PortFlag for sub-word
-- Controls - Agregate of scalar control lines
-- EnableBus - Concatenation of vector control lines
-- DataInBus - Input value of data bus in
-- AddressBus - Input value of address bus in
-- AddressValue - Decoded value of the AddressBus
-- MemoryTable - Input memory action table
-- PortType - The type of port (currently not used)
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure implements the majority of the memory
-- modeling functionality via lookup of the memory action
-- tables and performing the specified actions if matches
-- are found, or the default actions otherwise. The
-- overloadings are provided for the word and sub-word
-- (using the EnableBus and PortFlagArray arguments) addressing
-- cases.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
VARIABLE MemoryAction : VitalMemorySymbolType;
VARIABLE DataAction : VitalMemorySymbolType;
VARIABLE HighBit : NATURAL := MemoryData.NoOfBitsPerWord-1;
VARIABLE LowBit : NATURAL := 0;
VARIABLE Address : INTEGER := 0;
VARIABLE PortFlagTmp : VitalPortFlagType;
VARIABLE AddrFlag : VitalMemorySymbolType := 'g'; -- good addr
VARIABLE DataFlag : VitalMemorySymbolType := 'g'; -- good data
VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE);
VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE);
BEGIN
-- Optimize for case when all current inputs are same as previous
IF (PrevDataInBus = DataInBus
AND PrevAddressBus = AddressBus
AND PrevControls = Controls
AND PortFlag(0).MemoryCurrent = PortFlag(0).MemoryPrevious
AND PortFlag(0).DataCurrent = PortFlag(0).DataPrevious) THEN
PortFlag(0).OutputDisable := TRUE;
RETURN;
END IF;
PortFlag(0).DataPrevious := PortFlag(0).DataCurrent;
PortFlag(0).MemoryPrevious := PortFlag(0).MemoryCurrent;
PortFlag(0).OutputDisable := FALSE;
PortFlagTmp := PortFlag(0);
-- Convert address bus to integer value and table lookup flag
DecodeAddress(
Address => Address ,
AddrFlag => AddrFlag ,
MemoryData => MemoryData ,
PrevAddressBus => PrevAddressBus ,
AddressBus => AddressBus
);
-- Interpret data bus as a table lookup flag
DecodeData (
DataFlag => DataFlag ,
PrevDataInBus => PrevDataInBus ,
DataInBus => DataInBus ,
HighBit => HighBit ,
LowBit => LowBit
);
-- Lookup memory and data actions
MemoryTableLookUp(
MemoryAction => MemoryAction ,
DataAction => DataAction ,
MemoryCorruptMask => MemCorruptMask ,
DataCorruptMask => DatCorruptMask ,
PrevControls => PrevControls ,
Controls => Controls ,
AddrFlag => AddrFlag ,
DataFlag => DataFlag ,
MemoryTable => MemoryTable ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Handle data action before memory action
-- This allows reading previous memory contents
HandleDataAction(
DataOutBus => DataOutTmp ,
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => DatCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
DataAction => DataAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
HandleMemoryAction(
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => MemCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
MemoryAction => MemoryAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Set the output PortFlag(0) value
IF (DataAction = 'S') THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
IF (PortFlagTmp.DataCurrent = PortFlagTmp.DataPrevious
AND PortFlagTmp.DataCurrent = HIGHZ) THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
PortFlag(0) := PortFlagTmp;
-- Set previous values for subsequent edge detection
PrevControls := Controls;
PrevDataInBus := DataInBus;
PrevAddressBus := AddressBus;
-- Set the candidate zero delay return value
DataOutBus := DataOutTmp;
-- Set the output AddressValue for VitalMemoryCrossPorts
AddressValue := Address;
END VitalMemoryTable;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryTable (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PrevControls : INOUT std_logic_vector;
VARIABLE PrevEnableBus : INOUT std_logic_vector;
VARIABLE PrevDataInBus : INOUT std_logic_vector;
VARIABLE PrevAddressBus : INOUT std_logic_vector;
VARIABLE PortFlagArray : INOUT VitalPortFlagVectorType;
CONSTANT Controls : IN std_logic_vector;
CONSTANT EnableBus : IN std_logic_vector;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressBus : IN std_logic_vector;
VARIABLE AddressValue : INOUT VitalAddressValueType;
CONSTANT MemoryTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType := UNDEF;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
VARIABLE MemoryAction : VitalMemorySymbolType;
VARIABLE DataAction : VitalMemorySymbolType;
VARIABLE HighBit : NATURAL := BitsPerSubWord-1;
VARIABLE LowBit : NATURAL := 0;
VARIABLE Address : INTEGER := 0;
VARIABLE PortFlagTmp : VitalPortFlagType;
VARIABLE AddrFlag : VitalMemorySymbolType := 'g'; -- good addr
VARIABLE DataFlag : VitalMemorySymbolType := 'g'; -- good data
VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE);
VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE);
BEGIN
-- Optimize for case when all current inputs are same as previous
IF (PrevDataInBus = DataInBus
AND PrevAddressBus = AddressBus
AND PrevControls = Controls) THEN
CheckFlags:
FOR i IN 0 TO BitsPerEnable-1 LOOP
IF (PortFlagArray(i).MemoryCurrent /= PortFlagArray(i).MemoryPrevious
OR PortFlagArray(i).DataCurrent /= PortFlagArray(i).DataPrevious) THEN
EXIT CheckFlags;
END IF;
IF (i = BitsPerEnable-1) THEN
FOR j IN 0 TO BitsPerEnable-1 LOOP
PortFlagArray(j).OutputDisable := TRUE;
END LOOP;
RETURN;
END IF;
END LOOP;
END IF;
-- Convert address bus to integer value and table lookup flag
DecodeAddress(
Address => Address,
AddrFlag => AddrFlag,
MemoryData => MemoryData,
PrevAddressBus => PrevAddressBus,
AddressBus => AddressBus
);
-- Perform independent operations for each sub-word
FOR i IN 0 TO BitsPerEnable-1 LOOP
-- Set the output PortFlag(i) value
PortFlagArray(i).DataPrevious := PortFlagArray(i).DataCurrent;
PortFlagArray(i).MemoryPrevious := PortFlagArray(i).MemoryCurrent;
PortFlagArray(i).OutputDisable := FALSE;
PortFlagTmp := PortFlagArray(i);
-- Interpret data bus as a table lookup flag
DecodeData (
DataFlag => DataFlag ,
PrevDataInBus => PrevDataInBus ,
DataInBus => DataInBus ,
HighBit => HighBit ,
LowBit => LowBit
);
-- Lookup memory and data actions
MemoryTableLookUp(
MemoryAction => MemoryAction ,
DataAction => DataAction ,
MemoryCorruptMask => MemCorruptMask ,
DataCorruptMask => DatCorruptMask ,
PrevControls => PrevControls ,
PrevEnableBus => PrevEnableBus ,
Controls => Controls ,
EnableBus => EnableBus ,
EnableIndex => i ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable ,
AddrFlag => AddrFlag ,
DataFlag => DataFlag ,
MemoryTable => MemoryTable ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Handle data action before memory action
-- This allows reading previous memory contents
HandleDataAction(
DataOutBus => DataOutTmp ,
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => DatCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
DataAction => DataAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
HandleMemoryAction(
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => MemCorruptMask ,
DataInBus => DataInBus ,
Address => Address ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => MemoryTable ,
MemoryAction => MemoryAction ,
CallerName => MsgVMT ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Set the output PortFlag(i) value
IF (DataAction = 'S') THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
IF (PortFlagTmp.DataCurrent = PortFlagTmp.DataPrevious
AND PortFlagTmp.DataCurrent = HIGHZ) THEN
PortFlagTmp.OutputDisable := TRUE;
END IF;
PortFlagArray(i) := PortFlagTmp;
IF (i < BitsPerEnable-1) THEN
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END IF;
END LOOP;
-- Set previous values for subsequent edge detection
PrevControls := Controls;
PrevEnableBus := EnableBus;
PrevDataInBus := DataInBus;
PrevAddressBus := AddressBus;
-- Set the candidate zero delay return value
DataOutBus := DataOutTmp;
-- Set the output AddressValue for VitalMemoryCrossPorts
AddressValue := Address;
END VitalMemoryTable;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryCrossPorts
-- Parameters: DataOutBus - Output candidate zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- SamePortFlag - Operating mode for same port
-- SamePortAddressValue - Operating modes for cross ports
-- CrossPortAddressArray - Decoded AddressBus for cross ports
-- CrossPortMode - Write contention and crossport read control
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- Description: These procedures control the effect of memory operations
-- on a given port due to operations on other ports in a
-- multi-port memory.
-- This includes data write through when reading and writing
-- to the same address, as well as write contention when
-- there are multiple write to the same address.
-- If addresses do not match then data bus is unchanged.
-- The DataOutBus can be diabled with 'Z' value.
-- If the WritePortFlag is 'CORRUPT', that would mean
-- that the whole memory is corrupted. So, for corrupting
-- the Read port, the Addresses need not be compared.
--
-- CrossPortMode Enum Description
-- 1. CpRead Allows Cross Port Read Only
-- No contention checking.
-- 2. WriteContention Allows for write contention checks
-- only between multiple write ports
-- 3. ReadWriteContention Allows contention between read and
-- write ports. The action is to corrupt
-- the memory and the output bus.
-- 4. CpReadAndWriteContention Is a combination of 1 & 2
-- 5. CpReadAndReadContention Allows contention between read and
-- write ports. The action is to corrupt
-- the dataout bus only. The cp read is
-- performed if not contending.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryCrossPorts (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE SamePortFlag : INOUT VitalPortFlagVectorType;
CONSTANT SamePortAddressValue : IN VitalAddressValueType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT CrossPortMode : IN VitalCrossPortModeType
:= CpReadAndWriteContention;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE) := (OTHERS => 'Z');
VARIABLE MemoryTmp : std_logic_vector(DataOutBus'RANGE);
VARIABLE CrossPorts : NATURAL := CrossPortAddressArray'LENGTH;
VARIABLE LowBit : NATURAL := 0;
VARIABLE HighBit : NATURAL := BitsPerSubWord-1;
VARIABLE Address : VitalAddressValueType := SamePortAddressValue;
VARIABLE AddressJ : VitalAddressValueType;
VARIABLE AddressK : VitalAddressValueType;
VARIABLE PortFlagI : VitalPortFlagType;
VARIABLE PortFlagIJ : VitalPortFlagType;
VARIABLE PortFlagIK : VitalPortFlagType;
VARIABLE DoCpRead : BOOLEAN := FALSE;
VARIABLE DoWrCont : BOOLEAN := FALSE;
VARIABLE DoCpCont : BOOLEAN := FALSE;
VARIABLE DoRdWrCont : BOOLEAN := FALSE;
VARIABLE CpWrCont : BOOLEAN := FALSE;
VARIABLE ModeWrCont : BOOLEAN :=
(CrossPortMode=WriteContention) OR
(CrossPortMode=CpReadAndWriteContention);
VARIABLE ModeCpRead : BOOLEAN :=
(CrossPortMode=CpRead) OR
(CrossPortMode=CpReadAndWriteContention);
VARIABLE ModeCpCont : BOOLEAN := (CrossPortMode=ReadWriteContention);
VARIABLE ModeRdWrCont : BOOLEAN := (CrossPortMode=CpReadAndReadContention);
BEGIN
-- Check for disabled port (i.e. OTHERS => 'Z')
IF (DataOutBus = DataOutTmp) THEN
RETURN;
ELSE
DataOutTmp := DataOutBus;
END IF;
-- Check for error in address
IF (Address < 0) THEN
RETURN;
END IF;
ReadMemory(MemoryData,MemoryTmp,Address);
SubWordLoop: -- For each slice of the sub-word I
FOR i IN 0 TO BitsPerEnable-1 LOOP
PortFlagI := SamePortFlag(i);
-- For each cross port J: check with same port address
FOR j IN 0 TO CrossPorts-1 LOOP
PortFlagIJ := CrossPortFlagArray(i+j*BitsPerEnable);
AddressJ := CrossPortAddressArray(j);
IF (AddressJ < 0) THEN
NEXT;
END IF;
DoWrCont := (Address = AddressJ) AND
(ModeWrCont = TRUE) AND
((PortFlagI.MemoryCurrent = WRITE) OR
(PortFlagI.MemoryCurrent = CORRUPT)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
DoCpRead := (Address = AddressJ) AND
(ModeCpRead = TRUE) AND
((PortFlagI.MemoryCurrent = READ) OR
(PortFlagI.OutputDisable = TRUE)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
DoCpCont := (Address = AddressJ) AND
(ModeCpCont = TRUE) AND
((PortFlagI.MemoryCurrent = READ) OR
(PortFlagI.OutputDisable = TRUE)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
DoRdWrCont:= (Address = AddressJ) AND
(ModeRdWrCont = TRUE) AND
((PortFlagI.MemoryCurrent = READ) OR
(PortFlagI.OutputDisable = TRUE)) AND
((PortFlagIJ.MemoryCurrent = WRITE) OR
(PortFlagIJ.MemoryCurrent = CORRUPT)) ;
IF (DoWrCont OR DoCpCont) THEN
-- Corrupt dataout and memory
MemoryTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
SamePortFlag(i).MemoryCurrent := CORRUPT;
SamePortFlag(i).DataCurrent := CORRUPT;
SamePortFlag(i).OutputDisable := FALSE;
EXIT;
END IF;
IF (DoCpRead) THEN
-- Update dataout with memory
DataOutTmp(HighBit DOWNTO LowBit) :=
MemoryTmp(HighBit DOWNTO LowBit);
SamePortFlag(i).MemoryCurrent := READ;
SamePortFlag(i).DataCurrent := READ;
SamePortFlag(i).OutputDisable := FALSE;
EXIT;
END IF;
IF (DoRdWrCont) THEN
-- Corrupt dataout only
DataOutTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
SamePortFlag(i).DataCurrent := CORRUPT;
SamePortFlag(i).OutputDisable := FALSE;
EXIT;
END IF;
END LOOP;
IF (i < BitsPerEnable-1) THEN
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END IF;
END LOOP; -- SubWordLoop
DataOutBus := DataOutTmp;
IF (DoWrCont) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpWrCont,HeaderMsg,PortName);
END IF;
WriteMemory(MemoryData,MemoryTmp,Address);
END IF;
IF (DoCpCont) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpCpCont,HeaderMsg,PortName);
END IF;
WriteMemory(MemoryData,MemoryTmp,Address);
END IF;
IF (DoCpRead) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpCpRead,HeaderMsg,PortName);
END IF;
END IF;
IF (DoRdWrCont) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpRdWrCo,HeaderMsg,PortName);
END IF;
END IF;
END VitalMemoryCrossPorts;
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryCrossPorts (
VARIABLE MemoryData : INOUT VitalMemoryDataType;
CONSTANT CrossPortFlagArray : IN VitalPortFlagVectorType;
CONSTANT CrossPortAddressArray : IN VitalAddressValueVectorType;
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE MemoryTmp : std_logic_vector(BitsPerWord-1 DOWNTO 0);
VARIABLE CrossPorts : NATURAL := CrossPortAddressArray'LENGTH;
VARIABLE LowBit : NATURAL := 0;
VARIABLE HighBit : NATURAL := BitsPerSubWord-1;
VARIABLE AddressJ : VitalAddressValueType;
VARIABLE AddressK : VitalAddressValueType;
VARIABLE PortFlagIJ : VitalPortFlagType;
VARIABLE PortFlagIK : VitalPortFlagType;
VARIABLE CpWrCont : BOOLEAN := FALSE;
BEGIN
SubWordLoop: -- For each slice of the sub-word I
FOR i IN 0 TO BitsPerEnable-1 LOOP
-- For each cross port J: check with each cross port K
FOR j IN 0 TO CrossPorts-1 LOOP
PortFlagIJ := CrossPortFlagArray(i+j*BitsPerEnable);
AddressJ := CrossPortAddressArray(j);
-- Check for error in address
IF (AddressJ < 0) THEN
NEXT;
END IF;
ReadMemory(MemoryData,MemoryTmp,AddressJ);
-- For each cross port K
FOR k IN 0 TO CrossPorts-1 LOOP
IF (k <= j) THEN
NEXT;
END IF;
PortFlagIK := CrossPortFlagArray(i+k*BitsPerEnable);
AddressK := CrossPortAddressArray(k);
-- Check for error in address
IF (AddressK < 0) THEN
NEXT;
END IF;
CpWrCont := ( (AddressJ = AddressK) AND
(PortFlagIJ.MemoryCurrent = WRITE) AND
(PortFlagIK.MemoryCurrent = WRITE) ) OR
( (PortFlagIJ.MemoryCurrent = WRITE) AND
(PortFlagIK.MemoryCurrent = CORRUPT) ) OR
( (PortFlagIJ.MemoryCurrent = CORRUPT) AND
(PortFlagIK.MemoryCurrent = WRITE) ) OR
( (PortFlagIJ.MemoryCurrent = CORRUPT) AND
(PortFlagIK.MemoryCurrent = CORRUPT) ) ;
IF (CpWrCont) THEN
-- Corrupt memory only
MemoryTmp(HighBit DOWNTO LowBit) := (OTHERS => 'X');
EXIT;
END IF;
END LOOP; -- FOR k IN 0 TO CrossPorts-1 LOOP
IF (CpWrCont = TRUE) THEN
IF (MsgOn) THEN
PrintMemoryMessage(MsgVMCP,ErrMcpCpWrCont,HeaderMsg);
END IF;
WriteMemory(MemoryData,MemoryTmp,AddressJ);
END IF;
END LOOP; -- FOR j IN 0 TO CrossPorts-1 LOOP
IF (i < BitsPerEnable-1) THEN
-- Calculate HighBit and LowBit
LowBit := LowBit + BitsPerSubWord;
IF (LowBit > BitsPerWord) THEN
LowBit := BitsPerWord;
END IF;
HighBit := LowBit + BitsPerSubWord;
IF (HighBit > BitsPerWord) THEN
HighBit := BitsPerWord;
ELSE
HighBit := HighBit - 1;
END IF;
END IF;
END LOOP; -- SubWordLoop
END VitalMemoryCrossPorts;
-- ----------------------------------------------------------------------------
-- Procedure: VitalMemoryViolation
-- Parameters: DataOutBus - Output zero delay data bus out
-- MemoryData - Pointer to memory data structure
-- PortFlag - Indicates port operating mode
-- TimingDataArray - This is currently not used (comment out)
-- ViolationArray - Aggregation of violation variables
-- DataInBus - Input value of data bus in
-- AddressBus - Input value of address bus in
-- AddressValue - Decoded value of the AddressBus
-- ViolationTable - Input memory violation table
-- PortName - Port name string for messages
-- HeaderMsg - Header string for messages
-- MsgOn - Control the generation of messages
-- MsgSeverity - Control level of message generation
-- Description: This procedure is intended to implement all actions on the
-- memory contents and data out bus as a result of timing viols.
-- It uses the memory action table to perform various corruption
-- policies specified by the user.
-- ----------------------------------------------------------------------------
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationFlagsArray : IN X01ArrayT;
CONSTANT ViolationSizesArray : IN VitalMemoryViolFlagSizeType;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE BitsPerWord : NATURAL := MemoryData.NoOfBitsPerWord;
VARIABLE BitsPerSubWord : NATURAL := MemoryData.NoOfBitsPerSubWord;
VARIABLE BitsPerEnable : NATURAL := MemoryData.NoOfBitsPerEnable;
VARIABLE DataOutTmp : std_logic_vector(DataOutBus'RANGE)
:= DataOutBus;
VARIABLE MemoryAction : VitalMemorySymbolType;
VARIABLE DataAction : VitalMemorySymbolType;
-- VMT relies on the corrupt masks so HighBit/LowBit are full word
VARIABLE HighBit : NATURAL := BitsPerWord-1;
VARIABLE LowBit : NATURAL := 0;
VARIABLE PortFlagTmp : VitalPortFlagType;
VARIABLE VFlagArrayTmp : std_logic_vector
(0 TO ViolationFlagsArray'LENGTH-1);
VARIABLE MemCorruptMask : std_logic_vector (DataOutBus'RANGE);
VARIABLE DatCorruptMask : std_logic_vector (DataOutBus'RANGE);
BEGIN
-- Don't do anything if given an error address
IF (AddressValue < 0) THEN
RETURN;
END IF;
FOR i IN ViolationFlagsArray'RANGE LOOP
VFlagArrayTmp(i) := ViolationFlagsArray(i);
END LOOP;
-- Lookup memory and data actions
ViolationTableLookUp(
MemoryAction => MemoryAction ,
DataAction => DataAction ,
MemoryCorruptMask => MemCorruptMask ,
DataCorruptMask => DatCorruptMask ,
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => VFlagArrayTmp ,
ViolationSizesArray => ViolationSizesArray ,
ViolationTable => ViolationTable ,
BitsPerWord => BitsPerWord ,
BitsPerSubWord => BitsPerSubWord ,
BitsPerEnable => BitsPerEnable ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
-- Need to read incoming PF value (was not before)
PortFlagTmp := PortFlag(0);
IF (PortType = READ OR PortType = RDNWR) THEN
-- Handle data action before memory action
-- This allows reading previous memory contents
HandleDataAction(
DataOutBus => DataOutTmp ,
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => DatCorruptMask ,
DataInBus => DataInBus ,
Address => AddressValue ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => ViolationTable ,
DataAction => DataAction ,
CallerName => MsgVMV ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
END IF;
IF (PortType = WRITE OR PortType = RDNWR) THEN
HandleMemoryAction(
MemoryData => MemoryData ,
PortFlag => PortFlagTmp ,
CorruptMask => MemCorruptMask ,
DataInBus => DataInBus ,
Address => AddressValue ,
HighBit => HighBit ,
LowBit => LowBit ,
MemoryTable => ViolationTable ,
MemoryAction => MemoryAction ,
CallerName => MsgVMV ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn
);
END IF;
-- Check if we need to turn off PF.OutputDisable
IF (DataAction /= 'S') THEN
PortFlagTmp.OutputDisable := FALSE;
-- Set the output PortFlag(0) value
-- Note that all bits of PortFlag get PortFlagTmp
FOR i IN PortFlag'RANGE LOOP
PortFlag(i) := PortFlagTmp;
END LOOP;
END IF;
-- Set the candidate zero delay return value
DataOutBus := DataOutTmp;
END;
PROCEDURE VitalMemoryViolation (
VARIABLE DataOutBus : INOUT std_logic_vector;
VARIABLE MemoryData : INOUT VitalMemoryDataType;
VARIABLE PortFlag : INOUT VitalPortFlagVectorType;
CONSTANT DataInBus : IN std_logic_vector;
CONSTANT AddressValue : IN VitalAddressValueType;
CONSTANT ViolationFlags : IN std_logic_vector;
CONSTANT ViolationTable : IN VitalMemoryTableType;
CONSTANT PortType : IN VitalPortType;
CONSTANT PortName : IN STRING := "";
CONSTANT HeaderMsg : IN STRING := "";
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE VFlagArrayTmp : X01ArrayT (0 TO 0);
BEGIN
VitalMemoryViolation (
DataOutBus => DataOutBus ,
MemoryData => MemoryData ,
PortFlag => PortFlag ,
DataInBus => DataInBus ,
AddressValue => AddressValue ,
ViolationFlags => ViolationFlags ,
ViolationFlagsArray => VFlagArrayTmp ,
ViolationSizesArray => ( 0 => 0 ) ,
ViolationTable => ViolationTable ,
PortType => PortType ,
PortName => PortName ,
HeaderMsg => HeaderMsg ,
MsgOn => MsgOn ,
MsgSeverity => MsgSeverity
);
END;
END Vital_Memory ;
| gpl-2.0 | b47929b4e8c979905af77700197b17d0 | 0.60382 | 5.059877 | false | true | false | false |
tgingold/ghdl | testsuite/synth/oper01/cmp01.vhdl | 1 | 721 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cmp01 is
port (l : std_logic_vector(3 downto 0);
r : std_logic_vector(3 downto 0);
eq : out std_logic;
ne : out std_logic;
lt : out std_logic;
le : out std_logic;
ge : out std_logic;
gt : out std_logic);
end cmp01;
architecture behav of cmp01 is
begin
eq <= '1' when unsigned(l) = unsigned(r) else '0';
ne <= '1' when unsigned(l) /= unsigned(r) else '0';
lt <= '1' when unsigned(l) < unsigned(r) else '0';
le <= '1' when unsigned(l) <= unsigned(r) else '0';
gt <= '1' when unsigned(l) > unsigned(r) else '0';
ge <= '1' when unsigned(l) >= unsigned(r) else '0';
end behav;
| gpl-2.0 | 16685aec29dbddfb20e520e742274a0a | 0.583911 | 2.907258 | false | false | false | false |
tgingold/ghdl | testsuite/synth/iassoc01/tb_iassoc01.vhdl | 1 | 472 | entity tb_iassoc01 is
end tb_iassoc01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc01 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc01
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
assert res = 6 severity failure;
a <= 197;
b <= 203;
wait for 1 ns;
assert res = 400 severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 90806ad277edb8f0e6b3af3f6d4410d6 | 0.625 | 3.323944 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1298/generics.vhdl | 1 | 1,247 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Params is
generic (
BOO : boolean:=FALSE;
INT : integer:=0;
LOG : std_logic:='0';
VEC : std_logic_vector(7 downto 0):="00000000";
STR : string:="ABCD";
REA : real:=0.0
);
port (
boo_o : out std_logic;
int_o : out std_logic_vector(7 downto 0);
log_o : out std_logic;
vec_o : out std_logic_vector(7 downto 0);
str_o : out std_logic;
rea_o : out std_logic
);
end entity Params;
architecture RTL of Params is
begin
assert BOO=True report "The boolean is not True" severity note;
assert INT=255 report "The integer is not 255" severity note;
assert LOG='1' report "The std_logic is not '1'" severity note;
assert VEC="11111111" report "The std_logic_vector is not 11111111" severity note;
assert STR="WXYZ" report "The string is not WXYZ" severity note;
-- assert REA=1.1 report "The real is not 1.1" severity note;
boo_o <= '1' when BOO else '0';
int_o <= std_logic_vector(to_unsigned(INT, 8));
log_o <= LOG;
vec_o <= VEC;
str_o <= '1' when STR="WXYZ" else '0';
rea_o <= '1' when REA=1.1 else '0';
end architecture RTL;
| gpl-2.0 | 6d47b69945298d86cbd450c04a8d36d7 | 0.605453 | 3.222222 | false | false | false | false |
tgingold/ghdl | testsuite/synth/synth34/tb_repro_uns.vhdl | 1 | 645 | entity tb_repro_uns is
end tb_repro_uns;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_repro_uns is
signal clk : std_logic;
signal a : unsigned(7 downto 0);
signal b : unsigned(7 downto 0);
begin
dut: entity work.repro_uns
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"ab";
pulse;
assert b = x"ab" severity failure;
a <= x"12";
pulse;
assert b = x"12" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 67928fb5c4d83c45309960bf2483e603 | 0.589147 | 3.208955 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd | 4 | 2,084 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07 is
end entity inline_07;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_07 is
begin
process_5_a : process is
-- code from book:
procedure increment ( a : inout integer; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := a + n;
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in bit_vector := B"1" ) is -- . . .
-- not in book
begin
a := bit_vector(signed(a) + signed(n));
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := bit_vector(signed(a) + to_signed(n, a'length));
end procedure increment;
-- end not in book;
variable count_int : integer := 2;
variable count_bv : bit_vector (15 downto 0) := X"0002";
-- end of code from book
begin
-- code from book:
increment ( count_int, 2 );
increment ( count_int );
increment ( count_bv, X"0002");
increment ( count_bv, 1 );
-- increment ( count_bv );
-- end of code from book
wait;
end process process_5_a;
end architecture test;
| gpl-2.0 | b7a510690226f72b808cddf376349d88 | 0.62476 | 3.902622 | false | false | false | false |
nickg/nvc | test/regress/wave3.vhd | 1 | 2,101 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sub is
port (
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0) );
end entity;
architecture test of sub is
signal ctr : unsigned(3 to 18) := (others => '0');
signal ctr2 : unsigned(15 downto 0) := (others => '0');
begin
y <= x after 5 ns;
ctr <= ctr + 1 after 20 ns;
ctr2 <= ctr2 + 1 after 20 ns;
end architecture;
-------------------------------------------------------------------------------
package p is
signal s : bit;
end package;
-------------------------------------------------------------------------------
entity wave3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use work.p.all;
architecture test of wave3 is
signal x : std_logic_vector(7 downto 0) := X"AA";
signal y : std_logic_vector(7 downto 0);
signal z : std_logic := 'U';
signal o : std_logic := '0';
signal b : boolean;
signal m : string(1 to 3);
signal p : bit_vector(1 to 3);
signal q : bit_vector(3 downto 1);
signal t : delay_length;
type state is (INIT, ONE, TWO);
signal s : state;
subtype state_sub is state range ONE to TWO;
signal s2 : state_sub;
begin
x <= not x after 50 ns;
z <= 'X' after 100 ns, -- Appears same as 'U'
'H' after 200 ns,
'Z' after 300 ns,
'L' after 400 ns,
'-' after 500 ns,
'1' after 600 ns;
a_block: block is
signal i : natural; -- No integer type in FST?
signal c : character;
begin
i <= i + 1 after 20 ns;
c <= m((i rem 3) + 1);
end block;
m <= "abc";
work.p.s <= '1';
b <= true;
s <= ONE after 60 ns, TWO after 150 ns;
sub_i: entity work.sub
port map ( x, y );
gen: for i in 1 to 3 generate
signal g : integer;
begin
end generate;
p(1) <= '1';
p(2) <= '1';
p(3) <= '0';
q(1) <= '1';
q(2) <= '1';
q(3) <= '0';
t <= 20 us after 1 ps;
s2 <= TWO after 4 ns;
end architecture;
| gpl-3.0 | 2d1e732d185a621e14f874a0e533cdc2 | 0.495002 | 3.345541 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xil_defaultlib/doHistStretch_ap_fdiv_14_no_dsp_32.vhd | 2 | 10,801 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fdiv_14_no_dsp_32;
ARCHITECTURE doHistStretch_ap_fdiv_14_no_dsp_32_arch OF doHistStretch_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fdiv_14_no_dsp_32_arch;
| gpl-3.0 | 7ab5741c981c5e465e32485c9ac2c390 | 0.632719 | 3.219374 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_spi/tb_spi.vhd | 1 | 10,904 | -------------------------------------------------------------------------------------
-- FILE NAME : tb_spi.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : May 21, 2010
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity tb_spi is
end tb_spi;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of tb_spi is
-------------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------------
component generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end component generic_host_emu;
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant CLK_200_MHZ : time := 5 ns;
constant CLK_125_MHZ : time := 8 ns;
constant CLK_100_MHZ : time := 10 ns;
constant CLK_300_MHZ : time := 3.3333 ns;
constant CLK_25_MHZ : time := 40 ns;
constant CLK_167_MHZ : time := 6 ns;
constant DATA_WIDTH : natural := 8;
constant ADDR_WIDTH : natural := 8;
constant WR_BIT : std_logic := '0'; -- 0 means write
constant RD_BIT : std_logic := '1'; -- 1 means read
constant START_ADDR_AMC7823_CTRL0 : std_logic_vector(27 downto 0) := x"0000100";
constant STOP_ADDR_AMC7823_CTRL0 : std_logic_vector(27 downto 0) := x"00001FF";
-----------------------------------------------------------------------------------
-- SIGNALS
-----------------------------------------------------------------------------------
signal sysclk_p : std_logic := '1';
signal sysclk_n : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal rstn : std_logic := '0';
signal clk_cmd : std_logic;
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val : std_logic;
signal out_cmd : std_logic_vector(63 downto 0);
signal out_cmd_val4 : std_logic;
signal out_cmd4 : std_logic_vector(63 downto 0);
signal sclk_prebuf : std_logic;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal spi_sclk_phy : std_logic;
signal spi_sdo_phy : std_logic;
signal spi_sdi_phy : std_logic;
signal spi_csn_phy : std_logic;
signal spi_reset_phy : std_logic;
signal spi_sclk : std_logic;
signal spi_counter : std_logic_vector(7 downto 0);
signal spi0_capure : std_logic_vector(31 downto 0) := (others=>'0');
--***********************************************************************************
begin
--***********************************************************************************
-- Clock & reset generation
sysclk_p <= not sysclk_p after CLK_100_MHZ/2;
sysclk_n <= not sysclk_p;
clk <= not clk after CLK_125_MHZ / 2;
rst <= '0' after CLK_125_MHZ * 10;
rstn <= '1' after CLK_125_MHZ * 10;
----------------------------------------------------------------------------------------------------
-- Generic host interface
----------------------------------------------------------------------------------------------------
inst0_generic_host: generic_host_emu
generic map (
global_start_addr_gen => x"0000000",
global_stop_addr_gen => x"00000FF",
private_start_addr_gen => x"0000000",
private_stop_addr_gen => x"00000FF"
)
port map (
cmdclk_out_cmdclk => clk_cmd, -- out std_logic;
cmd_in_cmdin => out_cmd , -- in std_logic_vector(63 downto 0);
cmd_in_cmdin_val => out_cmd_val, -- in std_logic;
cmd_out_cmdout => in_cmd, -- out std_logic_vector(63 downto 0);
cmd_out_cmdout_val => in_cmd_val, -- out std_logic;
ifpga_rst_out_ifpga_rst => open, -- out std_logic;
clk_clkin => (others=>'0'), -- in std_logic_vector(31 downto 0);
rst_rstin => (others=>'0'), -- in std_logic_vector(31 downto 0);
sys_clk => clk, -- in std_logic;
sys_reset_n => rstn, -- in std_logic;
in_data_in_stop => open, -- out std_logic;
in_data_in_dval => '0', -- in std_logic;
in_data_in_data => (others=>'0'), -- in std_logic_vector(63 downto 0);
out_data_out_stop => '0', -- in std_logic;
out_data_out_dval => open, -- out std_logic;
out_data_out_data => open -- out std_logic_vector(63 downto 0)
);
----------------------------------------------------------------------------------------------------
-- Generate serial clocks for SPI (max 6.66MHz, due to ...)
----------------------------------------------------------------------------------------------------
process (clk_cmd)
-- Divide by 2^5 = 32, CLKmax = 32 x 6.66MHz
variable clk_div : std_logic_vector(4 downto 0) := (others => '0');
begin
if (rising_edge(clk_cmd)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
sclk_prebuf <= sclk_ext;
end if;
end process;
bufg_sclk : bufg
port map (
i => sclk_prebuf,
o => serial_clk
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling the FMC144 MONITOR
----------------------------------------------------------------------------------------------------
--spi_mon_ctrl0:
--entity work.amc7823_ctrl
--generic map (
-- START_ADDR => START_ADDR_AMC7823_CTRL0,
-- STOP_ADDR => STOP_ADDR_AMC7823_CTRL0
--)
--port map (
-- rst => rst,
-- clk => serial_clk,
-- -- Command Interface
-- clk_cmd => clk_cmd,
-- in_cmd_val => in_cmd_val,
-- in_cmd => in_cmd,
-- out_cmd_val => out_cmd_val4,
-- out_cmd => out_cmd4,
-- -- Serial Interface
-- trig_n_cs => spi_csn_phy,
-- trig_sclk => spi_sclk_phy,
-- trig_sdo => spi_sdo_phy,
-- trig_clksel0 => spi_sdi_phy
--);
--
spi_sclk <= spi_sclk_phy when spi_csn_phy = '0' else '0';
spi_adc1_ctrl0:
entity work.adc16dx370_ctrl
generic map (
START_ADDR => START_ADDR_AMC7823_CTRL0,
STOP_ADDR => STOP_ADDR_AMC7823_CTRL0
)
port map (
rst => rst,
clk => serial_clk,
-- Command Interface
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val4,
out_cmd => out_cmd4,
-- Serial Interface
trig_n_cs => spi_csn_phy,
trig_sclk => spi_sclk_phy,
trig_sdo => spi_sdo_phy,
trig_clksel0 => spi_sdi_phy
);
----------------------------------------------------------------------------------------------------
-- Command out merge & pipeline
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
out_cmd_val <= '0';
out_cmd <= (others => '0');
elsif (rising_edge(clk_cmd)) then
out_cmd_val <= out_cmd_val4;
out_cmd <= out_cmd4;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- SPI device model
----------------------------------------------------------------------------------------------------
spi_checker_inst:
entity work.spi_checker
port map(
clk => serial_clk,
sclk => serial_clk,
sdo => spi_sdi_phy,
sdi => spi_sdo_phy,
cs_n => spi_csn_phy,
reg0 => spi0_capure
);
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
| mit | 19fa843db91ee2e26862243d63d2c6a7 | 0.404989 | 4.120937 | false | false | false | false |
nickg/nvc | test/parse/vests1.vhd | 1 | 1,521 | entity something is
end entity;
architecture arch of something is
begin
end architecture;
configuration testbench of something is
for arch
end for;
end;
entity c01s03b01x00p12n01i00863ent is
end entity;
architecture c01s03b01x00p12n01i00863arch of c01s03b01x00p12n01i00863ent is
begin
K:block
component test
port(
sigin1 : in boolean := false;
sigout1 : out boolean ;
sigin2 : in bit := '0';
sigout2 : out bit ;
sigin4 : in severity_level := note ;
sigout4 : out severity_level ;
sigin5 : in integer := 0 ;
sigout5 : out integer ;
sigin6 : in real := 0.0;
sigout6 : out real ;
sigin7 : in time := 0 fs;
sigout7 : out time ;
sigin8 : in natural := 0 ;
sigout8 : out natural ;
sigin9 : in positive := 0 ;
sigout9 : out positive
);
end component;
BEGIN
T5: component test;
G: for i in 0 to 3 generate
T1: component test;
end generate;
end block;
end architecture;
configuration c01s03b01x00p12n01i00863cfg of c01s03b01x00p12n01i00863ent is
for c01s03b01x00p12n01i00863arch
for K
for T5:test use configuration work.testbench;
end for;
for G(3)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(0 to 2)
for all:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-3.0 | c9c49ea2bf5150bc0fc41b9811831631 | 0.602235 | 3.44898 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd | 4 | 3,132 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2261.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02261ent IS
END c07s02b06x00p05n01i02261ent;
ARCHITECTURE c07s02b06x00p05n01i02261arch OF c07s02b06x00p05n01i02261ent IS
constant s4p : real := 4.0;
constant s4n : real := (-4.0);
constant s5p : real := 5.0;
constant s5n : real := (-5.0);
BEGIN
TESTING: PROCESS
variable m1 : real := 4.0 * 5.0 ;
variable m2 : real := 4.0 * (-5.0);
variable m3 : real := (-4.0) * 5.0 ;
variable m4 : real := (-4.0) * (-5.0);
variable d1 : real := 4.0 / 5.0 ;
variable d2 : real := 4.0 / (-5.0);
variable d3 : real := (-4.0) / 5.0 ;
variable d4 : real := (-4.0) / (-5.0);
variable Em1 : real := s4p * s5p;
variable Em2 : real := s4p * s5n;
variable Em3 : real := s4n * s5p;
variable Em4 : real := s4n * s5n;
variable Ed1 : real := s4p / s5p;
variable Ed2 : real := s4p / s5n;
variable Ed3 : real := s4n / s5p;
variable Ed4 : real := s4n / s5n;
BEGIN
assert m1 = Em1;
assert m2 = Em2;
assert m3 = Em3;
assert m4 = Em4;
assert d1 = Ed1;
assert d2 = Ed2;
assert d3 = Ed3;
assert d4 = Ed4;
assert NOT((m1 = Em1) and
( m2 = Em2) and
( m3 = Em3) and
( m4 = Em4) and
( d1 = Ed1) and
( d2 = Ed2) and
( d3 = Ed3) and
( d4 = Ed4) )
report "***PASSED TEST: c07s02b06x00p05n01i02261"
severity NOTE;
assert (( m1 = Em1) and
( m2 = Em2) and
( m3 = Em3) and
( m4 = Em4) and
( d1 = Ed1) and
( d2 = Ed2) and
( d3 = Ed3) and
( d4 = Ed4) )
report "***FAILED TEST: c07s02b06x00p05n01i02261 - Constant real type multiplication and division test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02261arch;
| gpl-2.0 | daa2bbee9ea4c93325912da1278fd923 | 0.550128 | 3.11332 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd | 4 | 1,571 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_comparator is
end tb_comparator;
architecture TB_comparator of tb_comparator is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
signal cmp_out : std_logic;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
C1 : entity work.comparator(hysteresis)
port map(
plus_in => in_src,
minus_in => electrical_ref,
output => cmp_out
);
end TB_comparator;
| gpl-2.0 | 368976ac3afe5bafa2479c09c7b3b4ad | 0.671547 | 4.156085 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dff02/tb_dff08b.vhdl | 1 | 1,199 | entity tb_dff08b is
end tb_dff08b;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08b is
signal clk : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff08b
port map (
q => dout,
d => din,
en => en,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wait for 1 ns;
assert dout = x"aa" severity failure;
rst <= '1';
en <= '1';
pulse;
assert dout = x"00" severity failure;
rst <= '0';
din <= x"38";
pulse;
assert dout = x"38" severity failure;
din <= x"af";
pulse;
assert dout = x"af" severity failure;
en <= '0';
din <= x"b3";
pulse;
assert dout = x"af" severity failure;
en <= '0';
rst <= '1';
din <= x"b4";
pulse;
assert dout = x"af" severity failure;
en <= '1';
rst <= '1';
din <= x"b5";
pulse;
assert dout = x"00" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 99c6c12905e55ec3768176224affb1b6 | 0.53628 | 3.223118 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug088/assemble2.vhdl | 1 | 1,898 | library ieee;
use ieee.std_logic_1164.all;
entity assemble is
port (
A: in std_logic_vector(31 downto 0);
B: in std_logic_vector(31 downto 0);
C: in std_logic_vector(31 downto 0);
F: out std_logic_vector(31 downto 0)
);
end entity;
architecture fum of assemble is
type std_logic_2d is array
(integer range <>, integer range <>) of std_logic;
type column is array (31 downto 0) of std_logic;
type row is array (2 downto 0) of std_logic;
signal data: std_logic_2d (column'range, row'range);
function to_std_logic_2d (i0,i1,i2: std_logic_vector (column'range))
return std_logic_2d is
variable retdat: std_logic_2d (column'range, row'range);
begin
for i in column'range loop
retdat(i, 0) := i0(i);
retdat(i, 1) := i1(i);
retdat(i, 2) := i2(i);
end loop;
return retdat;
end function;
begin
data <= to_std_logic_2d(A, B, C);
F <= (others => data (15, 1)); -- B(15)
end architecture;
architecture fie of assemble is
type std_logic_2d is array
(integer range <>, integer range <>) of std_logic;
subtype column is std_logic_vector (31 downto 0);
subtype row is std_logic_vector (2 downto 0);
signal data: std_logic_2d (column'range, row'range);
function to_std_logic_2d (i0,i1,i2: std_logic_vector (column'range))
return std_logic_2d is
variable retdat: std_logic_2d (column'range, row'range);
begin
for i in retdat'range(1) loop
retdat(i, 0) := i0(i);
retdat(i, 1) := i1(i);
retdat(i, 2) := i2(i);
end loop;
return retdat;
end function;
begin
data <= to_std_logic_2d(A, B, C);
F <= (others => data (15, 1)); -- B(15)
end architecture;
| gpl-2.0 | 930449402ec5ca1016236432acfedd78 | 0.56059 | 3.272414 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd | 4 | 2,043 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_10 is
end entity ch_18_10;
----------------------------------------------------------------
architecture test of ch_18_10 is
begin
process is
use std.textio.all;
variable L : line;
-- code from book:
type speed_category is (stopped, slow, fast, maniacal);
variable speed : speed_category;
-- end of code from book
begin
speed := stopped;
-- code from book:
write ( L, speed_category'image(speed) );
-- end of code from book
writeline(output, L);
speed := slow;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := fast;
write ( L, speed_category'image(speed) );
writeline(output, L);
speed := maniacal;
write ( L, speed_category'image(speed) );
writeline(output, L);
-- code from book:
readline( input, L );
speed := speed_category'value(L.all);
-- end of code from book
wait;
end process;
end architecture test;
| gpl-2.0 | fa287293f35ae8b864dd1aae55135188 | 0.583945 | 4.118952 | false | false | false | false |
nickg/nvc | test/sem/ename.vhd | 1 | 995 | package ename_pack is
constant c : integer := << constant .top.foo : integer >>; -- Not supported
end package;
-------------------------------------------------------------------------------
entity ename is
end entity;
architecture test of ename is
alias e1 is <<signal .top.foo.bar : bit>>; -- OK
constant k1 : integer := <<constant foo.bar : integer>>; -- OK
signal s1 : bit_vector(1 to k1); -- OK
signal s2 : bit_vector(1 to <<signal foo.bar : integer>>); -- Error
constant k2 : integer := <<constant foo.baz : bit>>; -- Error
begin
p1: process is
begin
e1 <= '1'; -- OK
e1 := '1'; -- Error
<<variable foo.var : integer>> := 5; -- OK
<<signal ^.x.y : bit>> <= force '1'; -- OK
<<constant .x.y : bit>> <= release; -- Error
assert <<constant foo(<< signal a.b : integer >>).bar : integer>> = 1; -- Error
wait;
end process;
end architecture;
| gpl-3.0 | 20cc05c877690956db0962ceb8299c52 | 0.481407 | 3.856589 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue520/lrm.vhdl | 1 | 1,460 | entity TOP is
end entity TOP;
architecture ARCH of TOP is
signal S1, S2, S3: BIT;
alias DONE_SIG is <<signal .TOP.DUT.DONE: BIT>>; -- Legal
constant DATA_WIDTH: INTEGER:= <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH;
-- Illegal, because .TOP.DUT.DATA has not yet been elaborated
-- when the expression is evaluated
begin
P1: process ( DONE_SIG ) is -- Legal
begin
if DONE_SIG then -- Legal ...;
end if;
end process P1;
MONITOR: entity WORK.MY_MONITOR port map (DONE_SIG);
-- Illegal, because .TOP.DUT.DONE has not yet been elaborated
-- when the association element is elaborated
DUT: entity WORK.MY_DESIGN port map (s1, S2, S3);
MONITOR2: entity WORK.MY_MONITOR port map (DONE_SIG);
-- Legal, because .TOP.DUT.DONE has now been elaborated
B1: block
constant DATA_WIDTH: INTEGER := <<signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH
-- Legal, because .TOP.DUT.DATA has now been elaborated
begin
end block B1;
B2: block
constant C0: INTEGER := 6;
constant C1: INTEGER := <<constant .TOP.B3.C2: INTEGER>>;
-- Illegal, because .TOP.B3.C2 has not yet been elaborated
begin
end block B2;
B3: block
constant C2: INTEGER := <<constant .TOP.B2.C0: INTEGER>>; -- Legal
begin
end block B3;
-- Together, B2 and B3 are illegal, because they cannot be ordered
-- so that the objects are elaborated in the order .TOP.B2.C0,
-- then .TOP.B3.C2, and finally .TOP.B2.C1.
end architecture ARCH;
| gpl-2.0 | 6feedd69e7ee2a49d4d0d9da31c7ada3 | 0.678082 | 3.333333 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffsize.vhd | 2 | 1,519 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_ac_huffsize;
architecture augh of huff_make_dhuff_tb_ac_huffsize is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
| gpl-2.0 | 1cbf9c3ea2301b1b1c2cc68970366abe | 0.676103 | 2.893333 | false | false | false | false |
nickg/nvc | test/simp/genmap.vhd | 1 | 690 | entity sub1 is
generic (
x : integer := 5;
y : bit_vector(1 to 3) );
end entity;
package pack is
type rec is record
x, y : integer;
end record;
end package;
use work.pack.all;
entity sub2 is
generic ( r : rec );
end entity;
entity genmap is
end entity;
use work.pack.all;
architecture test of genmap is
begin
u1: entity work.sub1
generic map ( y => ('1', '1', '0'), x => 2 );
u2: entity work.sub1
generic map ( y => "101" );
u3: entity work.sub1
generic map (
0, y(1) => '1', y(2) => '0', y(3) => '1' );
u4: entity work.sub2
generic map ( r.y => 3, r.x => 2 );
end architecture;
| gpl-3.0 | b69f26028a9e4509dbbd4336998acccc | 0.530435 | 3.0131 | false | false | false | false |
nickg/nvc | test/regress/vests12.vhd | 1 | 57,306 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc754.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00754pkg is
subtype hi_to_low_range is integer range 0 to 7;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(0 to 15);
b:severity_level_vector(0 to 15);
c:integer_vector(0 to 15);
d:real_vector(0 to 15);
e:time_vector(0 to 15);
f:natural_vector(0 to 15);
g:positive_vector(0 to 15);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(0 to 7);
b: array_rec_cons(0 to 7);
c: array_rec_rec(0 to 7);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
constant size :integer := 7;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range 1 to 10;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78 : boolean_vector_range := (others => C1);
constant C79 : severity_level_vector_range := (others => C4) ;
constant C80 : integer_vector_range :=(others => C5) ;
constant C81 : real_vector_range :=(others => C6);
constant C82 : time_vector_range :=(others => C7);
constant C83 : natural_vector_range :=(others => C8);
constant C84 : positive_vector_range :=(others => C9);
constant C85 : array_rec_std(0 to 7) :=(others => C50) ;
constant C86 : array_rec_cons (0 to 7) :=(others => C51);
constant C88 : array_rec_rec(0 to 7) :=(others => C55);
constant C102 : record_of_arr_of_record:= (C85,C86,C88);
end c01s01b01x01p05n02i00754pkg;
use work.c01s01b01x01p05n02i00754pkg.all;
ENTITY vests12 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
port(
S1 : boolean_vector(zero to fifteen);
S2 : severity_level_vector(zero to fifteen);
S3 : integer_vector(zero to fifteen);
S4 : real_vector(zero to fifteen);
S5 : time_vector (zero to fifteen);
S6 : natural_vector(zero to fifteen);
S7 : positive_vector(zero to fifteen);
S8 : boolean_cons_vector;
S9 : severity_level_cons_vector ;
S10 : integer_cons_vector;
S11 : real_cons_vector;
S12 : time_cons_vector ;
S13 : natural_cons_vector ;
S14 : positive_cons_vector ;
S15 : boolean_cons_vectorofvector;
S16 : severity_level_cons_vectorofvector;
S17 : integer_cons_vectorofvector;
S18 : real_cons_vectorofvector;
S19 : time_cons_vectorofvector;
S20 : natural_cons_vectorofvector;
S21 : positive_cons_vectorofvector;
S22 : record_std_package;
S23 : record_cons_array;
S24 : record_cons_arrayofarray ;
S25 : boolean_vector_st;
S26 : severity_level_vector_st;
S27 : integer_vector_st;
S28 : real_vector_st;
S29 : time_vector_st;
S30 : natural_vector_st;
S31 : positive_vector_st;
S32 : record_array_st;
S33 : record_array_st;
S34 : record_array_new;
S35 : record_of_records;
S36 : byte;
S37 : word;
S38 : current_vector(zero to three);
S39 : resistance_vector(zero to three);
S40 : delay;
S41 : boolean_vector_range;
S42 : severity_level_vector_range ;
S43 : integer_vector_range ;
S44 : real_vector_range ;
S45 : time_vector_range ;
S46 : natural_vector_range ;
S47 : positive_vector_range ;
S48 : array_rec_std(zero to seven);
S49 : array_rec_cons(zero to seven);
S50 : array_rec_rec(zero to seven);
S51 : record_of_arr_of_record
);
END vests12;
ARCHITECTURE c01s01b01x01p05n02i00754arch OF vests12 IS
BEGIN
assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity error;
assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity error;
assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity error;
assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity error;
assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity error;
assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity error;
assert (S9'left = 15) report " severity_level_cons_vector error in the left generic value" severity error;
assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity error;
assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity error;
assert (S12'left = 15) report " time_cons_vector error in the left generic value" severity error;
assert (S13'left = 15) report " natural_cons_vector error in the left generic value" severity error;
assert (S14'left = 15) report " positive_cons_vector error in the left generic value" severity error;
assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity error;
assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity error;
assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity error;
assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity error;
assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity error;
assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity error;
assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity error;
assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity error;
assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity error;
assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S24.a'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.b'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.c'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.d'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.e'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.f'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.g'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity error;
assert (S26'left = 0) report " severity_level_vector_st error in the left generic value" severity error;
assert (S27'left = 0) report " integer_vector_st error in the left generic value" severity error;
assert (S28'left = 0) report " real_vector_st error in the left generic value" severity error;
assert (S29'left = 0) report " time_vector_st error in the left generic value" severity error;
assert (S30'left = 0) report " natural_vector_st error in the left generic value" severity error;
assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity error;
assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S36'left = 0) report " byte error in the left generic value" severity error;
assert (S37'left = 0) report " word error in the left generic value" severity error;
assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity error;
assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity error;
--assert (S40'left = 1) report " delay error in the left generic value" severity error;
assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity error;
assert (S42'left = 0) report " severity_level_vector_range error in the left generic value" severity error;
assert (S43'left = 0) report " integer_vector_range error in the left generic value" severity error;
assert (S44'left = 0) report " real_vector_range error in the left generic value" severity error;
assert (S45'left = 0) report " time_vector_range error in the left generic value" severity error;
assert (S46'left = 0) report " natural_vector_range error in the left generic value" severity error;
assert (S47'left = 0) report " positive_vector_range error in the left generic value" severity error;
assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity error;
assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity error;
assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity error;
assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity error;
assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity error;
assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity error;
assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity error;
assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity error;
assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity error;
assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity error;
assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity error;
assert (S9'right = 0) report " severity_level_cons_vector error in the right generic value" severity error;
assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity error;
assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity error;
assert (S12'right = 0) report " time_cons_vector error in the right generic value" severity error;
assert (S13'right = 0) report " natural_cons_vector error in the right generic value" severity error;
assert (S14'right = 0) report " positive_cons_vector error in the right generic value" severity error;
assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity error;
assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity error;
assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity error;
assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity error;
assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity error;
assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity error;
assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity error;
assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity error;
assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity error;
assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S24.a'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.b'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.c'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.d'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.e'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.f'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.g'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity error;
assert (S26'right = 15) report " severity_level_vector_st error in the right generic value" severity error;
assert (S27'right = 15) report " integer_vector_st error in the right generic value" severity error;
assert (S28'right = 15) report " real_vector_st error in the right generic value" severity error;
assert (S29'right = 15) report " time_vector_st error in the right generic value" severity error;
assert (S30'right = 15) report " natural_vector_st error in the right generic value" severity error;
assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity error;
assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S36'right = 7) report " byte error in the right generic value" severity error;
assert (S37'right = 15) report " word error in the right generic value" severity error;
assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity error;
assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity error;
--assert (S40'right = 1) report " delay error in the right generic value" severity error;
assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity error;
assert (S42'right = 7) report " severity_level_vector_range error in the right generic value" severity error;
assert (S43'right = 7) report " integer_vector_range error in the right generic value" severity error;
assert (S44'right = 7) report " real_vector_range error in the right generic value" severity error;
assert (S45'right = 7) report " time_vector_range error in the right generic value" severity error;
assert (S46'right = 7) report " natural_vector_range error in the right generic value" severity error;
assert (S47'right = 7) report " positive_vector_range error in the right generic value" severity error;
assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity error;
assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity error;
assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity error;
assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity error;
assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity error;
assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity error;
assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity error;
assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity error;
assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity error;
assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity error;
assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity error;
assert (S9'length = 16) report " severity_level_cons_vector error in the length generic value" severity error;
assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity error;
assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity error;
assert (S12'length = 16) report " time_cons_vector error in the length generic value" severity error;
assert (S13'length = 16) report " natural_cons_vector error in the length generic value" severity error;
assert (S14'length = 16) report " positive_cons_vector error in the length generic value" severity error;
assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity error;
assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity error;
assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity error;
assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity error;
assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity error;
assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity error;
assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity error;
assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity error;
assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity error;
assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S24.a'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.b'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.c'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.d'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.e'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.f'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.g'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity error;
assert (S26'length = 16) report " severity_level_vector_st error in the length generic value" severity error;
assert (S27'length = 16) report " integer_vector_st error in the length generic value" severity error;
assert (S28'length = 16) report " real_vector_st error in the length generic value" severity error;
assert (S29'length = 16) report " time_vector_st error in the length generic value" severity error;
assert (S30'length = 16) report " natural_vector_st error in the length generic value" severity error;
assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity error;
assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S36'length = 8) report " byte error in the length generic value" severity error;
assert (S37'length = 16) report " word error in the length generic value" severity error;
assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity error;
assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity error;
--assert (S40'length = 1) report " delay error in the length generic value" severity error;
assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity error;
assert (S42'length = 8) report " severity_level_vector_range error in the length generic value" severity error;
assert (S43'length = 8) report " integer_vector_range error in the length generic value" severity error;
assert (S44'length = 8) report " real_vector_range error in the length generic value" severity error;
assert (S45'length = 8) report " time_vector_range error in the length generic value" severity error;
assert (S46'length = 8) report " natural_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " positive_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity error;
assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity error;
assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity error;
assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
TESTING: PROCESS
BEGIN
assert NOT( (S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***PASSED TEST: c01s01b01x01p05n02i00754"
severity NOTE;
assert ((S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***FAILED TEST: c01s01b01x01p05n02i00754 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00754arch;
| gpl-3.0 | 6209d4346f8c3800ef04eb6820f4f1c6 | 0.569591 | 3.607781 | false | false | false | false |
nickg/nvc | test/lower/directmap.vhd | 1 | 642 | entity bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity directmap is
end entity;
architecture test of directmap is
signal x, y : integer;
begin
uut: entity work.bot
port map ( x, y );
process is
begin
x <= 0;
wait for 1 ns;
assert y = 1;
x <= 2;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
| gpl-3.0 | 19c9749587462c3e0b35b8745bf21395 | 0.465732 | 4.251656 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1464.vhd | 4 | 1,714 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1464.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p02n01i01464ent IS
END c08s08b00x00p02n01i01464ent;
ARCHITECTURE c08s08b00x00p02n01i01464arch OF c08s08b00x00p02n01i01464ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 1;
variable k : integer := 0;
BEGIN
case x
when 1 => k := 5;
when 2 => NULL;
when 3 => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p02n01i01464 - missing reserved word 'is'"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p02n01i01464arch;
| gpl-2.0 | 711f383899ada9393a6a8b3c7d8a315f | 0.660443 | 3.693966 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_valptr.vhd | 2 | 1,454 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_dhuff_tbl_valptr is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_dhuff_tbl_valptr;
architecture augh of p_jinfo_dc_dhuff_tbl_valptr is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(8 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | b82e8ab7561657547e2e1b3afb2829b3 | 0.675378 | 2.862205 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1313/issue.vhdl | 1 | 544 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
end issue;
architecture beh of issue is
begin
assert "+"(unsigned'("0001"), unsigned'("0001")) = unsigned'("0010");
assert "-"(unsigned'("0001"), unsigned'("0001")) = unsigned'("0000");
assert "="(unsigned'("0001"), unsigned'("0001"));
assert "+"(signed'("0001"), signed'("0001")) = signed'("0010");
assert "-"(signed'("0001"), signed'("0001")) = signed'("0000");
assert "="(signed'("0001"), signed'("0001"));
end architecture beh;
| gpl-2.0 | ae680e6bcbf981c8186da5eaed7d6c4d | 0.612132 | 4.02963 | false | false | false | false |
tgingold/ghdl | testsuite/synth/oper01/tb_cmp01.vhdl | 1 | 1,416 | entity tb_cmp01 is
end tb_cmp01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cmp01 is
signal l : std_logic_vector(3 downto 0);
signal r : std_logic_vector(3 downto 0);
signal eq : std_logic;
signal ne : std_logic;
signal lt : std_logic;
signal le : std_logic;
signal ge : std_logic;
signal gt : std_logic;
begin
cmp01_1: entity work.cmp01
port map (
l => l,
r => r,
eq => eq,
ne => ne,
lt => lt,
le => le,
ge => ge,
gt => gt);
process
begin
l <= x"5";
r <= x"7";
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '1' severity failure;
assert le = '1' severity failure;
assert ge = '0' severity failure;
assert gt = '0' severity failure;
l <= x"a";
r <= x"7";
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '0' severity failure;
assert le = '0' severity failure;
assert ge = '1' severity failure;
assert gt = '1' severity failure;
l <= x"9";
r <= x"9";
wait for 1 ns;
assert eq = '1' severity failure;
assert ne = '0' severity failure;
assert lt = '0' severity failure;
assert le = '1' severity failure;
assert ge = '1' severity failure;
assert gt = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | ca481ce666429e980eb3c51f532f110b | 0.575565 | 3.270208 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug0103/repro.vhdl | 1 | 411 | entity repro is
end repro;
entity buf is
port (i : bit; o : out bit);
end buf;
architecture behav of buf is
begin
o <= i;
end behav;
architecture behav of repro is
signal a, b : bit;
signal r : bit;
begin
dut: entity work.buf port map (i => a xor b, o => r);
process
begin
a <= '0';
b <= '1';
wait for 1 ns;
assert r = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | f4e676ef3b57de26413c623fa133362c | 0.59854 | 3.090226 | false | false | false | false |
nickg/nvc | test/regress/issue121.vhd | 5 | 1,135 | package A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean);
procedure PROC_B(I:in integer; O:out integer; Z:out boolean);
procedure PROC_C(I:in integer; O:out integer; Z:out boolean);
end package;
package body A is
procedure PROC_A(I:in integer; O:out integer; Z:out boolean) is
begin
-- Used to abort calling forward-declared procedure
PROC_B(I,O,Z);
end procedure;
procedure PROC_B(I:in integer; O:out integer; Z:out boolean) is
begin
PROC_C(I,O,Z);
end procedure;
procedure PROC_C(I:in integer; O:out integer; Z:out boolean) is
begin
O := I;
Z := (I = 0);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue121 is
end entity;
use work.A.all;
architecture test of issue121 is
begin
process is
variable o : integer;
variable z : boolean;
begin
proc_a(1, o, z);
assert o = 1;
assert not z;
proc_a(0, o, z);
assert o = 0;
assert z;
wait;
end process;
end architecture;
| gpl-3.0 | 09e4c72589afd928cb835fa3b7f35332 | 0.561233 | 3.61465 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug094/topb.vhdl | 1 | 498 | entity topb is
end topb;
architecture behav of topb is
signal clk : bit;
signal v : natural;
signal done : boolean := false;
begin
dut : entity work.entb
port map (clk => clk,
val => v);
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if done then
wait;
end if;
end process;
process
begin
v <= 2;
wait for 40 ns;
v <= 4;
wait for 80 ns;
done <= true;
wait;
end process;
end behav;
| gpl-2.0 | 71b747b8ab25ddbfd5e9f12717ab3ac8 | 0.542169 | 3.410959 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd | 4 | 1,912 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2506.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b04x00p03n01i02506ent IS
END c07s03b04x00p03n01i02506ent;
ARCHITECTURE c07s03b04x00p03n01i02506arch OF c07s03b04x00p03n01i02506ent IS
type rec_type is
record
x : bit;
y : integer;
z : boolean;
end record;
BEGIN
TESTING: PROCESS
variable S1 :rec_type;
BEGIN
S1 := rec_type'(bit'('0'), 1, true) ;-- No_Failure_here
assert NOT(S1.x='0' and S1.y=1 and S1.z=true)
report "***PASSED TEST: c07s03b04x00p03n01i02506"
severity NOTE;
assert (S1.x='0' and S1.y=1 and S1.z=true)
report "***FAILED TEST: c07s03b04x00p03n01i02506 - Expression type does not match type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b04x00p03n01i02506arch;
| gpl-2.0 | f1a44c81c55ac3b159b623133345ae5f | 0.655858 | 3.476364 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue635/fsm.vhdl | 1 | 31,984 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
-- %3 = alloca [3 x [4 x i32]], align 16
entity Ram0 is
generic
(
addressWidth : in positive;
busWidth : in positive;
size : in positive
);
port
(
clk : in std_logic;
address : in unsigned(addressWidth - 1 downto 0);
writeEnable : in std_logic;
dataIn : in std_logic_vector(busWidth - 1 downto 0);
dataOut : out std_logic_vector(busWidth - 1 downto 0)
);
end Ram0;
architecture Behavioral of Ram0 is
constant alignment : positive := busWidth / 8;
constant ramSize : positive := size / alignment;
type RamType is array(natural range <>) of std_logic_vector(busWidth - 1 downto 0);
subtype RamRange is natural range 0 to ramSize;
signal ram : RamType(RamRange) := (
0 => "00000000000000000000000000000001",
1 => "00000000000000000000000000000010",
2 => "00000000000000000000000000000011",
3 => "00000000000000000000000000000100",
4 => "00000000000000000000000000000010",
5 => "00000000000000000000000000000011",
6 => "00000000000000000000000000000100",
7 => "00000000000000000000000000000101",
8 => "00000000000000000000000000000011",
9 => "00000000000000000000000000000100",
10 => "00000000000000000000000000000101",
11 => "00000000000000000000000000000110",
others => "00000000000000000000000000000000");
begin
process(clk)
variable index : RamRange;
begin
if (rising_edge(clk))
then
index := to_integer(address) / alignment;
if (writeEnable = '1')
then
ram(index) <= dataIn;
end if;
dataOut <= ram(index);
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
-- %4 = alloca [2 x [2 x [2 x i32]]], align 16
entity Ram1 is
generic
(
addressWidth : in positive;
busWidth : in positive;
size : in positive
);
port
(
clk : in std_logic;
address : in unsigned(addressWidth - 1 downto 0);
writeEnable : in std_logic;
dataIn : in std_logic_vector(busWidth - 1 downto 0);
dataOut : out std_logic_vector(busWidth - 1 downto 0)
);
end Ram1;
architecture Behavioral of Ram1 is
constant alignment : positive := busWidth / 8;
constant ramSize : positive := size / alignment;
type RamType is array(natural range <>) of std_logic_vector(busWidth - 1 downto 0);
subtype RamRange is natural range 0 to ramSize;
signal ram : RamType(RamRange) := (
0 => "00000000000000000000000000000010",
1 => "00000000000000000000000000000010",
2 => "00000000000000000000000000000011",
3 => "00000000000000000000000000000100",
4 => "00000000000000000000000000000101",
5 => "00000000000000000000000000000110",
6 => "00000000000000000000000000000111",
7 => "00000000000000000000000000001000",
others => "00000000000000000000000000000000");
begin
process(clk)
variable index : RamRange;
begin
if (rising_edge(clk))
then
index := to_integer(address) / alignment;
if (writeEnable = '1')
then
ram(index) <= dataIn;
end if;
dataOut <= ram(index);
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
-- %5 = alloca [2 x [4 x double]], align 16
entity Ram2 is
generic
(
addressWidth : in positive;
busWidth : in positive;
size : in positive
);
port
(
clk : in std_logic;
address : in unsigned(addressWidth - 1 downto 0);
writeEnable : in std_logic;
dataIn : in std_logic_vector(busWidth - 1 downto 0);
dataOut : out std_logic_vector(busWidth - 1 downto 0)
);
end Ram2;
architecture Behavioral of Ram2 is
constant alignment : positive := busWidth / 8;
constant ramSize : positive := size / alignment;
type RamType is array(natural range <>) of std_logic_vector(busWidth - 1 downto 0);
subtype RamRange is natural range 0 to ramSize;
signal ram : RamType(RamRange) := (
0 => "10011001100110011001100110011010",
1 => "00111111101110011001100110011001",
2 => "10011001100110011001100110011010",
3 => "00111111110010011001100110011001",
4 => "00110011001100110011001100110011",
5 => "00111111110100110011001100110011",
6 => "10011001100110011001100110011010",
7 => "00111111110110011001100110011001",
8 => "10011001100110011001100110011010",
9 => "00111111110010011001100110011001",
10 => "00110011001100110011001100110011",
11 => "00111111110100110011001100110011",
12 => "10011001100110011001100110011010",
13 => "00111111110110011001100110011001",
14 => "00000000000000000000000000000000",
15 => "00111111111000000000000000000000",
others => "00000000000000000000000000000000");
begin
process(clk)
variable index : RamRange;
begin
if (rising_edge(clk))
then
index := to_integer(address) / alignment;
if (writeEnable = '1')
then
ram(index) <= dataIn;
end if;
dataOut <= ram(index);
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
entity Function_Z3fooi is
port
(
clk : in std_logic;
reset : in std_logic;
input1 : in signed(31 downto 0);
output : out signed(31 downto 0);
ready : out std_logic
);
end Function_Z3fooi;
architecture behavioral of Function_Z3fooi is
signal stackPointer : unsigned(7 downto 0);
signal ramAddress : unsigned(7 downto 0);
signal ramWriteEnable : std_logic;
signal ramDataIn : std_logic_vector(31 downto 0);
signal ramDataOut : std_logic_vector(31 downto 0);
-- signals for Ram0
signal ramAddress0 : unsigned(7 downto 0);
signal ramWriteEnable0 : std_logic;
signal ramDataIn0 : std_logic_vector(31 downto 0);
signal ramDataOut0 : std_logic_vector(31 downto 0);
-- signals for Ram1
signal ramAddress1 : unsigned(7 downto 0);
signal ramWriteEnable1 : std_logic;
signal ramDataIn1 : std_logic_vector(31 downto 0);
signal ramDataOut1 : std_logic_vector(31 downto 0);
-- signals for Ram2
signal ramAddress2 : unsigned(7 downto 0);
signal ramWriteEnable2 : std_logic;
signal ramDataIn2 : std_logic_vector(31 downto 0);
signal ramDataOut2 : std_logic_vector(31 downto 0);
begin
ramInstance : entity work.Ram
generic map
(
addressWidth => 8,
busWidth => 32,
size => 256
)
port map
(
clk => clk,
address => ramAddress,
writeEnable => ramWriteEnable,
dataIn => ramDataIn,
dataOut => ramDataOut
);
ramInstance0 : entity work.Ram0
generic map
(
addressWidth => 8,
busWidth => 32,
size => 256
)
port map
(
clk => clk,
address => ramAddress0,
writeEnable => ramWriteEnable0,
dataIn => ramDataIn0,
dataOut => ramDataOut0
);
ramInstance1 : entity work.Ram1
generic map
(
addressWidth => 8,
busWidth => 32,
size => 256
)
port map
(
clk => clk,
address => ramAddress1,
writeEnable => ramWriteEnable1,
dataIn => ramDataIn1,
dataOut => ramDataOut1
);
ramInstance2 : entity work.Ram2
generic map
(
addressWidth => 8,
busWidth => 32,
size => 256
)
port map
(
clk => clk,
address => ramAddress2,
writeEnable => ramWriteEnable2,
dataIn => ramDataIn2,
dataOut => ramDataOut2
);
process(clk, reset)
type State is (block1_cycle1, block1_cycle2, block1_cycle3, block1_cycle4, block1_cycle5, block1_cycle6, block1_cycle7, block1_cycle8, block1_cycle9, block1_cycle10, block1_cycle11, block2_cycle1, block2_cycle2, block2_cycle3, block4_cycle1, block5_cycle1, block5_cycle2, block5_cycle3, block7_cycle1, block8_cycle1, block8_cycle2, block8_cycle3, block10_cycle1, block10_cycle2, block10_cycle3, block10_cycle4, block10_cycle5, block10_cycle6, block10_cycle7, block10_cycle8, block11_cycle1, block11_cycle2, block11_cycle3, block9_cycle1, block12_cycle1, block12_cycle2, block12_cycle3, block6_cycle1, block13_cycle1, block13_cycle2, block13_cycle3, block3_cycle1, block14_cycle1, block14_cycle2, block14_cycle3, block16_cycle1, block17_cycle1, block17_cycle2, block17_cycle3, block19_cycle1, block19_cycle2, block19_cycle3, block19_cycle4, block19_cycle5, block19_cycle6, block19_cycle7, block19_cycle8, block19_cycle9, block19_cycle10, block19_cycle11, block19_cycle12, block19_cycle13, block19_cycle14, block19_cycle15, block20_cycle1, block20_cycle2, block20_cycle3, block18_cycle1, block21_cycle1, block21_cycle2, block21_cycle3, block15_cycle1, block22_cycle1, block22_cycle2, block22_cycle3, block24_cycle1, block24_cycle2, block24_cycle3, block24_cycle4, block24_cycle5, block24_cycle6, block25_cycle1, block25_cycle2, block25_cycle3, block23_cycle1, block23_cycle2, block23_cycle3);
variable lastState, currentState, nextState : State;
variable retValWritten : std_logic := '0';
variable variable84 : signed(31 downto 0);
variable variable82 : signed(7 downto 0);
variable variable81 : signed(7 downto 0);
variable variable79 : signed(31 downto 0);
variable variable15 : signed(31 downto 0);
variable variable32 : signed(31 downto 0);
variable variable29 : signed(31 downto 0);
variable variable52 : signed(7 downto 0);
variable variable76 : signed(31 downto 0);
variable variable27 : signed(7 downto 0);
variable variable38 : signed(7 downto 0);
variable variable80 : signed(7 downto 0);
variable variable26 : signed(63 downto 0);
variable variable22 : signed(0 downto 0);
variable variable21 : signed(31 downto 0);
variable variable20 : signed(7 downto 0);
variable variable18 : signed(31 downto 0);
variable variable30 : signed(7 downto 0);
variable variable53 : signed(31 downto 0);
variable variable19 : signed(0 downto 0);
variable variable40 : signed(7 downto 0);
variable variable55 : signed(7 downto 0);
variable variable25 : signed(7 downto 0);
variable variable64 : signed(7 downto 0);
variable variable17 : signed(7 downto 0);
variable variable6 : signed(7 downto 0);
variable variable4 : unsigned(7 downto 0);
variable variable28 : signed(63 downto 0);
variable variable1 : unsigned(7 downto 0);
variable variable5 : signed(31 downto 0);
variable variable75 : signed(63 downto 0);
variable variable3 : unsigned(7 downto 0);
variable variable2 : unsigned(7 downto 0);
variable variable34 : signed(7 downto 0);
variable variable7 : unsigned(7 downto 0);
variable variable31 : signed(31 downto 0);
variable variable16 : signed(0 downto 0);
variable variable13 : unsigned(7 downto 0);
variable variable11 : unsigned(7 downto 0);
variable variable39 : signed(7 downto 0);
variable variable12 : unsigned(7 downto 0);
variable variable56 : signed(7 downto 0);
variable variable37 : signed(7 downto 0);
variable variable42 : signed(0 downto 0);
variable variable83 : signed(7 downto 0);
variable variable67 : signed(7 downto 0);
variable variable24 : signed(63 downto 0);
variable variable43 : signed(7 downto 0);
variable variable59 : signed(63 downto 0);
variable variable36 : signed(7 downto 0);
variable variable46 : signed(31 downto 0);
variable variable10 : unsigned(7 downto 0);
variable variable68 : signed(7 downto 0);
variable variable70 : signed(31 downto 0);
variable variable47 : signed(7 downto 0);
variable variable33 : signed(7 downto 0);
variable variable74 : signed(31 downto 0);
variable variable14 : signed(7 downto 0);
variable variable48 : signed(31 downto 0);
variable variable23 : signed(7 downto 0);
variable variable49 : signed(31 downto 0);
variable variable50 : signed(7 downto 0);
variable variable57 : signed(63 downto 0);
variable variable65 : signed(7 downto 0);
variable variable51 : signed(31 downto 0);
variable variable8 : unsigned(7 downto 0);
variable variable72 : signed(7 downto 0);
variable variable54 : signed(31 downto 0);
variable variable45 : signed(0 downto 0);
variable variable63 : signed(31 downto 0);
variable variable35 : signed(7 downto 0);
variable variable58 : signed(7 downto 0);
variable variable78 : signed(31 downto 0);
variable variable41 : signed(31 downto 0);
variable variable60 : signed(31 downto 0);
variable variable61 : signed(7 downto 0);
variable variable66 : signed(7 downto 0);
variable variable69 : signed(7 downto 0);
variable variable71 : signed(0 downto 0);
variable variable9 : unsigned(7 downto 0);
variable variable73 : signed(31 downto 0);
variable variable62 : signed(31 downto 0);
variable variable44 : signed(31 downto 0);
variable variable77 : signed(7 downto 0);
begin
if (reset = '1')
then
currentState := block1_cycle1;
stackPointer <= (others => '0');
ready <= '0';
elsif (rising_edge(clk))
then
-- default values
ready <= '0';
ramAddress <= (others => '0');
ramWriteEnable <= '0';
ramDataIn <= (others => '0');
ramAddress0 <= (others => '0');
ramWriteEnable0 <= '0';
ramDataIn0 <= (others => '0');
ramAddress1 <= (others => '0');
ramWriteEnable1 <= '0';
ramDataIn1 <= (others => '0');
ramAddress2 <= (others => '0');
ramWriteEnable2 <= '0';
ramDataIn2 <= (others => '0');
case currentState is
-- block1
when block1_cycle1 =>
-- alloca
variable1 := stackPointer;
stackPointer <= stackPointer + 4;
-- store cycle 0
ramAddress <= variable1;
ramDataIn <= std_logic_vector(input1);
ramWriteEnable <= '1';
nextState := block1_cycle2;
when block1_cycle2 =>
-- alloca
variable2 := stackPointer;
stackPointer <= stackPointer + 16;
-- load cycle 0
ramAddress <= variable1;
nextState := block1_cycle3;
when block1_cycle3 =>
-- alloca
variable3 := stackPointer;
stackPointer <= stackPointer + 16;
-- load cycle 1
nextState := block1_cycle4;
when block1_cycle4 =>
-- alloca
variable4 := stackPointer;
stackPointer <= stackPointer + 16;
-- load cycle 2
variable5 := signed(ramDataOut);
variable6 := resize(variable5, 8);
nextState := block1_cycle5;
when block1_cycle5 =>
-- alloca
variable7 := stackPointer;
stackPointer <= stackPointer + 4;
-- store cycle 0
ramAddress <= variable7;
ramDataIn(7 downto 0) <= std_logic_vector(variable6);
ramWriteEnable <= '1';
nextState := block1_cycle6;
when block1_cycle6 =>
-- alloca
variable8 := stackPointer;
stackPointer <= stackPointer + 4;
-- store cycle 0
ramAddress <= variable8;
ramDataIn(7 downto 0) <= std_logic_vector(to_signed(0, 8));
ramWriteEnable <= '1';
nextState := block1_cycle7;
when block1_cycle7 =>
-- alloca
variable9 := stackPointer;
stackPointer <= stackPointer + 4;
nextState := block1_cycle8;
when block1_cycle8 =>
-- alloca
variable10 := stackPointer;
stackPointer <= stackPointer + 4;
nextState := block1_cycle9;
when block1_cycle9 =>
-- alloca
variable11 := stackPointer;
stackPointer <= stackPointer + 4;
nextState := block1_cycle10;
when block1_cycle10 =>
-- alloca
variable12 := stackPointer;
stackPointer <= stackPointer + 4;
nextState := block1_cycle11;
when block1_cycle11 =>
-- alloca
variable13 := stackPointer;
stackPointer <= stackPointer + 4;
nextState := block2_cycle1;
-- block2
when block2_cycle1 =>
-- load cycle 0
ramAddress <= variable8;
nextState := block2_cycle2;
when block2_cycle2 =>
-- load cycle 1
nextState := block2_cycle3;
when block2_cycle3 =>
-- load cycle 2
variable14 := signed(ramDataOut(7 downto 0));
variable15 := signed(resize(unsigned(variable14), 32));
if (variable15 < to_signed(2, 32)) then
variable16 := "1";
else
variable16 := "0";
end if;
if(variable16(0) = '1')then
nextState := block4_cycle1;
else
nextState := block3_cycle1;
end if;
-- block4
when block4_cycle1 =>
-- store cycle 0
ramAddress <= variable9;
ramDataIn(7 downto 0) <= std_logic_vector(to_signed(0, 8));
ramWriteEnable <= '1';
nextState := block5_cycle1;
-- block5
when block5_cycle1 =>
-- load cycle 0
ramAddress <= variable9;
nextState := block5_cycle2;
when block5_cycle2 =>
-- load cycle 1
nextState := block5_cycle3;
when block5_cycle3 =>
-- load cycle 2
variable17 := signed(ramDataOut(7 downto 0));
variable18 := signed(resize(unsigned(variable17), 32));
if (variable18 < to_signed(2, 32)) then
variable19 := "1";
else
variable19 := "0";
end if;
if(variable19(0) = '1')then
nextState := block7_cycle1;
else
nextState := block6_cycle1;
end if;
-- block7
when block7_cycle1 =>
-- store cycle 0
ramAddress <= variable10;
ramDataIn(7 downto 0) <= std_logic_vector(to_signed(0, 8));
ramWriteEnable <= '1';
nextState := block8_cycle1;
-- block8
when block8_cycle1 =>
-- load cycle 0
ramAddress <= variable10;
nextState := block8_cycle2;
when block8_cycle2 =>
-- load cycle 1
nextState := block8_cycle3;
when block8_cycle3 =>
-- load cycle 2
variable20 := signed(ramDataOut(7 downto 0));
variable21 := signed(resize(unsigned(variable20), 32));
if (variable21 < to_signed(2, 32)) then
variable22 := "1";
else
variable22 := "0";
end if;
if(variable22(0) = '1')then
nextState := block10_cycle1;
else
nextState := block9_cycle1;
end if;
-- block10
when block10_cycle1 =>
-- load cycle 0
ramAddress <= variable8;
nextState := block10_cycle2;
when block10_cycle2 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable9;
nextState := block10_cycle3;
when block10_cycle3 =>
-- load cycle 2
variable23 := signed(ramDataOut(7 downto 0));
variable24 := signed(resize(unsigned(variable23), 64));
-- %35 = getelementptr inbounds [2 x [2 x [2 x i32]]], [2 x [2 x [2 x i32]]]* %4, i64 0, i64 %34
variable3 := unsigned(resize(unsigned(variable24 * 4), 8));
-- load cycle 1
-- load cycle 0
ramAddress <= variable10;
nextState := block10_cycle4;
when block10_cycle4 =>
-- load cycle 2
variable25 := signed(ramDataOut(7 downto 0));
variable26 := signed(resize(unsigned(variable25), 64));
-- %38 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %35, i64 0, i64 %37
variable3 := variable3 + unsigned(resize(unsigned(variable26 * 2), 8));
-- load cycle 1
nextState := block10_cycle5;
when block10_cycle5 =>
-- load cycle 2
variable27 := signed(ramDataOut(7 downto 0));
variable28 := signed(resize(unsigned(variable27), 64));
-- %41 = getelementptr inbounds [2 x i32], [2 x i32]* %38, i64 0, i64 %40
variable3 := variable3 + unsigned(resize(unsigned(variable28 * 1), 8));
variable3 := unsigned(resize(unsigned(variable3 * 4), 8));
-- load cycle 0
ramAddress1 <= variable3;
nextState := block10_cycle6;
when block10_cycle6 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable7;
nextState := block10_cycle7;
when block10_cycle7 =>
-- load cycle 2
variable29 := signed(ramDataOut1);
-- load cycle 1
nextState := block10_cycle8;
when block10_cycle8 =>
-- load cycle 2
variable30 := signed(ramDataOut(7 downto 0));
variable31 := signed(resize(unsigned(variable30), 32));
variable32 := variable31 + variable29;
variable33 := resize(variable32, 8);
-- store cycle 0
ramAddress <= variable7;
ramDataIn(7 downto 0) <= std_logic_vector(variable33);
ramWriteEnable <= '1';
nextState := block11_cycle1;
-- block11
when block11_cycle1 =>
-- load cycle 0
ramAddress <= variable10;
nextState := block11_cycle2;
when block11_cycle2 =>
-- load cycle 1
nextState := block11_cycle3;
when block11_cycle3 =>
-- load cycle 2
variable34 := signed(ramDataOut(7 downto 0));
variable35 := variable34 + to_signed(1, 8);
-- store cycle 0
ramAddress <= variable10;
ramDataIn(7 downto 0) <= std_logic_vector(variable35);
ramWriteEnable <= '1';
nextState := block8_cycle1;
-- block9
when block9_cycle1 =>
nextState := block12_cycle1;
-- block12
when block12_cycle1 =>
-- load cycle 0
ramAddress <= variable9;
nextState := block12_cycle2;
when block12_cycle2 =>
-- load cycle 1
nextState := block12_cycle3;
when block12_cycle3 =>
-- load cycle 2
variable36 := signed(ramDataOut(7 downto 0));
variable37 := variable36 + to_signed(1, 8);
-- store cycle 0
ramAddress <= variable9;
ramDataIn(7 downto 0) <= std_logic_vector(variable37);
ramWriteEnable <= '1';
nextState := block5_cycle1;
-- block6
when block6_cycle1 =>
nextState := block13_cycle1;
-- block13
when block13_cycle1 =>
-- load cycle 0
ramAddress <= variable8;
nextState := block13_cycle2;
when block13_cycle2 =>
-- load cycle 1
nextState := block13_cycle3;
when block13_cycle3 =>
-- load cycle 2
variable38 := signed(ramDataOut(7 downto 0));
variable39 := variable38 + to_signed(1, 8);
-- store cycle 0
ramAddress <= variable8;
ramDataIn(7 downto 0) <= std_logic_vector(variable39);
ramWriteEnable <= '1';
nextState := block2_cycle1;
-- block3
when block3_cycle1 =>
-- store cycle 0
ramAddress <= variable11;
ramDataIn(7 downto 0) <= std_logic_vector(to_signed(0, 8));
ramWriteEnable <= '1';
nextState := block14_cycle1;
-- block14
when block14_cycle1 =>
-- load cycle 0
ramAddress <= variable11;
nextState := block14_cycle2;
when block14_cycle2 =>
-- load cycle 1
nextState := block14_cycle3;
when block14_cycle3 =>
-- load cycle 2
variable40 := signed(ramDataOut(7 downto 0));
variable41 := resize(variable40, 32);
if (variable41 < to_signed(1, 32)) then
variable42 := "1";
else
variable42 := "0";
end if;
if(variable42(0) = '1')then
nextState := block16_cycle1;
else
nextState := block15_cycle1;
end if;
-- block16
when block16_cycle1 =>
-- store cycle 0
ramAddress <= variable12;
ramDataIn(7 downto 0) <= std_logic_vector(to_signed(0, 8));
ramWriteEnable <= '1';
nextState := block17_cycle1;
-- block17
when block17_cycle1 =>
-- load cycle 0
ramAddress <= variable12;
nextState := block17_cycle2;
when block17_cycle2 =>
-- load cycle 1
nextState := block17_cycle3;
when block17_cycle3 =>
-- load cycle 2
variable43 := signed(ramDataOut(7 downto 0));
variable44 := resize(variable43, 32);
if (variable44 < to_signed(2, 32)) then
variable45 := "1";
else
variable45 := "0";
end if;
if(variable45(0) = '1')then
nextState := block19_cycle1;
else
nextState := block18_cycle1;
end if;
-- block19
when block19_cycle1 =>
-- %69 = getelementptr inbounds [2 x [2 x [2 x i32]]], [2 x [2 x [2 x i32]]]* %4, i64 0, i64 1
variable3 := resize(unsigned(to_unsigned(4, 64)), 8);
-- %70 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %69, i64 0, i64 1
variable3 := variable3 + resize(unsigned(to_unsigned(2, 64)), 8);
-- %71 = getelementptr inbounds [2 x i32], [2 x i32]* %70, i64 0, i64 1
variable3 := variable3 + resize(unsigned(to_unsigned(1, 64)), 8);
variable3 := unsigned(resize(unsigned(variable3 * 4), 8));
-- load cycle 0
ramAddress1 <= variable3;
-- %77 = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]]* %3, i64 0, i64 2
variable2 := resize(unsigned(to_unsigned(6, 64)), 8);
-- %78 = getelementptr inbounds [4 x i32], [4 x i32]* %77, i64 0, i64 3
variable2 := variable2 + resize(unsigned(to_unsigned(3, 64)), 8);
variable2 := unsigned(resize(unsigned(variable2 * 4), 8));
nextState := block19_cycle2;
when block19_cycle2 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable7;
nextState := block19_cycle3;
when block19_cycle3 =>
-- load cycle 2
variable46 := signed(ramDataOut1);
-- load cycle 1
nextState := block19_cycle4;
when block19_cycle4 =>
-- load cycle 2
variable47 := signed(ramDataOut(7 downto 0));
variable48 := signed(resize(unsigned(variable47), 32));
variable49 := variable48 + variable46;
variable50 := resize(variable49, 8);
-- store cycle 0
ramAddress <= variable7;
ramDataIn(7 downto 0) <= std_logic_vector(variable50);
ramWriteEnable <= '1';
nextState := block19_cycle5;
when block19_cycle5 =>
-- load cycle 0
ramAddress0 <= variable2;
nextState := block19_cycle6;
when block19_cycle6 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable7;
nextState := block19_cycle7;
when block19_cycle7 =>
-- load cycle 2
variable51 := signed(ramDataOut0);
-- load cycle 1
nextState := block19_cycle8;
when block19_cycle8 =>
-- load cycle 2
variable52 := signed(ramDataOut(7 downto 0));
variable53 := signed(resize(unsigned(variable52), 32));
variable54 := variable53 + variable51;
variable55 := resize(variable54, 8);
-- store cycle 0
ramAddress <= variable7;
ramDataIn(7 downto 0) <= std_logic_vector(variable55);
ramWriteEnable <= '1';
nextState := block19_cycle9;
when block19_cycle9 =>
-- load cycle 0
ramAddress <= variable11;
nextState := block19_cycle10;
when block19_cycle10 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable12;
nextState := block19_cycle11;
when block19_cycle11 =>
-- load cycle 2
variable56 := signed(ramDataOut(7 downto 0));
variable57 := resize(variable56, 64);
-- %86 = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]]* %3, i64 0, i64 %85
variable2 := unsigned(resize(unsigned(variable57 * 3), 8));
-- load cycle 1
nextState := block19_cycle12;
when block19_cycle12 =>
-- load cycle 2
variable58 := signed(ramDataOut(7 downto 0));
variable59 := resize(variable58, 64);
-- %89 = getelementptr inbounds [4 x i32], [4 x i32]* %86, i64 0, i64 %88
variable2 := variable2 + unsigned(resize(unsigned(variable59 * 1), 8));
variable2 := unsigned(resize(unsigned(variable2 * 4), 8));
-- load cycle 0
ramAddress0 <= variable2;
nextState := block19_cycle13;
when block19_cycle13 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable7;
nextState := block19_cycle14;
when block19_cycle14 =>
-- load cycle 2
variable60 := signed(ramDataOut0);
-- load cycle 1
nextState := block19_cycle15;
when block19_cycle15 =>
-- load cycle 2
variable61 := signed(ramDataOut(7 downto 0));
variable62 := signed(resize(unsigned(variable61), 32));
variable63 := variable62 + variable60;
variable64 := resize(variable63, 8);
-- store cycle 0
ramAddress <= variable7;
ramDataIn(7 downto 0) <= std_logic_vector(variable64);
ramWriteEnable <= '1';
nextState := block20_cycle1;
-- block20
when block20_cycle1 =>
-- load cycle 0
ramAddress <= variable12;
nextState := block20_cycle2;
when block20_cycle2 =>
-- load cycle 1
nextState := block20_cycle3;
when block20_cycle3 =>
-- load cycle 2
variable65 := signed(ramDataOut(7 downto 0));
variable66 := variable65 + to_signed(1, 8);
-- store cycle 0
ramAddress <= variable12;
ramDataIn(7 downto 0) <= std_logic_vector(variable66);
ramWriteEnable <= '1';
nextState := block17_cycle1;
-- block18
when block18_cycle1 =>
nextState := block21_cycle1;
-- block21
when block21_cycle1 =>
-- load cycle 0
ramAddress <= variable11;
nextState := block21_cycle2;
when block21_cycle2 =>
-- load cycle 1
nextState := block21_cycle3;
when block21_cycle3 =>
-- load cycle 2
variable67 := signed(ramDataOut(7 downto 0));
variable68 := variable67 + to_signed(1, 8);
-- store cycle 0
ramAddress <= variable11;
ramDataIn(7 downto 0) <= std_logic_vector(variable68);
ramWriteEnable <= '1';
nextState := block14_cycle1;
-- block15
when block15_cycle1 =>
-- store cycle 0
ramAddress <= variable13;
ramDataIn(7 downto 0) <= std_logic_vector(to_signed(0, 8));
ramWriteEnable <= '1';
nextState := block22_cycle1;
-- block22
when block22_cycle1 =>
-- load cycle 0
ramAddress <= variable13;
nextState := block22_cycle2;
when block22_cycle2 =>
-- load cycle 1
nextState := block22_cycle3;
when block22_cycle3 =>
-- load cycle 2
variable69 := signed(ramDataOut(7 downto 0));
variable70 := resize(variable69, 32);
if (variable70 < to_signed(2, 32)) then
variable71 := "1";
else
variable71 := "0";
end if;
if(variable71(0) = '1')then
nextState := block24_cycle1;
else
nextState := block23_cycle1;
end if;
-- block24
when block24_cycle1 =>
-- %108 = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]]* %3, i64 0, i64 0
variable2 := resize(unsigned(to_unsigned(0, 64)), 8);
-- load cycle 0
ramAddress <= variable13;
nextState := block24_cycle2;
when block24_cycle2 =>
-- load cycle 1
nextState := block24_cycle3;
when block24_cycle3 =>
-- load cycle 2
variable72 := signed(ramDataOut(7 downto 0));
variable73 := resize(variable72, 32);
variable74 := variable73 + to_signed(2, 32);
variable75 := resize(variable74, 64);
-- %113 = getelementptr inbounds [4 x i32], [4 x i32]* %108, i64 0, i64 %112
variable2 := variable2 + unsigned(resize(unsigned(variable75 * 1), 8));
variable2 := unsigned(resize(unsigned(variable2 * 4), 8));
-- load cycle 0
ramAddress0 <= variable2;
nextState := block24_cycle4;
when block24_cycle4 =>
-- load cycle 1
-- load cycle 0
ramAddress <= variable7;
nextState := block24_cycle5;
when block24_cycle5 =>
-- load cycle 2
variable76 := signed(ramDataOut0);
-- load cycle 1
nextState := block24_cycle6;
when block24_cycle6 =>
-- load cycle 2
variable77 := signed(ramDataOut(7 downto 0));
variable78 := signed(resize(unsigned(variable77), 32));
variable79 := variable78 + variable76;
variable80 := resize(variable79, 8);
-- store cycle 0
ramAddress <= variable7;
ramDataIn(7 downto 0) <= std_logic_vector(variable80);
ramWriteEnable <= '1';
nextState := block25_cycle1;
-- block25
when block25_cycle1 =>
-- load cycle 0
ramAddress <= variable13;
nextState := block25_cycle2;
when block25_cycle2 =>
-- load cycle 1
nextState := block25_cycle3;
when block25_cycle3 =>
-- load cycle 2
variable81 := signed(ramDataOut(7 downto 0));
variable82 := variable81 + to_signed(1, 8);
-- store cycle 0
ramAddress <= variable13;
ramDataIn(7 downto 0) <= std_logic_vector(variable82);
ramWriteEnable <= '1';
nextState := block22_cycle1;
-- block23
when block23_cycle1 =>
-- load cycle 0
ramAddress <= variable7;
nextState := block23_cycle2;
when block23_cycle2 =>
-- load cycle 1
nextState := block23_cycle3;
when block23_cycle3 =>
-- load cycle 2
variable83 := signed(ramDataOut(7 downto 0));
variable84 := signed(resize(unsigned(variable83), 32));
ready <= '1';
if (retValWritten = '0') then
output <= variable84;
retValWritten := '1';
end if;
end case;
lastState := currentState;
currentState := nextState;
end if;
end process;
end behavioral;
| gpl-2.0 | b64b903dddd81290775d1846c99f4f80 | 0.648355 | 3.39065 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd | 4 | 1,940 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.thermal_systems.all;
entity tb_diode is
end tb_diode;
architecture TB_diode of tb_diode is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
terminal r1_d1 : electrical;
terminal temp_in : thermal;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
tmp : entity work.TempConstant(ideal)
generic map(
level => 100.0
)
port map(
th1 => temp_in,
th2 => thermal_REF
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_src,
p2 => r1_d1
);
D1 : entity work.diode(one)
port map(
p => r1_d1,
m => electrical_ref,
j => temp_in
);
end TB_diode;
| gpl-2.0 | fa3eba1dec567b599e893fcefba03ae9 | 0.616495 | 3.983573 | false | false | false | false |
nickg/nvc | test/regress/vests27.vhd | 1 | 16,493 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01945pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- ----------------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01945pkg.all;
ENTITY vests27 IS
END vests27;
ARCHITECTURE c07s02b01x00p01n02i01945arch OF vests27 IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT AND_C_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
CONSTANT AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT AND_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
CONSTANT AND_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL AND_S_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
SIGNAL AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL AND_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
SIGNAL AND_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_1 : t_csa1_1 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE AND_V_csa1_3 : t_csa1_3 := ( '1', '0', '0', '0' );
VARIABLE AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE AND_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, FALSE, FALSE );
VARIABLE AND_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, FALSE, FALSE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4
REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4
REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test AND operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4
REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01945"
severity NOTE;
assert ( ( ARGA_C_csa1_1 AND ARGB_C_csa1_1 ) = AND_C_csa1_1 and
( ARGA_C_csa1_2 AND ARGB_C_csa1_2 ) = AND_C_csa1_2 and
( ARGA_C_csa1_3 AND ARGB_C_csa1_3 ) = AND_C_csa1_3 and
( ARGA_C_csa1_4 AND ARGB_C_csa1_4 ) = AND_C_csa1_4 and
( ARGA_C_usa1_1 AND ARGB_C_usa1_1 ) = AND_C_usa1_1 and
( ARGA_C_usa1_2 AND ARGB_C_usa1_2 ) = AND_C_usa1_2 and
( ARGA_C_usa1_3 AND ARGB_C_usa1_3 ) = AND_C_usa1_3 and
( ARGA_C_usa1_4 AND ARGB_C_usa1_4 ) = AND_C_usa1_4 and
( ARGA_S_csa1_1 AND ARGB_S_csa1_1 ) = AND_S_csa1_1 and
( ARGA_S_csa1_2 AND ARGB_S_csa1_2 ) = AND_S_csa1_2 and
( ARGA_S_csa1_3 AND ARGB_S_csa1_3 ) = AND_S_csa1_3 and
( ARGA_S_csa1_4 AND ARGB_S_csa1_4 ) = AND_S_csa1_4 and
( ARGA_S_usa1_1 AND ARGB_S_usa1_1 ) = AND_S_usa1_1 and
( ARGA_S_usa1_2 AND ARGB_S_usa1_2 ) = AND_S_usa1_2 and
( ARGA_S_usa1_3 AND ARGB_S_usa1_3 ) = AND_S_usa1_3 and
( ARGA_S_usa1_4 AND ARGB_S_usa1_4 ) = AND_S_usa1_4 and
( ARGA_V_csa1_1 AND ARGB_V_csa1_1 ) = AND_V_csa1_1 and
( ARGA_V_csa1_2 AND ARGB_V_csa1_2 ) = AND_V_csa1_2 and
( ARGA_V_csa1_3 AND ARGB_V_csa1_3 ) = AND_V_csa1_3 and
( ARGA_V_csa1_4 AND ARGB_V_csa1_4 ) = AND_V_csa1_4 and
( ARGA_V_usa1_1 AND ARGB_V_usa1_1 ) = AND_V_usa1_1 and
( ARGA_V_usa1_2 AND ARGB_V_usa1_2 ) = AND_V_usa1_2 and
( ARGA_V_usa1_3 AND ARGB_V_usa1_3 ) = AND_V_usa1_3 and
( ARGA_V_usa1_4 AND ARGB_V_usa1_4 ) = AND_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01945arch;
| gpl-3.0 | 462ffb6c9f5a38897c682a4c3a32736d | 0.544473 | 2.619184 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd | 4 | 2,269 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1028.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01028ent IS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type A2 is array (THREE, THREE) of BOOLEAN;
type A3 is array (THREE) of A1;
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: A2;
end record;
type R3 is record
RE3: A3;
end record;
END c06s04b00x00p02n01i01028ent;
ARCHITECTURE c06s04b00x00p02n01i01028arch OF c06s04b00x00p02n01i01028ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
variable V1: R1 ; -- := (RE1=>(others=>TRUE));
variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));
variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
BEGIN
V := V1.RE1(1);
assert NOT( V=false )
report "***PASSED TEST: c06s04b00x00p02n01i01028"
severity NOTE;
assert ( V=false )
report "***FAILED TEST: c06s04b00x00p02n01i01028 - The prefix of an indexed name can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01028arch;
| gpl-2.0 | 9da8ed3e89982ecd873ce2a16baeea2b | 0.630674 | 3.624601 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug21487/repro.vhdl | 3 | 899 | entity top is
end top;
use std.textio.all;
architecture ARCH of TOP is
type int_vector is array (integer range<>) of integer;
function driver_counter( values : int_vector ) return integer is
variable result : integer := 1;
variable l: line;
begin
for index in values'range loop
if values(index) /= 0 then
result := result + values (index);
write (l, integer'image(values(index)) & ",");
end if;
end loop;
report l.all & " count resolved => " & integer'image(result);
return result;
end function;
signal S1: driver_counter integer := 6;
begin
s1 <= 1 after 1 ns;
check: process
begin
assert s1 = 7 report "resolution function not called at init"
severity failure;
wait for 1 ns;
assert s1 = 2 report "resolution function not called at 1 ns"
severity failure;
wait;
end process;
end architecture;
| gpl-2.0 | b72f50e721acebf413fdcc7d66a893fa | 0.649611 | 3.891775 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug019/PoC/src/common/strings.vhdl | 2 | 30,073 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
constant C_POC_NUL : CHARACTER := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- character 0 causes Quartus to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is STD_LOGIC_VECTOR(7 downto 0);
type T_RAWSTRING is array (NATURAL range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : STRING) return T_IPSTYLE;
-- to_char
function to_char(value : STD_LOGIC) return CHARACTER;
function to_char(value : NATURAL) return CHARACTER;
function to_char(rawchar : T_RAWCHAR) return CHARACTER;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(value : BOOLEAN) return STRING;
function raw_format_bool_chr(value : BOOLEAN) return STRING;
function raw_format_bool_str(value : BOOLEAN) return STRING;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING;
function raw_format_nat_bin(value : NATURAL) return STRING;
function raw_format_nat_oct(value : NATURAL) return STRING;
function raw_format_nat_dec(value : NATURAL) return STRING;
function raw_format_nat_hex(value : NATURAL) return STRING;
-- str_format_* functions
function str_format(value : REAL; precision : NATURAL := 3) return STRING;
-- to_string
function to_string(value : BOOLEAN) return STRING;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING;
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING;
function to_string(rawstring : T_RAWSTRING) return STRING;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR;
-- to_digit*
function to_digit_bin(chr : character) return integer;
function to_digit_oct(chr : character) return integer;
function to_digit_dec(chr : character) return integer;
function to_digit_hex(chr : character) return integer;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : STRING) return INTEGER;
function to_natural_oct(str : STRING) return INTEGER;
function to_natural_dec(str : STRING) return INTEGER;
function to_natural_hex(str : STRING) return INTEGER;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : STRING) return NATURAL;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER;
function str_find(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_find(str : STRING; pattern : STRING) return BOOLEAN;
function str_ifind(str : STRING; chr : CHARACTER) return BOOLEAN;
function str_ifind(str : STRING; pattern : STRING) return BOOLEAN;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING;
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING;
function str_trim(str : STRING) return STRING;
function str_toLower(str : STRING) return STRING;
function str_toUpper(str : STRING) return STRING;
end package;
package body strings is
--
function to_IPStyle(str : STRING) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(I))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
end function;
-- to_char
-- ===========================================================================
function to_char(value : STD_LOGIC) return CHARACTER is
begin
case value IS
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- TODO: rename to to_HexDigit(..) ?
function to_char(value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(value < 16, HEX(value+1), 'X');
end function;
function to_char(rawchar : T_RAWCHAR) return CHARACTER is
begin
return CHARACTER'val(to_integer(unsigned(rawchar)));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(value : BOOLEAN) return STRING is
begin
return ite(value, "1", "0");
end function;
function raw_format_bool_chr(value : BOOLEAN) return STRING is
begin
return ite(value, "T", "F");
end function;
function raw_format_bool_str(value : BOOLEAN) return STRING is
begin
return str_toUpper(boolean'image(value));
end function;
function raw_format_slv_bin(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to slv'length);
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
J := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(2 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
variable j : NATURAL;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(slv'length - 1 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 3));
subtype TT_BCD is INTEGER range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : NATURAL;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_char(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : STD_LOGIC_VECTOR) return STRING is
variable Value : STD_LOGIC_VECTOR(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : STD_LOGIC_VECTOR(3 downto 0);
variable Result : STRING(1 to div_ceil(slv'length, 4));
variable j : NATURAL;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_char(to_integer(unsigned(Digit)));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(value : NATURAL) return STRING is
begin
return raw_format_slv_bin(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_oct(value : NATURAL) return STRING is
begin
return raw_format_slv_oct(to_slv(value, log2ceilnz(value+1)));
end function;
function raw_format_nat_dec(value : NATURAL) return STRING is
begin
return INTEGER'image(value);
end function;
function raw_format_nat_hex(value : NATURAL) return STRING is
begin
return raw_format_slv_hex(to_slv(value, log2ceilnz(value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(value : REAL; precision : NATURAL := 3) return STRING is
constant s : REAL := sign(value);
constant val : REAL := value * s;
constant int : INTEGER := integer(floor(val));
constant frac : INTEGER := integer(round((val - real(int)) * 10.0**precision));
constant frac_str : STRING := INTEGER'image(frac);
constant res : STRING := INTEGER'image(int) & "." & (1 to (precision - frac_str'length) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(value : boolean) return string is
begin
return raw_format_bool_str(value);
end function;
function to_string(value : INTEGER; base : POSITIVE := 10) return STRING is
constant absValue : NATURAL := abs(value);
constant len : POSITIVE := log10ceilnz(absValue);
variable power : POSITIVE;
variable Result : STRING(1 TO len);
begin
power := 1;
if (base = 10) then
return INTEGER'image(value);
else
for i in len downto 1 loop
Result(i) := to_char(absValue / power MOD base);
power := power * base;
end loop;
if (value < 0) then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- TODO: rename to slv_format(..) ?
function to_string(slv : STD_LOGIC_VECTOR; format : CHARACTER; length : NATURAL := 0; fill : CHARACTER := '0') return STRING is
constant int : INTEGER := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : STRING := INTEGER'image(int);
constant bin_len : POSITIVE := slv'length;
constant dec_len : POSITIVE := str'length;--log10ceilnz(int);
constant hex_len : POSITIVE := ite(((bin_len MOD 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : NATURAL := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : NATURAL;
variable Result : STRING(1 to ite((length = 0), len, imax(len, length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_char(to_integer(unsigned(slv((j * 4) + 3 downto (j * 4)))));
j := j + 1;
end loop;
else
report "unknown format" severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return STRING is
variable str : STRING(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
str(I - rawstring'low + 1) := to_char(rawstring(I));
end loop;
return str;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return result;
end function;
-- to_*
-- ===========================================================================
function to_digit_bin(chr : character) return integer is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
function to_digit_oct(chr : character) return integer is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
function to_digit_dec(chr : character) return integer is
begin
if chr_isDigit(chr) then
return character'pos(chr) - character'pos('0');
else
return -1;
end if;
end function;
function to_digit_hex(chr : character) return integer is
begin
if chr_isDigit(chr) then return character'pos(chr) - character'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - character'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - character'pos('A') + 10;
else return -1;
end if;
end function;
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity failure;
-- return statement is explicitly missing otherwise XST won't stop
end case;
end function;
function to_natural_bin(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_bin(str(I));
if (Digit /= -1) then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_oct(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_oct(str(I));
if (Digit /= -1) then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural_dec(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_dec(str(I));
if (Digit /= -1) then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result;
-- return INTEGER'value(str); -- 'value(...) is not supported by Vivado Synth 2014.1
end function;
function to_natural_hex(str : STRING) return INTEGER is
variable Result : NATURAL;
variable Digit : INTEGER;
begin
for i in str'range loop
Digit := to_digit_hex(str(I));
if (Digit /= -1) then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
function to_natural(str : STRING; base : CHARACTER := 'd') return INTEGER is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "unknown base" severity ERROR;
end case;
end function;
-- to_raw*
-- ===========================================================================
function to_RawChar(char : character) return t_rawchar is
begin
return std_logic_vector(to_unsigned(character'pos(char), t_rawchar'length));
end function;
function to_RawString(str : STRING) return T_RAWSTRING is
variable rawstr : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
rawstr(i - str'low) := to_RawChar(str(i));
end loop;
return rawstr;
end function;
-- resize
-- ===========================================================================
function resize(str : STRING; size : POSITIVE; FillChar : CHARACTER := C_POC_NUL) return STRING is
constant ConstNUL : STRING(1 to 1) := (others => C_POC_NUL);
variable Result : STRING(1 to size);
begin
Result := (others => FillChar);
if (str'length > 0) then
Result(1 to imin(size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
function str_length(str : STRING) return NATURAL is
begin
for i in str'range loop
if (str(i) = C_POC_NUL) then
return i - str'low;
end if;
end loop;
return str'length;
end function;
function str_equal(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
function str_match(str1 : STRING; str2 : STRING) return BOOLEAN is
constant len : NATURAL := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
function str_imatch(str1 : STRING; str2 : STRING) return BOOLEAN is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
function str_pos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if (str(i) = chr) then
return i;
end if;
end loop;
return -1;
end function;
function str_pos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
function str_ipos(str : STRING; chr : CHARACTER; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
function str_ipos(str : STRING; pattern : STRING; start : NATURAL := 0) return INTEGER is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
function str_find(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
function str_find(str : STRING; pattern : STRING) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
function str_ifind(str : STRING; chr : CHARACTER) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
function str_ifind(str : STRING; pattern : STRING) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
function str_replace(str : STRING; pattern : STRING; replace : STRING) return STRING is
variable pos : INTEGER;
begin
pos := str_pos(str, pattern);
if (pos > 0) then
if (pos = 1) then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- examples:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : STRING; start : INTEGER := 0; length : INTEGER := 0) return STRING is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if (start < 0) then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif (start = 0) then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if (length < 0) then -- length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + length;
elsif (length = 0) then -- length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- length is positive -> end substring at StartOfString + length
EndOfString := StartOfString + length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity error; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity error; end if;
return str(StartOfString to EndOfString);
end function;
function str_ltrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'range loop
if (str(i) /= char) then
return str(i to str'high);
end if;
end loop;
return "";
end function;
function str_rtrim(str : STRING; char : CHARACTER := ' ') return STRING is
begin
for i in str'reverse_range loop
if (str(i) /= char) then
return str(str'low to i);
end if;
end loop;
return "";
end function;
function str_trim(str : STRING) return STRING is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
function str_toLower(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toLower(str(I));
end loop;
return temp;
end function;
function str_toUpper(str : STRING) return STRING is
variable temp : STRING(str'range);
begin
for i in str'range loop
temp(I) := chr_toUpper(str(I));
end loop;
return temp;
end function;
end package body;
| gpl-2.0 | 8ce852e4f84fc389f84a130e8158efc4 | 0.63163 | 3.223949 | false | false | false | false |
tgingold/ghdl | testsuite/synth/if01/if02.vhdl | 1 | 434 | library ieee;
use ieee.std_logic_1164.all;
entity if02 is
port (c : std_logic_vector(7 downto 0);
s : std_logic;
r : out std_logic_vector(7 downto 0));
end if02;
architecture behav of if02 is
begin
process (c, s)
begin
if s = '0' then
r (6 downto 0) <= c (7 downto 1);
r (7) <= c (0);
else
r (0) <= c (7);
r (7 downto 1) <= c (6 downto 0);
end if;
end process;
end behav;
| gpl-2.0 | 8ae8c8bf084dc404150ab4825b32913a | 0.546083 | 2.855263 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd | 4 | 2,266 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity cache is
generic ( cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10) );
port ( halt : in bit );
end entity cache;
architecture instrumented of cache is
begin
-- code from book
cache_monitor : process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file
open append_mode is "cache-measurements";
-- . . .
-- not in book
constant miss_count : natural := 100;
constant total_accesses : natural := 1000;
constant total_delay : delay_length := 2400 ns;
-- end not in book
begin
-- . . .
loop
-- . . .
-- not in book
wait on halt;
-- end not in book
exit when halt = '1';
-- . . .
end loop;
write ( measurements,
measurement_record'(
-- write values of generics for this run
cache_size, block_size, associativity, benchmark_name,
-- calculate performance metrics
miss_rate => real(miss_count) / real(total_accesses),
ave_access_time => total_delay / total_accesses ) );
wait;
end process cache_monitor;
-- end code from book
end architecture instrumented;
| gpl-2.0 | 41e5abc7359d24a3b24bd9f3babf2d3a | 0.64872 | 4.283554 | false | false | false | false |
hubertokf/VHDL-Fast-Adders | CLAH/CLA2bits/32bits/CLAH32bits/CLAH32bits.vhd | 1 | 6,893 | LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH32bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END CLAH32bits;
ARCHITECTURE strc_CLAH32bits of CLAH32bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig, P4_sig, P5_sig, P6_sig, P7_sig, P8_sig, P9_sig, P10_sig, P11_sig, P12_sig, P13_sig, P14_sig, P15_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig, G4_sig, G5_sig, G6_sig, G7_sig, G8_sig, G9_sig, G10_sig, G11_sig, G12_sig, G13_sig, G14_sig, G15_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig, Cout4_temp_sig, Cout5_temp_sig, Cout6_temp_sig, Cout7_temp_sig: STD_LOGIC;
SIGNAL Cout8_temp_sig, Cout9_temp_sig, Cout10_temp_sig, Cout11_temp_sig, Cout12_temp_sig, Cout13_temp_sig, Cout14_temp_sig, Cout15_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4,SomaT5,SomaT6,SomaT7,SomaT8,SomaT9,SomaT10,SomaT11,SomaT12,SomaT13,SomaT14,SomaT15,SomaT16:STD_LOGIC_VECTOR(1 DOWNTO 0);
Component CLA2bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg32Bit
PORT (
valIn: in std_logic_vector(31 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(31 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg32Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg32Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg32Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0),
val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2),
val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4),
val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout4_temp_sig
);
Som4: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6),
val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
--novoooooooo--
Som5: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(9 DOWNTO 8),
val2(1 DOWNTO 0) => B_sig(9 DOWNTO 8),
CarryIn=>Cout4_temp_sig,
P=>P4_sig,
G=>G4_sig,
SomaResult=>SomaT5
);
CLGB3: CLGB PORT MAP(
P0=>P4_sig,
G0=>G4_sig,
P1=>P5_sig,
G1=>G5_sig,
Cin=>Cout4_temp_sig,
Cout1=>Cout5_temp_sig,
Cout2=>Cout6_temp_sig
);
Som6: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(11 DOWNTO 10),
val2(1 DOWNTO 0) => B_sig(11 DOWNTO 10),
CarryIn=>Cout5_temp_sig,
P=>P5_sig,
G=>G5_sig,
SomaResult=>SomaT6
);
Som7: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(13 DOWNTO 12),
val2(1 DOWNTO 0) => B_sig(13 DOWNTO 12),
CarryIn=>Cout6_temp_sig,
P=>P6_sig,
G=>G6_sig,
SomaResult=>SomaT7
);
CLGB4: CLGB PORT MAP(
P0=>P6_sig,
G0=>G6_sig,
P1=>P7_sig,
G1=>G7_sig,
Cin=>Cout6_temp_sig,
Cout1=>Cout7_temp_sig,
Cout2=>Cout8_temp_sig
);
Som8: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(15 DOWNTO 14),
val2(1 DOWNTO 0) => B_sig(15 DOWNTO 14),
CarryIn=>Cout7_temp_sig,
P=>P7_sig,
G=>G7_sig,
SomaResult=>SomaT8
);
--novoooooooo--
Som9: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(17 DOWNTO 16),
val2(1 DOWNTO 0) => B_sig(17 DOWNTO 16),
CarryIn=>Cout8_temp_sig,
P=>P8_sig,
G=>G8_sig,
SomaResult=>SomaT9
);
CLGB5: CLGB PORT MAP(
P0=>P8_sig,
G0=>G8_sig,
P1=>P9_sig,
G1=>G9_sig,
Cin=>Cout8_temp_sig,
Cout1=>Cout9_temp_sig,
Cout2=>Cout10_temp_sig
);
Som10: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(19 DOWNTO 18),
val2(1 DOWNTO 0) => B_sig(19 DOWNTO 18),
CarryIn=>Cout9_temp_sig,
P=>P9_sig,
G=>G9_sig,
SomaResult=>SomaT10
);
Som11: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(21 DOWNTO 20),
val2(1 DOWNTO 0) => B_sig(21 DOWNTO 20),
CarryIn=>Cout10_temp_sig,
P=>P10_sig,
G=>G10_sig,
SomaResult=>SomaT11
);
CLGB6: CLGB PORT MAP(
P0=>P10_sig,
G0=>G10_sig,
P1=>P11_sig,
G1=>G11_sig,
Cin=>Cout10_temp_sig,
Cout1=>Cout11_temp_sig,
Cout2=>Cout12_temp_sig
);
Som12: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(23 DOWNTO 22),
val2(1 DOWNTO 0) => B_sig(23 DOWNTO 22),
CarryIn=>Cout11_temp_sig,
P=>P11_sig,
G=>G11_sig,
SomaResult=>SomaT12
);
--novoooooooo--
Som13: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(25 DOWNTO 24),
val2(1 DOWNTO 0) => B_sig(25 DOWNTO 24),
CarryIn=>Cout12_temp_sig,
P=>P12_sig,
G=>G12_sig,
SomaResult=>SomaT13
);
CLGB7: CLGB PORT MAP(
P0=>P12_sig,
G0=>G12_sig,
P1=>P13_sig,
G1=>G13_sig,
Cin=>Cout12_temp_sig,
Cout1=>Cout13_temp_sig,
Cout2=>Cout14_temp_sig
);
Som14: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(27 DOWNTO 26),
val2(1 DOWNTO 0) => B_sig(27 DOWNTO 26),
CarryIn=>Cout13_temp_sig,
P=>P13_sig,
G=>G13_sig,
SomaResult=>SomaT14
);
Som15: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(29 DOWNTO 28),
val2(1 DOWNTO 0) => B_sig(29 DOWNTO 28),
CarryIn=>Cout14_temp_sig,
P=>P14_sig,
G=>G14_sig,
SomaResult=>SomaT15
);
CLGB8: CLGB PORT MAP(
P0=>P14_sig,
G0=>G14_sig,
P1=>P15_sig,
G1=>G15_sig,
Cin=>Cout14_temp_sig,
Cout1=>Cout15_temp_sig,
Cout2=>Cout_sig
);
Som16: CLA2bits PORT MAP(
val1(1 DOWNTO 0) => A_sig(31 DOWNTO 30),
val2(1 DOWNTO 0) => B_sig(31 DOWNTO 30),
CarryIn=>Cout15_temp_sig,
P=>P15_sig,
G=>G15_sig,
SomaResult=>SomaT16
);
Out_sig <= SomaT16 & SomaT15 & SomaT14 & SomaT13 & SomaT12 & SomaT11 & SomaT10 & SomaT9 & SomaT8 & SomaT7 & SomaT6 & SomaT5 & SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH32bits; | mit | 0ccf7aac16a7e0e8da3ce7c70222af3c | 0.634847 | 2.237261 | false | false | false | false |
nickg/nvc | test/regress/proc9.vhd | 1 | 425 | entity proc9 is
end entity;
architecture test of proc9 is
procedure foo (x : in integer; y : out bit_vector) is
constant c : bit_vector(1 to x) := (others => '1');
begin
wait for 1 ns;
y := c;
end procedure;
begin
process is
variable b : bit_vector(1 to 5);
begin
foo(5, b);
assert b = (1 to 5 => '1');
wait;
end process;
end architecture;
| gpl-3.0 | b97b71829922a580820848ebd455f6b9 | 0.538824 | 3.512397 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_ml.vhd | 2 | 1,405 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_ml;
architecture augh of p_jinfo_ac_dhuff_tbl_ml is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | e6537b5f64f851b4209ac48174f09c47 | 0.671174 | 2.832661 | false | false | false | false |
nickg/nvc | test/simp/issue320.vhd | 1 | 768 | package TEST_PACKAGE is
type CHANNEL_TYPE is (
CHANNEL_0,
CHANNEL_1,
CHANNEL_2
);
end TEST_PACKAGE;
use WORK.TEST_PACKAGE.all;
entity ISSUE320 is
end ISSUE320;
architecture MODEL of ISSUE320 is
function GEN_INIT_VALUE(CHANNEL: CHANNEL_TYPE) return integer is
variable value : integer;
begin
case CHANNEL is
when CHANNEL_1 => value := 1;
when CHANNEL_2 => value := 2;
when others => value := 0;
end case;
return value;
end function;
-- Strange error about not being able to find a libary as '.' in
-- mangled function name wrongly interpreted
constant INIT_VALUE : integer := GEN_INIT_VALUE(CHANNEL_0);
begin
end MODEL;
| gpl-3.0 | f905b77b840c2bdd58d26264e52d7367 | 0.604167 | 4.042105 | false | true | false | false |
tgingold/ghdl | testsuite/gna/bug040/sub_219.vhd | 2 | 1,725 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_219 is
port (
le : out std_logic;
output : out std_logic_vector(40 downto 0);
sign : in std_logic;
in_b : in std_logic_vector(40 downto 0);
in_a : in std_logic_vector(40 downto 0)
);
end sub_219;
architecture augh of sub_219 is
signal carry_inA : std_logic_vector(42 downto 0);
signal carry_inB : std_logic_vector(42 downto 0);
signal carry_res : std_logic_vector(42 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(41 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(40) & in_b(40) & carry_res(41);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
le <= tmp_le;
end architecture;
| gpl-2.0 | de06fb0529347534edbf839cf81359b0 | 0.624348 | 2.578475 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/sip_spi/fmc408_stellar_cmd.vhd | 1 | 11,370 | --------------------------------------------------------------------------------
-- file name : fmc408_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity -fmc408_stellar_cmd
-- arch_itecture - arch_fmc408_stellar_cmd
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- specify libraries.
--------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_1164.all ;
--------------------------------------------------------------------------------
-- entity declaration
--------------------------------------------------------------------------------
entity fmc408_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port
(
reset :in std_logic;
--command if
clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
--register interface
clk_reg :in std_logic; --register interface is synchronous to this clock
out_reg :out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val :out std_logic; --the out_reg has valid data (pulse)
out_reg_addr :out std_logic_vector(27 downto 0);--out register address
in_reg :in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val :in std_logic; --pulse to indicate requested register is valid
in_reg_req :out std_logic; --pulse to request data
in_reg_addr :out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_out_reg :out std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_out_val :out std_logic;
mbx_in_reg :in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val :in std_logic --pulse to indicate mailbox is valid
);
end entity fmc408_stellar_cmd ;
--------------------------------------------------------------------------------
-- arch_itecture declaration
--------------------------------------------------------------------------------
architecture arch_fmc408_stellar_cmd of fmc408_stellar_cmd is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0";
constant cmd_rd :std_logic_vector(3 downto 0) :=x"2";
constant cmd_wr :std_logic_vector(3 downto 0) :=x"1";
constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4";
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal register_wr :std_logic;
signal register_rd :std_logic;
signal out_cmd_val_sig :std_logic;
signal in_reg_addr_sig :std_logic_vector(27 downto 0):=(others=>'0');
signal mbx_in_val_sig :std_logic;
signal mbx_received :std_logic;
signal mbx_out_val_sig :std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk :in std_logic;
out_clk :in std_logic;
rst :in std_logic;
pulsein :in std_logic;
inbusy :out std_logic;
pulseout :out std_logic
);
end component;
begin
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_wr,
inbusy =>open,
pulseout =>out_reg_val
);
p2p1: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg,
rst =>reset,
pulsein =>register_rd,
inbusy =>open,
pulseout =>in_reg_req
);
p2p2: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>in_reg_val,
inbusy =>open,
pulseout =>out_cmd_val_sig
);
p2p3: pulse2pulse
port map
(
in_clk =>clk_reg,
out_clk =>clk_cmd ,
rst =>reset,
pulsein =>mbx_in_val,
inbusy =>open,
pulseout =>mbx_in_val_sig
);
p2p4: pulse2pulse
port map
(
in_clk =>clk_cmd,
out_clk =>clk_reg ,
rst =>reset,
pulsein =>mbx_out_val_sig,
inbusy =>open,
pulseout =>mbx_out_val
);
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig='1' and mbx_in_val_sig='1') then
mbx_received <= '1';
elsif( mbx_received ='1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig='1') then
out_cmd(31 downto 0) <=in_reg;
out_cmd(59 downto 32)<=in_reg_addr_sig+start_addr;
out_cmd(63 downto 60)<=cmd_rd_ack;
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd(31 downto 0) <=mbx_in_reg;
out_cmd(59 downto 32)<=start_addr;
out_cmd(63 downto 60)<=cmd_mbx;
else
out_cmd(63 downto 0)<=(others=>'0');
end if;
if (out_cmd_val_sig='1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig='1' or mbx_received='1' ) then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(clk_cmd )
begin
if(clk_cmd'event and clk_cmd='1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
out_reg_addr <= in_cmd(59 downto 32)-start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx) then
mbx_out_reg <= in_cmd(31 downto 0);
end if;
if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx ) then
mbx_out_val_sig <= '1';
else
mbx_out_val_sig <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
end architecture arch_fmc408_stellar_cmd ; -- of fmc408_stellar_cmd
| mit | 506021b6eaa6e769ab50f7155d8c49d6 | 0.447669 | 4.226766 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/input_split0.vhd | 2 | 1,822 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split0 is
port (
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic;
wa2_data : in std_logic_vector(31 downto 0);
wa2_addr : in std_logic_vector(4 downto 0);
wa2_en : in std_logic
);
end input_split0;
architecture augh of input_split0 is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa2_en = '1' then
ram( to_integer(wa2_addr) ) <= wa2_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra3_data <= ram( to_integer(ra3_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
ra2_data <= ram( to_integer(ra2_addr) );
end architecture;
| gpl-2.0 | deea35af4a7dbbbb65f9ce77f53c41c5 | 0.670143 | 2.781679 | false | false | false | false |
nickg/nvc | test/regress/operator6.vhd | 1 | 1,584 | entity operator6 is
end entity;
architecture test of operator6 is
function "=" (L: bit; R: bit) return bit is
begin
report "custom bit =" severity failure;
return L xnor R;
end function "=";
function "/=" (L: bit; R: bit) return bit is
begin
report "custom bit /=" severity failure;
return L xor R;
end function "/=";
function "=" (L: bit_vector; R: bit_vector) return bit is
begin
report "custom bit_vector =" severity failure;
if L = R then
return '1';
else
return '0';
end if;
end function "=";
function "/=" (L: bit_vector; R: bit_vector) return bit is
begin
report "custom bit_vector /=" severity failure;
if L /= R then
return '1';
else
return '0';
end if;
end function "/=";
constant ID_FLAG_C_SHF : bit_vector(1 to 3) := "100";
constant ID_RMW_SHF : bit := '1';
-- ** Note: 3972750ns+1: Report Note: bad else: s1_id_flag_c = 4 s1_id_rmw = '0'
signal s1_id_flag_c : bit_vector(1 to 3) := ID_FLAG_C_SHF;
signal s1_id_rmw : bit := '0';
begin
p1: process is
begin
-- report "bad else: s1_id_flag_c = " & integer'image(to_integer(unsigned(s1_id_flag_c))) & " s1_id_rmw = " & bit'image(to_bit(s1_id_rmw));
if s1_id_flag_c = ID_FLAG_C_SHF then
report "s1_id_flag_c = ID_FLAG_C_SHF";
end if;
if s1_id_rmw /= ID_RMW_SHF then
report "s1_id_rmw /= ID_RMW_SHF";
end if;
assert s1_id_flag_c = ID_FLAG_C_SHF and s1_id_rmw /= ID_RMW_SHF;
wait;
end process;
end architecture;
| gpl-3.0 | 1e9ff0b812eaf2e219456c9350230e57 | 0.573232 | 3.069767 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd | 4 | 6,488 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1360.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01360ent IS
END c08s05b00x00p03n01i01360ent;
ARCHITECTURE c08s05b00x00p03n01i01360arch OF c08s05b00x00p03n01i01360ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 :=c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01360"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01360 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01360arch;
| gpl-2.0 | 26c036f28f8d4b1c25a083be6304e654 | 0.582922 | 2.966621 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd | 4 | 2,224 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
| gpl-2.0 | eba2c1228d033225bcc82732d50b4939 | 0.629496 | 3.329341 | false | false | false | false |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd | 6 | 171,976 | `protect begin_protected
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`protect end_protected
| mit | b2d341f4e7cf92a2736849cd9ac35b31 | 0.955058 | 1.8323 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func02/func01.vhdl | 1 | 528 | library ieee;
use ieee.std_logic_1164.all;
entity func01 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end func01;
architecture behav of func01 is
function gen_and (v : std_logic_vector (7 downto 0);
len : natural := 6) return std_logic_vector is
variable res : std_logic_vector (7 downto 0);
begin
res := (others => '0');
res (len - 1 downto 0) := (others => '1');
return res and v;
end gen_and;
begin
b <= gen_and (a);
end behav;
| gpl-2.0 | bf005fdc13ce0e4d5fbaa32892cf23a8 | 0.602273 | 3.2 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/ip/xbip_dsp48_wrapper_v3_0_4/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 9 | 142,613 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103440)
`protect data_block
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`protect end_protected
| gpl-3.0 | 1365df4c2f733d35afae0c86a90a611f | 0.952957 | 1.834369 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue1051/psi_common_i2c_master.vhd | 1 | 21,002 | ------------------------------------------------------------------------------
-- Copyright (c) 2019 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
-- Authors: Oliver Bruendler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Description
------------------------------------------------------------------------------
-- This entity implements a simple I2C-master (multi master capable)
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
------------------------------------------------------------------------------
-- Package for Interface Simplification
------------------------------------------------------------------------------
package psi_common_i2c_master_pkg is
constant CMD_START : std_logic_vector(2 downto 0) := "000";
constant CMD_STOP : std_logic_vector(2 downto 0) := "001";
constant CMD_REPSTART : std_logic_vector(2 downto 0) := "010";
constant CMD_SEND : std_logic_vector(2 downto 0) := "011";
constant CMD_REC : std_logic_vector(2 downto 0) := "100";
end package;
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_i2c_master_pkg.all;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
-- $$ processes=stim,i2c $$
-- $$ tbpkg=work.psi_tb_compare_pkg,work.psi_tb_activity_pkg,work.psi_tb_txt_util,work.psi_tb_i2c_pkg $$
entity psi_common_i2c_master is
generic (
ClockFrequency_g : real := 125.0e6; -- in Hz $$ constant=125.0e6 $$
I2cFrequency_g : real := 100.0e3; -- in Hz $$ constant=1.0e6 $$
BusBusyTimeout_g : real := 1.0e-3; -- in sec $$ constant=100.0e-6 $$
CmdTimeout_g : real := 100.0e-6; -- in sec $$ constant=10.0e-6 $$
InternalTriState_g : boolean := true; -- $$ constant=true $$
DisableAsserts_g : boolean := false
);
port (
-- Control Signals
Clk : in std_logic; -- $$ type=clk; freq=125e6 $$
Rst : in std_logic; -- $$ type=rst; clk=Clk $$
-- Command Interface
CmdRdy : out std_logic;
CmdVld : in std_logic;
CmdType : in std_logic_vector(2 downto 0);
CmdData : in std_logic_vector(7 downto 0);
CmdAck : in std_logic;
-- Response Interface
RspVld : out std_logic;
RspType : out std_logic_vector(2 downto 0);
RspData : out std_logic_vector(7 downto 0);
RspAck : out std_logic;
RspArbLost : out std_logic;
RspSeq : out std_logic;
-- Status Interface
BusBusy : out std_logic;
TimeoutCmd : out std_logic;
-- I2c Interface with internal Tri-State (InternalTriState_g = true)
I2cScl : inout std_logic := 'Z';
I2cSda : inout std_logic := 'Z';
-- I2c Interface with external Tri-State (InternalTriState_g = false)
I2cScl_I : in std_logic := '0';
I2cScl_O : out std_logic;
I2cScl_T : out std_logic;
I2cSda_I : in std_logic := '0';
I2cSda_O : out std_logic;
I2cSda_T : out std_logic
);
end entity;
------------------------------------------------------------------------------
-- Architecture Declaration
------------------------------------------------------------------------------
architecture rtl of psi_common_i2c_master is
-- *** Constants ***
constant BusyTimoutLimit_c : integer := integer(ClockFrequency_g*BusBusyTimeout_g)-1;
constant QuarterPeriodLimit_c : integer := integer(ceil(ClockFrequency_g/I2cFrequency_g/4.0))-1;
constant CmdTimeoutLimit_c : integer := integer(ClockFrequency_g*CmdTimeout_g)-1;
-- *** Types ***
type Fsm_t is ( BusIdle_s, BusBusy_s, MinIdle_s, Start1_s, Start2_s, WaitCmd_s, WaitLowCenter_s, Stop1_s, Stop2_s, Stop3_s, RepStart1_s,
DataBit1_s, DataBit2_s, DataBit3_s, DataBit4_s, ArbitLost_s);
-- *** Two Process Method ***
type two_process_r is record
BusBusy : std_logic;
CmdRdy : std_logic;
SclLast : std_logic;
SdaLast : std_logic;
BusBusyToCnt : unsigned(log2ceil(BusyTimoutLimit_c+1)-1 downto 0);
TimeoutCmdCnt : unsigned(log2ceil(CmdTimeoutLimit_c+1)-1 downto 0);
QuartPeriodCnt : unsigned(log2ceil(QuarterPeriodLimit_c+1)-1 downto 0);
QPeriodTick : std_logic;
CmdTypeLatch : std_logic_vector(CmdType'range);
CmdAckLatch : std_logic;
Fsm : Fsm_t;
SclOut : std_logic;
SdaOut : std_logic;
RspVld : std_logic;
RspAck : std_logic;
RspSeq : std_logic;
RspData : std_logic_vector(7 downto 0);
RspArbLost : std_logic;
BitCnt : unsigned(3 downto 0); -- 8 Data + 1 Ack = 9 = 4 bits
ShReg : std_logic_vector(8 downto 0);
CmdTimeout : std_logic;
TimeoutCmd : std_logic;
end record;
signal r, r_next : two_process_r;
attribute dont_touch : string;
attribute dont_touch of r : signal is "true"; -- Required to Fix Vivado 2018.2 Synthesis Bug! Is fixed in Vivado 2019.1 according to Xilinx.
-- Tri-state buffer muxing
signal I2cScl_Input : std_logic;
signal I2cSda_Input : std_logic;
signal I2cScl_Sync : std_logic;
signal I2cSda_Sync : std_logic;
begin
--------------------------------------------------------------------------
-- Combinatorial Proccess
--------------------------------------------------------------------------
p_comb : process( Clk, r, I2cScl_Sync, I2cSda_Sync,
CmdVld, CmdType, CmdData, CmdAck)
variable v : two_process_r;
variable SclRe_v, SclFe_v, SdaRe_v, SdaFe_v : std_logic;
variable I2cStart_v, I2cStop_v : std_logic;
begin
-- *** hold variables stable ***
v := r;
-- *** Edge Detection ***
SclRe_v := not r.SclLast and I2cScl_Sync;
SclFe_v := r.SclLast and not I2cScl_Sync;
SdaRe_v := not r.SdaLast and I2cSda_Sync;
SdaFe_v := r.SdaLast and not I2cSda_Sync;
v.SclLast := I2cScl_Sync;
v.SdaLast := I2cSda_Sync;
-- *** Start/Stop Detection ***
I2cStart_v := r.SclLast and I2cScl_Sync and SdaFe_v;
I2cStop_v := r.SclLast and I2cScl_Sync and SdaRe_v;
-- *** Quarter Period Counter ***
-- The FSM may overwrite the counter in some cases!
v.QPeriodTick := '0';
if (r.Fsm = BusIdle_s) or (r.Fsm = BusBusy_s) then
v.QuartPeriodCnt := (others => '0');
elsif r.QuartPeriodCnt = QuarterPeriodLimit_c then
v.QuartPeriodCnt := (others => '0');
v.QPeriodTick := '1';
else
v.QuartPeriodCnt := r.QuartPeriodCnt + 1;
end if;
-- *** Command Timeout Detection ***
if r.Fsm = WaitCmd_s then
-- Timeout
if r.TimeoutCmdCnt = CmdTimeoutLimit_c then
v.CmdTimeout := '1';
-- Count
else
v.TimeoutCmdCnt := r.TimeoutCmdCnt + 1;
end if;
-- In all states except waiting for command, reset the timer
else
v.TimeoutCmdCnt := (others => '0');
end if;
-- *** Latch Command ***
if (r.CmdRdy = '1') and (CmdVld = '1') then
v.CmdTypeLatch := CmdType;
v.CmdAckLatch := CmdAck;
end if;
-- *** Default Values ***
v.RspVld := '0';
v.RspAck := not r.ShReg(0);
v.RspData := r.ShReg(8 downto 1);
v.RspSeq := '0';
v.RspArbLost := '0';
v.TimeoutCmd := '0';
v.CmdRdy := '0';
-- *** FSM ***
case r.Fsm is
-- **********************************************************************************************
-- Bus Idle
-- **********************************************************************************************
when BusIdle_s =>
-- Default Outputs
v.CmdRdy := '1';
v.BusBusyToCnt := (others => '0');
v.SclOut := '1';
v.SdaOut := '1';
v.CmdTimeout := '0';
-- Detect Bus Busy by Start Command
if (r.CmdRdy = '1') and (CmdVld = '1') then
-- Everyting else than START commands is ignored and an error is printed in this case
assert (CmdType = CMD_START) or DisableAsserts_g
report "###ERROR###: psi_common_i2c_master: In idle state, only CMD_START commands are allowed!"
severity error;
if CmdType = CMD_START then
v.Fsm := Start1_s;
v.CmdRdy := '0';
v.CmdTypeLatch := CmdType;
else
v.RspVld := '1';
v.RspSeq := '1';
end if;
-- Detect Busy from other master
elsif (I2cScl_Sync = '0') or (I2cStart_v = '1') then
v.Fsm := BusBusy_s;
v.CmdRdy := '0';
end if;
-- **********************************************************************************************
-- Bus Busy by other master
-- **********************************************************************************************
when BusBusy_s =>
-- Bus released
if I2cStop_v = '1' then
v.Fsm := MinIdle_s;
end if;
-- Timeout Handling
if I2cScl_Sync = '0' then
v.BusBusyToCnt := (others => '0');
elsif r.BusBusyToCnt = BusyTimoutLimit_c then
v.Fsm := BusIdle_s;
else
v.BusBusyToCnt := r.BusBusyToCnt + 1;
end if;
v.SclOut := '1';
v.SdaOut := '1';
-- Ensure that SDA stays low for at least half a clock period
when MinIdle_s =>
if r.QPeriodTick = '1' then
v.Fsm := BusIdle_s;
end if;
v.SclOut := '1';
v.SdaOut := '1';
-- **********************************************************************************************
-- Start Condition
-- **********************************************************************************************
-- State BusBusy_s Start1_s Start2_s WaitCmd_s
-- __________________________________
-- Scl ... |___________ ...
-- _______________________
-- SDA ... |______________________ ...
-- **********************************************************************************************
when Start1_s =>
if r.QPeriodTick = '1' then
v.Fsm := Start2_s;
end if;
-- Handle Clock Stretching in case of a repeated start (slave keeps SCL low)
if I2cScl_Sync = '0' and r.CmdTypeLatch = CMD_REPSTART then
v.QuartPeriodCnt := (others => '0');
end if;
-- Handle Arbitration (other master transmits start condition first)
if I2cSda_Sync = '0' then
v.Fsm := ArbitLost_s;
end if;
v.SclOut := '1';
v.SdaOut := '1';
when Start2_s =>
if r.QPeriodTick = '1' then
v.Fsm := WaitCmd_s;
v.RspVld := '1';
end if;
v.SclOut := '1';
v.SdaOut := '0';
-- **********************************************************************************************
-- Wait for user command (in first half of SCL low phase)
-- **********************************************************************************************
when WaitCmd_s =>
-- Default Outputs
v.CmdRdy := '1';
v.SclOut := '0';
-- All commands except START are allowed, START commands are ignored
if (r.CmdRdy = '1') and (CmdVld = '1') then
assert (CmdType = CMD_STOP) or (CmdType = CMD_REPSTART) or (CmdType = CMD_SEND) or (CmdType = CMD_REC) or DisableAsserts_g
report "###ERROR###: psi_common_i2c_master: In WaitCmd_s state, CMD_START commands are not allowed!"
severity error;
if (CmdType = CMD_STOP) or (CmdType = CMD_REPSTART) or (CmdType = CMD_SEND) or (CmdType = CMD_REC) then
v.Fsm := WaitLowCenter_s;
v.CmdRdy := '0';
else
v.RspVld := '1';
v.RspSeq := '1';
end if;
-- Latch data (used for SEND)
v.ShReg := CmdData & '0';
-- Command timeout - In this case send a STOP to free the bus
elsif r.CmdTimeout = '1' then
v.Fsm := WaitLowCenter_s;
v.CmdRdy := '0';
v.TimeoutCmd := '1';
end if;
-- **********************************************************************************************
-- Wait for center of SCL low phase (after user command arrived)
-- **********************************************************************************************
when WaitLowCenter_s =>
-- State Handling
v.SclOut := '0';
v.BitCnt := (others => '0');
-- Switch to commands
if r.QPeriodTick = '1' then
-- In timeout case, send a STOP to free the bus
if r.CmdTimeout = '1' then
v.Fsm := Stop1_s;
-- Else, go to requested command
else
case r.CmdTypeLatch is
when CMD_STOP => v.Fsm := Stop1_s;
when CMD_REPSTART => v.Fsm := RepStart1_s;
when CMD_SEND => v.Fsm := DataBit1_s;
when CMD_REC => v.Fsm := DataBit1_s;
when others => null;
end case;
end if;
end if;
-- **********************************************************************************************
-- Start Condition
-- **********************************************************************************************
-- State RepStart1_s Start1_s Start2_s WaitCmd_s
-- _____________________
-- Scl ..._________________| |___________ ...
-- __________________________
-- SDA ...XXX |_____________________ ...
-- **********************************************************************************************
-- States after RepStart1_s are shared with normal start condition
when RepStart1_s =>
if r.QPeriodTick = '1' then
-- The rest of the sequence is same as for START
v.Fsm := Start1_s;
-- Handle Arbitration other master prvents repeating start by transmitting 0
if I2cSda_Sync = '0' then
v.Fsm := ArbitLost_s;
end if;
end if;
v.SclOut := '0';
v.SdaOut := '1';
-- **********************************************************************************************
-- Start Condition
-- **********************************************************************************************
-- State DataBit1_s DataBit2_s DataBit3_s WaitCmd_s / DataBit4_s
-- _________________________
-- Scl ...___________| |___________ ...
--
-- SDA ...XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- **********************************************************************************************
-- The DataBit1_s is the second half of the SCL low period. So the
-- SDA Line is set at the beginning of DataBit1_s. After the SCL high period
-- of the last bit, the state is changed to WaitCmd_s. Otherwise the first half of the SCL low
-- period is executed (DataBit4_s) before the next bit starts (DataBit1_s)
when DataBit1_s =>
if r.QPeriodTick = '1' then
v.Fsm := DataBit2_s;
end if;
v.SclOut := '0';
-- Send Operation
if r.CmdTypeLatch = CMD_SEND then
-- For Ack, receive data
if r.BitCnt = 8 then
v.SdaOut := '1';
-- .. else send data
else
v.SdaOut := r.ShReg(8);
end if;
-- Receive Operatiom
else
-- Ack Handling
if r.BitCnt = 8 then
if r.CmdAckLatch = '1' then
v.SdaOut := '0';
else
v.SdaOut := '1';
end if;
-- .. else tri-state for receiving
else
v.SdaOut := '1';
end if;
end if;
when DataBit2_s =>
if r.QPeriodTick = '1' then
v.Fsm := DataBit3_s;
-- Shift register in the middle of the CLK pulse
v.ShReg := r.ShReg(7 downto 0) & I2cSda_Sync;
end if;
v.SclOut := '1';
-- Handle Clock Stretching (slave keeps SCL low)
if I2cScl_Sync = '0' then
v.QuartPeriodCnt := (others => '0');
end if;
-- Handle Arbitration for Sending (only databits, not ack)
if (r.CmdTypeLatch = CMD_SEND) and (r.BitCnt /= 8) then
if I2cSda_Sync /= r.SdaOut then
v.Fsm := ArbitLost_s;
end if;
-- Receiving does not need arbitration since slave addresses are unique
end if;
when DataBit3_s =>
if r.QPeriodTick = '1' then
-- Command Done after 9 bits (8 Data + 1 Ack)
if r.BitCnt = 8 then
v.Fsm := WaitCmd_s;
v.RspVld := '1';
-- Else goto next bit
else
v.Fsm := DataBit4_s;
end if;
end if;
v.SclOut := '1';
-- Handle Arbitration for Sending (only databits, not ack)
if (r.CmdTypeLatch = CMD_SEND) and (r.BitCnt /= 8) then
if I2cSda_Sync /= r.SdaOut then
v.Fsm := ArbitLost_s;
end if;
-- Receiving does not need arbitration since slave addresses are unique
end if;
when DataBit4_s =>
if r.QPeriodTick = '1' then
v.Fsm := DataBit1_s;
v.BitCnt:= r.BitCnt + 1;
end if;
v.SclOut := '0';
-- **********************************************************************************************
-- Stop Condition
-- **********************************************************************************************
-- State WaitCmd_s Stop1_s Stop2_s Stop3_s BusIdle_s
-- _____________________
-- Scl ..._____________________| |__________ ...
-- _____________________
-- SDA ...XXXXXXXXXXXX____________________| ...
-- **********************************************************************************************
when Stop1_s =>
if r.QPeriodTick = '1' then
v.Fsm := Stop2_s;
end if;
v.SclOut := '0';
v.SdaOut := '0';
when Stop2_s =>
if r.QPeriodTick = '1' then
v.Fsm := Stop3_s;
end if;
v.SclOut := '1';
v.SdaOut := '0';
-- Handle Clock Stretching (slave keeps SCL low)
if I2cScl_Sync = '0' then
v.QuartPeriodCnt := (others => '0');
end if;
when Stop3_s =>
if r.QPeriodTick = '1' then
-- Handle Arbitration
if I2cSda_Sync = '0' then
v.Fsm := ArbitLost_s;
-- Else the STOP was successful
else
v.Fsm := BusIdle_s;
v.RspVld := '1';
end if;
end if;
v.SclOut := '1';
v.SdaOut := '1';
-- **********************************************************************************************
-- Send Response in case the arbitration was lost
-- **********************************************************************************************
when ArbitLost_s =>
v.Fsm := BusBusy_s;
v.RspVld := '1';
v.RspAck := '0';
v.RspArbLost := '1';
v.SclOut := '1';
v.SdaOut := '1';
when others => null;
end case;
-- TODO: FSM Stuck detection timeout!
-- *** Bus Busy ***
if r.Fsm = BusIdle_s then
v.BusBusy := '0';
else
v.BusBusy := '1';
end if;
-- *** assign signal ***
r_next <= v;
end process;
--------------------------------------------------------------------------
-- Outputs
--------------------------------------------------------------------------
BusBusy <= r.BusBusy;
CmdRdy <= r.CmdRdy;
RspVld <= r.RspVld;
RspType <= r.CmdTypeLatch;
RspArbLost <= r.RspArbLost;
RspAck <= r.RspAck;
RspData <= r.RspData;
RspSeq <= r.RspSeq;
TimeoutCmd <= r.TimeoutCmd;
g_intTristate : if InternalTriState_g generate
I2cScl <= 'Z' when r.SclOut = '1' else '0';
I2cSda <= 'Z' when r.SdaOut = '1' else '0';
I2cScl_O <= '0';
I2cSda_O <= '0';
I2cScl_T <= '1';
I2cSda_T <= '1';
end generate;
g_extTristatte : if not InternalTriState_g generate
I2cScl_O <= r.SclOut;
I2cSda_O <= r.SdaOut;
I2cScl_T <= r.SclOut;
I2cSda_T <= r.SdaOut;
I2cScl <= 'Z';
I2cSda <= 'Z';
end generate;
--------------------------------------------------------------------------
-- Sequential Proccess
--------------------------------------------------------------------------
p_seq : process(Clk)
begin
if rising_edge(Clk) then
r <= r_next;
if Rst = '1' then
r.BusBusy <= '0';
r.CmdRdy <= '0';
r.SclLast <= '1';
r.SdaLast <= '1';
r.BusBusyToCnt <= (others => '0');
r.Fsm <= BusIdle_s;
r.SclOut <= '1';
r.SdaOut <= '1';
r.RspVld <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------
-- Component Instantiations
--------------------------------------------------------------------------
I2cScl_Input <= To01X(I2cScl) when InternalTriState_g else I2cScl_I;
I2cSda_Input <= To01X(I2cSda) when InternalTriState_g else I2cSda_I;
i_sync : entity work.psi_common_bit_cc
generic map (
NumBits_g => 2
)
port map (
BitsA(0) => I2cScl_Input,
BitsA(1) => I2cSda_Input,
ClkB => Clk,
BitsB(0) => I2cScl_Sync,
BitsB(1) => I2cSda_Sync
);
end;
| gpl-2.0 | dafe7247c1dc9153b4f5bdb7c451a0d8 | 0.461432 | 3.440131 | false | false | false | false |
tgingold/ghdl | libraries/openieee/math_real.vhdl | 2 | 5,356 | -- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.2 math_real package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package MATH_REAL is
-- The values were computed with at least 40 digits and rounded to
-- 20 digits after the dot. They were checked with the original ieee
-- specification (log2_of_e has an extra digit from the spec).
constant math_e : real := 2.71828_18284_59045_23536;
constant math_1_over_e : real := 0.36787_94411_71442_321596;
constant math_pi : real := 3.14159_26535_89793_23846;
constant math_2_pi : real := 6.28318_53071_79586_47693;
constant math_pi_over_2 : real := 1.57079_63267_94896_61923;
constant math_pi_over_3 : real := 1.04719_75511_96597_74615;
constant math_pi_over_4 : real := 0.78539_81633_97448_30962;
constant math_3_pi_over_2 : real := 4.71238_89803_84689_85769;
constant math_log_of_2 : real := 0.69314_71805_59945_30942;
constant math_log_of_10 : real := 2.30258_50929_94045_68402;
constant math_log2_of_e : real := 1.44269_50408_88963_40736;
constant math_log10_of_e : real := 0.43429_44819_03251_82765;
constant math_sqrt_2 : real := 1.41421_35623_73095_04880;
constant math_1_over_sqrt_2 : real := 0.70710_67811_86547_52440;
constant math_sqrt_pi : real := 1.77245_38509_05516_02730;
constant math_deg_to_rad : real := 0.01745_32925_19943_29577;
constant math_rad_to_deg : real := 57.29577_95130_82320_87680;
function SIGN (X : REAL) return REAL;
function CEIL (X : REAL) return REAL;
attribute foreign of ceil : function is "VHPIDIRECT ceil";
function FLOOR (X : REAL) return REAL;
attribute foreign of floor : function is "VHPIDIRECT floor";
function ROUND (X : REAL) return REAL;
attribute foreign of round : function is "VHPIDIRECT round";
function TRUNC (X : REAL) return REAL;
attribute foreign of trunc : function is "VHPIDIRECT trunc";
function "mod" (X, Y : REAL) return REAL;
-- Contrary to fmod, the sign of the result is the sign of Y.
function REALMAX (X, Y : REAL) return REAL;
attribute foreign of REALMAX : function is "VHPIDIRECT fmax";
function REALMIN (X, Y : REAL) return REAL;
attribute foreign of REALMIN : function is "VHPIDIRECT fmin";
procedure UNIFORM (SEED1, SEED2 : inout POSITIVE; X : out REAL);
-- Algorithm from: Pierre L'Ecuyer, CACM June 1988 Volume 31 Number 6
-- page 747 figure 3.
function SQRT (X : REAL) return REAL;
attribute foreign of SQRT : function is "VHPIDIRECT sqrt";
function CBRT (X : REAL) return REAL;
attribute foreign of CBRT : function is "VHPIDIRECT cbrt";
function "**" (X : INTEGER; Y : REAL) return REAL;
function "**" (X : REAL; Y : REAL) return REAL;
attribute foreign of "**" [ REAL, REAL return REAL ]: function is
"VHPIDIRECT pow";
function EXP (X : REAL) return REAL;
attribute foreign of EXP : function is "VHPIDIRECT exp";
function LOG (X : REAL) return REAL;
attribute foreign of LOG [ REAL return REAL ] : function is "VHPIDIRECT log";
function LOG2 (X : REAL) return REAL;
attribute foreign of LOG2 : function is "VHPIDIRECT log2";
function LOG10 (X : REAL) return REAL;
attribute foreign of LOG10 : function is "VHPIDIRECT log10";
function LOG (X : REAL; BASE : REAL) return REAL;
function SIN (X : REAL) return REAL;
attribute foreign of SIN : function is "VHPIDIRECT sin";
function COS (X : REAL) return REAL;
attribute foreign of COS : function is "VHPIDIRECT cos";
function TAN (X : REAL) return REAL;
attribute foreign of TAN : function is "VHPIDIRECT tan";
function ARCSIN (X : REAL) return REAL;
attribute foreign of ARCSIN : function is "VHPIDIRECT asin";
function ARCCOS (X : REAL) return REAL;
attribute foreign of ARCCOS : function is "VHPIDIRECT acos";
function ARCTAN (Y : REAL) return REAL;
attribute foreign of ARCTAN [ REAL return REAL ]: function is
"VHPIDIRECT atan";
function ARCTAN (Y, X : REAL) return REAL;
attribute foreign of ARCTAN [ REAL, REAL return REAL ]: function is
"VHPIDIRECT atan2";
function SINH (X : REAL) return REAL;
attribute foreign of SINH : function is "VHPIDIRECT sinh";
function COSH (X : REAL) return REAL;
attribute foreign of COSH : function is "VHPIDIRECT cosh";
function TANH (X : REAL) return REAL;
attribute foreign of TANH : function is "VHPIDIRECT tanh";
function ARCSINH (X : REAL) return REAL;
attribute foreign of ARCSINH : function is "VHPIDIRECT asinh";
function ARCCOSH (X : REAL) return REAL;
attribute foreign of ARCCOSH : function is "VHPIDIRECT acosh";
function ARCTANH (Y : REAL) return REAL;
attribute foreign of ARCTANH : function is "VHPIDIRECT atanh";
end MATH_REAL;
| gpl-2.0 | f911e70279a540b8c04af001c231874f | 0.699589 | 3.688705 | false | false | false | false |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_inst.vhd | 1 | 2,111 | component ghrd_10as066n2_f2sdram0_m is
port (
clk_clk : in std_logic := 'X'; -- clk
clk_reset_reset : in std_logic := 'X'; -- reset
master_address : out std_logic_vector(31 downto 0); -- address
master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
master_read : out std_logic; -- read
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(31 downto 0); -- writedata
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_readdatavalid : in std_logic := 'X'; -- readdatavalid
master_byteenable : out std_logic_vector(3 downto 0); -- byteenable
master_reset_reset : out std_logic -- reset
);
end component ghrd_10as066n2_f2sdram0_m;
u0 : component ghrd_10as066n2_f2sdram0_m
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clk_reset_reset => CONNECTED_TO_clk_reset_reset, -- clk_reset.reset
master_address => CONNECTED_TO_master_address, -- master.address
master_readdata => CONNECTED_TO_master_readdata, -- .readdata
master_read => CONNECTED_TO_master_read, -- .read
master_write => CONNECTED_TO_master_write, -- .write
master_writedata => CONNECTED_TO_master_writedata, -- .writedata
master_waitrequest => CONNECTED_TO_master_waitrequest, -- .waitrequest
master_readdatavalid => CONNECTED_TO_master_readdatavalid, -- .readdatavalid
master_byteenable => CONNECTED_TO_master_byteenable, -- .byteenable
master_reset_reset => CONNECTED_TO_master_reset_reset -- master_reset.reset
);
| mit | 6d178409dd310d12bae96f5353f83c90 | 0.500237 | 4.044061 | false | false | false | false |
lfmunoz/vhdl | templates/sip_cmd/ip_block_ctrl.vhd | 2 | 8,370 | -------------------------------------------------------------------------------------
-- FILE NAME : .vhd
-- AUTHOR :
-- COMPANY : 4DSP
-- ITEM : 1
-- UNITS : Entity -
-- architecture -
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- Specified libraries
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- Entity declaration
-------------------------------------------------------------------------------------
entity ip_block_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
cmd_busy : out std_logic;
reg0 : out std_logic_vector(31 downto 0);
reg1 : out std_logic_vector(31 downto 0);
reg2 : in std_logic_vector(31 downto 0);
reg3 : in std_logic_vector(31 downto 0);
reg4 : in std_logic_vector(31 downto 0);
reg5 : in std_logic_vector(31 downto 0);
reg6 : in std_logic_vector(31 downto 0);
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end ip_block_ctrl;
-------------------------------------------------------------------------------------
-- Architecture declaration
-------------------------------------------------------------------------------------
architecture Behavioral of ip_block_ctrl is
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_REG0 : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_REG1 : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_REG2 : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_REG3 : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_REG4 : std_logic_vector(31 downto 0) := x"00000004";
constant ADDR_REG5 : std_logic_vector(31 downto 0) := x"00000005";
constant ADDR_REG6 : std_logic_vector(31 downto 0) := x"00000006";
constant ADDR_REG7 : std_logic_vector(31 downto 0) := x"00000007";
constant ADDR_REG8 : std_logic_vector(31 downto 0) := x"00000008";
constant ADDR_REG9 : std_logic_vector(31 downto 0) := x"00000009";
constant ADDR_REGA : std_logic_vector(31 downto 0) := x"0000000A";
constant ADDR_REGB : std_logic_vector(31 downto 0) := x"0000000B";
constant ADDR_REGC : std_logic_vector(31 downto 0) := x"0000000C";
constant ADDR_REGD : std_logic_vector(31 downto 0) := x"0000000D";
constant ADDR_REGE : std_logic_vector(31 downto 0) := x"0000000E";
constant ADDR_REGF : std_logic_vector(31 downto 0) := x"0000000F";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal register0 : std_logic_vector(31 downto 0);
signal register1 : std_logic_vector(31 downto 0);
signal register2 : std_logic_vector(31 downto 0);
signal register3 : std_logic_vector(31 downto 0);
signal register4 : std_logic_vector(31 downto 0);
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal register9 : std_logic_vector(31 downto 0);
signal registerA : std_logic_vector(31 downto 0);
--*************************************************************************************************
begin
--*************************************************************************************************
reg0 <= register0;
reg1 <= register1;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
stellar_cmd_inst:
entity work.stellar_generic_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => mbx_in_val,
mbx_in_reg => mbx_in_reg
);
cmd_busy <= '0';
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
in_reg_val <= '0';
in_reg <= (others => '0');
register0 <= (others=>'0');
register1 <= (others=>'0');
elsif (rising_edge(clk_cmd)) then
------------------------------------------------------------
-- Write
------------------------------------------------------------
if (out_reg_val = '1' and out_reg_addr = ADDR_REG0) then
register0 <= out_reg;
end if;
if (out_reg_val = '1' and out_reg_addr = ADDR_REG1) then
register1 <= out_reg;
end if;
------------------------------------------------------------
-- Read
------------------------------------------------------------
if (in_reg_req = '1' and in_reg_addr = ADDR_REG0) then
in_reg_val <= '1';
in_reg <= register0;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG1) then
in_reg_val <= '1';
in_reg <= register1;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG2) then
in_reg_val <= '1';
in_reg <= reg2;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG3) then
in_reg_val <= '1';
in_reg <= reg3;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG4) then
in_reg_val <= '1';
in_reg <= reg4;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG5) then
in_reg_val <= '1';
in_reg <= reg5;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG6) then
in_reg_val <= '1';
in_reg <= reg6;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
--*************************************************************************************************
end Behavioral;
--*************************************************************************************************
| mit | eb04f85a02f446fceab2243db627840e | 0.406571 | 4.21875 | false | false | false | false |
nickg/nvc | test/regress/buffer1.vhd | 1 | 606 | entity sub is
port ( x : buffer natural );
end entity;
architecture test of sub is
begin
test: process is
begin
x <= 1;
wait for 1 ns;
x <= 2;
wait for 1 ns;
assert x = 2;
wait;
end process;
end architecture;
entity buffer1 is
end entity;
architecture test of buffer1 is
signal x : natural;
begin
uut: entity work.sub port map ( x );
main: process is
begin
assert x = 0;
wait for 1 ns;
assert x = 1;
wait for 1 ns;
assert x = 2;
wait;
end process;
end architecture;
| gpl-3.0 | a1dbf4230cdb12c5eded2aa9a6c0fea7 | 0.544554 | 3.811321 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd | 4 | 6,674 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n02i01327ent IS
END c08s04b01x00p03n02i01327ent;
ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
type WORD is array(0 to 31) of BIT;
type BYTE is array(7 downto 0) of BIT;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
-- Signals with no resolution function.
signal SWITCHSIG : SWITCH_LEVEL;
signal LOGICSIG : LOGIC_SWITCH;
signal CHARSIG : CHARACTER;
signal BOOLSIG : BOOLEAN;
signal SEVERSIG : SEVERITY_LEVEL;
signal INTSIG : INTEGER;
signal POSSIG : POSITIVE;
signal DISTSIG : DISTANCE;
signal TIMESIG : TIME;
signal REALSIG : REAL;
signal POSRSIG : POSITIVE_R;
signal BYTESIG : BYTE;
signal RECSIG : DATE;
-- Composite signals with resolution functions on the scalar subelements.
BEGIN
TESTING: PROCESS
-- local variables
variable ShouldBeTime : TIME := 0 ns;
variable k : integer := 0;
BEGIN
-- Test each signal assignment.
SWITCHSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SWITCHSIG;
if (ShouldBeTime /= now or switchsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SWITCHSIG = '1');
LOGICSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on LOGICSIG;
if (ShouldBeTime /= now or logicsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (LOGICSIG = '1');
CHARSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on CHARSIG;
if (ShouldBeTime /= now or charsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (CHARSIG = '1');
BOOLSIG <= TRUE after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BOOLSIG;
if (ShouldBeTime /= now or boolsig /= true) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BOOLSIG = TRUE);
SEVERSIG <= ERROR after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SEVERSIG;
if (ShouldBeTime /= now or seversig /= error) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SEVERSIG = ERROR);
INTSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on INTSIG;
if (ShouldBeTime /= now or intsig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (INTSIG = 47);
POSSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSSIG;
if (ShouldBeTime /= now or possig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSSIG = 47);
DISTSIG <= 1 A after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on DISTSIG;
if (ShouldBeTime /= now or distsig /= 1 A) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (DISTSIG = 1 A);
TIMESIG <= 10 ns after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on TIMESIG;
if (ShouldBeTime /= now or timesig /= 10 ns) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (TIMESIG = 10 ns);
REALSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on REALSIG;
if (ShouldBeTime /= now or realsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (REALSIG = 47.0);
POSRSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSRSIG;
if (ShouldBeTime /= now or posrsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSRSIG = 47.0);
BYTESIG <= B"10101010" after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BYTESIG;
if (ShouldBeTime /= now or bytesig /= B"10101010") then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BYTESIG = B"10101010");
RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on RECSIG;
if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.DAY = 14);
assert (RECSIG.MONTH = 2);
assert (RECSIG.YEAR = 1988);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p03n02i01327"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n02i01327arch;
| gpl-2.0 | 3df772f80eeff12befb77f3f718e8792 | 0.595595 | 3.720178 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/lpm_constant_oe0.vhd | 1 | 3,564 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: lpm_constant_oe0.vhd
-- Megafunction Name(s):
-- lpm_constant
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant_oe0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_constant_oe0;
ARCHITECTURE SYN OF lpm_constant_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
lpm_constant_component : lpm_constant
GENERIC MAP (
lpm_cvalue => 10,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 5
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "10"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_oe0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| mit | 4be13d1f11b408cdb11dd7746e15e4cd | 0.625421 | 3.739769 | false | false | false | false |
tgingold/ghdl | testsuite/synth/issue1243/issue.vhdl | 1 | 381 | library ieee;
use ieee.std_logic_1164.all;
entity issue is
end issue;
architecture beh of issue is
signal foo : std_logic_vector (10 downto 0) := (others=>'0');
signal bar1 : std_logic_vector (10 downto 0) := (others=>'0');
signal bar2 : std_logic_vector (10 downto 0) := (others=>'0');
begin
bar1 <= foo or x"40";
bar2 <= foo or "1";
end architecture beh;
| gpl-2.0 | 8a50f7759ed2d2b6ed3973f54c07a3cc | 0.635171 | 3.14876 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd | 4 | 3,158 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity edge_triggered_Dff is
generic ( Tprop, Tsetup, Thold : delay_length );
port ( clk : in bit; clr : in bit; d : in bit;
q : out bit );
end entity edge_triggered_Dff;
architecture basic of edge_triggered_Dff is
begin
state_change : process (clk, clr) is
begin
if clr = '1' then
q <= '0' after Tprop;
elsif clk'event and clk = '1' then
q <= d after Tprop;
end if;
end process state_change;
end architecture basic;
architecture hi_fanout of edge_triggered_Dff is
begin
state_change : process (clk, clr) is
begin
if clr = '1' then
q <= '0' after Tprop;
elsif clk'event and clk = '1' then
q <= d after Tprop;
end if;
end process state_change;
end architecture hi_fanout;
-- code from book
entity reg4 is
port ( clk, clr : in bit; d : in bit_vector(0 to 3);
q : out bit_vector(0 to 3) );
end entity reg4;
--------------------------------------------------
architecture struct of reg4 is
component flipflop is
generic ( Tprop, Tsetup, Thold : delay_length );
port ( clk : in bit; clr : in bit; d : in bit;
q : out bit );
end component flipflop;
begin
bit0 : component flipflop
generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
port map ( clk => clk, clr => clr, d => d(0), q => q(0) );
bit1 : component flipflop
generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
port map ( clk => clk, clr => clr, d => d(1), q => q(1) );
bit2 : component flipflop
generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
port map ( clk => clk, clr => clr, d => d(2), q => q(2) );
bit3 : component flipflop
generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
port map ( clk => clk, clr => clr, d => d(3), q => q(3) );
end architecture struct;
-- end code from book
configuration fg_13_01 of reg4 is
for struct
-- code from book (in text)
for bit0, bit1 : flipflop
use entity work.edge_triggered_Dff(basic);
end for;
-- end code from book
end for;
end configuration fg_13_01;
| gpl-2.0 | 432f2166e091e013d64d5b3e7212fbdf | 0.586764 | 3.684947 | false | false | false | false |
nickg/nvc | test/eopt/issue427.vhd | 1 | 2,776 | package SYNC is
type std_ulogic is ('0', '1', 'Z', 'H', 'U');
type std_ulogic_vector is array (natural range <>) of std_ulogic;
function resolved (x : in std_ulogic_vector) return std_ulogic;
subtype std_logic is resolved std_ulogic;
type std_logic_vector is array (natural range <>) of std_logic;
constant SYNC_MAX_PLUG_SIZE : integer := 32;
subtype SYNC_PLUG_NUM_TYPE is integer range 1 to SYNC_MAX_PLUG_SIZE;
alias SYNC_SIG_TYPE is std_logic;
subtype SYNC_REQ_TYPE is integer;
subtype SYNC_ACK_TYPE is std_logic;
type SYNC_REQ_VECTOR is array (INTEGER range <>) of SYNC_REQ_TYPE;
type SYNC_ACK_VECTOR is array (INTEGER range <>) of SYNC_ACK_TYPE;
component SYNC_SIG_DRIVER
generic (
PLUG_NUM : SYNC_PLUG_NUM_TYPE := 1
);
port (
SYNC : inout SYNC_SIG_TYPE;
REQ : in SYNC_REQ_TYPE;
ACK : out SYNC_ACK_TYPE
);
end component;
end package;
package body sync is
function resolved (x : in std_ulogic_vector) return std_ulogic is
begin
return x(x'left);
end function;
end package body;
library WORK;
use WORK.SYNC.all;
entity SYNC_SIG_DRIVER is
generic (
PLUG_NUM : SYNC_PLUG_NUM_TYPE := 1
);
port (
SYNC : inout SYNC_SIG_TYPE;
REQ : in SYNC_REQ_TYPE;
ACK : out SYNC_ACK_TYPE
);
end SYNC_SIG_DRIVER;
architecture MODEL of SYNC_SIG_DRIVER is
begin
process begin
SYNC <= 'Z';
ACK <= '0';
SYNC_LOOP: loop
if (REQ > 0) then
SYNC <= 'H';
wait until (SYNC = '1' or SYNC = '0');
SYNC <= '0';
ACK <= '1';
wait until (REQ = 0);
ACK <= '0';
elsif (REQ = 0) then
SYNC <= '0';
else
SYNC <= 'Z';
end if;
wait on REQ;
end loop;
end process;
end MODEL;
library WORK;
use WORK.SYNC.all;
entity TEST_NG is
end TEST_NG;
architecture MODEL of TEST_NG is
constant PLUG_SIZE : integer := 2;
signal SYNC : SYNC_SIG_TYPE;
signal REQ : SYNC_REQ_VECTOR(1 to PLUG_SIZE);
signal ACK : SYNC_ACK_VECTOR(1 to PLUG_SIZE);
begin
PLUG : for i in 1 to PLUG_SIZE generate
DRIVER : SYNC_SIG_DRIVER
generic map (PLUG_NUM => i)
port map (SYNC => SYNC,REQ => REQ(i),ACK => ACK(i));
end generate;
process begin
REQ(1) <= 0;
wait;
end process;
process begin
REQ(2) <= 0;
wait;
end process;
end MODEL;
| gpl-3.0 | 13ef0f47b99cc9e7562d78065fed6b32 | 0.516571 | 3.652632 | false | false | false | false |
nickg/nvc | test/bounds/aggregate.vhd | 1 | 1,319 | entity aggregate is
end entity;
architecture test of aggregate is
type my_enum is (A, B, C);
type my_enum_map is array (my_enum) of integer;
constant c1 : my_enum_map := (A => 1, A => 2, C => 3); -- Error
constant c2 : my_enum_map := my_enum_map'(A => 1, B => 2); -- Error
constant c3 : my_enum_map := (b => 1, a to c => 2); -- Error
subtype my_bit_vec is bit_vector(3 downto 1);
type my_int is range 10 downto 5;
type my_int_map is array (my_int) of integer;
constant c4 : my_bit_vec := (3 => '1', 2 => '0'); -- Error
constant c5 : my_int_map := (7 => 2); -- Error
constant c6 : integer_vector(1 to 3) := (1, 2, 3); -- OK
constant c7 : integer_vector(1 to 4) := (c6, 4); -- OK
constant c8 : integer_vector(1 to 3) := (c6, 4); -- Error
constant c9 : integer_vector(1 to 5) := (c6, 4); -- Error
constant c10 : integer_vector(1 to 3) := (1 to 3 => c6); -- OK
constant c11 : integer_vector(1 to 3) := (1 to 2 => c6(1 to 2)); -- Error
constant c12 : integer_vector(1 to 4) := (1 to 4 => c6); -- Error
constant c13 : integer_vector(1 to 4) :=
( integer_vector'(1, 2), integer_vector'(3, 4) ); -- OK
constant c14 : bit_vector(7 downto 0) :=
(3 downto 0 => "111", others => '0'); -- Error
begin
end architecture;
| gpl-3.0 | 2a72052875267619a5dcd7ae6479a6d3 | 0.55345 | 2.873638 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd | 4 | 1,901 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1389.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n02i01389ent IS
END c08s05b00x00p04n02i01389ent;
ARCHITECTURE c08s05b00x00p04n02i01389arch OF c08s05b00x00p04n02i01389ent IS
subtype C2 is BIT_VECTOR(1 to 2);
BEGIN
TESTING: PROCESS
variable S1 : BIT;
variable T1 : BIT;
variable BIT2 : C2 := B"11";
BEGIN
(S1, T1) := BIT2;
assert NOT((S1 = '1') and (T1 = '1'))
report "***PASSED TEST: c08s05b00x00p04n02i01389"
severity NOTE;
assert ((S1 = '1') and (T1 = '1'))
report "***FAILED TEST: c08s05b00x00p04n02i01389 - Base types of the expression on the right hand side is the same as the base type of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n02i01389arch;
| gpl-2.0 | 5a93244dd34db8cbab809f3aa9f98e77 | 0.659127 | 3.533457 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd | 4 | 3,246 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc478.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00478ent IS
END c03s02b01x01p19n01i00478ent;
ARCHITECTURE c03s02b01x01p19n01i00478arch OF c03s02b01x01p19n01i00478ent IS
function resolution4(i:in string) return character is
variable temp : character := 's' ;
begin
return temp;
end resolution4;
subtype character_state is resolution4 character;
constant C66 : character_state := 's';
function complex_scalar(s : character_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return character_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : character_state;
signal S2 : character_state;
signal S3 : character_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00478"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00478 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00478arch;
| gpl-2.0 | b33d6acb9aab2ca37f1b2ed5c2ed249b | 0.658041 | 3.731034 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue376/fx3_model_modified.vhdl | 1 | 7,751 | -- Copyright (c) 2013 Nuand LLC
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
library nuand ;
use nuand.util.all ;
entity fx3_model is
port (
fx3_pclk : buffer std_logic := '1' ;
fx3_gpif : inout std_logic_vector(31 downto 0) ;
fx3_ctl : inout std_logic_vector(12 downto 0) ;
fx3_uart_rxd : in std_logic ;
fx3_uart_txd : buffer std_logic ;
fx3_uart_cts : buffer std_logic ;
fx3_rx_en : in std_logic ;
fx3_rx_meta_en : in std_logic ;
fx3_tx_en : in std_logic ;
fx3_tx_meta_en : in std_logic
) ;
end entity ; -- fx3_model
architecture dma of fx3_model is
constant PCLK_HALF_PERIOD : time := 1 sec * (1.0/100.0e6/2.0) ;
-- Control mapping
-- alias dma0_rx_ack is fx3_ctl( 0) ;
-- alias dma1_rx_ack is fx3_ctl( 1) ;
-- alias dma2_tx_ack is fx3_ctl( 2) ;
-- alias dma3_tx_ack is fx3_ctl( 3) ;
-- alias dma_rx_enable is fx3_ctl( 4) ;
-- alias dma_tx_enable is fx3_ctl( 5) ;
-- alias dma_idle is fx3_ctl( 6) ;
-- alias system_reset is fx3_ctl( 7) ;
-- alias dma0_rx_reqx is fx3_ctl( 8) ;
-- alias dma1_rx_reqx is fx3_ctl(12) ; -- due to 9 being connected to dclk
-- alias dma2_tx_reqx is fx3_ctl(10) ;
-- alias dma3_tx_reqx is fx3_ctl(11) ;
type gpif_state_t is (IDLE, TX_SAMPLES, RX_SAMPLES) ;
signal gpif_state : gpif_state_t ;
begin
-- DCLK which isn't used
fx3_ctl(9) <= '0' ;
-- Create a 100MHz clock output
fx3_pclk <= not fx3_pclk after PCLK_HALF_PERIOD ;
rx_sample_stream : process
constant BLOCK_SIZE : natural := 512 ;
variable count : natural := 0 ;
begin
-- dma0_rx_reqx <= '1' ;
fx3_ctl (8) <= '1' ;
-- dma1_rx_reqx <= '1' ;
fx3_ctl (12) <= '1' ;
-- dma_rx_enable <= '0' ;
fx3_ctl (4) <= '0' ;
-- wait until rising_edge(fx3_pclk) and system_reset = '0' ;
wait until rising_edge(fx3_pclk) and fx3_ctl (7) = '0' ;
for i in 1 to 10 loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
if( fx3_rx_en = '0' ) then
wait;
end if;
wait for 30 us;
-- dma_rx_enable <= '1' ;
fx3_ctl (4) <= '1' ;
while true loop
for i in 0 to 2 loop
-- dma0_rx_reqx <= '0' ;
fx3_ctl (8) <= '0' ;
-- wait until rising_edge( fx3_pclk ) and dma0_rx_ack = '1' ;
wait until rising_edge( fx3_pclk ) and fx3_ctl (0) = '1' ;
wait until rising_edge( fx3_pclk ) ;
wait until rising_edge( fx3_pclk ) ;
-- dma0_rx_reqx <= '1' ;
fx3_ctl (8) <= '1' ;
for i in 1 to BLOCK_SIZE loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
end loop ;
-- dma_rx_enable <= '0' ;
fx3_ctl (4) <= '0' ;
for i in 0 to 5000 loop
wait until rising_edge(fx3_pclk) ;
end loop ;
-- dma_rx_enable <= '1' ;
fx3_ctl (4) <= '1' ;
for i in 0 to 10 loop
wait until rising_edge(fx3_pclk);
end loop ;
end loop ;
report "Done with RX sample stream" ;
wait ;
end process ;
tx_sample_stream : process
constant BLOCK_SIZE : natural := 512 ;
variable count : natural := 0 ;
variable timestamp_cntr : natural := 80;
variable header_len : natural := 0;
begin
-- dma2_tx_reqx <= '1' ;
fx3_ctl (10) <= '1' ;
-- dma3_tx_reqx <= '1' ;
fx3_ctl (11) <= '1' ;
-- dma_tx_enable <= '0' ;
fx3_ctl (5) <= '0' ;
fx3_gpif <= (others =>'Z') ;
-- wait until system_reset = '0' ;
wait until fx3_ctl (7) = '0' ;
for i in 0 to 1000 loop
wait until rising_edge( fx3_pclk ) ;
end loop ;
if( fx3_tx_en = '0' ) then
wait;
end if;
wait for 120 us;
-- dma_tx_enable <= '1' ;
fx3_ctl (5) <= '1' ;
for i in 0 to 3 loop
-- dma3_tx_reqx <= '0' ;
fx3_ctl (11) <= '0' ;
-- wait until rising_edge( fx3_pclk ) and dma3_tx_ack = '1' ;
wait until rising_edge( fx3_pclk ) and fx3_ctl (3) = '1' ;
wait until rising_edge( fx3_pclk ) ;
wait until rising_edge( fx3_pclk ) ;
-- dma3_tx_reqx <= '1' ;
fx3_ctl (11) <= '1' ;
if( fx3_tx_meta_en = '1') then
for i in 1 to 4 loop
if (i = 1 ) then
fx3_gpif <= x"12341234";
elsif (i = 3 ) then
fx3_gpif <= (others => '0');
elsif(i = 4) then
fx3_gpif <= (others => '1');
elsif (i = 2) then
fx3_gpif(31 downto 0) <= std_logic_vector(to_signed(timestamp_cntr, 32));
timestamp_cntr := timestamp_cntr + 508 * 2;
end if;
wait until rising_edge( fx3_pclk );
end loop;
header_len := 4;
else
header_len := 0;
end if;
for i in 1 to BLOCK_SIZE - header_len loop
fx3_gpif(31 downto 16) <= std_logic_vector(to_signed(count, 16)) ;
fx3_gpif(15 downto 0) <= std_logic_vector(to_signed(-count, 16)) ;
count := (count + 1) mod 2048 ;
wait until rising_edge( fx3_pclk );
end loop ;
fx3_gpif <= (others =>'Z');
for i in 1 to 10 loop
wait until rising_edge( fx3_pclk );
end loop ;
end loop ;
report "Done with TX sample stream" ;
wait ;
end process ;
reset_system : process
begin
-- system_reset <= '1' ;
fx3_ctl (7) <= '1' ;
-- dma_idle <= '0' ;
fx3_ctl (6) <= '0' ;
nop( fx3_pclk, 100 ) ;
-- system_reset <= '0' ;
fx3_ctl (7) <= '0' ;
nop( fx3_pclk, 10 ) ;
-- dma_idle <= '1' ;
fx3_ctl (6) <= '1' ;
wait ;
end process ;
-- TODO: UART Interface
fx3_uart_txd <= '1' ;
fx3_uart_cts <= '1' ;
end architecture ; -- dma
architecture inband_scheduler of fx3_model is
begin
end architecture ; -- inband_scheduler
| gpl-2.0 | 406e181c074272362e54e9ff1c8b0071 | 0.501226 | 3.426614 | false | false | false | false |
nickg/nvc | test/regress/ename1.vhd | 1 | 1,070 | entity bot is
end entity;
architecture test of bot is
signal x, y : natural;
begin
p1: process (y) is
begin
x <= y + 5;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ename1 is
end entity;
architecture test of ename1 is
begin
uut: entity work.bot;
p2: process is
begin
assert <<signal uut.x : natural>> = 0;
wait for 1 ns;
<<signal uut.y : natural>> <= force 5;
wait for 0 ns;
assert <<signal uut.x : natural>> = 5;
wait for 0 ns;
assert <<signal .ename1.uut.x : natural>> = 10;
<<signal uut.y : natural>> <= release;
wait for 1 ns;
assert <<signal .ename1.uut.x : natural>> = 5;
wait for 10 ns;
assert <<signal .ename1.uut.x : natural>> = 25;
wait;
end process;
p3: process is
alias y is <<signal uut.y : natural>>;
begin
y <= 0;
wait for 10 ns;
y <= 20;
wait;
end process;
end architecture;
| gpl-3.0 | ce188f0992ac1684a728c4e168e53c30 | 0.497196 | 3.848921 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd | 4 | 3,730 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00743pkg is
type arrtype is array (1 to 5) of bit;
constant defcon1 : bit;
constant defcon2 : integer;
constant defcon3 : arrtype;
constant defcon4 : boolean;
component comp1
generic (
constant dgc1 : bit := defcon1;
constant dgc2 : integer := defcon2;
constant dgc3 : arrtype := defcon3;
constant dgc4 : boolean := defcon4
);
port ( signal dcent1 : inout bit := dgc1;
signal dcent2 : inout integer := dgc2;
signal dcent3 : inout arrtype := dgc3;
signal dcent4 : inout boolean := dgc4
);
end component;
end c01s01b01x01p04n01i00743pkg;
package body c01s01b01x01p04n01i00743pkg is
constant defcon1 : bit := '1';
constant defcon2 : integer := 113;
constant defcon3 : arrtype := ('1','0','1','0','1');
constant defcon4 : boolean := TRUE;
end c01s01b01x01p04n01i00743pkg;
use work.c01s01b01x01p04n01i00743pkg.all;
entity c01s01b01x01p04n01i00743ent_a is
generic (
constant gc1 : bit;
constant gc2 : integer;
constant gc3 : arrtype;
constant gc4 : boolean
);
port ( signal cent1 : inout bit;
signal cent2 : inout integer;
signal cent3 : inout arrtype;
signal cent4 : inout boolean
);
end c01s01b01x01p04n01i00743ent_a;
architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00743"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00743arch_a;
use work.c01s01b01x01p04n01i00743pkg.all;
ENTITY c01s01b01x01p04n01i00743ent IS
generic ( constant gen_con : integer := 1334 );
port ( signal ee1 : inout boolean := TRUE;
signal ee2 : inout bit;
signal ee3 : inout integer;
signal ee4 : inout arrtype
);
END c01s01b01x01p04n01i00743ent;
ARCHITECTURE c01s01b01x01p04n01i00743arch OF c01s01b01x01p04n01i00743ent IS
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
generic map ( dgc1, dgc2, dgc3, dgc4 )
port map ( dcent1, dcent2, dcent3, dcent4 );
BEGIN
u1 : comp1;
END c01s01b01x01p04n01i00743arch;
| gpl-2.0 | 701697d9c338b5aeaba4223eccd7eecb | 0.652815 | 3.387829 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd | 4 | 2,716 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3135.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p12n01i03135ent_a IS
generic ( g1 : integer := 0 );
END c05s02b01x02p12n01i03135ent_a;
ARCHITECTURE c05s02b01x02p12n01i03135arch_a OF c05s02b01x02p12n01i03135ent_a IS
BEGIN
TESTING: PROCESS
BEGIN
assert g1 /= 0 report "g1 = 0 " severity FAILURE;
assert g1 /= 1 report "g1 = 1 " severity FAILURE;
assert g1 = -1 report "g1 /= -1 " severity FAILURE;
assert NOT( g1 /= 0 and
g1 /= 1 and
g1 = -1 )
report "***PASSED TEST: c05s02b01x02p12n01i03135"
severity NOTE;
assert ( g1 /= 0 and
g1 /= 1 and
g1 = -1 )
report "***FAILED TEST: c05s02b01x02p12n01i03135 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p12n01i03135arch_a;
ENTITY c05s02b01x02p12n01i03135ent IS
generic ( test_g : integer := -1 );
END c05s02b01x02p12n01i03135ent;
ARCHITECTURE c05s02b01x02p12n01i03135arch OF c05s02b01x02p12n01i03135ent IS
component ic_socket
generic ( local_g1 : integer := 1 );
end component;
for instance : ic_socket use entity work.c05s02b01x02p12n01i03135ent_a (c05s02b01x02p12n01i03135arch_a)
generic map (test_g);
BEGIN
instance : ic_socket;
END c05s02b01x02p12n01i03135arch;
configuration c05s02b01x02p12n01i03135cfg of c05s02b01x02p12n01i03135ent is
for c05s02b01x02p12n01i03135arch
end for;
end c05s02b01x02p12n01i03135cfg;
| gpl-2.0 | 9ad65837d0b98370ea570fa8ccb0f3f4 | 0.667526 | 3.272289 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd | 4 | 5,788 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1785.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
Package c09s06b00x00p04n07i01785pkg is
type info is record
field_1 : integer;
field_2 : real;
end record;
type stuff is array (Integer range 1 to 2) of info;
end c09s06b00x00p04n07i01785pkg;
use work.c09s06b00x00p04n07i01785pkg.all;
entity c09s06b00x00p04n07i01785ent_a is
port (
port_0 : in Boolean ;
port_1 : in Bit ;
port_2 : in Character ;
port_3 : in SEVERITY_LEVEL ;
port_4 : in Integer ;
port_5 : in Real ;
port_6 : in TIME ;
port_7 : in Natural ;
port_8 : in Positive ;
port_9 : in String ;
port_A : in Bit_vector ;
port_B : in stuff
);
end c09s06b00x00p04n07i01785ent_a;
use work.c09s06b00x00p04n07i01785pkg.all;
architecture c09s06b00x00p04n07i01785arch_a of c09s06b00x00p04n07i01785ent_a is
-- Check that the data was passed...
begin
TESTING: PROCESS(port_0,port_1,port_2,port_3,port_4,port_5,port_6,port_7,port_8)
BEGIN
assert NOT( port_0 = True and
port_1 = '0' and
port_2 = '@' and
port_3 = NOTE and
port_4 = 123456789 and
port_5 = 987654321.5 and
port_6 = 110 ns and
port_7 = 12312 and
port_8 = 3423 and
port_9 = "16 characters OK" and
port_A = B"01010010100101010010101001010100" and
port_B = ((123, 456.7), (890, 135.7)))
report "***PASSED TEST: c09s06b00x00p04n07i01785"
severity NOTE;
assert ( port_0 = True and
port_1 = '0' and
port_2 = '@' and
port_3 = NOTE and
port_4 = 123456789 and
port_5 = 987654321.5 and
port_6 = 110 ns and
port_7 = 12312 and
port_8 = 3423 and
port_9 = "16 characters OK" and
port_A = B"01010010100101010010101001010100" and
port_B = ((123, 456.7), (890, 135.7)))
report "***FAILED TEST: c09s06b00x00p04n07i01785 - Port map aspect associates a single actual with each local port in the corresponding component declaration test failed."
severity ERROR;
END PROCESS TESTING;
end c09s06b00x00p04n07i01785arch_a;
-----------------------------------------------------------------------
ENTITY c09s06b00x00p04n07i01785ent IS
END c09s06b00x00p04n07i01785ent;
use work.c09s06b00x00p04n07i01785pkg.all;
ARCHITECTURE c09s06b00x00p04n07i01785arch OF c09s06b00x00p04n07i01785ent IS
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal sig_0 : Boolean := TRUE;
signal sig_1 : Bit := '0';
signal sig_2 : Character := '@';
signal sig_3 : SEVERITY_LEVEL := NOTE;
signal sig_4 : Integer := 123456789;
signal sig_5 : Real := 987654321.5;
signal sig_6 : TIME := 110 NS;
signal sig_7 : Natural := 12312;
signal sig_8 : Positive := 3423;
signal sig_9 : String16 := "16 characters OK";
signal sig_A : REG32 := B"0101_0010_1001_0101_0010_1010_0101_0100";
signal sig_B : stuff := (( 123, 456.7 ), ( 890, 135.7 ));
component MultiType
port (
port_0 : in Boolean ;
port_1 : in Bit ;
port_2 : in Character ;
port_3 : in SEVERITY_LEVEL ;
port_4 : in Integer ;
port_5 : in Real ;
port_6 : in TIME ;
port_7 : in Natural ;
port_8 : in Positive ;
port_9 : in String ;
port_A : in Bit_vector ;
port_B : in stuff
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n07i01785ent_a (c09s06b00x00p04n07i01785arch_a);
BEGIN
u1 : MultiType
port map (
port_0 => sig_0,
port_1 => sig_1,
port_2 => sig_2,
port_3 => sig_3,
port_4 => sig_4,
port_5 => sig_5,
port_6 => sig_6,
port_7 => sig_7,
port_8 => sig_8,
port_9 => sig_9,
port_A => sig_A,
port_B => sig_B
);
END c09s06b00x00p04n07i01785arch;
| gpl-2.0 | 23680b2a4d73beb7d4d61c45b84d278f | 0.52246 | 3.564039 | false | false | false | false |
makestuff/comm-fpga | epp/vhdl/tb_unit/comm_fpga_epp_tb.vhdl | 1 | 6,313 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity comm_fpga_epp_tb is
end entity;
architecture behavioural of comm_fpga_epp_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
-- External interface ---------------------------------------------------------------------------
signal eppClk : std_logic;
signal eppData : std_logic_vector(7 downto 0);
signal eppAddrStb : std_logic;
signal eppDataStb : std_logic;
signal eppWrite : std_logic;
signal eppWait : std_logic;
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- comm_fpga_epp selects one of 128 channels to access
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data to be read from the selected channel
signal h2fValid : std_logic; -- comm_fpga_epp drives h2fValid='1' when it wants to write to the selected channel
signal h2fReady : std_logic; -- this must be driven high if the selected channel has room for data to be written to it
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data to be written to the selected channel
signal f2hValid : std_logic; -- this must be asserted if the selected channel has data available for reading
signal f2hReady : std_logic; -- comm_fpga_epp drives f2hReady='1' when it wants to read from the selected channel
begin
-- Instantiate comm_fpga_epp for testing
uut: entity work.comm_fpga_epp
port map(
clk_in => sysClk,
reset_in => '0',
-- EPP interface --------------------------------------------------------------------------
eppData_io => eppData,
eppAddrStb_in => eppAddrStb,
eppDataStb_in => eppDataStb,
eppWrite_in => eppWrite,
eppWait_out => eppWait,
-- Channel read/write interface -----------------------------------------------------------
chanAddr_out => chanAddr, -- which channel to connect the pipes to
f2hData_in => f2hData, -- \
f2hValid_in => f2hValid, -- Host >> FPGA pipe
f2hReady_out => f2hReady, -- /
h2fData_out => h2fData, -- \
h2fValid_out => h2fValid, -- Host << FPGA pipe
h2fReady_in => h2fReady -- /
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time for
-- signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive the EPP side
process
begin
eppData <= (others => 'Z');
eppAddrStb <= '1';
eppDataStb <= '1';
eppWrite <= '1';
wait for 10 ns;
eppWrite <= '0'; -- bring it out of RESET
wait for 45 ns;
-- Do address write
eppData <= x"55";
wait for 5 ns;
eppAddrStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppAddrStb <= '1';
wait for 5 ns;
eppData <= (others => 'Z');
wait until eppWait = '0';
wait for 5 ns;
-- Do data write 1
eppData <= x"12";
wait for 5 ns;
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait for 5 ns;
eppData <= (others => 'Z');
wait until eppWait = '0';
wait for 5 ns;
-- Do data write 2
eppData <= x"34";
wait for 5 ns;
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait for 5 ns;
eppData <= (others => 'Z');
wait until eppWait = '0';
wait for 5 ns;
-- Do data write 3
eppData <= x"56";
wait for 5 ns;
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait for 5 ns;
eppData <= (others => 'Z');
wait until eppWait = '0';
wait for 5 ns;
-- Do data write 4
eppData <= x"78";
wait for 5 ns;
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait for 5 ns;
eppData <= (others => 'Z');
wait until eppWait = '0';
wait for 5 ns;
eppWrite <= '1'; -- reading
-- Do data read 1
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait until eppWait = '0';
wait for 5 ns;
-- Do data read 2
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait until eppWait = '0';
wait for 5 ns;
-- Do data read 3
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait until eppWait = '0';
wait for 5 ns;
-- Do data read 4
eppDataStb <= '0';
wait until eppWait = '1';
wait for 5 ns;
eppDataStb <= '1';
wait until eppWait = '0';
eppWrite <= '0'; -- writing again
wait;
end process;
-- Drive the internal side
process
begin
f2hValid <= '0';
h2fReady <= '1';
f2hData <= (others => 'Z');
wait until h2fValid = '1';
wait until h2fValid = '0';
h2fReady <= '0';
wait for 120 ns;
h2fReady <= '1';
wait for 400 ns;
f2hValid <= '1';
f2hData <= x"87";
wait until f2hReady = '1';
f2hData <= x"65";
wait until f2hReady = '0';
wait until f2hReady = '1';
f2hData <= x"43";
wait until f2hReady = '0';
wait until f2hReady = '1';
f2hData <= x"21";
wait until f2hReady = '0';
wait until f2hReady = '1';
f2hData <= (others => 'Z');
f2hValid <= '0';
wait;
end process;
end architecture;
| gpl-3.0 | 4c687ab37fb057e5aed68e4365c6c68f | 0.595438 | 3.220918 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug090/crash6.vhdl | 1 | 1,708 | library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
t_n : in std_logic;
d : c_vector (len - 1 downto 0);
q : out stdector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : s;
signal rst_n : std_logic;
signal din, dout, dout2 : std_loor (7 downto 0);
component dff is
generic (len : natural := 8);
port (clk : in std_logic;
st_n : in std_logic;
d : std_ltor (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end component;
begin
mydff : entity work.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
dff2 : dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout2);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
chkr: process (clk)
begin
if rst_n = '0' then
null;
elsif rising_edge (clk) then
assert dout = dout2 report 2incoherence" severity failure;
[nd if;
end process chkr;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in din'range loop
din(i) <= '0';
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
| gpl-2.0 | 235795885e3d76dba7c8e652944a2f31 | 0.568501 | 3.174721 | false | false | false | false |
tgingold/ghdl | testsuite/synth/func01/tb_func06.vhdl | 1 | 581 | entity tb_func06 is
end tb_func06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func06 is
signal r : std_logic_vector(15 downto 0);
signal s : natural;
begin
dut: entity work.func06
port map (s, r);
process
begin
s <= 2;
wait for 1 ns;
assert r = x"1234" severity failure;
s <= 0;
wait for 1 ns;
assert r = x"0000" severity failure;
s <= 3;
wait for 1 ns;
assert r = x"5678" severity failure;
s <= 4;
wait for 1 ns;
assert r = x"0000" severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 988670785121a5ae637767769657b63e | 0.612737 | 3.192308 | false | false | false | false |
nickg/nvc | test/regress/record31.vhd | 1 | 844 | library ieee;
use ieee.std_logic_1164.all;
package pack is
type rec is record
f : std_logic_vector;
end record;
subtype rec4 is rec(f(1 to 4));
end package;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pack.all;
entity record31 is
port ( r : inout rec4 );
end entity;
architecture test of record31 is
begin
p1: process is
begin
r.f <= "ZZZZ";
wait for 1 ns;
assert r.f = "1010";
r.f <= "Z1ZZ";
wait for 1 ns;
assert r.f = "1X10";
wait;
end process;
p2: process is
begin
r.f <= "1010";
wait for 1 ns;
assert r.f = "1010";
wait for 1 ns;
assert r.f = "1X10";
wait;
end process;
end architecture;
| gpl-3.0 | 2a8e96c323c6618d5a21765224f8bf73 | 0.492891 | 3.531381 | false | false | false | false |
tgingold/ghdl | testsuite/synth/dispin01/tb_rec01.vhdl | 1 | 596 | entity tb_rec01 is
end tb_rec01;
library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;
architecture behav of tb_rec01 is
signal inp : myrec;
signal r : std_logic;
begin
dut: entity work.rec01
port map (inp => inp, o => r);
process
constant av : std_logic_vector := b"11001";
constant bv : std_logic_vector := b"01011";
constant rv : std_logic_vector := b"11011";
begin
for i in av'range loop
inp.a <= av (i);
inp.b <= bv (i);
wait for 1 ns;
assert r = rv(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 24c24587722d1561a4c633796efb5afd | 0.61745 | 3.104167 | false | false | false | false |
nickg/nvc | test/regress/concat7.vhd | 1 | 421 | entity concat7 is
end entity;
architecture test of concat7 is
type rec is record
f : string;
end record;
constant c1 : rec := ( f => ('a' & "bc") );
begin
p: process is
variable v : string(1 to 4);
begin
report "c1.f = " & c1.f;
v := ' ' & c1.f;
wait for 1 ns;
report v;
assert v = " abc";
wait;
end process;
end architecture;
| gpl-3.0 | 95035f561401500cb86ae0c8bed4dffc | 0.498812 | 3.395161 | false | false | false | false |
nickg/nvc | test/regress/textio7.vhd | 1 | 1,237 | --
-- Test READ for real types
--
entity textio7 is
end entity;
use std.textio.all;
architecture test of textio7 is
procedure check(value, expect : real) is
variable l : line;
begin
assert abs(value - expect) < 0.0001
report "value=" & real'image(value) & " expect=" & real'image(expect)
severity failure;
write(l, value);
writeline(output, l);
deallocate(l);
end procedure;
begin
main: process is
variable r : real;
variable l : line;
begin
l := new string'("1.23");
read(l, r);
check(r, 1.23);
deallocate(l);
l := new string'("+4");
read(l, r);
check(r, 4.0);
deallocate(l);
l := new string'("-0.001");
read(l, r);
check(r, -0.001);
deallocate(l);
l := new string'("1.23e2");
read(l, r);
check(r, 123.0);
deallocate(l);
l := new string'("1.994500e+03");
read(l, r);
check(r, 1994.5);
deallocate(l);
l := new string'(" 1.994500e+03");
read(l, r);
check(r, 1994.5);
deallocate(l);
wait;
end process;
end architecture;
| gpl-3.0 | 4ce43aad101fbdcb3ee0f7f36c170b8e | 0.48747 | 3.544413 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_timer_v2_0/hdl/src/vhdl/mux_onehot_f.vhd | 3 | 12,555 | -- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0_2;
--use proc_common_v4_0_2.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
| gpl-3.0 | f06da7798d56ef90247ed2e61de19bd7 | 0.441736 | 4.730595 | false | false | false | false |
nickg/nvc | test/simp/osvvm4.vhd | 1 | 1,189 | package ScoreboardGenericPkg is
generic (
type ExpectedType ;
type ActualType ;
function Match(Actual : ActualType ; -- defaults
Expected : ExpectedType) return boolean ; -- is "=" ;
function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
function actual_to_string (A : ActualType) return string -- is to_string ;
) ;
end package;
-------------------------------------------------------------------------------
package AlertLogPkg is
function MetaMatch (l, r : bit_vector) return boolean ;
function MetaMatch (l, r : integer) return boolean ;
end package;
-------------------------------------------------------------------------------
package ScoreBoardPkg_slv is new work.ScoreboardGenericPkg
generic map (
ExpectedType => bit_vector,
ActualType => bit_vector,
Match => work.AlertLogPkg.MetaMatch, -- "=", [std_logic_vector, std_logic_vector return boolean]
expected_to_string => to_hstring, -- [std_logic_vector return string]
actual_to_string => to_hstring -- [std_logic_vector return string]
) ;
| gpl-3.0 | e3199129049ac79c2f83ed6d6c064562 | 0.541632 | 4.794355 | false | false | false | false |
nickg/nvc | test/regress/guard3.vhd | 1 | 564 | entity guard3 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of guard3 is
signal s : std_logic bus := 'H';
begin
p1: process is
begin
assert s = 'H';
s <= '0';
wait for 1 ns;
assert s = '0';
s <= null after 5 ns;
wait for 1 ns;
assert s = '0';
wait for 5 ns;
assert s = 'Z';
s <= '1' after 1 ns;
wait for 0 ns;
assert s = 'Z';
wait for 1 ns;
assert s = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 6ed2c9fe31bfa923a99a3de63dd8083d | 0.485816 | 3.439024 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd | 3 | 10,182 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc995.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c06s03b00x00p08n01i00995pkg IS
--
-- This packages contains declarations of User attributes
--
-- ----------------------------------------------------------------------------------
--
TYPE RESISTANCE IS RANGE 0 TO 1E9
UNITS
pf;
nf = 1000 pf;
mf = 1000 nf;
END UNITS;
TYPE t_logic IS (
U, D,
Z0, Z1, ZDX, DZX, ZX,
W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
);
--
-- Scalar types Declarations
--
SUBTYPE st_scl1 IS BOOLEAN;
SUBTYPE st_scl2 IS BIT;
SUBTYPE st_scl3 IS CHARACTER;
SUBTYPE st_scl4 IS INTEGER;
SUBTYPE st_scl5 IS REAL;
SUBTYPE st_scl6 IS TIME;
SUBTYPE st_scl7 IS RESISTANCE;
SUBTYPE st_scl8 IS t_logic;
--
-- character string types
--
SUBTYPE st_str1 IS STRING;
SUBTYPE st_str2 IS STRING (1 TO 4);
--
-- Scalar types with a range constraint
--
SUBTYPE cst_scl1 IS BOOLEAN RANGE TRUE TO TRUE;
SUBTYPE cst_scl2 IS BIT RANGE '0' TO '0';
SUBTYPE cst_scl3 IS CHARACTER RANGE 'a' TO 'z';
SUBTYPE cst_scl4 IS INTEGER RANGE 10 DOWNTO 0;
SUBTYPE cst_scl5 IS REAL RANGE 0.0 TO 10.0;
SUBTYPE cst_scl6 IS TIME RANGE 0 fs TO 10 ns;
SUBTYPE cst_scl7 IS RESISTANCE RANGE 0 pf TO 10000 pf;
SUBTYPE cst_scl8 IS t_logic RANGE F0 TO FX;
-- ------------------------------------------------------------------------------------
-- Attribute Declarations
-- ------------------------------------------------------------------------------------
--
ATTRIBUTE atr_scl1 : st_scl1;
ATTRIBUTE atr_scl2 : st_scl2;
ATTRIBUTE atr_scl3 : st_scl3;
ATTRIBUTE atr_scl4 : st_scl4;
ATTRIBUTE atr_scl5 : st_scl5;
ATTRIBUTE atr_scl6 : st_scl6;
ATTRIBUTE atr_scl7 : st_scl7;
ATTRIBUTE atr_scl8 : st_scl8;
ATTRIBUTE atr_str1 : st_str1;
ATTRIBUTE atr_str2 : st_str2;
ATTRIBUTE cat_scl1 : cst_scl1;
ATTRIBUTE cat_scl2 : cst_scl2;
ATTRIBUTE cat_scl3 : cst_scl3;
ATTRIBUTE cat_scl4 : cst_scl4;
ATTRIBUTE cat_scl5 : cst_scl5;
ATTRIBUTE cat_scl6 : cst_scl6;
ATTRIBUTE cat_scl7 : cst_scl7;
ATTRIBUTE cat_scl8 : cst_scl8;
END;
USE WORK.c06s03b00x00p08n01i00995pkg.all;
ENTITY c06s03b00x00p08n01i00995ent IS
ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS TRUE;
ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS '0';
ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS 'z';
ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS 0;
ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10.0;
-- ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10 ns;
ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10000 pf;
ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS FX;
ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00995ent: ENTITY IS "entity";
ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00995ent: ENTITY IS "enty";
ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS TRUE;
ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS '0';
ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS 'z';
ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS 0;
ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10.0;
-- ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10 ns;
ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS 10000 pf;
ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS FX;
END c06s03b00x00p08n01i00995ent;
ARCHITECTURE c06s03b00x00p08n01i00995arch OF c06s03b00x00p08n01i00995ent IS
BEGIN
TESTING: PROCESS
BEGIN
ASSERT c06s03b00x00p08n01i00995ent'atr_scl1 = TRUE
REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl2 = '0'
REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl3 = 'z'
REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl4 = 0
REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl5 = 10.0
REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
-- ASSERT c06s03b00x00p08n01i00995ent'atr_scl6 = 10 ns
-- REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_scl8 = FX
REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_str1 = "entity"
REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'atr_str2 = "enty"
REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl1 = TRUE
REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl2 = '0'
REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl3 = 'z'
REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl4 = 0
REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl5 = 10.0
REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
-- ASSERT c06s03b00x00p08n01i00995ent'cat_scl6 = 10 ns
-- REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00995ent'cat_scl8 = FX
REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
assert NOT( c06s03b00x00p08n01i00995ent'atr_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'atr_scl2 = '0'
and c06s03b00x00p08n01i00995ent'atr_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'atr_scl4 = 0
and c06s03b00x00p08n01i00995ent'atr_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'atr_scl8 = FX
and c06s03b00x00p08n01i00995ent'atr_str1 = "entity"
and c06s03b00x00p08n01i00995ent'atr_str2 = "enty"
and c06s03b00x00p08n01i00995ent'cat_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'cat_scl2 = '0'
and c06s03b00x00p08n01i00995ent'cat_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'cat_scl4 = 0
and c06s03b00x00p08n01i00995ent'cat_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'cat_scl8 = FX )
report "***PASSED TEST: c06s03b00x00p08n01i00995"
severity NOTE;
assert ( c06s03b00x00p08n01i00995ent'atr_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'atr_scl2 = '0'
and c06s03b00x00p08n01i00995ent'atr_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'atr_scl4 = 0
and c06s03b00x00p08n01i00995ent'atr_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'atr_scl8 = FX
and c06s03b00x00p08n01i00995ent'atr_str1 = "entity"
and c06s03b00x00p08n01i00995ent'atr_str2 = "enty"
and c06s03b00x00p08n01i00995ent'cat_scl1 = TRUE
and c06s03b00x00p08n01i00995ent'cat_scl2 = '0'
and c06s03b00x00p08n01i00995ent'cat_scl3 = 'z'
and c06s03b00x00p08n01i00995ent'cat_scl4 = 0
and c06s03b00x00p08n01i00995ent'cat_scl5 = 10.0
-- and c06s03b00x00p08n01i00995ent'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00995ent'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00995ent'cat_scl8 = FX )
report "***FAILED TEST: c06s03b00x00p08n01i00995 - Expanded name denotes a primary unit contained in design library test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n01i00995arch;
| gpl-2.0 | 37c7b70eabf486f84e616df826166503 | 0.639167 | 2.94874 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd | 4 | 2,082 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_mosfet_noisy is
end tb_mosfet_noisy ;
architecture TB_mosfet_noisy of tb_mosfet_noisy is
-- Component declarations
-- Signal declarations
terminal d : electrical;
terminal g : electrical;
begin
-- Signal assignments
-- Component instances
mosfet1 : entity work.nmos_transistor_wa(noisy)
port map(
gate => g,
drain => d,
source => ELECTRICAL_REF
);
v1 : entity work.v_constant(ideal)
generic map(
level => 4.0
)
port map(
pos => g,
neg => ELECTRICAL_REF
);
mosfet2 : entity work.nmos_transistor_wa(noisy)
port map(
gate => g,
drain => ELECTRICAL_REF,
source => d
);
v4 : entity work.v_pulse(ideal)
generic map(
initial => 0.0,
pulse => 5.0,
ti2p => 1 ms,
tp2i => 1 ms,
delay => 1 us,
width => 1 us,
period => 2.002 ms
)
port map(
pos => d,
neg => ELECTRICAL_REF
);
end TB_mosfet_noisy ;
| gpl-2.0 | f0a5c9528d3acd1614d408a3d31ae46c | 0.600865 | 4.042718 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/sim/vhdl/doHist.autotb.vhd | 1 | 49,190 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity apatb_doHist_top is
generic (
AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns;
AUTOTB_TVIN_inStream_V_data_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_data_V.dat";
AUTOTB_TVIN_inStream_V_keep_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_keep_V.dat";
AUTOTB_TVIN_inStream_V_strb_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_strb_V.dat";
AUTOTB_TVIN_inStream_V_user_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_user_V.dat";
AUTOTB_TVIN_inStream_V_last_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_last_V.dat";
AUTOTB_TVIN_inStream_V_id_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_id_V.dat";
AUTOTB_TVIN_inStream_V_dest_V : STRING := "../tv/cdatafile/c.doHist.autotvin_inStream_V_dest_V.dat";
AUTOTB_TVIN_histo : STRING := "../tv/cdatafile/c.doHist.autotvin_histo.dat";
AUTOTB_TVIN_inStream_V_data_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_data_V.dat";
AUTOTB_TVIN_inStream_V_keep_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_keep_V.dat";
AUTOTB_TVIN_inStream_V_strb_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_strb_V.dat";
AUTOTB_TVIN_inStream_V_user_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_user_V.dat";
AUTOTB_TVIN_inStream_V_last_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_last_V.dat";
AUTOTB_TVIN_inStream_V_id_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_id_V.dat";
AUTOTB_TVIN_inStream_V_dest_V_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_inStream_V_dest_V.dat";
AUTOTB_TVIN_histo_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvin_histo.dat";
AUTOTB_TVOUT_histo : STRING := "../tv/cdatafile/c.doHist.autotvout_histo.dat";
AUTOTB_TVOUT_histo_out_wrapc : STRING := "../tv/rtldatafile/rtl.doHist.autotvout_histo.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "doHist.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "doHist.performance.result.transaction.xml";
LENGTH_inStream_V_data_V : INTEGER := 76800;
LENGTH_inStream_V_keep_V : INTEGER := 76800;
LENGTH_inStream_V_strb_V : INTEGER := 76800;
LENGTH_inStream_V_user_V : INTEGER := 76800;
LENGTH_inStream_V_last_V : INTEGER := 76800;
LENGTH_inStream_V_id_V : INTEGER := 76800;
LENGTH_inStream_V_dest_V : INTEGER := 76800;
LENGTH_histo : INTEGER := 256;
AUTOTB_TRANSACTION_NUM : INTEGER := 1
);
end apatb_doHist_top;
architecture behav of apatb_doHist_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal CTRL_BUS_AWADDR: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CTRL_BUS_AWVALID: STD_LOGIC;
signal CTRL_BUS_AWREADY: STD_LOGIC;
signal CTRL_BUS_WVALID: STD_LOGIC;
signal CTRL_BUS_WREADY: STD_LOGIC;
signal CTRL_BUS_WDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal CTRL_BUS_WSTRB: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CTRL_BUS_ARADDR: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal CTRL_BUS_ARVALID: STD_LOGIC;
signal CTRL_BUS_ARREADY: STD_LOGIC;
signal CTRL_BUS_RVALID: STD_LOGIC;
signal CTRL_BUS_RREADY: STD_LOGIC;
signal CTRL_BUS_RDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal CTRL_BUS_RRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal CTRL_BUS_BVALID: STD_LOGIC;
signal CTRL_BUS_BREADY: STD_LOGIC;
signal CTRL_BUS_BRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal CTRL_BUS_INTERRUPT: STD_LOGIC;
signal ap_clk : STD_LOGIC;
signal ap_rst_n : STD_LOGIC;
signal inStream_TDATA: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal inStream_TVALID: STD_LOGIC;
signal inStream_TREADY: STD_LOGIC;
signal inStream_TKEEP: STD_LOGIC_VECTOR (0 DOWNTO 0);
signal inStream_TSTRB: STD_LOGIC_VECTOR (0 DOWNTO 0);
signal inStream_TUSER: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal inStream_TLAST: STD_LOGIC_VECTOR (0 DOWNTO 0);
signal inStream_TID: STD_LOGIC_VECTOR (4 DOWNTO 0);
signal inStream_TDEST: STD_LOGIC_VECTOR (5 DOWNTO 0);
signal histo_ADDR_A: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal histo_EN_A: STD_LOGIC;
signal histo_WEN_A: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal histo_DIN_A: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal histo_DOUT_A: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal histo_CLK_A: STD_LOGIC;
signal histo_RST_A: STD_LOGIC;
signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
signal reported_stuck : STD_LOGIC := '0';
shared variable reported_stuck_cnt : INTEGER := 0;
component doHist is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TKEEP : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
interrupt : OUT STD_LOGIC);
end component;
signal bramhisto_Clk_A, bramhisto_Clk_B : STD_LOGIC;
signal bramhisto_Rst_A, bramhisto_Rst_B : STD_LOGIC;
signal bramhisto_EN_A, bramhisto_EN_B : STD_LOGIC;
signal bramhisto_WEN_A, bramhisto_WEN_B : STD_LOGIC_VECTOR(4 - 1 downto 0);
signal bramhisto_Addr_A, bramhisto_Addr_B : STD_LOGIC_VECTOR(31 downto 0);
signal bramhisto_Din_A, bramhisto_Din_B : STD_LOGIC_VECTOR(31 downto 0);
signal bramhisto_Dout_A, bramhisto_Dout_B : STD_LOGIC_VECTOR(31 downto 0);
signal bramhisto_ready : STD_LOGIC;
signal bramhisto_done : STD_LOGIC;
component AESL_autobram_histo is
port(
Clk_A : IN STD_LOGIC;
Rst_A : IN STD_LOGIC;
EN_A : IN STD_LOGIC;
WEN_A : IN STD_LOGIC_VECTOR;
Addr_A : IN STD_LOGIC_VECTOR;
Din_A : IN STD_LOGIC_VECTOR;
Dout_A : OUT STD_LOGIC_VECTOR;
Clk_B : IN STD_LOGIC;
Rst_B : IN STD_LOGIC;
EN_B : IN STD_LOGIC;
WEN_B : IN STD_LOGIC_VECTOR;
Addr_B : IN STD_LOGIC_VECTOR;
Din_B : IN STD_LOGIC_VECTOR;
Dout_B : OUT STD_LOGIC_VECTOR;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal inStream_ready : STD_LOGIC := '0';
signal inStream_done : STD_LOGIC := '0';
signal axi_s_inStream_TVALID : STD_LOGIC := '0';
signal axi_s_inStream_TREADY : STD_LOGIC := '0';
signal reg_inStream_TVALID : STD_LOGIC := '0';
signal reg_inStream_TREADY : STD_LOGIC := '0';
signal ap_c_n_tvin_trans_num_inStream_V_data_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_keep_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_strb_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_user_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_last_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_id_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal ap_c_n_tvin_trans_num_inStream_V_dest_V : STD_LOGIC_VECTOR(31 DOWNTO 0) := conv_std_logic_vector(1, 32);
signal inStream_ready_reg : STD_LOGIC := '0';
component AESL_axi_s_inStream is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_inStream_TDATA : OUT STD_LOGIC_VECTOR;
inStream_TDATA_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TKEEP : OUT STD_LOGIC_VECTOR;
inStream_TKEEP_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TSTRB : OUT STD_LOGIC_VECTOR;
inStream_TSTRB_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TUSER : OUT STD_LOGIC_VECTOR;
inStream_TUSER_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TLAST : OUT STD_LOGIC_VECTOR;
inStream_TLAST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TID : OUT STD_LOGIC_VECTOR;
inStream_TID_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TDEST : OUT STD_LOGIC_VECTOR;
inStream_TDEST_trans_num : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TRAN_inStream_TVALID : OUT STD_LOGIC;
TRAN_inStream_TREADY : IN STD_LOGIC;
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end component;
signal AESL_slave_output_done : STD_LOGIC;
signal AESL_slave_start : STD_LOGIC;
signal AESL_slave_write_start_in : STD_LOGIC;
signal AESL_slave_write_start_finish : STD_LOGIC;
signal AESL_slave_ready : STD_LOGIC;
signal slave_start_status : STD_LOGIC := '0';
signal start_rise : STD_LOGIC := '0';
signal ready_rise : STD_LOGIC := '0';
signal slave_done_status : STD_LOGIC := '0';
component AESL_AXI_SLAVE_CTRL_BUS is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_WDATA : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_WSTRB : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_ARADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_RDATA : IN STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_RRESP : IN STD_LOGIC_VECTOR;
TRAN_s_axi_CTRL_BUS_BVALID : IN STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_CTRL_BUS_BRESP : IN STD_LOGIC_VECTOR;
TRAN_CTRL_BUS_interrupt : IN STD_LOGIC;
TRAN_CTRL_BUS_ready_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_ready_in : IN STD_LOGIC;
TRAN_CTRL_BUS_done_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_idle_out : OUT STD_LOGIC;
TRAN_CTRL_BUS_write_start_in : IN STD_LOGIC;
TRAN_CTRL_BUS_write_start_finish : OUT STD_LOGIC;
TRAN_CTRL_BUS_transaction_done_in : IN STD_LOGIC;
TRAN_CTRL_BUS_start_in : IN STD_LOGIC
);
end component;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
begin
AESL_inst_doHist : doHist port map (
s_axi_CTRL_BUS_AWADDR => CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WVALID => CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => CTRL_BUS_WREADY,
s_axi_CTRL_BUS_WDATA => CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_ARADDR => CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RVALID => CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => CTRL_BUS_RREADY,
s_axi_CTRL_BUS_RDATA => CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => CTRL_BUS_RRESP,
s_axi_CTRL_BUS_BVALID => CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => CTRL_BUS_BREADY,
s_axi_CTRL_BUS_BRESP => CTRL_BUS_BRESP,
interrupt => CTRL_BUS_INTERRUPT,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
inStream_TDATA => inStream_TDATA,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
inStream_TDEST => inStream_TDEST,
histo_Addr_A => histo_ADDR_A,
histo_EN_A => histo_EN_A,
histo_WEN_A => histo_WEN_A,
histo_Din_A => histo_DIN_A,
histo_Dout_A => histo_DOUT_A,
histo_Clk_A => histo_CLK_A,
histo_Rst_A => histo_RST_A
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst_n <= AESL_reset;
AESL_reset <= rst;
AESL_start <= start;
AESL_ce <= ce;
AESL_continue <= continue;
AESL_slave_write_start_in <= slave_start_status ;
AESL_slave_start <= AESL_slave_write_start_finish;
AESL_done <= slave_done_status ;
slave_start_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
slave_start_status <= '1';
else
if (AESL_start = '1' ) then
start_rise <= '1';
end if;
if (start_rise = '1' and AESL_done = '1' ) then
slave_start_status <= '1';
end if;
if (AESL_slave_write_start_in = '1') then
slave_start_status <= '0';
start_rise <= '0';
end if;
end if;
end if;
end process;
slave_ready_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_slave_ready <= '0';
ready_rise <= '0';
else
if (AESL_ready = '1' ) then
ready_rise <= '1';
end if;
if (ready_rise = '1' and AESL_done_delay = '1' ) then
AESL_slave_ready <= '1';
end if;
if (AESL_slave_ready = '1') then
AESL_slave_ready <= '0';
ready_rise <= '0';
end if;
end if;
end if;
end process;
slave_done_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if (AESL_done = '1') then
slave_done_status <= '0';
elsif (AESL_slave_output_done = '1' ) then
slave_done_status <= '1';
end if;
end if;
end process;
AESL_inst_histo : AESL_autobram_histo port map (
Clk_A => bramhisto_Clk_A,
Rst_A => bramhisto_Rst_A,
EN_A => bramhisto_EN_A,
WEN_A => bramhisto_WEN_A,
Addr_A => bramhisto_Addr_A,
Din_A => bramhisto_Din_A,
Dout_A => bramhisto_Dout_A,
Clk_B => bramhisto_Clk_B,
Rst_B => bramhisto_Rst_B,
EN_B => bramhisto_EN_B,
WEN_B => bramhisto_WEN_B,
Addr_B => bramhisto_Addr_B,
Din_B => bramhisto_Din_B,
Dout_B => bramhisto_Dout_B,
ready => bramhisto_ready,
done => bramhisto_done
);
-- Assignment between dut and bramhisto
bramhisto_Clk_A <= histo_CLK_A;
bramhisto_Rst_A <= histo_RST_A;
bramhisto_Addr_A <= histo_ADDR_A;
bramhisto_EN_A <= histo_EN_A;
histo_DOUT_A <= bramhisto_Dout_A;
bramhisto_WEN_A <= histo_WEN_A;
bramhisto_Din_A <= histo_DIN_A;
bramhisto_WEN_B <= (others => '0');
bramhisto_Din_B <= (others => '0');
bramhisto_ready <= ready;
bramhisto_done <= interface_done;
AESL_axi_s_inst_inStream : AESL_axi_s_inStream port map (
clk => AESL_clock,
reset => AESL_reset,
TRAN_inStream_TDATA => inStream_TDATA,
inStream_TDATA_trans_num => ap_c_n_tvin_trans_num_inStream_V_data_V,
TRAN_inStream_TKEEP => inStream_TKEEP,
inStream_TKEEP_trans_num => ap_c_n_tvin_trans_num_inStream_V_keep_V,
TRAN_inStream_TSTRB => inStream_TSTRB,
inStream_TSTRB_trans_num => ap_c_n_tvin_trans_num_inStream_V_strb_V,
TRAN_inStream_TUSER => inStream_TUSER,
inStream_TUSER_trans_num => ap_c_n_tvin_trans_num_inStream_V_user_V,
TRAN_inStream_TLAST => inStream_TLAST,
inStream_TLAST_trans_num => ap_c_n_tvin_trans_num_inStream_V_last_V,
TRAN_inStream_TID => inStream_TID,
inStream_TID_trans_num => ap_c_n_tvin_trans_num_inStream_V_id_V,
TRAN_inStream_TDEST => inStream_TDEST,
inStream_TDEST_trans_num => ap_c_n_tvin_trans_num_inStream_V_dest_V,
TRAN_inStream_TVALID => axi_s_inStream_TVALID,
TRAN_inStream_TREADY => axi_s_inStream_TREADY,
ready => inStream_ready,
done => inStream_done
);
inStream_ready <= inStream_ready_reg or ready_initial;
inStream_done <= '0';
gen_reg_inStream_TVALID_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
reg_inStream_TVALID <= axi_s_inStream_TVALID;
while(true) loop
wait until axi_s_inStream_TVALID'event;
if(axi_s_inStream_TVALID = '1') then
end if;
reg_inStream_TVALID <= axi_s_inStream_TVALID;
end loop;
end process;
inStream_TVALID <= reg_inStream_TVALID;
axi_s_inStream_TREADY <= inStream_TREADY;
AESL_axi_slave_inst_CTRL_BUS : AESL_AXI_SLAVE_CTRL_BUS port map (
clk => AESL_clock,
reset => AESL_reset,
TRAN_s_axi_CTRL_BUS_AWADDR => CTRL_BUS_AWADDR,
TRAN_s_axi_CTRL_BUS_AWVALID => CTRL_BUS_AWVALID,
TRAN_s_axi_CTRL_BUS_AWREADY => CTRL_BUS_AWREADY,
TRAN_s_axi_CTRL_BUS_WVALID => CTRL_BUS_WVALID,
TRAN_s_axi_CTRL_BUS_WREADY => CTRL_BUS_WREADY,
TRAN_s_axi_CTRL_BUS_WDATA => CTRL_BUS_WDATA,
TRAN_s_axi_CTRL_BUS_WSTRB => CTRL_BUS_WSTRB,
TRAN_s_axi_CTRL_BUS_ARADDR => CTRL_BUS_ARADDR,
TRAN_s_axi_CTRL_BUS_ARVALID => CTRL_BUS_ARVALID,
TRAN_s_axi_CTRL_BUS_ARREADY => CTRL_BUS_ARREADY,
TRAN_s_axi_CTRL_BUS_RVALID => CTRL_BUS_RVALID,
TRAN_s_axi_CTRL_BUS_RREADY => CTRL_BUS_RREADY,
TRAN_s_axi_CTRL_BUS_RDATA => CTRL_BUS_RDATA,
TRAN_s_axi_CTRL_BUS_RRESP => CTRL_BUS_RRESP,
TRAN_s_axi_CTRL_BUS_BVALID => CTRL_BUS_BVALID,
TRAN_s_axi_CTRL_BUS_BREADY => CTRL_BUS_BREADY,
TRAN_s_axi_CTRL_BUS_BRESP => CTRL_BUS_BRESP,
TRAN_CTRL_BUS_interrupt => CTRL_BUS_INTERRUPT,
TRAN_CTRL_BUS_ready_out => AESL_ready,
TRAN_CTRL_BUS_ready_in => AESL_slave_ready,
TRAN_CTRL_BUS_done_out => AESL_slave_output_done,
TRAN_CTRL_BUS_idle_out => AESL_idle,
TRAN_CTRL_BUS_write_start_in => AESL_slave_write_start_in,
TRAN_CTRL_BUS_write_start_finish => AESL_slave_write_start_finish,
TRAN_CTRL_BUS_transaction_done_in => AESL_done_delay,
TRAN_CTRL_BUS_start_in => AESL_slave_start
);
generate_ready_cnt_proc : process(ready_initial, AESL_clock)
begin
if(AESL_clock'event and AESL_clock = '0') then
if(ready_initial = '1') then
ready_cnt <= conv_std_logic_vector(1, 32);
end if;
elsif(AESL_clock'event and AESL_clock = '1') then
if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_ready = '1') then
ready_cnt <= ready_cnt + 1;
end if;
end if;
end if;
end process;
generate_done_cnt_proc : process(AESL_reset, AESL_clock)
begin
if(AESL_reset = '0') then
done_cnt <= (others => '0');
elsif(AESL_clock'event and AESL_clock = '1') then
if(done_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_done = '1') then
done_cnt <= done_cnt + 1;
end if;
end if;
end if;
end process;
generate_sim_done_proc : process
begin
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for AUTOTB_CLOCK_PERIOD_DIV2;
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '0';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '1';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '1';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1';
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_ready_delay;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
proc_gen_inStream_internal_ready : process
variable internal_trans_num : INTEGER;
begin
wait until AESL_reset = '1';
wait until ready_initial = '1';
inStream_ready_reg <= '0';
wait until AESL_clock'event and AESL_clock = '1';
internal_trans_num := 1;
while(internal_trans_num /= AUTOTB_TRANSACTION_NUM + 1) loop
if (true
and ap_c_n_tvin_trans_num_inStream_V_data_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_keep_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_strb_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_user_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_last_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_id_V > internal_trans_num
and ap_c_n_tvin_trans_num_inStream_V_dest_V > internal_trans_num
) then
inStream_ready_reg <= '1';
wait until AESL_clock'event and AESL_clock = '1';
inStream_ready_reg <= '0';
internal_trans_num := internal_trans_num + 1;
else
wait until AESL_clock'event and AESL_clock = '1';
end if;
end loop;
inStream_ready_reg <= '0';
wait;
end process;
-- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor
write_output_transactor_histo_runtime_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
begin
file_open(fstatus, fp, AUTOTB_TVOUT_histo_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_histo_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
file_close(fp);
while done_cnt /= AUTOTB_TRANSACTION_NUM loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus, fp, AUTOTB_TVOUT_histo_out_wrapc, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_histo_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '0') then
if(AESL_reset = '0') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
reported_stuck_cnt := 0;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
reported_stuck <= '0';
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_slave_write_start_finish = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '1');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i);
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
lattotal := lattotal + latthistime;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrthistime := latthistime;
else
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
end if;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
thrtotal := thrtotal + thrthistime;
end loop;
lataver := lattotal / AUTOTB_TRANSACTION_NUM;
thraver := thrtotal / AUTOTB_TRANSACTION_NUM;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrmax := 0;
thrmin := 0;
thraver := 0;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
else
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
end if;
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
if (AUTOTB_TRANSACTION_NUM = 1) then
i := 0;
thr_array(i) := 0;
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
else
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
end if;
file_close(fp);
wait;
end process;
end behav;
| gpl-3.0 | da6fcc59881eae6821d37bc394c5a95b | 0.55247 | 3.39663 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug084/func_test2.vhdl | 1 | 1,721 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity func_test2 is
generic (NBITS: natural := 6);
end entity;
architecture fum of func_test2 is
signal dividend: std_logic_vector (NBITS - 1 downto 0);
function mod5 (dividend: std_logic_vector) return std_logic is
type remains is (r0, r1, r2, r3, r4); -- remainder values
type remain_array is array (NBITS downto 0) of remains;
type branch is array (remains, bit) of remains;
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
variable remaind: remain_array := (others => r0);
variable tbit: bit_vector (NBITS - 1 downto 0);
begin
tbit := to_bitvector(dividend); -- little endian
for i in dividend'length - 1 downto 0 loop
remaind(i) := br_table(remaind(i + 1),tbit(i));
end loop;
if remaind(0) = r0 then
return '1';
else
return '0';
end if;
end function;
begin
process
variable errors: natural;
begin
errors := 0;
for i in 0 to 2 ** NBITS - 1 loop
dividend <= std_logic_vector(to_unsigned(i, NBITS));
wait for 0 ns;
report "mod5(" & integer'image(i) &") = " &
std_ulogic'image(mod5(dividend));
end loop;
wait;
end process;
end architecture;
| gpl-2.0 | 2890cb2c0b80118e874cb7b3f5c56120 | 0.476467 | 3.782418 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue718/bug_repro.vhdl | 1 | 1,768 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use std.textio.all;
package rom is
generic (
word_bits: positive;
address_bits: positive;
rom_filename: string
);
subtype word_type is std_logic_vector(word_bits-1 downto 0);
impure function read_at(address: in integer range 0 to 2**address_bits-1) return word_type;
end package rom;
package body rom is
impure function read_at(
address: in integer range 0 to 2**address_bits-1
) return word_type is
type rom_type is array(0 to 2**address_bits-1) of word_type;
impure function init_rom_from_file (filename: in string) return rom_type is
file rom_file: text;
variable file_line : line;
variable rom_array: rom_type;
begin
file_open(rom_file, filename, read_mode);
for i in rom_type'range loop
readline(rom_file, file_line);
read(file_line, rom_array(i));
end loop;
file_close(rom_file);
return rom_array;
end function;
constant rom_array: rom_type := init_rom_from_file(rom_filename);
begin
return rom_array(address);
end function read_at;
end package body rom;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use std.textio.all;
entity test is
end test;
architecture dataflow of test is
package p is new work.rom generic map(
word_bits => 2,
address_bits => 2,
rom_filename => "rom.txt"
);
signal word: std_logic_vector(1 downto 0);
begin
process (all)
begin
word <= p.read_at(0);
end process;
end dataflow;
| gpl-2.0 | 4d369e433f2790dd806cb3ef4e59a15f | 0.624434 | 3.578947 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd | 4 | 1,913 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc392.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p06n01i00392ent IS
END c03s02b01x01p06n01i00392ent;
ARCHITECTURE c03s02b01x01p06n01i00392arch OF c03s02b01x01p06n01i00392ent IS
type M1 is array (positive range <>) of integer;
signal S1 : M1(3 to 30) ; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
S1(3) <= 3 after 3 ns;
S1(30) <= 30 after 3 ns;
wait for 10 ns;
assert NOT(S1(3)=3 and S1(30)=30)
report "***PASSED TEST: c03s02b01x01p06n01i00392"
severity NOTE;
assert (S1(3)=3 and S1(30)=30)
report "***FAILED TEST: c03s02b01x01p06n01i00392 - Subtype indication of array object declaration must denote a constrained array."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p06n01i00392arch;
| gpl-2.0 | 6976b5f6d612a1a645dc1f2da22eec8d | 0.666492 | 3.52302 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/output_split2.vhd | 2 | 1,410 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split2;
architecture augh of output_split2 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 5c5c87507c88ee951365d85bd1ab4220 | 0.673759 | 2.895277 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd | 4 | 1,484 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity moving_mass is
port ( terminal external_attachment : translational );
end entity moving_mass;
----------------------------------------------------------------
architecture behavioral of moving_mass is
constant mass : real := 10.0;
constant stiffness : real := 2.0;
constant damping : real := 5.0;
quantity position across driving_force through external_attachment;
quantity velocity : real;
begin
position == velocity'integ;
mass * velocity'dot == driving_force - stiffness * velocity'integ - damping * velocity
tolerance velocity'tolerance;
end architecture behavioral;
| gpl-2.0 | e42ad0552d71fb60b46136b680de5f0d | 0.703504 | 4.443114 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue810/my_time_pkg.vhdl | 1 | 257 | package my_time_pkg is
type my_time is range -integer'low to integer'high units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
end package my_time_pkg;
| gpl-2.0 | 9b64e04ffeb9021db77715d68ee99736 | 0.575875 | 3.059524 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd | 4 | 2,100 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_07a is
end entity inline_07a;
----------------------------------------------------------------
library ieee_proposed; use ieee_proposed.thermal_systems.all;
architecture test of inline_07a is
-- code from book:
type A is array (1 to 4, 31 downto 0) of boolean;
nature B is array (1 to 10, 19 downto 0) of thermal;
-- end of code from book
begin
process_1_i : process is
variable free_map : bit_vector(1 to 10) := "0011010110";
variable count : natural;
begin
-- code from book (just the conditions):
assert A'low(1) = 1; assert B'left(1) = 1;
assert A'high(2) = 31; assert B'right(2) = 0;
-- assert A'reverse_range(2) is 0 to 31; assert B'range(1) is 1 to 10;
assert A'length(2) = 32; assert B'length(1) = 10;
assert A'ascending(2) = false; assert B'ascending(1) = true;
assert A'low = 1; assert A'length = 4;
assert B'high = 10; assert B'length = 10;
--
count := 0;
for index in free_map'range loop
if free_map(index) = '1' then
count := count + 1;
end if;
end loop;
-- end of code from book
wait;
end process process_1_i;
end architecture test;
| gpl-2.0 | 4b8bdf139fbaa93472d5dacd27e554eb | 0.610952 | 3.818182 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffsize.vhd | 2 | 1,519 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_dc_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_dc_huffsize;
architecture augh of huff_make_dhuff_tb_dc_huffsize is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
| gpl-2.0 | 4773bd6680b3917dedf9bb9aaa7241dd | 0.676103 | 2.893333 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue256/testcase2_testbench.vhd | 2 | 704 | entity testcase2_testbench is
end entity testcase2_testbench;
architecture bench of testcase2_testbench is
signal clk: bit;
begin
dut: entity work.testcase2(empty) port map(clk => clk);
stimulus: process is
begin
-- Valid low and high pulses
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
-- Confirm that we're timing events, not transactions
clk <= '1';
wait for 5 ns;
-- Now send a short pulse to make the assertion fire
clk <= '0';
wait for 5 ns;
-- Assertion should fire here, at 30ns
clk <= '1';
wait;
end process stimulus;
end architecture bench;
| gpl-2.0 | 9a27fd0bfd95d112c6470894b0931bde | 0.578125 | 4.266667 | false | true | false | false |
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